├── AVR8.idx ├── LICENSE ├── README.md ├── atmega328.pspec ├── avr8.ldefs ├── avr8.sinc ├── avr8egcc.cspec ├── avr8gcc.cspec └── avr_instruction_helper.py /AVR8.idx: -------------------------------------------------------------------------------- 1 | @atmel-0856-avr-instruction-set-manual.pdf[Atmel AVR Instruction Set Manual, November, 2016 (0856L)] 2 | ADC, 30 3 | ADD, 32 4 | ADDIW, 33 5 | AND, 35 6 | ANDI, 36 7 | ASR, 37 8 | BCLR, 38 9 | BLD, 39 10 | BRBC, 40 11 | BRBS, 41 12 | BRCC, 42 13 | BRCS, 43 14 | BREAK, 44 15 | BREQ, 45 16 | BRGE, 46 17 | BRHC, 47 18 | BRHS, 48 19 | BRID, 49 20 | BRIE, 50 21 | BRLO, 51 22 | BRLT, 52 23 | BRMI, 53 24 | BRNE, 54 25 | BRPL, 55 26 | BRSH, 56 27 | BRTC, 57 28 | BRTS, 58 29 | BRVC, 59 30 | BRVS, 60 31 | BSET, 61 32 | BST, 62 33 | CALL, 63 34 | CBI, 65 35 | CBR, 66 36 | CLC, 67 37 | CLH, 68 38 | CLI, 69 39 | CLN, 70 40 | CLR, 71 41 | CLS, 72 42 | CLT, 73 43 | CLV, 74 44 | CLZ, 75 45 | COM, 76 46 | CP, 77 47 | CPC, 79 48 | CPI, 81 49 | CPSE, 83 50 | DEC, 84 51 | DES, 86 52 | EICALL, 87 53 | EIJMP, 88 54 | ELPM, 89 55 | EOR, 91 56 | FMUL, 92 57 | FMULS, 94 58 | FMULSU, 96 59 | ICALL, 98 60 | IJMP, 99 61 | IN, 100 62 | INC, 101 63 | JMP, 103 64 | LAC, 104 65 | LAS, 105 66 | LAT, 106 67 | LD, 107 68 | LDD, 109 69 | LDI, 115 70 | LDS, 116 71 | LPM, 118 72 | LSL, 120 73 | LSR, 122 74 | MOV, 123 75 | MOVW, 124 76 | MUL, 125 77 | MULS, 126 78 | MULSU, 127 79 | NEG, 129 80 | NOP, 131 81 | OR, 132 82 | ORI, 133 83 | OUT, 134 84 | POP, 135 85 | PUSH, 136 86 | RCALL, 137 87 | RET, 139 88 | RETI, 140 89 | RJMP, 142 90 | ROL, 143 91 | ROR, 145 92 | SBC, 147 93 | SBCI, 149 94 | SBI, 151 95 | SBIC, 152 96 | SBIS, 153 97 | SBIW, 154 98 | SBR, 156 99 | SBRC, 157 100 | SBRS, 158 101 | SEC, 159 102 | SEH, 160 103 | SEI, 161 104 | SEN, 162 105 | SER, 163 106 | SES, 164 107 | SET, 165 108 | SEV, 166 109 | SEZ, 167 110 | SLEEP, 168 111 | SPM, 169 112 | ST, 173 113 | STD, 175 114 | STS, 179 115 | SUB, 181 116 | SUBI, 183 117 | SWAP, 185 118 | TST, 186 119 | WDR, 187 120 | XCH, 188 121 | 122 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Atmel AVR helpers for Ghidra 2 | ============================ 3 | 4 | Contents include: 5 | * Processor definitions for ATmega328p processor 6 | * Manual index for Atmel AVR Instruction Set Manual 7 | * Ghidra script to place short instruction descriptions as EOL comments over 8 | selected program region 9 | * Modifications to AVR8 SLEIGH specification and gcc compiler specs 10 | 11 | Will attempt to push processor definitions and manual index upstream when 12 | source code is released. 13 | 14 | -------------------------------------------------------------------------------- /atmega328.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | -------------------------------------------------------------------------------- /avr8.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 14 | AVR8 with 16-bit word addressable code space 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 31 | AVR8 with 22-bit word addressable code space 32 | 33 | 34 | 35 | 36 | 37 | 46 | AVR8 for an Atmega 256 47 | 48 | 49 | 50 | 51 | 60 | AVR8 for an Atmega 328 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | -------------------------------------------------------------------------------- /avr8.sinc: -------------------------------------------------------------------------------- 1 | # sleigh specification for the avr8 2 | # 3 | # Currently designed for ATMega64 in non-ATmel103 configuration 4 | # - 0x20-0xff as IO memory, rather than 0x20-0x5f 5 | # 6 | # This is a ATMega64 with a 64k sized memory 7 | # Other parts avaible have a 4M sized memory so that stack 8 | # pointer would be three bytes instead 9 | 10 | define endian=little; 11 | # Declaring space to be wordsized... alternative is to do byte sized 12 | define alignment=2; 13 | 14 | # Force fusion of two byte operations in a row by decoding as words 15 | #@define FUSION "" 16 | 17 | # mem space should really be the default, but the loading scripts will 18 | # prefer the code space as the default. By being explicit for every 19 | # instruction, we can eliminate the ambiguity for at least the 20 | # decompiler. None-the-less, other than when loading the binary into 21 | # Ghidra, it's still preferable to see the name of IO locations used, 22 | # rather than code addresses, so leave mem space as the default. 23 | 24 | define space code type=ram_space size=3 wordsize=2 default; 25 | define space register type=ram_space size=1; 26 | define space mem type=ram_space size=2 wordsize=1; 27 | 28 | # Using decimal rather than hex to match specs 29 | # TODO: These general purpose registers should reside with the 'mem' space from 0x00-0x1f 30 | #define register offset=0 size=1 [ 31 | define mem offset=0 size=1 [ 32 | R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 33 | R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 34 | R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi 35 | Zlo Zhi 36 | ]; 37 | 38 | #define register offset=0 size=2 [ 39 | define mem offset=0 size=2 [ 40 | R1R0 R3R2 R5R4 R7R6 R9R8 41 | R11R10 R13R12 R15R14 R17R16 R19R18 42 | R21R20 R23R22 R25R24 43 | X Y Z 44 | ]; 45 | 46 | #define register offset=0x10 size=4 [ 47 | define mem offset=0x10 size=4 [ 48 | R19R18R17R16 R23R22R21R20 49 | ]; 50 | 51 | # Techinically, the stack pointer is in the i/o space so should be addressable with the 52 | # rest of the i/o registers. However, Ghidra does not react well to the stack pointer 53 | # being indirectly addressable so we're making an exception. 54 | define register offset=0x3D size=1 [ SPL SPH ]; 55 | define register offset=0x3D size=2 [ SP ]; 56 | 57 | define register offset=0x42 size=$(PCBYTESIZE) [ PC ]; 58 | 59 | define register offset=0x80 size=1 [ 60 | Cflg Zflg Nflg Vflg Sflg Hflg Tflg Iflg SKIP 61 | ]; 62 | 63 | ##################################### 64 | 65 | # I discovered different parts have different io layouts not just different io 66 | define mem offset=0x5B size=1 [ RAMPZ ]; 67 | define mem offset=0x5F size=1 [ SREG ]; 68 | 69 | @if HASEIND == "1" 70 | define mem offset=0x5C size=1 [ EIND ]; 71 | @endif 72 | 73 | ############################## 74 | 75 | # Define context bits 76 | define register offset=0x90 size=4 contextreg; 77 | 78 | define context contextreg 79 | useSkipCond=(0,0) noflow # =1 skip instruction if SKIP register is true 80 | 81 | # transient context 82 | phase=(1,1) # =0 check for useSkipCond, =1 parse instruction 83 | ; 84 | 85 | ## Following 8051 example rather than define bitrange 86 | # Works better as distinct variables 87 | @define Cflag "Cflg" 88 | @define Zflag "Zflg" 89 | @define Nflag "Nflg" 90 | @define Vflag "Vflg" 91 | @define Sflag "Sflg" 92 | @define Hflag "Hflg" 93 | @define Tflag "Tflg" 94 | @define Iflag "Iflg" 95 | 96 | 97 | define token opword (16) 98 | ophi16 = ( 0,15) 99 | ophi9 = ( 7,15) 100 | ophi8 = ( 8,15) 101 | ophi7 = ( 9,15) 102 | ophi6 = (10,15) 103 | ophi5 = (11,15) 104 | ophi4 = (12,15) 105 | ophi2 = (14,15) 106 | opbit13 = (13,13) 107 | opbit12 = (12,12) 108 | opbit9 = ( 9, 9) 109 | opbit8 = ( 8, 8) 110 | opbit7 = ( 7, 7) 111 | opbit3 = ( 3, 3) 112 | opbit2 = ( 2, 2) 113 | opbit0 = ( 0, 0) 114 | oplow12 = ( 0,11) 115 | oplow12signed = ( 0,11) signed 116 | oplow4 = ( 0, 3) 117 | oplow3_cc_set = ( 0, 2) 118 | oplow3_cc_clr = ( 0, 2) 119 | oplow3_flag = ( 0, 2) 120 | oplow3 = ( 0, 2) 121 | oplow2 = ( 0, 1) 122 | op1to3 = ( 1, 3) 123 | op2to3 = ( 2, 3) 124 | op3to7 = ( 3, 7) 125 | op4to8 = ( 4, 8) 126 | op4to6 = ( 4, 6) 127 | op4to6_flag = ( 4, 6) 128 | op6to7 = ( 6, 7) 129 | op9to10 = ( 9,10) 130 | op10to11 = (10,11) 131 | RdHi = ( 4, 7) 132 | RdHi3 = ( 4, 6) 133 | RdFull = ( 4, 8) 134 | RrHi = ( 0, 3) 135 | RrHi3 = ( 0, 2) 136 | RrLow = ( 0, 3) 137 | RrHiLowSel = ( 9, 9) 138 | Rdw2 = ( 4, 5) 139 | Rdw4 = ( 4, 7) 140 | Rrw4 = ( 0, 3) 141 | Rstq = ( 3, 3) 142 | RstPtr = ( 2, 3) 143 | op0to3 = ( 0, 3) 144 | op3to9signed = ( 3, 9) signed 145 | op4to7 = ( 4, 7) 146 | op8to11 = ( 8,11) 147 | ; 148 | define token immtok(16) 149 | next16 = (0,15) 150 | ; 151 | 152 | define token opfusion16(32) 153 | op1hi4 = (12,15) 154 | op2hi4 = (28,31) 155 | op1hi6 = (10,15) 156 | op2hi6 = (26,31) 157 | op1low4 = ( 0, 3) 158 | op2low4 = (16,19) 159 | op1bits0to3 = ( 0, 3) 160 | op2bits0to3 = (16,19) 161 | op1bits1to3 = ( 1, 3) 162 | op2bits1to3 = (17,19) 163 | op1bits4to8 = ( 4, 8) 164 | op2bits4to8 = (20,24) 165 | op1bits5to7 = ( 5, 7) 166 | op2bits5to7 = (21,23) 167 | op1bits5to8 = ( 5, 8) 168 | op2bits5to8 = (21,24) 169 | op1bits8to11 = ( 8,11) 170 | op2bits8to11 = (24,27) 171 | op1bit0 = ( 0, 0) 172 | op2bit0 = (16,16) 173 | op1bit4 = ( 4, 4) 174 | op2bit4 = (20,20) 175 | op1bit9 = ( 9, 9) 176 | op2bit9 = (25,25) 177 | op1RdPair = ( 5, 8) 178 | op1RdPairHi = ( 5, 7) 179 | op1RrPairLow = ( 1, 3) 180 | op1RrPairHi = ( 1, 3) 181 | op1RrPairSel = ( 9, 9) 182 | ; 183 | 184 | define token opfusion24(48) 185 | f3op1hi4 = (12,15) 186 | f3op2hi4 = (28,31) 187 | f3op3hi4 = (34,47) 188 | f3op1hi6 = (10,15) 189 | f3op2hi6 = (26,31) 190 | f3op3hi6 = (42,47) 191 | f3op1bits0to3 = ( 0, 3) 192 | f3op2bits0to3 = (16,19) 193 | f3op3bits0to3 = (32,35) 194 | f3op2bits4to7 = (20,23) 195 | f3op1bits5to7 = ( 5, 7) 196 | f3op3bits5to7 = (37,39) 197 | f3op1bits8to11 = ( 8,11) 198 | f3op2bits8to11 = (24,27) 199 | f3op1bit4 = ( 4, 4) 200 | f3op3bit4 = (36,36) 201 | f3op3bit8 = (40,40) 202 | f3op3bit9 = (41,41) 203 | f3op1RdPairHi = ( 5, 7) 204 | f3op2RdHi = (20,23) 205 | ; 206 | 207 | define token opfusionLdsw(64) # lds lds 208 | ldswop1hi7 = ( 9,15) 209 | ldswop2hi7 = (41,47) 210 | ldswop1low4 = ( 0, 3) 211 | ldswop2low4 = (32,35) 212 | ldswop1bits5to8 = ( 5, 8) 213 | ldswop2bits5to8 = (37,40) 214 | ldswop1bit4 = ( 4, 4) 215 | ldswop2bit4 = (36,36) 216 | ldswop1bit16 = (16,16) 217 | ldswop2bit16 = (48,48) 218 | ldswop1imm15 = (17,31) 219 | ldswop2imm15 = (49,63) 220 | ldswop1imm6 = (17,22) 221 | ldswop2imm6 = (49,54) 222 | ldswop1imm16 = (16,31) 223 | ldswop2imm16 = (48,63) 224 | ldswop1RdPair = ( 5, 8) 225 | stswop2RdPair = (37,40) 226 | ; 227 | 228 | attach variables [ oplow3_flag op4to6_flag ] [ 229 | Cflg Zflg Nflg Vflg Sflg Hflg Tflg Iflg 230 | ]; 231 | 232 | attach names [ oplow3_cc_set ] [ 233 | cs eq mi vs lt hs ts ie 234 | ]; 235 | 236 | attach names [ oplow3_cc_clr ] [ 237 | cc ne pl vc ge hc tc id 238 | ]; 239 | 240 | attach variables [ RdHi RrHi f3op2RdHi ] [ 241 | R16 R17 R18 R19 242 | R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi 243 | Zlo Zhi ] 244 | ; 245 | attach variables [ RdHi3 RrHi3 ] [ 246 | R16 R17 R18 R19 247 | R20 R21 R22 R23 248 | ]; 249 | attach variables [ RrLow ] [ 250 | R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 251 | R10 R11 R12 R13 R14 R15 252 | ]; 253 | attach variables [ RdFull ] [ 254 | R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 255 | R10 R11 R12 R13 R14 R15 256 | R16 R17 R18 R19 257 | R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi 258 | Zlo Zhi 259 | ]; 260 | attach variables [ Rdw2 ] [ 261 | R25R24 X Y Z 262 | ]; 263 | attach variables [ Rstq ] [ 264 | Z Y 265 | ]; 266 | attach variables [ RstPtr ] [ 267 | Z _ Y X 268 | ]; 269 | attach variables [ Rdw4 Rrw4 op1RdPair ldswop1RdPair stswop2RdPair ] [ 270 | R1R0 R3R2 R5R4 R7R6 R9R8 271 | R11R10 R13R12 R15R14 R17R16 R19R18 272 | R21R20 R23R22 R25R24 273 | X Y Z 274 | ]; 275 | attach variables [ op1RrPairLow ] [ 276 | R1R0 R3R2 R5R4 R7R6 R9R8 277 | R11R10 R13R12 R15R14 278 | ]; 279 | attach variables [ op1RrPairHi op1RdPairHi f3op1RdPairHi ] [ 280 | R17R16 R19R18 281 | R21R20 R23R22 R25R24 282 | X Y Z 283 | ]; 284 | 285 | 286 | RrFull: RrHi is RrHiLowSel=1 & RrHi { tmp:1 = RrHi; export tmp; } 287 | RrFull: RrLow is RrHiLowSel=0 & RrLow { tmp:1 = RrLow; export tmp; } 288 | 289 | # Alternative: try using some subcontructors 290 | op1RrPair: op1RrPairHi is op1RrPairSel=1 & op1RrPairHi { tmp:2 = op1RrPairHi; export tmp; } 291 | op1RrPair: op1RrPairLow is op1RrPairSel=0 & op1RrPairLow { tmp:2 = op1RrPairLow; export tmp; } 292 | 293 | 294 | # I'm uneasy at these... as they require the top of the stack 295 | # to know what size element to reserve before the push. 296 | # The docs should probably say that the top of the stack byte is unused... 297 | macro pushPC(val) { 298 | SP = SP - $(PCBYTESIZE); 299 | *[mem]:$(PCBYTESIZE) SP = val; 300 | } 301 | macro popPC(val) { 302 | val = *[mem]:$(PCBYTESIZE) SP; 303 | SP = SP + $(PCBYTESIZE); 304 | } 305 | macro push8(val) { 306 | SP = SP -1; 307 | *[mem]:1 SP = val; 308 | } 309 | macro pop8(val) { 310 | val = *[mem]:1 SP; 311 | SP = SP + 1; 312 | } 313 | # .slaspec shortcoming: Hflag isn't computed for most results 314 | macro setSflag() { 315 | $(Sflag) = $(Nflag) ^ $(Vflag); 316 | } 317 | macro setResultFlags(result){ 318 | $(Nflag) = (result & 0x80) == 0x80; 319 | $(Zflag) = (result == 0x0); 320 | setSflag(); 321 | } 322 | macro setResult16Flags(result) { 323 | $(Nflag) = (result & 0x8000) == 0x8000; 324 | $(Zflag) = (result == 0x0); 325 | setSflag(); 326 | } 327 | macro setSubCarry(pre,sub){ # pre - sub 328 | $(Cflag) = (pre < sub); 329 | } 330 | # The decompilation looks better when the pcode comparision is used, 331 | # rather than walking though the bit examples in the manual. 332 | # todo: consolidate these 333 | macro setVflagForSub(pre,sub,res){ # res = pre - sub 334 | $(Vflag) = scarry(pre,sub); 335 | } 336 | macro setVflagForSub16(pre,sub){ # pre - sub 337 | $(Vflag) = scarry(pre,sub); 338 | } 339 | macro setVflagForAdd(arg1,arg2,res){ 340 | local a = (res & 0x80) >> 7; 341 | local b = (arg1 & 0x80) >> 7; 342 | local c = (arg2 & 0x80) >> 7; 343 | local V = (b & c & (~a)) ^ ((~b) & (~c) & a); 344 | $(Vflag) = V & 0x01; 345 | } 346 | macro setCflagForAdd(arg1,arg2,res){ 347 | # pcode has a two form version... but not one taking carry in 348 | $(Cflag) = carry(arg1,arg2); 349 | } 350 | macro doSubtract(pre,sub,res){ 351 | local x = pre - sub; 352 | setVflagForSub(pre,sub,x); 353 | res = x; 354 | setSubCarry(pre, sub); 355 | setResultFlags(res); 356 | $(Sflag) = pre s< sub; 357 | } 358 | macro doSubtractWithCarry(pre,subNoCarry,res){ 359 | local sub = subNoCarry + $(Cflag); 360 | local oldZflag = $(Zflag); 361 | doSubtract(pre,sub,res); 362 | $(Zflag) = oldZflag & $(Zflag); 363 | $(Sflag) = pre s< sub; 364 | } 365 | macro setMulFlags(res) { 366 | $(Cflag) = ((res & 0x8000) != 0); 367 | $(Zflag) = (res == 0); 368 | } 369 | 370 | # Handle possible skip instruction 371 | # This next line is a NOP except for the phase, which is never really checked. 372 | # A better fix may be to use -l, and ensure phase=1 is checked on the base constructors. 373 | :^instruction is phase=0 & useSkipCond=0 & instruction [ phase=1; ] { build instruction; } 374 | :^instruction is phase=0 & useSkipCond=1 & instruction [ phase=1; ] { 375 | if (SKIP) goto inst_next; 376 | build instruction; 377 | } 378 | 379 | # K8 is immediate for Rd,K8 forms 380 | K8: val is op0to3 & op8to11 [ val = (op8to11 << 4) | op0to3; ] { tmp:1 = val; export tmp; } 381 | 382 | @ifdef FUSION 383 | K16fuse: val is op1bits0to3 & op1bits8to11 & op2bits0to3 & op2bits8to11 [ val = (((op2bits8to11 << 4) | op2bits0to3) << 8) | ((op1bits8to11 << 4) | op1bits0to3); ] { tmp:2 = val; export tmp; } 384 | f3cmpK16: val is f3op1bits0to3 & f3op1bits8to11 & f3op2bits0to3 & f3op2bits8to11 [ val = (((f3op2bits8to11 << 4) | f3op2bits0to3) << 8) | ((f3op1bits8to11 << 4) | f3op1bits0to3); ] { tmp:2 = val; export tmp; } 385 | f3cmpK8: val is f3op2bits0to3 & f3op2bits8to11 [ val = (f3op2bits8to11 << 4) | f3op2bits0to3; ] { tmp:1 = val; export tmp; } 386 | @endif 387 | 388 | rel7addr: rel is op3to9signed [ rel = (op3to9signed + inst_next);] { 389 | export *[code]:2 rel; 390 | } 391 | rel7dst: byteOffset is op3to9signed & rel7addr [ byteOffset = (op3to9signed + inst_next) << 1;] { 392 | export rel7addr; 393 | } 394 | 395 | rel12addr: rel is oplow12signed [ rel = oplow12signed + inst_start + 1; ] { 396 | export *[code]:2 rel; 397 | } 398 | rel12dst: byteOffset is oplow12signed & rel12addr [ byteOffset = (oplow12signed + inst_start + 1) << 1; ] { 399 | export rel12addr; 400 | } 401 | 402 | abs22addr: loc is op4to8 & opbit0; next16 [ loc = (op4to8 << 17) | (opbit0 << 16) | next16; ] { 403 | export *[code]:2 loc; 404 | } 405 | abs22dst: byteOffset is (op4to8 & opbit0; next16) & abs22addr [ byteOffset = ((op4to8 << 17) | (opbit0 << 16) | next16) << 1; ] { 406 | export abs22addr; 407 | } 408 | 409 | next16memPtrVal1: next16 is next16 { export *[mem]:1 next16; } 410 | 411 | @ifdef FUSION 412 | ldswMemPtrVal2: ldswop1imm16 is ldswop1imm16 { export *[mem]:2 ldswop1imm16; } 413 | stswMemPtrVal2: ldswop2imm16 is ldswop2imm16 { export *[mem]:2 ldswop2imm16; } 414 | @endif 415 | 416 | # K6 is used in dword operation 417 | K6: val is oplow4 & op6to7 [ val = (op6to7 << 4) | oplow4; ] { tmp:1 = val; export tmp; } 418 | # K7 is used by lds 419 | K7addr: val is oplow4 & op9to10 & opbit8 [ val = ((1 ^ opbit8) << 7) | (opbit8 << 6) | (op9to10 << 4) | oplow4; ] { 420 | tmp:1 = val; export tmp; 421 | } 422 | # Join against various spaces for dataspace... 423 | # ##################################################################################### 424 | # COMMENTING OUT BECAUSE "Subtable symbol K7addr is not allowed in context block" 425 | #K7Ioaddr: val is K7addr [ val = K7addr - 0x20; ] { tmp:1 = val; export tmp; } 426 | # ##################################################################################### 427 | # COMMENTING OUT BECAUSE "Subtable symbol K7Ioaddr is not allowed in context block" 428 | #A7Ioaddr: val is K7Ioaddr [ val = (K7Ioaddr | 0x00) + 0x20 ; ] { export *[mem]:1 val; } 429 | Aio6: val is oplow4 & op9to10 [ val = ((op9to10 << 4) | oplow4) + 0x20; ] { export *[mem]:1 val; } 430 | Aio5: val is op3to7 [ val = (op3to7 | 0x00) + 0x20; ] { export *[mem]:1 val; } 431 | q6: val is oplow3 & op10to11 & opbit13 [ val = (opbit13 << 5) | (op10to11 << 3) | oplow3; ] { tmp:1 = val; export tmp; } 432 | 433 | @ifdef FUSION 434 | # Predicates to verify that fusion will be valid here. 435 | # We just want to construct these. The rules are not null to avoid a NOP bug with sleigh 436 | fusion16rrrrPred: val is op1bit0=0 & op2bit0=1 & op1bit4=0 & op2bit4=1 & op1bit9=op2bit9 & op1bits5to8=op2bits5to8 & op1bits1to3=op2bits1to3 [ val = 0; ] { tmp:2=val; export tmp; } 437 | fusion16rkrkPred: val is op1bits5to7=op2bits5to7 & op1bit4=0 & op2bit4=1 [ val=0; ] { tmp:2 = val; export tmp; } 438 | f3cmpPairPred: val is f3op1bits5to7=f3op3bits5to7 & f3op1bit4=0 & f3op3bit4=1 & f3op3bit8=1 [ val=0; ] { tmp:2 = val; export tmp; } 439 | f3cmpLdiPred: val is f3op3bit9=1 & f3op3bits0to3=f3op2bits4to7 [ val=0; ] { tmp:2 = val; export tmp; } 440 | ldswPairPred: val is ldswop1bit4=0 & ldswop2bit4=1 & ldswop1bits5to8=ldswop2bits5to8 [ val=0; ] { tmp:2 = val; export tmp; } 441 | stswPairPred: val is ldswop1bit4=1 & ldswop2bit4=0 & ldswop1bits5to8=ldswop2bits5to8 [ val=0; ] { tmp:2 = val; export tmp; } 442 | # would like to check this for const pair, but hangs sleigh compiler: ldswop1imm15=ldswop2imm15 443 | # So check as a few in a row 444 | # Not any better & ldswop1imm5b=ldswop2imm5b & ldswop1imm5c=ldswop2imm5c 445 | ldswConstPairPred: val is ldswop1bit16=0 & ldswop2bit16=1 & ldswop1imm6=ldswop2imm6 [ val=0; ] { tmp:2 = val; export tmp; } 446 | stswConstPairPred: val is ldswop1bit16=1 & ldswop2bit16=0 & ldswop1imm6=ldswop2imm6 [ val=0; ] { tmp:2 = val; export tmp; } 447 | @endif 448 | 449 | define pcodeop todo; 450 | define pcodeop todoflow; 451 | define pcodeop todoflags; 452 | define pcodeop todotst; 453 | 454 | define pcodeop break; 455 | 456 | @ifdef FUSION 457 | # add followed by adc 458 | :addw op1RdPair,op1RrPair is phase=1 & op1hi6=0x3 & op2hi6=0x7 & op1RdPair & op1RrPair & fusion16rrrrPred { 459 | $(Cflag) = carry(op1RdPair,op1RrPair); 460 | local pre = op1RdPair; 461 | local post = op1RdPair + op1RrPair; 462 | op1RdPair = post; 463 | $(Vflag) = (0x0000 == (pre & 0x8000)) & ((post & 0x8000) == 0x8000); 464 | setResult16Flags(post); 465 | } 466 | @endif 467 | # Rd,Rr 468 | :adc RdFull,RrFull is phase=1 & ophi6=0x7 & RdFull & RrFull { 469 | local res = RdFull + RrFull + $(Cflag); 470 | setCflagForAdd(RdFull,RrFull,res); 471 | setResultFlags(res); 472 | RdFull = res; 473 | } 474 | # Rd,Rr 475 | :add RdFull,RrFull is phase=1 & ophi6=0x3 & RdFull & RrFull { 476 | local res = RdFull + RrFull; 477 | setCflagForAdd(RdFull,RrFull,res); 478 | setResultFlags(res); 479 | RdFull = res; 480 | } 481 | # adiw Rd+1:Rd,K6 482 | :adiw Rdw2,K6 is phase=1 & ophi8=0x96 & Rdw2 & K6 { 483 | local pre = Rdw2; 484 | Rdw2 = Rdw2 + zext(K6); 485 | $(Cflag) = carry(pre,zext(K6)); 486 | $(Vflag) = (0x0000 == (pre & 0x8000)) & ((Rdw2 & 0x8000) == 0x8000); 487 | setResult16Flags(Rdw2); 488 | } 489 | # and Rd,Rr 490 | :and RdFull,RrFull is phase=1 & ophi6=8 & RdFull & RrFull { 491 | RdFull = RdFull & RrFull; 492 | $(Vflag) = 0; 493 | setResultFlags(RdFull); 494 | } 495 | # andi Rd,K 496 | :andi RdHi,K8 is phase=1 & ophi4=7 & RdHi & K8 { 497 | RdHi = RdHi & K8; 498 | $(Vflag) = 0; 499 | setResultFlags(RdHi); 500 | } 501 | # asr Rd 502 | :asr RdFull is phase=1 & ophi7=0x4a & oplow4=0x5 & RdFull { #done 503 | $(Cflag) = RdFull & 0x01; 504 | RdFull = RdFull s>> 1; 505 | $(Nflag) = (RdFull & 0x80) == 0x80; 506 | $(Vflag) = $(Nflag) ^ $(Cflag); 507 | setResultFlags(RdFull); 508 | } 509 | # bclr s 510 | :bclr op4to6_flag is phase=1 & ophi9=0x129 & oplow4=0x4 & op4to6_flag { #done 511 | op4to6_flag = 0; 512 | } 513 | # bld Rd,b 514 | :bld RdFull,oplow3 is phase=1 & ophi7=0x7c & opbit3=0 & RdFull & oplow3 { 515 | local b = $(Tflag) << oplow3; 516 | local mask = 0xff ^ (1 << oplow3); 517 | RdFull = (RdFull & mask) | b; 518 | } 519 | # brbc s,k 520 | # General brbc instruction replaced by condition-code specific variants below 521 | #:brbc rel7dst,oplow3_flag is phase=1 & ophi6=0x3d & rel7dst & oplow3_flag { 522 | # if (!oplow3_flag) 523 | # goto rel7dst; 524 | #} 525 | :br^oplow3_cc_clr rel7dst is phase=1 & ophi6=0x3d & rel7dst & oplow3_cc_clr & oplow3_flag{ 526 | if (!oplow3_flag) 527 | goto rel7dst; 528 | } 529 | 530 | # brbs s,k (see prev instruction) 531 | # General brbs instruction replaced by condition-code specific variants below 532 | #:brbs rel7dst,oplow3_flag is phase=1 & ophi6=0x3c & rel7dst & oplow3_flag { 533 | # if (oplow3_flag) 534 | # goto rel7dst; 535 | #} 536 | :br^oplow3_cc_set rel7dst is phase=1 & ophi6=0x3c & rel7dst & oplow3_cc_set & oplow3_flag { 537 | if (oplow3_flag) 538 | goto rel7dst; 539 | } 540 | :break is phase=1 & ophi16=0x9598 { 541 | break(); 542 | } 543 | # bset s 544 | :bset op4to6_flag is phase=1 & ophi9=(0x94<<1) & oplow4=0x8 & op4to6_flag { 545 | op4to6_flag = 1; 546 | } 547 | # bst Rd,b 548 | :bst RdFull,oplow3 is phase=1 & ophi7=0x7d & opbit3=0 & RdFull & oplow3 { 549 | $(Tflag) = (RdFull >> oplow3) & 0x01; 550 | } 551 | # call k - todo - handle upper bits for 24 bit architecture 552 | :call abs22dst is phase=1 & (ophi7=0x4a & op1to3=0x7) ... & abs22dst { 553 | tmp:3 = inst_next >> 1; 554 | @if PCBYTESIZE == "2" 555 | ptr:2 = tmp:2; 556 | @else 557 | ptr:3 = tmp; 558 | @endif 559 | pushPC(ptr); 560 | PC = &abs22dst; 561 | call abs22dst; 562 | } 563 | # cbi A,b 564 | :cbi Aio5,oplow3 is phase=1 & ophi8=0x98 & Aio5 & oplow3 { 565 | local x = Aio5; 566 | x = x & (0xff ^ (1 << oplow3)); 567 | Aio5 = x; 568 | } 569 | # cbr - not actual instruction 570 | 571 | # clc, clh, cli, cln ... variants on register clearing 572 | # sub bits give which bits in SREG to clear 573 | :clc is phase=1 & ophi16=0x9488 { 574 | $(Cflag) = 0; 575 | } 576 | :clh is phase=1 & ophi16=0x94d8 { 577 | $(Hflag) = 0; 578 | } 579 | :cli is phase=1 & ophi16=0x94f8 { 580 | $(Iflag) = 0; 581 | } 582 | :cln is phase=1 & ophi16=0x94a8 { 583 | $(Nflag) = 0; 584 | } 585 | :cls is phase=1 & ophi16=0x94c8 { 586 | $(Sflag) = 0; 587 | } 588 | :clt is phase=1 & ophi16=0x94e8 { 589 | $(Tflag) = 0; 590 | } 591 | :clv is phase=1 & ophi16=0x94b8 { 592 | $(Vflag) = 0; 593 | } 594 | :clz is phase=1 & ophi16=0x9498 { 595 | $(Zflag) = 0; 596 | } 597 | # clr Rd - really is EOR Rd, Rd 598 | :com RdFull is phase=1 & ophi7=0x4a & RdFull { 599 | RdFull = 0xff - RdFull; 600 | $(Vflag) = 0; 601 | $(Cflag) = 1; 602 | setResultFlags(RdFull); 603 | } 604 | :cp RdFull,RrFull is phase=1 & ophi6=0x05 & RdFull & RrFull { 605 | local x = RdFull - RrFull; 606 | setSubCarry(RdFull,RrFull); 607 | setVflagForSub(RdFull,RrFull,x); 608 | setResultFlags(x); 609 | # but doesn't set result into a register 610 | } 611 | :cpc RdFull,RrFull is phase=1 & ophi6=0x1 & RdFull & RrFull { 612 | local res = 3; 613 | doSubtractWithCarry(RdFull,RrFull,res); 614 | } 615 | :cpi RdHi,K8 is phase=1 & ophi4=0x3 & RdHi & K8 { 616 | local res = 3; 617 | doSubtract(RdHi,K8,res); 618 | } 619 | @ifdef FUSION 620 | # cpi; ldi; cpc sequence 621 | :cpiw f3op1RdPairHi,f3cmpK16" ;ldi "f3op2RdHi,f3cmpK8 is phase=1 & f3op1hi4=0x3 & f3op2hi4=0xe & f3op3hi6=0x1 & f3cmpPairPred & f3cmpLdiPred & f3op1RdPairHi & f3op2RdHi & f3cmpK16 & f3cmpK8 { 622 | local res = 3; 623 | doSubtract(f3op1RdPairHi,f3cmpK16,res); 624 | f3op2RdHi = f3cmpK8; 625 | } 626 | # cp; cpc sequence 627 | :cpw op1RdPair,op1RrPair phase=1 & is op1hi6=0x5 & op2hi6=0x1 & fusion16rrrrPred & op1RdPair & op1RrPair { 628 | local res = op1RdPair - op1RrPair; 629 | setVflagForSub16(op1RdPair,op1RrPair); 630 | setSubCarry(op1RdPair, op1RrPair); 631 | setResult16Flags(res); 632 | $(Sflag) = op1RdPair s< op1RrPair; 633 | } 634 | @endif 635 | 636 | :cpse RdFull,RrFull is phase=1 & ophi6=0x4 & RdFull & RrFull [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { 637 | SKIP = (RdFull == RrFull); 638 | } 639 | 640 | :dec RdFull is phase=1 & ophi7=0x4a & oplow4=0xa & RdFull { 641 | # doesn't set the C flag 642 | $(Vflag) = RdFull == 0x80; 643 | RdFull = RdFull - 1; 644 | setResultFlags(RdFull); 645 | } 646 | :des op4to7 is phase=1 & ophi8=0x94 & oplow4=0xb & op4to7 { todo(); } 647 | 648 | # I discovered some parts where PCBYTESIZE would be 3 don't have the EIND reg (Atmega128). 649 | # To handle that, need another flag 650 | @if HASEIND == "1" 651 | :eicall is phase=1 & ophi16=0x9519 { 652 | ptr:3 = inst_next >> 1; 653 | pushPC(ptr); 654 | PC = zext(Z) | (zext(EIND) << 16); 655 | call [PC]; 656 | } 657 | 658 | :eijmp is phase=1 & ophi16=0x9419 { 659 | PC = zext(Z) | (zext(EIND) << 16); 660 | goto [PC]; 661 | } 662 | @endif 663 | 664 | @if PCBYTESIZE == "3" 665 | :elpm is phase=1 & ophi16=0x95d8 { 666 | ptr:3 = zext(Z) | (zext(RAMPZ) << 16); 667 | tmp:2 = *[code]:2 (ptr >> 1); 668 | val:2 = (tmp >> (Z & 0x1)); 669 | R0 = val:1; 670 | } 671 | :elpm RdFull, Z is phase=1 & ophi7=0x48 & oplow4=0x6 & RdFull & Z { 672 | ptr:3 = zext(Z) | (zext(RAMPZ) << 16); 673 | tmp:2 = *[code]:2 (ptr >> 1); 674 | val:2 = (tmp >> (Z & 0x1)); 675 | RdFull = val:1; 676 | } 677 | 678 | :elpm RdFull, Z^"+" is phase=1 & ophi7=0x48 & oplow4=0x7 & RdFull & Z { 679 | ptr:3 = zext(Z) | (zext(RAMPZ) << 16); 680 | tmp:2 = *[code]:2 (ptr >> 1); 681 | val:2 = (tmp >> (Z & 0x1)); 682 | RdFull = val:1; 683 | ptr = ptr + 1; 684 | Z = ptr:2; 685 | RAMPZ = ptr[16,8]; 686 | } 687 | @endif 688 | 689 | :eor RdFull,RrFull is phase=1 & ophi6=0x9 & RdFull & RrFull { 690 | RdFull = RdFull ^ RrFull; 691 | $(Vflag) = 0; 692 | setResultFlags(RdFull); 693 | } 694 | 695 | :fmul RdHi,RrHi is phase=1 & ophi9=0x6 & opbit3=1 & RdHi & RrHi { todo(); } 696 | :fmuls RdHi,RrHi is phase=1 & ophi9=0x7 & opbit3=0 & RdHi & RrHi { todo(); } 697 | :fmulsu RdHi,RrHi is phase=1 & ophi9=0x7 & opbit3=1 & RdHi & RrHi { todo(); } 698 | 699 | :icall is phase=1 & ophi16=0x9509 { 700 | tmp:3 = inst_next >> 1; 701 | @if PCBYTESIZE == "2" 702 | ptr:2 = tmp:2; 703 | @else 704 | ptr:3 = tmp; 705 | @endif 706 | pushPC(ptr); 707 | PC = zext(Z); 708 | call [PC]; 709 | } 710 | :ijmp is phase=1 & ophi16=0x9409 { 711 | PC = zext(Z); 712 | goto [PC]; 713 | } 714 | # in Rd,A 715 | :in RdFull,Aio6 is phase=1 & ophi5=0x16 & RdFull & Aio6 { 716 | RdFull = Aio6; 717 | } 718 | :in RdFull,SPL is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xd & SPL { 719 | RdFull = SPL; 720 | } 721 | :in RdFull,SPH is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xe & SPH { 722 | RdFull = SPH; 723 | } 724 | 725 | :inc RdFull is phase=1 & ophi7=0x4a & oplow4=0x3 & RdFull { 726 | # inc doesn't set the C flag. 727 | $(Vflag) = RdFull == 0x7f; 728 | RdFull = RdFull + 1; 729 | setResultFlags(RdFull); 730 | } 731 | :jmp abs22dst is phase=1 & (ophi7=0x4a & op1to3=0x6) ... & abs22dst { 732 | PC = &abs22dst; 733 | goto abs22dst; 734 | } 735 | 736 | :lac Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x6 & Z & RdFull { 737 | tmp:1 = *[mem]:1 Z; 738 | tmp = tmp & (0xff - RdFull); 739 | *[mem]:1 Z = tmp; 740 | } 741 | 742 | :las Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x5 & Z & RdFull { 743 | tmp:1 = *[mem]:1 Z; 744 | tmp = tmp | RdFull; 745 | *[mem]:1 Z = tmp; 746 | } 747 | 748 | :lat Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x7 & Z & RdFull { 749 | tmp:1 = *[mem]:1 Z; 750 | tmp = tmp ^ RdFull; 751 | *[mem]:1 Z = tmp; 752 | } 753 | 754 | # three forms, really just specifying the increment mode 755 | # ld Rd,X 756 | :ld RdFull,X is phase=1 & ophi7=0x48 & oplow4=0xc & X & RdFull { 757 | tmp:2 = X; 758 | RdFull = *[mem]:1 tmp; 759 | } 760 | # ld Rd,Y; ld Rd,Z 761 | :ld RdFull,RstPtr is phase=1 & ophi7=0x40 & oplow3=0x0 & RdFull & RstPtr { 762 | tmp:2 = RstPtr; 763 | RdFull = *[mem]:1 tmp; 764 | } 765 | 766 | # ld Rd,Y+ ; ld Rd, X+; ld Rd, Z+ 767 | LdPlus: RstPtr^"+" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; } 768 | :ld RdFull,LdPlus is phase=1 & ophi7=0x48 & oplow2=0x01 & RdFull & LdPlus { 769 | RdFull = *[mem]:1 LdPlus; 770 | } 771 | # ld Rd,-Y ; ld Rd, -X; ld Rd, -Z 772 | LdPredec: "-"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; } 773 | :ld RdFull,LdPredec is phase=1 & ophi7=0x48 & oplow2=0x02 & RdFull & LdPredec { 774 | tmp:2 = LdPredec; 775 | RdFull = *[mem]:1 tmp; 776 | } 777 | 778 | # ldd Rd,Y+q 779 | # ldd Rd,Z+q 780 | :ldd RdFull,Rstq"+"q6 is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=0 & Rstq & RdFull & q6 { 781 | local ptr = Rstq + zext(q6); 782 | RdFull = *[mem]:1 ptr; 783 | } 784 | 785 | # Rd,K 786 | :ldi RdHi,K8 is phase=1 & ophi4=0xe & RdHi & K8 { 787 | RdHi = K8; 788 | } 789 | # lds Rd,k 790 | :lds RdFull,next16memPtrVal1 is phase=1 & ophi7=0x48 & oplow4=0 & RdFull; next16memPtrVal1 { 791 | RdFull = next16memPtrVal1; 792 | } 793 | @ifdef FUSION 794 | # Fuse together consecuitive lds ; lds 795 | # 796 | :ldsw ldswop1RdPair,ldswMemPtrVal2 is phase=1 & ldswop1hi7=0x48 & ldswop2hi7=0x48 & ldswop1low4=0 & ldswop2low4=0 & ldswMemPtrVal2 & ldswop1RdPair & ldswPairPred & ldswConstPairPred { 797 | ldswop1RdPair = ldswMemPtrVal2; 798 | } 799 | @endif 800 | # lds Rd,k Seem to get some problems here... but 16-bit instruction isn't available on all atmega64. 801 | # Furthermore, it will sometimes conflict with ldd Z+q for q=0x2_ 802 | #:lds RdHi,A7Ioaddr is ophi5=0x14 & RdHi & A7Ioaddr { 803 | # todo(); # Not currently implemented 804 | # RdHi = A7Ioaddr; 805 | #} 806 | # TODO: lpm semantic behavior needs verification ! 807 | # lpm R0 808 | :lpm R0 is phase=1 & ophi16=0x95c8 & R0 { 809 | ptr:3 = zext(Z); 810 | tmp:2 = *[code]:2 (ptr >> 1); 811 | val:2 = (tmp >> (Z & 0x1)); 812 | R0 = val:1; 813 | } 814 | # lpm Rd,Z 815 | :lpm RdFull,Z is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & Z & opbit0=0 { 816 | ptr:3 = zext(Z); 817 | tmp:2 = *[code]:2 (ptr >> 1); 818 | val:2 = (tmp >> (Z & 0x1)); 819 | RdFull = val:1; 820 | } 821 | # lpm Rd,Z+ 822 | LpmPlus: Z^"+" is Z { } 823 | :lpm RdFull,LpmPlus is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & opbit0=1 & LpmPlus { 824 | ptr:3 = zext(Z); 825 | tmp:2 = *[code]:2 (ptr >> 1); 826 | val:2 = (tmp >> (Z & 0x1)); 827 | RdFull = val:1; 828 | Z = Z + 1; 829 | } 830 | # Equivalent to add with additional constraint of same source and destination registers 831 | :lsl RdFull is phase=1 & ophi6=0x3 & (opbit8=opbit9 & oplow4=op4to7) & RdFull { 832 | $(Cflag) = RdFull & 0x80; 833 | RdFull = (RdFull << 1); 834 | $(Nflag) = RdFull & 0x80; 835 | $(Vflag) = $(Nflag) ^ $(Cflag); 836 | setResultFlags(RdFull); 837 | } 838 | :lsr RdFull is phase=1 & ophi7=0x4a & oplow4=0x6 & RdFull { 839 | $(Cflag) = RdFull & 0x01; 840 | RdFull = (RdFull >> 1); 841 | $(Vflag) = $(Cflag); 842 | setResultFlags(RdFull); 843 | } 844 | # mov Rd,Rr 845 | :mov RdFull,RrFull is phase=1 & ophi6=0xb & RdFull & RrFull { 846 | RdFull = RrFull; 847 | } 848 | # movw Rd+1:Rd,Rr+1Rr 849 | :movw Rdw4,Rrw4 is phase=1 & ophi8=0x1 & Rdw4 & Rrw4 { 850 | Rdw4 = Rrw4; 851 | } 852 | :mul RdFull,RrFull is phase=1 & ophi6=0x27 & RdFull & RrFull { 853 | a:2 = zext(RdFull); 854 | b:2 = zext(RrFull); 855 | R1R0 = a * b; 856 | setMulFlags(R1R0); 857 | } 858 | :muls RdHi,RrHi is phase=1 & ophi8=0x2 & RdHi & RrHi { 859 | a:2 = sext(RdHi); 860 | b:2 = sext(RrHi); 861 | R1R0 = a * b; 862 | setMulFlags(R1R0); 863 | } 864 | :mulsu RdHi3,RrHi3 is phase=1 & ophi8=0x3 & opbit7=0 & opbit3=0 & RdHi3 & RrHi3 { 865 | a:2 = sext(RdHi3); 866 | b:2 = zext(RrHi3); 867 | R1R0 = a * b; 868 | setMulFlags(R1R0); 869 | } 870 | :neg RdFull is phase=1 & ophi7=0x4a & oplow4=1 & RdFull { 871 | $(Vflag) = (RdFull == 0x80); 872 | RdFull = 0 - RdFull; 873 | $(Cflag) = (RdFull != 0); 874 | setResultFlags(RdFull); 875 | } 876 | :nop is phase=1 & ophi16=0x0 { 877 | } 878 | :or RdFull,RrFull is phase=1 & ophi6=0xa & RdFull & RrFull { 879 | RdFull = RdFull | RrFull; 880 | $(Vflag) = 0; 881 | setResultFlags(RdFull); 882 | } 883 | :ori RdHi,K8 is phase=1 & ophi4=0x6 & RdHi & K8 { 884 | RdHi = RdHi | K8; 885 | $(Vflag) = 0; 886 | setResultFlags(RdHi); 887 | } 888 | # out A,Rr # Note: Rr occupies the normal Rd position 889 | :out Aio6,RdFull is phase=1 & ophi5=0x17 & Aio6 & RdFull { 890 | Aio6 = RdFull; 891 | } 892 | :out SPL,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xd & SPL { 893 | SPL = RdFull; 894 | } 895 | :out SPH,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xe & SPH { 896 | SPH = RdFull; 897 | } 898 | 899 | :pop RdFull is phase=1 & ophi7=0x48 & oplow4=0xf & RdFull { 900 | pop8(RdFull); 901 | } 902 | # push Rf # Note: Rr occupies the normal Rd position 903 | :push RdFull is phase=1 & ophi7=0x49 & oplow4=0xf & RdFull { 904 | push8(RdFull); 905 | } 906 | :rcall rel12dst is phase=1 & ophi4=0xd & rel12dst { 907 | tmp:3 = inst_next >> 1; 908 | @if PCBYTESIZE == "2" 909 | ptr:2 = tmp:2; 910 | @else 911 | ptr:3 = tmp; 912 | @endif 913 | pushPC(ptr); 914 | PC = &rel12dst; 915 | call rel12dst; 916 | } 917 | :ret is phase=1 & ophi16=0x9508 { 918 | # Could also handle word size options here 919 | popPC(PC); 920 | return [PC]; 921 | } 922 | :reti is phase=1 & ophi16=0x9518 { 923 | $(Iflag) = 1; 924 | popPC(PC); 925 | return [PC]; 926 | } 927 | # rjmp k 928 | :rjmp rel12dst is phase=1 & ophi4=0xc & rel12dst { 929 | goto rel12dst; 930 | } 931 | # Equivalent to adc with additional constraint of same source and destination registers 932 | :rol RdFull is phase=1 & ophi6=0x7 & (opbit8=opbit9 & oplow4=op4to7) & RdFull { 933 | local c = $(Cflag); 934 | local cnew = RdFull & 0x80; 935 | RdFull = c | (RdFull << 1); 936 | $(Cflag) = cnew; 937 | $(Nflag) = (RdFull & 0x80) == 0x80; 938 | $(Vflag) = $(Cflag) ^ $(Nflag); 939 | setResultFlags(RdFull); 940 | } 941 | :ror RdFull is phase=1 & ophi7=0x4a & oplow4=0x7 & RdFull { 942 | local c = $(Cflag); 943 | local cnew = RdFull & 0x01; 944 | RdFull = (c << 7) | (RdFull >> 1); 945 | $(Cflag) = cnew; 946 | $(Nflag) = (RdFull & 0x80) == 0x80; 947 | $(Vflag) = $(Cflag) ^ $(Nflag); 948 | setResultFlags(RdFull); 949 | } 950 | :sbc RdFull,RrFull is phase=1 & ophi6=0x2 & RdFull & RrFull { 951 | doSubtractWithCarry(RdFull,RrFull,RdFull); 952 | } 953 | :sbci RdHi,K8 is phase=1 & ophi4=4 & RdHi & K8 { 954 | doSubtractWithCarry(RdHi,K8,RdHi); 955 | } 956 | @ifdef FUSION 957 | # subi sbci 958 | :subiw op1RdPairHi,K16fuse is phase=1 & op1hi4=0x5 & op2hi4=0x4 & K16fuse & fusion16rkrkPred & op1RdPairHi { 959 | # doSubtract(op1RdPairHi,K16fuse,op1RdPairHi); 960 | local res = op1RdPairHi - K16fuse; 961 | local pre = op1RdPairHi; 962 | setVflagForSub16(pre,K16fuse); 963 | setSubCarry(op1RdPairHi, K16fuse); 964 | op1RdPairHi = res; 965 | setResult16Flags(res); 966 | $(Sflag) = pre s< K16fuse; 967 | } 968 | @endif 969 | :sbi Aio5,oplow3 is phase=1 & ophi8=0x9a & Aio5 & oplow3 { 970 | Aio5 = Aio5 | (1 << oplow3); 971 | } 972 | 973 | :sbic Aio5,oplow3 is phase=1 & ophi8=0x99 & Aio5 & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { 974 | SKIP = ((Aio5 & (1 << oplow3)) == 0); 975 | } 976 | :sbis Aio5,oplow3 is phase=1 & ophi8=0x9b & Aio5 & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { 977 | SKIP = ((Aio5 & (1 << oplow3)) != 0); 978 | } 979 | 980 | :sbiw Rdw2,K6 is phase=1 & ophi8=0x97 & Rdw2 & K6 { 981 | local pre = Rdw2; 982 | Rdw2 = Rdw2 - zext(K6); 983 | $(Cflag) = Rdw2 < zext(K6); 984 | $(Vflag) = (0x8000 == (pre & 0x8000)) & ((Rdw2 & 0x8000) == 0x0000); 985 | setResult16Flags(Rdw2); 986 | } 987 | # sbr is an alias for ori 988 | 989 | :sbrc RdFull,oplow3 is phase=1 & ophi7=0x7e & opbit3=0 & RdFull & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { 990 | SKIP = ((RdFull & (1 << oplow3)) == 0); 991 | } 992 | :sbrs RdFull,oplow3 is phase=1 & ophi7=0x7f & opbit3=0 & RdFull & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { 993 | SKIP = ((RdFull & (1 << oplow3)) != 0); 994 | } 995 | :sec is phase=1 & ophi16=0x9408 { 996 | $(Cflag) = 1; 997 | } 998 | :seh is phase=1 & ophi16=0x9458 { 999 | $(Hflag) = 1; 1000 | } 1001 | :sei is phase=1 & ophi16=0x9478 { 1002 | $(Iflag) = 1; 1003 | } 1004 | :sen is phase=1 & ophi16=0x9428 { 1005 | $(Nflag) = 1; 1006 | } 1007 | :ser RdHi is phase=1 & ophi8=0xef & oplow4=0xf & RdHi { 1008 | RdHi = 0xff; 1009 | } 1010 | :ses is phase=1 & ophi16=0x9448 { 1011 | $(Sflag) = 1; 1012 | } 1013 | :set is phase=1 & ophi16=0x9468 { 1014 | $(Tflag) = 1; 1015 | } 1016 | :sev is phase=1 & ophi16=0x9438 { 1017 | $(Vflag) = 1; 1018 | } 1019 | :sez is phase=1 & ophi16=0x9418 { 1020 | $(Zflag) = 1; 1021 | } 1022 | define pcodeop sleep; 1023 | :sleep is phase=1 & ophi16=0x9588 { 1024 | sleep(); 1025 | } 1026 | define pcodeop store_program_mem; # make this stand out. 1027 | :spm Z is phase=1 & ophi16=0x95e8 & Z { 1028 | ptr:3 = zext(Z) << 1; 1029 | *[code]:2 ptr = R1R0; 1030 | store_program_mem(); 1031 | } 1032 | :spm Z^"+" is phase=1 & ophi16=0x95f8 & Z { 1033 | ptr:3 = zext(Z) << 1; 1034 | *[code]:2 ptr = R1R0; 1035 | Z = Z + 1; 1036 | store_program_mem(); 1037 | } 1038 | # For stores, see the ld code (just flip bit 9) 1039 | :st X, RdFull is phase=1 & ophi7=0x49 & oplow4=0xc & X & RdFull { 1040 | tmp:2 = X; 1041 | *[mem]:1 tmp = RdFull; 1042 | } 1043 | # st Rd,Y; st Rd,Z 1044 | :st RstPtr, RdFull is phase=1 & ophi7=0x41 & oplow3=0x0 & RdFull & RstPtr { 1045 | tmp:2 = RstPtr; 1046 | *[mem]:1 tmp = RdFull; 1047 | } 1048 | 1049 | # st Rd,Y+ ; st Rd, X+; st Rd, Z+ 1050 | StPlus: RstPtr^"+" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; } 1051 | :st StPlus, RdFull is phase=1 & ophi7=0x49 & oplow2=0x01 & RdFull & StPlus { 1052 | *[mem]:1 StPlus = RdFull; 1053 | } 1054 | # st Rd,-Y ; st Rd, -X; st Rd, -Z 1055 | StPredec: "-"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; } 1056 | :st StPredec, RdFull is phase=1 & ophi7=0x49 & oplow2=0x02 & RdFull & StPredec { 1057 | tmp:2 = StPredec; 1058 | *[mem]:1 tmp = RdFull; 1059 | } 1060 | # std Rd,Y+q; std Rd,Z+q 1061 | StdYq: Rstq^"+"^q6 is Rstq & q6 { local ptr = Rstq + zext(q6); export ptr; } 1062 | :std StdYq, RdFull is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=1 & RdFull & StdYq { 1063 | *[mem]:1 StdYq = RdFull; 1064 | } 1065 | 1066 | :sts next16memPtrVal1,RdFull is phase=1 & ophi7=0x49 & oplow4=0 & RdFull; next16memPtrVal1 { 1067 | next16memPtrVal1 = RdFull; 1068 | } 1069 | @ifdef FUSION 1070 | # sts ; sts emits backwards with respect to lds; lds 1071 | :stsw stswMemPtrVal2,stswop2RdPair is phase=1 & ldswop1hi7=0x49 & ldswop2hi7=0x49 & ldswop1low4=0 & ldswop2low4=0 & stswMemPtrVal2 & stswop2RdPair & stswPairPred & stswConstPairPred { 1072 | stswMemPtrVal2 = stswop2RdPair; 1073 | } 1074 | @endif 1075 | # see manual for computation of address for 16-bit STS 1076 | :sts RdHi is phase=1 & ophi5=0x15 & RdHi { todo(); } 1077 | :sub RdFull,RrFull is phase=1 & ophi6=0x6 & RdFull & RrFull { 1078 | doSubtract(RdFull,RrFull,RdFull); 1079 | } 1080 | # Rd,K 1081 | :subi RdHi,K8 is phase=1 & ophi4=5 & RdHi & K8 { 1082 | doSubtract(RdHi,K8,RdHi); 1083 | } 1084 | :swap RdFull is phase=1 & ophi7=0x4a & oplow4=2 & RdFull { 1085 | RdFull = (RdFull >> 4) | (RdFull << 4); 1086 | } 1087 | # tst is AND Rd,Rd 1088 | define pcodeop watchdog_reset; 1089 | :wdr is phase=1 & ophi16=0x95a8 { 1090 | watchdog_reset(); 1091 | } 1092 | :xch RdFull is phase=1 & ophi7=0x49 & oplow4=0x4 & RdFull { 1093 | ptr:2 = Z; 1094 | local tmp = *[mem]:1 ptr; 1095 | *[mem]:1 ptr = RdFull; 1096 | RdFull = tmp; 1097 | } 1098 | -------------------------------------------------------------------------------- /avr8egcc.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | -------------------------------------------------------------------------------- /avr8gcc.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | -------------------------------------------------------------------------------- /avr_instruction_helper.py: -------------------------------------------------------------------------------- 1 | # Create EOL comments with AVR instruction descriptions 2 | # @author: Austin Roach 3 | # @category: Instructions.AVR 4 | 5 | # Descriptions from Atmega328p datasheet 6 | _AVR_INSTRUCTIONS = \ 7 | {"add": "Add two registers without carry", 8 | "adc": "Add two registers with carry", 9 | "adiw": "Add immediate to word", 10 | "sub": "Subtract two registers", 11 | "subi": "Subtract constant from register", 12 | "sbc": "Subtract two registers with carry", 13 | "sbci": "Subtract constant from register with carry", 14 | "sbiw": "Subtract immediate from word", 15 | "and": "Logical AND registers", 16 | "andi": "Logical AND register and constant", 17 | "or": "Logical OR registers", 18 | "ori": "Logical OR register and constant", 19 | "eor": "Exclusive or registers", 20 | "com": "Ones complement", 21 | "neg": "Twos complement", 22 | "sbr": "Set bit(s) in register", 23 | "cbr": "Clear bit(s) in register", 24 | "inc": "Increment", 25 | "dec": "Decrement", 26 | "tst": "Test for zero or minus", 27 | "clr": "Clear register", 28 | "ser": "Set register", 29 | "mul": "Multiply unsigned", 30 | "muls": "Multiply signed", 31 | "mulsu": "Multiply signed with unsigned", 32 | "fmul": "Fractional multiply unsigned", 33 | "fmuls": "Fractional multiply signed", 34 | "fmulsu": "Fractional multiply signed with unsigned", 35 | "rjmp": "Relative jump", 36 | "ijmp": "Indirect jump to (Z)", 37 | "jmp": "Direct jump", 38 | "rcall": "Relative subroutine call", 39 | "icall": "Indirect call to (Z)", 40 | "call": "Direct subroutine call", 41 | "ret": "Subroutine return", 42 | "reti": "Interrupt return", 43 | "cpse": "Compare, skip if equal", 44 | "cp": "Compare", 45 | "cpc": "Compare with carry", 46 | "cpi": "Compare Register with immediate", 47 | "sbrc": "Skip if bit in register cleared", 48 | "sbrs": "Skip if bit in register set", 49 | "sbic": "Skip if bit in I/O register cleared", 50 | "sbis": "Skip if bit in I/O register set", 51 | "brbs": "Branch if status flag set", 52 | "brbc": "Branch if status flag cleared", 53 | "breq": "Branch if equal", 54 | "brne": "Branch if not equal", 55 | "brcs": "Branch if carry set", 56 | "brcc": "Branch if carry cleared", 57 | "brsh": "Branch if same or higher", 58 | "brlo": "Branch if lower", 59 | "brmi": "Branch if minus", 60 | "brpl": "Branch if plus", 61 | "brge": "Branch if greater or equal, signed", 62 | "brlt": "Branch if less than, signed", 63 | "brhs": "Branch if half carry flag set", 64 | "brhc": "Branch if half carry flag cleared", 65 | "brts": "Branch if T flag set", 66 | "brtc": "Branch if T flag cleared", 67 | "brvs": "Branch if overflow flag set", 68 | "brvc": "Branch if overflow flag cleared", 69 | "brie": "Branch if interrupt enabled", 70 | "brid": "Branch if interrupt disabled", 71 | "sbi": "Set bit in I/O register", 72 | "cbi": "Clear bit in I/O register", 73 | "lsl": "Logical shift left", 74 | "lsr": "Logical shift right", 75 | "rol": "Rotate left through carry", 76 | "ror": "Rotate right through carry", 77 | "asr": "Arithmetic shift right", 78 | "swap": "Swap nibbles", 79 | "bset": "Set flag", 80 | "bclr": "Clear flag", 81 | "bst": "Bit store from register to T", 82 | "bld": "Bit load from T to register", 83 | "sec": "Set carry", 84 | "clc": "Clear carry", 85 | "sen": "Set negative flag", 86 | "cln": "Clear negative flag", 87 | "sez": "Set zero flag", 88 | "clz": "Clear zero flag", 89 | "sei": "Global interrupt enable", 90 | "cli": "Global interrupt disable", 91 | "ses": "Set signed test flag", 92 | "cls": "Clear signed test flag", 93 | "sev": "Set twos-complement overflow", 94 | "clv": "Clear twos-complement overflow", 95 | "set": "Set T in SREG", 96 | "clt": "Clear T in SREG", 97 | "seh": "Set half carry flag", 98 | "clh": "Clear half carry flag", 99 | "mov": "Move between registers", 100 | "movw": "Copy register word", 101 | "ldi": "Load immediate", 102 | "ld": "Load indirect", 103 | "ld+": "Load indirect and post-increment", 104 | "-ld": "Load indirect and pre-decrement", 105 | "ldd": "Load indirect with displacement", 106 | "lds": "Load direct from SRAM", 107 | "st": "Store indirect", 108 | "st+": "Store indirect and post-increment", 109 | "-st": "Store indirect and pre-decrement", 110 | "std": "Store indirect with displacement", 111 | "sts": "Store direct from SRAM", 112 | "lpm": "Load program memory", 113 | "lpm+": "Load program memory and post-increment", 114 | "spm": "Store program memory", 115 | "in": "In from I/O location", 116 | "out": "Out to I/O location", 117 | "push": "Push register on stack", 118 | "pop": "Pop register from stack", 119 | "nop": "No operation", 120 | "sleep": "Sleep", 121 | "wdr": "Watchdog reset", 122 | "break": "Break"} 123 | 124 | def add_eol_comment(comment, addr): 125 | # Don't trample previous EOL comments 126 | if getEOLComment(addr) is None: 127 | listing = currentProgram.getListing() 128 | codeUnit = listing.getCodeUnitAt(addr) 129 | codeUnit.setComment(codeUnit.EOL_COMMENT, comment) 130 | 131 | def get_mnemonic(thisInstr): 132 | return thisInstr.getPrototype().getMnemonic(thisInstr.getInstructionContext()) 133 | 134 | def get_operand(thisInstr, opNum): 135 | return thisInstr.getDefaultOperandRepresentation(opNum) 136 | 137 | def add_instr_desc_comment(currInstr): 138 | currMnemonic = get_mnemonic(currInstr) 139 | currAddr = currInstr.getInstructionContext().getAddress() 140 | 141 | # Special case to handle pre-decrement/post-increment variants of ld 142 | if currMnemonic == "ld": 143 | secondOperand = get_operand(currInstr, 1) 144 | if len(secondOperand) == 2: 145 | if secondOperand[1] == "+": 146 | currMnemonic = "ld+" 147 | elif secondOperand[0] == "-": 148 | currMnemonic = "-ld" 149 | 150 | # Special case to handle pre-decrement/post-increment variants of st 151 | if currMnemonic == "st": 152 | firstOperand = get_operand(currInstr, 0) 153 | if len(firstOperand) == 2: 154 | if firstOperand[1] == "+": 155 | currMnemonic = "st+" 156 | elif firstOperand[0] == "-": 157 | currMnemonic = "-st" 158 | 159 | # Special case to handle pre-decrement/post-increment variants of lpm 160 | if currMnemonic == "lpm": 161 | secondOperand = get_operand(currInstr, 1) 162 | if len(secondOperand) == 2: 163 | if secondOperand[1] == "+": 164 | currMnemonic = "lpm+" 165 | 166 | # Add a comment for the current mnemonic 167 | add_eol_comment(_AVR_INSTRUCTIONS[currMnemonic], currAddr) 168 | 169 | def loop_over_selection(): 170 | # If no selection, try to add a comment for the current address 171 | if currentSelection is None: 172 | currInstr = getInstructionAt(currentAddress) 173 | if currInstr: 174 | add_instr_desc_comment(currInstr) 175 | return 176 | 177 | currAddr = currentSelection.getMinAddress() 178 | currInstr = getInstructionAt(currAddr) 179 | if not currInstr: 180 | # There's no instruction at the current address, so try to find one 181 | # later in the selection 182 | currInstr = getInstructionAfter(currAddr) 183 | if not currInstr: 184 | # We must not have one at all 185 | return 186 | currAddr = currInstr.getInstructionContext().getAddress() 187 | 188 | 189 | while currAddr < currentSelection.getMaxAddress(): 190 | # Check to be sure that this instruction is in the selection, to handle 191 | # non-contiguous selection regions 192 | if currentSelection.contains(currInstr.getInstructionContext().getAddress()): 193 | add_instr_desc_comment(currInstr) 194 | 195 | currInstr = currInstr.getNext() 196 | if not(currInstr): 197 | # No more instructions in the selection 198 | break 199 | 200 | currAddr = currInstr.getInstructionContext().getAddress() 201 | 202 | if __name__ == "__main__": 203 | loop_over_selection() 204 | 205 | --------------------------------------------------------------------------------