├── .gitignore ├── README.md ├── aijubrd ├── axi3.v ├── blit.vlt ├── build.tcl ├── c │ ├── dat.h │ ├── dport.c │ ├── fns.h │ ├── main.c │ ├── mkfile │ └── telnet.c ├── dport │ ├── dport.v │ ├── dport.vh │ ├── dport_aux.v │ ├── dport_gtp.v │ ├── dport_phy.v │ ├── dport_pxclk.v │ ├── dport_pxconv.v │ ├── dport_pxconv_tb.v │ ├── dport_regs.v │ ├── dport_scrambler.v │ └── dport_stuff.v ├── extra.xdc ├── fns.tcl ├── mkfile ├── pulse_sync.v ├── regs.v ├── sync.v ├── top.v └── top.xdc ├── blit.v ├── blit_bus.v ├── blit_cpu.v ├── blit_disp.v ├── blit_ram.v ├── blit_ramarb.v ├── blit_regs.v ├── blit_rom.v ├── fx68k.sv ├── fx68k_microrom.mem ├── fx68k_nanorom.mem ├── rom.mem ├── run.sh └── sim.cc /.gitignore: -------------------------------------------------------------------------------- 1 | /obj_dir 2 | *.jou 3 | *.log 4 | usage_statistics_webtalk.html 5 | usage_statistics_webtalk.xml 6 | .Xil 7 | /aijubrd/build 8 | *.5 9 | 5.out 10 | *.vcd 11 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | FPGA Blit 2 | =========== 3 | 4 | This is an FPGA implementation of the Blit terminal (the original 68K version, not the DMD5620). 5 | It's only meant to be "software-compatible" and not an accurate reproduction of the original hardware (which is hard without schematics). 6 | It's based on the games/blit emulator shipped with 9front (which is itself based on reverse-engineering the register locations by reading the Blit source code in the V8 release). 7 | 8 | The code in the root directory is meant to be independent of the hardware, although it may have to be adjusted because not all details will work on all platforms (e.g. it uses block RAMs for the 256KB RAM). 9 | The `aijubrd` directory contains an implementation for [aijuboard](http://aiju.de/electronics/aijuboard/), which uses DisplayPort for output (padding the 800x1024 image from the blit to 1280x1024) and handles the keyboard, mouse and UART interfaces from Plan 9. 10 | 11 | The `aijubrd` directory has files `top.v` and `top.xdc` which are generated using the [`vlt` tool](https://github.com/aiju/hdl/tree/master/tools/vlt). 12 | -------------------------------------------------------------------------------- /aijubrd/axi3.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | /* limitation in vlt -- to be replaced by a parameter */ 3 | `define ID 12 4 | 5 | module axi3 #( 6 | parameter TIMEOUT = 1048575 7 | ) ( 8 | input wire clk, 9 | input wire rstn, 10 | 11 | output wire axiaclk, 12 | 13 | input wire axiarvalid, 14 | output reg axiarready, 15 | input wire [31:0] axiaraddr, 16 | input wire [1:0] axiarburst, axiarlock, 17 | input wire [2:0] axiarsize, axiarprot, 18 | input wire [3:0] axiarlen, axiarcache, axiarqos, 19 | input wire [`ID-1:0] axiarid, 20 | 21 | output reg axirvalid, 22 | input wire axirready, 23 | output reg [31:0] axirdata, 24 | output reg [`ID-1:0] axirid, 25 | output reg [1:0] axirresp, 26 | output reg axirlast, 27 | 28 | input wire axiawvalid, 29 | output reg axiawready, 30 | input wire [31:0] axiawaddr, 31 | input wire [1:0] axiawburst, axiawlock, 32 | input wire [2:0] axiawsize, axiawprot, 33 | input wire [3:0] axiawlen, axiawcache, axiawqos, 34 | input wire [`ID-1:0] axiawid, 35 | 36 | input wire axiwvalid, 37 | output reg axiwready, 38 | input wire [31:0] axiwdata, 39 | input wire [3:0] axiwstrb, 40 | input wire [`ID-1:0] axiwid, 41 | input wire axiwlast, 42 | 43 | output reg axibvalid, 44 | input wire axibready, 45 | output reg [1:0] axibresp, 46 | output reg [`ID-1:0] axibid, 47 | 48 | output reg [31:0] outaddr, 49 | input wire [31:0] outrdata, 50 | output reg [31:0] outwdata, 51 | output reg outwr, 52 | output reg outreq, 53 | input wire outack, 54 | input wire outerr, 55 | output reg [3:0] outwstrb 56 | ); 57 | 58 | localparam OKAY = 0; 59 | // localparam EXOKAY = 1; 60 | localparam SLVERR = 2; 61 | localparam DECERR = 3; 62 | // localparam FIXED = 0; 63 | localparam INCR = 1; 64 | // localparam WRAP = 2; 65 | 66 | reg [2:0] state; 67 | localparam IDLE = 0; 68 | localparam READOUT = 1; 69 | localparam READREPLY = 2; 70 | localparam WAITWRDATA = 3; 71 | localparam WRITEOUT = 4; 72 | localparam WRRESP = 5; 73 | 74 | reg rpend; 75 | reg [31:0] axiawaddr0, axiaraddr0; 76 | reg [1:0] axiawburst0, axiarburst0; 77 | reg [1:0] axiawsize0, axiarsize0; 78 | reg [3:0] axiawlen0, axiarlen0; 79 | reg [31:0] timer; 80 | 81 | assign axiaclk = clk; 82 | 83 | function [31:0] nextaddr(input [31:0] addr, input [1:0] axiburst, input [1:0] size); 84 | case(axiburst) 85 | default: nextaddr = addr; 86 | INCR: nextaddr = addr + (1<; 18 | auxp ; 19 | auxn ; 20 | tx ; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /aijubrd/build.tcl: -------------------------------------------------------------------------------- 1 | source fns.tcl 2 | 3 | new 4 | read_verilog -sv [notb [here]/*.v [here]/../*.v [here]/dport/*.v] 5 | read_verilog -sv [here]/../fx68k.sv 6 | read_xdc [here]/top.xdc 7 | read_xdc [here]/extra.xdc 8 | synth top none 9 | implement 10 | bitstream 11 | -------------------------------------------------------------------------------- /aijubrd/c/dat.h: -------------------------------------------------------------------------------- 1 | extern uchar *mmio; 2 | 3 | enum { 4 | UART_IN_DATA = 0x00, 5 | UART_IN_STATUS = 0x04, 6 | KBD_IN_DATA = 0x08, 7 | KBD_IN_STATUS = 0x0C, 8 | UART_OUT = 0x10, 9 | MOUSE = 0x14, 10 | MOUSE_BUT = 0x18, 11 | 12 | }; 13 | -------------------------------------------------------------------------------- /aijubrd/c/dport.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include "dat.h" 5 | #include "fns.h" 6 | 7 | enum { 8 | CTRL = 0x00, 9 | STS = 0x04, 10 | AUXCTRL = 0x08, 11 | AUXSTAT = 0x0C, 12 | HVACT = 0x40, 13 | HVTOT = 0x44, 14 | HVSYNC = 0x48, 15 | HVDATA = 0x4c, 16 | MISC = 0x50, 17 | MVID0 = 0x54, 18 | NVID0 = 0x58, 19 | SCLK0 = 0x5c, 20 | MVID1 = 0x60, 21 | NVID1 = 0x64, 22 | SCLK1 = 0x68, 23 | 24 | LINK_BW_SET = 0x100, 25 | LANE_COUNT_SET = 0x101, 26 | TRAINING_PATTERN_SET = 0x102, 27 | TRAINING_LANE0_SET = 0x103, 28 | TRAINING_LANE1_SET = 0x104, 29 | LANE0_1_STATUS = 0x202, 30 | LANE_ALIGN_STATUS_UPDATED = 0x204, 31 | ADJUST_REQUEST_LANE0_1 = 0x206, 32 | 33 | LANE0_CR_DONE = 1, 34 | LANE0_CHANNEL_EQ_DONE = 2, 35 | LANE0_SYMBOL_LOCKED = 4, 36 | LANE1_CR_DONE = 16, 37 | LANE1_CHANNEL_EQ_DONE = 32, 38 | LANE1_SYMBOL_LOCKED = 64, 39 | INTERLANE_ALIGN_DONE = 1, 40 | }; 41 | 42 | u32int 43 | dp_read(int a) 44 | { 45 | u32int v; 46 | 47 | if(a != AUXSTAT) print("read DP %.2x = ", a); 48 | v = *(u32int*)(&mmio[0x100 + a]); 49 | if(a != AUXSTAT) print("%.8ux\n", v); 50 | return v; 51 | } 52 | 53 | void 54 | dp_write(int a, u32int v) 55 | { 56 | if(a != AUXCTRL) print("write DP %.2x = %.8ux\n", a, v); 57 | *(u32int*)(&mmio[0x100 + a]) = v; 58 | } 59 | 60 | u8int 61 | aux_read(int a) 62 | { 63 | u32int s; 64 | u8int *m; 65 | 66 | print("read AUX %.3x = ", a); 67 | m = mmio + 0x200; 68 | m[0] = 0x90 | a >> 16 & 0xf; 69 | m[1] = a >> 8; 70 | m[2] = a; 71 | m[3] = 0; 72 | dp_write(AUXCTRL, 1<<31 | 3); 73 | do{ 74 | sleep(1); 75 | s = dp_read(AUXSTAT); 76 | }while((s & 1<<31) == 0); 77 | if((s & 0x100) != 0) sysfatal("aux timeout"); 78 | if((s & 0x1f) != 2) sysfatal("wrong number of bytes returned"); 79 | if(m[0] != 0) sysfatal("aux error code %.2x", m[0]); 80 | print("%.2x\n", m[1]); 81 | return m[1]; 82 | } 83 | 84 | void 85 | aux_write(int a, u8int v) 86 | { 87 | u32int s; 88 | u8int *m; 89 | 90 | print("write AUX %.3x = %.2x\n", a, v); 91 | m = mmio + 0x200; 92 | m[0] = 0x80 | a >> 16 & 0xf; 93 | m[1] = a >> 8; 94 | m[2] = a; 95 | m[3] = 0; 96 | m[4] = v; 97 | dp_write(AUXCTRL, 1<<31 | 4); 98 | do{ 99 | sleep(1); 100 | s = dp_read(AUXSTAT); 101 | }while((s & 1<<31) == 0); 102 | if((s & 0x100) != 0) sysfatal("aux timeout"); 103 | if((s & 0x1f) != 1) sysfatal("wrong number of bytes returned"); 104 | if(m[0] != 0) sysfatal("aux error code %.2x", m[0]); 105 | } 106 | 107 | void 108 | dport(void) 109 | { 110 | uchar s; 111 | int twolane, fast, emph0, emph1, swing0, swing1, ctr, lasts, stage; 112 | 113 | emph0 = 0; 114 | swing0 = 0; 115 | emph1 = 0; 116 | swing1 = 0; 117 | 118 | dp_write(CTRL, 0); 119 | dp_write(MISC, 0x21); 120 | 121 | dp_write(HVACT, 1280 << 16 | 1024); 122 | dp_write(HVTOT, 1712 << 16 | 1060); 123 | dp_write(HVSYNC, 136 << 16 | 3); 124 | dp_write(HVDATA, 352 << 16 | 35); 125 | dp_write(MVID0, 41); 126 | dp_write(NVID0, 61); 127 | dp_write(SCLK0, 44049); 128 | dp_write(MVID1, 25); 129 | dp_write(NVID1, 62); 130 | dp_write(SCLK1, 26426); 131 | 132 | ctr = 0; 133 | lasts = -1; 134 | fast = 1; 135 | twolane = 1; 136 | aux_write(LINK_BW_SET, fast ? 0x0A : 0x06); 137 | aux_write(LANE_COUNT_SET, twolane + 1); 138 | stage = 0; 139 | for(;;){ 140 | print("stage %d\n", stage); 141 | dp_write(CTRL, 1 << 17 | (stage == 1 ? 0x3000 : 0x2000) | swing1 << 10 | swing0 << 8 | emph1 << 6 | emph0 << 4 | twolane << 1 | fast); 142 | aux_write(TRAINING_PATTERN_SET, 1 + stage); 143 | aux_write(TRAINING_LANE0_SET, (emph0 == 3) << 6 | emph0 << 3 | (swing0 == 3) << 2 | swing0); 144 | aux_write(TRAINING_LANE1_SET, (emph1 == 3) << 6 | emph1 << 3 | (swing1 == 3) << 2 | swing1); 145 | sleep(10); 146 | s = aux_read(LANE0_1_STATUS); 147 | if(stage == 0){ 148 | if((s & LANE0_CR_DONE) != 0 && (!twolane || (s & (LANE1_CR_DONE) != 0))){ 149 | stage = 1; 150 | lasts = -1; 151 | } 152 | }else{ 153 | if((s & LANE0_CR_DONE) == 0 || twolane && (s & LANE1_CR_DONE) == 0) 154 | stage = 0; 155 | else if((~s & (LANE0_CHANNEL_EQ_DONE | LANE0_SYMBOL_LOCKED | (twolane * (LANE1_CHANNEL_EQ_DONE | LANE1_SYMBOL_LOCKED)))) == 0){ 156 | if(aux_read(LANE_ALIGN_STATUS_UPDATED) & INTERLANE_ALIGN_DONE) 157 | break; 158 | } 159 | } 160 | s = aux_read(ADJUST_REQUEST_LANE0_1); 161 | if(s == lasts){ 162 | if(++ctr == 5) 163 | sysfatal("training failed"); 164 | }else 165 | ctr = 0; 166 | lasts = s; 167 | swing0 = s & 3; 168 | emph0 = s >> 2 & 3; 169 | swing1 = s >> 4 & 3; 170 | emph1 = s >> 6 & 3; 171 | } 172 | dp_write(CTRL, 0x1000 | swing1 << 10 | swing0 << 8 | emph1 << 6 | emph0 << 4 | twolane << 1 | fast); 173 | aux_write(TRAINING_PATTERN_SET, 0); 174 | } 175 | -------------------------------------------------------------------------------- /aijubrd/c/fns.h: -------------------------------------------------------------------------------- 1 | void dport(void); 2 | u32int reg_read(int a); 3 | void reg_write(int a, u32int v); 4 | u32int reg_poll(int, u32int, u32int); 5 | void telnetinit(char *); 6 | -------------------------------------------------------------------------------- /aijubrd/c/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include "dat.h" 8 | #include "fns.h" 9 | 10 | uchar *mmio; 11 | 12 | u32int 13 | reg_read(int a) 14 | { 15 | u32int v; 16 | 17 | v = *(u32int*)(&mmio[a]); 18 | return v; 19 | } 20 | 21 | void 22 | reg_write(int a, u32int v) 23 | { 24 | *(u32int*)(&mmio[a]) = v; 25 | } 26 | 27 | u32int 28 | reg_poll(int a, u32int m, u32int v) 29 | { 30 | int c; 31 | u32int s; 32 | 33 | for(c = 0;; c++){ 34 | s = reg_read(a); 35 | if((s & m) == v) 36 | return s; 37 | if(c > 1000) 38 | sleep(1); 39 | } 40 | } 41 | 42 | static Channel *keych; 43 | static uchar 44 | keymap[] = { 45 | [Kup-KF] 0xf1, 46 | [Kdown-KF] 0xf2, 47 | [Kleft-KF] 0xf3, 48 | [Kright-KF] 0xf4, 49 | [1] 0xf6, /* PF1 */ 50 | [2] 0xf7, /* PF2 */ 51 | [3] 0xf8, /* PF3 */ 52 | [4] 0xf9, /* PF4 */ 53 | [12] 0xfe, /* SET-UP */ 54 | [Kpgdown-KF] 0xb0, /* SCROLL */ 55 | [Kins-KF] 0xe0, /* BREAK */ 56 | }; 57 | 58 | static void 59 | keyproc(void *) 60 | { 61 | int fd, cfd, ch, rc; 62 | static char buf[256]; 63 | char *p; 64 | Rune r; 65 | 66 | fd = open("/dev/cons", OREAD); 67 | if(fd < 0) 68 | sysfatal("open: %r"); 69 | cfd = open("/dev/consctl", OWRITE); 70 | if(cfd < 0) 71 | sysfatal("open: %r"); 72 | fprint(cfd, "rawon"); 73 | for(;;){ 74 | rc = read(fd, buf, sizeof(buf) - 1); 75 | if(rc <= 0) 76 | sysfatal("read /dev/cons: %r"); 77 | for(p = buf; p < buf + rc && (p += chartorune(&r, p)); ){ 78 | if(r == Kend){ 79 | close(fd); 80 | threadexitsall(nil); 81 | } 82 | ch = r; 83 | if(ch == '\n') ch = '\r'; 84 | else if(ch >= KF){ 85 | if(ch >= KF + nelem(keymap)) continue; 86 | ch = keymap[ch - KF]; 87 | if(ch == 0) continue; 88 | }else if(ch >= 0x80) continue; 89 | send(keych, &ch); 90 | } 91 | } 92 | } 93 | 94 | static void 95 | keywproc(void *) 96 | { 97 | int ch; 98 | 99 | for(;;){ 100 | recv(keych, &ch); 101 | reg_poll(KBD_IN_STATUS, 1, 0); 102 | reg_write(KBD_IN_DATA, ch); 103 | } 104 | } 105 | 106 | static void 107 | mouseproc(void *) 108 | { 109 | Mousectl *mc; 110 | int fd; 111 | 112 | mc = initmouse(nil, nil); 113 | if(mc == nil) sysfatal("initmouse: %r"); 114 | fd = open("/dev/fbctl", OWRITE); 115 | if(fd < 0) sysfatal("open: %r"); 116 | fprint(fd, "size 800x1024x32 x8r8g8b8"); 117 | for(;;){ 118 | if(readmouse(mc) < 0) 119 | sysfatal("readmouse: %r"); 120 | reg_write(MOUSE, 799 - mc->xy.x | 1023 - mc->xy.y << 16); 121 | reg_write(MOUSE_BUT, mc->buttons >> 2 & 1 | mc->buttons & 2 | mc->buttons << 2 & 4); 122 | } 123 | } 124 | 125 | void 126 | threadmain(int argc, char **argv) 127 | { 128 | ARGBEGIN{ 129 | default: sysfatal("usage"); 130 | }ARGEND; 131 | if(argc != 1) sysfatal("usage"); 132 | 133 | mmio = segattach(0, "axi", nil, 1048576*4); 134 | if(mmio == (uchar*)-1) 135 | sysfatal("segattach: %r"); 136 | 137 | dport(); 138 | 139 | keych = chancreate(sizeof(char), 128); 140 | proccreate(keyproc, nil, mainstacksize); 141 | proccreate(keywproc, nil, mainstacksize); 142 | proccreate(mouseproc, nil, mainstacksize); 143 | 144 | telnetinit(argv[0]); 145 | } 146 | -------------------------------------------------------------------------------- /aijubrd/c/mkfile: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include "dat.h" 5 | #include "fns.h" 6 | 7 | Channel *telnetrxch, *telnettxch; 8 | Channel *uartrxch, *uarttxch; 9 | int teldebug; 10 | 11 | enum { 12 | SE = 240, 13 | NOP = 241, 14 | BRK = 243, 15 | IP = 244, 16 | AO = 245, 17 | AYT = 246, 18 | EC = 247, 19 | EL = 248, 20 | GA = 249, 21 | SB = 250, 22 | WILL = 251, 23 | WONT = 252, 24 | DO = 253, 25 | DONT = 254, 26 | IAC = 255, 27 | 28 | XMITBIN = 0, 29 | ECHO = 1, 30 | SUPRGA = 3, 31 | LINEEDIT = 34, 32 | 33 | }; 34 | 35 | int telfd; 36 | 37 | static void 38 | netrproc(void *) 39 | { 40 | static uchar buf[512]; 41 | int n, c; 42 | uchar *p; 43 | 44 | for(;;){ 45 | n = read(telfd, buf, sizeof(buf)); 46 | if(n < 0) sysfatal("read: %r"); 47 | for(p = buf; p < buf + n; p++){ 48 | c = *p; 49 | send(telnetrxch, &c); 50 | } 51 | } 52 | } 53 | 54 | static void 55 | netwproc(void *) 56 | { 57 | static uchar buf[512]; 58 | int c; 59 | uchar *p; 60 | 61 | for(;;){ 62 | recv(telnettxch, &c); 63 | p = buf; 64 | do 65 | *p++ = c; 66 | while(nbrecv(telnettxch, &c) > 0); 67 | if(write(telfd, buf, p - buf) < p - buf) 68 | sysfatal("write: %r"); 69 | } 70 | } 71 | 72 | static void 73 | telnetrthread(void *) 74 | { 75 | int c; 76 | 77 | for(;;){ 78 | recv(telnetrxch, &c); 79 | if(c != IAC){ 80 | send(uartrxch, &c); 81 | continue; 82 | } 83 | recv(telnetrxch, &c); 84 | switch(c){ 85 | case NOP: break; 86 | case WILL: 87 | recv(telnetrxch, &c); 88 | if(teldebug) fprint(2, "WILL %d\n", c); 89 | break; 90 | case WONT: 91 | recv(telnetrxch, &c); 92 | if(teldebug) fprint(2, "WONT %d\n", c); 93 | break; 94 | case DO: 95 | recv(telnetrxch, &c); 96 | if(teldebug) fprint(2, "DO %d\n", c); 97 | break; 98 | case DONT: 99 | recv(telnetrxch, &c); 100 | if(teldebug) fprint(2, "DONT %d\n", c); 101 | break; 102 | case IAC: 103 | send(uartrxch, &c); 104 | break; 105 | default: 106 | fprint(2, "unknown telnet command %d\n", c); 107 | } 108 | } 109 | } 110 | 111 | static void 112 | cmd(int a, int b) 113 | { 114 | send(telnettxch, &a); 115 | if(b >= 0) send(telnettxch, &b); 116 | } 117 | 118 | static void 119 | telnetwthread(void *) 120 | { 121 | int c; 122 | 123 | for(;;){ 124 | recv(uarttxch, &c); 125 | send(telnettxch, &c); 126 | if(c == 0xff) 127 | send(telnettxch, &c); 128 | } 129 | } 130 | 131 | static void 132 | uartrproc(void *) 133 | { 134 | int c; 135 | 136 | for(;;){ 137 | recv(uartrxch, &c); 138 | reg_poll(UART_IN_STATUS, 1, 0); 139 | reg_write(UART_IN_DATA, c); 140 | } 141 | } 142 | 143 | static void 144 | uartwproc(void *) 145 | { 146 | int c; 147 | 148 | for(;;){ 149 | c = reg_poll(UART_OUT, 1<<31, 0); 150 | send(uarttxch, &c); 151 | } 152 | } 153 | 154 | void 155 | telnetinit(char *dialstr) 156 | { 157 | telfd = dial(netmkaddr(dialstr, nil, "telnet"), nil, nil, nil); 158 | if(telfd < 0) sysfatal("dial: %r"); 159 | telnetrxch = chancreate(sizeof(int), 128); 160 | telnettxch = chancreate(sizeof(int), 128); 161 | uartrxch = chancreate(sizeof(int), 128); 162 | uarttxch = chancreate(sizeof(int), 128); 163 | cmd(WILL, XMITBIN); 164 | cmd(DO, XMITBIN); 165 | cmd(DONT, ECHO); 166 | cmd(DO, SUPRGA); 167 | cmd(WILL, SUPRGA); 168 | cmd(WONT, LINEEDIT); 169 | cmd(DONT, LINEEDIT); 170 | proccreate(netrproc, nil, mainstacksize); 171 | proccreate(netwproc, nil, mainstacksize); 172 | threadcreate(telnetrthread, nil, mainstacksize); 173 | threadcreate(telnetwthread, nil, mainstacksize); 174 | proccreate(uartrproc, nil, mainstacksize); 175 | proccreate(uartwproc, nil, mainstacksize); 176 | } 177 | -------------------------------------------------------------------------------- /aijubrd/dport/dport.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport( 4 | input wire clk, 5 | 6 | input wire pixel_valid, 7 | input wire [15:0] pixel_data, 8 | 9 | input wire [7:0] reg_addr, 10 | output wire [31:0] reg_rdata, 11 | input wire [31:0] reg_wdata, 12 | input wire reg_wr, 13 | input wire reg_req, 14 | output wire reg_ack, 15 | input wire [3:0] reg_wstrb, 16 | output wire reg_err, 17 | 18 | input wire [4:0] aux_addr, 19 | input wire [31:0] aux_wdata, 20 | input wire aux_req, 21 | input wire aux_wr, 22 | output reg aux_ack, 23 | output reg [31:0] aux_rdata, 24 | 25 | input wire [1:0] refclk, 26 | output wire [3:0] tx, 27 | inout wire auxp, 28 | inout wire auxn, 29 | 30 | output wire dmahstart, 31 | output wire vblank 32 | ); 33 | 34 | wire auxi; 35 | 36 | /*AUTOWIRE*/ 37 | // Beginning of automatic wires (for undeclared instantiated-module outputs) 38 | wire [`ATTRMAX:0] attr; // From regs_i of dport_regs.v 39 | wire [31:0] auxctrl; // From regs_i of dport_regs.v 40 | wire auxd; // From aux_i of dport_aux.v 41 | wire auxo; // From aux_i of dport_aux.v 42 | wire [31:0] auxstat; // From aux_i of dport_aux.v 43 | wire dmastart; // From pxclk_i of dport_pxclk.v 44 | wire [47:0] dp_pixel_data; // From pxconv_i of dport_pxconv.v 45 | wire dp_pixel_ready; // From stuff_i of dport_stuff.v 46 | wire dp_pixel_valid; // From pxconv_i of dport_pxconv.v 47 | wire dpclk; // From gtp_i of dport_gtp.v 48 | wire [15:0] dpdat0; // From stuff_i of dport_stuff.v 49 | wire [15:0] dpdat1; // From stuff_i of dport_stuff.v 50 | wire dpdmahstart; // From pxclk_i of dport_pxclk.v 51 | wire dphstart; // From pxclk_i of dport_pxclk.v 52 | wire [1:0] dpisk0; // From stuff_i of dport_stuff.v 53 | wire [1:0] dpisk1; // From stuff_i of dport_stuff.v 54 | wire dpvblank; // From pxclk_i of dport_pxclk.v 55 | wire dpvstart; // From pxclk_i of dport_pxclk.v 56 | wire gtpready; // From gtp_i of dport_gtp.v 57 | wire [31:0] phyctl; // From regs_i of dport_regs.v 58 | wire raw_pixel_ready; // From pxconv_i of dport_pxconv.v 59 | wire [15:0] txdat0; // From phy_i of dport_phy.v 60 | wire [15:0] txdat1; // From phy_i of dport_phy.v 61 | wire [1:0] txisk0; // From phy_i of dport_phy.v 62 | wire [1:0] txisk1; // From phy_i of dport_phy.v 63 | // End of automatics 64 | 65 | wire speed = phyctl[0]; 66 | wire twolane = phyctl[1]; 67 | wire [1:0] preemph0 = phyctl[5:4]; 68 | wire [1:0] preemph1 = phyctl[7:6]; 69 | wire [1:0] swing0 = phyctl[9:8]; 70 | wire [1:0] swing1 = phyctl[11:10]; 71 | wire [1:0] phymode = phyctl[13:12]; 72 | wire [2:0] prbssel = phyctl[16:14]; 73 | wire reset = phyctl[17]; 74 | 75 | dport_regs regs_i(/*AUTOINST*/ 76 | // Outputs 77 | .reg_rdata (reg_rdata[31:0]), 78 | .reg_ack (reg_ack), 79 | .reg_err (reg_err), 80 | .attr (attr[`ATTRMAX:0]), 81 | .phyctl (phyctl[31:0]), 82 | .auxctrl (auxctrl[31:0]), 83 | // Inputs 84 | .clk (clk), 85 | .reg_addr (reg_addr[7:0]), 86 | .reg_wdata (reg_wdata[31:0]), 87 | .reg_wr (reg_wr), 88 | .reg_req (reg_req), 89 | .reg_wstrb (reg_wstrb[3:0]), 90 | .auxstat (auxstat[31:0])); 91 | dport_aux aux_i(/*AUTOINST*/ 92 | // Outputs 93 | .auxstat (auxstat[31:0]), 94 | .aux_ack (aux_ack), 95 | .aux_rdata (aux_rdata[31:0]), 96 | .auxo (auxo), 97 | .auxd (auxd), 98 | // Inputs 99 | .clk (clk), 100 | .auxctrl (auxctrl[31:0]), 101 | .aux_addr (aux_addr[4:0]), 102 | .aux_wdata (aux_wdata[31:0]), 103 | .aux_req (aux_req), 104 | .aux_wr (aux_wr), 105 | .auxi (auxi)); 106 | 107 | reg fiforeset = 1'b1; 108 | reg [7:0] rstctr; 109 | always @(posedge clk) begin 110 | if(rstctr != 255) 111 | rstctr <= rstctr + 1; 112 | else 113 | fiforeset <= 1'b0; 114 | end 115 | 116 | wire [63:0] fifodo; 117 | wire fifoempty; 118 | wire fiforden; 119 | FIFO36E1 #( 120 | .DATA_WIDTH("18"), 121 | .SIM_DEVICE("7SERIES"), 122 | .FIFO_MODE("FIFO36_72"), 123 | .ALMOST_FULL_OFFSET(32), 124 | .FIRST_WORD_FALL_THROUGH("TRUE") 125 | ) fifo( 126 | .WRCLK(clk), 127 | .WREN(pixel_valid), 128 | .DI({48'b0, pixel_data}), 129 | 130 | .RDCLK(dpclk), 131 | .DO(fifodo), 132 | .RDEN(fiforden), 133 | .EMPTY(fifoempty), 134 | .RST(fiforeset) 135 | ); 136 | wire [15:0] raw_pixel_data = fifodo[15:0]; 137 | wire raw_pixel_valid = !fifoempty && !fiforeset; 138 | assign fiforden = raw_pixel_valid && raw_pixel_ready; 139 | dport_pxconv pxconv_i(/*AUTOINST*/ 140 | // Outputs 141 | .raw_pixel_ready (raw_pixel_ready), 142 | .dp_pixel_valid (dp_pixel_valid), 143 | .dp_pixel_data (dp_pixel_data[47:0]), 144 | // Inputs 145 | .dpclk (dpclk), 146 | .reset (reset), 147 | .raw_pixel_valid (raw_pixel_valid), 148 | .raw_pixel_data (raw_pixel_data[15:0]), 149 | .dp_pixel_ready (dp_pixel_ready), 150 | .dpdmahstart (dpdmahstart)); 151 | dport_pxclk pxclk_i(/*AUTOINST*/ 152 | // Outputs 153 | .dphstart (dphstart), 154 | .dpvstart (dpvstart), 155 | .dmastart (dmastart), 156 | .dpvblank (dpvblank), 157 | .dpdmahstart (dpdmahstart), 158 | // Inputs 159 | .dpclk (dpclk), 160 | .attr (attr[`ATTRMAX:0]), 161 | .speed (speed), 162 | .reset (reset)); 163 | pulse_sync sync_hstart(dpclk, clk, dpdmahstart, dmahstart); 164 | pulse_sync sync_vblank(dpclk, clk, dpvblank, vblank); 165 | dport_stuff stuff_i(/*AUTOINST*/ 166 | // Outputs 167 | .dp_pixel_ready (dp_pixel_ready), 168 | .dpdat0 (dpdat0[15:0]), 169 | .dpdat1 (dpdat1[15:0]), 170 | .dpisk0 (dpisk0[1:0]), 171 | .dpisk1 (dpisk1[1:0]), 172 | // Inputs 173 | .dpclk (dpclk), 174 | .dp_pixel_valid (dp_pixel_valid), 175 | .dp_pixel_data (dp_pixel_data[47:0]), 176 | .dphstart (dphstart), 177 | .dpvstart (dpvstart), 178 | .dmastart (dmastart), 179 | .attr (attr[`ATTRMAX:0]), 180 | .twolane (twolane), 181 | .speed (speed), 182 | .reset (reset)); 183 | wire [15:0] scrdat0, scrdat1; 184 | wire [1:0] scrisk0, scrisk1; 185 | dport_scrambler scr0(dpclk, dpdat0, dpisk0, scrdat0, scrisk0); 186 | dport_scrambler scr1(dpclk, dpdat1, dpisk1, scrdat1, scrisk1); 187 | dport_phy phy_i(/*AUTOINST*/ 188 | // Outputs 189 | .txdat0 (txdat0[15:0]), 190 | .txdat1 (txdat1[15:0]), 191 | .txisk0 (txisk0[1:0]), 192 | .txisk1 (txisk1[1:0]), 193 | // Inputs 194 | .dpclk (dpclk), 195 | .phymode (phymode[1:0]), 196 | .scrdat0 (scrdat0[15:0]), 197 | .scrdat1 (scrdat1[15:0]), 198 | .scrisk0 (scrisk0[1:0]), 199 | .scrisk1 (scrisk1[1:0])); 200 | dport_gtp gtp_i( 201 | .refclkp(refclk), 202 | .tx0data(txdat0), 203 | .tx1data(txdat1), 204 | .tx0isk(txisk0), 205 | .tx1isk(txisk1), 206 | /*AUTOINST*/ 207 | // Outputs 208 | .dpclk (dpclk), 209 | .gtpready (gtpready), 210 | .tx (tx[3:0]), 211 | // Inputs 212 | .clk (clk), 213 | .prbssel (prbssel[2:0]), 214 | .speed (speed), 215 | .preemph0 (preemph0[1:0]), 216 | .swing0 (swing0[1:0]), 217 | .preemph1 (preemph1[1:0]), 218 | .swing1 (swing1[1:0])); 219 | 220 | wire auxi0; 221 | sync auxsync(clk, !auxi0, auxi); 222 | PULLUP p0(.O(auxp)); 223 | PULLDOWN p1(.O(auxn)); 224 | IOBUFDS #(.DIFF_TERM("false"), .IOSTANDARD("BLVDS_25")) io_1(.I(!auxo), .O(auxi0), .T(auxd), .IO(auxp), .IOB(auxn)); 225 | 226 | endmodule 227 | -------------------------------------------------------------------------------- /aijubrd/dport/dport.vh: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ps 2 | `default_nettype none 3 | 4 | `define ATTRMAX 273 5 | `define symBS 8'hbc 6 | `define symBE 8'hfb 7 | `define symSS 8'h5c 8 | `define symSE 8'hfd 9 | `define symFS 8'hfe 10 | `define symFE 8'hf7 11 | `define symSR 8'h1c 12 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_aux.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport_aux( 4 | input wire clk, 5 | 6 | input wire [31:0] auxctrl, 7 | output wire [31:0] auxstat, 8 | 9 | input wire [4:0] aux_addr, 10 | input wire [31:0] aux_wdata, 11 | input wire aux_req, 12 | input wire aux_wr, 13 | output reg aux_ack, 14 | output wire [31:0] aux_rdata, 15 | 16 | input wire auxi, 17 | output reg auxo, 18 | output reg auxd 19 | ); 20 | 21 | reg auxidle = 1'b1; 22 | wire [4:0] auxwlen = auxctrl[4:0]; 23 | wire auxgo = auxctrl[31] && auxidle; 24 | 25 | reg [4:0] auxrlen; 26 | reg auxdone; 27 | reg auxtimeout; 28 | 29 | assign auxstat = {auxidle, 22'b0, auxtimeout, 3'b0, auxrlen}; 30 | always @(posedge clk) begin 31 | auxidle <= auxidle && !auxgo || auxdone; 32 | end 33 | 34 | reg [7:0] mem[0:31]; 35 | 36 | wire memce0, memce1; 37 | wire memwr0, memwr1; 38 | wire [4:0] memaddr0, memaddr1; 39 | wire [7:0] memwdata0, memwdata1; 40 | reg [7:0] memrdata0, memrdata1; 41 | 42 | always @(posedge clk) begin 43 | if(memce0) begin 44 | if(memwr0) 45 | mem[memaddr0] <= memwdata0; 46 | else 47 | memrdata0 <= mem[memaddr0]; 48 | end 49 | end 50 | always @(posedge clk) begin 51 | if(memce1) begin 52 | if(memwr1) 53 | mem[memaddr1] <= memwdata1; 54 | else 55 | memrdata1 <= mem[memaddr1]; 56 | end 57 | end 58 | 59 | assign memce0 = aux_req; 60 | assign memwr0 = aux_wr; 61 | assign memaddr0 = aux_addr; 62 | assign memwdata0 = aux_wdata[{aux_addr[1:0], 3'b0} +: 8]; 63 | assign aux_rdata = {4{memrdata0}}; 64 | always @(posedge clk) 65 | aux_ack <= aux_req; 66 | 67 | localparam TIMEOUT = 40000; 68 | localparam CLKDIV = 100; 69 | reg [6:0] auxdiv; 70 | wire auxclk = auxdiv < CLKDIV/2; 71 | wire auxtick = auxdiv == CLKDIV-1; 72 | initial auxdiv = 0; 73 | always @(posedge clk) 74 | if(auxtick) 75 | auxdiv <= 0; 76 | else 77 | auxdiv <= auxdiv + 1; 78 | 79 | parameter NCO = 20; 80 | parameter SYSMHZ = 100; 81 | parameter MAXKHZ = 1500; 82 | parameter MINKHZ = 750; 83 | localparam [NCO-1:0] MAXFREQ = 4.0 * MAXKHZ * (1< MAXFREQ) fctr_ = MAXFREQ; 121 | end 122 | 2'b01: begin 123 | freq = fctr - alpha; 124 | fctr_ = fctr - beta; 125 | if(fctr_ < MINFREQ) fctr_ = MINFREQ; 126 | end 127 | endcase 128 | {carry, rxdiv_} = {1'b0, rxdiv} + {1'b0, freq}; 129 | end 130 | always @(posedge clk) begin 131 | rxclkup <= 0; 132 | rxclkdn <= 0; 133 | if(carry) begin 134 | rxclk <= !rxclk; 135 | if(rxclk) 136 | rxclkdn <= 1; 137 | else 138 | rxclkup <= 1; 139 | end 140 | end 141 | reg [7:0] rxd; 142 | reg rxdok; 143 | wire sync = rxd == 8'b11110000; 144 | always @(posedge clk) begin 145 | rxdok <= 0; 146 | if(rxclkup) begin 147 | rxd <= {rxd[6:0], auxi}; 148 | rxdok <= 1; 149 | end 150 | end 151 | 152 | reg [2:0] txstate, txstate_, rxstate; 153 | reg rxstart, clrctr, clridx, incidx, loadsr, loadsr0; 154 | reg [3:0] ctr; 155 | reg [4:0] idx; 156 | reg [7:0] sr; 157 | 158 | localparam IDLE = 0; 159 | localparam TXPREC = 1; 160 | localparam TXSYNC = 2; 161 | localparam TXDATA = 3; 162 | localparam TXEND = 4; 163 | localparam TXWAIT = 5; 164 | initial txstate = IDLE; 165 | reg auxgo0; 166 | always @(posedge clk) begin 167 | loadsr0 <= auxtick && loadsr; 168 | if(auxtick) begin 169 | txstate <= txstate_; 170 | ctr <= clrctr ? 0 : ctr + 1; 171 | sr <= {sr[6:0], 1'b0}; 172 | if(clridx) 173 | idx <= 0; 174 | if(incidx) 175 | idx <= idx + 1; 176 | auxgo0 <= 1'b0; 177 | end 178 | if(auxgo) 179 | auxgo0 <= 1'b1; 180 | if(loadsr0) 181 | sr <= memrdata1; 182 | end 183 | 184 | always @(*) begin 185 | txstate_ = txstate; 186 | clrctr = 0; 187 | clridx = 0; 188 | incidx = 0; 189 | loadsr = 0; 190 | auxo = 0; 191 | auxd = 1; 192 | rxstart = 0; 193 | case(txstate) 194 | IDLE: 195 | if(auxgo0) begin 196 | txstate_ = TXPREC; 197 | clrctr = 1; 198 | clridx = 1; 199 | end 200 | TXPREC: begin 201 | auxo = !auxclk; 202 | auxd = 0; 203 | if(ctr == 15) begin 204 | txstate_ = TXSYNC; 205 | clrctr = 1; 206 | end 207 | end 208 | TXSYNC: begin 209 | auxo = !ctr[1]; 210 | auxd = 0; 211 | if(ctr == 3) begin 212 | txstate_ = TXDATA; 213 | clrctr = 1; 214 | loadsr = 1; 215 | end 216 | end 217 | TXDATA: begin 218 | auxo = !(auxclk ^ sr[7]); 219 | auxd = 0; 220 | if(ctr == 7) begin 221 | loadsr = 1; 222 | incidx = 1; 223 | clrctr = 1; 224 | if(idx == auxwlen) 225 | txstate_ = TXEND; 226 | end 227 | end 228 | TXEND: begin 229 | auxo = !ctr[1]; 230 | auxd = 0; 231 | if(ctr == 3) begin 232 | clrctr = 1; 233 | txstate_ = TXWAIT; 234 | rxstart = 1; 235 | end 236 | end 237 | TXWAIT: 238 | if(rxstate == IDLE) 239 | txstate_ = IDLE; 240 | endcase 241 | end 242 | 243 | reg [3:0] inv, rxctr; 244 | initial rxstate = IDLE; 245 | reg [7:0] rxsr; 246 | reg [4:0] rxbctr; 247 | reg rxbyte; 248 | localparam RXDELAY = 1; 249 | localparam RXWAIT = 2; 250 | localparam RXDATA = 3; 251 | localparam RXPARK = 4; 252 | reg [15:0] rxtimer; 253 | 254 | always @(posedge clk) begin 255 | auxdone <= 0; 256 | rxbyte <= 0; 257 | if(rxdok) 258 | rxctr <= sync ? 0 : rxctr + 1; 259 | case(rxstate) 260 | IDLE: 261 | if(rxstart) begin 262 | rxstate <= RXDELAY; 263 | rxbctr <= 0; 264 | end 265 | RXDELAY: 266 | if(rxdok) begin 267 | rxbctr <= rxbctr + 1; 268 | if(rxbctr == 7) begin 269 | rxtimer <= TIMEOUT; 270 | rxstate <= RXWAIT; 271 | end 272 | end 273 | RXWAIT: 274 | if(rxtimer == 0) begin 275 | rxstate <= IDLE; 276 | auxdone <= 1; 277 | auxtimeout <= 1; 278 | end else begin 279 | rxtimer <= rxtimer - 1; 280 | if(rxdok && sync) begin 281 | rxstate <= RXDATA; 282 | inv <= 0; 283 | rxbctr <= 0; 284 | end 285 | end 286 | RXDATA: 287 | if(rxdok) begin 288 | if(rxctr[0]) begin 289 | rxsr <= {rxsr[6:0], rxd[1]}; 290 | if(rxd[0] == rxd[1]) 291 | inv <= inv + 1; 292 | end 293 | if(rxctr == 15) 294 | rxbyte <= 1; 295 | if(sync) begin 296 | rxstate <= RXPARK; 297 | auxrlen <= rxbctr; 298 | auxdone <= 1; 299 | auxtimeout <= 0; 300 | end 301 | end 302 | RXPARK: 303 | if(rxdok && rxctr == 15) 304 | rxstate <= IDLE; 305 | endcase 306 | if(rxbyte) 307 | rxbctr <= rxbctr + 1; 308 | end 309 | 310 | assign memce1 = rxbyte || auxtick && loadsr; 311 | assign memwr1 = rxbyte; 312 | assign memaddr1 = rxbyte ? rxbctr : incidx ? idx + 1 : idx; 313 | assign memwdata1 = rxsr; 314 | 315 | endmodule 316 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_gtp.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport_gtp( 4 | input wire clk, 5 | input wire [1:0] refclkp, 6 | output wire dpclk, 7 | output reg gtpready, 8 | input wire [2:0] prbssel, 9 | input wire [15:0] tx0data, 10 | input wire [15:0] tx1data, 11 | input wire [1:0] tx0isk, 12 | input wire [1:0] tx1isk, 13 | output wire [3:0] tx, 14 | input wire speed, 15 | input wire [1:0] preemph0, 16 | input wire [1:0] swing0, 17 | input wire [1:0] preemph1, 18 | input wire [1:0] swing1 19 | 20 | ); 21 | 22 | reg pllreset, txreset; 23 | wire pll0lock, pll0locks; 24 | wire pll0clk, pll0refclk, pll1clk, pll1refclk; 25 | wire tx0resetdone, tx1resetdone, tx0resetdones, tx1resetdones; 26 | wire tx0outclk, tx1outclk; 27 | wire refclk; 28 | wire speed0; 29 | sync speedsync(clk, speed, speed0); 30 | reg speed1, drpen; 31 | reg [15:0] drpdi; 32 | wire [4:0] postcursor0 = preemph0 == 3 ? 26 : preemph0 == 2 ? 20 : preemph0 == 1 ? 14 : 0; 33 | wire [3:0] diffctrl0 = swing0 == 3 ? 13 : swing0 == 2 ? 9 : swing0 == 1 ? 6 : 3; 34 | wire [4:0] postcursor1 = preemph1 == 3 ? 26 : preemph1 == 2 ? 20 : preemph1 == 1 ? 14 : 0; 35 | wire [3:0] diffctrl1 = swing1 == 3 ? 13 : swing1 == 2 ? 9 : swing1 == 1 ? 6 : 3; 36 | 37 | always @(posedge clk) begin 38 | speed1 <= speed0; 39 | drpen <= speed1 != speed0; 40 | drpdi <= {10'b0010000000, speed0 ? 6'd3 : 6'd1}; 41 | end 42 | 43 | gtpchan tx0(clk, txreset, tx0resetdone, prbssel, tx0data, tx0isk, tx0outclk, dpclk, pll0clk, pll1clk, pll0refclk, pll1refclk, tx[0], tx[1], postcursor0, diffctrl0); 44 | gtpchan tx1(clk, txreset, tx1resetdone, prbssel, tx1data, tx1isk, tx1outclk, dpclk, pll0clk, pll1clk, pll0refclk, pll1refclk, tx[2], tx[3], postcursor1, diffctrl1); 45 | BUFG bufg(.I(tx0outclk), .O(dpclk)); 46 | IBUFDS_GTE2 refclkbuf(.CEB(0), .I(refclkp[0]), .IB(refclkp[1]), .O(refclk)); 47 | 48 | GTPE2_COMMON # 49 | ( 50 | // Simulation attributes 51 | .SIM_RESET_SPEEDUP ("false"), 52 | .SIM_PLL0REFCLK_SEL (3'b001), 53 | .SIM_PLL1REFCLK_SEL (3'b001), 54 | .SIM_VERSION ( "2.0"), 55 | 56 | .PLL0_FBDIV (3), 57 | .PLL0_FBDIV_45 (4), 58 | .PLL0_REFCLK_DIV (1), 59 | .PLL1_FBDIV (1), 60 | .PLL1_FBDIV_45 (4), 61 | .PLL1_REFCLK_DIV (1), 62 | 63 | //----------------COMMON BLOCK Attributes--------------- 64 | .BIAS_CFG (64'h0000000000050001), 65 | .COMMON_CFG (32'h00000000), 66 | 67 | //--------------------------PLL Attributes---------------------------- 68 | .PLL0_CFG (27'h01F03DC), 69 | .PLL0_DMON_CFG (1'b0), 70 | .PLL0_INIT_CFG (24'h00001E), 71 | .PLL0_LOCK_CFG (9'h1E8), 72 | .PLL1_CFG (27'h01F03DC), 73 | .PLL1_DMON_CFG (1'b0), 74 | .PLL1_INIT_CFG (24'h00001E), 75 | .PLL1_LOCK_CFG (9'h1E8), 76 | .PLL_CLKOUT_CFG (8'h00), 77 | 78 | //--------------------------Reserved Attributes---------------------------- 79 | .RSVD_ATTR0 (16'h0000), 80 | .RSVD_ATTR1 (16'h0000) 81 | 82 | ) 83 | gtpe2_common_i 84 | ( 85 | .GTREFCLK1 (refclk), 86 | .PLL0OUTCLK (pll0clk), 87 | .PLL0OUTREFCLK (pll0refclk), 88 | .PLL1OUTCLK (pll1clk), 89 | .PLL1OUTREFCLK (pll1refclk), 90 | .PLL0LOCK (pll0lock), 91 | .PLL0LOCKDETCLK (clk), 92 | .PLL0LOCKEN (1), 93 | .PLL0REFCLKSEL (3'b001), 94 | .PLL0RESET (pllreset), 95 | .PLL1LOCKEN (1), 96 | .PLL1REFCLKSEL (3'b001), 97 | .BGRCALOVRDENB (1), 98 | .BGBYPASSB (1), 99 | .BGMONITORENB (1), 100 | .BGPDB (1), 101 | .BGRCALOVRD (5'b11111), 102 | .RCALENB (1), 103 | .DRPCLK (clk), 104 | .DRPADDR (4), 105 | .DRPEN (drpen), 106 | .DRPWE (1), 107 | .DRPDI (drpdi) 108 | ); 109 | 110 | reg [2:0] state; 111 | reg [7:0] ctr; 112 | 113 | sync pll0locks_i(clk, pll0lock, pll0locks); 114 | sync txresetdone0s_i(clk, tx0resetdone, tx0resetdones); 115 | sync txresetdone1s_i(clk, tx1resetdone, tx1resetdones); 116 | 117 | initial state = 0; 118 | initial gtpready = 0; 119 | always @(posedge clk) begin 120 | case(state) 121 | 0: begin 122 | pllreset <= 1; 123 | txreset <= 1; 124 | ctr <= 0; 125 | state <= 1; 126 | end 127 | 1: begin 128 | ctr <= ctr + 1; 129 | if(ctr == 255) begin 130 | pllreset <= 0; 131 | state <= 2; 132 | end 133 | end 134 | 2: 135 | if(pll0locks) begin 136 | state <= 3; 137 | ctr <= 0; 138 | end 139 | 3: begin 140 | ctr <= ctr + 1; 141 | if(ctr == 255) begin 142 | txreset <= 0; 143 | state <= 4; 144 | end 145 | end 146 | 4: 147 | if(tx0resetdones && tx1resetdones) begin 148 | gtpready <= 1; 149 | state <= 5; 150 | end 151 | endcase 152 | if(speed0 != speed1) 153 | state <= 0; 154 | end 155 | 156 | endmodule 157 | 158 | module gtpchan( 159 | input wire clk, 160 | input wire txreset, 161 | output wire txresetdone, 162 | input wire [2:0] prbssel, 163 | input wire [15:0] txdata, 164 | input wire [1:0] txisk, 165 | output wire txoutclk, 166 | input wire dpclk, 167 | input wire pll0clk, 168 | input wire pll1clk, 169 | input wire pll0refclk, 170 | input wire pll1refclk, 171 | output wire txp, 172 | output wire txn, 173 | input wire [4:0] postcursor, 174 | input wire [3:0] diffctrl 175 | ); 176 | 177 | GTPE2_CHANNEL # 178 | ( 179 | //_______________________ Simulation-Only Attributes __________________ 180 | 181 | .SIM_RECEIVER_DETECT_PASS ("TRUE"), 182 | .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), 183 | .SIM_RESET_SPEEDUP ("FALSE"), 184 | .SIM_VERSION ("2.0"), 185 | 186 | 187 | //----------------RX Byte and Word Alignment Attributes--------------- 188 | .ALIGN_COMMA_DOUBLE ("FALSE"), 189 | .ALIGN_COMMA_ENABLE (10'b1111111111), 190 | .ALIGN_COMMA_WORD (1), 191 | .ALIGN_MCOMMA_DET ("TRUE"), 192 | .ALIGN_MCOMMA_VALUE (10'b1010000011), 193 | .ALIGN_PCOMMA_DET ("TRUE"), 194 | .ALIGN_PCOMMA_VALUE (10'b0101111100), 195 | .SHOW_REALIGN_COMMA ("TRUE"), 196 | .RXSLIDE_AUTO_WAIT (7), 197 | .RXSLIDE_MODE ("OFF"), 198 | .RX_SIG_VALID_DLY (10), 199 | 200 | //----------------RX 8B/10B Decoder Attributes--------------- 201 | .RX_DISPERR_SEQ_MATCH ("TRUE"), 202 | .DEC_MCOMMA_DETECT ("FALSE"), 203 | .DEC_PCOMMA_DETECT ("FALSE"), 204 | .DEC_VALID_COMMA_ONLY ("FALSE"), 205 | 206 | //----------------------RX Clock Correction Attributes---------------------- 207 | .CBCC_DATA_SOURCE_SEL ("ENCODED"), 208 | .CLK_COR_SEQ_2_USE ("FALSE"), 209 | .CLK_COR_KEEP_IDLE ("FALSE"), 210 | .CLK_COR_MAX_LAT (9), 211 | .CLK_COR_MIN_LAT (7), 212 | .CLK_COR_PRECEDENCE ("TRUE"), 213 | .CLK_COR_REPEAT_WAIT (0), 214 | .CLK_COR_SEQ_LEN (1), 215 | .CLK_COR_SEQ_1_ENABLE (4'b1111), 216 | .CLK_COR_SEQ_1_1 (10'b0100000000), 217 | .CLK_COR_SEQ_1_2 (10'b0000000000), 218 | .CLK_COR_SEQ_1_3 (10'b0000000000), 219 | .CLK_COR_SEQ_1_4 (10'b0000000000), 220 | .CLK_CORRECT_USE ("FALSE"), 221 | .CLK_COR_SEQ_2_ENABLE (4'b1111), 222 | .CLK_COR_SEQ_2_1 (10'b0100000000), 223 | .CLK_COR_SEQ_2_2 (10'b0000000000), 224 | .CLK_COR_SEQ_2_3 (10'b0000000000), 225 | .CLK_COR_SEQ_2_4 (10'b0000000000), 226 | 227 | //----------------------RX Channel Bonding Attributes---------------------- 228 | .CHAN_BOND_KEEP_ALIGN ("FALSE"), 229 | .CHAN_BOND_MAX_SKEW (1), 230 | .CHAN_BOND_SEQ_LEN (1), 231 | .CHAN_BOND_SEQ_1_1 (10'b0000000000), 232 | .CHAN_BOND_SEQ_1_2 (10'b0000000000), 233 | .CHAN_BOND_SEQ_1_3 (10'b0000000000), 234 | .CHAN_BOND_SEQ_1_4 (10'b0000000000), 235 | .CHAN_BOND_SEQ_1_ENABLE (4'b1111), 236 | .CHAN_BOND_SEQ_2_1 (10'b0000000000), 237 | .CHAN_BOND_SEQ_2_2 (10'b0000000000), 238 | .CHAN_BOND_SEQ_2_3 (10'b0000000000), 239 | .CHAN_BOND_SEQ_2_4 (10'b0000000000), 240 | .CHAN_BOND_SEQ_2_ENABLE (4'b1111), 241 | .CHAN_BOND_SEQ_2_USE ("FALSE"), 242 | .FTS_DESKEW_SEQ_ENABLE (4'b1111), 243 | .FTS_LANE_DESKEW_CFG (4'b1111), 244 | .FTS_LANE_DESKEW_EN ("FALSE"), 245 | 246 | //-------------------------RX Margin Analysis Attributes---------------------------- 247 | .ES_CONTROL (6'b000000), 248 | .ES_ERRDET_EN ("FALSE"), 249 | .ES_EYE_SCAN_EN ("FALSE"), 250 | .ES_HORZ_OFFSET (12'h010), 251 | .ES_PMA_CFG (10'b0000000000), 252 | .ES_PRESCALE (5'b00000), 253 | .ES_QUALIFIER (80'h00000000000000000000), 254 | .ES_QUAL_MASK (80'h00000000000000000000), 255 | .ES_SDATA_MASK (80'h00000000000000000000), 256 | .ES_VERT_OFFSET (9'b000000000), 257 | 258 | //-----------------------FPGA RX Interface Attributes------------------------- 259 | .RX_DATA_WIDTH (20), 260 | 261 | //-------------------------PMA Attributes---------------------------- 262 | .OUTREFCLK_SEL_INV (2'b11), 263 | .PMA_RSV (32'h00000333), 264 | .PMA_RSV2 (32'h00002040), 265 | .PMA_RSV3 (2'b00), 266 | .PMA_RSV4 (4'b0000), 267 | .RX_BIAS_CFG (16'b0000111100110011), 268 | .DMONITOR_CFG (24'h000A00), 269 | .RX_CM_SEL (2'b01), 270 | .RX_CM_TRIM (4'b0000), 271 | .RX_DEBUG_CFG (14'b00000000000000), 272 | .RX_OS_CFG (13'b0000010000000), 273 | .TERM_RCAL_CFG (15'b100001000010000), 274 | .TERM_RCAL_OVRD (3'b000), 275 | .TST_RSV (32'h00000000), 276 | .RX_CLK25_DIV (6), 277 | .TX_CLK25_DIV (6), 278 | .UCODEER_CLR (1'b0), 279 | 280 | //-------------------------PCI Express Attributes---------------------------- 281 | .PCS_PCIE_EN ("FALSE"), 282 | 283 | //-------------------------PCS Attributes---------------------------- 284 | .PCS_RSVD_ATTR (48'h000000000000), 285 | 286 | //-----------RX Buffer Attributes------------ 287 | .RXBUF_ADDR_MODE ("FAST"), 288 | .RXBUF_EIDLE_HI_CNT (4'b1000), 289 | .RXBUF_EIDLE_LO_CNT (4'b0000), 290 | .RXBUF_EN ("TRUE"), 291 | .RX_BUFFER_CFG (6'b000000), 292 | .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), 293 | .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), 294 | .RXBUF_RESET_ON_EIDLE ("FALSE"), 295 | .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), 296 | .RXBUFRESET_TIME (5'b00001), 297 | .RXBUF_THRESH_OVFLW (61), 298 | .RXBUF_THRESH_OVRD ("FALSE"), 299 | .RXBUF_THRESH_UNDFLW (4), 300 | .RXDLY_CFG (16'h001F), 301 | .RXDLY_LCFG (9'h030), 302 | .RXDLY_TAP_CFG (16'h0000), 303 | .RXPH_CFG (24'hC00002), 304 | .RXPHDLY_CFG (24'h084020), 305 | .RXPH_MONITOR_SEL (5'b00000), 306 | .RX_XCLK_SEL ("RXREC"), 307 | .RX_DDI_SEL (6'b000000), 308 | .RX_DEFER_RESET_BUF_EN ("TRUE"), 309 | 310 | //---------------------CDR Attributes------------------------- 311 | 312 | //For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008 313 | 314 | //For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010 315 | .RXCDR_CFG (83'h0001107FE206021081010), 316 | .RXCDR_FR_RESET_ON_EIDLE (1'b0), 317 | .RXCDR_HOLD_DURING_EIDLE (1'b0), 318 | .RXCDR_PH_RESET_ON_EIDLE (1'b0), 319 | .RXCDR_LOCK_CFG (6'b001001), 320 | 321 | //-----------------RX Initialization and Reset Attributes------------------- 322 | .RXCDRFREQRESET_TIME (5'b00001), 323 | .RXCDRPHRESET_TIME (5'b00001), 324 | .RXISCANRESET_TIME (5'b00001), 325 | .RXPCSRESET_TIME (5'b00001), 326 | .RXPMARESET_TIME (5'b00011), 327 | 328 | //-----------------RX OOB Signaling Attributes------------------- 329 | .RXOOB_CFG (7'b0000110), 330 | 331 | //-----------------------RX Gearbox Attributes--------------------------- 332 | .RXGEARBOX_EN ("FALSE"), 333 | .GEARBOX_MODE (3'b000), 334 | 335 | //-----------------------PRBS Detection Attribute----------------------- 336 | .RXPRBS_ERR_LOOPBACK (1'b0), 337 | 338 | //-----------Power-Down Attributes---------- 339 | .PD_TRANS_TIME_FROM_P2 (12'h03c), 340 | .PD_TRANS_TIME_NONE_P2 (8'h3c), 341 | .PD_TRANS_TIME_TO_P2 (8'h64), 342 | 343 | //-----------RX OOB Signaling Attributes---------- 344 | .SAS_MAX_COM (64), 345 | .SAS_MIN_COM (36), 346 | .SATA_BURST_SEQ_LEN (4'b1111), 347 | .SATA_BURST_VAL (3'b100), 348 | .SATA_EIDLE_VAL (3'b100), 349 | .SATA_MAX_BURST (8), 350 | .SATA_MAX_INIT (21), 351 | .SATA_MAX_WAKE (7), 352 | .SATA_MIN_BURST (4), 353 | .SATA_MIN_INIT (12), 354 | .SATA_MIN_WAKE (4), 355 | 356 | //-----------RX Fabric Clock Output Control Attributes---------- 357 | .TRANS_TIME_RATE (8'h0E), 358 | 359 | //------------TX Buffer Attributes---------------- 360 | .TXBUF_EN ("TRUE"), 361 | .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), 362 | .TXDLY_CFG (16'h001F), 363 | .TXDLY_LCFG (9'h030), 364 | .TXDLY_TAP_CFG (16'h0000), 365 | .TXPH_CFG (16'h0780), 366 | .TXPHDLY_CFG (24'h084020), 367 | .TXPH_MONITOR_SEL (5'b00000), 368 | .TX_XCLK_SEL ("TXOUT"), 369 | 370 | //-----------------------FPGA TX Interface Attributes------------------------- 371 | .TX_DATA_WIDTH (20), 372 | 373 | //-----------------------TX Configurable Driver Attributes------------------------- 374 | .TX_DEEMPH0 (6'b000000), 375 | .TX_DEEMPH1 (6'b000000), 376 | .TX_EIDLE_ASSERT_DELAY (3'b110), 377 | .TX_EIDLE_DEASSERT_DELAY (3'b100), 378 | .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), 379 | .TX_MAINCURSOR_SEL (1'b0), 380 | .TX_DRIVE_MODE ("DIRECT"), 381 | .TX_MARGIN_FULL_0 (7'b1001110), 382 | .TX_MARGIN_FULL_1 (7'b1001001), 383 | .TX_MARGIN_FULL_2 (7'b1000101), 384 | .TX_MARGIN_FULL_3 (7'b1000010), 385 | .TX_MARGIN_FULL_4 (7'b1000000), 386 | .TX_MARGIN_LOW_0 (7'b1000110), 387 | .TX_MARGIN_LOW_1 (7'b1000100), 388 | .TX_MARGIN_LOW_2 (7'b1000010), 389 | .TX_MARGIN_LOW_3 (7'b1000000), 390 | .TX_MARGIN_LOW_4 (7'b1000000), 391 | 392 | //-----------------------TX Gearbox Attributes-------------------------- 393 | .TXGEARBOX_EN ("FALSE"), 394 | 395 | //-----------------------TX Initialization and Reset Attributes-------------------------- 396 | .TXPCSRESET_TIME (5'b00001), 397 | .TXPMARESET_TIME (5'b00001), 398 | 399 | //-----------------------TX Receiver Detection Attributes-------------------------- 400 | .TX_RXDETECT_CFG (14'h1832), 401 | .TX_RXDETECT_REF (3'b100), 402 | 403 | //---------------- JTAG Attributes --------------- 404 | .ACJTAG_DEBUG_MODE (1'b0), 405 | .ACJTAG_MODE (1'b0), 406 | .ACJTAG_RESET (1'b0), 407 | 408 | //---------------- CDR Attributes --------------- 409 | .CFOK_CFG (43'h49000040E80), 410 | .CFOK_CFG2 (7'b0100000), 411 | .CFOK_CFG3 (7'b0100000), 412 | .CFOK_CFG4 (1'b0), 413 | .CFOK_CFG5 (2'h0), 414 | .CFOK_CFG6 (4'b0000), 415 | .RXOSCALRESET_TIME (5'b00011), 416 | .RXOSCALRESET_TIMEOUT (5'b00000), 417 | 418 | //---------------- PMA Attributes --------------- 419 | .CLK_COMMON_SWING (1'b0), 420 | .RX_CLKMUX_EN (1'b1), 421 | .TX_CLKMUX_EN (1'b1), 422 | .ES_CLK_PHASE_SEL (1'b0), 423 | .USE_PCS_CLK_PHASE_SEL (1'b0), 424 | .PMA_RSV6 (1'b0), 425 | .PMA_RSV7 (1'b0), 426 | 427 | //---------------- TX Configuration Driver Attributes --------------- 428 | .TX_PREDRIVER_MODE (1'b0), 429 | .PMA_RSV5 (1'b0), 430 | .SATA_PLL_CFG ("VCO_3000MHZ"), 431 | 432 | //---------------- RX Fabric Clock Output Control Attributes --------------- 433 | .RXOUT_DIV (2), 434 | 435 | //---------------- TX Fabric Clock Output Control Attributes --------------- 436 | .TXOUT_DIV (2), 437 | 438 | //---------------- RX Phase Interpolator Attributes--------------- 439 | .RXPI_CFG0 (3'b000), 440 | .RXPI_CFG1 (1'b1), 441 | .RXPI_CFG2 (1'b1), 442 | 443 | //------------RX Equalizer Attributes------------- 444 | .ADAPT_CFG0 (20'h00000), 445 | .RXLPMRESET_TIME (7'b0001111), 446 | .RXLPM_BIAS_STARTUP_DISABLE (1'b0), 447 | .RXLPM_CFG (4'b0110), 448 | .RXLPM_CFG1 (1'b0), 449 | .RXLPM_CM_CFG (1'b0), 450 | .RXLPM_GC_CFG (9'b111100010), 451 | .RXLPM_GC_CFG2 (3'b001), 452 | .RXLPM_HF_CFG (14'b00001111110000), 453 | .RXLPM_HF_CFG2 (5'b01010), 454 | .RXLPM_HF_CFG3 (4'b0000), 455 | .RXLPM_HOLD_DURING_EIDLE (1'b0), 456 | .RXLPM_INCM_CFG (1'b0), 457 | .RXLPM_IPCM_CFG (1'b1), 458 | .RXLPM_LF_CFG (18'b000000001111110000), 459 | .RXLPM_LF_CFG2 (5'b01010), 460 | .RXLPM_OSINT_CFG (3'b100), 461 | 462 | //---------------- TX Phase Interpolator PPM Controller Attributes--------------- 463 | .TXPI_CFG0 (2'b00), 464 | .TXPI_CFG1 (2'b00), 465 | .TXPI_CFG2 (2'b00), 466 | .TXPI_CFG3 (1'b0), 467 | .TXPI_CFG4 (1'b0), 468 | .TXPI_CFG5 (3'b000), 469 | .TXPI_GREY_SEL (1'b0), 470 | .TXPI_INVSTROBE_SEL (1'b0), 471 | .TXPI_PPMCLK_SEL ("TXUSRCLK2"), 472 | .TXPI_PPM_CFG (8'h00), 473 | .TXPI_SYNFREQ_PPM (3'b000), 474 | 475 | //---------------- LOOPBACK Attributes--------------- 476 | .LOOPBACK_CFG (1'b0), 477 | .PMA_LOOPBACK_CFG (1'b0), 478 | 479 | //----------------RX OOB Signalling Attributes--------------- 480 | .RXOOB_CLK_CFG ("PMA"), 481 | 482 | //----------------TX OOB Signalling Attributes--------------- 483 | .TXOOB_CFG (1'b0), 484 | 485 | //----------------RX Buffer Attributes--------------- 486 | .RXSYNC_MULTILANE (1'b1), 487 | .RXSYNC_OVRD (1'b0), 488 | .RXSYNC_SKIP_DA (1'b0), 489 | 490 | //----------------TX Buffer Attributes--------------- 491 | .TXSYNC_MULTILANE (0), 492 | .TXSYNC_OVRD (0), 493 | .TXSYNC_SKIP_DA (1'b0) 494 | 495 | 496 | ) 497 | gtpe2_i 498 | ( 499 | 500 | .TSTIN (20'b11111111111111111111), 501 | .DRPCLK (clk), 502 | 503 | .RXSYSCLKSEL (2'b11), 504 | 505 | .TX8B10BEN (1), 506 | 507 | .PLL0CLK (pll0clk), 508 | .PLL0REFCLK (pll0refclk), 509 | .PLL1CLK (pll1clk), 510 | .PLL1REFCLK (pll1refclk), 511 | 512 | .RXPD (2'b11), 513 | 514 | .GTRXRESET (txreset), 515 | .RXLPMRESET (txreset), 516 | .GTTXRESET (txreset), 517 | .TXUSERRDY (1), 518 | 519 | .TXDATA (txdata), 520 | .TXUSRCLK (dpclk), 521 | .TXUSRCLK2 (dpclk), 522 | 523 | .TXCHARISK (txisk), 524 | .TXDLYBYPASS (1), 525 | 526 | .GTPTXN (txn), 527 | .GTPTXP (txp), 528 | .TXBUFDIFFCTRL (3'b100), 529 | .TXDIFFCTRL (diffctrl), 530 | .TXOUTCLK (txoutclk), 531 | .TXOUTCLKSEL (3'b010), 532 | .TXPOSTCURSOR (postcursor), 533 | 534 | .TXRESETDONE (txresetdone), 535 | .TXPRBSSEL (prbssel), 536 | .TXPOLARITY (1), 537 | .TXPIPPMSEL (1) 538 | 539 | ); 540 | 541 | 542 | endmodule 543 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_phy.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport_phy( 4 | input wire dpclk, 5 | input wire [1:0] phymode, 6 | input wire [15:0] scrdat0, 7 | input wire [15:0] scrdat1, 8 | input wire [1:0] scrisk0, 9 | input wire [1:0] scrisk1, 10 | output reg [15:0] txdat0, 11 | output reg [15:0] txdat1, 12 | output reg [1:0] txisk0, 13 | output reg [1:0] txisk1 14 | ); 15 | 16 | reg [2:0] ctr; 17 | reg [15:0] txdat1_0, txdat0_, txdat1_; 18 | reg [1:0] txisk1_0, txisk0_, txisk1_; 19 | always @(posedge dpclk) begin 20 | txdat0 <= txdat0_; 21 | txisk0 <= txisk0_; 22 | txdat1 <= txdat1_0; 23 | txisk1 <= txisk1_0; 24 | txdat1_0 <= txdat1_; 25 | txisk1_0 <= txisk1_; 26 | if(ctr == 4) 27 | ctr <= 0; 28 | else 29 | ctr <= ctr + 1; 30 | end 31 | 32 | always @(*) begin 33 | txdat0_ = 0; 34 | txdat1_ = 0; 35 | txisk0_ = 0; 36 | txisk1_ = 0; 37 | case(phymode) 38 | 1: begin 39 | txdat0_ = scrdat0; 40 | txdat1_ = scrdat1; 41 | txisk0_ = scrisk0; 42 | txisk1_ = scrisk1; 43 | end 44 | 2: begin 45 | txdat0_ = 16'h4A4A; 46 | txdat1_ = 16'h4A4A; 47 | end 48 | 3: begin 49 | case(ctr) 50 | 0, 1: begin 51 | txdat0_ = 16'hcbbc; 52 | txisk0_ = 2'b01; 53 | end 54 | 2, 3, 4: txdat0_ = 16'h4a4a; 55 | endcase 56 | txdat1_ = txdat0_; 57 | txisk1_ = txisk0_; 58 | end 59 | endcase 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_pxclk.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport_pxclk( 4 | input wire dpclk, 5 | input wire [`ATTRMAX:0] attr, 6 | input wire speed, 7 | input wire reset, 8 | output reg dphstart, 9 | output reg dpvstart, 10 | output reg dmastart, 11 | output reg dpvblank, 12 | output reg dpdmahstart 13 | ); 14 | 15 | wire [15:0] vact = attr[15:0]; 16 | wire [15:0] hact = attr[31:16]; 17 | wire [15:0] vtot = attr[47:32]; 18 | wire [15:0] htot = attr[63:48]; 19 | wire [15:0] vsync = attr[79:64]; 20 | wire [15:0] hsync = attr[95:80]; 21 | wire [15:0] vdata = attr[111:96]; 22 | wire [15:0] hdata = attr[127:112]; 23 | wire [15:0] misc = attr[143:128]; 24 | wire [23:0] Mvid = speed ? attr[232:209] : attr[167:144]; 25 | wire [23:0] Nvid = speed ? attr[256:233] : attr[191:168]; 26 | wire [16:0] sclkinc = speed ? attr[273:257] : attr[208:192]; 27 | 28 | reg [30:0] pxctr; 29 | reg [15:0] yctr; 30 | always @(posedge dpclk) begin 31 | dpvstart <= 0; 32 | dpdmahstart <= 0; 33 | dpvblank <= 0; 34 | dmastart <= 0; 35 | if(pxctr[30:15] >= htot) begin 36 | pxctr <= pxctr - {htot, 15'd0} + {15'd0, sclkinc}; 37 | dphstart <= 1; 38 | dpvstart <= yctr == 0; 39 | dpdmahstart <= yctr < vact; 40 | if(yctr == vtot) begin 41 | yctr <= 0; 42 | end else 43 | yctr <= yctr + 1; 44 | if(yctr == vact) 45 | dpvblank <= 1'b1; 46 | end else begin 47 | pxctr <= pxctr + {15'd0, sclkinc}; 48 | dphstart <= 0; 49 | end 50 | if(reset) begin 51 | pxctr <= 0; 52 | yctr <= 0; 53 | dphstart <= 0; 54 | dpvstart <= 0; 55 | dpdmahstart <= 0; 56 | dpvblank <= 0; 57 | end 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_pxconv.v: -------------------------------------------------------------------------------- 1 | module dport_pxconv( 2 | input wire dpclk, 3 | input wire reset, 4 | 5 | input wire raw_pixel_valid, 6 | input wire [15:0] raw_pixel_data, 7 | output wire raw_pixel_ready, 8 | 9 | output reg dp_pixel_valid, 10 | output reg [47:0] dp_pixel_data, 11 | input wire dp_pixel_ready, 12 | 13 | input wire dpdmahstart 14 | ); 15 | 16 | localparam PAD = 240; 17 | localparam BLITH = 800; 18 | localparam TOTH = BLITH + 2 * PAD; 19 | 20 | localparam [24:0] BRIGHT = 24'h00_F0_00; 21 | localparam [24:0] DARK = 24'h00_21_00; 22 | localparam [24:0] PADCOL = 24'h00_00_00; 23 | 24 | reg [15:0] sr; 25 | reg sr_valid; 26 | reg [4:0] sr_ctr; 27 | wire sr_ready; 28 | assign raw_pixel_ready = (sr_ctr == 0 || sr_ready && sr_ctr <= 1) || reset; 29 | always @(posedge dpclk) begin 30 | if(sr_valid && sr_ready) begin 31 | sr <= sr << 2; 32 | sr_ctr <= sr_ctr - 1; 33 | if(sr_ctr == 1) 34 | sr_valid <= 1'b0; 35 | end 36 | if(raw_pixel_valid && raw_pixel_ready) begin 37 | sr <= raw_pixel_data; 38 | sr_valid <= 1'b1; 39 | sr_ctr <= 8; 40 | end 41 | if(reset) begin 42 | sr_valid <= 1'b0; 43 | sr_ctr <= 0; 44 | end 45 | end 46 | wire [47:0] sr_data = {sr[14] ? BRIGHT : DARK, sr[15] ? BRIGHT : DARK}; 47 | 48 | reg active; 49 | reg [15:0] x; 50 | 51 | assign sr_ready = (!dp_pixel_valid || dp_pixel_ready) && (x >= PAD && x < PAD + BLITH); 52 | always @(posedge dpclk) begin 53 | if(dp_pixel_valid && dp_pixel_ready) 54 | dp_pixel_valid <= 1'b0; 55 | if(dpdmahstart) begin 56 | active <= 1'b1; 57 | x <= 0; 58 | end 59 | if(active && (!dp_pixel_valid || dp_pixel_ready)) begin 60 | if(x < PAD) begin 61 | dp_pixel_valid <= 1'b1; 62 | dp_pixel_data <= {2{PADCOL}}; 63 | x <= x + 2; 64 | end else if(x < PAD + BLITH) begin 65 | if(sr_valid) begin 66 | dp_pixel_valid <= 1'b1; 67 | dp_pixel_data <= sr_data; 68 | x <= x + 2; 69 | end 70 | end else begin 71 | dp_pixel_valid <= 1'b1; 72 | dp_pixel_data <= {2{PADCOL}}; 73 | if(x == TOTH - 2) begin 74 | x <= 0; 75 | active <= 1'b0; 76 | end else 77 | x <= x + 2; 78 | end 79 | end 80 | if(reset) begin 81 | dp_pixel_valid <= 1'b0; 82 | x <= 0; 83 | active <= 1'b0; 84 | end 85 | end 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_pxconv_tb.v: -------------------------------------------------------------------------------- 1 | module dport_pxconv_tb; 2 | 3 | /*AUTOWIRE*/ 4 | // Beginning of automatic wires (for undeclared instantiated-module outputs) 5 | wire [17:0] dma_addr; // From blit_disp_i of blit_disp.v 6 | wire dma_req; // From blit_disp_i of blit_disp.v 7 | wire dmastart; // From dport_pxclk_i of dport_pxclk.v 8 | wire [47:0] dp_pixel_data; // From dport_pxconv_i of dport_pxconv.v 9 | wire dp_pixel_ready; // From dport_stuff_i of dport_stuff.v 10 | wire dp_pixel_valid; // From dport_pxconv_i of dport_pxconv.v 11 | wire [15:0] dpdat0; // From dport_stuff_i of dport_stuff.v 12 | wire [15:0] dpdat1; // From dport_stuff_i of dport_stuff.v 13 | wire dpdmahstart; // From dport_pxclk_i of dport_pxclk.v 14 | wire dphstart; // From dport_pxclk_i of dport_pxclk.v 15 | wire [1:0] dpisk0; // From dport_stuff_i of dport_stuff.v 16 | wire [1:0] dpisk1; // From dport_stuff_i of dport_stuff.v 17 | wire dpvblank; // From dport_pxclk_i of dport_pxclk.v 18 | wire dpvstart; // From dport_pxclk_i of dport_pxclk.v 19 | wire [15:0] pixel_data; // From blit_disp_i of blit_disp.v 20 | wire pixel_valid; // From blit_disp_i of blit_disp.v 21 | wire [15:0] raw_pixel_data; // From fifo_i of fifo.v 22 | wire raw_pixel_ready; // From dport_pxconv_i of dport_pxconv.v 23 | wire raw_pixel_valid; // From fifo_i of fifo.v 24 | // End of automatics 25 | /*AUTOREGINPUT*/ 26 | // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) 27 | reg [17:0] daddr; // To blit_disp_i of blit_disp.v 28 | reg dma_ack; // To blit_disp_i of blit_disp.v 29 | reg [15:0] dma_rdata; // To blit_disp_i of blit_disp.v 30 | reg [15:0] dstat; // To blit_disp_i of blit_disp.v 31 | reg reset; // To dport_pxclk_i of dport_pxclk.v, ... 32 | // End of automatics 33 | 34 | wire twolane = 1'b1; 35 | wire speed = 1'b1; 36 | wire [`ATTRMAX:0] attr = { 37 | 17'd26426, 24'd62, 24'd25, 38 | 17'd44049, 24'd61, 24'd41, 39 | 16'h21, 40 | 16'd352, 16'd35, 41 | 16'd136, 16'd3, 42 | 16'd1712, 16'd1060, 43 | 16'd1280, 16'd1024 44 | }; 45 | 46 | reg dpclk; 47 | initial dpclk = 1'b0; 48 | always #3.7 dpclk <= !dpclk; 49 | 50 | reg clk; 51 | initial clk = 1'b0; 52 | always #5 clk <= !clk; 53 | 54 | initial #300000 $finish; 55 | 56 | initial begin 57 | $dumpfile("test.vcd"); 58 | $dumpvars; 59 | end 60 | 61 | initial begin 62 | reset = 1'b1; 63 | #1000 reset = 1'b0; 64 | #80000 reset = 1'b1; 65 | #90000 reset = 1'b0; 66 | end 67 | 68 | always @(posedge clk) begin 69 | dma_ack <= dma_req; 70 | dma_rdata <= dma_addr; 71 | end 72 | 73 | wire dmahstart; 74 | pulse_sync sync_dmahstart(dpclk, clk, dpdmahstart, dmahstart); 75 | wire vblank; 76 | pulse_sync sync_dmavblank(dpclk, clk, dpvblank, vblank); 77 | blit_disp blit_disp_i(/*AUTOINST*/ 78 | // Outputs 79 | .dma_req (dma_req), 80 | .dma_addr (dma_addr[17:0]), 81 | .pixel_valid (pixel_valid), 82 | .pixel_data (pixel_data[15:0]), 83 | // Inputs 84 | .clk (clk), 85 | .daddr (daddr[17:0]), 86 | .dstat (dstat[15:0]), 87 | .dma_ack (dma_ack), 88 | .dma_rdata (dma_rdata[15:0]), 89 | .dmahstart (dmahstart), 90 | .vblank (vblank)); 91 | fifo fifo_i(/*AUTOINST*/ 92 | // Outputs 93 | .raw_pixel_valid (raw_pixel_valid), 94 | .raw_pixel_data (raw_pixel_data[15:0]), 95 | // Inputs 96 | .clk (clk), 97 | .dpclk (dpclk), 98 | .pixel_valid (pixel_valid), 99 | .pixel_data (pixel_data[15:0]), 100 | .raw_pixel_ready (raw_pixel_ready)); 101 | dport_pxclk dport_pxclk_i(/*AUTOINST*/ 102 | // Outputs 103 | .dphstart (dphstart), 104 | .dpvstart (dpvstart), 105 | .dmastart (dmastart), 106 | .dpvblank (dpvblank), 107 | .dpdmahstart (dpdmahstart), 108 | // Inputs 109 | .dpclk (dpclk), 110 | .attr (attr[`ATTRMAX:0]), 111 | .speed (speed), 112 | .reset (reset)); 113 | dport_pxconv dport_pxconv_i(/*AUTOINST*/ 114 | // Outputs 115 | .raw_pixel_ready (raw_pixel_ready), 116 | .dp_pixel_valid (dp_pixel_valid), 117 | .dp_pixel_data (dp_pixel_data[47:0]), 118 | // Inputs 119 | .dpclk (dpclk), 120 | .reset (reset), 121 | .raw_pixel_valid (raw_pixel_valid), 122 | .raw_pixel_data (raw_pixel_data[15:0]), 123 | .dp_pixel_ready (dp_pixel_ready), 124 | .dpdmahstart (dpdmahstart)); 125 | 126 | dport_stuff dport_stuff_i(/*AUTOINST*/ 127 | // Outputs 128 | .dp_pixel_ready (dp_pixel_ready), 129 | .dpdat0 (dpdat0[15:0]), 130 | .dpdat1 (dpdat1[15:0]), 131 | .dpisk0 (dpisk0[1:0]), 132 | .dpisk1 (dpisk1[1:0]), 133 | // Inputs 134 | .dpclk (dpclk), 135 | .dp_pixel_valid (dp_pixel_valid), 136 | .dp_pixel_data (dp_pixel_data[47:0]), 137 | .dphstart (dphstart), 138 | .dpvstart (dpvstart), 139 | .dmastart (dmastart), 140 | .attr (attr[`ATTRMAX:0]), 141 | .twolane (twolane), 142 | .speed (speed), 143 | .reset (reset)); 144 | 145 | endmodule 146 | 147 | module fifo( 148 | input wire clk, 149 | input wire dpclk, 150 | 151 | input wire pixel_valid, 152 | input wire [15:0] pixel_data, 153 | 154 | output wire raw_pixel_valid, 155 | output wire [15:0] raw_pixel_data, 156 | input wire raw_pixel_ready 157 | ); 158 | 159 | localparam FIFOLEN = 512; 160 | 161 | reg [15:0] fifo[0:FIFOLEN-1]; 162 | reg [31:0] wrptr, rdptr; 163 | 164 | always @(posedge clk) begin 165 | if(pixel_valid && (wrptr + 1) % FIFOLEN != rdptr) begin 166 | fifo[wrptr] <= pixel_data; 167 | wrptr <= (wrptr + 1) % FIFOLEN; 168 | end 169 | end 170 | 171 | assign raw_pixel_valid = rdptr != wrptr; 172 | assign raw_pixel_data = fifo[rdptr]; 173 | always @(posedge dpclk) begin 174 | if(raw_pixel_valid && raw_pixel_ready) begin 175 | rdptr <= (rdptr + 1) % FIFOLEN; 176 | end 177 | end 178 | 179 | endmodule 180 | 181 | // Local Variables: 182 | // verilog-library-directories:("." "../..") 183 | // End: 184 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_regs.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport_regs( 4 | input wire clk, 5 | 6 | input wire [7:0] reg_addr, 7 | output reg [31:0] reg_rdata, 8 | input wire [31:0] reg_wdata, 9 | input wire reg_wr, 10 | input wire reg_req, 11 | output reg reg_ack, 12 | input wire [3:0] reg_wstrb, 13 | output reg reg_err, 14 | 15 | output reg [`ATTRMAX:0] attr, 16 | 17 | output reg [31:0] phyctl, 18 | 19 | output reg [31:0] auxctrl, 20 | input wire [31:0] auxstat 21 | ); 22 | 23 | initial begin 24 | attr = 0; 25 | end 26 | always @(posedge clk) begin 27 | reg_ack <= reg_req; 28 | auxctrl[31] <= 1'b0; 29 | if(reg_req) begin 30 | reg_err <= 1'b0; 31 | if(reg_wr) 32 | casez(reg_addr) 33 | 'h00: phyctl <= reg_wdata; 34 | 'h08: auxctrl <= reg_wdata; 35 | 'h40: attr[31:0] <= reg_wdata; 36 | 'h44: attr[63:32] <= reg_wdata; 37 | 'h48: attr[95:64] <= reg_wdata; 38 | 'h4c: attr[127:96] <= reg_wdata; 39 | 'h50: attr[143:128] <= reg_wdata[15:0]; 40 | 'h54: attr[167:144] <= reg_wdata[23:0]; 41 | 'h58: attr[191:168] <= reg_wdata[23:0]; 42 | 'h5c: attr[208:192] <= reg_wdata[16:0]; 43 | 'h60: attr[232:209] <= reg_wdata[23:0]; 44 | 'h64: attr[256:233] <= reg_wdata[23:0]; 45 | 'h68: attr[273:257] <= reg_wdata[16:0]; 46 | default: reg_err <= 1'b1; 47 | endcase 48 | else 49 | case(reg_addr) 50 | 'h00: reg_rdata <= phyctl; 51 | 'h08: reg_rdata <= auxctrl; 52 | 'h0c: reg_rdata <= auxstat; 53 | default: reg_err <= 1'b1; 54 | endcase 55 | end 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_scrambler.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport_scrambler( 4 | input wire clk, 5 | input wire [15:0] indata, 6 | input wire [1:0] inisk, 7 | output reg [15:0] outdata, 8 | output reg [1:0] outisk 9 | ); 10 | 11 | reg [15:0] lfsr, lfsr_; 12 | reg [8:0] bsctr; 13 | reg [15:0] key; 14 | 15 | initial begin 16 | lfsr = 16'hffff; 17 | bsctr = 0; 18 | end 19 | wire [1:0] bs, reset; 20 | assign bs[0] = inisk[0] && indata[7:0] == `symBS; 21 | assign bs[1] = inisk[1] && indata[15:8] == `symBS; 22 | assign reset = bsctr == 0 ? bs : 0; 23 | always @(posedge clk) begin 24 | outisk <= inisk; 25 | outdata[7:0] <= reset[0] ? `symSR : indata[7:0] ^ (!inisk[0] ? key[7:0] : 0); 26 | outdata[15:8] <= reset[1] ? `symSR : indata[15:8] ^ (!inisk[1] ? key[15:8] : 0); 27 | lfsr <= lfsr_; 28 | if(reset[0]) 29 | lfsr <= 'he817; 30 | if(reset[1]) 31 | lfsr <= 'hffff; 32 | if(|bs) 33 | bsctr <= bsctr + 1; 34 | end 35 | 36 | always @(*) begin 37 | lfsr_[0] = lfsr[0] ^ lfsr[11] ^ lfsr[12] ^ lfsr[13]; 38 | lfsr_[1] = lfsr[1] ^ lfsr[12] ^ lfsr[13] ^ lfsr[14]; 39 | lfsr_[2] = lfsr[2] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15]; 40 | lfsr_[3] = lfsr[0] ^ lfsr[3] ^ lfsr[11] ^ lfsr[12] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15]; 41 | lfsr_[4] = lfsr[0] ^ lfsr[1] ^ lfsr[4] ^ lfsr[11] ^ lfsr[14] ^ lfsr[15]; 42 | lfsr_[5] = lfsr[0] ^ lfsr[1] ^ lfsr[2] ^ lfsr[5] ^ lfsr[11] ^ lfsr[13] ^ lfsr[15]; 43 | lfsr_[6] = lfsr[1] ^ lfsr[2] ^ lfsr[3] ^ lfsr[6] ^ lfsr[12] ^ lfsr[14]; 44 | lfsr_[7] = lfsr[2] ^ lfsr[3] ^ lfsr[4] ^ lfsr[7] ^ lfsr[13] ^ lfsr[15]; 45 | lfsr_[8] = lfsr[3] ^ lfsr[4] ^ lfsr[5] ^ lfsr[8] ^ lfsr[14]; 46 | lfsr_[9] = lfsr[4] ^ lfsr[5] ^ lfsr[6] ^ lfsr[9] ^ lfsr[15]; 47 | lfsr_[10] = lfsr[5] ^ lfsr[6] ^ lfsr[7] ^ lfsr[10]; 48 | lfsr_[11] = lfsr[6] ^ lfsr[7] ^ lfsr[8] ^ lfsr[11]; 49 | lfsr_[12] = lfsr[7] ^ lfsr[8] ^ lfsr[9] ^ lfsr[12]; 50 | lfsr_[13] = lfsr[8] ^ lfsr[9] ^ lfsr[10] ^ lfsr[13]; 51 | lfsr_[14] = lfsr[9] ^ lfsr[10] ^ lfsr[11] ^ lfsr[14]; 52 | lfsr_[15] = lfsr[10] ^ lfsr[11] ^ lfsr[12] ^ lfsr[15]; 53 | 54 | key[0] = lfsr[15]; 55 | key[1] = lfsr[14]; 56 | key[2] = lfsr[13]; 57 | key[3] = lfsr[12]; 58 | key[4] = lfsr[11]; 59 | key[5] = lfsr[10]; 60 | key[6] = lfsr[9]; 61 | key[7] = lfsr[8]; 62 | key[8] = lfsr[7]; 63 | key[9] = lfsr[6]; 64 | key[10] = lfsr[5]; 65 | key[11] = lfsr[4] ^ lfsr[15]; 66 | key[12] = lfsr[3] ^ lfsr[14] ^ lfsr[15]; 67 | key[13] = lfsr[2] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15]; 68 | key[14] = lfsr[1] ^ lfsr[12] ^ lfsr[13] ^ lfsr[14]; 69 | key[15] = lfsr[0] ^ lfsr[11] ^ lfsr[12] ^ lfsr[13]; 70 | 71 | if(reset[0]) 72 | key[15:8] = 'hff; 73 | end 74 | endmodule 75 | -------------------------------------------------------------------------------- /aijubrd/dport/dport_stuff.v: -------------------------------------------------------------------------------- 1 | `include "dport.vh" 2 | 3 | module dport_stuff( 4 | input wire dpclk, 5 | input wire dp_pixel_valid, 6 | input wire [47:0] dp_pixel_data, 7 | output reg dp_pixel_ready, 8 | 9 | input wire dphstart, 10 | input wire dpvstart, 11 | input wire dmastart, 12 | 13 | output reg [15:0] dpdat0, 14 | output reg [15:0] dpdat1, 15 | output reg [1:0] dpisk0, 16 | output reg [1:0] dpisk1, 17 | 18 | input wire [`ATTRMAX:0] attr, 19 | input wire twolane, 20 | input wire speed, 21 | input wire reset 22 | ); 23 | 24 | parameter MAXCTR = 15; 25 | 26 | reg [15:0] dpdat0_, dpdat1_; 27 | reg [1:0] dpisk0_, dpisk1_; 28 | 29 | reg [3:0] state, state_; 30 | localparam RESET = 0; 31 | localparam IDLE = 1; 32 | localparam ACTIVE = 2; 33 | localparam STUFF = 3; 34 | localparam VBLANK = 4; 35 | localparam VBID = 5; 36 | localparam EOL = 6; 37 | 38 | reg hstart, vstart, hstart_, vstart_, pxcons; 39 | 40 | wire [15:0] vact = attr[15:0]; 41 | wire [15:0] hact = attr[31:16]; 42 | wire [15:0] vtot = attr[47:32]; 43 | wire [15:0] htot = attr[63:48]; 44 | wire [15:0] vsync = attr[79:64]; 45 | wire [15:0] hsync = attr[95:80]; 46 | wire [15:0] vdata = attr[111:96]; 47 | wire [15:0] hdata = attr[127:112]; 48 | wire [15:0] misc = attr[143:128]; 49 | wire [23:0] Mvid = speed ? attr[232:209] : attr[167:144]; 50 | wire [23:0] Nvid = speed ? attr[256:233] : attr[191:168]; 51 | wire [15:0] sclkinc = (speed ? attr[273:257] : attr[208:192]) >> twolane; 52 | 53 | reg [23:0] px[0:3]; 54 | reg [2:0] pxfill, pxfill_; 55 | reg [1:0] pxrem, pxrem_; 56 | reg [5:0] tuctr, ctr, tuctr_, ctr_; 57 | reg [15:0] xrem, xrem_, yrem, yrem_; 58 | 59 | reg [18:0] tufctr; 60 | wire [19:0] tufround = tufctr + 'h800; 61 | wire [5:0] tufill = tufround[16:11]; 62 | wire [18:0] tufinc = ({3'd0, sclkinc} << 1) + {3'd0, sclkinc}; 63 | wire [19:0] tufincround = tufinc + 'h800; 64 | reg tufreset, tufstep; 65 | reg [11:0] resetctr; 66 | 67 | always @(posedge dpclk) begin 68 | if(reset) begin 69 | state <= RESET; 70 | hstart <= 0; 71 | vstart <= 0; 72 | pxrem <= 0; 73 | tuctr <= 0; 74 | pxfill <= 0; 75 | xrem <= 0; 76 | yrem <= 0; 77 | ctr <= 0; 78 | tufctr <= 0; 79 | end else begin 80 | state <= state_; 81 | hstart <= hstart_; 82 | vstart <= vstart_; 83 | pxrem <= pxrem_; 84 | tuctr <= tuctr_; 85 | ctr <= ctr_; 86 | xrem <= xrem_; 87 | yrem <= yrem_; 88 | pxfill <= pxfill_; 89 | end 90 | dpdat0 <= dpdat0_; 91 | dpdat1 <= dpdat1_; 92 | dpisk0 <= dpisk0_; 93 | dpisk1 <= dpisk1_; 94 | if(tufreset) 95 | tufctr <= tufinc; 96 | else if(tufstep) begin 97 | tufctr <= tufctr - {2'd0, tufill, 11'd0} + tufinc; 98 | tuctr <= tufill; 99 | end 100 | resetctr <= resetctr + 1; 101 | 102 | if(pxcons) 103 | if(twolane) begin 104 | px[0] <= px[2]; 105 | px[1] <= px[3]; 106 | end else begin 107 | px[0] <= px[1]; 108 | px[1] <= px[2]; 109 | px[2] <= px[3]; 110 | end 111 | 112 | if(dp_pixel_valid && dp_pixel_ready) begin 113 | px[pxfill_ - 2] <= dp_pixel_data[23:0]; 114 | px[pxfill_ - 1] <= dp_pixel_data[47:24]; 115 | end 116 | end 117 | 118 | always @(*) begin 119 | pxfill_ = pxfill; 120 | if(pxcons) 121 | pxfill_ = pxfill_ - (twolane ? 2 : 1); 122 | dp_pixel_ready = pxfill_ < 3 && !reset && !dmastart; 123 | if(dp_pixel_valid && dp_pixel_ready) 124 | pxfill_ = pxfill_ + 2; 125 | if(dmastart) 126 | pxfill_ = 0; 127 | end 128 | 129 | always @(*) begin 130 | state_ = state; 131 | hstart_ = hstart && !vstart || dphstart; 132 | vstart_ = vstart || dpvstart; 133 | pxrem_ = pxrem; 134 | tuctr_ = tuctr; 135 | ctr_ = ctr; 136 | xrem_ = xrem; 137 | yrem_ = yrem; 138 | dpdat0_ = 0; 139 | dpdat1_ = 0; 140 | dpisk0_ = 0; 141 | dpisk1_ = 0; 142 | pxcons = 0; 143 | tufreset = 0; 144 | tufstep = 0; 145 | 146 | case(state) 147 | RESET: begin 148 | if(!reset) 149 | state_ = IDLE; 150 | if(resetctr == 0) begin 151 | dpdat0_ = {8'd8, `symBS}; 152 | dpdat1_ = {8'd8, `symBS}; 153 | dpisk0_ = 2'b01; 154 | dpisk1_ = 2'b01; 155 | end 156 | end 157 | IDLE: begin 158 | if(vstart_) begin 159 | if(pxfill >= 3) begin 160 | state_ = ACTIVE; 161 | xrem_ = (hact << 1) + hact; 162 | if(twolane) 163 | xrem_ = xrem_ + 1 >> 1; 164 | yrem_ = vact; 165 | vstart_ = 0; 166 | hstart_ = 0; 167 | dpdat0_ = {`symBE, 8'b0}; 168 | dpdat1_ = {`symBE, 8'b0}; 169 | dpisk0_ = 2'b10; 170 | dpisk1_ = 2'b10; 171 | tufreset = 1; 172 | tuctr_ = tufincround[16:11]; 173 | end 174 | end else if(hstart_ && yrem > 0 && pxfill >= 3) begin 175 | state_ = ACTIVE; 176 | xrem_ = (hact << 1) + hact; 177 | if(twolane) 178 | xrem_ = xrem_ + 1 >> 1; 179 | ctr_ = 0; 180 | hstart_ = 0; 181 | dpdat0_ = {`symBE, 8'b0}; 182 | dpdat1_ = {`symBE, 8'b0}; 183 | dpisk0_ = 2'b10; 184 | dpisk1_ = 2'b10; 185 | tufreset = 1; 186 | tuctr_ = tufincround[16:11]; 187 | end else if(hstart_ && yrem == 0) begin 188 | dpdat0_ = {8'h1, `symBS}; 189 | dpdat1_ = {8'h1, `symBS}; 190 | dpisk0_ = 2'b01; 191 | dpisk1_ = 2'b01; 192 | ctr_ = 1; 193 | hstart_ = 0; 194 | state_ = VBID; 195 | end 196 | end 197 | ACTIVE: begin 198 | case(pxrem) 199 | 0: begin 200 | dpdat0_ = px[0][15:0]; 201 | dpdat1_ = px[1][15:0]; 202 | end 203 | 1: begin 204 | dpdat0_ = px[0][23:8]; 205 | dpdat1_ = px[1][23:8]; 206 | end 207 | 2: begin 208 | dpdat0_ = {px[twolane ? 2 : 1][7:0], px[0][23:16]}; 209 | dpdat1_ = {px[3][7:0], px[1][23:16]}; 210 | end 211 | endcase 212 | ctr_ = ctr + 1; 213 | if(tuctr == 0 || xrem == 0) begin 214 | state_ = STUFF; 215 | dpdat0_ = {8'b0, `symFS}; 216 | dpdat1_ = {8'b0, `symFS}; 217 | dpisk0_ = 2'b01; 218 | dpisk1_ = 2'b01; 219 | if(xrem == 0) begin 220 | dpdat0_ = {7'b0, yrem == 1, `symBS}; 221 | dpdat1_ = {7'b0, yrem == 1, `symBS}; 222 | state_ = VBID; 223 | ctr_ = 1; 224 | end else if(ctr == MAXCTR) begin 225 | dpdat0_[15:8] = `symFE; 226 | dpdat1_[15:8] = `symFE; 227 | dpisk0_[1] = 1; 228 | dpisk1_[1] = 1; 229 | state_ = ACTIVE; 230 | ctr_ = 0; 231 | end 232 | end else if(tuctr == 1 || xrem == 1) begin 233 | tuctr_ = 0; 234 | state_ = STUFF; 235 | pxrem_ = pxrem == 2 ? 0 : pxrem + 1; 236 | pxcons = pxrem[1]; 237 | xrem_ = xrem - 1; 238 | if(xrem_ == 0) begin 239 | state_ = VBID; 240 | ctr_ = 0; 241 | dpdat0_[15:8] = `symBS; 242 | dpdat1_[15:8] = `symBS; 243 | end else begin 244 | dpdat0_[15:8] = `symFS; 245 | dpdat1_[15:8] = `symFS; 246 | end 247 | dpisk0_[1] = 1; 248 | dpisk1_[1] = 1; 249 | end else begin 250 | pxrem_ = pxrem == 0 ? 2 : pxrem - 1; 251 | pxcons = pxrem != 0; 252 | tuctr_ = tuctr - 2; 253 | xrem_ = xrem - 2; 254 | end 255 | end 256 | STUFF: begin 257 | if(ctr == MAXCTR) begin 258 | dpdat0_[15:8] = `symFE; 259 | dpdat1_[15:8] = `symFE; 260 | dpisk0_[1] = 1; 261 | dpisk1_[1] = 1; 262 | ctr_ = 0; 263 | state_ = ACTIVE; 264 | tufstep = 1; 265 | end else 266 | ctr_ = ctr + 1; 267 | end 268 | VBLANK: begin 269 | ctr_ = ctr + 1; 270 | if(twolane) 271 | case(ctr) 272 | 0: begin 273 | dpdat0_ = {`symSS, `symSS}; 274 | dpdat1_ = {`symSS, `symSS}; 275 | dpisk0_ = 3; 276 | dpisk1_ = 3; 277 | end 278 | 1: begin 279 | dpdat0_ = {Mvid[15:8], Mvid[23:16]}; 280 | dpdat1_ = {Mvid[15:8], Mvid[23:16]}; 281 | end 282 | 2: begin 283 | dpdat0_ = {htot[15:8], Mvid[7:0]}; 284 | dpdat1_ = {hdata[15:8], Mvid[7:0]}; 285 | end 286 | 3: begin 287 | dpdat0_ = {vtot[15:8], htot[7:0]}; 288 | dpdat1_ = {vdata[15:8], hdata[7:0]}; 289 | end 290 | 4: begin 291 | dpdat0_ = {hsync[15:8], vtot[7:0]}; 292 | dpdat1_ = {vsync[15:8], vdata[7:0]}; 293 | end 294 | 5: begin 295 | dpdat0_ = {Mvid[23:16], hsync[7:0]}; 296 | dpdat1_ = {Mvid[23:16], vsync[7:0]}; 297 | end 298 | 6: begin 299 | dpdat0_ = {Mvid[7:0], Mvid[15:8]}; 300 | dpdat1_ = {Mvid[7:0], Mvid[15:8]}; 301 | end 302 | 7: begin 303 | dpdat0_ = {hact[7:0], hact[15:8]}; 304 | dpdat1_ = {Nvid[15:8], Nvid[23:16]}; 305 | end 306 | 8: begin 307 | dpdat0_ = {vact[7:0], vact[15:8]}; 308 | dpdat1_ = {misc[7:0], Nvid[7:0]}; 309 | end 310 | 9: begin 311 | dpdat0_ = 0; 312 | dpdat1_ = {8'b0, misc[15:8]}; 313 | end 314 | 10: begin 315 | dpdat0_ = {8'b0, `symSE}; 316 | dpdat1_ = {8'b0, `symSE}; 317 | dpisk0_ = 2'b01; 318 | dpisk1_ = 2'b01; 319 | ctr_ = 0; 320 | state_ = IDLE; 321 | end 322 | endcase 323 | else 324 | case(ctr) 325 | 0: begin 326 | dpdat0_ = {`symSS, `symSS}; 327 | dpisk0_ = 3; 328 | end 329 | 1: dpdat0_ = {Mvid[15:8], Mvid[23:16]}; 330 | 2: dpdat0_ = {htot[15:8], Mvid[7:0]}; 331 | 3: dpdat0_ = {vtot[15:8], htot[7:0]}; 332 | 4: dpdat0_ = {hsync[15:8], vtot[7:0]}; 333 | 5: dpdat0_ = {Mvid[23:16], hsync[7:0]}; 334 | 6: dpdat0_ = {Mvid[7:0], Mvid[15:8]}; 335 | 7: dpdat0_ = {hdata[7:0], hdata[15:8]}; 336 | 8: dpdat0_ = {vdata[7:0], vdata[15:8]}; 337 | 9: dpdat0_ = {vsync[7:0], vsync[15:8]}; 338 | 10: dpdat0_ = {Mvid[15:8], Mvid[23:16]}; 339 | 11: dpdat0_ = {hact[15:8], Mvid[7:0]}; 340 | 12: dpdat0_ = {vact[15:8], hact[7:0]}; 341 | 13: dpdat0_ = {8'b0, vact[7:0]}; 342 | 14: dpdat0_ = {Mvid[23:16], 8'b0}; 343 | 15: dpdat0_ = {Mvid[7:0], Mvid[15:8]}; 344 | 16: dpdat0_ = {Nvid[15:8], Nvid[23:16]}; 345 | 17: dpdat0_ = {misc[7:0], Nvid[7:0]}; 346 | 18: dpdat0_ = {8'b0, misc[15:8]}; 347 | 19: begin 348 | dpdat0_ = {8'b0, `symSE}; 349 | dpisk0_ = 2'b01; 350 | ctr_ = 0; 351 | state_ = IDLE; 352 | end 353 | endcase 354 | end 355 | VBID: begin 356 | ctr_ = ctr + 2; 357 | dpisk0_ = 0; 358 | dpisk1_ = 0; 359 | case(ctr % 3) 360 | 0: dpdat0_ = {Mvid[7:0], 7'b0, yrem <= 1}; 361 | 1: dpdat0_ = {8'b0, Mvid[7:0]}; 362 | 2: dpdat0_ = {7'b0, yrem <= 1, 8'b0}; 363 | endcase 364 | if(!twolane && (ctr == 10 || ctr == 11) || twolane && (ctr == 4 || ctr == 5)) begin 365 | ctr_ = 0; 366 | state_ = EOL; 367 | end 368 | dpdat1_ = dpdat0_; 369 | end 370 | EOL: begin 371 | state_ = yrem == 1 ? VBLANK : IDLE; 372 | if(yrem != 0) 373 | yrem_ = yrem - 1; 374 | end 375 | endcase 376 | end 377 | 378 | endmodule 379 | -------------------------------------------------------------------------------- /aijubrd/extra.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name DPCLK -period 7.4 [get_nets dport0/dpclk] 2 | set_false_path -from [get_clocks FCLK] -to [get_clocks DPCLK] 3 | set_false_path -from [get_clocks DPCLK] -to [get_clocks FCLK] 4 | -------------------------------------------------------------------------------- /aijubrd/fns.tcl: -------------------------------------------------------------------------------- 1 | set thepart xc7z015clg485-1 2 | set hdl [file normalize [file dirname [info script]]/..] 3 | 4 | proc new {} { 5 | global thepart 6 | close_project -quiet 7 | create_project -in_memory -part $thepart 8 | } 9 | 10 | proc here {} { 11 | file dirname [info script] 12 | } 13 | 14 | proc checktarget {} { 15 | global target 16 | 17 | if {![info exists target]} { 18 | set target [here]/build 19 | } 20 | file mkdir $target 21 | } 22 | 23 | proc synth {top {flatten_hierarchy none} {mode default}} { 24 | global target thepart 25 | checktarget 26 | 27 | synth_design -top $top -part $thepart -flatten_hierarchy $flatten_hierarchy -mode $mode 28 | write_checkpoint -force $target/post_synth 29 | } 30 | 31 | proc implement {} { 32 | global target 33 | checktarget 34 | 35 | opt_design 36 | place_design 37 | write_checkpoint -force $target/post_place 38 | phys_opt_design 39 | route_design 40 | write_checkpoint -force $target/post_route 41 | 42 | report_timing_summary -file $target/post_route_timing.rpt 43 | report_utilization -file $target/post_route_util.rpt 44 | } 45 | 46 | proc bitstream {} { 47 | global target 48 | checktarget 49 | write_bitstream -force -bin_file -file $target/out.bit 50 | 51 | if {! [string match -nocase {*timing constraints are met*} \ 52 | [report_timing_summary -no_header -no_detailed_paths -return_string]]} \ 53 | {puts " **** timing constraints not met ****"} 54 | } 55 | 56 | proc notb {args} { 57 | set y {} 58 | foreach x [glob {*}$args] { 59 | if { ! [regexp {_tb\.v$} $x ] } { 60 | lappend y $x 61 | } 62 | } 63 | return $y 64 | } 65 | -------------------------------------------------------------------------------- /aijubrd/mkfile: -------------------------------------------------------------------------------- 1 | all:V: top.v top.xdc 2 | 3 | top.v:DV: blit.vlt 4 | vlt -lc $prereq >$target 5 | 6 | top.xdc:DV: blit.vlt 7 | vlt -lc -O xdc $prereq | grep -v 'IOSTANDARD.*comp_[pn]' >$target 8 | 9 | clean:V: 10 | rm -f *.jou *.log 11 | -------------------------------------------------------------------------------- /aijubrd/pulse_sync.v: -------------------------------------------------------------------------------- 1 | module pulse_sync( 2 | input wire clk_a, 3 | input wire clk_b, 4 | 5 | input wire in, 6 | output reg out 7 | ); 8 | 9 | reg ta; 10 | initial ta = 1'b0; 11 | always @(posedge clk_a) begin 12 | ta <= ta ^ in; 13 | end 14 | wire tb; 15 | reg tb0; 16 | initial tb0 = 1'b0; 17 | sync sync_i(clk_b, ta, tb); 18 | always @(posedge clk_b) begin 19 | tb0 <= tb; 20 | out <= tb ^ tb0; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /aijubrd/regs.v: -------------------------------------------------------------------------------- 1 | module regs( 2 | input wire clk, 3 | 4 | input wire reg_req, 5 | input wire reg_wr, 6 | input wire [7:0] reg_addr, 7 | input wire [31:0] reg_wdata, 8 | output reg reg_ack, 9 | output reg [31:0] reg_rdata, 10 | output reg reg_err, 11 | 12 | output reg uart_in_valid, 13 | output reg [7:0] uart_in_data, 14 | input wire uart_in_ready, 15 | 16 | input wire uart_out_valid, 17 | input wire [7:0] uart_out_data, 18 | output reg uart_out_ready, 19 | 20 | output reg kbd_in_valid, 21 | output reg [7:0] kbd_in_data, 22 | input wire kbd_in_ready, 23 | 24 | input wire kbd_out_valid, 25 | input wire [7:0] kbd_out_data, 26 | output wire kbd_out_ready, 27 | 28 | output reg [15:0] mouse_x, 29 | output reg [15:0] mouse_y, 30 | output reg [2:0] mouse_but 31 | ); 32 | 33 | assign kbd_out_ready = 1'b1; 34 | always @(posedge clk) begin 35 | if(uart_in_valid && uart_in_ready) 36 | uart_in_valid <= 1'b0; 37 | if(kbd_in_valid && kbd_in_ready) 38 | kbd_in_valid <= 1'b0; 39 | reg_ack <= reg_req; 40 | reg_err <= 1'b0; 41 | uart_out_ready <= 1'b0; 42 | if(reg_req) begin 43 | if(reg_wr) 44 | case(reg_addr) 45 | 8'h0: begin 46 | uart_in_valid <= 1'b1; 47 | uart_in_data <= reg_wdata[7:0]; 48 | end 49 | 8'h8: begin 50 | kbd_in_valid <= 1'b1; 51 | kbd_in_data <= reg_wdata[7:0]; 52 | end 53 | 8'h14: {mouse_y, mouse_x} <= reg_wdata; 54 | 8'h18: mouse_but <= reg_wdata; 55 | default: reg_err <= 1'b1; 56 | endcase 57 | else 58 | case(reg_addr) 59 | 8'h4: reg_rdata <= {31'b0, uart_in_valid}; 60 | 8'hc: reg_rdata <= {31'b0, kbd_in_valid}; 61 | 8'h10: begin 62 | reg_rdata <= {!uart_out_valid, 23'b0, uart_out_data}; 63 | uart_out_ready <= uart_out_valid; 64 | end 65 | default: reg_err <= 1'b1; 66 | endcase 67 | end 68 | end 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /aijubrd/sync.v: -------------------------------------------------------------------------------- 1 | module sync( 2 | input wire clk, 3 | input wire din, 4 | output wire dout 5 | ); 6 | 7 | `ifdef SIMULATION 8 | reg d0, d1; 9 | `else 10 | (* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg d0, d1; 11 | `endif 12 | 13 | always @(posedge clk) begin 14 | d0 <= din; 15 | d1 <= d0; 16 | end 17 | 18 | assign dout = d1; 19 | initial begin 20 | d0 <= 0; 21 | d1 <= 0; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /aijubrd/top.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [1:0] refclk, 3 | inout wire auxn, 4 | inout wire auxp, 5 | output wire [3:0] tx 6 | ); 7 | 8 | wire [15:0] mouse_x; 9 | wire _outerr; 10 | wire [15:0] mouse_y; 11 | wire _gp0aclk; 12 | wire [2:0] _gp0awprot; 13 | wire [11:0] _gp0arid; 14 | wire [11:0] _gp0awid; 15 | wire dport_reg_wr; 16 | wire [15:0] pixel_data; 17 | wire dport_aux_wr; 18 | wire [3:0] _gp0arcache; 19 | wire [31:0] dport_reg_rdata; 20 | wire [3:0] _gp0awcache; 21 | wire [31:0] dport_reg_wdata; 22 | wire [7:0] reg_addr; 23 | wire [3:0] _fclkclk; 24 | wire clk = _fclkclk[0]; 25 | wire [31:0] dport_aux_rdata; 26 | wire [31:0] dport_aux_wdata; 27 | wire _gp0arvalid; 28 | wire _gp0arready; 29 | wire _gp0awvalid; 30 | wire [31:0] _outaddr; 31 | wire _gp0awready; 32 | wire dport_reg_ack; 33 | wire kbd_out_valid; 34 | wire [3:0] dport_reg_wstrb; 35 | wire kbd_out_ready; 36 | wire [7:0] kbd_in_data; 37 | wire uart_in_valid; 38 | wire dport_aux_ack; 39 | wire uart_in_ready; 40 | wire [1:0] _gp0arburst; 41 | wire [7:0] uart_out_data; 42 | wire dport_reg_req; 43 | wire dport_reg_err; 44 | wire [1:0] _gp0awburst; 45 | wire [31:0] _gp0rdata; 46 | wire [31:0] _gp0wdata; 47 | wire [3:0] _gp0arlen; 48 | wire dport_aux_req; 49 | wire [3:0] _gp0awlen; 50 | wire vblank; 51 | wire [1:0] _gp0bresp; 52 | wire reg_wr; 53 | wire [3:0] _gp0arqos; 54 | wire _gp0rlast; 55 | wire [3:0] _fclkresetn; 56 | wire pixel_valid; 57 | wire [3:0] _gp0awqos; 58 | wire _gp0wlast; 59 | wire [1:0] _gp0rresp; 60 | wire [11:0] _gp0bid; 61 | wire [3:0] _gp0wstrb; 62 | wire _outwr; 63 | wire [11:0] _gp0rid; 64 | wire [31:0] reg_rdata; 65 | wire [11:0] _gp0wid; 66 | wire [31:0] reg_wdata; 67 | wire [7:0] dport_reg_addr; 68 | wire [31:0] _outrdata; 69 | wire rstn = _fclkresetn[0]; 70 | wire dmahstart; 71 | wire [31:0] _outwdata; 72 | wire reg_ack; 73 | wire [4:0] dport_aux_addr; 74 | wire [2:0] mouse_but; 75 | wire [31:0] _gp0araddr; 76 | wire kbd_in_valid; 77 | wire _gp0bvalid; 78 | wire [31:0] _gp0awaddr; 79 | wire kbd_in_ready; 80 | wire _gp0bready; 81 | wire [7:0] kbd_out_data; 82 | wire uart_out_valid; 83 | wire [1:0] _gp0arlock; 84 | wire reg_req; 85 | wire reg_err; 86 | wire _outack; 87 | wire uart_out_ready; 88 | wire [1:0] _gp0awlock; 89 | wire _gp0rvalid; 90 | wire [3:0] _outwstrb; 91 | wire [7:0] uart_in_data; 92 | wire _gp0rready; 93 | wire _gp0wvalid; 94 | wire _gp0wready; 95 | wire [1:0] _gp0arsize; 96 | wire [1:0] _gp0awsize; 97 | wire [2:0] _gp0arprot; 98 | wire _outreq; 99 | 100 | regs regs0( 101 | .reg_req(reg_req), 102 | .reg_wr(reg_wr), 103 | .reg_addr(reg_addr), 104 | .reg_wdata(reg_wdata), 105 | .reg_ack(reg_ack), 106 | .reg_rdata(reg_rdata), 107 | .reg_err(reg_err), 108 | .clk(clk), 109 | .uart_in_valid(uart_in_valid), 110 | .uart_in_data(uart_in_data), 111 | .uart_in_ready(uart_in_ready), 112 | .uart_out_valid(uart_out_valid), 113 | .uart_out_data(uart_out_data), 114 | .uart_out_ready(uart_out_ready), 115 | .kbd_in_valid(kbd_in_valid), 116 | .kbd_in_data(kbd_in_data), 117 | .kbd_in_ready(kbd_in_ready), 118 | .kbd_out_valid(kbd_out_valid), 119 | .kbd_out_data(kbd_out_data), 120 | .kbd_out_ready(kbd_out_ready), 121 | .mouse_x(mouse_x), 122 | .mouse_y(mouse_y), 123 | .mouse_but(mouse_but) 124 | ); 125 | blit blit0( 126 | .clk(clk), 127 | .uart_in_valid(uart_in_valid), 128 | .uart_in_data(uart_in_data), 129 | .uart_in_ready(uart_in_ready), 130 | .uart_out_valid(uart_out_valid), 131 | .uart_out_data(uart_out_data), 132 | .uart_out_ready(uart_out_ready), 133 | .kbd_in_valid(kbd_in_valid), 134 | .kbd_in_data(kbd_in_data), 135 | .kbd_in_ready(kbd_in_ready), 136 | .kbd_out_valid(kbd_out_valid), 137 | .kbd_out_data(kbd_out_data), 138 | .kbd_out_ready(kbd_out_ready), 139 | .pixel_valid(pixel_valid), 140 | .pixel_data(pixel_data), 141 | .dmahstart(dmahstart), 142 | .vblank(vblank), 143 | .mouse_x(mouse_x), 144 | .mouse_y(mouse_y), 145 | .mouse_but(mouse_but) 146 | ); 147 | dport dport0( 148 | .reg_addr(dport_reg_addr), 149 | .reg_rdata(dport_reg_rdata), 150 | .reg_wdata(dport_reg_wdata), 151 | .reg_wr(dport_reg_wr), 152 | .reg_req(dport_reg_req), 153 | .reg_ack(dport_reg_ack), 154 | .reg_wstrb(dport_reg_wstrb), 155 | .reg_err(dport_reg_err), 156 | .aux_addr(dport_aux_addr), 157 | .aux_wdata(dport_aux_wdata), 158 | .aux_req(dport_aux_req), 159 | .aux_wr(dport_aux_wr), 160 | .aux_ack(dport_aux_ack), 161 | .aux_rdata(dport_aux_rdata), 162 | .refclk(refclk), 163 | .auxp(auxp), 164 | .auxn(auxn), 165 | .tx(tx), 166 | .clk(clk), 167 | .pixel_valid(pixel_valid), 168 | .pixel_data(pixel_data), 169 | .dmahstart(dmahstart), 170 | .vblank(vblank) 171 | ); 172 | _intercon _intercon( 173 | .clk(clk), 174 | .rstn(rstn), 175 | .reg_req(reg_req), 176 | .reg_ack(reg_ack), 177 | .reg_addr(reg_addr), 178 | .reg_rdata(reg_rdata), 179 | .reg_wdata(reg_wdata), 180 | .reg_wr(reg_wr), 181 | .reg_err(reg_err), 182 | .dport_reg_req(dport_reg_req), 183 | .dport_reg_ack(dport_reg_ack), 184 | .dport_reg_addr(dport_reg_addr), 185 | .dport_reg_rdata(dport_reg_rdata), 186 | .dport_reg_wdata(dport_reg_wdata), 187 | .dport_reg_wr(dport_reg_wr), 188 | .dport_reg_err(dport_reg_err), 189 | .dport_reg_wstrb(dport_reg_wstrb), 190 | .dport_aux_req(dport_aux_req), 191 | .dport_aux_ack(dport_aux_ack), 192 | .dport_aux_addr(dport_aux_addr), 193 | .dport_aux_rdata(dport_aux_rdata), 194 | .dport_aux_wdata(dport_aux_wdata), 195 | .dport_aux_wr(dport_aux_wr), 196 | ._outaddr(_outaddr), 197 | ._outrdata(_outrdata), 198 | ._outwdata(_outwdata), 199 | ._outwr(_outwr), 200 | ._outreq(_outreq), 201 | ._outack(_outack), 202 | ._outerr(_outerr), 203 | ._outwstrb(_outwstrb) 204 | ); 205 | axi3 _axi3( 206 | .axiaclk(_gp0aclk), 207 | .axiarvalid(_gp0arvalid), 208 | .axiarready(_gp0arready), 209 | .axiaraddr(_gp0araddr), 210 | .axiarburst(_gp0arburst), 211 | .axiarlock(_gp0arlock), 212 | .axiarsize(_gp0arsize), 213 | .axiarprot(_gp0arprot), 214 | .axiarlen(_gp0arlen), 215 | .axiarcache(_gp0arcache), 216 | .axiarqos(_gp0arqos), 217 | .axiarid(_gp0arid), 218 | .axirvalid(_gp0rvalid), 219 | .axirready(_gp0rready), 220 | .axirdata(_gp0rdata), 221 | .axirid(_gp0rid), 222 | .axirresp(_gp0rresp), 223 | .axirlast(_gp0rlast), 224 | .axiawvalid(_gp0awvalid), 225 | .axiawready(_gp0awready), 226 | .axiawaddr(_gp0awaddr), 227 | .axiawburst(_gp0awburst), 228 | .axiawlock(_gp0awlock), 229 | .axiawsize(_gp0awsize), 230 | .axiawprot(_gp0awprot), 231 | .axiawlen(_gp0awlen), 232 | .axiawcache(_gp0awcache), 233 | .axiawqos(_gp0awqos), 234 | .axiawid(_gp0awid), 235 | .axiwvalid(_gp0wvalid), 236 | .axiwready(_gp0wready), 237 | .axiwdata(_gp0wdata), 238 | .axiwstrb(_gp0wstrb), 239 | .axiwid(_gp0wid), 240 | .axiwlast(_gp0wlast), 241 | .axibvalid(_gp0bvalid), 242 | .axibready(_gp0bready), 243 | .axibresp(_gp0bresp), 244 | .axibid(_gp0bid), 245 | .outaddr(_outaddr), 246 | .outrdata(_outrdata), 247 | .outwdata(_outwdata), 248 | .outwr(_outwr), 249 | .outreq(_outreq), 250 | .outack(_outack), 251 | .outerr(_outerr), 252 | .outwstrb(_outwstrb), 253 | .clk(clk), 254 | .rstn(rstn) 255 | ); 256 | (* DONT_TOUCH="YES" *)PS7 _PS7( 257 | .MAXIGP0ACLK(_gp0aclk), 258 | .MAXIGP0AWPROT(_gp0awprot), 259 | .MAXIGP0ARID(_gp0arid), 260 | .MAXIGP0AWID(_gp0awid), 261 | .MAXIGP0ARCACHE(_gp0arcache), 262 | .MAXIGP0AWCACHE(_gp0awcache), 263 | .FCLKCLK(_fclkclk), 264 | .MAXIGP0ARVALID(_gp0arvalid), 265 | .MAXIGP0ARREADY(_gp0arready), 266 | .MAXIGP0AWVALID(_gp0awvalid), 267 | .MAXIGP0AWREADY(_gp0awready), 268 | .MAXIGP0ARBURST(_gp0arburst), 269 | .MAXIGP0AWBURST(_gp0awburst), 270 | .MAXIGP0RDATA(_gp0rdata), 271 | .MAXIGP0WDATA(_gp0wdata), 272 | .MAXIGP0ARLEN(_gp0arlen), 273 | .MAXIGP0AWLEN(_gp0awlen), 274 | .MAXIGP0BRESP(_gp0bresp), 275 | .MAXIGP0ARQOS(_gp0arqos), 276 | .MAXIGP0RLAST(_gp0rlast), 277 | .FCLKRESETN(_fclkresetn), 278 | .MAXIGP0AWQOS(_gp0awqos), 279 | .MAXIGP0WLAST(_gp0wlast), 280 | .MAXIGP0RRESP(_gp0rresp), 281 | .MAXIGP0BID(_gp0bid), 282 | .MAXIGP0WSTRB(_gp0wstrb), 283 | .MAXIGP0RID(_gp0rid), 284 | .MAXIGP0WID(_gp0wid), 285 | .MAXIGP0ARADDR(_gp0araddr), 286 | .MAXIGP0BVALID(_gp0bvalid), 287 | .MAXIGP0AWADDR(_gp0awaddr), 288 | .MAXIGP0BREADY(_gp0bready), 289 | .MAXIGP0ARLOCK(_gp0arlock), 290 | .MAXIGP0AWLOCK(_gp0awlock), 291 | .MAXIGP0RVALID(_gp0rvalid), 292 | .MAXIGP0RREADY(_gp0rready), 293 | .MAXIGP0WVALID(_gp0wvalid), 294 | .MAXIGP0WREADY(_gp0wready), 295 | .MAXIGP0ARSIZE(_gp0arsize), 296 | .MAXIGP0AWSIZE(_gp0awsize), 297 | .MAXIGP0ARPROT(_gp0arprot) 298 | ); 299 | endmodule 300 | 301 | module _intercon( 302 | input wire clk, 303 | input wire rstn, 304 | input wire _outreq, 305 | input wire _outwr, 306 | output reg _outack, 307 | output reg _outerr, 308 | input wire [31:0] _outaddr, 309 | input wire [3:0] _outwstrb, 310 | input wire [31:0] _outwdata, 311 | output reg [31:0] _outrdata, 312 | output reg reg_req, 313 | input wire reg_ack, 314 | input wire reg_err, 315 | output wire [31:0] reg_addr, 316 | input wire [31:0] reg_rdata, 317 | output wire [31:0] reg_wdata, 318 | output wire reg_wr, 319 | output reg dport_reg_req, 320 | input wire dport_reg_ack, 321 | input wire dport_reg_err, 322 | output wire [31:0] dport_reg_addr, 323 | input wire [31:0] dport_reg_rdata, 324 | output wire [31:0] dport_reg_wdata, 325 | output wire dport_reg_wr, 326 | output wire [3:0] dport_reg_wstrb, 327 | output reg dport_aux_req, 328 | input wire dport_aux_ack, 329 | output wire [31:0] dport_aux_addr, 330 | input wire [31:0] dport_aux_rdata, 331 | output wire [31:0] dport_aux_wdata, 332 | output wire dport_aux_wr 333 | ); 334 | 335 | localparam IDLE = 0; 336 | localparam WAIT_reg_ = 1; 337 | localparam WAIT_dport_reg_ = 2; 338 | localparam WAIT_dport_aux_ = 3; 339 | reg [2:0] state; 340 | 341 | always @(posedge clk or negedge rstn) 342 | if(!rstn) begin 343 | state <= IDLE; 344 | _outack <= 1'b0; 345 | _outerr <= 1'b0; 346 | _outrdata <= 32'bx; 347 | reg_req <= 1'b0; 348 | dport_reg_req <= 1'b0; 349 | dport_aux_req <= 1'b0; 350 | end else begin 351 | _outack <= 1'b0; 352 | reg_req <= 1'b0; 353 | dport_reg_req <= 1'b0; 354 | dport_aux_req <= 1'b0; 355 | case(state) 356 | IDLE: 357 | if(_outreq) 358 | casez(_outaddr[29:0]) 359 | default: begin 360 | _outack <= 1'b1; 361 | _outerr <= 1'b1; 362 | end 363 | 30'b00000000000000000000000zzzzzzzz: begin 364 | state <= WAIT_reg_; 365 | reg_req <= 1'b1; 366 | end 367 | 30'b00000000000000000000001zzzzzzzz: begin 368 | state <= WAIT_dport_reg_; 369 | dport_reg_req <= 1'b1; 370 | end 371 | 30'b00000000000000000000010000zzzzz: begin 372 | state <= WAIT_dport_aux_; 373 | dport_aux_req <= 1'b1; 374 | end 375 | endcase 376 | WAIT_reg_: 377 | if(reg_ack) begin 378 | state <= IDLE; 379 | _outack <= 1'b1; 380 | _outerr <= reg_err; 381 | _outrdata <= reg_rdata; 382 | end 383 | WAIT_dport_reg_: 384 | if(dport_reg_ack) begin 385 | state <= IDLE; 386 | _outack <= 1'b1; 387 | _outerr <= dport_reg_err; 388 | _outrdata <= dport_reg_rdata; 389 | end 390 | WAIT_dport_aux_: 391 | if(dport_aux_ack) begin 392 | state <= IDLE; 393 | _outack <= 1'b1; 394 | _outerr <= 1'b0; 395 | _outrdata <= dport_aux_rdata; 396 | end 397 | endcase 398 | end 399 | 400 | assign reg_addr = _outaddr; 401 | assign reg_wr = _outwr; 402 | assign reg_wdata = _outwdata; 403 | assign dport_reg_addr = _outaddr; 404 | assign dport_reg_wr = _outwr; 405 | assign dport_reg_wdata = _outwdata; 406 | assign dport_reg_wstrb = _outwstrb; 407 | assign dport_aux_addr = _outaddr; 408 | assign dport_aux_wr = _outwr; 409 | assign dport_aux_wdata = _outwdata; 410 | endmodule 411 | -------------------------------------------------------------------------------- /aijubrd/top.xdc: -------------------------------------------------------------------------------- 1 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 2 | set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] 3 | create_clock -name FCLK -period 10.000 [get_pins {_PS7/FCLKCLK[0]}] 4 | set_property PACKAGE_PIN U5 [get_ports {refclk[0]}] 5 | set_property PACKAGE_PIN V5 [get_ports {refclk[1]}] 6 | set_property IOSTANDARD BLVDS_25 [get_ports {auxn}] 7 | set_property PACKAGE_PIN AB19 [get_ports {auxn}] 8 | set_property IOSTANDARD BLVDS_25 [get_ports {auxp}] 9 | set_property PACKAGE_PIN AB18 [get_ports {auxp}] 10 | set_property PACKAGE_PIN AA3 [get_ports {tx[0]}] 11 | set_property PACKAGE_PIN AB3 [get_ports {tx[1]}] 12 | set_property PACKAGE_PIN W2 [get_ports {tx[2]}] 13 | set_property PACKAGE_PIN Y2 [get_ports {tx[3]}] 14 | -------------------------------------------------------------------------------- /blit.v: -------------------------------------------------------------------------------- 1 | module blit 2 | #(parameter HZ = 100_000_000) 3 | ( 4 | input wire clk, 5 | 6 | input wire uart_in_valid, 7 | input wire [7:0] uart_in_data, 8 | output wire uart_in_ready, 9 | 10 | output wire uart_out_valid, 11 | output wire [7:0] uart_out_data, 12 | input wire uart_out_ready, 13 | 14 | input wire kbd_in_valid, 15 | input wire [7:0] kbd_in_data, 16 | output wire kbd_in_ready, 17 | 18 | output wire kbd_out_valid, 19 | output wire [7:0] kbd_out_data, 20 | input wire kbd_out_ready, 21 | 22 | output wire pixel_valid, 23 | output wire [15:0] pixel_data, 24 | 25 | input wire dmahstart, 26 | input wire vblank, 27 | 28 | input wire [15:0] mouse_x, 29 | input wire [15:0] mouse_y, 30 | input wire [2:0] mouse_but 31 | ); 32 | 33 | /*AUTOWIRE*/ 34 | // Beginning of automatic wires (for undeclared instantiated-module outputs) 35 | wire bootup; // From regs_i of blit_regs.v 36 | wire cpu_ack; // From bus_i of blit_bus.v 37 | wire [23:0] cpu_addr; // From cpu_i of blit_cpu.v 38 | wire cpu_err; // From bus_i of blit_bus.v 39 | wire cpu_ram_ack; // From ramarb_i of blit_ramarb.v 40 | wire [17:0] cpu_ram_addr; // From bus_i of blit_bus.v 41 | wire [15:0] cpu_ram_rdata; // From ramarb_i of blit_ramarb.v 42 | wire cpu_ram_req; // From bus_i of blit_bus.v 43 | wire [15:0] cpu_ram_wdata; // From bus_i of blit_bus.v 44 | wire cpu_ram_we; // From bus_i of blit_bus.v 45 | wire [1:0] cpu_ram_wstrb; // From bus_i of blit_bus.v 46 | wire [15:0] cpu_rdata; // From bus_i of blit_bus.v 47 | wire cpu_req; // From cpu_i of blit_cpu.v 48 | wire [15:0] cpu_wdata; // From cpu_i of blit_cpu.v 49 | wire cpu_we; // From cpu_i of blit_cpu.v 50 | wire [1:0] cpu_wstrb; // From cpu_i of blit_cpu.v 51 | wire [17:0] daddr; // From regs_i of blit_regs.v 52 | wire dma_ack; // From ramarb_i of blit_ramarb.v 53 | wire [17:0] dma_addr; // From disp_i of blit_disp.v 54 | wire [15:0] dma_rdata; // From ramarb_i of blit_ramarb.v 55 | wire dma_req; // From disp_i of blit_disp.v 56 | wire [15:0] dstat; // From regs_i of blit_regs.v 57 | wire [7:1] irq; // From regs_i of blit_regs.v 58 | wire ram_ack; // From ram_i of blit_ram.v 59 | wire [17:0] ram_addr; // From ramarb_i of blit_ramarb.v 60 | wire [15:0] ram_rdata; // From ram_i of blit_ram.v 61 | wire ram_req; // From ramarb_i of blit_ramarb.v 62 | wire [15:0] ram_wdata; // From ramarb_i of blit_ramarb.v 63 | wire ram_we; // From ramarb_i of blit_ramarb.v 64 | wire [1:0] ram_wstrb; // From ramarb_i of blit_ramarb.v 65 | wire regs_ack; // From regs_i of blit_regs.v 66 | wire [7:0] regs_addr; // From bus_i of blit_bus.v 67 | wire [15:0] regs_rdata; // From regs_i of blit_regs.v 68 | wire regs_req; // From bus_i of blit_bus.v 69 | wire [15:0] regs_wdata; // From bus_i of blit_bus.v 70 | wire regs_we; // From bus_i of blit_bus.v 71 | wire [1:0] regs_wstrb; // From bus_i of blit_bus.v 72 | wire rom_ack; // From rom_i of blit_rom.v 73 | wire [15:0] rom_addr; // From bus_i of blit_bus.v 74 | wire [15:0] rom_rdata; // From rom_i of blit_rom.v 75 | wire rom_req; // From bus_i of blit_bus.v 76 | // End of automatics 77 | 78 | blit_cpu #(.HZ(HZ)) cpu_i(/*AUTOINST*/ 79 | // Outputs 80 | .cpu_req (cpu_req), 81 | .cpu_addr (cpu_addr[23:0]), 82 | .cpu_wdata (cpu_wdata[15:0]), 83 | .cpu_wstrb (cpu_wstrb[1:0]), 84 | .cpu_we (cpu_we), 85 | // Inputs 86 | .clk (clk), 87 | .cpu_ack (cpu_ack), 88 | .cpu_rdata (cpu_rdata[15:0]), 89 | .cpu_err (cpu_err), 90 | .irq (irq[7:1])); 91 | 92 | blit_bus bus_i(/*AUTOINST*/ 93 | // Outputs 94 | .cpu_ack (cpu_ack), 95 | .cpu_rdata (cpu_rdata[15:0]), 96 | .cpu_err (cpu_err), 97 | .rom_req (rom_req), 98 | .rom_addr (rom_addr[15:0]), 99 | .cpu_ram_req (cpu_ram_req), 100 | .cpu_ram_addr (cpu_ram_addr[17:0]), 101 | .cpu_ram_wdata (cpu_ram_wdata[15:0]), 102 | .cpu_ram_wstrb (cpu_ram_wstrb[1:0]), 103 | .cpu_ram_we (cpu_ram_we), 104 | .regs_req (regs_req), 105 | .regs_addr (regs_addr[7:0]), 106 | .regs_wdata (regs_wdata[15:0]), 107 | .regs_wstrb (regs_wstrb[1:0]), 108 | .regs_we (regs_we), 109 | // Inputs 110 | .clk (clk), 111 | .cpu_req (cpu_req), 112 | .cpu_addr (cpu_addr[23:0]), 113 | .cpu_wdata (cpu_wdata[15:0]), 114 | .cpu_wstrb (cpu_wstrb[1:0]), 115 | .cpu_we (cpu_we), 116 | .rom_ack (rom_ack), 117 | .rom_rdata (rom_rdata[15:0]), 118 | .cpu_ram_ack (cpu_ram_ack), 119 | .cpu_ram_rdata (cpu_ram_rdata[15:0]), 120 | .regs_ack (regs_ack), 121 | .regs_rdata (regs_rdata[15:0]), 122 | .bootup (bootup)); 123 | 124 | blit_rom rom_i(/*AUTOINST*/ 125 | // Outputs 126 | .rom_ack (rom_ack), 127 | .rom_rdata (rom_rdata[15:0]), 128 | // Inputs 129 | .clk (clk), 130 | .rom_req (rom_req), 131 | .rom_addr (rom_addr[15:0])); 132 | 133 | blit_ram ram_i(/*AUTOINST*/ 134 | // Outputs 135 | .ram_ack (ram_ack), 136 | .ram_rdata (ram_rdata[15:0]), 137 | // Inputs 138 | .clk (clk), 139 | .ram_req (ram_req), 140 | .ram_addr (ram_addr[17:0]), 141 | .ram_wdata (ram_wdata[15:0]), 142 | .ram_wstrb (ram_wstrb[1:0]), 143 | .ram_we (ram_we)); 144 | 145 | blit_regs #(.HZ(HZ)) regs_i(/*AUTOINST*/ 146 | // Outputs 147 | .regs_ack (regs_ack), 148 | .regs_rdata (regs_rdata[15:0]), 149 | .irq (irq[7:1]), 150 | .bootup (bootup), 151 | .daddr (daddr[17:0]), 152 | .dstat (dstat[15:0]), 153 | .uart_in_ready (uart_in_ready), 154 | .uart_out_valid (uart_out_valid), 155 | .uart_out_data (uart_out_data[7:0]), 156 | .kbd_in_ready (kbd_in_ready), 157 | .kbd_out_valid (kbd_out_valid), 158 | .kbd_out_data (kbd_out_data[7:0]), 159 | // Inputs 160 | .clk (clk), 161 | .regs_req (regs_req), 162 | .regs_addr (regs_addr[7:0]), 163 | .regs_wdata (regs_wdata[15:0]), 164 | .regs_wstrb (regs_wstrb[1:0]), 165 | .regs_we (regs_we), 166 | .uart_in_valid (uart_in_valid), 167 | .uart_in_data (uart_in_data[7:0]), 168 | .uart_out_ready (uart_out_ready), 169 | .kbd_in_valid (kbd_in_valid), 170 | .kbd_in_data (kbd_in_data[7:0]), 171 | .kbd_out_ready (kbd_out_ready), 172 | .vblank (vblank), 173 | .mouse_x (mouse_x[15:0]), 174 | .mouse_y (mouse_y[15:0]), 175 | .mouse_but (mouse_but[2:0])); 176 | 177 | blit_ramarb ramarb_i(/*AUTOINST*/ 178 | // Outputs 179 | .cpu_ram_ack (cpu_ram_ack), 180 | .cpu_ram_rdata (cpu_ram_rdata[15:0]), 181 | .dma_ack (dma_ack), 182 | .dma_rdata (dma_rdata[15:0]), 183 | .ram_req (ram_req), 184 | .ram_addr (ram_addr[17:0]), 185 | .ram_wdata (ram_wdata[15:0]), 186 | .ram_wstrb (ram_wstrb[1:0]), 187 | .ram_we (ram_we), 188 | // Inputs 189 | .clk (clk), 190 | .cpu_ram_req (cpu_ram_req), 191 | .cpu_ram_addr (cpu_ram_addr[17:0]), 192 | .cpu_ram_wdata (cpu_ram_wdata[15:0]), 193 | .cpu_ram_wstrb (cpu_ram_wstrb[1:0]), 194 | .cpu_ram_we (cpu_ram_we), 195 | .dma_req (dma_req), 196 | .dma_addr (dma_addr[17:0]), 197 | .ram_ack (ram_ack), 198 | .ram_rdata (ram_rdata[15:0])); 199 | 200 | blit_disp disp_i(/*AUTOINST*/ 201 | // Outputs 202 | .dma_req (dma_req), 203 | .dma_addr (dma_addr[17:0]), 204 | .pixel_valid (pixel_valid), 205 | .pixel_data (pixel_data[15:0]), 206 | // Inputs 207 | .clk (clk), 208 | .daddr (daddr[17:0]), 209 | .dstat (dstat[15:0]), 210 | .dma_ack (dma_ack), 211 | .dma_rdata (dma_rdata[15:0]), 212 | .dmahstart (dmahstart), 213 | .vblank (vblank)); 214 | 215 | endmodule 216 | -------------------------------------------------------------------------------- /blit_bus.v: -------------------------------------------------------------------------------- 1 | module blit_bus( 2 | input wire clk, 3 | 4 | input wire cpu_req, 5 | input wire [23:0] cpu_addr, 6 | input wire [15:0] cpu_wdata, 7 | input wire [1:0] cpu_wstrb, 8 | input wire cpu_we, 9 | output reg cpu_ack, 10 | output reg [15:0] cpu_rdata, 11 | output reg cpu_err, 12 | 13 | output reg rom_req, 14 | output wire [15:0] rom_addr, 15 | input wire rom_ack, 16 | input wire [15:0] rom_rdata, 17 | 18 | output reg cpu_ram_req, 19 | output wire [17:0] cpu_ram_addr, 20 | output wire [15:0] cpu_ram_wdata, 21 | output wire [1:0] cpu_ram_wstrb, 22 | output wire cpu_ram_we, 23 | input wire cpu_ram_ack, 24 | input wire [15:0] cpu_ram_rdata, 25 | 26 | output reg regs_req, 27 | output wire [7:0] regs_addr, 28 | output wire [15:0] regs_wdata, 29 | output wire [1:0] regs_wstrb, 30 | output wire regs_we, 31 | input wire regs_ack, 32 | input wire [15:0] regs_rdata, 33 | 34 | input wire bootup 35 | ); 36 | 37 | assign rom_addr = cpu_addr[15:0]; 38 | 39 | assign cpu_ram_addr = cpu_addr[17:0]; 40 | assign cpu_ram_wdata = cpu_wdata; 41 | assign cpu_ram_wstrb = cpu_wstrb; 42 | assign cpu_ram_we = cpu_we; 43 | 44 | assign regs_addr = cpu_addr[7:0]; 45 | assign regs_wdata = cpu_wdata; 46 | assign regs_wstrb = cpu_wstrb; 47 | assign regs_we = cpu_we; 48 | 49 | reg [31:0] state; 50 | localparam IDLE = 0; 51 | localparam ROM = 1; 52 | localparam RAM = 2; 53 | localparam REGS = 3; 54 | 55 | always @(posedge clk) begin 56 | cpu_ack <= 1'b0; 57 | cpu_err <= 1'b0; 58 | rom_req <= 1'b0; 59 | cpu_ram_req <= 1'b0; 60 | regs_req <= 1'b0; 61 | case(state) 62 | IDLE: 63 | if(cpu_req) begin 64 | casez(cpu_addr) 65 | 24'b0000_00zz_zzzz_zzzz_zzzz_zzzz: 66 | if(cpu_addr < 8) begin 67 | if(bootup) begin 68 | rom_req <= 1'b1; 69 | state <= ROM; 70 | end else begin 71 | cpu_ack <= 1'b1; 72 | cpu_err <= 1'b1; 73 | end 74 | end else begin 75 | cpu_ram_req <= 1'b1; 76 | state <= RAM; 77 | end 78 | 24'h4zzzz: begin 79 | rom_req <= 1'b1; 80 | state <= ROM; 81 | end 82 | 24'h600zz: begin 83 | regs_req <= 1'b1; 84 | state <= REGS; 85 | end 86 | default: begin 87 | $display("error %o", cpu_addr); 88 | cpu_ack <= 1'b1; 89 | //cpu_err <= 1'b1; 90 | end 91 | endcase 92 | end 93 | ROM: 94 | if(rom_ack) begin 95 | cpu_ack <= 1'b1; 96 | cpu_rdata <= rom_rdata; 97 | state <= IDLE; 98 | end 99 | RAM: 100 | if(cpu_ram_ack) begin 101 | cpu_ack <= 1'b1; 102 | cpu_rdata <= cpu_ram_rdata; 103 | state <= IDLE; 104 | end 105 | REGS: 106 | if(regs_ack) begin 107 | cpu_ack <= 1'b1; 108 | cpu_rdata <= regs_rdata; 109 | state <= IDLE; 110 | end 111 | endcase 112 | end 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /blit_cpu.v: -------------------------------------------------------------------------------- 1 | module blit_cpu 2 | #(parameter HZ = 100_000_000) 3 | ( 4 | input wire clk, 5 | 6 | output reg cpu_req, 7 | output reg [23:0] cpu_addr, 8 | output reg [15:0] cpu_wdata, 9 | output reg [1:0] cpu_wstrb, 10 | output reg cpu_we, 11 | input wire cpu_ack, 12 | input wire [15:0] cpu_rdata, 13 | input wire cpu_err, 14 | 15 | input wire [7:1] irq 16 | ); 17 | 18 | wire E; 19 | 20 | /*AUTOWIRE*/ 21 | // Beginning of automatic wires (for undeclared instantiated-module outputs) 22 | wire ASn; // From fx68k_i of fx68k.v 23 | wire BGn; // From fx68k_i of fx68k.v 24 | wire FC0; // From fx68k_i of fx68k.v 25 | wire FC1; // From fx68k_i of fx68k.v 26 | wire FC2; // From fx68k_i of fx68k.v 27 | wire LDSn; // From fx68k_i of fx68k.v 28 | wire UDSn; // From fx68k_i of fx68k.v 29 | wire VMAn; // From fx68k_i of fx68k.v 30 | wire eRWn; // From fx68k_i of fx68k.v 31 | wire [23:1] eab; // From fx68k_i of fx68k.v 32 | wire [15:0] oEdb; // From fx68k_i of fx68k.v 33 | wire oHALTEDn; // From fx68k_i of fx68k.v 34 | wire oRESETn; // From fx68k_i of fx68k.v 35 | // End of automatics 36 | 37 | localparam CPUHZ = 8_000_000; 38 | /* verilator lint_off WIDTH */ 39 | /* verilator lint_off WIDTHCONCAT */ 40 | localparam [15:0] CPUDIV = {2 * CPUHZ, 16'b0} / HZ; 41 | /* verilator lint_on WIDTH */ 42 | /* verilator lint_on WIDTHCONCAT */ 43 | 44 | reg [15:0] div; 45 | reg tick; 46 | reg phase; 47 | reg enPhi1; 48 | reg enPhi2; 49 | 50 | always @(posedge clk) begin 51 | {tick, div} <= div + CPUDIV; 52 | enPhi1 <= 1'b0; 53 | enPhi2 <= 1'b0; 54 | if(tick) begin 55 | if(phase) 56 | enPhi2 <= 1'b1; 57 | else 58 | enPhi1 <= 1'b1; 59 | phase <= !phase; 60 | end 61 | end 62 | 63 | reg extReset; 64 | wire pwrUp = extReset; 65 | reg [3:0] resctr; 66 | 67 | initial begin 68 | extReset = 1'b1; 69 | resctr = 4'd15; 70 | end 71 | always @(posedge clk) begin 72 | if(enPhi1 && resctr > 0) 73 | resctr <= resctr - 1; 74 | else 75 | extReset <= 1'b0; 76 | end 77 | 78 | reg DTACKn = 1'b1; 79 | reg BERRn = 1'b1; 80 | reg VPAn = 1'b1; 81 | wire BRn = 1'b1; 82 | wire BGACKn = 1'b1; 83 | 84 | reg [15:0] iEdb; 85 | reg [3:0] state; 86 | reg [2:0] IPLn = 3'b111; 87 | wire IPL0n = IPLn[0]; 88 | wire IPL1n = IPLn[1]; 89 | wire IPL2n = IPLn[2]; 90 | 91 | always @(posedge clk) begin 92 | case(state) 93 | 0: if(!extReset && (!UDSn || !LDSn)) begin 94 | if(FC0 && FC1 && FC2) begin 95 | VPAn <= 1'b0; 96 | state <= 2; 97 | end else begin 98 | cpu_req <= 1'b1; 99 | cpu_addr <= {eab, 1'b0}; 100 | cpu_wdata <= oEdb; 101 | cpu_we <= !eRWn; 102 | cpu_wstrb <= {!UDSn, !LDSn}; 103 | state <= 1; 104 | end 105 | end 106 | 1: begin 107 | cpu_req <= 1'b0; 108 | if(cpu_ack) begin 109 | if(cpu_err) 110 | BERRn <= 1'b0; 111 | else 112 | DTACKn <= 1'b0; 113 | iEdb <= cpu_rdata; 114 | state <= 2; 115 | end 116 | end 117 | 2: begin 118 | if(UDSn && LDSn) begin 119 | DTACKn <= 1'b1; 120 | BERRn <= 1'b1; 121 | VPAn <= 1'b1; 122 | state <= 0; 123 | end 124 | end 125 | endcase 126 | end 127 | 128 | always @(posedge clk) begin 129 | case(1'b1) 130 | irq[7]: IPLn <= 3'b000; 131 | irq[6]: IPLn <= 3'b001; 132 | irq[5]: IPLn <= 3'b010; 133 | irq[4]: IPLn <= 3'b011; 134 | irq[3]: IPLn <= 3'b100; 135 | irq[2]: IPLn <= 3'b101; 136 | irq[1]: IPLn <= 3'b110; 137 | default: IPLn <= 3'b111; 138 | endcase 139 | end 140 | 141 | fx68k fx68k_i( 142 | /*AUTOINST*/ 143 | // Outputs 144 | .eRWn (eRWn), 145 | .ASn (ASn), 146 | .LDSn (LDSn), 147 | .UDSn (UDSn), 148 | .E (E), 149 | .VMAn (VMAn), 150 | .FC0 (FC0), 151 | .FC1 (FC1), 152 | .FC2 (FC2), 153 | .BGn (BGn), 154 | .oRESETn (oRESETn), 155 | .oHALTEDn (oHALTEDn), 156 | .oEdb (oEdb[15:0]), 157 | .eab (eab[23:1]), 158 | // Inputs 159 | .clk (clk), 160 | .extReset (extReset), 161 | .pwrUp (pwrUp), 162 | .enPhi1 (enPhi1), 163 | .enPhi2 (enPhi2), 164 | .DTACKn (DTACKn), 165 | .VPAn (VPAn), 166 | .BERRn (BERRn), 167 | .BRn (BRn), 168 | .BGACKn (BGACKn), 169 | .IPL0n (IPL0n), 170 | .IPL1n (IPL1n), 171 | .IPL2n (IPL2n), 172 | .iEdb (iEdb[15:0])); 173 | 174 | endmodule 175 | -------------------------------------------------------------------------------- /blit_disp.v: -------------------------------------------------------------------------------- 1 | module blit_disp 2 | ( 3 | input wire clk, 4 | 5 | input wire [17:0] daddr, 6 | input wire [15:0] dstat, 7 | 8 | output reg dma_req, 9 | output reg [17:0] dma_addr, 10 | input wire dma_ack, 11 | input wire [15:0] dma_rdata, 12 | 13 | input wire dmahstart, 14 | input wire vblank, 15 | 16 | output reg pixel_valid, 17 | output reg [15:0] pixel_data 18 | ); 19 | 20 | reg [7:0] ctr; 21 | reg dma_issued; 22 | 23 | always @(posedge clk) begin 24 | if(vblank) begin 25 | dma_addr <= daddr; 26 | end 27 | if(dmahstart) begin 28 | ctr <= 50; 29 | end 30 | dma_req <= 1'b0; 31 | pixel_valid <= 1'b0; 32 | if(!dma_issued) begin 33 | if(ctr > 0) begin 34 | dma_req <= 1'b1; 35 | dma_issued <= 1'b1; 36 | end 37 | end else begin 38 | if(dma_ack) begin 39 | dma_issued <= 1'b0; 40 | pixel_valid <= 1'b1; 41 | pixel_data <= dma_rdata; 42 | dma_addr <= dma_addr + 2; 43 | ctr <= ctr - 1; 44 | end 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /blit_ram.v: -------------------------------------------------------------------------------- 1 | module blit_ram( 2 | input wire clk, 3 | 4 | input wire ram_req, 5 | input wire [17:0] ram_addr, 6 | input wire [15:0] ram_wdata, 7 | input wire [1:0] ram_wstrb, 8 | input wire ram_we, 9 | output reg ram_ack, 10 | output reg [15:0] ram_rdata 11 | ); 12 | 13 | reg [7:0] raml[0:131071]; 14 | reg [7:0] ramh[0:131071]; 15 | 16 | always @(posedge clk) begin 17 | ram_ack <= 1'b0; 18 | if(ram_req) begin 19 | ram_ack <= 1'b1; 20 | if(ram_we) begin 21 | if(ram_wstrb[0]) 22 | raml[ram_addr[17:1]] <= ram_wdata[7:0]; 23 | if(ram_wstrb[1]) 24 | ramh[ram_addr[17:1]] <= ram_wdata[15:8]; 25 | end else begin 26 | ram_rdata <= {ramh[ram_addr[17:1]], raml[ram_addr[17:1]]}; 27 | end 28 | end 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /blit_ramarb.v: -------------------------------------------------------------------------------- 1 | module blit_ramarb( 2 | input wire clk, 3 | 4 | input wire cpu_ram_req, 5 | input wire [17:0] cpu_ram_addr, 6 | input wire [15:0] cpu_ram_wdata, 7 | input wire [1:0] cpu_ram_wstrb, 8 | input wire cpu_ram_we, 9 | output reg cpu_ram_ack, 10 | output reg [15:0] cpu_ram_rdata, 11 | 12 | input wire dma_req, 13 | input wire [17:0] dma_addr, 14 | output reg dma_ack, 15 | output reg [15:0] dma_rdata, 16 | 17 | output reg ram_req, 18 | output reg [17:0] ram_addr, 19 | output wire [15:0] ram_wdata, 20 | output wire [1:0] ram_wstrb, 21 | output reg ram_we, 22 | input wire ram_ack, 23 | input wire [15:0] ram_rdata 24 | ); 25 | 26 | assign ram_wdata = cpu_ram_wdata; 27 | assign ram_wstrb = cpu_ram_wstrb; 28 | 29 | reg cpu_ram_pending, cpu_ram_issued; 30 | reg dma_pending, dma_issued; 31 | 32 | always @(posedge clk) begin 33 | ram_req <= 1'b0; 34 | cpu_ram_ack <= 1'b0; 35 | dma_ack <= 1'b0; 36 | 37 | if(dma_req || dma_pending) begin 38 | if(cpu_ram_issued || dma_issued) begin 39 | dma_pending <= 1'b1; 40 | end else begin 41 | ram_req <= 1'b1; 42 | ram_addr <= dma_addr; 43 | ram_we <= 1'b0; 44 | dma_issued <= 1'b1; 45 | dma_pending <= 1'b0; 46 | end 47 | end 48 | if(cpu_ram_req || cpu_ram_pending) begin 49 | if(dma_req || dma_pending || cpu_ram_issued || dma_issued) begin 50 | cpu_ram_pending <= 1'b1; 51 | end else begin 52 | ram_req <= 1'b1; 53 | ram_addr <= cpu_ram_addr; 54 | ram_we <= cpu_ram_we; 55 | cpu_ram_issued <= 1'b1; 56 | cpu_ram_pending <= 1'b0; 57 | end 58 | end 59 | if(ram_ack) begin 60 | if(cpu_ram_issued) begin 61 | cpu_ram_ack <= 1'b1; 62 | cpu_ram_rdata <= ram_rdata; 63 | cpu_ram_issued <= 1'b0; 64 | end 65 | if(dma_issued) begin 66 | dma_ack <= 1'b1; 67 | dma_rdata <= ram_rdata; 68 | dma_issued <= 1'b0; 69 | end 70 | end 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /blit_regs.v: -------------------------------------------------------------------------------- 1 | module blit_regs 2 | #(parameter HZ = 100_000_000) 3 | ( 4 | input wire clk, 5 | 6 | input wire regs_req, 7 | input wire [7:0] regs_addr, 8 | input wire [15:0] regs_wdata, 9 | input wire [1:0] regs_wstrb, 10 | input wire regs_we, 11 | output reg regs_ack, 12 | output reg [15:0] regs_rdata, 13 | 14 | output wire [7:1] irq, 15 | 16 | output reg bootup, 17 | 18 | output reg [17:0] daddr, 19 | output reg [15:0] dstat, 20 | 21 | input wire uart_in_valid, 22 | input wire [7:0] uart_in_data, 23 | output reg uart_in_ready, 24 | 25 | output reg uart_out_valid, 26 | output reg [7:0] uart_out_data, 27 | input wire uart_out_ready, 28 | 29 | input wire kbd_in_valid, 30 | input wire [7:0] kbd_in_data, 31 | output reg kbd_in_ready, 32 | 33 | output reg kbd_out_valid, 34 | output reg [7:0] kbd_out_data, 35 | input wire kbd_out_ready, 36 | 37 | input wire vblank, 38 | 39 | input wire [15:0] mouse_x, 40 | input wire [15:0] mouse_y, 41 | input wire [2:0] mouse_but 42 | ); 43 | 44 | localparam BAUD = 40000; 45 | /* verilator lint_off WIDTH */ 46 | localparam [15:0] UARTTIM = HZ / (BAUD * 11); 47 | /* verilator lint_on WIDTH */ 48 | reg [15:0] uartrxctr; 49 | wire uartblock = uartrxctr > 0; 50 | always @(posedge clk) begin 51 | if(uartrxctr > 0) 52 | uartrxctr <= uartrxctr - 1; 53 | if(uart_in_valid && uart_in_ready) 54 | uartrxctr <= UARTTIM; 55 | end 56 | 57 | wire [15:0] mask = {{8{regs_wstrb[1]}}, {8{regs_wstrb[0]}}}; 58 | 59 | reg [7:0] uartctrl; 60 | wire uart_rx_irq_en = uartctrl[7]; 61 | wire uart_tx_irq_en = uartctrl[6:5] == 2'b01; 62 | wire [7:0] uartstat = {6'b0, !uart_out_valid || uart_out_ready, uart_in_valid && !uartblock}; 63 | 64 | reg [7:0] kbdctrl; 65 | wire kbd_rx_irq_en = kbdctrl[7]; 66 | wire kbd_tx_irq_en = kbdctrl[6:5] == 2'b01; 67 | wire [7:0] kbdstat = {6'b0, !kbd_out_valid || kbd_out_ready, kbd_in_valid}; 68 | 69 | reg vblank_irq; 70 | reg mouse_irq; 71 | assign irq = { 72 | 1'b0, 73 | 1'b0, 74 | uart_tx_irq_en && (!uart_out_valid || uart_out_ready) || uart_rx_irq_en && uart_in_valid && !uartblock, 75 | mouse_irq, 76 | 1'b0, 77 | kbd_tx_irq_en && (!kbd_out_valid || kbd_out_ready) || kbd_rx_irq_en && kbd_in_valid, 78 | vblank_irq 79 | }; 80 | 81 | initial bootup = 1'b1; 82 | 83 | reg [2:0] mouse_but_last; 84 | always @(posedge clk) begin 85 | if(uart_out_valid && uart_out_ready) 86 | uart_out_valid <= 1'b0; 87 | if(kbd_out_valid && kbd_out_ready) 88 | kbd_out_valid <= 1'b0; 89 | regs_ack <= regs_req; 90 | uart_in_ready <= 1'b0; 91 | kbd_in_ready <= 1'b0; 92 | 93 | if(regs_req && regs_we) begin 94 | case(regs_addr) 95 | 8'o10: uartctrl <= regs_wdata[7:0]; 96 | 8'o12: begin 97 | if(!uart_out_valid || uart_out_ready) begin 98 | uart_out_valid <= 1'b1; 99 | uart_out_data <= regs_wdata[7:0]; 100 | end 101 | end 102 | 8'o30: daddr[17:2] <= daddr[17:2] & ~mask | regs_wdata & mask; 103 | 8'o40: dstat <= dstat & ~mask | dstat & mask; 104 | 8'o24, 8'o26: begin end 105 | 8'o60: kbdctrl <= regs_wdata[7:0]; 106 | 8'o62: begin 107 | if(!kbd_out_valid || kbd_out_ready) begin 108 | kbd_out_valid <= 1'b1; 109 | kbd_out_data <= regs_wdata[7:0]; 110 | end 111 | end 112 | 8'o70: vblank_irq <= 1'b0; 113 | default: $display("write to %o = %h", regs_addr, regs_wdata); 114 | endcase 115 | end else if(regs_req && !regs_we) begin 116 | case(regs_addr) 117 | 8'o0: regs_rdata <= mouse_y; 118 | 8'o2: regs_rdata <= mouse_x; 119 | 8'o10: regs_rdata <= {2{uartstat}}; 120 | 8'o12: begin 121 | regs_rdata <= {2{uart_in_data}}; 122 | uart_in_ready <= !uartblock; 123 | end 124 | 8'o20, 8'o24: begin 125 | mouse_irq <= 1'b0; 126 | regs_rdata <= {2{{5'b0, mouse_but}}}; 127 | end 128 | 8'o30: regs_rdata <= daddr[17:2]; 129 | 8'o40: regs_rdata <= dstat; 130 | 8'o60: regs_rdata <= {2{kbdstat}}; 131 | 8'o62: begin 132 | regs_rdata <= {2{kbd_in_data}}; 133 | kbd_in_ready <= 1'b1; 134 | end 135 | 8'o26: begin end 136 | default: $display("read from %o", regs_addr); 137 | endcase 138 | end 139 | if(vblank) vblank_irq <= 1'b1; 140 | if(mouse_but != mouse_but_last) mouse_irq <= 1'b1; 141 | mouse_but_last <= mouse_but; 142 | end 143 | 144 | endmodule 145 | -------------------------------------------------------------------------------- /blit_rom.v: -------------------------------------------------------------------------------- 1 | module blit_rom( 2 | input wire clk, 3 | 4 | input wire rom_req, 5 | input wire [15:0] rom_addr, 6 | output reg rom_ack, 7 | output reg [15:0] rom_rdata 8 | ); 9 | 10 | reg [15:0] rom[0:24575]; 11 | 12 | initial begin 13 | $readmemh("rom.mem", rom); 14 | `ifdef VERILATOR 15 | rom[109] = 1; 16 | `endif 17 | end 18 | 19 | always @(posedge clk) begin 20 | rom_ack <= rom_req; 21 | if(rom_req) begin 22 | rom_rdata <= rom[rom_addr[15:1]]; 23 | end 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /fx68k_microrom.mem: -------------------------------------------------------------------------------- 1 | 10010000101100000 2 | 10000100000000000 3 | 00101001011010000 4 | 00111110011000000 5 | 01000000000001100 6 | 01000000000001100 7 | 01000010010000000 8 | 10001100011100000 9 | 01000100010000000 10 | 10000000010000000 11 | 10000000010000000 12 | 01000100010000000 13 | 00001010010000000 14 | 10000000100000000 15 | 10000000100000000 16 | 01101001100000000 17 | 00000000000000000 18 | 00000000000000000 19 | 00000000000000000 20 | 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00000001000001000000000001001000000100000000000001010000000001011001 306 | 00100000000000001000001000000000100000000000000010000100000010000000 307 | 11000001000000000000010000001001001000010000000101000000000000110001 308 | 00000000000110000000000001000000100000000000000101000100000100010000 309 | 00000000000101000000000001000000100000000000000101000100000100010000 310 | 00000000000010100000000001010000000100000000000101000000000000010000 311 | 00000000000101000000000001001010000100000000000001010000000001011001 312 | 11100101001000011100000000000000010000010000010010001000000000100000 313 | 00100000000000001000000000001000001000000000000110000000000000110001 314 | 00100000000000011000000000000000100000000100011100000101000100011000 315 | 00100000000000011000000000010000110100000000011100000101000100011000 316 | 01100011100000011000000100010010000000000000000101110000000000000011 317 | 01100010000000011000010100000000010000000000001100000001000000011000 318 | 10000000000100100000000001001000000100010000000001000000000001011001 319 | 01100010000000011000010100000010010000000000001100110001000100011000 320 | 01100011000000011000010000010000000100000000011101110000000001011000 321 | 00000000000000000000010000000000100000000110000101000000000000010000 322 | 00000000000000000000000000000000000000011100001110000000000000011000 323 | 10100000000000001000010000001000101000000110000101000000000000100001 324 | 00100000000000011000000000110001100100001111011001100000000011000010 325 | 00000001000000000000010000000001100001001010000101000010100010010000 326 | 00100010001000111000010000010000000100000000011101000000000001010000 327 | 00100100000100111100000000000000000000000000000101000000000000010000 328 | 00100010000100011000010001010000000100000000011100010000000001010000 329 | 01000001000000000000000100010000011000000000000010000000000000000000 330 | 00000000000000000000010000000000100010000000000101000010001000010000 331 | 00100000000100111000000000000000100000000010000100100000000000010000 332 | 00100010000000011000010000001000001000000000000101000000000000110001 333 | 00000001000000000000010000000000100000000000000101000100000010010000 334 | 00000000000000000000000000000000000000000000000010000000000000000000 335 | 00000000000000000000001000000000100100000000000000110010000001011000 336 | 00000000011000000000000000000010110110000000001100000000001101011000 337 | -------------------------------------------------------------------------------- /run.sh: -------------------------------------------------------------------------------- 1 | verilator $* -CFLAGS "`sdl2-config --cflags`" -LDFLAGS "`sdl2-config --libs`" --cc blit.v -Wno-fatal --exe sim.cc && make -j -C obj_dir -f Vblit.mk && obj_dir/Vblit 2 | -------------------------------------------------------------------------------- /sim.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include "Vblit.h" 7 | #if VM_TRACE 8 | #include "verilated_vcd_c.h" 9 | #else 10 | #include "verilated.h" 11 | #endif 12 | 13 | std::list kbd; 14 | std::list uart; 15 | Vblit *tb; 16 | 17 | void putuart(char c) 18 | { 19 | uart.push_back(c); 20 | if(!tb->uart_in_valid){ 21 | tb->uart_in_valid = 1; 22 | tb->uart_in_data = c; 23 | } 24 | } 25 | 26 | void putkbd(char c) 27 | { 28 | kbd.push_back(c); 29 | if(!tb->kbd_in_valid){ 30 | tb->kbd_in_valid = 1; 31 | tb->kbd_in_data = c; 32 | } 33 | } 34 | 35 | int main(int argc, char **argv) { 36 | Verilated::commandArgs(argc, argv); 37 | tb = new Vblit; 38 | char c; 39 | while(read(0, &c, 1) > 0) 40 | putuart(c); 41 | 42 | if(SDL_Init(SDL_INIT_VIDEO) < 0) 43 | errx(1, "SDL_Init failed"); 44 | SDL_Window *window; 45 | SDL_Renderer *renderer; 46 | if(SDL_CreateWindowAndRenderer(800, 1024, 0, &window, &renderer) < 0) 47 | errx(1, "SDL_CreateWindowAndRenderer failed"); 48 | SDL_Surface *screen = SDL_GetWindowSurface(window); 49 | SDL_RenderClear(renderer); 50 | SDL_RenderPresent(renderer); 51 | 52 | #if VM_TRACE 53 | Verilated::traceEverOn(true); 54 | VerilatedVcdC *tfp = new VerilatedVcdC; 55 | tb->trace(tfp, 99); 56 | tfp->open("simx.vcd"); 57 | #endif 58 | 59 | int pixx = 0, pixy = 0, toggle = 1; 60 | 61 | tb->uart_out_ready = 0; 62 | tb->kbd_out_ready = 1; 63 | 64 | const int rowdiv = 65536.0 * 1060 * 60 / 100e6; 65 | int rowctr = 0; 66 | int y = 0; 67 | for(int t = 0; !Verilated::gotFinish(); t++) { 68 | SDL_Event ev; 69 | if((t & 0xff) == 0) 70 | while(SDL_PollEvent(&ev)){ 71 | switch(ev.type){ 72 | case SDL_TEXTINPUT: { 73 | for(char *p = ev.text.text; *p != 0; p++) 74 | putkbd(*p); 75 | break; 76 | } 77 | case SDL_QUIT: return 0; 78 | } 79 | } 80 | if(!tb->clk){ 81 | rowctr += rowdiv; 82 | if((rowctr>>16) != 0){ 83 | rowctr -= 1<<16; 84 | tb->dmahstart = y < 1024; 85 | tb->vblank = y == 1024; 86 | if(++y == 1060) y = 0; 87 | }else{ 88 | tb->dmahstart = 0; 89 | tb->vblank = 0; 90 | } 91 | if(tb->pixel_valid){ 92 | for(int i = 0; i < 16; i++){ 93 | int c = (tb->pixel_data & 1<<15-i) ? (toggle ? 200 : 255) : (toggle ? 55 : 0); 94 | SDL_SetRenderDrawColor(renderer, c, c, c, 255); 95 | SDL_RenderDrawPoint(renderer, pixx, pixy); 96 | pixx++; 97 | } 98 | if(pixx == 800){ 99 | pixx = 0; 100 | SDL_RenderPresent(renderer); 101 | if(pixy == 1023){ 102 | pixy = 0; 103 | toggle = !toggle; 104 | }else 105 | pixy++; 106 | } 107 | } 108 | if(tb->uart_in_valid && tb->uart_in_ready){ 109 | uart.pop_front(); 110 | if(uart.size() > 0) 111 | tb->uart_in_data = uart.front(); 112 | else 113 | tb->uart_in_valid = 0; 114 | } 115 | tb->uart_out_ready = t % 200 == 0; 116 | if(tb->uart_out_valid && tb->uart_out_ready) 117 | putuart(tb->uart_out_data); 118 | if(tb->kbd_in_valid && tb->kbd_in_ready){ 119 | kbd.pop_front(); 120 | if(kbd.size() > 0) 121 | tb->kbd_in_data = kbd.front(); 122 | else 123 | tb->kbd_in_valid = 0; 124 | } 125 | } 126 | tb->clk = !tb->clk; 127 | tb->eval(); 128 | #if VM_TRACE 129 | tfp->dump(t); 130 | #endif 131 | } 132 | #if VM_TRACE 133 | tfp->close(); 134 | #endif 135 | 136 | return 0; 137 | } 138 | --------------------------------------------------------------------------------