├── .github ├── FUNDING.yml └── ISSUE_TEMPLATE │ └── module-request.md ├── .gitignore ├── Adders ├── FA.v ├── HA.v ├── nBitCarryLookAheadAdder.v └── nBitRippleCarryAdder.v ├── CONTRIBUTING.md ├── Counters ├── nBitCounter.v └── nBitJohnsonCounter.v ├── FFs ├── DFF │ ├── DFF.v │ ├── DFF_AsyncClear.v │ └── DFF_SyncClear.v ├── JKFF │ ├── JKFF.v │ ├── JKFF_AsyncClear.v │ └── JKFF_SyncClear.v └── TFF │ ├── TFF.v │ ├── TFF_AsyncClear.v │ └── TFF_SyncClear.v ├── LICENSE ├── Multiplexers and De-Multiplexers ├── deMUX1To2n.v └── mux2nTo1.v ├── Multipliers ├── boothMultiplier4Bit.v ├── serialParallelMultiplier4Bit.v └── wallaceTreeMultiplier8Bit.v ├── README.md ├── barrelShifterNBit.v ├── clkDivider.v ├── clock.v ├── dLatch.v ├── designExampleDDMano.v ├── fifo.v ├── lfsr.v ├── memory.v ├── nBitShiftRegister.v ├── patternDetector.v ├── switchDebouncer.v ├── testbench.v └── twoComplementer.v /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | liberapay: aklsh 2 | ko_fi: aklsh 3 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/module-request.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Module request 3 | about: Suggest an idea for this project 4 | title: "[REQUEST]" 5 | labels: enhancement 6 | assignees: aklsh 7 | 8 | --- 9 | 10 | **Describe the behaviour of the module** 11 | A clear and concise description of what the module should do 12 | 13 | **Describe any progress you have made** 14 | A clear and concise description of any alternative solutions or features you've considered. 15 | 16 | **Additional context** 17 | Add any other context or screenshots about the feature request here. 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.vcd 2 | .hdl_checker/ 3 | *.o 4 | *.out 5 | -------------------------------------------------------------------------------- /Adders/FA.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: FA.v 6 | // Modified: 2020-07-16 7 | // Description: 1-Bit Full Adder module 8 | // - Uses primitives for sum and carry outputs 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | primitive carryOut (output Cout, input A, input B, input Cin); 19 | 20 | // Truth Table for carry out 21 | table 22 | // A B Cin Cout 23 | 1 1 ? : 1 ; 24 | 1 ? 1 : 1 ; 25 | ? 1 1 : 1 ; 26 | 0 0 ? : 0 ; 27 | 0 ? 0 : 0 ; 28 | ? 0 0 : 0 ; 29 | endtable 30 | endprimitive 31 | 32 | primitive sumOut (output sum, input A, input B, input Cin); 33 | 34 | // Truth Table for sum 35 | table 36 | // A B Cin sum 37 | 1 1 1 : 1 ; 38 | 1 0 0 : 1 ; 39 | 0 1 0 : 1 ; 40 | 0 0 1 : 1 ; 41 | 0 0 0 : 0 ; 42 | 0 1 1 : 0 ; 43 | 1 0 1 : 0 ; 44 | 1 1 0 : 0 ; 45 | endtable 46 | endprimitive 47 | 48 | module FA(output Cout, output sum, input A, input B, input Cin); 49 | 50 | // instantiating sum and carry primitives 51 | sumOut s(sum, A, B, Cin); 52 | carryOut co(Cout, A, B, Cin); 53 | endmodule 54 | -------------------------------------------------------------------------------- /Adders/HA.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: HA.v 6 | // Modified: 2020-07-16 7 | // Description: 1-Bit Half Adder Module 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | primitive outSum(output sum, input A, input B); 19 | 20 | // Truth Table for sum 21 | table 22 | // A B sum 23 | 0 0 : 0 ; 24 | 0 1 : 1 ; 25 | 1 0 : 1 ; 26 | 1 1 : 0 ; 27 | endtable 28 | endprimitive 29 | 30 | primitive outCarry(output carry, input A, input B); 31 | 32 | // Truth Table for carry out 33 | table 34 | // A B carry 35 | 0 0 : 0 ; 36 | 0 1 : 0 ; 37 | 1 0 : 0 ; 38 | 1 1 : 1 ; 39 | endtable 40 | endprimitive 41 | 42 | module HA (output carry, output sum, input A, input B); 43 | 44 | // instantiating sum and carry primitives 45 | outSum s(sum, A, B); 46 | outCarry c(carry, A, B); 47 | endmodule 48 | -------------------------------------------------------------------------------- /Adders/nBitCarryLookAheadAdder.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: nBitCarryLookAheadAdder.v 6 | // Modified: 2020-07-16 7 | // Description: N-Bit Carry Look Ahead Adder 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module nBitCarryLookAheadAdder #(parameter n = 4)(output[n:0] total, input[n-1:0] A, input[n-1:0] B); 19 | 20 | wire[n-1:0] gi, pi, sum; 21 | wire[n:0] ci; 22 | 23 | assign ci[0] = 1'b0; 24 | 25 | genvar i; 26 | generate 27 | for(i = 0;i < n;i = i+1) begin: giAndpi 28 | assign gi[i] = A[i]&B[i]; 29 | assign pi[i] = A[i]^B[i]; 30 | assign ci[i+1] = gi[i]|(pi[i]&ci[i]); 31 | end 32 | endgenerate 33 | 34 | genvar j; 35 | generate 36 | for(j = 0;j < n;j = j+1) begin: calculation 37 | FA adder(.Cout(), .sum(sum[j]), .A(A[j]), .B(B[j]), .Cin(ci[j])); 38 | end 39 | endgenerate 40 | 41 | assign total = {ci[n], sum[n-1:0]}; 42 | endmodule 43 | -------------------------------------------------------------------------------- /Adders/nBitRippleCarryAdder.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: nBitRippleCarryAdder.v 6 | // Modified: 2020-07-16 7 | // Description: N-Bit Ripple Carry Adder 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module nBitRippleCarryAdder #(parameter n = 4)(output[n:0] total, input[n-1:0] A, input[n-1:0] B); 19 | 20 | wire[n-1:0] carryMiddle, sum; 21 | 22 | genvar i; 23 | generate 24 | for(i = 0;i < n;i = i+1) begin: genAdder 25 | if(i == 0) 26 | HA f(carryMiddle[0], sum[0], A[0], B[0]); 27 | else 28 | FA f(carryMiddle[i], sum[i], A[i], B[i], carryMiddle[i-1]); 29 | end 30 | endgenerate 31 | 32 | assign total = {carryMiddle[n-1], sum[n-1:0]}; 33 | endmodule 34 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing 2 | 1. A file should contain only one module. It can have more than one primitives though. 3 | 3. Module name and file name have to be the same. 4 | 132. In module definitions, output ports have to be declared first, followed by inout ports and then input ports. Same goes with primitives too. 5 | 12. Use camelCase for names. 6 | 4. Please try to make the module as general as possible using parameters. (It's fine if it isn't though) 7 | -------------------------------------------------------------------------------- /Counters/nBitCounter.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: nBitCounter.v 6 | // Modified: 2020-07-16 7 | // Description: N-Bit Counter, with customisable increment 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module nBitCounter #(parameter n = 32, parameter inc = 1, parameter seed = 0) (output reg[n-1:0] count, input clk, input rst, input[n-1:0] pl, input load); 19 | 20 | // initially set count to start/seed 21 | initial begin 22 | count = seed; 23 | end 24 | 25 | always @ (posedge clk, rst, load) begin 26 | // if load input is active, stop counting and take in the load 27 | if(load) 28 | count = pl; 29 | 30 | // if reset is active, reset to 0 31 | else if(rst) 32 | count = 0; 33 | 34 | // else, increment count by increment value 35 | else 36 | count = count + inc; 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /Counters/nBitJohnsonCounter.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: nBitJohnsonCounter.v 6 | // Modified: 2020-07-16 7 | // Description: N-Bit Johnson Counter 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module nBitJohnsonCounter #(parameter integer n = 8) (output reg[n-1:0] JC, input clk); 19 | 20 | // initially feed in 1 to register 21 | initial begin 22 | JC = 1; 23 | end 24 | 25 | // every clock edge, shift the bit to right nd connect inverted o/p of last to i/p of first 26 | always @(posedge clk) begin 27 | JC = {~JC[0], JC[n-1:1]}; 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /FFs/DFF/DFF.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: DFF.v 6 | // Modified: 2020-07-16 7 | // Description: D-Flip Flop 8 | // - No Clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module DFF(output reg Q, input D, input clk); 19 | // DFF is positive edge-triggered 20 | always@(posedge clk) begin 21 | Q <= D; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /FFs/DFF/DFF_AsyncClear.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: DFF_AsyncClear.v 6 | // Modified: 2020-07-16 7 | // Description: D-Flip Flop 8 | // - Asynchronous Clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module DFF_AsyncClear(output reg Q, input D, input clk, input clr); 19 | 20 | // DFF is positive edge-triggered 21 | always @ (posedge clk, clr) begin 22 | // if clr becomes 1, immediately clear FF o/p to 0 23 | if(clr) 24 | Q <= 1'b0; 25 | else 26 | Q <= D; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /FFs/DFF/DFF_SyncClear.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: DFF_SyncClear.v 6 | // Modified: 2020-07-16 7 | // Description: D-Flip Flop 8 | // - Synchronous Clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module DFF_SyncClear(output reg Q, input D, input clk, input clr); 19 | 20 | // DFF is positive edge-triggered 21 | always @ (posedge clk) begin 22 | // check if clr is 1, ONLY AT POSITIVE CLOCK EDGE, then clear o/p 23 | if(clr) 24 | Q = 1'b0; 25 | else 26 | Q = D; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /FFs/JKFF/JKFF.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: JKFF.v 6 | // Modified: 2020-07-16 7 | // Description: J-K Flip Flop 8 | // - No clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module JKFF (output reg Q, input J, input K, input clk); 19 | 20 | initial begin 21 | Q = 0; 22 | end 23 | 24 | always @ (posedge clk) begin 25 | case({J,K}) 26 | 2'b00: Q <= Q; 27 | 2'b01: Q <= 0; 28 | 2'b10: Q <= 1; 29 | 2'b11: Q <= ~Q; 30 | endcase 31 | end 32 | endmodule 33 | -------------------------------------------------------------------------------- /FFs/JKFF/JKFF_AsyncClear.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: JKFF_AsyncClear.v 6 | // Modified: 2020-07-16 7 | // Description: J-K Flip Flop 8 | // - Asynchronous clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module JKFF_AsyncClear (output reg Q, input J, input K, input clr, input clk); 19 | 20 | initial begin 21 | Q = 0; 22 | end 23 | 24 | always @ (posedge clk, posedge clr) begin 25 | if(clr) 26 | Q <= 0; 27 | else begin 28 | case({J,K}) 29 | 2'b00: Q <= Q; 30 | 2'b01: Q <= 0; 31 | 2'b10: Q <= 1; 32 | 2'b11: Q <= ~Q; 33 | endcase 34 | end 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /FFs/JKFF/JKFF_SyncClear.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: JKFF_SyncClear.v 6 | // Modified: 2020-07-16 7 | // Description: J-K Flip Flop 8 | // - Synchronous clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module JKFF_SyncClear (output reg Q, input J, input K, input clr, input clk); 19 | 20 | initial begin 21 | Q = 0; 22 | end 23 | 24 | always @ (posedge clk) begin 25 | if(clr) 26 | Q <= 0; 27 | else begin 28 | case({J,K}) 29 | 2'b00: Q <= Q; 30 | 2'b01: Q <= 0; 31 | 2'b10: Q <= 1; 32 | 2'b11: Q <= ~Q; 33 | endcase 34 | end 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /FFs/TFF/TFF.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: TFF.v 6 | // Modified: 2020-07-16 7 | // Description: T-Flip Flop 8 | // - No Clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module TFF (output reg Q, input T, input clk); 19 | 20 | initial begin 21 | Q = 0; 22 | end 23 | 24 | always @ (posedge clk) begin 25 | Q <= Q ^ T; 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /FFs/TFF/TFF_AsyncClear.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: TFF_AsyncClear.v 6 | // Modified: 2020-07-16 7 | // Description: T-Flip Flop 8 | // - Asynchronous Clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module TFF_AsyncClear (output reg Q, input T, input clr, input clk); 19 | 20 | initial begin 21 | Q = 0; 22 | end 23 | 24 | always @ (posedge clk, posedge clr) begin 25 | if(clr) 26 | Q <= 0; 27 | else 28 | Q <= Q ^ T; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /FFs/TFF/TFF_SyncClear.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: TFF_SyncClear.v 6 | // Modified: 2020-07-16 7 | // Description: T-Flip Flop 8 | // - Synchronous Clear 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module TFF_SyncClear (output reg Q, input T, input clr, input clk); 19 | 20 | initial begin 21 | Q = 0; 22 | end 23 | 24 | always @ (posedge clk) begin 25 | if(clr) 26 | Q <= 0; 27 | else 28 | Q <= Q ^ T; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Akilesh Kannan 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Multiplexers and De-Multiplexers/deMUX1To2n.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: deMUX1To2n.v 6 | // Modified: 2020-07-16 7 | // Description: A General 1 to 2^n Demultiplexer, 1 bit Data 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module deMUX1To2n #(parameter n = 2, parameter logn = $clog2(n)) (output reg[n-1:0] outDemux, input a, input[logn-1:0] s); 19 | 20 | // initially set all outputs to 0 21 | initial begin 22 | outDemux = 0; 23 | end 24 | 25 | // all outputs have to be 0, except for the selected output required 26 | always @(a, s) begin 27 | // set all to 0, then change the selected output 28 | outDemux = 0; 29 | outDemux[s-:1] = a; 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /Multiplexers and De-Multiplexers/mux2nTo1.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: mux2nTo1.v 6 | // Modified: 2020-07-16 7 | // Description: A general 2^n to 1 MUX, data width = 1bit 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module mux2nTo1 #(parameter n = 2, parameter logn = $clog2(n)) (output reg outMux, input[n-1:0] I, input[logn-1:0] S); 19 | 20 | // output has to be selected input always 21 | always @ (I or S) begin 22 | outMux = I[S-:1]; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /Multipliers/boothMultiplier4Bit.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: boothMultiplier4Bit.v 6 | // Modified: 2020-07-15 7 | // Description: 4 bit Booth Multiplier 8 | // Signed Multiplication 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module boothMultiplier4Bit(output reg[7:0] prod, output reg busy, input[3:0] mc, input[3:0] mp, input clk, input start); 19 | 20 | reg [3:0] A, Q, M; 21 | reg Q_1; 22 | reg [2:0] count; 23 | wire [3:0] sum, difference; 24 | 25 | always @(posedge clk) begin 26 | if (start) begin 27 | A <= 0; 28 | M <= mc; 29 | Q <= mp; 30 | Q_1 <= 1'b0; 31 | count <= 0; 32 | end 33 | else begin 34 | busy <= 1'b1; 35 | case ({Q[0], Q_1}) 36 | 2'b0_1 : {A, Q, Q_1} <= {sum[3], sum, Q}; 37 | 2'b1_0 : {A, Q, Q_1} <= {difference[3], difference, Q}; 38 | default: {A, Q, Q_1} <= {A[3], A, Q}; 39 | endcase 40 | count <= count + 1'b1; 41 | if(count == 4) begin 42 | busy <= 1'b0; 43 | prod <= {A, Q}; 44 | count <= 0; 45 | end 46 | end 47 | end 48 | 49 | assign sum = A + M; 50 | assign difference = A + ~M + 1'b1; 51 | endmodule 52 | -------------------------------------------------------------------------------- /Multipliers/serialParallelMultiplier4Bit.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: serialParallelMultiplier4Bit.v 6 | // Modified: 2020-07-15 7 | // Description: 4-bit Serial-Parallel Multiplier 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module serialParallelMultiplier4Bit(output reg [7:0] out, output finish, input reset, input clk, input [3:0] A, input [3:0] B); 19 | 20 | reg [3:0] State; // state machine 21 | reg [8:0] ACC; // Accumulator 22 | assign finish = (State == 9) ? 1'b1:1'b0; // Finish Flag 23 | 24 | always @(posedge clk, A, B) begin 25 | if(reset) begin 26 | State <= 0; 27 | ACC <= 0; 28 | out <= 0; 29 | end 30 | else if (State == 0) begin 31 | ACC[8:4] <= 5'b0; // begin cycle 32 | ACC[3:0] <= A; // Load A (one of our inputs) 33 | State <= 1; 34 | end 35 | else if (State == 1 || State == 3 || State == 5 || State == 7) begin 36 | // add/shift State 37 | if(ACC[0] == 1'b1) begin // add multiplicand 38 | ACC[8:4] <= {1'b0, ACC[7:4]} + B; 39 | State <= State + 1; 40 | end 41 | else begin 42 | ACC <= {1'b0, ACC[8:1]}; // shift right 43 | State <= State + 2; 44 | end 45 | end 46 | else if(State == 2 || State == 4 || State == 6 || State == 8) begin 47 | // shift State 48 | ACC <= {1'b0, ACC[8:1]}; // shift right 49 | State <= State + 1; 50 | end 51 | else if(State == 9) begin 52 | //State <= 0; 53 | out <= ACC[7:0]; // loading data of accumulator in output 54 | end 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /Multipliers/wallaceTreeMultiplier8Bit.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: wallaceTreeMultiplier8Bit.v 6 | // Modified: 2020-07-15 7 | // Description: 8-bit Wallace Tree Multiplier 8 | // Unsigned multiplication 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module wallaceTreeMultiplier8Bit (output[15:0] result, input[7:0] a, input[7:0] b); 19 | 20 | reg[7:0] wallaceTree[7:0]; 21 | integer i, j; 22 | 23 | always @(a, b) begin 24 | for(i = 0;i < 8;i = i+1) 25 | for(j = 0;j < 8;j = j+1) 26 | wallaceTree[i][j] = a[i] & b[j]; 27 | end 28 | // result[0] 29 | assign result[0] = wallaceTree[0][0]; 30 | 31 | // result[1] 32 | wire result1_c; 33 | HA result1_HA_1(result1_c, result[1], wallaceTree[0][1], wallaceTree[1][0]); 34 | 35 | // result[2] 36 | wire result2_c_temp_1, result2_c, result2_temp_1; 37 | FA result2_FA_1(result2_c_temp_1, result2_temp_1, wallaceTree[0][2], wallaceTree[1][1], result1_c); 38 | HA result2_HA_1(result2_c, result[2], wallaceTree[2][0], result2_temp_1); 39 | 40 | // result[3] 41 | wire result3_c_temp_1, result3_c_temp_2, result3_c, result3_temp_1, result3_temp_2; 42 | FA result3_FA_1(result3_c_temp_1, result3_temp_1, wallaceTree[0][3], wallaceTree[1][2], result2_c); 43 | FA result3_FA_2(result3_c_temp_2, result3_temp_2, wallaceTree[2][1], result3_temp_1, result2_c_temp_1); 44 | HA result3_HA_1(result3_c, result[3], wallaceTree[3][0], result3_temp_2); 45 | 46 | // result[4] 47 | wire result4_c_temp_1, result4_c_temp_2, result4_c_temp_3, result4_c, result4_temp_1, result4_temp_2, result4_temp_3; 48 | FA result4_FA_1(result4_c_temp_1, result4_temp_1, wallaceTree[0][4], wallaceTree[1][3], result3_c); 49 | FA result4_FA_2(result4_c_temp_2, result4_temp_2, wallaceTree[2][2], result4_temp_1, result3_c_temp_1); 50 | FA result4_FA_3(result4_c_temp_3, result4_temp_3, wallaceTree[3][1], result4_temp_2, result3_c_temp_2); 51 | HA result4_HA_1(result4_c, result[4], wallaceTree[4][0], result4_temp_3); 52 | 53 | // result[5] 54 | wire result5_c_temp_1, result5_c_temp_2, result5_c_temp_3, result5_c_temp_4, result5_c, result5_temp_1, result5_temp_2, result5_temp_3, result5_temp_4; 55 | FA result5_FA_1(result5_c_temp_1, result5_temp_1, wallaceTree[0][5], wallaceTree[1][4], result4_c); 56 | FA result5_FA_2(result5_c_temp_2, result5_temp_2, wallaceTree[2][3], result5_temp_1, result4_c_temp_1); 57 | FA result5_FA_3(result5_c_temp_3, result5_temp_3, wallaceTree[3][2], result5_temp_2, result4_c_temp_2); 58 | FA result5_FA_4(result5_c_temp_4, result5_temp_4, wallaceTree[4][1], result5_temp_3, result4_c_temp_3); 59 | HA result5_HA_1(result5_c, result[5], wallaceTree[5][0], result5_temp_4); 60 | 61 | // result[6] 62 | wire result6_c_temp_1, result6_c_temp_2, result6_c_temp_3, result6_c_temp_4, result6_c_temp_5, result6_c, result6_temp_1, result6_temp_2, result6_temp_3, result6_temp_4, result6_temp_5; 63 | FA result6_FA_1(result6_c_temp_1, result6_temp_1, wallaceTree[0][6], wallaceTree[1][5], result5_c); 64 | FA result6_FA_2(result6_c_temp_2, result6_temp_2, wallaceTree[2][4], result6_temp_1, result5_c_temp_1); 65 | FA result6_FA_3(result6_c_temp_3, result6_temp_3, wallaceTree[3][3], result6_temp_2, result5_c_temp_2); 66 | FA result6_FA_4(result6_c_temp_4, result6_temp_4, wallaceTree[4][2], result6_temp_3, result5_c_temp_3); 67 | FA result6_FA_5(result6_c_temp_5, result6_temp_5, wallaceTree[5][1], result6_temp_4, result5_c_temp_4); 68 | HA result6_HA_1(result6_c, result[6], wallaceTree[6][0], result6_temp_5); 69 | 70 | // result[7] 71 | wire result7_c_temp_1, result7_c_temp_2, result7_c_temp_3, result7_c_temp_4, result7_c_temp_5, result7_c_temp_6, result7_c, result7_temp_1, result7_temp_2, result7_temp_3, result7_temp_4, result7_temp_5, result7_temp_6; 72 | FA result7_FA_1(result7_c_temp_1, result7_temp_1, wallaceTree[0][7], wallaceTree[1][6], result6_c); 73 | FA result7_FA_2(result7_c_temp_2, result7_temp_2, wallaceTree[2][5], result7_temp_1, result6_c_temp_1); 74 | FA result7_FA_3(result7_c_temp_3, result7_temp_3, wallaceTree[3][4], result7_temp_2, result6_c_temp_2); 75 | FA result7_FA_4(result7_c_temp_4, result7_temp_4, wallaceTree[4][3], result7_temp_3, result6_c_temp_3); 76 | FA result7_FA_5(result7_c_temp_5, result7_temp_5, wallaceTree[5][2], result7_temp_4, result6_c_temp_4); 77 | FA result7_FA_6(result7_c_temp_6, result7_temp_6, wallaceTree[6][1], result7_temp_5, result6_c_temp_5); 78 | HA result7_HA_1(result7_c, result[7], wallaceTree[7][0], result7_temp_6); 79 | 80 | // result[8] 81 | wire result8_c_temp_1, result8_c_temp_2, result8_c_temp_3, result8_c_temp_4, result8_c_temp_5, result8_c_temp_6, result8_c, result8_temp_1, result8_temp_2, result8_temp_3, result8_temp_4, result8_temp_5, result8_temp_6; 82 | FA result8_FA_1(result8_c_temp_1, result8_temp_1, wallaceTree[1][7], wallaceTree[2][6], result7_c); 83 | FA result8_FA_2(result8_c_temp_2, result8_temp_2, wallaceTree[3][5], result8_temp_1, result7_c_temp_1); 84 | FA result8_FA_3(result8_c_temp_3, result8_temp_3, wallaceTree[4][4], result8_temp_2, result7_c_temp_2); 85 | FA result8_FA_4(result8_c_temp_4, result8_temp_4, wallaceTree[5][3], result8_temp_3, result7_c_temp_3); 86 | FA result8_FA_5(result8_c_temp_5, result8_temp_5, wallaceTree[6][2], result8_temp_4, result7_c_temp_4); 87 | FA result8_FA_6(result8_c_temp_6, result8_temp_6, wallaceTree[7][1], result8_temp_5, result7_c_temp_5); 88 | HA result8_HA_1(result8_c, result[8], result8_temp_6, result7_c_temp_6); 89 | 90 | // result[9] 91 | wire result9_c_temp_1, result9_c_temp_2, result9_c_temp_3, result9_c_temp_4, result9_c, result9_temp_1, result9_temp_2, result9_temp_3, result9_temp_4; 92 | FA result9_FA_1(result9_c_temp_1, result9_temp_1, wallaceTree[2][7], wallaceTree[3][6], result8_c); 93 | FA result9_FA_2(result9_c_temp_2, result9_temp_2, wallaceTree[4][5], result9_temp_1, result8_c_temp_1); 94 | FA result9_FA_3(result9_c_temp_3, result9_temp_3, wallaceTree[5][4], result9_temp_2, result8_c_temp_2); 95 | FA result9_FA_4(result9_c_temp_4, result9_temp_4, wallaceTree[6][3], result9_temp_3, result8_c_temp_3); 96 | FA result9_FA_5(result9_c_temp_5, result9_temp_5, wallaceTree[7][2], result9_temp_4, result8_c_temp_4); 97 | FA result9_FA_6(result9_c, result[9], result9_temp_5, result8_c_temp_5, result8_c_temp_6); 98 | 99 | // result[10] 100 | wire result10_c_temp_1, result10_c_temp_2, result10_c_temp_3, result10_c, result10_temp_1, result10_temp_2, result10_temp_3; 101 | FA result10_FA_1(result10_c_temp_1, result10_temp_1, wallaceTree[3][7], wallaceTree[4][6], result9_c); 102 | FA result10_FA_2(result10_c_temp_2, result10_temp_2, wallaceTree[5][5], result10_temp_1, result9_c_temp_1); 103 | FA result10_FA_3(result10_c_temp_3, result10_temp_3, wallaceTree[6][4], result10_temp_2, result9_c_temp_2); 104 | FA result10_FA_4(result10_c_temp_4, result10_temp_4, wallaceTree[7][3], result10_temp_3, result9_c_temp_3); 105 | FA result10_FA_5(result10_c, result[10], result10_temp_4, result9_c_temp_4, result9_c_temp_5); 106 | 107 | // result[11] 108 | wire result11_c_temp_1, result11_c_temp_2, result11_c, result11_temp_1, result11_temp_2; 109 | FA result11_FA_1(result11_c_temp_1, result11_temp_1, wallaceTree[4][7], wallaceTree[5][6], result10_c); 110 | FA result11_FA_2(result11_c_temp_2, result11_temp_2, wallaceTree[6][5], result11_temp_1, result10_c_temp_1); 111 | FA result11_FA_3(result11_c_temp_3, result11_temp_3, wallaceTree[7][4], result11_temp_2, result10_c_temp_2); 112 | FA result11_FA_4(result11_c, result[11], result11_temp_3, result10_c_temp_3, result10_c_temp_4); 113 | 114 | // result[12] 115 | wire result12_c_temp_1, result12_c, result12_temp_1; 116 | FA result12_FA_1(result12_c_temp_1, result12_temp_1, wallaceTree[5][7], wallaceTree[6][6], result11_c); 117 | FA result12_FA_2(result12_c_temp_2, result12_temp_2, wallaceTree[7][5], result12_temp_1, result11_c_temp_1); 118 | FA result12_FA_3(result12_c, result[12], result12_temp_2, result11_c_temp_2, result11_c_temp_3); 119 | 120 | // result[13] 121 | wire result13_c; 122 | FA result13_FA_1(result13_c_temp_1, result13_temp_1, wallaceTree[6][7], wallaceTree[7][6], result12_c); 123 | FA result13_FA_2(result13_c, result[13], result13_temp_1, result12_c_temp_2, result12_c_temp_1); 124 | 125 | // result[14] 126 | FA result14_FA_1(result14_c, result[14], wallaceTree[7][7], result13_c, result13_c_temp_1); 127 | 128 | // result[15] 129 | assign result[15] = result14_c; 130 | endmodule 131 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Getting Started with Verilog 2 | 3 | This repository contains some verilog modules which are the elementary and fundamental building blocks of a digital circuit. It is best suited for those who are just getting started with Verilog. 4 | 5 | **Table of Contents** 6 | - [Modules](#modules) 7 | - [Flip Flops](#flip-flops) 8 | - [Adder Circuits](#adder-circuits) 9 | - [Counters](#counters) 10 | - [Multiplexers and De-Multiplexers](#multiplexers-and-de-multiplexers) 11 | - [Multipliers](#multipliers) 12 | - [Miscellaneous](#miscellaneous) 13 | - [Usage and Installation](#usage-and-installation) 14 | - [Contributing](#contributing) 15 | - [License](#license) 16 | 17 | ## Modules 18 | ### Flip Flops 19 | - #### [D Flip-Flop](/FFs/DFF/) 20 | * [without *Clear/Reset*](/FFs/DFF/DFF.v) 21 | * [with __*Synchronous*__ *Clear/Reset*](/FFs/DFF/DFF_SyncClear.v) 22 | * [with __*Asynchronous*__ *Clear/Reset*](/FFs/DFF/DFF_AsyncClear.v) 23 | 24 | - #### [T Flip-Flop](/FFs/TFF.v) 25 | * [without *Clear/Reset*](/FFs/TFF/TFF.v) 26 | * [with __*Synchronous*__ *Clear/Reset*](/FFs/TFF/TFF_SyncClear.v) 27 | * [with __*Asynchronous*__ *Clear/Reset*](/FFs/TFF/TFF_AsyncClear.v) 28 | - #### [JK Flip-Flop](/FFs/JKFF/) 29 | * [without *Clear/Reset*](/FFs/JKFF/JKFF.v) 30 | * [with __*Synchronous*__ *Clear/Reset*](/FFs/JKFF/JKFF_SyncClear.v) 31 | * [with __*Asynchronous*__ *Clear/Reset*](/FFs/JKFF/JKFF_AsyncClear.v) 32 | 33 | 34 | ### Adder Circuits 35 | * [1 Bit Half Adder](/Adders/HA.v) 36 | * [1 Bit Full Adder](/Adders/FA.v) 37 | * [N Bit Carry Look Ahead Adder](/Adders/nBitCarryLookAheadAdder.v) 38 | * [N Bit Ripple Carry Adder](/Adders/nBitRippleCarryAdder.v) 39 | 40 | ### Counters 41 | * [N Bit Counter (generic)](/Counters/nBitCounter.v) 42 | * [N Bit Johnson Counter](/Counters/nBitJohnsonCounter.v) 43 | 44 | ### Multiplexers and De-Multiplexers 45 | * [2n to 1 Multiplexer](/Multiplexers%20and%20De-Multiplexers/mux2nTo1.v) 46 | * [1 to 2n De-Multiplexer](/Multiplexers%20and%20De-Multiplexers/deMUX1To2n.v) 47 | 48 | ### Multipliers 49 | * [(8 Bit) Wallace Tree Multiplier](/Multipliers/wallaceTreeMultiplier8Bit.v) 50 | * [(4 Bit) Serial Parallel Multiplier](/Multipliers/serialParallelMultiplier4Bit.v) 51 | * [(4 Bit) Booth Multiplier](/Multipliers/boothMultiplier4Bit.v) 52 | 53 | 54 | ### Miscellaneous 55 | * [Clock (customisable tick rate)](/clock.v) 56 | * [Clock Divider (customisable factor)](/clkDivider.v) 57 | * [D Latch](/dLatch.v) 58 | * [Memory](/memory.v) 59 | * [32 Bit LFSR - Pseudo Random Number Generator](/lfsr.v) 60 | * [Switch Debouncer](/switchDebouncer.v) 61 | * [Pattern Detector](/patternDetector.v) 62 | * [Two's Complementer](/twoComplementer.v) 63 | * [N Bit Shift Register (universal shift register)](/nBitShiftRegister.v) 64 | * [Typical Example of circuit with datapath and control unit](/designExampleDDMano.v) 65 | * [N-Bit Barrel Shifter](/barrelShifterNBit.v) 66 | * [FIFO](/fifo.v) 67 | 68 | ## Usage and Installation 69 | 1. Clone this repository to local machine - `git clone https://github.com/aklsh/getting-started-with-verilog.git`. 70 | 2. cd into the repository - `cd getting-started-with-verilog/` 71 | 3. Edit the testbench in the file `testbench.v` by instantiating the module you want to check, and providing the stimulus in the initial block. 72 | 4. Run with `make`. 73 | 74 | ## Contributing 75 | Feel free to submit pull requests with more such modules. Do take a look at the [format of an accepted file](/CONTRIBUTING.md) before contributing. 76 | 77 | ## License 78 | [MIT © Akilesh Kannan](/LICENSE) 79 | -------------------------------------------------------------------------------- /barrelShifterNBit.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: barrelShifterNBit.v 6 | // Modified: 2020-07-15 7 | // Description: N-Bit Barrel Shifter module 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module barrelShifterNBit #(parameter n = 4) (output reg[n-1:0] out, input[n-1:0] in, input[$clog2(n):0] shift); 19 | 20 | integer i; 21 | always @ (in, shift) begin 22 | for(i = 0; i < n; i = i+1) begin 23 | if(i + shift < n) 24 | out[i+shift] = in[i]; 25 | else 26 | out[i+shift-n] = in[i]; 27 | end 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /clkDivider.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: clkDivider.v 6 | // Modified: 2020-07-15 7 | // Description: Customisable clock divider 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module clkDivider #(parameter integer factor = 100) (output clkOut, input clkIn); 19 | 20 | reg[31:0] counter; 21 | 22 | // initially set counter to 0 23 | initial begin 24 | counter = 32'd0; 25 | end 26 | 27 | // count the number of clock cycles of input clock 28 | always @ (posedge clkIn) begin 29 | counter <= counter + 1; 30 | // if number of clock cycles is equal to the factor, set counter to 0. 31 | if(counter == factor) 32 | counter <= 0; 33 | end 34 | 35 | // assign value to output clock, by checking with value of counter 36 | assign clkOut = (counter < factor/2) ? 1'b0 : 1'b1; 37 | endmodule 38 | -------------------------------------------------------------------------------- /clock.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: clock.v 6 | // Modified: 2020-07-15 7 | // Description: General Clock Module 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module clock #(parameter tickRate = 1) (output reg clk); 19 | 20 | initial begin 21 | clk = 1'b0; 22 | forever #tickRate clk = ~clk; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /dLatch.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: dLatch.v 6 | // Modified: 2020-07-15 7 | // Description: D-Latch (Level-Triggered Memory element) 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module dLatch(output reg Q, input D, input enable); 19 | 20 | // Level Trigger 21 | always @(enable, D) begin 22 | // if latch is enabled, then set o/p 23 | if(enable) 24 | Q <= D; 25 | else 26 | Q <= 1'bz; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /designExampleDDMano.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: designExampleDDMano.v 6 | // Modified: 2020-07-15 7 | // Description: Implementation of system used to illustrate the use of ASMD charts and RTL 8 | // representation, in the book "Digital Design, With An Introduction to Verilog HDL" 9 | // by M. Morris Mano and Michael D. Ciletti 10 | // (Fig. 8.12) 11 | // 12 | // License: MIT 13 | // 14 | ///////////////////////////////////////////////////////////////////////////////////////////////////////// 15 | 16 | `default_nettype None 17 | 18 | `timescale 1ns/1ps 19 | 20 | module designExampleDDMano(A, E, F, clk, rstAL, start); 21 | 22 | output[3:0] A; 23 | output E, F; 24 | input clk, rstAL, start; 25 | 26 | // instantiating control unit and datapath unit 27 | designExampleDTP datapathUnit(A, E, F, clrE, clrAF, setE, setF, incrA, clk); 28 | designExampleCTRL controlUnit(clrE, setE, setF, clrAF, incrA, A[3], A[2], start, rstAL, clk); 29 | endmodule 30 | 31 | module designExampleCTRL(clrE, setE, setF, clrAF, incrA, A3, A2, start, rstAL, clk); 32 | 33 | output reg clrE, setE, setF, clrAF, incrA; 34 | input A3, A2, start, rstAL, clk; 35 | reg[1:0] currState, nextState; 36 | parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b11; 37 | 38 | always @(posedge clk, negedge rstAL) 39 | if(rstAL == 0) currState <= S0; 40 | else currState <= nextState; 41 | 42 | always @ (start, A2, A3, currState) begin 43 | nextState = S0; 44 | case(currState) 45 | S0: 46 | if(start) nextState = S1; 47 | else nextState = S0; 48 | S1: 49 | if(A2 & A3) nextState = S2; 50 | else nextState = S1; 51 | S2: 52 | nextState = S0; 53 | default: 54 | nextState = S0; 55 | endcase 56 | end 57 | 58 | always @ (currState, A2, start) begin 59 | setE = 0; setF = 0; clrE = 0; clrAF = 0; incrA = 0; 60 | case(currState) 61 | S0: 62 | if(start) clrAF = 1; 63 | S1: 64 | begin incrA = 1; if(A2) setE = 1; else setE = 0; end 65 | S2: 66 | setF = 1; 67 | endcase 68 | end 69 | endmodule 70 | 71 | module designExampleDTP(A, E, F, clrE, clrAF, setE, setF, incrA, clk); 72 | 73 | output reg[3:0] A; 74 | output reg E, F; 75 | input clrE, clrAF, setE, setF, incrA, clk; 76 | 77 | always @ (posedge clk) begin 78 | if(setE) E <= 1; 79 | if(setF) F <= 1; 80 | if(clrE) E <= 0; 81 | if(clrAF) begin A <= 0; F <= 0; end 82 | if(incrA) A <= A+1; 83 | end 84 | endmodule 85 | -------------------------------------------------------------------------------- /fifo.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: fifo.v 6 | // Modified: 2020-07-15 7 | // Description: First In First Out (FIFO) Buffer 8 | // - Synchronous Operation 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module fifo #(parameter DATA_WIDTH = 1, // width of each stored element 19 | ADDRESS_WIDTH = 13 // address width of the buffer 20 | ) 21 | (output reg [DATA_WIDTH-1:0] dataOut, // output data 22 | output full, // signal for indicating FIFO is full 23 | output empty, // signal for indicating FIFO is empty 24 | output [ADDRESS_WIDTH:0] filled, // number of memory locations filled 25 | input read, // read signal 26 | input write, // write signal 27 | input [DATA_WIDTH-1:0] dataIn, // data to write 28 | input reset, // reset signal (Active-High) 29 | input enable, // enable signal 30 | input clk // clock pulse 31 | ); 32 | 33 | 34 | /* 35 | First In First Out Buffer 36 | 37 | 38 | +------------------------......-------------+ 39 | | | | | | | |...... | | | | 40 | +------------------------......-------------+ 41 | ↑ ↑ 42 | read write 43 | 44 | 45 | - Read output data in read pointer location 46 | - Write input data to write pointer location 47 | - Both pointers set to 0 initially 48 | - If empty, do not read 49 | - If full, do not write 50 | - Reset to erase memory 51 | 52 | */ 53 | 54 | reg [DATA_WIDTH-1:0] memory [0:FIFO_SIZE-1]; // main memory 55 | wire writeEnable, readEnable; // actual read/write signals, incorporating empty and full exceptions 56 | reg [ADDRESS_WIDTH:0] readPointer, writePointer; // read and write pointers 57 | 58 | assign writeEnable = write & !full; 59 | assign readEnable = read & !empty; 60 | 61 | always @(posedge clk) begin 62 | if (reset) begin 63 | writePointer <= 0; 64 | readPointer <= 0; 65 | end 66 | else begin 67 | if (enable) begin 68 | if (readEnable) begin 69 | dataOut <= memory[readPointer]; 70 | readPointer <= readPointer+1; 71 | end 72 | if (writeEnable) begin 73 | memory[writePointer] <= dataIn; 74 | writePointer <= writePointer+1; 75 | end 76 | end 77 | else begin 78 | writePointer <= writePointer; 79 | readPointer <= readPointer; 80 | end 81 | end 82 | end 83 | 84 | // assign outputs 85 | assign filled = writePointer - readPointer; 86 | assign full = (filled == {1'b1, {ADDRESS_WIDTH-1{1'b0}}}); 87 | assign empty = (filled == 0); 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /lfsr.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: lfsr.v 6 | // Modified: 2020-07-15 7 | // Description: Linear Feedback Shift Register (32-bit) 8 | // Used a pseudo-random number generator 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module lfsr #(parameter seed = 32'b1) (output reg[31:0] LFSRregister, input clk); 19 | 20 | // initially register will contain seed value 21 | initial begin 22 | LFSRregister = seed; 23 | end 24 | 25 | // at edge of each clock pulse, shift and XOR required bits 26 | always @(posedge clk) begin 27 | LFSRregister = LFSRregister << 1; 28 | LFSRregister[0] = LFSRregister[31] ^ LFSRregister[29] ^ LFSRregister[25] ^ LFSRregister[24]; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /memory.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: memory.v 6 | // Modified: 2020-07-15 7 | // Description: General Memory module 8 | // Can be used to build RAM, ROM etc. 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module memory #(parameter integer wordSize = 4, parameter integer numWords = 64)(output reg[wordSize-1:0] dataOut, input enable, input[$clog2(numWords)-1:0] address, input[wordSize-1:0] dataIn, input readWrite); 19 | 20 | reg[wordSize-1:0] mem[numWords-1:0]; 21 | 22 | // Whenever there is a change in either enable or readWrite, execute the always block 23 | always @(enable, readWrite) begin 24 | if(enable) begin 25 | /* 26 | readWrite = 1 ==> read; 27 | readWrite = 0 ==> write; 28 | */ 29 | if(readWrite) 30 | dataOut = mem[address]; 31 | else 32 | mem[address] = dataIn; 33 | end 34 | 35 | // if not enabled, register is not connected 36 | else 37 | dataOut = 64'bz; 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /nBitShiftRegister.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: nBitShiftRegister.v 6 | // Modified: 2020-07-15 7 | // Description: General Shift Register 8 | // Configurable for Left-/Right- shift 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module nBitShiftRegister #(parameter integer n = 4) (output reg[n-1:0] Q, input[n-1:0] D, input dSerial, input clk, input shiftL, input shiftR, input load, input clr); 19 | 20 | always @(posedge clk, negedge clr) begin 21 | if(clr == 1'b0) 22 | Q <= 0; 23 | else begin 24 | if(shiftL) begin 25 | Q <= Q << 1; 26 | Q[0] <= dSerial; 27 | end 28 | if(shiftR) begin 29 | Q <= Q >> 1; 30 | Q[n-1] <= dSerial; 31 | end 32 | if(load) 33 | Q <= D; 34 | end 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /patternDetector.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: patternDetector.v 6 | // Modified: 2020-07-15 7 | // Description: General Pattern detector module 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module patternDetector #(parameter pattern = 3'b111, parameter patternSize = $bits(pattern)) (output reg Y, input A, input clk); 19 | 20 | reg[patternSize-1:0] inputStream; 21 | 22 | always @(posedge clk, A) begin 23 | inputStream = {inputStream[patternSize-2:0], A}; 24 | end 25 | always @(posedge clk) begin 26 | Y = (inputStream === pattern) ? 1'b1:1'b0; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /switchDebouncer.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: switchDebouncer.v 6 | // Modified: 2020-07-15 7 | // Description: Switch Debouncing Circuit 8 | // 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module switchDebouncer #(parameter integer N = 16) (output reg switchOut, input switchIn, input clk); 19 | 20 | wire rst, add; 21 | reg dFF1, dFF2; 22 | reg[N-1:0] timeReg, nextReg; 23 | 24 | assign rst = dFF1 ^ dFF2; 25 | assign add = ~timeReg[N-1]; 26 | always @(rst, add, timeReg) begin 27 | case({rst, add}) 28 | 2'b00: nextReg <= timeReg; 29 | 2'b01: nextReg <= timeReg + 1; 30 | default: nextReg <= {N{1'b0}}; 31 | endcase 32 | end 33 | always @(posedge clk) begin 34 | dFF1 <= switchIn; 35 | dFF2 <= dFF1; 36 | timeReg <= nextReg; 37 | end 38 | always @(posedge clk) begin 39 | if(timeReg[N-1] == 1'b1) 40 | switchOut <= dFF2; 41 | else 42 | switchOut <= switchOut; 43 | end 44 | endmodule 45 | -------------------------------------------------------------------------------- /testbench.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: testbench.v 6 | // Modified: 2020-07-15 7 | // Description: Testbench Blueprint 8 | // - Instantiate the modules to test 9 | // - Provide Stimulus 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module testbench; 19 | 20 | // parameters (if used) 21 | localparam tickRate = 10; //half time-period of clock (in ns) 22 | 23 | // all necessary variables 24 | wire clk; 25 | 26 | // generating file to see signals 27 | initial begin 28 | $dumpfile("test.vcd"); 29 | $dumpvars(0, testbench); 30 | end 31 | 32 | // clock-pulse 33 | clock #(.tickRate(tickRate)) clockModule(clk); 34 | 35 | // instantiating module and other parallel statements 36 | //module name #() uut(); 37 | 38 | // stimuli 39 | initial begin 40 | #100 $finish; 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /twoComplementer.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2020 Akilesh Kannan 4 | // 5 | // File: twoComplementer.v 6 | // Modified: 2020-07-15 7 | // Description: Two's complementer module 8 | // Find additive inverse 9 | // 10 | // License: MIT 11 | // 12 | //////////////////////////////////////////////////////////////////////// 13 | 14 | `default_nettype None 15 | 16 | `timescale 1ns/1ps 17 | 18 | module twoComplementer #(parameter N = 4) (output wire[N-1:0] twoComp, input[N-1:0] in); 19 | wire[N:0] total; 20 | 21 | assign total = ~in+1; 22 | assign twoComp = total[N-1:0]; 23 | endmodule 24 | --------------------------------------------------------------------------------