├── .gitignore ├── LICENSE ├── README.md ├── advanced ├── ddrsound │ ├── DDRSound.qpf │ ├── DDRSound.qsf │ ├── DDRSound.srf │ ├── DDRSound.sv │ ├── README.md │ ├── base_pack.vhd │ ├── ddram.sv │ ├── dpram.vhd │ ├── files.qip │ ├── ovo.vhd │ ├── soc.v │ ├── stp1.stp │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── ltc2308.sv │ │ ├── mcp23009.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ ├── pll_hdmi_0002.v │ │ │ └── pll_hdmi_0002_q13.qip │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ └── video_mixer.sv │ ├── video.v │ └── wave_sound.sv ├── fbexample │ ├── .gitignore │ ├── FBExample.qpf │ ├── FBExample.qsf │ ├── FBExample.sdc │ ├── FBExample.srf │ ├── FBExample.sv │ ├── Readme.md │ ├── clean.bat │ ├── files.qip │ ├── releases │ │ ├── FB.mra │ │ └── wallpaper1.zip │ ├── rtl │ │ ├── pll.qip │ │ ├── pll.v │ │ └── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ ├── scripts │ │ ├── convertimage.py │ │ └── wallpaper1.jpg │ └── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── math.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ ├── pll_audio_0002.qip │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_freak.sv │ │ └── video_mixer.sv ├── sound │ ├── Sound.qpf │ ├── Sound.qsf │ ├── Sound.srf │ ├── Sound.sv │ ├── base_pack.vhd │ ├── dk_wave.v │ ├── dpram.vhd │ ├── files.qip │ ├── ovo.vhd │ ├── readme.md │ ├── romextract │ │ ├── convert_sound.sh │ │ └── dumppf.c │ ├── soc.v │ ├── sound_rom.v │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── ltc2308.sv │ │ ├── mcp23009.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ ├── pll_hdmi_0002.v │ │ │ └── pll_hdmi_0002_q13.qip │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ └── video_mixer.sv │ └── video.v ├── synth │ ├── LICENSE │ ├── README.md │ ├── Synth.qpf │ ├── Synth.qsf │ ├── Synth.srf │ ├── Synth.sv │ ├── base_pack.vhd │ ├── createromsynth.py │ ├── data │ │ └── exp_lookup_table.rom │ ├── ddram.sv │ ├── dpram.vhd │ ├── files.qip │ ├── hdl │ │ ├── amplitude_modulator.vh │ │ ├── clock_divider.vh │ │ ├── eight_bit_exponential_decay_lookup.vh │ │ ├── envelope_generator.vh │ │ ├── filter_ewma.vh │ │ ├── filter_svf.vh │ │ ├── filter_svf_pipelined.vh │ │ ├── flanger.vh │ │ ├── multi_channel_mixer.vh │ │ ├── pdm_dac.vh │ │ ├── tiny-synth-all.vh │ │ ├── tone_generator.vh │ │ ├── tone_generator_noise.vh │ │ ├── tone_generator_pulse.vh │ │ ├── tone_generator_saw.vh │ │ ├── tone_generator_triangle.vh │ │ ├── two_into_one_mixer.vh │ │ └── voice.vh │ ├── ovo.vhd │ ├── romsynth.v │ ├── soc.v │ ├── stp1.stp │ ├── syn │ │ ├── double.syn │ │ ├── noise.syn │ │ └── sound.syn │ ├── synth.v │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── ltc2308.sv │ │ ├── mcp23009.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ ├── pll_hdmi_0002.v │ │ │ └── pll_hdmi_0002_q13.qip │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ └── video_mixer.sv │ ├── video.v │ └── wave_sound.sv ├── vexample │ ├── VExample.qpf │ ├── VExample.qsf │ ├── VExample.srf │ ├── VExample.sv │ ├── base_pack.vhd │ ├── dpram.vhd │ ├── files.qip │ ├── ovo.vhd │ ├── romextract │ │ └── 00.wav │ ├── sim │ │ ├── bram.sv │ │ ├── dpram_dc.sv │ │ ├── nspram.sv │ │ └── spram.sv │ ├── soc.v │ ├── stp1.stp │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── ltc2308.sv │ │ ├── mcp23009.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ ├── pll_hdmi_0002.v │ │ │ └── pll_hdmi_0002_q13.qip │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ └── video_mixer.sv │ ├── verilator │ │ ├── Makefile │ │ ├── imgui │ │ │ ├── Makefile │ │ │ ├── imconfig.h │ │ │ ├── imgui.cpp │ │ │ ├── imgui.h │ │ │ ├── imgui_draw.cpp │ │ │ ├── imgui_impl_opengl2.cpp │ │ │ ├── imgui_impl_opengl2.h │ │ │ ├── imgui_impl_sdl.cpp │ │ │ ├── imgui_impl_sdl.h │ │ │ ├── imgui_internal.h │ │ │ ├── imgui_memory_editor.h │ │ │ ├── imgui_widgets.cpp │ │ │ ├── imstb_rectpack.h │ │ │ ├── imstb_textedit.h │ │ │ └── imstb_truetype.h │ │ ├── readme.txt │ │ ├── sim_main.cpp │ │ ├── sound_verilator.v │ │ ├── vga.cpp │ │ └── vga.h │ ├── video.v │ └── wave_sound.v ├── zaxddr │ ├── README.md │ ├── ZaxDDR.qpf │ ├── ZaxDDR.qsf │ ├── ZaxDDR.srf │ ├── ZaxDDR.sv │ ├── base_pack.vhd │ ├── ddram.sv │ ├── files.qip │ ├── ovo.vhd │ ├── soc.v │ ├── stp1.stp │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── ltc2308.sv │ │ ├── mcp23009.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ ├── pll_hdmi_0002.v │ │ │ └── pll_hdmi_0002_q13.qip │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ └── video_mixer.sv │ ├── video.v │ └── wave_sound.sv └── zaxsound │ ├── ZaxSound.qpf │ ├── ZaxSound.qsf │ ├── ZaxSound.srf │ ├── ZaxSound.sv │ ├── base_pack.vhd │ ├── dk_wave.v │ ├── dkongjr_wav_sound.v │ ├── dpram.vhd │ ├── files.qip │ ├── ovo.vhd │ ├── readme.md │ ├── romextract │ ├── convert_sound.sh │ └── dumppf.c │ ├── soc.v │ ├── sound_rom.v │ ├── sys │ ├── alsa.sv │ ├── arcade_video.v │ ├── ascal.vhd │ ├── audio_out.v │ ├── build_id.tcl │ ├── ddr_svc.sv │ ├── gamma_corr.sv │ ├── hdmi_config.sv │ ├── hps_io.v │ ├── hq2x.sv │ ├── i2c.v │ ├── i2s.v │ ├── ltc2308.sv │ ├── mcp23009.sv │ ├── osd.v │ ├── pll.13.qip │ ├── pll.qip │ ├── pll.v │ ├── pll │ │ ├── pll_0002.qip │ │ ├── pll_0002.v │ │ └── pll_0002_q13.qip │ ├── pll_cfg.qip │ ├── pll_cfg.v │ ├── pll_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ ├── pll_hdmi.13.qip │ ├── pll_hdmi.qip │ ├── pll_hdmi.v │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ ├── pll_hdmi_0002.v │ │ └── pll_hdmi_0002_q13.qip │ ├── pll_hdmi_adj.vhd │ ├── pll_q13.qip │ ├── pll_q17.qip │ ├── scandoubler.v │ ├── scanlines.v │ ├── sd_card.v │ ├── sigma_delta_dac.v │ ├── spdif.v │ ├── sys.qip │ ├── sys.tcl │ ├── sys_analog.tcl │ ├── sys_dual_sdram.tcl │ ├── sys_top.sdc │ ├── sys_top.v │ ├── sysmem.sv │ ├── vga_out.sv │ ├── video_cleaner.sv │ └── video_mixer.sv │ ├── video.v │ └── zaxxon_discrete_sound.sv ├── basic ├── README.md ├── cassette_overlay │ ├── Overlay.qpf │ ├── Overlay.qsf │ ├── Overlay.sv │ ├── README.md │ ├── build.sh │ ├── files.qip │ ├── font.pf │ ├── rtl │ │ ├── background.hex │ │ ├── bram.sv │ │ ├── cas_bram.sv │ │ ├── charmap.v │ │ ├── dpram.vhd │ │ ├── font.hex │ │ ├── overlay.notworking │ │ ├── overlay.v │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── rom.hex │ │ ├── soc.v │ │ └── vga.v │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.sv │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── math.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ │ ├── pll_audio_0002.qip │ │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── shadowmask.sv │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_freak.sv │ │ ├── video_freezer.sv │ │ └── video_mixer.sv │ └── verilator │ │ ├── Makefile │ │ ├── background.hex │ │ ├── font.hex │ │ ├── imgui.ini │ │ ├── misterbackground.hex │ │ ├── overlay_tb.v │ │ ├── rom.hex │ │ ├── sim.sln │ │ ├── sim.vcxproj │ │ ├── sim.vcxproj.filters │ │ ├── sim.vcxproj.user │ │ ├── sim │ │ ├── imgui │ │ │ ├── Makefile │ │ │ ├── imconfig.h │ │ │ ├── imgui.cpp │ │ │ ├── imgui.h │ │ │ ├── imgui_demo.cpp │ │ │ ├── imgui_draw.cpp │ │ │ ├── imgui_impl_dx11.cpp │ │ │ ├── imgui_impl_dx11.h │ │ │ ├── imgui_impl_opengl2.cpp │ │ │ ├── imgui_impl_opengl2.h │ │ │ ├── imgui_impl_sdl.cpp │ │ │ ├── imgui_impl_sdl.h │ │ │ ├── imgui_impl_win32.cpp │ │ │ ├── imgui_impl_win32.h │ │ │ ├── imgui_internal.h │ │ │ ├── imgui_memory_editor.h │ │ │ ├── imgui_tables.cpp │ │ │ ├── imgui_widgets.cpp │ │ │ ├── imstb_rectpack.h │ │ │ ├── imstb_textedit.h │ │ │ └── imstb_truetype.h │ │ ├── sim_bus.cpp │ │ ├── sim_bus.h │ │ ├── sim_clock.cpp │ │ ├── sim_clock.h │ │ ├── sim_console.cpp │ │ ├── sim_console.h │ │ ├── sim_input.cpp │ │ ├── sim_input.h │ │ ├── sim_video.cpp │ │ ├── sim_video.h │ │ └── vinc │ │ │ ├── gtkwave │ │ │ ├── fastlz.c │ │ │ ├── fastlz.h │ │ │ ├── fst_config.h │ │ │ ├── fstapi.c │ │ │ ├── fstapi.h │ │ │ ├── lz4.c │ │ │ ├── lz4.h │ │ │ └── wavealloca.h │ │ │ ├── verilated.cpp │ │ │ ├── verilated.h │ │ │ ├── verilated.mk │ │ │ ├── verilated.v │ │ │ ├── verilated_config.h │ │ │ ├── verilated_config.h.in │ │ │ ├── verilated_cov.cpp │ │ │ ├── verilated_cov.h │ │ │ ├── verilated_cov_key.h │ │ │ ├── verilated_dpi.cpp │ │ │ ├── verilated_dpi.h │ │ │ ├── verilated_fst_c.cpp │ │ │ ├── verilated_fst_c.h │ │ │ ├── verilated_heavy.h │ │ │ ├── verilated_imp.h │ │ │ ├── verilated_save.cpp │ │ │ ├── verilated_save.h │ │ │ ├── verilated_sc.h │ │ │ ├── verilated_sym_props.h │ │ │ ├── verilated_syms.h │ │ │ ├── verilated_threads.cpp │ │ │ ├── verilated_threads.h │ │ │ ├── verilated_unordered_set_map.h │ │ │ ├── verilated_vcd_c.cpp │ │ │ ├── verilated_vcd_c.h │ │ │ ├── verilated_vcd_sc.cpp │ │ │ ├── verilated_vcd_sc.h │ │ │ ├── verilated_vpi.cpp │ │ │ ├── verilated_vpi.h │ │ │ ├── verilatedos.h │ │ │ └── vltstd │ │ │ ├── svdpi.h │ │ │ └── vpi_user.h │ │ ├── sim_main.cpp │ │ └── verilate.sh ├── lesson0 │ └── README.md ├── lesson1 │ ├── Lesson1.qpf │ ├── Lesson1.qsf │ ├── Lesson1.sdc │ ├── Lesson1.sv │ ├── README.md │ ├── files.qip │ ├── lesson1.png │ ├── lesson1_grey.png │ ├── lesson1_red.png │ ├── lesson1_white.png │ ├── rtl │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ └── vga.v │ ├── solution │ │ ├── Lesson1.sv │ │ └── rtl │ │ │ └── vga.v │ └── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── math.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ ├── pll_audio_0002.qip │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_freak.sv │ │ └── video_mixer.sv ├── lesson2 │ ├── Image Examples │ │ ├── MiSTer160.jpg │ │ ├── MiSTer640.jpg │ │ ├── bird.bin │ │ ├── image.png │ │ ├── image640.hex │ │ └── image_Bird.hex │ ├── Lesson2.qpf │ ├── Lesson2.qsf │ ├── Lesson2.sv │ ├── README.md │ ├── files.qip │ ├── img2hex.sh │ ├── lesson2.png │ ├── rtl │ │ ├── dpram.vhd │ │ ├── image.bin │ │ ├── image.hex │ │ ├── image.qip │ │ ├── image.v │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── soc.v │ │ └── vga.v │ ├── solution │ │ ├── Lesson2.sv │ │ ├── files.qip │ │ └── rtl │ │ │ ├── dpram.vhd │ │ │ ├── soc.v │ │ │ └── vga.v │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── math.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ │ ├── pll_audio_0002.qip │ │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_freak.sv │ │ └── video_mixer.sv │ └── verilator │ │ ├── Makefile │ │ ├── imgui │ │ ├── Makefile │ │ ├── imconfig.h │ │ ├── imgui.cpp │ │ ├── imgui.h │ │ ├── imgui_demo.cpp │ │ ├── imgui_draw.cpp │ │ ├── imgui_impl_dx11.cpp │ │ ├── imgui_impl_dx11.h │ │ ├── imgui_impl_opengl2.cpp │ │ ├── imgui_impl_opengl2.h │ │ ├── imgui_impl_sdl.cpp │ │ ├── imgui_impl_sdl.h │ │ ├── imgui_impl_win32.cpp │ │ ├── imgui_impl_win32.h │ │ ├── imgui_internal.h │ │ ├── imgui_memory_editor.h │ │ ├── imgui_tables.cpp │ │ ├── imgui_widgets.cpp │ │ ├── imstb_rectpack.h │ │ ├── imstb_textedit.h │ │ └── imstb_truetype.h │ │ ├── imgui_win │ │ └── imgui_memory_editor.h │ │ ├── lesson2_tb.v │ │ ├── obj_dir │ │ └── Vtop_classes.mk │ │ ├── ram │ │ └── bram.sv │ │ ├── sim.sln │ │ ├── sim.vcxproj │ │ ├── sim.vcxproj.filters │ │ ├── sim.vcxproj.user │ │ ├── sim_main.cpp │ │ ├── verilate.sh │ │ └── vinc │ │ ├── gtkwave │ │ ├── fastlz.c │ │ ├── fastlz.h │ │ ├── fst_config.h │ │ ├── fstapi.c │ │ ├── fstapi.h │ │ ├── lz4.c │ │ ├── lz4.h │ │ └── wavealloca.h │ │ ├── verilated.cpp │ │ ├── verilated.h │ │ ├── verilated.mk │ │ ├── verilated.v │ │ ├── verilated_config.h │ │ ├── verilated_config.h.in │ │ ├── verilated_cov.cpp │ │ ├── verilated_cov.h │ │ ├── verilated_cov_key.h │ │ ├── verilated_dpi.cpp │ │ ├── verilated_dpi.h │ │ ├── verilated_fst_c.cpp │ │ ├── verilated_fst_c.h │ │ ├── verilated_heavy.h │ │ ├── verilated_imp.h │ │ ├── verilated_save.cpp │ │ ├── verilated_save.h │ │ ├── verilated_sc.h │ │ ├── verilated_sym_props.h │ │ ├── verilated_syms.h │ │ ├── verilated_threads.cpp │ │ ├── verilated_threads.h │ │ ├── verilated_unordered_set_map.h │ │ ├── verilated_vcd_c.cpp │ │ ├── verilated_vcd_c.h │ │ ├── verilated_vcd_sc.cpp │ │ ├── verilated_vcd_sc.h │ │ ├── verilated_vpi.cpp │ │ ├── verilated_vpi.h │ │ ├── verilatedos.h │ │ └── vltstd │ │ ├── svdpi.h │ │ └── vpi_user.h ├── lesson3 │ ├── Lesson3.qpf │ ├── Lesson3.qsf │ ├── Lesson3.sv │ ├── Makefile │ ├── README.md │ ├── boot_rom.c │ ├── boot_rom.hex │ ├── boot_rom.qip │ ├── boot_rom.v │ ├── files.qip │ ├── lesson3.png │ ├── ram4k.qip │ ├── ram4k.v │ ├── rtl │ │ ├── T80 │ │ │ ├── T80.vhd │ │ │ ├── T80_ALU.vhd │ │ │ ├── T80_MCode.vhd │ │ │ ├── T80_Reg.vhd │ │ │ ├── T80pa.vhd │ │ │ ├── T80s.vhd │ │ │ └── t80.qip │ │ ├── bram.sv │ │ ├── dpram.vhd │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── rom.hex │ │ ├── soc.v │ │ ├── tv80 │ │ │ ├── TV80.qip │ │ │ ├── tv80_alu.v │ │ │ ├── tv80_core.v │ │ │ ├── tv80_mcode.v │ │ │ ├── tv80_reg.v │ │ │ ├── tv80n.v │ │ │ └── tv80s.v │ │ └── vga.v │ ├── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── math.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ │ ├── pll_audio_0002.qip │ │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_freak.sv │ │ └── video_mixer.sv │ └── verilator │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── imgui.ini │ │ ├── lesson3_tb.v │ │ ├── rom.hex │ │ ├── sim.sln │ │ ├── sim.vcxproj │ │ ├── sim.vcxproj.filters │ │ ├── sim.vcxproj.user │ │ ├── sim │ │ ├── imgui │ │ │ ├── Makefile │ │ │ ├── imconfig.h │ │ │ ├── imgui.cpp │ │ │ ├── imgui.h │ │ │ ├── imgui_demo.cpp │ │ │ ├── imgui_draw.cpp │ │ │ ├── imgui_impl_dx11.cpp │ │ │ ├── imgui_impl_dx11.h │ │ │ ├── imgui_impl_opengl2.cpp │ │ │ ├── imgui_impl_opengl2.h │ │ │ ├── imgui_impl_sdl.cpp │ │ │ ├── imgui_impl_sdl.h │ │ │ ├── imgui_impl_win32.cpp │ │ │ ├── imgui_impl_win32.h │ │ │ ├── imgui_internal.h │ │ │ ├── imgui_memory_editor.h │ │ │ ├── imgui_tables.cpp │ │ │ ├── imgui_widgets.cpp │ │ │ ├── imstb_rectpack.h │ │ │ ├── imstb_textedit.h │ │ │ └── imstb_truetype.h │ │ ├── sim_audio.cpp │ │ ├── sim_audio.h │ │ ├── sim_bus.cpp │ │ ├── sim_bus.h │ │ ├── sim_clock.cpp │ │ ├── sim_clock.h │ │ ├── sim_console.cpp │ │ ├── sim_console.h │ │ ├── sim_input.cpp │ │ ├── sim_input.h │ │ ├── sim_video.cpp │ │ ├── sim_video.h │ │ └── vinc │ │ │ ├── gtkwave │ │ │ ├── fastlz.c │ │ │ ├── fastlz.h │ │ │ ├── fst_config.h │ │ │ ├── fst_win_unistd.h │ │ │ ├── fstapi.c │ │ │ ├── fstapi.h │ │ │ ├── lz4.c │ │ │ ├── lz4.h │ │ │ └── wavealloca.h │ │ │ ├── verilated.cpp │ │ │ ├── verilated.h │ │ │ ├── verilated.mk │ │ │ ├── verilated.mk.in │ │ │ ├── verilated.v │ │ │ ├── verilated_config.h │ │ │ ├── verilated_config.h.in │ │ │ ├── verilated_cov.cpp │ │ │ ├── verilated_cov.h │ │ │ ├── verilated_cov_key.h │ │ │ ├── verilated_dpi.cpp │ │ │ ├── verilated_dpi.h │ │ │ ├── verilated_fst_c.cpp │ │ │ ├── verilated_fst_c.h │ │ │ ├── verilated_fst_sc.cpp │ │ │ ├── verilated_fst_sc.h │ │ │ ├── verilated_heavy.h │ │ │ ├── verilated_imp.h │ │ │ ├── verilated_intrinsics.h │ │ │ ├── verilated_save.cpp │ │ │ ├── verilated_save.h │ │ │ ├── verilated_sc.h │ │ │ ├── verilated_sym_props.h │ │ │ ├── verilated_syms.h │ │ │ ├── verilated_threads.cpp │ │ │ ├── verilated_threads.h │ │ │ ├── verilated_trace.h │ │ │ ├── verilated_trace_defs.h │ │ │ ├── verilated_trace_imp.cpp │ │ │ ├── verilated_unordered_set_map.h │ │ │ ├── verilated_vcd_c.cpp │ │ │ ├── verilated_vcd_c.h │ │ │ ├── verilated_vcd_sc.cpp │ │ │ ├── verilated_vcd_sc.h │ │ │ ├── verilated_vpi.cpp │ │ │ ├── verilated_vpi.h │ │ │ ├── verilatedos.h │ │ │ └── vltstd │ │ │ ├── svdpi.h │ │ │ └── vpi_user.h │ │ ├── sim_main.cpp │ │ └── verilate.sh ├── lesson3_68k │ ├── LICENSE │ ├── README.md │ ├── clean.bat │ ├── demo68k.jpg │ ├── demo68k.qpf │ ├── demo68k.qsf │ ├── demo68k.sv │ ├── files.qip │ ├── releases │ │ └── _put_rbf_here_ │ ├── rom │ │ ├── 68k.ld │ │ ├── bin2hex │ │ │ └── bin2hex.c │ │ ├── go.bat │ │ └── rom.c │ ├── rtl │ │ ├── fx68k.v │ │ ├── fx68kAlu.v │ │ ├── m68k.v │ │ ├── m68k_tb.v │ │ ├── microrom.mem │ │ ├── nanorom.mem │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── ram8kx16.qip │ │ ├── ram8kx16.v │ │ ├── ram8kx16_bb.v │ │ ├── rom.hex │ │ ├── rom8kx16.qip │ │ ├── rom8kx16.v │ │ ├── rom8kx16_bb.v │ │ ├── uaddrPla.v │ │ ├── video_timing.v │ │ ├── vram.qip │ │ ├── vram.v │ │ ├── vram_bb.v │ │ └── vram_inst.v │ └── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── math.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ ├── pll_audio_0002.qip │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_freak.sv │ │ └── video_mixer.sv ├── lesson4 │ ├── Lesson4.qpf │ ├── Lesson4.qsf │ ├── Lesson4.sv │ ├── Lesson4_description.txt │ ├── Makefile │ ├── T80 │ │ ├── T80.vhd │ │ ├── T80_ALU.vhd │ │ ├── T80_MCode.vhd │ │ ├── T80_Reg.vhd │ │ ├── T80pa.vhd │ │ ├── T80s.vhd │ │ └── t80.qip │ ├── boot_rom.c │ ├── boot_rom.hex │ ├── boot_rom.qip │ ├── boot_rom.v │ ├── sdram.v │ ├── sys │ │ ├── ascal.vhd │ │ ├── build_id.tcl │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── lpf48k.sv │ │ ├── osd.v │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ └── pll_0002.v │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_hdmi_cfg.qip │ │ ├── pll_hdmi_cfg.v │ │ ├── pll_hdmi_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── reset_source.v │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_mixer.sv │ │ └── vip_config.sv │ └── vga.v ├── lesson6 │ ├── Lesson6.qpf │ ├── Lesson6.qsf │ ├── Lesson6.rom │ ├── Lesson6.sv │ ├── Lesson6_description.txt │ ├── Makefile │ ├── T80 │ │ ├── T80.vhd │ │ ├── T80_ALU.vhd │ │ ├── T80_MCode.vhd │ │ ├── T80_Reg.vhd │ │ ├── T80pa.vhd │ │ ├── T80s.vhd │ │ └── t80.qip │ ├── boot_rom.c │ ├── irqvec.s │ ├── lesson6.png │ ├── sdram.v │ ├── sys │ │ ├── ascal.vhd │ │ ├── build_id.tcl │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── lpf48k.sv │ │ ├── osd.v │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ └── pll_0002.v │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_hdmi_cfg.qip │ │ ├── pll_hdmi_cfg.v │ │ ├── pll_hdmi_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── reset_source.v │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_mixer.sv │ │ └── vip_config.sv │ └── vga.v ├── lesson8 │ ├── Lesson8.qpf │ ├── Lesson8.qsf │ ├── Lesson8.sv │ ├── Lesson8 │ │ ├── Lesson8.rom │ │ └── song.ym │ ├── Lesson8_description.txt │ ├── Makefile │ ├── T80 │ │ ├── T80.vhd │ │ ├── T80_ALU.vhd │ │ ├── T80_MCode.vhd │ │ ├── T80_Reg.vhd │ │ ├── T80pa.vhd │ │ ├── T80s.vhd │ │ └── t80.qip │ ├── YM2149_volmix.vhd │ ├── bin2c.c │ ├── boot_rom.c │ ├── diskio.h │ ├── font.c │ ├── font.fnt │ ├── integer.h │ ├── irqvec.s │ ├── lesson8.png │ ├── mmc.c │ ├── pff.c │ ├── pff.h │ ├── pffconf.h │ ├── sdram.v │ ├── sigma_delta_dac2.v │ ├── soc.v │ ├── song.ym │ ├── sys │ │ ├── ascal.vhd │ │ ├── build_id.tcl │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── lpf48k.sv │ │ ├── osd.v │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ └── pll_0002.v │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ │ ├── pll_hdmi_0002.qip │ │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_hdmi_cfg.qip │ │ ├── pll_hdmi_cfg.v │ │ ├── pll_hdmi_cfg │ │ │ ├── altera_pll_reconfig_core.v │ │ │ └── altera_pll_reconfig_top.v │ │ ├── reset_source.v │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_mixer.sv │ │ └── vip_config.sv │ ├── vga.v │ ├── vol_table_array.vhd │ └── ym_deint.c └── lesson9 │ ├── Lesson9.qpf │ ├── Lesson9.qsf │ ├── Lesson9.sv │ ├── Lesson9 │ └── boot.rom │ ├── Lesson9_description.txt │ ├── Makefile │ ├── T80 │ ├── T80.vhd │ ├── T80_ALU.vhd │ ├── T80_MCode.vhd │ ├── T80_Reg.vhd │ ├── T80pa.vhd │ ├── T80s.vhd │ └── t80.qip │ ├── bin2c.c │ ├── boot_rom.c │ ├── font.c │ ├── font.fnt │ ├── irqvec.s │ ├── keyboard.v │ ├── lesson9.png │ ├── mouse.v │ ├── ps2_intf.vhd │ ├── sdram.v │ ├── soc.v │ ├── stp3.stp │ ├── sys │ ├── ascal.vhd │ ├── build_id.tcl │ ├── hdmi_config.sv │ ├── hps_io.v │ ├── hq2x.sv │ ├── i2c.v │ ├── i2s.v │ ├── lpf48k.sv │ ├── osd.v │ ├── pll.qip │ ├── pll.v │ ├── pll │ │ ├── pll_0002.qip │ │ └── pll_0002.v │ ├── pll_hdmi.qip │ ├── pll_hdmi.v │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ └── pll_hdmi_0002.v │ ├── pll_hdmi_adj.vhd │ ├── pll_hdmi_cfg.qip │ ├── pll_hdmi_cfg.v │ ├── pll_hdmi_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ ├── reset_source.v │ ├── scandoubler.v │ ├── scanlines.v │ ├── sd_card.v │ ├── sigma_delta_dac.v │ ├── spdif.v │ ├── sys.qip │ ├── sys_top.sdc │ ├── sys_top.v │ ├── sysmem.sv │ ├── vga_out.sv │ ├── video_cleaner.sv │ ├── video_mixer.sv │ └── vip_config.sv │ └── vga.v ├── ddrgraphics ├── ddrbackground │ ├── DDRBackground.qpf │ ├── DDRBackground.qsf │ ├── DDRBackground.srf │ ├── DDRBackground.sv │ ├── README.md │ ├── files.qip │ ├── rtl │ │ ├── base_pack.vhd │ │ ├── ddram.sv │ │ ├── dpram.vhd │ │ ├── ovo.vhd │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── soc.v │ │ └── video.v │ ├── stp1.stp │ └── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ ├── pll_0002.qip │ │ ├── pll_0002.v │ │ └── pll_0002_q13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ ├── pll_audio_0002.qip │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ ├── pll_hdmi_0002.v │ │ └── pll_hdmi_0002_q13.qip │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_crop.sv │ │ └── video_mixer.sv ├── ddrbackground512 │ ├── DDRBackground.srf │ ├── DDRBackground512.qpf │ ├── DDRBackground512.qsf │ ├── DDRBackground512.sv │ ├── README.md │ ├── files.qip │ ├── rtl │ │ ├── base_pack.vhd │ │ ├── ddram.sv │ │ ├── dpram.vhd │ │ ├── ovo.vhd │ │ ├── pattern_vg.v │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ ├── soc.v │ │ ├── sync_vg.v │ │ ├── top_sync_vg_pattern.v │ │ └── video.v │ ├── stp1.stp │ └── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ ├── pll_0002.qip │ │ ├── pll_0002.v │ │ └── pll_0002_q13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ ├── pll_audio_0002.qip │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ ├── pll_hdmi_0002.v │ │ └── pll_hdmi_0002_q13.qip │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sd_card.v │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_crop.sv │ │ └── video_mixer.sv └── ddrbackground5128bitnewddr │ ├── DDRBackground.srf │ ├── DDRBackground5128bit.qpf │ ├── DDRBackground5128bit.qsf │ ├── DDRBackground5128bit.sv │ ├── README.md │ ├── files.qip │ ├── pal_ram.qip │ ├── pal_ram.v │ ├── pal_ram_bb.v │ ├── rtl │ ├── base_pack.vhd │ ├── ddram.sv │ ├── dpram.vhd │ ├── ovo.vhd │ ├── pattern_vg.v │ ├── pll.qip │ ├── pll.v │ ├── pll │ │ ├── pll_0002.qip │ │ ├── pll_0002.v │ │ └── pll_0002_q13.qip │ ├── ram64_8.qip │ ├── ram64_8.v │ ├── ram64_8_bb.v │ ├── soc.v │ ├── sync_vg.v │ ├── top_sync_vg_pattern.v │ └── video.v │ ├── stp1.stp │ └── sys │ ├── alsa.sv │ ├── arcade_video.v │ ├── ascal.vhd │ ├── audio_out.v │ ├── build_id.tcl │ ├── ddr_svc.sv │ ├── f2sdram_safe_terminator.sv │ ├── gamma_corr.sv │ ├── hdmi_config.sv │ ├── hps_io.v │ ├── hq2x.sv │ ├── i2c.v │ ├── i2s.v │ ├── iir_filter.v │ ├── ltc2308.sv │ ├── mcp23009.sv │ ├── mt32pi.sv │ ├── osd.v │ ├── pll.13.qip │ ├── pll.qip │ ├── pll.v │ ├── pll │ ├── pll_0002.qip │ ├── pll_0002.v │ └── pll_0002_q13.qip │ ├── pll_audio.13.qip │ ├── pll_audio.qip │ ├── pll_audio.v │ ├── pll_audio │ ├── pll_audio_0002.qip │ └── pll_audio_0002.v │ ├── pll_cfg.qip │ ├── pll_cfg.v │ ├── pll_cfg │ ├── altera_pll_reconfig_core.v │ └── altera_pll_reconfig_top.v │ ├── pll_hdmi.13.qip │ ├── pll_hdmi.qip │ ├── pll_hdmi.v │ ├── pll_hdmi │ ├── pll_hdmi_0002.qip │ ├── pll_hdmi_0002.v │ └── pll_hdmi_0002_q13.qip │ ├── pll_hdmi_adj.vhd │ ├── pll_q13.qip │ ├── pll_q17.qip │ ├── scandoubler.v │ ├── scanlines.v │ ├── sd_card.sv │ ├── sd_card.v │ ├── sigma_delta_dac.v │ ├── spdif.v │ ├── sys.qip │ ├── sys.tcl │ ├── sys_analog.tcl │ ├── sys_dual_sdram.tcl │ ├── sys_top.sdc │ ├── sys_top.v │ ├── sysmem.sv │ ├── vga_out.sv │ ├── video_cleaner.sv │ ├── video_crop.sv │ └── video_mixer.sv └── verilator └── detect2600_verilator ├── 2600mapper.csv ├── Makefile ├── README.md ├── atari_verilator.v ├── cart_constants.vh ├── check.py ├── detect2600.sv ├── romschecklist.chk └── sim_main.cpp /.gitignore: -------------------------------------------------------------------------------- 1 | db 2 | greybox_tmp 3 | incremental_db 4 | output_files 5 | simulation 6 | hc_output 7 | scaler 8 | hps_isw_handoff 9 | vip 10 | *_sim 11 | .qsys_edit 12 | PLLJ_PLLSPE_INFO.txt 13 | *.bak 14 | *.orig 15 | *.rej 16 | *.qdf 17 | *.rpt 18 | *.smsg 19 | *.summary 20 | *.done 21 | *.jdi 22 | *.pin 23 | *.sof 24 | *.qws 25 | *.ppf 26 | *.ddb 27 | build_id.v 28 | c5_pin_model_dump.txt 29 | *.sopcinfo 30 | *.csv 31 | *.f 32 | *.cmp 33 | *.sip 34 | *.spd 35 | *.bsf 36 | *~ 37 | *.xml 38 | *.cdf 39 | *.qarlog 40 | qar_info.json 41 | .vs 42 | Debug 43 | Release 44 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # MiSTer Tutorial Repo 2 | 3 | 4 | ## Start with the basic lessons. Most of these are ported from MiST 5 | 6 | [Basic Lessons](basic) 7 | 8 | ## There are a number of graphics setups that render from DDRAM 9 | 10 | [ddrgraphics](ddrgraphics) 11 | 12 | ## There are some good sound demos that use SDRAM and DDRAM 13 | 14 | [advanced](advanced) -------------------------------------------------------------------------------- /advanced/ddrsound/DDRSound.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.0" 2 | PROJECT_REVISION = "DDRSound" 3 | -------------------------------------------------------------------------------- /advanced/ddrsound/README.md: -------------------------------------------------------------------------------- 1 | # DDRSound 2 | 3 | This demo takes the wav parser and player and has it store and read the wav data from ddr memory. We are using an 8bit interface, but it might make sense to use a 16bit interface. 4 | 5 | The DDR code requires that you present an address to the controller, and then wait for it to return a signal saying that the byte is available. This makes the state machine in the wav player a little more complicated. Also, writing data is a bit more complicated, because we need to use the ioctl_wait to tell the HPS to wait until the ddr system has written the data. 6 | 7 | The wav_wr (we) line doesn't want to stay high. It needs to be high to start, and then can't go high until wav_data_ready. Basically, 8 | it needs to be high for one clock, then low while we wait for the ddr system to tell us the ram is ready to take another write. 9 | 10 | 11 | -------------------------------------------------------------------------------- /advanced/ddrsound/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE soc.v 3 | set_global_assignment -name SYSTEMVERILOG_FILE video.v 4 | set_global_assignment -name VHDL_FILE ovo.vhd 5 | set_global_assignment -name VHDL_FILE base_pack.vhd 6 | set_global_assignment -name SYSTEMVERILOG_FILE wave_sound.sv 7 | set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv 8 | set_global_assignment -name SYSTEMVERILOG_FILE "DDRSound.sv" 9 | -------------------------------------------------------------------------------- /advanced/ddrsound/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input pixel_clock, 7 | output [9:0] hcnt, 8 | output VGA_HS, 9 | output VGA_VS, 10 | output [7:0] VGA_R, 11 | output [7:0] VGA_G, 12 | output [7:0] VGA_B, 13 | output VGA_DE, 14 | output VGA_HBLANK, 15 | output VGA_VBLANK 16 | ); 17 | 18 | 19 | 20 | video_gen video_gen ( 21 | .reset (reset), 22 | .hcnt(hcnt), 23 | .pclk (pixel_clock), 24 | .hs (VGA_HS), 25 | .vs (VGA_VS), 26 | .r (VGA_R), 27 | .g (VGA_G), 28 | .b (VGA_B), 29 | .VGA_HBLANK(VGA_HBLANK), 30 | .VGA_VBLANK(VGA_VBLANK), 31 | .VGA_DE(VGA_DE) 32 | ); 33 | 34 | 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 8 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] 9 | set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll_hdmi.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] 8 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] 9 | set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 6 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 4 | -------------------------------------------------------------------------------- /advanced/ddrsound/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /advanced/fbexample/.gitignore: -------------------------------------------------------------------------------- 1 | db 2 | greybox_tmp 3 | incremental_db 4 | output_files 5 | simulation 6 | hc_output 7 | scaler 8 | hps_isw_handoff 9 | vip 10 | *_sim 11 | .qsys_edit 12 | PLLJ_PLLSPE_INFO.txt 13 | *.bak 14 | *.orig 15 | *.rej 16 | *.qdf 17 | *.rpt 18 | *.smsg 19 | *.summary 20 | *.done 21 | *.jdi 22 | *.pin 23 | *.sof 24 | *.qws 25 | *.ppf 26 | *.ddb 27 | build_id.v 28 | c5_pin_model_dump.txt 29 | *.sopcinfo 30 | *.csv 31 | *.f 32 | *.cmp 33 | *.sip 34 | *.spd 35 | *.bsf 36 | *~ 37 | *.xml 38 | *_netlist 39 | *.cdf 40 | **/.DS_Store -------------------------------------------------------------------------------- /advanced/fbexample/FBExample.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.0" 2 | PROJECT_REVISION = "FBExample" 3 | -------------------------------------------------------------------------------- /advanced/fbexample/FBExample.sdc: -------------------------------------------------------------------------------- 1 | derive_pll_clocks 2 | derive_clock_uncertainty 3 | 4 | # core specific constraints 5 | -------------------------------------------------------------------------------- /advanced/fbexample/Readme.md: -------------------------------------------------------------------------------- 1 | # FB Example 2 | 3 | This is a simple core to display a 1280x720 (720p) static image using the framebuffer from DDRAM. We use an MRA to pop the raw image we make with python into ram. 4 | 5 | -------------------------------------------------------------------------------- /advanced/fbexample/clean.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | del /s *.bak 3 | del /s *.orig 4 | del /s *.rej 5 | del /s *~ 6 | rmdir /s /q db 7 | rmdir /s /q incremental_db 8 | rmdir /s /q output_files 9 | rmdir /s /q simulation 10 | rmdir /s /q greybox_tmp 11 | rmdir /s /q hc_output 12 | rmdir /s /q .qsys_edit 13 | rmdir /s /q hps_isw_handoff 14 | rmdir /s /q sys\.qsys_edit 15 | rmdir /s /q sys\vip 16 | for /d %%i in (sys\*_sim) do rmdir /s /q "%%i" 17 | for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i" 18 | del build_id.v 19 | del c5_pin_model_dump.txt 20 | del PLLJ_PLLSPE_INFO.txt 21 | del /s *.qws 22 | del /s *.ppf 23 | del /s *.ddb 24 | del /s *.csv 25 | del /s *.cmp 26 | del /s *.sip 27 | del /s *.spd 28 | del /s *.bsf 29 | del /s *.f 30 | del /s *.sopcinfo 31 | del /s *.xml 32 | del *.cdf 33 | del *.rpt 34 | del /s new_rtl_netlist 35 | del /s old_rtl_netlist 36 | pause 37 | -------------------------------------------------------------------------------- /advanced/fbexample/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SDC_FILE FBExample.sdc 3 | set_global_assignment -name SYSTEMVERILOG_FILE FBExample.sv 4 | -------------------------------------------------------------------------------- /advanced/fbexample/releases/FB.mra: -------------------------------------------------------------------------------- 1 | 2 | Journey 3 | 0216 4 | 201912310000 5 | 1984 6 | Bally Midway 7 | Action 8 | FBExample 9 | image 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /advanced/fbexample/releases/wallpaper1.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/advanced/fbexample/releases/wallpaper1.zip -------------------------------------------------------------------------------- /advanced/fbexample/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/fbexample/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/fbexample/scripts/convertimage.py: -------------------------------------------------------------------------------- 1 | from PIL import Image 2 | import sys 3 | 4 | from array import * 5 | 6 | def convertImage(name): 7 | 8 | name_array = name.split('.') 9 | print(name_array) 10 | print(name_array[:-1]) 11 | out_name='_'.join(name_array[:-1])+'.img' 12 | print(out_name) 13 | 14 | im = Image.open(name).convert('RGBA') 15 | (s,s,width,height)=im.getbbox() 16 | print(width,height) 17 | count = 0 18 | 19 | bin_array3 = array('B') 20 | 21 | for y in range(height): 22 | for x in range(width): 23 | count = count+1 24 | pixel = im.getpixel((x,y)) 25 | print(pixel) 26 | r = pixel[0] 27 | g = pixel[1] 28 | b = pixel[2] 29 | a = pixel[3] 30 | #r = count # for debugging 31 | 32 | bin_array3.append(r&0xFF) 33 | bin_array3.append(g&0xFF) 34 | bin_array3.append(b&0xFF) 35 | bin_array3.append(a&0xFF) 36 | newFile = open(out_name, "wb") 37 | newFile.write(bin_array3) 38 | 39 | if __name__ == "__main__": 40 | name="hello.png" 41 | print(len(sys.argv)) 42 | if (len(sys.argv)<=1): 43 | name="wallpaper1.jpg" 44 | else: 45 | name=sys.argv[1] 46 | print(name) 47 | convertImage(name) 48 | -------------------------------------------------------------------------------- /advanced/fbexample/scripts/wallpaper1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/advanced/fbexample/scripts/wallpaper1.jpg -------------------------------------------------------------------------------- /advanced/fbexample/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /advanced/fbexample/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /advanced/fbexample/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/fbexample/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /advanced/fbexample/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /advanced/fbexample/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /advanced/fbexample/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /advanced/sound/Sound.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.0" 2 | PROJECT_REVISION = "Sound" 3 | -------------------------------------------------------------------------------- /advanced/sound/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE soc.v 3 | set_global_assignment -name SYSTEMVERILOG_FILE video.v 4 | set_global_assignment -name SYSTEMVERILOG_FILE sound_rom.v 5 | set_global_assignment -name VHDL_FILE ovo.vhd 6 | set_global_assignment -name VHDL_FILE base_pack.vhd 7 | set_global_assignment -name VHDL_FILE dpram.vhd 8 | 9 | set_global_assignment -name SYSTEMVERILOG_FILE "Sound.sv" 10 | -------------------------------------------------------------------------------- /advanced/sound/readme.md: -------------------------------------------------------------------------------- 1 | ## 2 | http://soundfile.sapp.org/doc/WaveFormat/ 3 | https://github.com/bustinstuff/fpga/blob/master/prog_fpgas/mojo/ch08_wav_player/src/wav_player.v 4 | 5 | https://tomverbeure.github.io/video_timings_calculator 6 | -------------------------------------------------------------------------------- /advanced/sound/romextract/convert_sound.sh: -------------------------------------------------------------------------------- 1 | #sox sepways.wav --bits 16 --encoding signed-integer --endian little journey.raw 2 | #sox sepways.wav --bits 16 --encoding signed-integer --endian little -r 11025 -c 1 journey.raw 3 | sox sepways.wav -b 8 --encoding signed-integer --endian little -r 11025 -c 1 journey.raw 4 | head -c16384 journey.raw > jshort.rom 5 | -------------------------------------------------------------------------------- /advanced/sound/romextract/dumppf.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #define kSize 1024*16 5 | 6 | unsigned char b[kSize]; 7 | 8 | main(int argc, char *argv[]) 9 | { 10 | int i; 11 | char *bs; 12 | 13 | if (1 || argc > 1 && argv[1][0] == '-' && argv[1][1] == 'c') { 14 | // case 15 | read(0, b, kSize); 16 | 17 | printf(" // centipede\n"); 18 | printf(" case (a)\n"); 19 | for (i = 0; i < kSize; i++) { 20 | printf("\t14'h%03x: q = 8'h%02x; // 0x%03x\n", i, b[i], i); 21 | } 22 | printf(" endcase\n"); 23 | } else { 24 | // initial block 25 | printf("initial begin\n"); 26 | printf("\t// centipede\n"); 27 | 28 | read(0, b, 8192); 29 | for (i = 0; i < 2048; i++) { 30 | printf("\trom[%d] = 8'h%02x; // 0x%04x\n", i, b[i], i); 31 | } 32 | 33 | printf("end\n"); 34 | } 35 | 36 | exit(0); 37 | } 38 | -------------------------------------------------------------------------------- /advanced/sound/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input pixel_clock, 7 | output SDRAM_nCS, 8 | output VGA_HS, 9 | output VGA_VS, 10 | output [7:0] VGA_R, 11 | output [7:0] VGA_G, 12 | output [7:0] VGA_B, 13 | output VGA_DE, 14 | output VGA_HBLANK, 15 | output VGA_VBLANK 16 | ); 17 | 18 | // de-activate unused SDRAM 19 | assign SDRAM_nCS = 1; 20 | 21 | 22 | video_gen video_gen ( 23 | .reset (reset), 24 | .pclk (pixel_clock), 25 | .hs (VGA_HS), 26 | .vs (VGA_VS), 27 | .r (VGA_R), 28 | .g (VGA_G), 29 | .b (VGA_B), 30 | .VGA_HBLANK(VGA_HBLANK), 31 | .VGA_VBLANK(VGA_VBLANK), 32 | .VGA_DE(VGA_DE) 33 | ); 34 | 35 | 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /advanced/sound/sound_rom.v: -------------------------------------------------------------------------------- 1 | 2 | module sound_rom(input clk, 3 | input reset, 4 | input [13:0] a, 5 | output [7:0] dout 6 | ); 7 | 8 | reg [7:0] q; 9 | 10 | always @(posedge clk or posedge reset) 11 | if (reset) 12 | q = 0; 13 | else 14 | //`include "../roms/extract/rom_code_case.v" 15 | `include "dk_wave.v" 16 | 17 | assign dout = q; 18 | 19 | 20 | endmodule // rom 21 | -------------------------------------------------------------------------------- /advanced/sound/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 8 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] 9 | set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll_hdmi.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] 8 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] 9 | set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 6 | -------------------------------------------------------------------------------- /advanced/sound/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 4 | -------------------------------------------------------------------------------- /advanced/sound/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /advanced/synth/Synth.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.0" 2 | PROJECT_REVISION = "Synth" 3 | -------------------------------------------------------------------------------- /advanced/synth/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE soc.v 3 | set_global_assignment -name SYSTEMVERILOG_FILE video.v 4 | set_global_assignment -name VHDL_FILE ovo.vhd 5 | set_global_assignment -name VHDL_FILE base_pack.vhd 6 | set_global_assignment -name SYSTEMVERILOG_FILE wave_sound.sv 7 | set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv 8 | set_global_assignment -name SYSTEMVERILOG_FILE "romsynth.v" 9 | set_global_assignment -name SYSTEMVERILOG_FILE "Synth.sv" 10 | -------------------------------------------------------------------------------- /advanced/synth/hdl/eight_bit_exponential_decay_lookup.vh: -------------------------------------------------------------------------------- 1 | `ifndef __TINY_SYNTH_EXP_LOOKUP_TABLE__ 2 | `define __TINY_SYNTH_EXP_LOOKUP_TABLE__ 3 | 4 | /* 5 | * map from 8-bit -> 8-bit value for exponential falloff of decay and release 6 | * in the envelope generator. 7 | */ 8 | 9 | `ifndef __TINY_SYNTH_ROOT_FOLDER 10 | `define __TINY_SYNTH_ROOT_FOLDER ".." 11 | `endif 12 | 13 | module eight_bit_exponential_decay_lookup ( 14 | input wire [7:0] din, 15 | output wire [7:0] dout 16 | ); 17 | 18 | reg [0:7] exp_lookup [0:255]; 19 | initial $readmemh("data/exp_lookup_table.rom", exp_lookup); 20 | 21 | assign dout = exp_lookup[din]; 22 | 23 | endmodule 24 | 25 | `endif 26 | -------------------------------------------------------------------------------- /advanced/synth/hdl/tiny-synth-all.vh: -------------------------------------------------------------------------------- 1 | `ifndef __TINY_SYNTH_ALL__ 2 | `define __TINY_SYNTH_ALL__ 3 | 4 | `ifndef __TINY_SYNTH_ROOT_FOLDER 5 | `define __TINY_SYNTH_ROOT_FOLDER ("..") 6 | `endif 7 | 8 | `include "clock_divider.vh" 9 | `include "amplitude_modulator.vh" 10 | `include "eight_bit_exponential_decay_lookup.vh" 11 | `include "envelope_generator.vh" 12 | `include "pdm_dac.vh" 13 | `include "tone_generator_noise.vh" 14 | `include "tone_generator_pulse.vh" 15 | `include "tone_generator_saw.vh" 16 | `include "tone_generator_triangle.vh" 17 | `include "tone_generator.vh" 18 | `include "two_into_one_mixer.vh" 19 | `include "multi_channel_mixer.vh" 20 | `include "voice.vh" 21 | `include "flanger.vh" 22 | `include "filter_ewma.vh" 23 | `include "filter_svf.vh" 24 | `include "filter_svf_pipelined.vh" 25 | 26 | `endif 27 | -------------------------------------------------------------------------------- /advanced/synth/hdl/tone_generator_saw.vh: -------------------------------------------------------------------------------- 1 | `ifndef __TINY_SYNTH_TONE_SAW__ 2 | `define __TINY_SYNTH_TONE_SAW__ 3 | /* ============================= 4 | * Sawtooth tone generator 5 | * ============================= 6 | * 7 | * Generates a sawtooth output waveform. 8 | * 9 | * Principle of operation: 10 | * 11 | * Take the upper OUTPUT_BITS from the accumulator. 12 | */ 13 | module tone_generator_saw #( 14 | parameter ACCUMULATOR_BITS = 24, 15 | parameter OUTPUT_BITS = 12) 16 | ( 17 | input [ACCUMULATOR_BITS-1:0] accumulator, 18 | output wire [OUTPUT_BITS-1:0] dout); 19 | 20 | assign dout = accumulator[ACCUMULATOR_BITS-1 -: OUTPUT_BITS]; 21 | 22 | endmodule 23 | 24 | `endif 25 | -------------------------------------------------------------------------------- /advanced/synth/hdl/two_into_one_mixer.vh: -------------------------------------------------------------------------------- 1 | `ifndef __TINY_SYNTH_TWO_INTO_ONE_MIXER__ 2 | `define __TINY_SYNTH_TWO_INTO_ONE_MIXER__ 3 | 4 | /* =================== 5 | * Two-into-one mixer 6 | * =================== 7 | * 8 | * Mixes two input signals into a single output. 9 | */ 10 | module two_into_one_mixer #( 11 | parameter DATA_BITS = 12 12 | ) 13 | ( 14 | input signed [DATA_BITS-1:0] a, 15 | input signed [DATA_BITS-1:0] b, 16 | output signed [DATA_BITS-1:0] dout 17 | ); 18 | 19 | wire signed [DATA_BITS:0] intermediate; 20 | 21 | assign intermediate = a+b; 22 | 23 | assign dout = intermediate >>> 1; 24 | 25 | endmodule 26 | 27 | `endif 28 | -------------------------------------------------------------------------------- /advanced/synth/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input pixel_clock, 7 | output [9:0] hcnt, 8 | output VGA_HS, 9 | output VGA_VS, 10 | output [7:0] VGA_R, 11 | output [7:0] VGA_G, 12 | output [7:0] VGA_B, 13 | output VGA_DE, 14 | output VGA_HBLANK, 15 | output VGA_VBLANK 16 | ); 17 | 18 | 19 | 20 | video_gen video_gen ( 21 | .reset (reset), 22 | .hcnt(hcnt), 23 | .pclk (pixel_clock), 24 | .hs (VGA_HS), 25 | .vs (VGA_VS), 26 | .r (VGA_R), 27 | .g (VGA_G), 28 | .b (VGA_B), 29 | .VGA_HBLANK(VGA_HBLANK), 30 | .VGA_VBLANK(VGA_VBLANK), 31 | .VGA_DE(VGA_DE) 32 | ); 33 | 34 | 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /advanced/synth/syn/double.syn: -------------------------------------------------------------------------------- 1 | "@ -------------------------------------------------------------------------------- /advanced/synth/syn/noise.syn: -------------------------------------------------------------------------------- 1 | % -------------------------------------------------------------------------------- /advanced/synth/syn/sound.syn: -------------------------------------------------------------------------------- 1 | % -------------------------------------------------------------------------------- /advanced/synth/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 8 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] 9 | set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll_hdmi.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] 8 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] 9 | set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 6 | -------------------------------------------------------------------------------- /advanced/synth/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 4 | -------------------------------------------------------------------------------- /advanced/synth/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /advanced/vexample/VExample.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.0" 2 | PROJECT_REVISION = "VExample" 3 | -------------------------------------------------------------------------------- /advanced/vexample/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE soc.v 3 | set_global_assignment -name SYSTEMVERILOG_FILE video.v 4 | set_global_assignment -name VHDL_FILE ovo.vhd 5 | set_global_assignment -name VHDL_FILE base_pack.vhd 6 | set_global_assignment -name SYSTEMVERILOG_FILE wave_sound.v 7 | set_global_assignment -name SYSTEMVERILOG_FILE sim/nspram.sv 8 | set_global_assignment -name SYSTEMVERILOG_FILE sim/bram.sv 9 | set_global_assignment -name SYSTEMVERILOG_FILE "VExample.sv" 10 | -------------------------------------------------------------------------------- /advanced/vexample/romextract/00.wav: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/advanced/vexample/romextract/00.wav -------------------------------------------------------------------------------- /advanced/vexample/sim/bram.sv: -------------------------------------------------------------------------------- 1 | module dpram_dc #( 2 | parameter width_a = 8, 3 | parameter widthad_a = 10 4 | ) ( 5 | // Port A 6 | input wire clock_a, 7 | input wire wren_a, 8 | input wire [widthad_a-1:0] address_a, 9 | input wire [width_a-1:0] data_a, 10 | output reg [width_a-1:0] q_a, 11 | 12 | // Port B 13 | input wire clock_b, 14 | input wire wren_b, 15 | input wire [widthad_a-1:0] address_b, 16 | input wire [width_a-1:0] data_b, 17 | output reg [width_a-1:0] q_b, 18 | 19 | input wire byteena_a, 20 | input wire byteena_b 21 | ); 22 | 23 | // Shared memory 24 | reg [width_a-1:0] mem [(2**widthad_a)-1:0]; 25 | 26 | // Port A 27 | always @(posedge clock_a) begin 28 | q_a <= mem[address_a]; 29 | if(wren_a) begin 30 | q_a <= data_a; 31 | mem[address_a] <= data_a; 32 | end 33 | end 34 | 35 | // Port B 36 | always @(posedge clock_b) begin 37 | q_b <= mem[address_b]; 38 | if(wren_b) begin 39 | q_b <= data_b; 40 | mem[address_b] <= data_b; 41 | end 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /advanced/vexample/sim/dpram_dc.sv: -------------------------------------------------------------------------------- 1 | 2 | module dpram_dc #(parameter widthad_a=8, parameter width_a=8) 3 | ( 4 | input logic clock_a, 5 | input logic clock_b, 6 | input logic wren_a, 7 | input logic [(width_a-1):0] data_a, 8 | input logic byteena_a, 9 | input logic [(widthad_a-1):0] address_a, 10 | output logic [(width_a-1):0] q_a, 11 | 12 | input logic wren_b, 13 | input logic [(width_a-1):0] data_b, 14 | input logic byteena_b, 15 | input logic [(widthad_a-1):0] address_b, 16 | output logic [(width_a-1):0] q_b 17 | ); 18 | 19 | reg [(width_a-1):0] mem [(2**widthad_a-1):0]; 20 | 21 | always @(posedge clock_a) 22 | begin 23 | q_a= byteena_a ? mem[address_a] : {width_a{1'b1}}; 24 | if (wren_a) 25 | begin 26 | mem[address_a] <= data_a; 27 | q_a= byteena_a ? data_a : {width_a{1'b1}}; 28 | end 29 | //$display("a: data=%h addr=%h ",q_a, address_a ); 30 | end 31 | always @(posedge clock_b) 32 | begin 33 | q_b= byteena_b ? mem[address_b] : {width_a{1'b1}}; 34 | if (wren_b) 35 | begin 36 | mem[address_b] <= data_b; 37 | q_b= byteena_b ? data_b : {width_a{1'b1}}; 38 | end 39 | //$display("b: data=%h addr=%h ",q_b, address_b ); 40 | end 41 | 42 | 43 | 44 | endmodule: dpram_dc 45 | -------------------------------------------------------------------------------- /advanced/vexample/sim/nspram.sv: -------------------------------------------------------------------------------- 1 | module spram #( 2 | parameter data_width = 8, 3 | parameter addr_width = 10 4 | ) ( 5 | // Port A 6 | input wire clock, 7 | input wire wren, 8 | input wire [addr_width-1:0] address, 9 | input wire [data_width-1:0] data, 10 | output reg [data_width-1:0] q, 11 | 12 | input wire cs 13 | ); 14 | 15 | // Shared memory 16 | reg [data_width-1:0] mem [(2**addr_width)-1:0]; 17 | 18 | // Port A 19 | always @(posedge clock) begin 20 | q <= mem[address]; 21 | if(wren) begin 22 | q <= data; 23 | mem[address] <= data; 24 | end 25 | end 26 | 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /advanced/vexample/sim/spram.sv: -------------------------------------------------------------------------------- 1 | module spram #(parameter addr_width=8, parameter data_width=8) 2 | ( 3 | input logic clock, 4 | input logic wren, 5 | input logic [(data_width-1):0] data, 6 | input logic cs, 7 | input logic [(addr_width-1):0] address, 8 | output logic [(data_width-1):0] q 9 | ); 10 | 11 | logic [(data_width-1):0] mem [(2**addr_width-1):0]; 12 | 13 | always_ff @(posedge clock) 14 | begin 15 | if (wren) mem[address] <= data; 16 | //$display("data=%h addr=%h word=%h",data, addr, addr[31:2]); 17 | end 18 | 19 | assign q= cs ? mem[address] : {data_width{1'b1}}; 20 | 21 | endmodule: spram 22 | -------------------------------------------------------------------------------- /advanced/vexample/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input pixel_clock, 7 | output [9:0] hcnt, 8 | output VGA_HS, 9 | output VGA_VS, 10 | output [7:0] VGA_R, 11 | output [7:0] VGA_G, 12 | output [7:0] VGA_B, 13 | output VGA_DE, 14 | output VGA_HBLANK, 15 | output VGA_VBLANK 16 | ); 17 | 18 | 19 | 20 | video_gen video_gen ( 21 | .reset (reset), 22 | .hcnt(hcnt), 23 | .pclk (pixel_clock), 24 | .hs (VGA_HS), 25 | .vs (VGA_VS), 26 | .r (VGA_R), 27 | .g (VGA_G), 28 | .b (VGA_B), 29 | .VGA_HBLANK(VGA_HBLANK), 30 | .VGA_VBLANK(VGA_VBLANK), 31 | .VGA_DE(VGA_DE) 32 | ); 33 | 34 | 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /advanced/vexample/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 8 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] 9 | set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll_hdmi.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] 8 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] 9 | set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 6 | -------------------------------------------------------------------------------- /advanced/vexample/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 4 | -------------------------------------------------------------------------------- /advanced/vexample/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /advanced/vexample/verilator/readme.txt: -------------------------------------------------------------------------------- 1 | https://danstrother.com/2010/09/11/inferring-rams-in-fpgas/#verilog 2 | -------------------------------------------------------------------------------- /advanced/vexample/verilator/vga.h: -------------------------------------------------------------------------------- 1 | #ifdef __cplusplus 2 | extern "C" { 3 | #endif 4 | int joystick_fire(void); 5 | int joystick_start(void); 6 | int joystick_coin(void); 7 | int joystick_right(void); 8 | int joystick_left(void); 9 | int joystick_up(void); 10 | int joystick_down(void); 11 | 12 | #ifdef __cplusplus 13 | } 14 | #endif 15 | -------------------------------------------------------------------------------- /advanced/zaxddr/README.md: -------------------------------------------------------------------------------- 1 | # ZaxDDR 2 | 3 | This demo will eventually hookup 1 through 0 keys, each for a different zaxxon sample. 4 | 5 | 6 | -------------------------------------------------------------------------------- /advanced/zaxddr/ZaxDDR.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.0" 2 | PROJECT_REVISION = "ZaxDDR" 3 | -------------------------------------------------------------------------------- /advanced/zaxddr/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE soc.v 2 | set_global_assignment -name SYSTEMVERILOG_FILE video.v 3 | set_global_assignment -name VHDL_FILE ovo.vhd 4 | set_global_assignment -name VHDL_FILE base_pack.vhd 5 | set_global_assignment -name SYSTEMVERILOG_FILE wave_sound.sv 6 | set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv 7 | set_global_assignment -name SYSTEMVERILOG_FILE "ZaxDDR.sv" 8 | -------------------------------------------------------------------------------- /advanced/zaxddr/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input pixel_clock, 7 | output [9:0] hcnt, 8 | output VGA_HS, 9 | output VGA_VS, 10 | output [7:0] VGA_R, 11 | output [7:0] VGA_G, 12 | output [7:0] VGA_B, 13 | output VGA_DE, 14 | output VGA_HBLANK, 15 | output VGA_VBLANK 16 | ); 17 | 18 | 19 | 20 | video_gen video_gen ( 21 | .reset (reset), 22 | .hcnt(hcnt), 23 | .pclk (pixel_clock), 24 | .hs (VGA_HS), 25 | .vs (VGA_VS), 26 | .r (VGA_R), 27 | .g (VGA_G), 28 | .b (VGA_B), 29 | .VGA_HBLANK(VGA_HBLANK), 30 | .VGA_VBLANK(VGA_VBLANK), 31 | .VGA_DE(VGA_DE) 32 | ); 33 | 34 | 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 8 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] 9 | set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll_hdmi.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] 8 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] 9 | set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 6 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 4 | -------------------------------------------------------------------------------- /advanced/zaxddr/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /advanced/zaxsound/ZaxSound.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.0" 2 | PROJECT_REVISION = "ZaxSound" 3 | -------------------------------------------------------------------------------- /advanced/zaxsound/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE soc.v 3 | set_global_assignment -name SYSTEMVERILOG_FILE video.v 4 | set_global_assignment -name SYSTEMVERILOG_FILE sound_rom.v 5 | set_global_assignment -name VHDL_FILE ovo.vhd 6 | set_global_assignment -name VHDL_FILE base_pack.vhd 7 | set_global_assignment -name VHDL_FILE dpram.vhd 8 | set_global_assignment -name SYSTEMVERILOG_FILE dkongjr_wav_sound.v 9 | set_global_assignment -name SYSTEMVERILOG_FILE "ZaxSound.sv" 10 | -------------------------------------------------------------------------------- /advanced/zaxsound/readme.md: -------------------------------------------------------------------------------- 1 | ## 2 | http://soundfile.sapp.org/doc/WaveFormat/ 3 | https://github.com/bustinstuff/fpga/blob/master/prog_fpgas/mojo/ch08_wav_player/src/wav_player.v 4 | 5 | https://tomverbeure.github.io/video_timings_calculator 6 | -------------------------------------------------------------------------------- /advanced/zaxsound/romextract/convert_sound.sh: -------------------------------------------------------------------------------- 1 | #sox sepways.wav --bits 16 --encoding signed-integer --endian little journey.raw 2 | #sox sepways.wav --bits 16 --encoding signed-integer --endian little -r 11025 -c 1 journey.raw 3 | sox sepways.wav -b 8 --encoding signed-integer --endian little -r 11025 -c 1 journey.raw 4 | head -c16384 journey.raw > jshort.rom 5 | -------------------------------------------------------------------------------- /advanced/zaxsound/romextract/dumppf.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #define kSize 1024*16 5 | 6 | unsigned char b[kSize]; 7 | 8 | main(int argc, char *argv[]) 9 | { 10 | int i; 11 | char *bs; 12 | 13 | if (1 || argc > 1 && argv[1][0] == '-' && argv[1][1] == 'c') { 14 | // case 15 | read(0, b, kSize); 16 | 17 | printf(" // centipede\n"); 18 | printf(" case (a)\n"); 19 | for (i = 0; i < kSize; i++) { 20 | printf("\t14'h%03x: q = 8'h%02x; // 0x%03x\n", i, b[i], i); 21 | } 22 | printf(" endcase\n"); 23 | } else { 24 | // initial block 25 | printf("initial begin\n"); 26 | printf("\t// centipede\n"); 27 | 28 | read(0, b, 8192); 29 | for (i = 0; i < 2048; i++) { 30 | printf("\trom[%d] = 8'h%02x; // 0x%04x\n", i, b[i], i); 31 | } 32 | 33 | printf("end\n"); 34 | } 35 | 36 | exit(0); 37 | } 38 | -------------------------------------------------------------------------------- /advanced/zaxsound/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input pixel_clock, 7 | output SDRAM_nCS, 8 | output [9:0] hcnt, 9 | output VGA_HS, 10 | output VGA_VS, 11 | output [7:0] VGA_R, 12 | output [7:0] VGA_G, 13 | output [7:0] VGA_B, 14 | output VGA_DE, 15 | output VGA_HBLANK, 16 | output VGA_VBLANK 17 | ); 18 | 19 | // de-activate unused SDRAM 20 | assign SDRAM_nCS = 1; 21 | 22 | 23 | video_gen video_gen ( 24 | .reset (reset), 25 | .hcnt(hcnt), 26 | .pclk (pixel_clock), 27 | .hs (VGA_HS), 28 | .vs (VGA_VS), 29 | .r (VGA_R), 30 | .g (VGA_G), 31 | .b (VGA_B), 32 | .VGA_HBLANK(VGA_HBLANK), 33 | .VGA_VBLANK(VGA_VBLANK), 34 | .VGA_DE(VGA_DE) 35 | ); 36 | 37 | 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /advanced/zaxsound/sound_rom.v: -------------------------------------------------------------------------------- 1 | 2 | module sound_rom(input clk, 3 | input reset, 4 | input [13:0] a, 5 | output [7:0] dout 6 | ); 7 | 8 | reg [7:0] q; 9 | 10 | always @(posedge clk or posedge reset) 11 | if (reset) 12 | q = 0; 13 | else 14 | //`include "../roms/extract/rom_code_case.v" 15 | `include "dk_wave.v" 16 | 17 | assign dout = q; 18 | 19 | 20 | endmodule // rom 21 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 8 | set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] 9 | set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll_hdmi.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] 8 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] 9 | set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"] 10 | 11 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 12 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 13 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 14 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 6 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 4 | -------------------------------------------------------------------------------- /advanced/zaxsound/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/cassette_overlay/README.md: -------------------------------------------------------------------------------- 1 | Cassette Overlay 2 | -------------------------- 3 | 4 | 5 | 6 | # Step one build existing code 7 | 8 | Load this project into quartus and build it. The RBF will be in the output_files folder, copy it to your MiSTer and see if you can run it. 9 | 10 | 11 | # Step two run simulation in linux, mac or windows 12 | 13 | [Jimmy Stone's Verilator Template](https://github.com/JimmyStones/Verilator_Template) 14 | -------------------------------------------------------------------------------- /basic/cassette_overlay/build.sh: -------------------------------------------------------------------------------- 1 | TARGETS=( verilator rtl ) 2 | 3 | # Hexify rom and font and copy to build targets 4 | for TARGET in "${TARGETS[@]}"; do 5 | od -An -t x1 -v font.pf > $TARGET/font.hex 6 | done 7 | 8 | -------------------------------------------------------------------------------- /basic/cassette_overlay/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE Overlay.sv 2 | set_global_assignment -name VERILOG_FILE rtl/vga.v 3 | set_global_assignment -name VERILOG_FILE rtl/soc.v 4 | set_global_assignment -name VERILOG_FILE rtl/overlay.v 5 | set_global_assignment -name VERILOG_FILE rtl/charmap.v 6 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/cas_bram.sv 7 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/bram.sv 8 | -------------------------------------------------------------------------------- /basic/cassette_overlay/font.pf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/cassette_overlay/font.pf -------------------------------------------------------------------------------- /basic/cassette_overlay/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/cassette_overlay/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/cassette_overlay/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /basic/cassette_overlay/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /basic/cassette_overlay/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/cassette_overlay/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/cassette_overlay/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /basic/cassette_overlay/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /basic/cassette_overlay/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/imgui.ini: -------------------------------------------------------------------------------- 1 | [Window][Debug##Default] 2 | Pos=60,60 3 | Size=400,400 4 | Collapsed=0 5 | 6 | [Window][Debug Log] 7 | Pos=19,8 8 | Size=520,600 9 | Collapsed=0 10 | 11 | [Window][Virtual Dev Board v1.0] 12 | Pos=580,10 13 | Size=1000,1000 14 | Collapsed=0 15 | 16 | [Window][RAM Editor] 17 | Pos=8,403 18 | Size=544,317 19 | Collapsed=0 20 | 21 | [Window][ROM Editor] 22 | Pos=1261,701 23 | Size=669,407 24 | Collapsed=0 25 | 26 | [Window][VRAM Editor] 27 | Pos=115,701 28 | Size=560,393 29 | Collapsed=0 30 | 31 | [Window][CPU Registers] 32 | Pos=38,206 33 | Size=269,174 34 | Collapsed=0 35 | 36 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim.vcxproj.user: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | false 5 | 6 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/sim_bus.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include 3 | #include "verilated_heavy.h" 4 | #include "sim_console.h" 5 | 6 | 7 | #ifndef _MSC_VER 8 | #else 9 | #define WIN32 10 | #endif 11 | 12 | 13 | struct SimBus_DownloadChunk { 14 | public: 15 | std::string file; 16 | int index; 17 | 18 | SimBus_DownloadChunk() { 19 | file = ""; 20 | index = -1; 21 | } 22 | 23 | SimBus_DownloadChunk(std::string file, int index) { 24 | this->file = std::string(file); 25 | this->index = index; 26 | } 27 | }; 28 | 29 | struct SimBus { 30 | public: 31 | 32 | IData* ioctl_addr; 33 | CData* ioctl_index; 34 | CData* ioctl_wait; 35 | CData* ioctl_download; 36 | CData* ioctl_upload; 37 | CData* ioctl_wr; 38 | CData* ioctl_dout; 39 | CData* ioctl_din; 40 | 41 | void BeforeEval(void); 42 | void AfterEval(void); 43 | void QueueDownload(std::string file, int index); 44 | 45 | SimBus(DebugConsole c); 46 | ~SimBus(); 47 | 48 | private: 49 | std::queue downloadQueue; 50 | SimBus_DownloadChunk currentDownload; 51 | void SetDownload(std::string file, int index); 52 | }; 53 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/sim_clock.cpp: -------------------------------------------------------------------------------- 1 | #include "sim_clock.h" 2 | #include 3 | 4 | //bool clk, old; 5 | //int ratio, count; 6 | 7 | SimClock::SimClock(int r) { 8 | ratio = r; 9 | count = 0; 10 | clk = false; 11 | old = false; 12 | } 13 | 14 | SimClock::~SimClock() { 15 | } 16 | 17 | void SimClock::Tick() { 18 | old = clk; 19 | count++; 20 | if (count >= ratio) { 21 | clk = !clk; count = 0; 22 | } 23 | } 24 | 25 | void SimClock::Reset() { 26 | count = 0; 27 | clk = false; 28 | old = false; 29 | } 30 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/sim_clock.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | class SimClock 4 | { 5 | 6 | public: 7 | bool clk, old; 8 | 9 | SimClock(int r); 10 | ~SimClock(); 11 | void Tick(); 12 | void Reset(); 13 | 14 | private: 15 | int ratio, count; 16 | }; -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/sim_console.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "imgui.h" 3 | 4 | struct DebugConsole { 5 | public: 6 | void AddLog(const char* fmt, ...) IM_FMTARGS(2); 7 | DebugConsole(); 8 | ~DebugConsole(); 9 | void ClearLog(); 10 | void Draw(const char* title, bool* p_open); 11 | void ExecCommand(const char* command_line); 12 | int TextEditCallback(ImGuiInputTextCallbackData* data); 13 | }; 14 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/sim_input.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef _MSC_VER 3 | #else 4 | #define WIN32 5 | #pragma comment(lib, "dinput8.lib") 6 | #pragma comment(lib, "dxguid.lib") 7 | #endif 8 | #include 9 | 10 | struct SimInput { 11 | public: 12 | 13 | int inputCount = 0; 14 | bool inputs[16]; 15 | int mappings[16]; 16 | 17 | void Read(); 18 | int Initialise(); 19 | void CleanUp(); 20 | void SetMapping(int index, int code); 21 | SimInput(int count); 22 | ~SimInput(); 23 | }; 24 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/sim_video.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #ifndef _MSC_VER 5 | #include "imgui_impl_sdl.h" 6 | #include "imgui_impl_opengl2.h" 7 | #else 8 | #define WIN32 9 | #include "imgui_impl_win32.h" 10 | #include "imgui_impl_dx11.h" 11 | #include 12 | #include 13 | #endif 14 | 15 | struct SimVideo { 16 | public: 17 | 18 | int output_width; 19 | int output_height; 20 | int output_rotate; 21 | bool output_vflip; 22 | 23 | int count_pixel; 24 | int count_line; 25 | int count_frame; 26 | 27 | float stats_fps; 28 | float stats_frameTime; 29 | int stats_xMax; 30 | int stats_xMin; 31 | int stats_yMax; 32 | int stats_yMin; 33 | 34 | ImTextureID texture_id; 35 | 36 | SimVideo(int width, int height, int rotate); 37 | ~SimVideo(); 38 | void UpdateTexture(); 39 | void CleanUp(); 40 | void StartFrame(); 41 | void Clock(bool hblank, bool vblank, uint32_t colour); 42 | int Initialise(const char* windowTitle); 43 | }; 44 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/vinc/gtkwave/fst_config.h: -------------------------------------------------------------------------------- 1 | /* This file specifically for FST usage */ 2 | /* config.h. Generated from config.h.in by configure. */ 3 | /* config.h.in. Generated from configure.ac by autoheader. */ 4 | 5 | /* Define to 1 if you have and it should be used (not on Ultrix). */ 6 | #if !defined(__MINGW32__) 7 | # define HAVE_ALLOCA_H 1 8 | #endif 9 | 10 | /* Define to 1 if fseeko (and presumably ftello) exists and is declared. */ 11 | #define HAVE_FSEEKO 1 12 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/vinc/verilated_config.h: -------------------------------------------------------------------------------- 1 | // -*- mode: C++; c-file-style: "cc-mode" -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can 5 | // redistribute it and/or modify it under the terms of either the GNU 6 | // Lesser General Public License Version 3 or the Perl Artistic License. 7 | // Version 2.0. 8 | // 9 | // Verilator is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | //************************************************************************* 15 | /// 16 | /// \file 17 | /// \brief Verilator: Auto version information include for all Verilated C files 18 | /// 19 | /// Code available from: https://verilator.org 20 | /// 21 | //************************************************************************* 22 | 23 | 24 | ///**** Product and Version name 25 | 26 | // Autoconf substitutes this with the strings from AC_INIT. 27 | #define VERILATOR_PRODUCT "Verilator" 28 | #define VERILATOR_VERSION "4.028 2020-02-06" 29 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/sim/vinc/verilated_config.h.in: -------------------------------------------------------------------------------- 1 | // -*- mode: C++; c-file-style: "cc-mode" -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can 5 | // redistribute it and/or modify it under the terms of either the GNU 6 | // Lesser General Public License Version 3 or the Perl Artistic License. 7 | // Version 2.0. 8 | // 9 | // Verilator is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | //************************************************************************* 15 | /// 16 | /// \file 17 | /// \brief Verilator: Auto version information include for all Verilated C files 18 | /// 19 | /// Code available from: https://verilator.org 20 | /// 21 | //************************************************************************* 22 | 23 | 24 | ///**** Product and Version name 25 | 26 | // Autoconf substitutes this with the strings from AC_INIT. 27 | #define VERILATOR_PRODUCT "@PACKAGE_NAME@" 28 | #define VERILATOR_VERSION "@PACKAGE_VERSION@" 29 | -------------------------------------------------------------------------------- /basic/cassette_overlay/verilator/verilate.sh: -------------------------------------------------------------------------------- 1 | verilator -cc -exe --public --compiler msvc --converge-limit 2000 -Wno-WIDTH -Wno-IMPLICIT -Wno-MODDUP -Wno-UNSIGNED -Wno-CASEINCOMPLETE -Wno-CASEX -Wno-SYMRSVDWORD -Wno-COMBDLY -Wno-INITIALDLY -Wno-BLKANDNBLK -Wno-UNOPTFLAT -Wno-SELRANGE -Wno-CMPCONST -Wno-CASEOVERLAP -Wno-PINMISSING --top-module top lesson3_tb.v ../rtl/vga.v ../rtl/bram.sv ../rtl/soc.v \ 2 | ../rtl/tv80/tv80_core.v \ 3 | ../rtl/tv80/tv80_alu.v \ 4 | ../rtl/tv80/tv80_mcode.v \ 5 | ../rtl/tv80/tv80_reg.v \ 6 | ../rtl/tv80/tv80n.v \ 7 | ../rtl/tv80/tv80s.v 8 | -------------------------------------------------------------------------------- /basic/lesson1/Lesson1.sdc: -------------------------------------------------------------------------------- 1 | derive_pll_clocks 2 | derive_clock_uncertainty 3 | 4 | # core specific constraints 5 | -------------------------------------------------------------------------------- /basic/lesson1/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE Lesson1.sv 2 | set_global_assignment -name QIP_FILE sys/sys.qip 3 | set_global_assignment -name VERILOG_FILE rtl/vga.v 4 | set_global_assignment -name SDC_FILE Lesson1.sdc -------------------------------------------------------------------------------- /basic/lesson1/lesson1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson1/lesson1.png -------------------------------------------------------------------------------- /basic/lesson1/lesson1_grey.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson1/lesson1_grey.png -------------------------------------------------------------------------------- /basic/lesson1/lesson1_red.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson1/lesson1_red.png -------------------------------------------------------------------------------- /basic/lesson1/lesson1_white.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson1/lesson1_white.png -------------------------------------------------------------------------------- /basic/lesson1/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson1/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson1/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /basic/lesson1/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /basic/lesson1/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson1/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson1/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /basic/lesson1/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /basic/lesson1/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/lesson2/Image Examples/MiSTer160.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson2/Image Examples/MiSTer160.jpg -------------------------------------------------------------------------------- /basic/lesson2/Image Examples/MiSTer640.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson2/Image Examples/MiSTer640.jpg -------------------------------------------------------------------------------- /basic/lesson2/Image Examples/bird.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson2/Image Examples/bird.bin -------------------------------------------------------------------------------- /basic/lesson2/Image Examples/image.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson2/Image Examples/image.png -------------------------------------------------------------------------------- /basic/lesson2/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE Lesson2.sv 2 | set_global_assignment -name QIP_FILE sys/sys.qip 3 | set_global_assignment -name QIP_FILE rtl/image.qip 4 | set_global_assignment -name VERILOG_FILE rtl/vga.v 5 | set_global_assignment -name VERILOG_FILE rtl/soc.v 6 | -------------------------------------------------------------------------------- /basic/lesson2/img2hex.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | avconv -vcodec png -i image.png -vcodec rawvideo -f rawvideo -pix_fmt rgb8 image.raw 3 | srec_cat image.raw -binary -o image.hex -intel 4 | 5 | -------------------------------------------------------------------------------- /basic/lesson2/lesson2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson2/lesson2.png -------------------------------------------------------------------------------- /basic/lesson2/rtl/image.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson2/rtl/image.bin -------------------------------------------------------------------------------- /basic/lesson2/rtl/image.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "image.v"] 5 | -------------------------------------------------------------------------------- /basic/lesson2/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson2/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson2/solution/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE Lesson2.sv 2 | set_global_assignment -name QIP_FILE sys/sys.qip 3 | set_global_assignment -name QIP_FILE rtl/image.qip 4 | set_global_assignment -name VERILOG_FILE rtl/vga.v 5 | set_global_assignment -name VERILOG_FILE rtl/soc.v 6 | set_global_assignment -name VHDL_FILE rtl/dpram.vhd -------------------------------------------------------------------------------- /basic/lesson2/solution/rtl/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input pixel_clock, 6 | input ioctl_wr, 7 | input [13:0] ioctl_addr, 8 | input [7:0] ioctl_data, 9 | output reg progress, 10 | output VGA_HS, 11 | output VGA_VS, 12 | output [7:0] VGA_R, 13 | output [7:0] VGA_G, 14 | output [7:0] VGA_B, 15 | output VGA_DE 16 | ); 17 | 18 | 19 | 20 | vga vga ( 21 | .pclk (pixel_clock), 22 | 23 | .cpu_clk ( pixel_clock ), 24 | .ioctl_wr ( ioctl_wr ), 25 | .ioctl_addr ( ioctl_addr ), 26 | .ioctl_data ( ioctl_data ), 27 | 28 | .hs (VGA_HS), 29 | .vs (VGA_VS), 30 | .r (VGA_R), 31 | .g (VGA_G), 32 | .b (VGA_B), 33 | .VGA_DE(VGA_DE) 34 | ); 35 | 36 | 37 | 38 | 39 | 40 | endmodule -------------------------------------------------------------------------------- /basic/lesson2/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /basic/lesson2/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /basic/lesson2/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson2/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson2/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /basic/lesson2/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /basic/lesson2/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/lesson2/verilator/sim.vcxproj.user: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | -------------------------------------------------------------------------------- /basic/lesson2/verilator/verilate.sh: -------------------------------------------------------------------------------- 1 | verilator -cc -exe --public --compiler msvc --converge-limit 2000 -Wno-WIDTH -Wno-IMPLICIT -Wno-MODDUP -Wno-UNSIGNED -Wno-CASEINCOMPLETE -Wno-CASEX -Wno-SYMRSVDWORD -Wno-COMBDLY -Wno-INITIALDLY -Wno-BLKANDNBLK -Wno-UNOPTFLAT -Wno-SELRANGE -Wno-CMPCONST -Wno-CASEOVERLAP -Wno-PINMISSING --top-module top lesson2_tb.v ../solution/rtl/vga.v ram/bram.sv ../solution/rtl/soc.v 2 | -------------------------------------------------------------------------------- /basic/lesson2/verilator/vinc/gtkwave/fst_config.h: -------------------------------------------------------------------------------- 1 | /* This file specifically for FST usage */ 2 | /* config.h. Generated from config.h.in by configure. */ 3 | /* config.h.in. Generated from configure.ac by autoheader. */ 4 | 5 | /* Define to 1 if you have and it should be used (not on Ultrix). */ 6 | #if !defined(__MINGW32__) 7 | # define HAVE_ALLOCA_H 1 8 | #endif 9 | 10 | /* Define to 1 if fseeko (and presumably ftello) exists and is declared. */ 11 | #define HAVE_FSEEKO 1 12 | -------------------------------------------------------------------------------- /basic/lesson2/verilator/vinc/verilated_config.h: -------------------------------------------------------------------------------- 1 | // -*- mode: C++; c-file-style: "cc-mode" -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can 5 | // redistribute it and/or modify it under the terms of either the GNU 6 | // Lesser General Public License Version 3 or the Perl Artistic License. 7 | // Version 2.0. 8 | // 9 | // Verilator is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | //************************************************************************* 15 | /// 16 | /// \file 17 | /// \brief Verilator: Auto version information include for all Verilated C files 18 | /// 19 | /// Code available from: https://verilator.org 20 | /// 21 | //************************************************************************* 22 | 23 | 24 | ///**** Product and Version name 25 | 26 | // Autoconf substitutes this with the strings from AC_INIT. 27 | #define VERILATOR_PRODUCT "Verilator" 28 | #define VERILATOR_VERSION "4.028 2020-02-06" 29 | -------------------------------------------------------------------------------- /basic/lesson2/verilator/vinc/verilated_config.h.in: -------------------------------------------------------------------------------- 1 | // -*- mode: C++; c-file-style: "cc-mode" -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can 5 | // redistribute it and/or modify it under the terms of either the GNU 6 | // Lesser General Public License Version 3 or the Perl Artistic License. 7 | // Version 2.0. 8 | // 9 | // Verilator is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | //************************************************************************* 15 | /// 16 | /// \file 17 | /// \brief Verilator: Auto version information include for all Verilated C files 18 | /// 19 | /// Code available from: https://verilator.org 20 | /// 21 | //************************************************************************* 22 | 23 | 24 | ///**** Product and Version name 25 | 26 | // Autoconf substitutes this with the strings from AC_INIT. 27 | #define VERILATOR_PRODUCT "@PACKAGE_NAME@" 28 | #define VERILATOR_VERSION "@PACKAGE_VERSION@" 29 | -------------------------------------------------------------------------------- /basic/lesson3/Makefile: -------------------------------------------------------------------------------- 1 | SDCC=sdcc 2 | CPU=z80 3 | CODE=boot_rom 4 | 5 | all: $(CODE).hex 6 | 7 | %.ihx: %.c 8 | $(SDCC) -m$(CPU) $< 9 | 10 | %.hex: %.ihx 11 | mv $< $@ 12 | 13 | %.bin: %.hex 14 | srec_cat $< -intel -o $@ -binary 15 | 16 | disasm: $(CODE).bin 17 | z80dasm -a -t -g 0 $< 18 | 19 | clean: 20 | rm -rf *~ *.asm *.ihx *.lk *.lst *.map *.noi *.rel *.sym 21 | -------------------------------------------------------------------------------- /basic/lesson3/README.md: -------------------------------------------------------------------------------- 1 | Lesson 3: Z80 CPU and RAM 2 | -------------------------- 3 | 4 | 5 | [![Lesson 3 Video](http://img.youtube.com/vi/K5M7aqQiXSI/0.jpg)](https://www.youtube.com/watch?v=K5M7aqQiXSI "Lesson 2 Video") 6 | 7 | 8 | # Step one build existing code 9 | 10 | Load this project into quartus and build it. The RBF will be in the output_files folder, copy it to your MiSTer and see if you can run it. 11 | 12 | ![](lesson3.png) 13 | 14 | # Step two run simulation in linux, mac or windows 15 | 16 | [Jimmy Stone's Verilator Template](https://github.com/JimmyStones/Verilator_Template) 17 | -------------------------------------------------------------------------------- /basic/lesson3/boot_rom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "boot_rom.v"] 5 | -------------------------------------------------------------------------------- /basic/lesson3/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE Lesson3.sv 2 | set_global_assignment -name QIP_FILE rtl/T80/t80.qip 3 | set_global_assignment -name QIP_FILE rtl/tv80/TV80.qip 4 | set_global_assignment -name CDF_FILE jtag.cdf 5 | set_global_assignment -name QIP_FILE sys/sys.qip 6 | set_global_assignment -name VERILOG_FILE rtl/vga.v 7 | set_global_assignment -name VERILOG_FILE rtl/soc.v 8 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/bram.sv -------------------------------------------------------------------------------- /basic/lesson3/lesson3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson3/lesson3.png -------------------------------------------------------------------------------- /basic/lesson3/ram4k.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram4k.v"] 5 | -------------------------------------------------------------------------------- /basic/lesson3/rtl/T80/t80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] 7 | -------------------------------------------------------------------------------- /basic/lesson3/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson3/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson3/rtl/tv80/TV80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_core.v"] 2 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_alu.v"] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_mcode.v"] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_reg.v"] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80n.v"] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80s.v"] -------------------------------------------------------------------------------- /basic/lesson3/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /basic/lesson3/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /basic/lesson3/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson3/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson3/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /basic/lesson3/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /basic/lesson3/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/.gitignore: -------------------------------------------------------------------------------- 1 | /.vs 2 | /obj_dir 3 | /x64 -------------------------------------------------------------------------------- /basic/lesson3/verilator/imgui.ini: -------------------------------------------------------------------------------- 1 | [Window][Debug##Default] 2 | Pos=60,60 3 | Size=400,400 4 | Collapsed=0 5 | 6 | [Window][Debug Log] 7 | Pos=19,8 8 | Size=520,600 9 | Collapsed=0 10 | 11 | [Window][Virtual Dev Board v1.0] 12 | Pos=580,10 13 | Size=1000,1000 14 | Collapsed=0 15 | 16 | [Window][RAM Editor] 17 | Pos=8,403 18 | Size=544,317 19 | Collapsed=0 20 | 21 | [Window][ROM Editor] 22 | Pos=1351,695 23 | Size=669,407 24 | Collapsed=0 25 | 26 | [Window][VRAM Editor] 27 | Pos=115,771 28 | Size=560,393 29 | Collapsed=0 30 | 31 | [Window][CPU Registers] 32 | Pos=38,206 33 | Size=269,174 34 | Collapsed=0 35 | 36 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim.vcxproj.user: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | false 5 | 6 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/sim_audio.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include "sim_clock.h" 5 | 6 | struct SimAudio { 7 | public: 8 | 9 | SimClock clock; 10 | 11 | static const unsigned short debug_max_samples = 600; 12 | float debug_positions[debug_max_samples]; 13 | float debug_wave_l[debug_max_samples]; 14 | float debug_wave_r[debug_max_samples]; 15 | int debug_pos; 16 | 17 | SimAudio(int systemClockFrequency, bool saveToFile); 18 | ~SimAudio(); 19 | void Clock(signed short left, signed short right); 20 | void CollectDebug(signed short left, signed short right); 21 | void Initialise(); 22 | void CleanUp(); 23 | }; 24 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/sim_clock.cpp: -------------------------------------------------------------------------------- 1 | #include "sim_clock.h" 2 | #include 3 | 4 | SimClock::SimClock() { 5 | ratio = 1; 6 | count = 0; 7 | clk = false; 8 | old = false; 9 | } 10 | 11 | SimClock::SimClock(int r) { 12 | ratio = r; 13 | count = 0; 14 | clk = false; 15 | old = false; 16 | } 17 | 18 | 19 | SimClock::~SimClock() { 20 | } 21 | 22 | void SimClock::Tick() { 23 | old = clk; 24 | count++; 25 | if (count > ratio) { 26 | count = 0; 27 | } 28 | clk = (count == 0); 29 | } 30 | 31 | void SimClock::Reset() { 32 | count = 0; 33 | clk = false; 34 | old = false; 35 | } 36 | 37 | bool SimClock::IsRising() { 38 | return clk && !old; 39 | } 40 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/sim_clock.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | class SimClock 4 | { 5 | 6 | public: 7 | bool clk, old; 8 | 9 | SimClock(); 10 | SimClock(int r); 11 | ~SimClock(); 12 | void Tick(); 13 | void Reset(); 14 | bool IsRising(); 15 | 16 | private: 17 | int ratio, count; 18 | }; -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/sim_console.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "imgui.h" 3 | 4 | struct DebugConsole { 5 | public: 6 | void AddLog(const char* fmt, ...) IM_FMTARGS(2); 7 | DebugConsole(); 8 | ~DebugConsole(); 9 | void ClearLog(); 10 | void Draw(const char* title, bool* p_open, ImVec2 size); 11 | void ExecCommand(const char* command_line); 12 | int TextEditCallback(ImGuiInputTextCallbackData* data); 13 | }; 14 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/sim_video.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #ifndef _MSC_VER 5 | #include "imgui_impl_sdl.h" 6 | #include "imgui_impl_opengl2.h" 7 | #else 8 | #define WIN32 9 | #include "imgui_impl_win32.h" 10 | #include "imgui_impl_dx11.h" 11 | #include 12 | #include 13 | #endif 14 | 15 | struct SimVideo { 16 | public: 17 | 18 | int output_width; 19 | int output_height; 20 | int output_rotate; 21 | bool output_vflip; 22 | 23 | int count_pixel; 24 | int count_line; 25 | int count_frame; 26 | 27 | float stats_fps; 28 | float stats_frameTime; 29 | int stats_xMax; 30 | int stats_xMin; 31 | int stats_yMax; 32 | int stats_yMin; 33 | 34 | ImTextureID texture_id; 35 | 36 | SimVideo(int width, int height, int rotate); 37 | ~SimVideo(); 38 | void UpdateTexture(); 39 | void CleanUp(); 40 | void StartFrame(); 41 | void Clock(bool hblank, bool vblank, bool hsync, bool vsync, uint32_t colour); 42 | int Initialise(const char* windowTitle); 43 | }; 44 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/vinc/gtkwave/fst_config.h: -------------------------------------------------------------------------------- 1 | /* This file specifically for FST usage */ 2 | /* config.h. Generated from config.h.in by configure. */ 3 | /* config.h.in. Generated from configure.ac by autoheader. */ 4 | 5 | /* Define to 1 if you have and it should be used (not on Ultrix). */ 6 | #if !defined(__MINGW32__) && !defined(__FreeBSD__) 7 | # define HAVE_ALLOCA_H 1 8 | #endif 9 | 10 | /* Define to 1 if fseeko (and presumably ftello) exists and is declared. */ 11 | #define HAVE_FSEEKO 1 12 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/vinc/verilated.v: -------------------------------------------------------------------------------- 1 | //************************************************************************* 2 | // 3 | // Code available from: https://verilator.org 4 | // 5 | // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can 6 | // redistribute it and/or modify it under the terms of either the GNU 7 | // Lesser General Public License Version 3 or the Perl Artistic License 8 | // Version 2.0. 9 | // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 10 | // 11 | //========================================================================= 12 | // 13 | // DESCRIPTION: Verilator: Include in verilog files to hide verilator defines 14 | 15 | `ifdef _VERILATED_V_ `else 16 | `define _VERILATED_V_ 1 17 | 18 | // Hide verilator pragmas from other tools 19 | `ifdef VERILATOR `else 20 | `define coverage_block_off 21 | `endif 22 | 23 | // Hide file descriptor difference - deprecated - for older versions 24 | `define verilator_file_descriptor integer 25 | 26 | `endif // guard 27 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/vinc/verilated_config.h: -------------------------------------------------------------------------------- 1 | // -*- mode: C++; c-file-style: "cc-mode" -*- 2 | //************************************************************************* 3 | // 4 | // Code available from: https://verilator.org 5 | // 6 | // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can 7 | // redistribute it and/or modify it under the terms of either the GNU 8 | // Lesser General Public License Version 3 or the Perl Artistic License 9 | // Version 2.0. 10 | // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 11 | // 12 | //************************************************************************* 13 | /// 14 | /// \file 15 | /// \brief Verilator program version information header 16 | /// 17 | //************************************************************************* 18 | 19 | /// Verilator product name, e.g. "Verilator" 20 | // Autoconf substitutes this with the strings from AC_INIT. 21 | #define VERILATOR_PRODUCT "Verilator" 22 | 23 | /// Verilator version name, e.g. "1.000 2000-01-01" 24 | // Autoconf substitutes this with the strings from AC_INIT. 25 | #define VERILATOR_VERSION "4.204 2021-06-12" 26 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/sim/vinc/verilated_config.h.in: -------------------------------------------------------------------------------- 1 | // -*- mode: C++; c-file-style: "cc-mode" -*- 2 | //************************************************************************* 3 | // 4 | // Code available from: https://verilator.org 5 | // 6 | // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can 7 | // redistribute it and/or modify it under the terms of either the GNU 8 | // Lesser General Public License Version 3 or the Perl Artistic License 9 | // Version 2.0. 10 | // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 11 | // 12 | //************************************************************************* 13 | /// 14 | /// \file 15 | /// \brief Verilator program version information header 16 | /// 17 | //************************************************************************* 18 | 19 | /// Verilator product name, e.g. "Verilator" 20 | // Autoconf substitutes this with the strings from AC_INIT. 21 | #define VERILATOR_PRODUCT "@PACKAGE_NAME@" 22 | 23 | /// Verilator version name, e.g. "1.000 2000-01-01" 24 | // Autoconf substitutes this with the strings from AC_INIT. 25 | #define VERILATOR_VERSION "@PACKAGE_VERSION@" 26 | -------------------------------------------------------------------------------- /basic/lesson3/verilator/verilate.sh: -------------------------------------------------------------------------------- 1 | verilator -cc -exe --public --compiler msvc --converge-limit 2000 -Wno-WIDTH -Wno-IMPLICIT -Wno-MODDUP -Wno-UNSIGNED -Wno-CASEINCOMPLETE -Wno-CASEX -Wno-SYMRSVDWORD -Wno-COMBDLY -Wno-INITIALDLY -Wno-BLKANDNBLK -Wno-UNOPTFLAT -Wno-SELRANGE -Wno-CMPCONST -Wno-CASEOVERLAP -Wno-PINMISSING --top-module top \ 2 | lesson3_tb.v \ 3 | ../rtl/vga.v \ 4 | ../rtl/bram.sv \ 5 | ../rtl/soc.v \ 6 | ../rtl/tv80/tv80_core.v \ 7 | ../rtl/tv80/tv80_alu.v \ 8 | ../rtl/tv80/tv80_mcode.v \ 9 | ../rtl/tv80/tv80_reg.v \ 10 | ../rtl/tv80/tv80n.v \ 11 | ../rtl/tv80/tv80s.v 12 | -------------------------------------------------------------------------------- /basic/lesson3_68k/README.md: -------------------------------------------------------------------------------- 1 | # demo68k 2 | MiSTer use of 68000 cpu core and targetting C code. 3 | 4 | If you wish to build your own rom you will need a compiler for the Motorola 68000 CPU. 5 | There is a sample batch file included for building on windows although the steps should be the same on Linux. 6 | 7 | A linker script .ld file allows gcc to place the reset vector table, rom, and ram locations. If you change the 8 | addressing you will have to update it. 9 | 10 | Be aware that creating the Intel hex file requires the addresses are in words and not byte offsets. Quartus 17 will not load 11 | 16 bit hex files correctly unless there is only one 16 bit word per line in the hex file. 12 | -------------------------------------------------------------------------------- /basic/lesson3_68k/clean.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | del /s *.bak 3 | del /s *.orig 4 | del /s *.rej 5 | del /s *~ 6 | rmdir /s /q db 7 | rmdir /s /q incremental_db 8 | rmdir /s /q output_files 9 | rmdir /s /q simulation 10 | rmdir /s /q greybox_tmp 11 | rmdir /s /q hc_output 12 | rmdir /s /q .qsys_edit 13 | rmdir /s /q hps_isw_handoff 14 | rmdir /s /q sys\.qsys_edit 15 | rmdir /s /q sys\vip 16 | for /d %%i in (sys\*_sim) do rmdir /s /q "%%i" 17 | for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i" 18 | del build_id.v 19 | del c5_pin_model_dump.txt 20 | del PLLJ_PLLSPE_INFO.txt 21 | del /s *.qws 22 | del /s *.ppf 23 | del /s *.ddb 24 | del /s *.csv 25 | del /s *.cmp 26 | del /s *.sip 27 | del /s *.spd 28 | del /s *.bsf 29 | del /s *.f 30 | del /s *.sopcinfo 31 | del /s *.xml 32 | del *.cdf 33 | del *.rpt 34 | del /s new_rtl_netlist 35 | del /s old_rtl_netlist 36 | pause 37 | -------------------------------------------------------------------------------- /basic/lesson3_68k/demo68k.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson3_68k/demo68k.jpg -------------------------------------------------------------------------------- /basic/lesson3_68k/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE demo68k.sv 2 | set_global_assignment -name SDC_FILE demo68k.sdc 3 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_timing.v 4 | set_global_assignment -name VERILOG_FILE rtl/uaddrPla.v 5 | set_global_assignment -name VERILOG_FILE rtl/rom.v 6 | set_global_assignment -name VERILOG_FILE rtl/ram.v 7 | set_global_assignment -name VERILOG_FILE rtl/fx68kAlu.v 8 | set_global_assignment -name VERILOG_FILE rtl/fx68k.v 9 | set_global_assignment -name QIP_FILE rtl/vram.qip 10 | set_global_assignment -name QIP_FILE rtl/ram8kx16.qip 11 | set_global_assignment -name QIP_FILE rtl/rom8kx16.qip 12 | -------------------------------------------------------------------------------- /basic/lesson3_68k/releases/_put_rbf_here_: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson3_68k/releases/_put_rbf_here_ -------------------------------------------------------------------------------- /basic/lesson3_68k/rom/68k.ld: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | rom (rx) : ORIGIN = 0x000000, LENGTH = 0x02000 4 | ram (rwx) : ORIGIN = 0x100000, LENGTH = 0x02000 5 | vram (rw) : ORIGIN = 0x800000, LENGTH = 0x25800 6 | } 7 | 8 | STACK_SIZE = 0x100; 9 | 10 | /* Section Definitions */ 11 | SECTIONS 12 | { 13 | .text : 14 | { 15 | KEEP(*(.vectors .vectors.*)) 16 | _stext = .; 17 | *(.text.*) 18 | *(.rodata.*) 19 | _etext = .; 20 | } > rom 21 | 22 | .bss (NOLOAD) : 23 | { 24 | _sbss = . ; 25 | *(.bss .bss.*) 26 | *(COMMON) 27 | _ebss = . ; 28 | } > ram 29 | 30 | .data : 31 | { 32 | _sdata = .; 33 | *(.data*); 34 | _edata = .; 35 | } > ram AT >rom 36 | 37 | /* stack section */ 38 | .stack (NOLOAD): 39 | { 40 | _sstack = .; 41 | . = ALIGN(8); 42 | . = . + STACK_SIZE; 43 | . = ALIGN(8); 44 | _estack = .; 45 | } > ram 46 | 47 | .dummy_vram : 48 | { 49 | _vram = .; 50 | KEEP(*(.dummy_vram)) 51 | } > vram 52 | 53 | _end = . ; 54 | } -------------------------------------------------------------------------------- /basic/lesson3_68k/rom/go.bat: -------------------------------------------------------------------------------- 1 | ; toolchain available 2 | ; https://gnutoolchains.com/m68k-elf/ 3 | 4 | m68k-elf-gcc -Wall -nostdlib -nodefaultlibs -fomit-frame-pointer -m68000 -c test.c 5 | m68k-elf-ld -T 68k.ld test.o 6 | m68k-elf-objcopy -I coff-m68k -O binary a.out test.bin 7 | 8 | ; disassembly can be generated using 9 | ; m68k-elf-objdump -d a.out -------------------------------------------------------------------------------- /basic/lesson3_68k/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson3_68k/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson3_68k/rtl/ram8kx16.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram8kx16.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram8kx16_inst.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram8kx16_bb.v"] 7 | -------------------------------------------------------------------------------- /basic/lesson3_68k/rtl/rom8kx16.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom8kx16.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom8kx16_bb.v"] 6 | -------------------------------------------------------------------------------- /basic/lesson3_68k/rtl/vram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "vram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vram_inst.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vram_bb.v"] 7 | -------------------------------------------------------------------------------- /basic/lesson3_68k/rtl/vram_inst.v: -------------------------------------------------------------------------------- 1 | vram vram_inst ( 2 | .address_a ( address_a_sig ), 3 | .address_b ( address_b_sig ), 4 | .data_a ( data_a_sig ), 5 | .data_b ( data_b_sig ), 6 | .inclock ( inclock_sig ), 7 | .outclock ( outclock_sig ), 8 | .wren_a ( wren_a_sig ), 9 | .wren_b ( wren_b_sig ), 10 | .q_a ( q_a_sig ), 11 | .q_b ( q_b_sig ) 12 | ); 13 | -------------------------------------------------------------------------------- /basic/lesson3_68k/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /basic/lesson3_68k/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /basic/lesson3_68k/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson3_68k/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson3_68k/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /basic/lesson3_68k/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /basic/lesson3_68k/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/lesson4/Lesson4_description.txt: -------------------------------------------------------------------------------- 1 | Created on:Thursday, January 10, 2019 2 | Based on:Lesson3 3 | -------------------------------------------------------------------------------- /basic/lesson4/Makefile: -------------------------------------------------------------------------------- 1 | SDCC=sdcc 2 | CPU=z80 3 | CODE=boot_rom 4 | 5 | all: $(CODE).hex 6 | 7 | %.ihx: %.c 8 | $(SDCC) -m$(CPU) $< 9 | 10 | %.hex: %.ihx 11 | mv $< $@ 12 | 13 | %.bin: %.hex 14 | srec_cat $< -intel -o $@ -binary 15 | 16 | disasm: $(CODE).bin 17 | z80dasm -a -t -g 0 $< 18 | 19 | clean: 20 | rm -rf *~ *.asm *.ihx *.lk *.lst *.map *.noi *.rel *.sym 21 | -------------------------------------------------------------------------------- /basic/lesson4/T80/t80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] 7 | -------------------------------------------------------------------------------- /basic/lesson4/boot_rom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "boot_rom.v"] 5 | -------------------------------------------------------------------------------- /basic/lesson4/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson4/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson4/sys/scanlines.v: -------------------------------------------------------------------------------- 1 | module scanlines #(parameter v2=0) 2 | ( 3 | input clk, 4 | 5 | input [1:0] scanlines, 6 | input [23:0] din, 7 | output reg [23:0] dout, 8 | input hs,vs 9 | ); 10 | 11 | reg [1:0] scanline; 12 | always @(posedge clk) begin 13 | reg old_hs, old_vs; 14 | 15 | old_hs <= hs; 16 | old_vs <= vs; 17 | 18 | if(old_hs && ~hs) begin 19 | if(v2) begin 20 | scanline <= scanline + 1'd1; 21 | if (scanline == scanlines) scanline <= 0; 22 | end 23 | else scanline <= scanline ^ scanlines; 24 | end 25 | if(old_vs && ~vs) scanline <= 0; 26 | end 27 | 28 | wire [7:0] r,g,b; 29 | assign {r,g,b} = din; 30 | 31 | always @(*) begin 32 | case(scanline) 33 | 1: // reduce 25% = 1/2 + 1/4 34 | dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, 35 | {1'b0, g[7:1]} + {2'b00, g[7:2]}, 36 | {1'b0, b[7:1]} + {2'b00, b[7:2]}}; 37 | 38 | 2: // reduce 50% = 1/2 39 | dout = {{1'b0, r[7:1]}, 40 | {1'b0, g[7:1]}, 41 | {1'b0, b[7:1]}}; 42 | 43 | 3: // reduce 75% = 1/4 44 | dout = {{2'b00, r[7:2]}, 45 | {2'b00, g[7:2]}, 46 | {2'b00, b[7:2]}}; 47 | 48 | default: dout = {r,g,b}; 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /basic/lesson4/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/lesson6/Lesson6.rom: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson6/Lesson6.rom -------------------------------------------------------------------------------- /basic/lesson6/Lesson6_description.txt: -------------------------------------------------------------------------------- 1 | Created on:Saturday, January 12, 2019 2 | Based on:Lesson4 3 | -------------------------------------------------------------------------------- /basic/lesson6/Makefile: -------------------------------------------------------------------------------- 1 | SDCC=sdcc 2 | CPU=z80 3 | CODE=boot_rom 4 | TTY=/dev/ttyUSB0 5 | OBJ=$(CODE).rel irqvec.rel 6 | ROM=z80_soc.rom 7 | 8 | all: $(ROM) 9 | 10 | bin2c: bin2c.c 11 | 12 | irqvec.rel: irqvec.s 13 | sdasz80 -o $@ $< 14 | 15 | %.rel: %.c 16 | $(SDCC) -m$(CPU) -c $< 17 | 18 | $(CODE).ihx: $(OBJ) 19 | $(SDCC) -m$(CPU) $(OBJ) 20 | 21 | %.hex: %.ihx 22 | cp $< $@ 23 | 24 | %.bin: %.hex 25 | srec_cat -multiple $< -intel -o $@ -binary 26 | 27 | $(ROM): $(CODE).bin 28 | cp $< $@ 29 | 30 | disasm: $(CODE).bin 31 | z80dasm -a -t -g 0 $< 32 | 33 | clean: 34 | rm -rf *~ *.asm *.ihx *.lk *.lst *.map *.noi *.rel *.sym *.bin 35 | 36 | run: $(ROM) 37 | stty -F $(TTY) speed 115200 raw -echo 38 | timeout 1s cp $(TTY) /dev/null || /bin/true 39 | echo "x $(ROM) `stat -c%s $<`" > $(TTY) 40 | sx $< <$(TTY) >$(TTY) 41 | echo "r" > $(TTY) 42 | -------------------------------------------------------------------------------- /basic/lesson6/T80/t80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] 7 | -------------------------------------------------------------------------------- /basic/lesson6/irqvec.s: -------------------------------------------------------------------------------- 1 | ;; This is a nasty hack. This overwrites the reti at 0x38 which has already 2 | ;; been set by crt0.s with a jump into our interrupt routine. This results 3 | ;; in two contradicting entries in the hex file and the converter has to deal 4 | ;; with that. srec_cat can be told to accept it. Quartus accepts it by default 5 | .globl _isr 6 | .area VECTOR (ABS) 7 | 8 | .org 0x38 9 | jp _isr 10 | -------------------------------------------------------------------------------- /basic/lesson6/lesson6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson6/lesson6.png -------------------------------------------------------------------------------- /basic/lesson6/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson6/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson6/sys/scanlines.v: -------------------------------------------------------------------------------- 1 | module scanlines #(parameter v2=0) 2 | ( 3 | input clk, 4 | 5 | input [1:0] scanlines, 6 | input [23:0] din, 7 | output reg [23:0] dout, 8 | input hs,vs 9 | ); 10 | 11 | reg [1:0] scanline; 12 | always @(posedge clk) begin 13 | reg old_hs, old_vs; 14 | 15 | old_hs <= hs; 16 | old_vs <= vs; 17 | 18 | if(old_hs && ~hs) begin 19 | if(v2) begin 20 | scanline <= scanline + 1'd1; 21 | if (scanline == scanlines) scanline <= 0; 22 | end 23 | else scanline <= scanline ^ scanlines; 24 | end 25 | if(old_vs && ~vs) scanline <= 0; 26 | end 27 | 28 | wire [7:0] r,g,b; 29 | assign {r,g,b} = din; 30 | 31 | always @(*) begin 32 | case(scanline) 33 | 1: // reduce 25% = 1/2 + 1/4 34 | dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, 35 | {1'b0, g[7:1]} + {2'b00, g[7:2]}, 36 | {1'b0, b[7:1]} + {2'b00, b[7:2]}}; 37 | 38 | 2: // reduce 50% = 1/2 39 | dout = {{1'b0, r[7:1]}, 40 | {1'b0, g[7:1]}, 41 | {1'b0, b[7:1]}}; 42 | 43 | 3: // reduce 75% = 1/4 44 | dout = {{2'b00, r[7:2]}, 45 | {2'b00, g[7:2]}, 46 | {2'b00, b[7:2]}}; 47 | 48 | default: dout = {r,g,b}; 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /basic/lesson6/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/lesson8/Lesson8/Lesson8.rom: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson8/Lesson8/Lesson8.rom -------------------------------------------------------------------------------- /basic/lesson8/Lesson8/song.ym: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson8/Lesson8/song.ym -------------------------------------------------------------------------------- /basic/lesson8/Lesson8_description.txt: -------------------------------------------------------------------------------- 1 | Created on:Wednesday, January 16, 2019 2 | Based on:Lesson6 3 | -------------------------------------------------------------------------------- /basic/lesson8/Makefile: -------------------------------------------------------------------------------- 1 | SDCC=sdcc 2 | CPU=z80 3 | CODE=boot_rom 4 | TTY=/dev/ttyUSB0 5 | OBJ=$(CODE).rel irqvec.rel 6 | ROM=z80_soc.rom 7 | 8 | all: $(ROM) 9 | 10 | bin2c: bin2c.c 11 | 12 | irqvec.rel: irqvec.s 13 | sdasz80 -o $@ $< 14 | 15 | %.rel: %.c 16 | $(SDCC) -m$(CPU) -c $< 17 | 18 | $(CODE).ihx: $(OBJ) 19 | $(SDCC) -m$(CPU) $(OBJ) 20 | 21 | %.hex: %.ihx 22 | cp $< $@ 23 | 24 | %.bin: %.hex 25 | srec_cat -multiple $< -intel -o $@ -binary 26 | 27 | $(ROM): $(CODE).bin 28 | cp $< $@ 29 | 30 | disasm: $(CODE).bin 31 | z80dasm -a -t -g 0 $< 32 | 33 | clean: 34 | rm -rf *~ *.asm *.ihx *.lk *.lst *.map *.noi *.rel *.sym *.bin 35 | 36 | run: $(ROM) 37 | stty -F $(TTY) speed 115200 raw -echo 38 | timeout 1s cp $(TTY) /dev/null || /bin/true 39 | echo "x $(ROM) `stat -c%s $<`" > $(TTY) 40 | sx $< <$(TTY) >$(TTY) 41 | echo "r" > $(TTY) 42 | -------------------------------------------------------------------------------- /basic/lesson8/T80/t80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] 7 | -------------------------------------------------------------------------------- /basic/lesson8/diskio.h: -------------------------------------------------------------------------------- 1 | /*----------------------------------------------------------------------- 2 | / PFF - Low level disk interface modlue include file (C)ChaN, 2014 3 | /-----------------------------------------------------------------------*/ 4 | 5 | #ifndef _DISKIO_DEFINED 6 | #define _DISKIO_DEFINED 7 | 8 | #ifdef __cplusplus 9 | extern "C" { 10 | #endif 11 | 12 | #include "integer.h" 13 | 14 | 15 | /* Status of Disk Functions */ 16 | typedef BYTE DSTATUS; 17 | 18 | 19 | /* Results of Disk Functions */ 20 | typedef enum { 21 | RES_OK = 0, /* 0: Function succeeded */ 22 | RES_ERROR, /* 1: Disk error */ 23 | RES_NOTRDY, /* 2: Not ready */ 24 | RES_PARERR /* 3: Invalid parameter */ 25 | } DRESULT; 26 | 27 | 28 | /*---------------------------------------*/ 29 | /* Prototypes for disk control functions */ 30 | 31 | DSTATUS disk_initialize (void); 32 | DRESULT disk_readp (BYTE* buff, DWORD sector, UINT offser, UINT count); 33 | DRESULT disk_writep (const BYTE* buff, DWORD sc); 34 | 35 | #define STA_NOINIT 0x01 /* Drive not initialized */ 36 | #define STA_NODISK 0x02 /* No medium in the drive */ 37 | 38 | #ifdef __cplusplus 39 | } 40 | #endif 41 | 42 | #endif /* _DISKIO_DEFINED */ 43 | -------------------------------------------------------------------------------- /basic/lesson8/font.fnt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson8/font.fnt -------------------------------------------------------------------------------- /basic/lesson8/integer.h: -------------------------------------------------------------------------------- 1 | /*-------------------------------------------*/ 2 | /* Integer type definitions for FatFs module */ 3 | /*-------------------------------------------*/ 4 | 5 | #ifndef _FF_INTEGER 6 | #define _FF_INTEGER 7 | 8 | #ifdef _WIN32 /* FatFs development platform */ 9 | 10 | #include 11 | #include 12 | 13 | #else /* Embedded platform */ 14 | 15 | /* This type MUST be 8 bit */ 16 | typedef unsigned char BYTE; 17 | 18 | /* These types MUST be 16 bit */ 19 | typedef short SHORT; 20 | typedef unsigned short WORD; 21 | typedef unsigned short WCHAR; 22 | 23 | /* These types MUST be 16 bit or 32 bit */ 24 | typedef int INT; 25 | typedef unsigned int UINT; 26 | 27 | /* These types MUST be 32 bit */ 28 | typedef long LONG; 29 | typedef unsigned long DWORD; 30 | 31 | #endif 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /basic/lesson8/irqvec.s: -------------------------------------------------------------------------------- 1 | ;; This is a nasty hack. This overwrites the reti at 0x38 which has already 2 | ;; been set by crt0.s with a jump into our interrupt routine. This results 3 | ;; in two contradicting entries in the hex file and the converter has to deal 4 | ;; with that. srec_cat can be told to accept it. Quartus accepts it by default 5 | .globl _isr 6 | .area VECTOR (ABS) 7 | 8 | .org 0x38 9 | jp _isr 10 | -------------------------------------------------------------------------------- /basic/lesson8/lesson8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson8/lesson8.png -------------------------------------------------------------------------------- /basic/lesson8/song.ym: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson8/song.ym -------------------------------------------------------------------------------- /basic/lesson8/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson8/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson8/sys/scanlines.v: -------------------------------------------------------------------------------- 1 | module scanlines #(parameter v2=0) 2 | ( 3 | input clk, 4 | 5 | input [1:0] scanlines, 6 | input [23:0] din, 7 | output reg [23:0] dout, 8 | input hs,vs 9 | ); 10 | 11 | reg [1:0] scanline; 12 | always @(posedge clk) begin 13 | reg old_hs, old_vs; 14 | 15 | old_hs <= hs; 16 | old_vs <= vs; 17 | 18 | if(old_hs && ~hs) begin 19 | if(v2) begin 20 | scanline <= scanline + 1'd1; 21 | if (scanline == scanlines) scanline <= 0; 22 | end 23 | else scanline <= scanline ^ scanlines; 24 | end 25 | if(old_vs && ~vs) scanline <= 0; 26 | end 27 | 28 | wire [7:0] r,g,b; 29 | assign {r,g,b} = din; 30 | 31 | always @(*) begin 32 | case(scanline) 33 | 1: // reduce 25% = 1/2 + 1/4 34 | dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, 35 | {1'b0, g[7:1]} + {2'b00, g[7:2]}, 36 | {1'b0, b[7:1]} + {2'b00, b[7:2]}}; 37 | 38 | 2: // reduce 50% = 1/2 39 | dout = {{1'b0, r[7:1]}, 40 | {1'b0, g[7:1]}, 41 | {1'b0, b[7:1]}}; 42 | 43 | 3: // reduce 75% = 1/4 44 | dout = {{2'b00, r[7:2]}, 45 | {2'b00, g[7:2]}, 46 | {2'b00, b[7:2]}}; 47 | 48 | default: dout = {r,g,b}; 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /basic/lesson8/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /basic/lesson9/Lesson9/boot.rom: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson9/Lesson9/boot.rom -------------------------------------------------------------------------------- /basic/lesson9/Lesson9_description.txt: -------------------------------------------------------------------------------- 1 | Created on:Sunday, January 13, 2019 2 | Based on:Lesson6 3 | -------------------------------------------------------------------------------- /basic/lesson9/Makefile: -------------------------------------------------------------------------------- 1 | SDCC=sdcc 2 | CPU=z80 3 | CODE=boot_rom 4 | TTY=/dev/ttyUSB0 5 | OBJ=$(CODE).rel font.rel 6 | ROM=z80_soc.rom 7 | 8 | all: $(ROM) 9 | 10 | bin2c: bin2c.c 11 | 12 | font.part: font.fnt 13 | dd if=$< of=$@ bs=1 count=768 skip=256 14 | 15 | font.c: font.part bin2c 16 | ./bin2c font.part font.c "unsigned char font[]" 17 | 18 | %.rel: %.c 19 | $(SDCC) -m$(CPU) -c $< 20 | 21 | $(CODE).ihx: $(OBJ) 22 | $(SDCC) -m$(CPU) $(OBJ) 23 | 24 | %.hex: %.ihx 25 | cp $< $@ 26 | 27 | %.bin: %.hex 28 | srec_cat -multiple $< -intel -o $@ -binary 29 | 30 | $(ROM): $(CODE).bin 31 | cp $< $@ 32 | 33 | disasm: $(CODE).bin 34 | z80dasm -a -t -g 0 $< 35 | 36 | clean: 37 | rm -rf *~ *.asm *.ihx *.lk *.lst *.map *.noi *.rel *.sym *.bin bin2c *.part 38 | 39 | run: $(ROM) 40 | stty -F $(TTY) speed 115200 raw -echo 41 | timeout 1s cp $(TTY) /dev/null || /bin/true 42 | echo "x $< `stat -c%s $<`" > $(TTY) 43 | sx $< <$(TTY) >$(TTY) 44 | echo "r" > $(TTY) 45 | 46 | reset: 47 | echo "r" > $(TTY) 48 | -------------------------------------------------------------------------------- /basic/lesson9/T80/t80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] 7 | -------------------------------------------------------------------------------- /basic/lesson9/font.fnt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson9/font.fnt -------------------------------------------------------------------------------- /basic/lesson9/irqvec.s: -------------------------------------------------------------------------------- 1 | ;; This is a nasty hack. This overwrites the reti at 0x38 which has already 2 | ;; been set by crt0.s with a jump into our interrupt routine. This results 3 | ;; in two contradicting entries in the hex file and the converter has to deal 4 | ;; with that. srec_cat can be told to accept it. Quartus accepts it by default 5 | .globl _isr 6 | .area VECTOR (ABS) 7 | 8 | .org 0x38 9 | jp _isr 10 | -------------------------------------------------------------------------------- /basic/lesson9/lesson9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alanswx/Tutorials_MiSTer/4080878c5d72b92e0ca7cde96c66bb20669d4cc2/basic/lesson9/lesson9.png -------------------------------------------------------------------------------- /basic/lesson9/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /basic/lesson9/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /basic/lesson9/sys/scanlines.v: -------------------------------------------------------------------------------- 1 | module scanlines #(parameter v2=0) 2 | ( 3 | input clk, 4 | 5 | input [1:0] scanlines, 6 | input [23:0] din, 7 | output reg [23:0] dout, 8 | input hs,vs 9 | ); 10 | 11 | reg [1:0] scanline; 12 | always @(posedge clk) begin 13 | reg old_hs, old_vs; 14 | 15 | old_hs <= hs; 16 | old_vs <= vs; 17 | 18 | if(old_hs && ~hs) begin 19 | if(v2) begin 20 | scanline <= scanline + 1'd1; 21 | if (scanline == scanlines) scanline <= 0; 22 | end 23 | else scanline <= scanline ^ scanlines; 24 | end 25 | if(old_vs && ~vs) scanline <= 0; 26 | end 27 | 28 | wire [7:0] r,g,b; 29 | assign {r,g,b} = din; 30 | 31 | always @(*) begin 32 | case(scanline) 33 | 1: // reduce 25% = 1/2 + 1/4 34 | dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, 35 | {1'b0, g[7:1]} + {2'b00, g[7:2]}, 36 | {1'b0, b[7:1]} + {2'b00, b[7:2]}}; 37 | 38 | 2: // reduce 50% = 1/2 39 | dout = {{1'b0, r[7:1]}, 40 | {1'b0, g[7:1]}, 41 | {1'b0, b[7:1]}}; 42 | 43 | 3: // reduce 75% = 1/4 44 | dout = {{2'b00, r[7:2]}, 45 | {2'b00, g[7:2]}, 46 | {2'b00, b[7:2]}}; 47 | 48 | default: dout = {r,g,b}; 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /basic/lesson9/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/README.md: -------------------------------------------------------------------------------- 1 | # DDRBackground 2 | 3 | This demo loads a binary image into DDR and then displays it. 4 | 5 | 6 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/soc.v 3 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.v 4 | set_global_assignment -name VHDL_FILE rtl/ovo.vhd 5 | set_global_assignment -name VHDL_FILE rtl/base_pack.vhd 6 | set_global_assignment -name VHDL_FILE rtl/dpram.vhd 7 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/ddram.sv 8 | set_global_assignment -name SYSTEMVERILOG_FILE "DDRBackground.sv" 9 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/rtl/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input clk, 7 | input pixel_clock, 8 | output [9:0] hcnt, 9 | output VGA_HS, 10 | output VGA_VS, 11 | output [7:0] VGA_R, 12 | output [7:0] VGA_G, 13 | output [7:0] VGA_B, 14 | output VGA_DE, 15 | output VGA_HBLANK, 16 | output VGA_VBLANK 17 | ); 18 | 19 | 20 | 21 | video_gen video_gen ( 22 | .reset (reset), 23 | .hcnt(hcnt), 24 | .clk (clk), 25 | .pclk (pixel_clock), 26 | .hs (VGA_HS), 27 | .vs (VGA_VS), 28 | .r (VGA_R), 29 | .g (VGA_G), 30 | .b (VGA_B), 31 | .VGA_HBLANK(VGA_HBLANK), 32 | .VGA_VBLANK(VGA_VBLANK), 33 | .VGA_DE(VGA_DE) 34 | ); 35 | 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/README.md: -------------------------------------------------------------------------------- 1 | # DDRBackground 2 | 3 | This demo loads a binary image into DDR and then displays it. 4 | 5 | 6 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.v 3 | set_global_assignment -name VHDL_FILE rtl/ovo.vhd 4 | set_global_assignment -name VHDL_FILE rtl/base_pack.vhd 5 | set_global_assignment -name VHDL_FILE rtl/dpram.vhd 6 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/ddram.sv 7 | set_global_assignment -name SYSTEMVERILOG_FILE "DDRBackground512.sv" 8 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/rtl/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input clk, 7 | input pixel_clock, 8 | output [9:0] hcnt, 9 | output VGA_HS, 10 | output VGA_VS, 11 | output [7:0] VGA_R, 12 | output [7:0] VGA_G, 13 | output [7:0] VGA_B, 14 | output VGA_DE, 15 | output VGA_HBLANK, 16 | output VGA_VBLANK 17 | ); 18 | 19 | 20 | 21 | video_gen video_gen ( 22 | .reset (reset), 23 | .hcnt(hcnt), 24 | .clk (clk), 25 | .pclk (pixel_clock), 26 | .hs (VGA_HS), 27 | .vs (VGA_VS), 28 | .r (VGA_R), 29 | .g (VGA_G), 30 | .b (VGA_B), 31 | .VGA_HBLANK(VGA_HBLANK), 32 | .VGA_VBLANK(VGA_VBLANK), 33 | .VGA_DE(VGA_DE) 34 | ); 35 | 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground512/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/README.md: -------------------------------------------------------------------------------- 1 | # DDRBackground 2 | 3 | This demo loads a binary image into DDR and then displays it. 4 | 5 | 6 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/files.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.v 3 | set_global_assignment -name VHDL_FILE rtl/ovo.vhd 4 | set_global_assignment -name VHDL_FILE rtl/base_pack.vhd 5 | set_global_assignment -name VHDL_FILE rtl/dpram.vhd 6 | set_global_assignment -name SYSTEMVERILOG_FILE rtl/ddram.sv 7 | set_global_assignment -name SYSTEMVERILOG_FILE "DDRBackground5128bit.sv" 8 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/pal_ram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pal_ram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pal_ram_bb.v"] 6 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/rtl/ram64_8.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram64_8.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram64_8_bb.v"] 6 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/rtl/soc.v: -------------------------------------------------------------------------------- 1 | // A simple system-on-a-chip (SoC) for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | module soc ( 5 | input reset, 6 | input clk, 7 | input pixel_clock, 8 | output [9:0] hcnt, 9 | output VGA_HS, 10 | output VGA_VS, 11 | output [7:0] VGA_R, 12 | output [7:0] VGA_G, 13 | output [7:0] VGA_B, 14 | output VGA_DE, 15 | output VGA_HBLANK, 16 | output VGA_VBLANK 17 | ); 18 | 19 | 20 | 21 | video_gen video_gen ( 22 | .reset (reset), 23 | .hcnt(hcnt), 24 | .clk (clk), 25 | .pclk (pixel_clock), 26 | .hs (VGA_HS), 27 | .vs (VGA_VS), 28 | .r (VGA_R), 29 | .g (VGA_G), 30 | .b (VGA_B), 31 | .VGA_HBLANK(VGA_HBLANK), 32 | .VGA_VBLANK(VGA_VBLANK), 33 | .VGA_DE(VGA_DE) 34 | ); 35 | 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/pll_hdmi/pll_hdmi_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /ddrgraphics/ddrbackground5128bitnewddr/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /verilator/detect2600_verilator/cart_constants.vh: -------------------------------------------------------------------------------- 1 | typedef enum bit[4:0] { 2 | BANK00, BANKF8, BANKF6, BANKFE, BANKE0, BANK3F, BANKF4, BANKP2, 3 | BANKFA, BANKCV, BANK2K, BANKUA, BANKE7, BANKF0, BANK32, BANKAR, 4 | BANK3E, BANKSB, BANKWD, BANKEF, BANKDPCP, BANKCTY, BANKCDF 5 | } bss_type ; 6 | 7 | --------------------------------------------------------------------------------