├── README.md ├── final ├── 1101_final.pdf ├── README.md ├── report.pdf └── src │ ├── 00_TESTBED │ ├── PATTERN │ │ ├── golden0.dat │ │ ├── golden1.dat │ │ ├── golden2.dat │ │ ├── golden3.dat │ │ ├── golden4.dat │ │ ├── indata0.dat │ │ ├── indata1.dat │ │ ├── indata2.dat │ │ ├── indata3.dat │ │ └── indata4.dat │ └── testbench.v │ ├── 01_RTL │ ├── 01_run │ ├── 03_run_vcs_sim │ ├── 04_run_dve │ ├── 99_clean_up │ ├── GSIM.v │ ├── Lint │ │ ├── .sg.tcl.swo │ │ ├── .wdir │ │ ├── SG_InstanceVsModuleName.json │ │ ├── cvsd_lint.prj │ │ ├── cvsd_lint │ │ │ ├── .CurrentSessionRunSummaryFiles │ │ │ ├── .design_setup_db │ │ │ │ └── autogenerated__default_snapshot │ │ │ │ │ ├── NomDBLib │ │ │ │ │ ├── __du_srcfiles.info │ │ │ │ │ ├── __lib_src.info │ │ │ │ │ └── __libhdlfiles_src.info │ │ │ │ │ └── __init__.sdb │ │ │ ├── .project_snapshot │ │ │ ├── .project_status │ │ │ ├── .tmp_load_session_goal │ │ │ │ ├── spyglass.log │ │ │ │ ├── spyglass.vdb │ │ │ │ └── spyglass_spysch │ │ │ │ │ ├── .nlv │ │ │ │ │ └── spyglass_sdc │ │ │ │ │ └── sdcSchematicInfo │ │ │ ├── .tmp_sg_current_goal │ │ │ │ ├── spyglass.log │ │ │ │ ├── spyglass.vdb │ │ │ │ └── spyglass_spysch │ │ │ │ │ └── .nlv │ │ │ ├── .tmp_xml │ │ │ │ ├── .GSIM_cvsd_lint.int │ │ │ │ └── .GSIM_cvsd_lint_summary.xml │ │ │ ├── GSIM │ │ │ │ ├── .SG_SaveRestoreDB │ │ │ │ │ └── autogenerated__default_snapshot │ │ │ │ │ │ ├── GoalDBLib │ │ │ │ │ │ └── cvsd_lint │ │ │ │ │ │ │ └── flat_root │ │ │ │ │ │ │ └── GSIM │ │ │ │ │ │ │ ├── block │ │ │ │ │ │ │ ├── flags │ │ │ │ │ │ │ └── prd │ │ │ │ │ │ ├── NomDBLib │ │ │ │ │ │ ├── .MD5sum │ │ │ │ │ │ ├── .nom_edit_info │ │ │ │ │ │ ├── AcOvlRtl_1 │ │ │ │ │ │ ├── AcOvlRtl_2 │ │ │ │ │ │ ├── Ac_multitop01_3 │ │ │ │ │ │ ├── AnalyzeBBox_3 │ │ │ │ │ │ ├── DetectTopDesignUnits_3 │ │ │ │ │ │ ├── ElabSummary_3 │ │ │ │ │ │ ├── GenTopLevelBlocksForAutoSoc_3 │ │ │ │ │ │ ├── GenerateConfMap_2 │ │ │ │ │ │ ├── HangingNetPreReq-ML_3 │ │ │ │ │ │ ├── Latch_VePreReqRule_1 │ │ │ │ │ │ ├── LogNMuxPrereq_3 │ │ │ │ │ │ ├── PECHECK04_3 │ │ │ │ │ │ ├── PECHECK09_3 │ │ │ │ │ │ ├── Pragma_setupa_3 │ │ │ │ │ │ ├── Prereqs_ConstantInput-ML_1 │ │ │ │ │ │ ├── Prereqs_ConstantInput-ML_2 │ │ │ │ │ │ ├── Prereqs_InferLatch_1 │ │ │ │ │ │ ├── Prereqs_RptNegEdgeFF-ML_1 │ │ │ │ │ │ ├── ResetFlop-ML_3 │ │ │ │ │ │ ├── Reset_check05_3 │ │ │ │ │ │ ├── SGDC_meta_design_hier01_3 │ │ │ │ │ │ ├── TxvVhMeta01_2 │ │ │ │ │ │ ├── Txv_SvaSetup01_1 │ │ │ │ │ │ ├── _SYNC_RESET_ATTR_dump.sdb │ │ │ │ │ │ ├── __du_srcfiles.info │ │ │ │ │ │ ├── __lib_src.info │ │ │ │ │ │ ├── _cdc_save_license01_3 │ │ │ │ │ │ ├── _db_format.sdb │ │ │ │ │ │ ├── _inst_attr_dump.sdb │ │ │ │ │ │ ├── _inst_dump.sdb │ │ │ │ │ │ ├── _meta_delay01_3 │ │ │ │ │ │ ├── _mod_dump.sdb │ │ │ │ │ │ ├── _net_dump.sdb │ │ │ │ │ │ ├── _nom_ftable.sdb │ │ │ │ │ │ ├── _nom_sch_dump.sdb │ │ │ │ │ │ ├── _port_dump.sdb │ │ │ │ │ │ ├── _syncResetStyleRTL_3 │ │ │ │ │ │ ├── _type_tree_dump.sdb │ │ │ │ │ │ ├── _vhMeta01_2 │ │ │ │ │ │ ├── msg_db │ │ │ │ │ │ │ ├── nom │ │ │ │ │ │ │ │ ├── .gayab_nom_mod.lst │ │ │ │ │ │ │ │ └── auxi │ │ │ │ │ │ │ │ │ ├── GSIM │ │ │ │ │ │ │ │ │ └── _disable_rule_ │ │ │ │ │ │ │ └── rtl │ │ │ │ │ │ │ │ └── verilog │ │ │ │ │ │ │ │ └── GSIM.mod.dmp │ │ │ │ │ │ └── nom_sde │ │ │ │ │ │ │ ├── .MD5sum │ │ │ │ │ │ │ ├── _db_format.sdb │ │ │ │ │ │ │ ├── _inst_attr_dump.sdb │ │ │ │ │ │ │ ├── _inst_dump.sdb │ │ │ │ │ │ │ ├── _mod_dump.sdb │ │ │ │ │ │ │ ├── _net_dump.sdb │ │ │ │ │ │ │ ├── _nom_ftable.sdb │ │ │ │ │ │ │ ├── _nom_sch_dump.sdb │ │ │ │ │ │ │ ├── _port_dump.sdb │ │ │ │ │ │ │ └── _type_tree_dump.sdb │ │ │ │ │ │ ├── __init__.sdb │ │ │ │ │ │ ├── analyzer │ │ │ │ │ │ ├── 1639834818_file_list.txt │ │ │ │ │ │ ├── 1639834818_macro_defs_list.txt │ │ │ │ │ │ └── 1639834818_macro_usage.txt │ │ │ │ │ │ ├── pragma2Constraint.sgdc │ │ │ │ │ │ └── pragma2Waiver.swl │ │ │ │ └── cvsd_lint │ │ │ │ │ ├── .sg.env │ │ │ │ │ ├── spyglass.vdb │ │ │ │ │ ├── spyglass.vdb.data │ │ │ │ │ ├── spyglass_reports │ │ │ │ │ └── SpyGlass │ │ │ │ │ │ └── blocks.rpt │ │ │ │ │ └── spyglass_spysch │ │ │ │ │ ├── .nlv │ │ │ │ │ ├── NomSavedStatus │ │ │ │ │ ├── analyzer │ │ │ │ │ ├── 1639834818_file_list.txt │ │ │ │ │ ├── 1639834818_macro_defs_list.txt │ │ │ │ │ └── 1639834818_macro_usage.txt │ │ │ │ │ ├── concorde │ │ │ │ │ └── ungroup.tcl │ │ │ │ │ ├── constraint │ │ │ │ │ ├── DesignDeletedSGDCForSignOff.sgdc │ │ │ │ │ ├── DesignWaiver.sgdc │ │ │ │ │ ├── DesignWaiverForSignOff.sgdc │ │ │ │ │ ├── pragma2Constraint.sgdc │ │ │ │ │ ├── sg_waivers.pl │ │ │ │ │ ├── sgdcSchematicInfo │ │ │ │ │ └── spg_autogenerated_waivers.sgdc │ │ │ │ │ ├── gui_files.dump │ │ │ │ │ ├── gui_sparse_attr.dump.bin.gz │ │ │ │ │ ├── lic │ │ │ │ │ └── .sde_info │ │ │ │ │ ├── nomdb │ │ │ │ │ ├── .MD5sum │ │ │ │ │ ├── .spg_nomtype.info │ │ │ │ │ ├── .spg_version.info │ │ │ │ │ ├── _db_format.sdb │ │ │ │ │ ├── _inst_attr_dump.sdb │ │ │ │ │ ├── _inst_dump.sdb │ │ │ │ │ ├── _mod_dump.sdb │ │ │ │ │ ├── _net_dump.sdb │ │ │ │ │ ├── _nom_ftable.sdb │ │ │ │ │ ├── _nom_sch_dump.sdb │ │ │ │ │ ├── _port_dump.sdb │ │ │ │ │ └── _type_tree_dump.sdb │ │ │ │ │ ├── sg_del.pl │ │ │ │ │ ├── sg_msgtag.pl │ │ │ │ │ ├── sg_msgtag.txt │ │ │ │ │ ├── smdb │ │ │ │ │ ├── .dbmd5 │ │ │ │ │ ├── .version │ │ │ │ │ ├── _sdc2sgdcOptFile │ │ │ │ │ ├── custom_viol_attr.db │ │ │ │ │ ├── file.db │ │ │ │ │ ├── fixed_viol.db │ │ │ │ │ ├── message.db │ │ │ │ │ ├── message.db.tmp │ │ │ │ │ ├── rule.db │ │ │ │ │ └── tags.db │ │ │ │ │ │ ├── msg_tags.db │ │ │ │ │ │ ├── rule_tags.db │ │ │ │ │ │ ├── str_def.db │ │ │ │ │ │ └── tag_def.db │ │ │ │ │ ├── spyglass │ │ │ │ │ └── clom_file │ │ │ │ │ ├── tag_name_id_mapping.txt │ │ │ │ │ ├── txt.vdbdir │ │ │ │ │ └── main.vdbdat │ │ │ │ │ └── waiver │ │ │ │ │ ├── pragma2Waiver.swl │ │ │ │ │ └── pragma2Waiver_varfile.swl │ │ │ ├── Run_Summary │ │ │ │ ├── .latest_GSIM_cvsd_lint_ │ │ │ │ └── Run_Summary.18122021214027213343.txt │ │ │ ├── consolidated_reports │ │ │ │ └── GSIM_cvsd_lint │ │ │ │ │ ├── README │ │ │ │ │ ├── SignalUsageReport.rpt │ │ │ │ │ ├── W448_Report │ │ │ │ │ ├── checksum.rpt │ │ │ │ │ ├── elab_summary.rpt │ │ │ │ │ ├── moresimple.rpt │ │ │ │ │ ├── no_msg_reporting_rules.rpt │ │ │ │ │ └── spyglass.log │ │ │ └── html_reports │ │ │ │ └── goals_summary.html │ │ ├── rtl_only.f │ │ ├── run_lint │ │ └── sg.tcl │ ├── buffer.v │ ├── core.v │ ├── overflow.v │ └── rtl_01.f │ ├── 02_SYN │ ├── 02_eps_run.dc │ ├── 02_run.dc │ ├── Netlist │ │ ├── GSIM_syn.ddc │ │ ├── GSIM_syn.sdc │ │ ├── GSIM_syn.sdf │ │ └── GSIM_syn.v │ ├── eps_phy_cons.tcl │ ├── syn.tcl │ └── syn_eps.tcl │ ├── 03_GATE │ ├── 03_run │ └── rtl_03.f │ ├── 04_POWER │ ├── 04_try_run │ ├── try_diff.py │ └── try_script.tcl │ ├── 05_APR │ ├── GSIM_pr.sdf │ └── GSIM_pr.v │ └── 06_POST │ ├── 06_run │ └── rtl_06.f ├── hw1 ├── 1101_hw1.pdf └── src │ ├── 01_run │ ├── 99_clean │ ├── alu.v │ ├── hidden │ ├── hidden_I.dat │ └── hidden_O.dat │ ├── pattern │ ├── INST0_I.dat │ ├── INST0_O.dat │ ├── INST1_I.dat │ ├── INST1_O.dat │ ├── INST2_I.dat │ ├── INST2_O.dat │ ├── INST3_I.dat │ ├── INST3_O.dat │ ├── INST4_I.dat │ ├── INST4_O.dat │ ├── INST5_I.dat │ ├── INST5_O.dat │ ├── INST6_I.dat │ ├── INST6_O.dat │ ├── INST7_I.dat │ ├── INST7_O.dat │ ├── INST8_I.dat │ └── INST8_O.dat │ └── testbench.v ├── hw2 ├── 1101_hw2.pdf └── src │ ├── 00_TESTBED │ ├── PATTERN │ │ ├── hidden_pattern │ │ │ ├── h0 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h1 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h10 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h11 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h12 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h13 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h14 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h15 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h16 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h17 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h18 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h19 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h2 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h3 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h4 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h5 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h6 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h7 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ ├── h8 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ │ └── h9 │ │ │ │ ├── data.dat │ │ │ │ ├── inst.dat │ │ │ │ └── status.dat │ │ ├── p0 │ │ │ ├── data.dat │ │ │ ├── inst.dat │ │ │ ├── inst_assemble.dat │ │ │ └── status.dat │ │ └── p1 │ │ │ ├── data.dat │ │ │ ├── inst.dat │ │ │ ├── inst_assemble.dat │ │ │ └── status.dat │ └── testbed.v │ └── 01_RTL │ ├── 01_run │ ├── 99_clean_up │ ├── alu.v │ ├── control.v │ ├── core.v │ ├── data_mem.v │ ├── define.v │ ├── inst_mem.v │ ├── reg_file.v │ └── rtl.f ├── hw3 ├── 1101_hw3.pdf └── src │ ├── 00_TESTBED │ ├── PATTERN │ │ ├── golden0.dat │ │ ├── golden1.dat │ │ ├── golden2.dat │ │ ├── golden3.dat │ │ ├── golden4.dat │ │ ├── goldencyk.dat │ │ ├── goldencyk2.dat │ │ ├── goldencyk3.dat │ │ ├── goldencyk4.dat │ │ ├── indata0.dat │ │ ├── indata1.dat │ │ ├── indata2.dat │ │ ├── indata3.dat │ │ ├── indata4.dat │ │ ├── indatacyk3.dat │ │ ├── opmode0.dat │ │ ├── opmode1.dat │ │ ├── opmode2.dat │ │ ├── opmode3.dat │ │ ├── opmode4.dat │ │ ├── opmodecyk.dat │ │ ├── opmodecyk2.dat │ │ ├── opmodecyk3.dat │ │ └── opmodecyk4.dat │ ├── hidden │ │ ├── golden_hidden.dat │ │ ├── indata_hidden.dat │ │ └── opmode_hidden.dat │ └── testbed.v │ ├── 01_RTL │ ├── 01_run │ ├── 99_clean_up │ ├── census.v │ ├── color.v │ ├── define.v │ ├── ipdc.v │ ├── median.v │ └── rtl_01.f │ ├── 02_SYN │ ├── 02_run.dc │ ├── Netlist │ │ ├── ipdc_syn.ddc │ │ ├── ipdc_syn.sdf │ │ └── ipdc_syn.v │ ├── Report │ │ ├── ipdc_syn.area │ │ └── ipdc_syn.timing │ ├── ipdc_dc.sdc │ └── syn.tcl │ ├── 03_GATE │ ├── 03_run │ ├── 99_clean_up │ └── rtl_03.f │ ├── ranking.txt │ ├── report.txt │ ├── sram_256x8 │ ├── sram_256x8.pdf │ ├── sram_256x8.v │ ├── sram_256x8_slow_syn.db │ └── sram_256x8_slow_syn.lib │ ├── sram_4096x8 │ ├── sram_4096x8.pdf │ ├── sram_4096x8.v │ ├── sram_4096x8_slow_syn.db │ └── sram_4096x8_slow_syn.lib │ └── sram_512x8 │ ├── sram_512x8.pdf │ ├── sram_512x8.v │ ├── sram_512x8_slow_syn.db │ └── sram_512x8_slow_syn.lib ├── hw4 ├── 1101_hw4.pdf ├── ICC2019.pdf └── src │ ├── 00_TESTBED │ ├── PATTERN │ │ ├── f1.dat │ │ ├── f2.dat │ │ ├── f3.dat │ │ ├── f4.dat │ │ ├── f5.dat │ │ ├── f6.dat │ │ ├── f7.dat │ │ └── pattern1.dat │ └── testfixture.v │ ├── 01_RTL │ ├── 01_runall_rtl │ ├── IOTDF.v │ └── define.v │ ├── 02_SYN │ ├── .synopsys_dc.setup │ ├── 02_run.dc │ ├── IOTDF_DC.sdc │ ├── Netlist │ │ ├── IOTDF_syn.ddc │ │ ├── IOTDF_syn.sdc │ │ ├── IOTDF_syn.sdf │ │ └── IOTDF_syn.v │ ├── Report │ │ ├── IOTDF_syn.area │ │ ├── IOTDF_syn.timing │ │ ├── check_design.txt │ │ └── check_timing.txt │ └── syn.tcl │ ├── 03_GATE │ └── 03_runall_syn │ └── 04_POWER │ ├── .synopsys_pt.setup │ ├── 04_run_power │ ├── F1_7.power │ └── pt_script.tcl └── hw5 ├── 1101_hw5.pdf ├── report.pdf └── src ├── 00_TESTBED ├── PATTERN │ ├── golden0.dat │ ├── golden1.dat │ ├── golden2.dat │ ├── golden3.dat │ ├── golden4.dat │ ├── goldencyk.dat │ ├── goldencyk2.dat │ ├── goldencyk3.dat │ ├── goldencyk4.dat │ ├── indata0.dat │ ├── indata1.dat │ ├── indata2.dat │ ├── indata3.dat │ ├── indata4.dat │ ├── indatacyk3.dat │ ├── opmode0.dat │ ├── opmode1.dat │ ├── opmode2.dat │ ├── opmode3.dat │ ├── opmode4.dat │ ├── opmodecyk.dat │ ├── opmodecyk2.dat │ ├── opmodecyk3.dat │ └── opmodecyk4.dat ├── hidden │ ├── golden_hidden.dat │ ├── indata_hidden.dat │ └── opmode_hidden.dat └── testbed.v ├── 05_APR ├── design_data │ ├── ipdc_cts.sdc │ ├── ipdc_syn.sdc │ └── ipdc_syn.v ├── ipdc_pr.sdf ├── ipdc_pr.v └── mmmc.view └── 06_POST ├── 06_run ├── rtl_06.f └── sram_256x8 ├── sram_256x8.pdf ├── sram_256x8.v ├── sram_256x8_slow_syn.db └── sram_256x8_slow_syn.lib /README.md: -------------------------------------------------------------------------------- 1 | # NTU_CVSD_2021 2 | Computer-Aided VLSI System Design 3 | -------------------------------------------------------------------------------- /final/1101_final.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/albertfan1120/NTU_CVSD_2021/HEAD/final/1101_final.pdf -------------------------------------------------------------------------------- /final/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/albertfan1120/NTU_CVSD_2021/HEAD/final/README.md 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3 | Clock period: 6.0 (ns) 4 | 5 | Area : 83051.425465 (um^2) 6 | 7 | Use DesignWare? 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