├── README ├── utils ├── lib ├── include ├── .gitignore ├── drp.h └── bitfile.h ├── fpga ├── common │ ├── lib │ └── tb │ │ ├── mqnic_core_axi │ │ └── mqnic.py │ │ ├── mqnic_core_pcie_us │ │ └── mqnic.py │ │ ├── mqnic_core_pcie_ptile │ │ └── mqnic.py │ │ ├── mqnic_core_pcie_s10 │ │ └── mqnic.py │ │ ├── mqnic_core_pcie_us_tdma │ │ └── mqnic.py │ │ └── Makefile ├── lib │ ├── axis │ ├── pcie │ │ ├── README │ │ ├── example │ │ │ ├── AU200 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ └── Makefile │ │ │ ├── AU250 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ └── Makefile │ │ │ ├── AU280 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ └── Makefile │ │ │ ├── AU50 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── Makefile │ │ │ │ │ └── README.md │ │ │ ├── fb2CG │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ ├── led.tcl │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── Makefile │ │ │ │ │ └── led.tcl │ │ │ ├── 520N_MX │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ └── common │ │ │ │ │ └── README.md │ │ │ ├── ExaNIC_X10 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ └── Makefile │ │ │ ├── ExaNIC_X25 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ └── Makefile │ │ │ ├── S10DX_DK │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ └── rtl │ │ │ │ │ └── common │ │ │ ├── S10MX_DK │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ └── rtl │ │ │ │ │ └── common │ │ │ ├── VCU108 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── Makefile │ │ │ │ │ └── README.md │ │ │ ├── VCU118 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── Makefile │ │ │ │ │ └── README.md │ │ │ ├── VCU1525 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── Makefile │ │ │ │ │ └── README.md │ │ │ ├── ZCU106 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ ├── Makefile │ │ │ │ │ └── README.md │ │ │ ├── ADM_PCIE_9V3 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── common │ │ │ │ │ ├── driver │ │ │ │ │ └── README.md │ │ │ │ └── fpga_axi │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── driver │ │ │ │ │ └── Makefile │ │ │ ├── DE10_Agilex │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ └── common │ │ │ │ │ └── README.md │ │ │ └── common │ │ │ │ ├── tb │ │ │ │ └── example_core_pcie │ │ │ │ │ └── pcie_if.py │ │ │ │ └── driver │ │ │ │ └── example │ │ │ │ └── Makefile │ │ ├── tb │ │ │ ├── pcie_msix │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_s10_if │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_tlp_mux │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_us_if │ │ │ │ └── pcie_if.py │ │ │ ├── dma_if_pcie_rd │ │ │ │ ├── pcie_if.py │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── dma_if_pcie_wr │ │ │ │ ├── pcie_if.py │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── pcie_axi_master │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_axil_master │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_ptile_if │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_ptile_if_rx │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_ptile_if_tx │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_s10_if_rx │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_s10_if_tx │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_tlp_demux │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_tlp_fifo │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_tlp_fifo_mux │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_us_if_cc │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_us_if_cq │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_us_if_rc │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_us_if_rq │ │ │ │ └── pcie_if.py │ │ │ ├── dma_if_axi │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── dma_psdpram │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── pcie_axi_master_rd │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_axi_master_wr │ │ │ │ └── pcie_if.py │ │ │ ├── pcie_tlp_demux_bar │ │ │ │ └── pcie_if.py │ │ │ ├── dma_if_axi_rd │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── dma_if_axi_wr │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── dma_if_pcie_us │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── dma_if_pcie_us_rd │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── dma_if_pcie_us_wr │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── dma_psdpram_async │ │ │ │ └── dma_psdp_ram.py │ │ │ ├── pcie_axil_master_minimal │ │ │ │ └── pcie_if.py │ │ │ ├── dma_client_axis_sink │ │ │ │ └── dma_psdp_ram.py │ │ │ └── dma_client_axis_source │ │ │ │ └── dma_psdp_ram.py │ │ ├── AUTHORS │ │ ├── .gitignore │ │ ├── scripts │ │ │ ├── pcie_rescan.sh │ │ │ ├── pcie_flr.sh │ │ │ ├── pcie_reset.sh │ │ │ └── pcie_ext_tag.sh │ │ └── tox.ini │ ├── eth │ │ ├── lib │ │ │ └── axis │ │ │ │ ├── README │ │ │ │ ├── AUTHORS │ │ │ │ ├── .gitignore │ │ │ │ └── tox.ini │ │ ├── tb │ │ │ ├── eth_phy_10g │ │ │ │ └── baser.py │ │ │ ├── ptp_td_phc │ │ │ │ └── ptp_td.py │ │ │ ├── axis_baser_rx_64 │ │ │ │ └── baser.py │ │ │ ├── axis_baser_tx_64 │ │ │ │ └── baser.py │ │ │ ├── axis_ep.py │ │ │ ├── eth_mac_phy_10g │ │ │ │ └── baser.py │ │ │ ├── ptp_td_leaf │ │ │ │ └── ptp_td.py │ │ │ ├── ptp_td_rel2tod │ │ │ │ └── ptp_td.py │ │ │ ├── eth_mac_phy_10g_fifo │ │ │ │ └── baser.py │ │ │ ├── xgmii_baser_dec_64 │ │ │ │ └── baser.py │ │ │ └── xgmii_baser_enc_64 │ │ │ │ └── baser.py │ │ ├── example │ │ │ ├── ATLYS │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── clock.ucf │ │ │ │ │ └── Makefile │ │ │ ├── Arty │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── C10LP │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── DE2-115 │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── DE5-Net │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── cores │ │ │ │ │ └── Makefile │ │ │ │ │ └── Makefile │ │ │ ├── HTG640 │ │ │ │ ├── fpga │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── Makefile │ │ │ │ │ └── coregen │ │ │ │ │ │ ├── coregen.cgp │ │ │ │ │ │ └── Makefile │ │ │ │ └── fpga_cxpt16 │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── Makefile │ │ │ │ │ └── coregen │ │ │ │ │ ├── coregen.cgp │ │ │ │ │ └── Makefile │ │ │ ├── RV901T │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── clock.ucf │ │ │ ├── ZCU102 │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── ZCU106 │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── 520N_MX │ │ │ │ └── fpga_10g │ │ │ │ │ └── lib │ │ │ │ │ └── eth │ │ │ ├── Alveo │ │ │ │ └── fpga_25g │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── ExaNIC_X10 │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── HTG9200 │ │ │ │ ├── fpga_25g │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ └── pll │ │ │ │ │ │ └── HTG9200_161-9k2_161.slabtimeproj │ │ │ │ └── fpga_fmc_htg_6qsfp_25g │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── pll │ │ │ │ │ ├── HTG9200_161-9k2_161.slabtimeproj │ │ │ │ │ └── HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj │ │ │ ├── KC705 │ │ │ │ ├── fpga_gmii │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── clock.xdc │ │ │ │ │ └── Makefile │ │ │ │ ├── fpga_rgmii │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ │ └── generate_bit_iodelay.tcl │ │ │ │ │ └── Makefile │ │ │ │ └── fpga_sgmii │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── ip │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ └── Makefile │ │ │ ├── ML605 │ │ │ │ ├── fpga_gmii │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── clock.ucf │ │ │ │ │ └── Makefile │ │ │ │ ├── fpga_rgmii │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── clock.ucf │ │ │ │ │ └── Makefile │ │ │ │ └── fpga_sgmii │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── Makefile │ │ │ │ │ └── coregen │ │ │ │ │ ├── coregen.cgp │ │ │ │ │ └── Makefile │ │ │ ├── NetFPGA_SUME │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── ip │ │ │ │ │ ├── ten_gig_eth_pcs_pma_0.tcl │ │ │ │ │ └── ten_gig_eth_pcs_pma_1.tcl │ │ │ │ │ └── Makefile │ │ │ ├── NexysVideo │ │ │ │ └── fpga │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── generate_bit_iodelay.tcl │ │ │ │ │ └── Makefile │ │ │ ├── S10DX_DK │ │ │ │ └── fpga_10g │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── S10MX_DK │ │ │ │ └── fpga_10g │ │ │ │ │ └── lib │ │ │ │ │ └── eth │ │ │ ├── VCU108 │ │ │ │ ├── fpga_10g │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── ip │ │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ └── Makefile │ │ │ │ └── fpga_1g │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── ip │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ └── Makefile │ │ │ ├── VCU118 │ │ │ │ ├── fpga_1g │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── Makefile │ │ │ │ │ └── ip │ │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ ├── fpga_25g │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── Makefile │ │ │ │ │ └── ip │ │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ └── fpga_fmc_htg_6qsfp_25g │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── pll │ │ │ │ │ └── VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj │ │ │ │ │ └── ip │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ ├── fb2CG │ │ │ │ └── fpga_25g │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── Makefile │ │ │ │ │ └── led.tcl │ │ │ ├── ADM_PCIE_9V3 │ │ │ │ └── fpga_25g │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ └── Makefile │ │ │ ├── DCS7132LB │ │ │ │ └── fpga_25g │ │ │ │ │ └── lib │ │ │ │ │ └── eth │ │ │ └── ExaNIC_X25 │ │ │ │ └── fpga_25g │ │ │ │ ├── lib │ │ │ │ └── eth │ │ │ │ └── Makefile │ │ ├── AUTHORS │ │ ├── .gitignore │ │ └── tox.ini │ ├── axi │ │ ├── AUTHORS │ │ ├── .gitignore │ │ └── tox.ini │ └── psmake │ │ ├── examples │ │ ├── xsdk │ │ │ ├── helloworldlib.h │ │ │ ├── baud_rate.sed │ │ │ ├── helloworldlib.c │ │ │ └── helloworld.patch │ │ └── vitis │ │ │ ├── baud_rate.sed │ │ │ ├── example_app │ │ │ └── platform_config.h │ │ │ └── helloworld.patch │ │ └── .gitignore ├── app │ ├── dma_bench │ │ ├── lib │ │ ├── rtl │ │ │ └── common │ │ ├── modules │ │ │ ├── mqnic │ │ │ └── mqnic_app_dma_bench │ │ │ │ └── Makefile │ │ └── tb │ │ │ └── mqnic_core_pcie_us │ │ │ └── mqnic.py │ ├── template │ │ ├── lib │ │ ├── utils │ │ │ ├── lib │ │ │ └── include │ │ ├── rtl │ │ │ └── common │ │ ├── modules │ │ │ ├── mqnic │ │ │ └── mqnic_app_template │ │ │ │ └── Makefile │ │ └── tb │ │ │ └── mqnic_core_pcie_us │ │ │ └── mqnic.py │ └── custom_port_demo │ │ ├── lib │ │ ├── rtl │ │ └── common │ │ ├── tb │ │ └── mqnic_core_pcie_us │ │ │ └── mqnic.py │ │ └── utils │ │ └── zcu102_demo.sh ├── mqnic │ ├── KR260 │ │ └── fpga │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ └── tb │ │ │ └── fpga_core │ │ │ └── mqnic.py │ ├── Alveo │ │ ├── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ ├── tb │ │ │ │ └── fpga_core │ │ │ │ │ └── mqnic.py │ │ │ ├── hbm.xdc │ │ │ ├── cfgmclk.xdc │ │ │ ├── boot.xdc │ │ │ ├── Makefile │ │ │ └── ip │ │ │ │ ├── cms.tcl │ │ │ │ ├── ddr4_0.tcl │ │ │ │ └── ddr4_0_au280.tcl │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── hbm.xdc │ │ │ ├── boot.xdc │ │ │ ├── Makefile │ │ │ └── ip │ │ │ ├── cms.tcl │ │ │ ├── ddr4_0.tcl │ │ │ └── ddr4_0_au280.tcl │ ├── VCU108 │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── Makefile │ ├── VCU118 │ │ ├── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ ├── tb │ │ │ │ └── fpga_core │ │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ ├── Makefile │ │ │ └── ip │ │ │ │ └── ddr4_0.tcl │ │ └── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ ├── Makefile │ │ │ └── ip │ │ │ └── ddr4_0.tcl │ ├── XUPP3R │ │ ├── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ ├── tb │ │ │ │ └── fpga_core │ │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── ip │ │ │ │ ├── ddr4_0_xupp3r.tcl │ │ │ │ ├── ddr4_0_xusp3s.tcl │ │ │ │ └── ddr4_sodimm_0_xusp3s.tcl │ │ └── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── ip │ │ │ └── ddr4_0.tcl │ ├── ZCU102 │ │ └── fpga │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ ├── sync_signal.v │ │ │ └── common │ │ │ ├── ps │ │ │ └── petalinux │ │ │ │ ├── .petalinux │ │ │ │ └── .gitkeep │ │ │ │ ├── project-spec │ │ │ │ ├── hw-description │ │ │ │ │ └── metadata │ │ │ │ ├── meta-user │ │ │ │ │ ├── recipes-bsp │ │ │ │ │ │ ├── device-tree │ │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ │ └── pl-custom.dtsi │ │ │ │ │ │ │ └── device-tree.bbappend │ │ │ │ │ │ ├── uboot-device-tree │ │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ │ └── system-user.dtsi │ │ │ │ │ │ │ └── uboot-device-tree.bbappend │ │ │ │ │ │ ├── u-boot │ │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ │ └── platform-top.h │ │ │ │ │ │ │ └── u-boot-xlnx_%.bbappend │ │ │ │ │ │ └── fsbl-firmware │ │ │ │ │ │ │ └── fsbl-firmware_%.bbappend │ │ │ │ │ ├── conf │ │ │ │ │ │ ├── petalinuxbsp.conf │ │ │ │ │ │ ├── user-rootfsconfig │ │ │ │ │ │ └── layer.conf │ │ │ │ │ ├── recipes-kernel │ │ │ │ │ │ └── linux │ │ │ │ │ │ │ ├── linux-xlnx_%.bbappend │ │ │ │ │ │ │ └── linux-xlnx │ │ │ │ │ │ │ └── enable_ptp.cfg │ │ │ │ │ └── recipes-apps │ │ │ │ │ │ ├── gpio-demo │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ └── Makefile │ │ │ │ │ │ └── gpio-demo.bb │ │ │ │ │ │ └── peekpoke │ │ │ │ │ │ ├── files │ │ │ │ │ │ └── Makefile │ │ │ │ │ │ └── peekpoke.bb │ │ │ │ ├── attributes │ │ │ │ └── configs │ │ │ │ │ └── init-ifupdown │ │ │ │ │ └── interfaces │ │ │ │ ├── Makefile │ │ │ │ ├── local.mk │ │ │ │ ├── config.project │ │ │ │ └── .gitignore │ │ │ ├── fpga │ │ │ └── .gitignore │ │ │ ├── tb │ │ │ ├── fpga_core │ │ │ │ └── mqnic.py │ │ │ └── fpga_core_app_custom_port_demo │ │ │ │ └── mqnic.py │ │ │ ├── Makefile │ │ │ └── ip │ │ │ └── ddr4_0.tcl │ ├── fb2CG │ │ ├── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ ├── tb │ │ │ │ └── fpga_core │ │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── Makefile │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── Makefile │ ├── 250_SoC │ │ ├── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ └── tb │ │ │ └── fpga_core │ │ │ └── mqnic.py │ ├── 520N_MX │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ └── tb │ │ │ └── fpga_core │ │ │ └── mqnic.py │ ├── IA_420F │ │ └── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ └── mac_100g.sdc │ ├── NetFPGA_SUME │ │ └── fpga │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── pcie.xdc │ │ │ ├── ip │ │ │ ├── ten_gig_eth_pcs_pma_0.tcl │ │ │ └── ten_gig_eth_pcs_pma_1.tcl │ │ │ └── Makefile │ ├── Nexus_K3P_Q │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── ip │ │ │ └── ddr4_0.tcl │ ├── Nexus_K3P_S │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ └── boot.xdc │ ├── ZCU106 │ │ ├── fpga_pcie │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ ├── tb │ │ │ │ └── fpga_core │ │ │ │ │ └── mqnic.py │ │ │ ├── Makefile │ │ │ └── ip │ │ │ │ └── ddr4_0.tcl │ │ └── fpga_zynqmp │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ ├── sync_signal.v │ │ │ └── common │ │ │ ├── ps │ │ │ └── petalinux │ │ │ │ ├── .petalinux │ │ │ │ └── .gitkeep │ │ │ │ ├── project-spec │ │ │ │ ├── hw-description │ │ │ │ │ └── metadata │ │ │ │ ├── meta-user │ │ │ │ │ ├── recipes-bsp │ │ │ │ │ │ ├── device-tree │ │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ │ └── pl-custom.dtsi │ │ │ │ │ │ │ └── device-tree.bbappend │ │ │ │ │ │ ├── uboot-device-tree │ │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ │ └── system-user.dtsi │ │ │ │ │ │ │ └── uboot-device-tree.bbappend │ │ │ │ │ │ ├── u-boot │ │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ │ └── platform-top.h │ │ │ │ │ │ │ └── u-boot-xlnx_%.bbappend │ │ │ │ │ │ └── fsbl-firmware │ │ │ │ │ │ │ └── fsbl-firmware_%.bbappend │ │ │ │ │ ├── conf │ │ │ │ │ │ ├── petalinuxbsp.conf │ │ │ │ │ │ ├── user-rootfsconfig │ │ │ │ │ │ └── layer.conf │ │ │ │ │ ├── recipes-kernel │ │ │ │ │ │ └── linux │ │ │ │ │ │ │ ├── linux-xlnx_%.bbappend │ │ │ │ │ │ │ └── linux-xlnx │ │ │ │ │ │ │ └── enable_ptp.cfg │ │ │ │ │ └── recipes-apps │ │ │ │ │ │ ├── gpio-demo │ │ │ │ │ │ ├── files │ │ │ │ │ │ │ └── Makefile │ │ │ │ │ │ └── gpio-demo.bb │ │ │ │ │ │ └── peekpoke │ │ │ │ │ │ ├── files │ │ │ │ │ │ └── Makefile │ │ │ │ │ │ └── peekpoke.bb │ │ │ │ ├── attributes │ │ │ │ └── configs │ │ │ │ │ └── init-ifupdown │ │ │ │ │ └── interfaces │ │ │ │ ├── Makefile │ │ │ │ ├── local.mk │ │ │ │ ├── config.project │ │ │ │ └── .gitignore │ │ │ ├── fpga │ │ │ └── .gitignore │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── Makefile │ │ │ └── ip │ │ │ └── ddr4_0.tcl │ ├── fb4CGg3 │ │ ├── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ ├── tb │ │ │ │ └── fpga_core │ │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── ip │ │ │ │ ├── ddr4_0.tcl │ │ │ │ └── ddr4_sodimm_0.tcl │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── ip │ │ │ ├── ddr4_0.tcl │ │ │ └── ddr4_sodimm_0.tcl │ ├── ADM_PCIE_9V3 │ │ ├── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ │ └── common │ │ │ ├── tb │ │ │ │ └── fpga_core │ │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── Makefile │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ ├── boot.xdc │ │ │ └── Makefile │ ├── DE10_Agilex │ │ └── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ └── mac_100g.sdc │ ├── DK_DEV_1SDX_P_A │ │ └── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ └── mac_100g.sdc │ ├── DK_DEV_1SMX_H_A │ │ └── fpga_25g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ └── tb │ │ │ └── fpga_core │ │ │ └── mqnic.py │ ├── DK_DEV_AGF014EA │ │ └── fpga_100g │ │ │ ├── app │ │ │ ├── lib │ │ │ ├── rtl │ │ │ └── common │ │ │ ├── tb │ │ │ └── fpga_core │ │ │ │ └── mqnic.py │ │ │ └── mac_100g.sdc │ └── DNPCIe_40G_KU_LL_2QSFP │ │ └── fpga │ │ ├── app │ │ ├── lib │ │ ├── rtl │ │ └── common │ │ ├── tb │ │ └── fpga_core │ │ │ └── mqnic.py │ │ ├── boot.xdc │ │ └── ip │ │ └── ddr4_0.tcl ├── watch.sh └── build_images_project.ini ├── lib └── mqnic │ ├── .gitignore │ ├── mqnic_hw.h │ ├── mqnic_ioctl.h │ └── reg_block.h ├── scripts ├── pcie └── mqnic_ddcmd.sh ├── AUTHORS ├── meta-corundum ├── recipes-devtools │ └── mqnic-tools │ │ ├── files │ │ ├── lib │ │ ├── utils │ │ ├── include │ │ └── modules │ │ └── mqnic-tools.bb ├── recipes-modules │ └── kernel-module-mqnic │ │ ├── files │ │ └── mqnic │ │ └── kernel-module-mqnic.bb └── conf │ └── layer.conf ├── docs ├── requirements.txt ├── source │ ├── diagrams │ │ └── svg │ │ │ ├── corundum_block.odg │ │ │ ├── queue_pointers.odg │ │ │ ├── corundum_tdma_ctrl_block.odg │ │ │ ├── corundum_queue_manager_block.odg │ │ │ └── corundum_tx_scheduler_block.odg │ ├── modules │ │ ├── cpl_queue_manager.rst │ │ ├── index.rst │ │ ├── rx_hash.rst │ │ ├── rx_checksum.rst │ │ ├── desc_fetch.rst │ │ ├── cpl_write.rst │ │ ├── tx_checksum.rst │ │ ├── rx_engine.rst │ │ ├── tx_engine.rst │ │ ├── mqnic_egress.rst │ │ ├── mqnic_interface_rx.rst │ │ ├── mqnic_interface_tx.rst │ │ ├── mqnic_ingress.rst │ │ └── mqnic_interface.rst │ ├── contents.rst │ └── glossary.rst └── Makefile ├── modules └── mqnic │ └── .gitignore ├── .gitignore ├── .readthedocs.yaml └── tox.ini /README: -------------------------------------------------------------------------------- 1 | README.md -------------------------------------------------------------------------------- /utils/lib: -------------------------------------------------------------------------------- 1 | ../lib/ -------------------------------------------------------------------------------- /fpga/common/lib: -------------------------------------------------------------------------------- 1 | ../lib/ -------------------------------------------------------------------------------- /fpga/lib/axis: -------------------------------------------------------------------------------- 1 | eth/lib/axis/ -------------------------------------------------------------------------------- /utils/include: -------------------------------------------------------------------------------- 1 | ../include/ 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/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/mqnic.py: -------------------------------------------------------------------------------- 1 | ../../../../../common/tb/mqnic.py -------------------------------------------------------------------------------- /meta-corundum/recipes-modules/kernel-module-mqnic/files/mqnic: -------------------------------------------------------------------------------- 1 | ../../../../modules/mqnic -------------------------------------------------------------------------------- /fpga/lib/eth/lib/axis/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.lxt 3 | *.pyc 4 | *.vvp 5 | *.kate-swp 6 | 7 | -------------------------------------------------------------------------------- /fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/mqnic.py: -------------------------------------------------------------------------------- 1 | ../../../../../common/tb/mqnic.py -------------------------------------------------------------------------------- /fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/mqnic.py: -------------------------------------------------------------------------------- 1 | ../../../../../common/tb/mqnic.py -------------------------------------------------------------------------------- /fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/mqnic.py: -------------------------------------------------------------------------------- 1 | ../../../../../common/tb/mqnic.py -------------------------------------------------------------------------------- /fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/mqnic.py: -------------------------------------------------------------------------------- 1 | ../../../../../common/tb/mqnic.py -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/Makefile: -------------------------------------------------------------------------------- 1 | ../../../../../lib/psmake/petalinux.mk -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/mqnic.py: -------------------------------------------------------------------------------- 1 | ../../../../../common/tb/mqnic.py -------------------------------------------------------------------------------- /fpga/lib/pcie/scripts/pcie_rescan.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | echo 1 > /sys/bus/pci/rescan 4 | 5 | 6 | -------------------------------------------------------------------------------- /utils/.gitignore: -------------------------------------------------------------------------------- 1 | mqnic-config 2 | mqnic-bmc 3 | mqnic-dump 4 | mqnic-fw 5 | mqnic-xcvr 6 | perout 7 | -------------------------------------------------------------------------------- /fpga/lib/psmake/.gitignore: -------------------------------------------------------------------------------- 1 | # generic intermediate and editor backup files 2 | *.swp 3 | *.~ 4 | .#* 5 | *~ 6 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | }; 3 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | }; 3 | -------------------------------------------------------------------------------- /fpga/lib/psmake/examples/xsdk/helloworldlib.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | void helloworld(void) 4 | { 5 | printf("Hello World\n\r"); 6 | } 7 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/petalinuxbsp.conf: -------------------------------------------------------------------------------- 1 | #User Configuration 2 | 3 | #OE_TERMINAL = "tmux" 4 | 5 | -------------------------------------------------------------------------------- /docs/source/diagrams/svg/corundum_block.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/docs/source/diagrams/svg/corundum_block.odg -------------------------------------------------------------------------------- /docs/source/diagrams/svg/queue_pointers.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/docs/source/diagrams/svg/queue_pointers.odg -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/conf/petalinuxbsp.conf: -------------------------------------------------------------------------------- 1 | #User Configuration 2 | 3 | #OE_TERMINAL = "tmux" 4 | 5 | -------------------------------------------------------------------------------- /modules/mqnic/.gitignore: -------------------------------------------------------------------------------- 1 | *.cmd 2 | *.mod 3 | *.mod.c 4 | *.o 5 | *.ko 6 | 7 | .tmp_versions/ 8 | modules.order 9 | Module.symvers 10 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_100g/hbm.xdc: -------------------------------------------------------------------------------- 1 | # force debug hub to use HBM APB clock to prevent CDC issues 2 | connect_debug_port dbg_hub/clk [get_nets */*/APB_0_PCLK] 3 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_25g/hbm.xdc: -------------------------------------------------------------------------------- 1 | # force debug hub to use HBM APB clock to prevent CDC issues 2 | connect_debug_port dbg_hub/clk [get_nets */*/APB_0_PCLK] 3 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/files/system-user.dtsi: -------------------------------------------------------------------------------- 1 | /include/ "system-conf.dtsi" 2 | / { 3 | }; 4 | -------------------------------------------------------------------------------- /docs/source/diagrams/svg/corundum_tdma_ctrl_block.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/docs/source/diagrams/svg/corundum_tdma_ctrl_block.odg -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/files/system-user.dtsi: -------------------------------------------------------------------------------- 1 | /include/ "system-conf.dtsi" 2 | / { 3 | }; 4 | -------------------------------------------------------------------------------- /docs/source/diagrams/svg/corundum_queue_manager_block.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/docs/source/diagrams/svg/corundum_queue_manager_block.odg -------------------------------------------------------------------------------- /docs/source/diagrams/svg/corundum_tx_scheduler_block.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/docs/source/diagrams/svg/corundum_tx_scheduler_block.odg -------------------------------------------------------------------------------- /fpga/lib/eth/example/KC705/fpga_gmii/clock.xdc: -------------------------------------------------------------------------------- 1 | # Clock constraints 2 | 3 | # BUFGMUX outputs 4 | set_clock_groups -physically_exclusive -group clk_mmcm_out -group phy_tx_clk 5 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | -------------------------------------------------------------------------------- /fpga/watch.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | watch -n 30 "./collect_utilization.py --csv output.csv --log output.log > /dev/null ; cat output.csv | column -s, -t -H 1 -T 3 -c 210" 4 | 5 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | -------------------------------------------------------------------------------- /fpga/mqnic/NetFPGA_SUME/fpga/pcie.xdc: -------------------------------------------------------------------------------- 1 | 2 | 3 | set_false_path -to [get_pins {pcie_pipe_pclk_bufgctrl_inst/S0}] 4 | set_false_path -to [get_pins {pcie_pipe_pclk_bufgctrl_inst/S1}] 5 | 6 | -------------------------------------------------------------------------------- /docs/source/modules/cpl_queue_manager.rst: -------------------------------------------------------------------------------- 1 | .. _mod_cpl_queue_manager: 2 | 3 | ===================== 4 | ``cpl_queue_manager`` 5 | ===================== 6 | 7 | ``cpl_queue_manager`` implements -------------------------------------------------------------------------------- /fpga/lib/eth/example/NexysVideo/fpga/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | # IDELAY on RGMII from PHY chip 4 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 5 | 6 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/KC705/fpga_rgmii/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | # IDELAY on RGMII from PHY chip 4 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 5 | 6 | -------------------------------------------------------------------------------- /fpga/lib/psmake/examples/vitis/example_app/platform_config.h: -------------------------------------------------------------------------------- 1 | #ifndef __PLATFORM_CONFIG_H_ 2 | #define __PLATFORM_CONFIG_H_ 3 | 4 | #define STDOUT_IS_PSU_UART 5 | #define UART_DEVICE_ID 1 6 | #endif 7 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_100g/cfgmclk.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for cfgmclk 2 | 3 | # Fcfgmclk is 50 MHz +/- 15%, rounding to 15 ns period 4 | create_clock -period 15 -name cfgmclk [get_pins startupe3_inst/CFGMCLK] 5 | -------------------------------------------------------------------------------- /docs/source/modules/index.rst: -------------------------------------------------------------------------------- 1 | .. _fpga_mod: 2 | 3 | ======= 4 | Modules 5 | ======= 6 | 7 | 8 | 9 | .. toctree:: 10 | :maxdepth: 1 11 | :caption: Contents: 12 | :glob: 13 | 14 | overview 15 | * 16 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/local.mk: -------------------------------------------------------------------------------- 1 | HDF ?= ../../fpga/fpga.xsa 2 | 3 | # shortcut to build PetaLinux project including boot files 4 | build-boot: 5 | $(MAKE) build 6 | $(MAKE) package-boot 7 | 8 | .PHONY: build-boot 9 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/local.mk: -------------------------------------------------------------------------------- 1 | HDF ?= ../../fpga/fpga.xsa 2 | 3 | # shortcut to build PetaLinux project including boot files 4 | build-boot: 5 | $(MAKE) build 6 | $(MAKE) package-boot 7 | 8 | .PHONY: build-boot 9 | -------------------------------------------------------------------------------- /fpga/mqnic/fb2CG/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_100g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU108/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU118/fpga_100g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU118/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/XUPP3R/fpga_100g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/XUPP3R/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/fb2CG/fpga_100g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/fb4CGg3/fpga_100g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/fb4CGg3/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/ADM_PCIE_9V3/fpga_100g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/ADM_PCIE_9V3/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/Nexus_K3P_Q/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/Nexus_K3P_S/fpga_25g/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/boot.xdc: -------------------------------------------------------------------------------- 1 | # Timing constraints for FPGA boot logic 2 | 3 | set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] 4 | set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] 5 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/attributes: -------------------------------------------------------------------------------- 1 | #Virtual Providers 2 | 3 | 4 | 5 | #defconfigs 6 | 7 | UBOOT_DEFAULT_DEFCONFIG="xilinx_zynqmp_virt_defconfig" 8 | 9 | #atf 10 | CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE="0x8000000" 11 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend: -------------------------------------------------------------------------------- 1 | SRC_URI += "file://enable_ptp.cfg\ 2 | file://enable_dsa.cfg\ 3 | " 4 | 5 | FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" 6 | 7 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/attributes: -------------------------------------------------------------------------------- 1 | #Virtual Providers 2 | 3 | 4 | 5 | #defconfigs 6 | 7 | UBOOT_DEFAULT_DEFCONFIG="xilinx_zynqmp_virt_defconfig" 8 | 9 | #atf 10 | CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE="0x8000000" 11 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/corundum/HEAD/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend: -------------------------------------------------------------------------------- 1 | SRC_URI += "file://enable_ptp.cfg\ 2 | file://enable_dsa.cfg\ 3 | " 4 | 5 | FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" 6 | 7 | -------------------------------------------------------------------------------- /docs/source/modules/rx_hash.rst: -------------------------------------------------------------------------------- 1 | .. _mod_rx_hash: 2 | 3 | =========== 4 | ``rx_hash`` 5 | =========== 6 | 7 | ``rx_hash`` implements flow hashing on the receive path. It extracts IP addresses and ports from packet headers and computes a 32-bit Toeplitz flow hash. 8 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.lxt 3 | *.pyc 4 | *.vvp 5 | *.kate-swp 6 | 7 | .* 8 | !.gitignore 9 | 10 | # Kernel 11 | *.o 12 | *.cmd 13 | *.mod 14 | *.mod.c 15 | Module.symvers 16 | modules.order 17 | *.ko 18 | 19 | # Vivado 20 | *.jou 21 | *.log 22 | *.str 23 | 24 | tags 25 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/NexysVideo/fpga/fpga/generate_bit_iodelay.tcl: -------------------------------------------------------------------------------- 1 | open_project fpga.xpr 2 | open_run impl_1 3 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 4 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 5 | write_bitstream -force fpga.bit 6 | exit 7 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/KC705/fpga_rgmii/fpga/generate_bit_iodelay.tcl: -------------------------------------------------------------------------------- 1 | open_project fpga.xpr 2 | open_run impl_1 3 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 4 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 5 | write_bitstream -force fpga.bit 6 | exit 7 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/fsbl-firmware/fsbl-firmware_%.bbappend: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # enable message level FSBL_DEBUG_DETAILED 3 | 4 | #YAML_COMPILER_FLAGS_append = " -DFSBL_DEBUG_DETAILED" 5 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/fsbl-firmware/fsbl-firmware_%.bbappend: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # enable message level FSBL_DEBUG_DETAILED 3 | 4 | #YAML_COMPILER_FLAGS_append = " -DFSBL_DEBUG_DETAILED" 5 | -------------------------------------------------------------------------------- /docs/source/modules/rx_checksum.rst: -------------------------------------------------------------------------------- 1 | .. _mod_rx_checksum: 2 | 3 | =============== 4 | ``rx_checksum`` 5 | =============== 6 | 7 | ``rx_checksum`` implements the receive checksum offloading support. It computes 16 bit checksum of Ethernet frame payload to aid in IP checksum offloading by the host network stack. 8 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU108/fpga_10g/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | set_property LOC BITSLICE_RX_TX_X1Y35 [get_cells -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/idelay_cal}] 4 | #set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_inst/RST} -include_replicated_objects ] 5 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU108/fpga_1g/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | set_property LOC BITSLICE_RX_TX_X1Y35 [get_cells -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/idelay_cal}] 4 | #set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_inst/RST} -include_replicated_objects ] 5 | -------------------------------------------------------------------------------- /docs/source/modules/desc_fetch.rst: -------------------------------------------------------------------------------- 1 | .. _mod_desc_fetch: 2 | 3 | ============== 4 | ``desc_fetch`` 5 | ============== 6 | 7 | ``desc_fetch`` manages operations associated with fetching descriptors. It is responsible for dequeuing descriptors from the queue managers and reading descriptors from host memory via DMA. 8 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/common/driver/example/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # object files to build 3 | obj-m += example.o 4 | example-objs += example_driver.o 5 | 6 | all: 7 | make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules 8 | 9 | clean: 10 | make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean 11 | 12 | -------------------------------------------------------------------------------- /fpga/app/custom_port_demo/utils/zcu102_demo.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # SPDX-License-Identifier: BSD-2-Clause-Views 3 | # Copyright (c) 2023 Missing Link Electronics, Inc. 4 | 5 | while true 6 | do 7 | for i in {0..127} 8 | do 9 | (set -x; devmem 0xa8000010 8 $i) 10 | sleep 1 11 | done 12 | done 13 | -------------------------------------------------------------------------------- /meta-corundum/conf/layer.conf: -------------------------------------------------------------------------------- 1 | BBPATH .= ":${LAYERDIR}" 2 | BBFILES += "${LAYERDIR}/recipes-*/*/*.bb ${LAYERDIR}/recipes-*/*/*.bbappend" 3 | BBFILE_COLLECTIONS += "meta-corundum" 4 | BBFILE_PATTERN_meta-corundum = "^${LAYERDIR}/" 5 | BBFILE_PRIORITY_meta-corundum = "5" 6 | LAYERSERIES_COMPAT_meta-corundum = "gatesgarth zeus" 7 | -------------------------------------------------------------------------------- /docs/source/modules/cpl_write.rst: -------------------------------------------------------------------------------- 1 | .. _mod_cpl_write: 2 | 3 | ============= 4 | ``cpl_write`` 5 | ============= 6 | 7 | ``cpl_write`` manages operations associated with completion writeback. It is responsible for enqueuing completion and event records into the completion queue managers and writing records into host memory via DMA. 8 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/config.project: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file; DO NOT EDIT. 3 | # PetaLinux SDK Project Configuration 4 | # 5 | CONFIG_PROJECT_ADDITIONAL_COMPONENTS_SEARCH_PATH="" 6 | 7 | # 8 | # Subsystems of the project 9 | # 10 | CONFIG_PROJECT_SUBSYSTEM_LINUX_INSTANCE_LINUX=y 11 | CONFIG_PROJECT_SUBSYSTEMS=y 12 | -------------------------------------------------------------------------------- /docs/source/modules/tx_checksum.rst: -------------------------------------------------------------------------------- 1 | .. _mod_tx_checksum: 2 | 3 | =============== 4 | ``tx_checksum`` 5 | =============== 6 | 7 | ``tx_checksum`` implements the transmit checksum offloading support. It computes 16 bit checksum of frame data with specified start offset, then inserts computed checksum at the position specified by the host network stack. 8 | -------------------------------------------------------------------------------- /fpga/common/tb/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: BSD-2-Clause-Views 2 | # Copyright (c) 2020-2023 The Regents of the University of California 3 | 4 | TOPTARGETS := all clean 5 | 6 | SUBDIRS := $(wildcard */.) 7 | 8 | $(TOPTARGETS): $(SUBDIRS) 9 | $(SUBDIRS): 10 | $(MAKE) -C $@ $(MAKECMDGOALS) 11 | 12 | .PHONY: $(TOPTARGETS) $(SUBDIRS) 13 | 14 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/config.project: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file; DO NOT EDIT. 3 | # PetaLinux SDK Project Configuration 4 | # 5 | CONFIG_PROJECT_ADDITIONAL_COMPONENTS_SEARCH_PATH="" 6 | 7 | # 8 | # Subsystems of the project 9 | # 10 | CONFIG_PROJECT_SUBSYSTEM_LINUX_INSTANCE_LINUX=y 11 | CONFIG_PROJECT_SUBSYSTEMS=y 12 | -------------------------------------------------------------------------------- /docs/source/contents.rst: -------------------------------------------------------------------------------- 1 | .. _contents: 2 | 3 | ======== 4 | Contents 5 | ======== 6 | 7 | .. toctree:: 8 | :numbered: 9 | :includehidden: 10 | 11 | index 12 | gettingstarted 13 | debugging 14 | tuning 15 | porting 16 | macaddr 17 | operations 18 | modules/index 19 | rb/index 20 | devicelist 21 | glossary -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile: -------------------------------------------------------------------------------- 1 | APP = gpio-demo 2 | 3 | # Add any other object files to this list below 4 | APP_OBJS = gpio-demo.o 5 | 6 | all: $(APP) 7 | 8 | $(APP): $(APP_OBJS) 9 | $(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS) 10 | 11 | clean: 12 | -rm -f $(APP) *.elf *.gdb *.o 13 | 14 | 15 | -------------------------------------------------------------------------------- /docs/source/modules/rx_engine.rst: -------------------------------------------------------------------------------- 1 | .. _mod_rx_engine: 2 | 3 | ============= 4 | ``rx_engine`` 5 | ============= 6 | 7 | ``rx_engine`` manages receive datapath operations including descriptor dequeue and fetch via DMA, packet reception, data writeback via DMA, and completion enqueue and writeback via DMA. It also handles PTP timestamps for inclusion in completion records. 8 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile: -------------------------------------------------------------------------------- 1 | APP = gpio-demo 2 | 3 | # Add any other object files to this list below 4 | APP_OBJS = gpio-demo.o 5 | 6 | all: $(APP) 7 | 8 | $(APP): $(APP_OBJS) 9 | $(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS) 10 | 11 | clean: 12 | -rm -f $(APP) *.elf *.gdb *.o 13 | 14 | 15 | -------------------------------------------------------------------------------- /.readthedocs.yaml: -------------------------------------------------------------------------------- 1 | # Read the Docs configuration file 2 | # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details 3 | 4 | version: 2 5 | 6 | build: 7 | os: ubuntu-22.04 8 | tools: 9 | python: "3.11" 10 | 11 | python: 12 | install: 13 | - requirements: docs/requirements.txt 14 | 15 | sphinx: 16 | configuration: docs/source/conf.py 17 | -------------------------------------------------------------------------------- /docs/source/modules/tx_engine.rst: -------------------------------------------------------------------------------- 1 | .. _mod_tx_engine: 2 | 3 | ============= 4 | ``tx_engine`` 5 | ============= 6 | 7 | ``tx_engine`` manages transmit datapath operations including descriptor dequeue and fetch via DMA, packet data fetch via DMA, packet transmission, and completion enqueue and writeback via DMA. It also handles PTP timestamps for inclusion in completion records. 8 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ATLYS/fpga/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_int" TNM = "ffs_clk_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_int_to_gmii_rx_clk" = FROM "ffs_clk_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_int" 10 ns; 7 | -------------------------------------------------------------------------------- /fpga/mqnic/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.MDIO_Management {false} \ 6 | CONFIG.base_kr {BASE-R} \ 7 | CONFIG.SupportLevel {1} \ 8 | CONFIG.DClkRate {125} \ 9 | ] [get_ips ten_gig_eth_pcs_pma_0] 10 | -------------------------------------------------------------------------------- /fpga/mqnic/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_1 3 | 4 | set_property -dict [list \ 5 | CONFIG.MDIO_Management {false} \ 6 | CONFIG.base_kr {BASE-R} \ 7 | CONFIG.SupportLevel {0} \ 8 | CONFIG.DClkRate {125} \ 9 | ] [get_ips ten_gig_eth_pcs_pma_1] 10 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.MDIO_Management {false} \ 6 | CONFIG.base_kr {BASE-R} \ 7 | CONFIG.SupportLevel {1} \ 8 | CONFIG.DClkRate {125} \ 9 | ] [get_ips ten_gig_eth_pcs_pma_0] 10 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_1 3 | 4 | set_property -dict [list \ 5 | CONFIG.MDIO_Management {false} \ 6 | CONFIG.base_kr {BASE-R} \ 7 | CONFIG.SupportLevel {0} \ 8 | CONFIG.DClkRate {125} \ 9 | ] [get_ips ten_gig_eth_pcs_pma_1] 10 | -------------------------------------------------------------------------------- /docs/source/modules/mqnic_egress.rst: -------------------------------------------------------------------------------- 1 | .. _mod_mqnic_egress: 2 | 3 | ================ 4 | ``mqnic_egress`` 5 | ================ 6 | 7 | ``mqnic_egress`` implements egress processing on the transmit side. This consists of: 8 | 9 | 1. Transmit checksum offloading 10 | 11 | ``mqnic_egress`` integrates the following modules: 12 | 13 | * :ref:`mod_tx_checksum`: transmit checksum offloading 14 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/user-rootfsconfig: -------------------------------------------------------------------------------- 1 | #Note: Mention Each package in individual line 2 | #These packages will get added into rootfs menu entry 3 | 4 | CONFIG_gpio-demo 5 | CONFIG_peekpoke 6 | 7 | CONFIG_iproute2-devlink 8 | CONFIG_iputils-ping 9 | CONFIG_iperf2 10 | CONFIG_linuxptp 11 | 12 | CONFIG_kernel-module-mqnic 13 | CONFIG_mqnic-tools 14 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/conf/user-rootfsconfig: -------------------------------------------------------------------------------- 1 | #Note: Mention Each package in individual line 2 | #These packages will get added into rootfs menu entry 3 | 4 | CONFIG_gpio-demo 5 | CONFIG_peekpoke 6 | 7 | CONFIG_iproute2-devlink 8 | CONFIG_iputils-ping 9 | CONFIG_iperf2 10 | CONFIG_linuxptp 11 | 12 | CONFIG_kernel-module-mqnic 13 | CONFIG_mqnic-tools 14 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/DE5-Net/fpga/cores/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | QMEGAWIZ=qmegawiz 3 | 4 | # Sources 5 | QMWSRC=phy.v 6 | QMWSRC+=phy_reconfig.v 7 | 8 | # Targets 9 | TARGETS=$(QMWSRC:.v=) 10 | 11 | # Rules 12 | .PHONY: all 13 | all: $(TARGETS) 14 | 15 | .PHONY: clean 16 | clean: 17 | -rm -rf $(TARGETS) 18 | 19 | %: %.v 20 | mkdir -p $@ 21 | cp -a $< $@ 22 | cd $@ && $(QMEGAWIZ) -silent $< 23 | 24 | -------------------------------------------------------------------------------- /fpga/build_images_project.ini: -------------------------------------------------------------------------------- 1 | [general] 2 | prefix = corundum 3 | parallel = 16 4 | synth_parallel = 8 5 | dirs = 6 | mqnic 7 | 8 | [vivado] 9 | # settings_file = /opt/Xilinx/vivado-settings 10 | 11 | [ise] 12 | # settings_file = /opt/Xilinx/ise-settings 13 | 14 | [quartus] 15 | # settings_file = /opt/altera/quartus-settings 16 | 17 | [quartus-pro] 18 | # settings_file = /opt/altera/quartus-pro-settings 19 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/RV901T/fpga/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_125mhz_int_to_gmii_rx_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_125mhz_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_125mhz_int" 10 ns; 7 | -------------------------------------------------------------------------------- /fpga/lib/psmake/examples/vitis/helloworld.patch: -------------------------------------------------------------------------------- 1 | --- a/helloworld.c 2020-09-01 11:44:33.249528296 +0200 2 | +++ b/helloworld.c~ 2020-09-01 12:02:34.945994392 +0200 3 | @@ -54,7 +54,7 @@ 4 | { 5 | init_platform(); 6 | 7 | - print("Hello World\n\r"); 8 | + print("Hello World Vitis Makefile\n\r"); 9 | print("Successfully ran Hello World application"); 10 | cleanup_platform(); 11 | return 0; 12 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ML605/fpga_gmii/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_125mhz_int_to_gmii_rx_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_125mhz_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_125mhz_int" 10 ns; 7 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ML605/fpga_rgmii/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_125mhz_int_to_gmii_rx_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_125mhz_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_125mhz_int" 10 ns; 7 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/KC705/fpga_sgmii/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {Transceiver} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | ] [get_ips gig_ethernet_pcs_pma_0] 10 | -------------------------------------------------------------------------------- /docs/source/modules/mqnic_interface_rx.rst: -------------------------------------------------------------------------------- 1 | .. _mod_mqnic_interface_rx: 2 | 3 | ====================== 4 | ``mqnic_interface_rx`` 5 | ====================== 6 | 7 | ``mqnic_interface_rx`` implements the host-side receive datapath. 8 | 9 | ``mqnic_interface_rx`` integrates the following modules: 10 | 11 | * :ref:`mod_rx_engine`: receive engine 12 | * :ref:`mod_mqnic_ingress`: ingress datapath 13 | * ``dma_client_axis_sink``: internal DMA engine 14 | -------------------------------------------------------------------------------- /docs/source/modules/mqnic_interface_tx.rst: -------------------------------------------------------------------------------- 1 | .. _mod_mqnic_interface_tx: 2 | 3 | ====================== 4 | ``mqnic_interface_tx`` 5 | ====================== 6 | 7 | ``mqnic_interface_tx`` implements the host-side transmit datapath. 8 | 9 | ``mqnic_interface_tx`` integrates the following modules: 10 | 11 | * :ref:`mod_tx_engine`: transmit engine 12 | * ``dma_client_axis_source``: internal DMA engine 13 | * :ref:`mod_mqnic_egress`: egress datapath 14 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | ] [get_ips gig_ethernet_pcs_pma_0] 11 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | ] [get_ips gig_ethernet_pcs_pma_0] 11 | -------------------------------------------------------------------------------- /meta-corundum/recipes-modules/kernel-module-mqnic/kernel-module-mqnic.bb: -------------------------------------------------------------------------------- 1 | SUMMARY = "Corundum mqnic driver kernel module" 2 | SECTION = "kernel" 3 | LICENSE = "MIT & GPLv2" 4 | LIC_FILES_CHKSUM = " \ 5 | file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302 \ 6 | file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6" 7 | 8 | inherit module 9 | 10 | SRC_URI = " \ 11 | file://mqnic \ 12 | " 13 | 14 | S = "${WORKDIR}/mqnic" 15 | -------------------------------------------------------------------------------- /docs/source/modules/mqnic_ingress.rst: -------------------------------------------------------------------------------- 1 | .. _mod_mqnic_ingress: 2 | 3 | ================= 4 | ``mqnic_ingress`` 5 | ================= 6 | 7 | ``mqnic_ingress`` implements ingress processing on the receive path. This consists of: 8 | 9 | 1. Receive checksum offloading 10 | 2. RSS flow hashing 11 | 12 | ``mqnic_ingress`` integrates the following modules: 13 | 14 | * :ref:`mod_rx_checksum`: receive checksum offloading 15 | * :ref:`mod_rx_hash`: RSS flow hash computation 16 | -------------------------------------------------------------------------------- /fpga/lib/pcie/scripts/pcie_flr.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | 5 | if [ -z "$dev" ]; then 6 | echo "Error: no device specified" 7 | exit 1 8 | fi 9 | 10 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 11 | dev="0000:$dev" 12 | fi 13 | 14 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 15 | echo "Error: device $dev not found" 16 | exit 1 17 | fi 18 | 19 | echo "Resetting function $dev..." 20 | 21 | echo 1 > "/sys/bus/pci/devices/$dev/reset" 22 | 23 | 24 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/layer.conf: -------------------------------------------------------------------------------- 1 | # We have a conf and classes directory, add to BBPATH 2 | BBPATH .= ":${LAYERDIR}" 3 | 4 | # We have recipes-* directories, add to BBFILES 5 | BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ 6 | ${LAYERDIR}/recipes-*/*/*.bbappend" 7 | 8 | BBFILE_COLLECTIONS += "meta-user" 9 | BBFILE_PATTERN_meta-user = "^${LAYERDIR}/" 10 | BBFILE_PRIORITY_meta-user = "7" 11 | LAYERSERIES_COMPAT_meta-user = "gatesgarth zeus" 12 | -------------------------------------------------------------------------------- /fpga/lib/psmake/examples/xsdk/helloworld.patch: -------------------------------------------------------------------------------- 1 | --- a/helloworld.c 2020-05-13 11:53:50.934001488 +0200 2 | +++ b/helloworld.c~ 2020-05-13 14:19:33.378515155 +0200 3 | @@ -48,13 +48,14 @@ 4 | #include 5 | #include "platform.h" 6 | #include "xil_printf.h" 7 | +#include "helloworldlib.h" 8 | 9 | 10 | int main() 11 | { 12 | init_platform(); 13 | 14 | - print("Hello World\n\r"); 15 | + helloworld(); 16 | 17 | cleanup_platform(); 18 | return 0; 19 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/conf/layer.conf: -------------------------------------------------------------------------------- 1 | # We have a conf and classes directory, add to BBPATH 2 | BBPATH .= ":${LAYERDIR}" 3 | 4 | # We have recipes-* directories, add to BBFILES 5 | BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ 6 | ${LAYERDIR}/recipes-*/*/*.bbappend" 7 | 8 | BBFILE_COLLECTIONS += "meta-user" 9 | BBFILE_PATTERN_meta-user = "^${LAYERDIR}/" 10 | BBFILE_PRIORITY_meta-user = "7" 11 | LAYERSERIES_COMPAT_meta-user = "gatesgarth zeus" 12 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile: -------------------------------------------------------------------------------- 1 | PEEK = peek 2 | POKE = poke 3 | 4 | # Add any other object files to this list below 5 | PEEK_OBJS = peek.o 6 | POKE_OBJS = poke.o 7 | 8 | all: $(PEEK) $(POKE) 9 | 10 | $(POKE): $(POKE_OBJS) 11 | $(CC) $(LDFLAGS) -o $@ $(POKE_OBJS) $(LDLIBS) 12 | 13 | $(PEEK): $(PEEK_OBJS) 14 | $(CC) $(LDFLAGS) -o $@ $(PEEK_OBJS) $(LDLIBS) 15 | 16 | clean: 17 | -rm -f $(POKE) $(PEEK) *.elf *.gdb *.o 18 | 19 | 20 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile: -------------------------------------------------------------------------------- 1 | PEEK = peek 2 | POKE = poke 3 | 4 | # Add any other object files to this list below 5 | PEEK_OBJS = peek.o 6 | POKE_OBJS = poke.o 7 | 8 | all: $(PEEK) $(POKE) 9 | 10 | $(POKE): $(POKE_OBJS) 11 | $(CC) $(LDFLAGS) -o $@ $(POKE_OBJS) $(LDLIBS) 12 | 13 | $(PEEK): $(PEEK_OBJS) 14 | $(CC) $(LDFLAGS) -o $@ $(PEEK_OBJS) $(LDLIBS) 15 | 16 | clean: 17 | -rm -f $(POKE) $(PEEK) *.elf *.gdb *.o 18 | 19 | 20 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/C10LP/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/DE2-115/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/DE5-Net/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = cores fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/S10DX_DK/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_100g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU108/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU118/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/fb2CG/fpga_100g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/fb2CG/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ATLYS/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/Arty/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/scripts/pcie_reset.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | 5 | if [ -z "$dev" ]; then 6 | echo "Error: no device specified" 7 | exit 1 8 | fi 9 | 10 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 11 | dev="0000:$dev" 12 | fi 13 | 14 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 15 | echo "Error: device $dev not found" 16 | exit 1 17 | fi 18 | 19 | echo "Removing $dev..." 20 | 21 | echo 1 > "/sys/bus/pci/devices/$dev/remove" 22 | 23 | echo "Rescanning bus..." 24 | 25 | echo 1 > "/sys/bus/pci/rescan" 26 | 27 | 28 | -------------------------------------------------------------------------------- /fpga/mqnic/NetFPGA_SUME/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU118/fpga_100g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_pcie/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/Alveo/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ExaNIC_X10/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/KC705/fpga_gmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ML605/fpga_gmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/NexysVideo/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU108/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU108/fpga_1g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU118/fpga_1g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU118/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ZCU102/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ZCU106/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/fb2CG/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU200/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU250/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU280/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU50/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/fb2CG/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/ADM_PCIE_9V3/fpga_100g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/mqnic/ADM_PCIE_9V3/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ExaNIC_X25/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG640/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = coregen fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/KC705/fpga_rgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/KC705/fpga_sgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ML605/fpga_rgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/NetFPGA_SUME/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU108/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU118/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU1525/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ZCU106/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/fb2CG/fpga/led.tcl: -------------------------------------------------------------------------------- 1 | # Timing constraints for led_sreg_driver 2 | 3 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { 4 | puts "Inserting timing constraints for led_sreg_driver instance $inst" 5 | 6 | set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] 7 | 8 | if {[llength $select_ffs]} { 9 | set_property ASYNC_REG TRUE $select_ffs 10 | set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /utils/drp.h: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSD-2-Clause-Views 2 | /* 3 | * Copyright (c) 2022-2023 The Regents of the University of California 4 | */ 5 | 6 | #ifndef DRP_H 7 | #define DRP_H 8 | 9 | #include 10 | #include 11 | 12 | int drp_rb_reg_read(const struct mqnic_reg_block *rb, uint32_t addr, uint32_t *val); 13 | int drp_rb_reg_write(const struct mqnic_reg_block *rb, uint32_t addr, uint32_t val); 14 | 15 | void drp_rb_reg_if_init(struct mqnic_reg_if *reg, struct mqnic_reg_block *rb); 16 | 17 | #endif /* DRP_H */ 18 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ML605/fpga_sgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = coregen fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/fb2CG/fpga_25g/led.tcl: -------------------------------------------------------------------------------- 1 | # Timing constraints for led_sreg_driver 2 | 3 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { 4 | puts "Inserting timing constraints for led_sreg_driver instance $inst" 5 | 6 | set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] 7 | 8 | if {[llength $select_ffs]} { 9 | set_property ASYNC_REG TRUE $select_ffs 10 | set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/fb2CG/fpga_axi/led.tcl: -------------------------------------------------------------------------------- 1 | # Timing constraints for led_sreg_driver 2 | 3 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { 4 | puts "Inserting timing constraints for led_sreg_driver instance $inst" 5 | 6 | set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] 7 | 8 | if {[llength $select_ffs]} { 9 | set_property ASYNC_REG TRUE $select_ffs 10 | set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG640/fpga_cxpt16/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = coregen fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ 11 | CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ 12 | CONFIG.Tx_In_Upper_Nibble {0} \ 13 | ] [get_ips gig_ethernet_pcs_pma_0] 14 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ 11 | CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ 12 | CONFIG.Tx_In_Upper_Nibble {0} \ 13 | ] [get_ips gig_ethernet_pcs_pma_0] 14 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ 11 | CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ 12 | CONFIG.Tx_In_Upper_Nibble {0} \ 13 | ] [get_ips gig_ethernet_pcs_pma_0] 14 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/enable_ptp.cfg: -------------------------------------------------------------------------------- 1 | CONFIG_NET_PTP_CLASSIFY=y 2 | CONFIG_MACB_USE_HWSTAMP=y 3 | # CONFIG_CAVIUM_PTP is not set 4 | CONFIG_PPS=m 5 | # CONFIG_PPS_DEBUG is not set 6 | 7 | # 8 | # PPS clients support 9 | # 10 | # CONFIG_PPS_CLIENT_KTIMER is not set 11 | # CONFIG_PPS_CLIENT_LDISC is not set 12 | # CONFIG_PPS_CLIENT_GPIO is not set 13 | 14 | # 15 | # PPS generators support 16 | # 17 | CONFIG_PTP_1588_CLOCK=m 18 | # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set 19 | # CONFIG_PTP_1588_CLOCK_IDTCM is not set 20 | # CONFIG_PTP_1588_CLOCK_XILINX is not set 21 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/enable_ptp.cfg: -------------------------------------------------------------------------------- 1 | CONFIG_NET_PTP_CLASSIFY=y 2 | CONFIG_MACB_USE_HWSTAMP=y 3 | # CONFIG_CAVIUM_PTP is not set 4 | CONFIG_PPS=m 5 | # CONFIG_PPS_DEBUG is not set 6 | 7 | # 8 | # PPS clients support 9 | # 10 | # CONFIG_PPS_CLIENT_KTIMER is not set 11 | # CONFIG_PPS_CLIENT_LDISC is not set 12 | # CONFIG_PPS_CLIENT_GPIO is not set 13 | 14 | # 15 | # PPS generators support 16 | # 17 | CONFIG_PTP_1588_CLOCK=m 18 | # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set 19 | # CONFIG_PTP_1588_CLOCK_IDTCM is not set 20 | # CONFIG_PTP_1588_CLOCK_XILINX is not set 21 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG640/fpga/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Wed Apr 1 17:38:18 2015 2 | 3 | SET addpads = false 4 | SET asysymbol = true 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = false 7 | SET designentry = Verilog 8 | SET device = xc6vhx565t 9 | SET devicefamily = virtex6 10 | SET flowvendor = Other 11 | SET formalverification = false 12 | SET foundationsym = false 13 | SET implementationfiletype = Ngc 14 | SET package = ff1923 15 | SET removerpms = false 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -2 18 | SET verilogsim = true 19 | SET vhdlsim = false 20 | SET workingdirectory = ./tmp/ 21 | 22 | # CRC: 3d2f7d04 23 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:" 2 | 3 | SRC_URI += "file://platform-top.h" 4 | 5 | do_configure_append () { 6 | if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then 7 | install ${WORKDIR}/platform-auto.h ${S}/include/configs/ 8 | install ${WORKDIR}/platform-top.h ${S}/include/configs/ 9 | fi 10 | } 11 | 12 | do_configure_append_microblaze () { 13 | if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then 14 | install -d ${B}/source/board/xilinx/microblaze-generic/ 15 | install ${WORKDIR}/config.mk ${B}/source/board/xilinx/microblaze-generic/ 16 | fi 17 | } 18 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ML605/fpga_sgmii/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Wed Jun 21 16:05:33 2017 2 | 3 | SET addpads = false 4 | SET asysymbol = true 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = false 7 | SET designentry = Verilog 8 | SET device = xc6vlx130t 9 | SET devicefamily = virtex6 10 | SET flowvendor = Other 11 | SET formalverification = false 12 | SET foundationsym = false 13 | SET implementationfiletype = Ngc 14 | SET package = ff1156 15 | SET removerpms = false 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -1 18 | SET verilogsim = true 19 | SET vhdlsim = false 20 | SET workingdirectory = ./tmp/ 21 | 22 | # CRC: 2db0eed3 23 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_25g/ip/cms.tcl: -------------------------------------------------------------------------------- 1 | 2 | # create block design 3 | create_bd_design "cms" 4 | 5 | # create CMS IP 6 | set cms_block [create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem cms_subsystem_0] 7 | make_bd_pins_external $cms_block 8 | make_bd_intf_pins_external $cms_block 9 | 10 | # assign addresses 11 | assign_bd_address -target_address_space /s_axi_ctrl_0 [get_bd_addr_segs $cms_block/s_axi_ctrl/Mem0] -force 12 | 13 | # save block design and create HDL wrapper 14 | save_bd_design [current_bd_design] 15 | add_files -norecurse [make_wrapper -files [get_files [get_property FILE_NAME [current_bd_design]]] -top] 16 | close_bd_design [current_bd_design] 17 | -------------------------------------------------------------------------------- /meta-corundum/recipes-devtools/mqnic-tools/mqnic-tools.bb: -------------------------------------------------------------------------------- 1 | SUMMARY = "Corundum mqnic driver support tools" 2 | SECTION = "devel" 3 | LICENSE = "MIT & GPLv2" 4 | LIC_FILES_CHKSUM = " \ 5 | file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302 \ 6 | file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6" 7 | 8 | SRC_URI = " \ 9 | file://utils \ 10 | file://include \ 11 | file://lib \ 12 | file://modules \ 13 | " 14 | 15 | S = "${WORKDIR}/utils" 16 | 17 | do_compile() { 18 | make 19 | } 20 | 21 | do_install() { 22 | # NOTE: Makefile currently defaults to PREFIX=/usr/local ! 23 | make DESTDIR=${D} PREFIX=/usr install 24 | } 25 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Wed Apr 1 17:38:18 2015 2 | 3 | SET addpads = false 4 | SET asysymbol = true 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = false 7 | SET designentry = Verilog 8 | SET device = xc6vhx565t 9 | SET devicefamily = virtex6 10 | SET flowvendor = Other 11 | SET formalverification = false 12 | SET foundationsym = false 13 | SET implementationfiletype = Ngc 14 | SET package = ff1923 15 | SET removerpms = false 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -2 18 | SET verilogsim = true 19 | SET vhdlsim = false 20 | SET workingdirectory = ./tmp/ 21 | 22 | # CRC: 3d2f7d04 23 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_100g/ip/cms.tcl: -------------------------------------------------------------------------------- 1 | 2 | # create block design 3 | create_bd_design "cms" 4 | 5 | # create CMS IP 6 | set cms_block [create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem cms_subsystem_0] 7 | make_bd_pins_external $cms_block 8 | make_bd_intf_pins_external $cms_block 9 | 10 | # assign addresses 11 | assign_bd_address -target_address_space /s_axi_ctrl_0 [get_bd_addr_segs $cms_block/s_axi_ctrl/Mem0] -force 12 | 13 | # save block design and create HDL wrapper 14 | save_bd_design [current_bd_design] 15 | add_files -norecurse [make_wrapper -files [get_files [get_property FILE_NAME [current_bd_design]]] -top] 16 | close_bd_design [current_bd_design] 17 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb: -------------------------------------------------------------------------------- 1 | # 2 | # This is the GPIO-DEMO apllication recipe 3 | # 4 | # 5 | 6 | SUMMARY = "gpio-demo application" 7 | SECTION = "PETALINUX/apps" 8 | LICENSE = "MIT" 9 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" 10 | SRC_URI = "file://gpio-demo.c \ 11 | file://Makefile \ 12 | " 13 | S = "${WORKDIR}" 14 | CFLAGS_prepend = "-I ${S}/include" 15 | do_compile() { 16 | oe_runmake 17 | } 18 | do_install() { 19 | install -d ${D}${bindir} 20 | install -m 0755 ${S}/gpio-demo ${D}${bindir} 21 | 22 | } 23 | 24 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:" 2 | 3 | SRC_URI += "file://platform-top.h" 4 | 5 | do_configure_append () { 6 | if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then 7 | install ${WORKDIR}/platform-auto.h ${S}/include/configs/ 8 | install ${WORKDIR}/platform-top.h ${S}/include/configs/ 9 | fi 10 | } 11 | 12 | do_configure_append_microblaze () { 13 | if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then 14 | install -d ${B}/source/board/xilinx/microblaze-generic/ 15 | install ${WORKDIR}/config.mk ${B}/source/board/xilinx/microblaze-generic/ 16 | fi 17 | } 18 | -------------------------------------------------------------------------------- /fpga/lib/axi/tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.24 21 | jinja2 == 3.1.2 22 | 23 | commands = 24 | pytest {posargs:-n auto --verbose} 25 | 26 | # pytest configuration 27 | [pytest] 28 | testpaths = 29 | tb 30 | addopts = 31 | --ignore-glob=tb/test_*.py 32 | --import-mode importlib 33 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb: -------------------------------------------------------------------------------- 1 | # 2 | # This is the GPIO-DEMO apllication recipe 3 | # 4 | # 5 | 6 | SUMMARY = "gpio-demo application" 7 | SECTION = "PETALINUX/apps" 8 | LICENSE = "MIT" 9 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" 10 | SRC_URI = "file://gpio-demo.c \ 11 | file://Makefile \ 12 | " 13 | S = "${WORKDIR}" 14 | CFLAGS_prepend = "-I ${S}/include" 15 | do_compile() { 16 | oe_runmake 17 | } 18 | do_install() { 19 | install -d ${D}${bindir} 20 | install -m 0755 ${S}/gpio-demo ${D}${bindir} 21 | 22 | } 23 | 24 | -------------------------------------------------------------------------------- /fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/mac_100g.sdc: -------------------------------------------------------------------------------- 1 | # E-Tile MACs 2 | proc constrain_etile_mac { inst } { 3 | puts "Inserting timing constraints for MAC $inst" 4 | 5 | set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ] 6 | set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ] 7 | 8 | constrain_sync_reset_inst "$inst|.mac_reset_sync_inst" 9 | } 10 | 11 | constrain_etile_mac "qsfp1_mac_inst" 12 | constrain_etile_mac "qsfp2_mac_inst" 13 | -------------------------------------------------------------------------------- /fpga/lib/eth/lib/axis/tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.20 21 | jinja2 == 3.1.2 22 | 23 | commands = 24 | pytest {posargs:-n auto --verbose} 25 | 26 | # pytest configuration 27 | [pytest] 28 | testpaths = 29 | tb 30 | addopts = 31 | --ignore-glob=tb/test_*.py 32 | --import-mode importlib 33 | -------------------------------------------------------------------------------- /utils/bitfile.h: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSD-2-Clause-Views 2 | /* 3 | * Copyright (c) 2020-2023 The Regents of the University of California 4 | */ 5 | 6 | #ifndef BITFILE_H 7 | #define BITFILE_H 8 | 9 | struct bitfile { 10 | char *header; 11 | char *name; 12 | char *part; 13 | char *date; 14 | char *time; 15 | 16 | size_t data_len; 17 | char *data; 18 | }; 19 | 20 | struct bitfile *bitfile_create_from_file(const char *bit_file_name); 21 | 22 | struct bitfile *bitfile_create_from_buffer(char *buffer, size_t len); 23 | 24 | int bitfile_parse(struct bitfile *bf, char *buffer, size_t len); 25 | 26 | void bitfile_close(struct bitfile *bf); 27 | 28 | #endif // BITFILE_H 29 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | # Put it first so that "make" without argument is like "make help". 12 | help: 13 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 14 | 15 | .PHONY: help Makefile 16 | 17 | # Catch-all target: route all unknown targets to Sphinx using the new 18 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 19 | %: Makefile 20 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 21 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" 2 | 3 | SRC_URI_append = " file://config file://system-user.dtsi" 4 | 5 | python () { 6 | if d.getVar("CONFIG_DISABLE"): 7 | d.setVarFlag("do_configure", "noexec", "1") 8 | } 9 | 10 | export PETALINUX 11 | do_configure_append () { 12 | script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" 13 | data=${PETALINUX}/etc/hsm/data/ 14 | eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ 15 | -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ 16 | -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" 17 | } 18 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" 2 | 3 | SRC_URI_append = " file://config file://system-user.dtsi" 4 | 5 | python () { 6 | if d.getVar("CONFIG_DISABLE"): 7 | d.setVarFlag("do_configure", "noexec", "1") 8 | } 9 | 10 | export PETALINUX 11 | do_configure_append () { 12 | script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" 13 | data=${PETALINUX}/etc/hsm/data/ 14 | eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ 15 | -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ 16 | -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" 17 | } 18 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb: -------------------------------------------------------------------------------- 1 | # 2 | # This is the peekpoke apllication recipe 3 | # 4 | # 5 | 6 | SUMMARY = "peekpoke application" 7 | SECTION = "PETALINUX/apps" 8 | LICENSE = "MIT" 9 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" 10 | SRC_URI = "file://peek.c \ 11 | file://poke.c \ 12 | file://Makefile \ 13 | " 14 | S = "${WORKDIR}" 15 | CFLAGS_prepend = "-I ${S}/include" 16 | do_compile() { 17 | oe_runmake 18 | } 19 | do_install() { 20 | install -d ${D}${bindir} 21 | install -m 0755 ${S}/peek ${D}${bindir} 22 | install -m 0755 ${S}/poke ${D}${bindir} 23 | 24 | } 25 | 26 | -------------------------------------------------------------------------------- /fpga/mqnic/XUPP3R/fpga_100g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {9996} \ 11 | CONFIG.C0.DDR4_MemoryType {RDIMMs} \ 12 | CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ 13 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 14 | CONFIG.C0.DDR4_CasLatency {17} \ 15 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 16 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 17 | ] [get_ips ddr4_0] 18 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb: -------------------------------------------------------------------------------- 1 | # 2 | # This is the peekpoke apllication recipe 3 | # 4 | # 5 | 6 | SUMMARY = "peekpoke application" 7 | SECTION = "PETALINUX/apps" 8 | LICENSE = "MIT" 9 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" 10 | SRC_URI = "file://peek.c \ 11 | file://poke.c \ 12 | file://Makefile \ 13 | " 14 | S = "${WORKDIR}" 15 | CFLAGS_prepend = "-I ${S}/include" 16 | do_compile() { 17 | oe_runmake 18 | } 19 | do_install() { 20 | install -d ${D}${bindir} 21 | install -m 0755 ${S}/peek ${D}${bindir} 22 | install -m 0755 ${S}/poke ${D}${bindir} 23 | 24 | } 25 | 26 | -------------------------------------------------------------------------------- /fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0_xupp3r.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {9996} \ 11 | CONFIG.C0.DDR4_MemoryType {RDIMMs} \ 12 | CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ 13 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 14 | CONFIG.C0.DDR4_CasLatency {17} \ 15 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 16 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 17 | ] [get_ips ddr4_0] 18 | -------------------------------------------------------------------------------- /lib/mqnic/reg_block.h: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSD-2-Clause-Views 2 | /* 3 | * Copyright (c) 2021-2023 The Regents of the University of California 4 | */ 5 | 6 | #ifndef REG_BLOCK_H 7 | #define REG_BLOCK_H 8 | 9 | #include 10 | #include 11 | 12 | struct mqnic_reg_block { 13 | uint32_t type; 14 | uint32_t version; 15 | volatile uint8_t *base; 16 | volatile uint8_t *regs; 17 | }; 18 | 19 | struct mqnic_reg_block *mqnic_enumerate_reg_block_list(volatile uint8_t *base, size_t offset, size_t size); 20 | struct mqnic_reg_block *mqnic_find_reg_block(struct mqnic_reg_block *list, uint32_t type, uint32_t version, int index); 21 | void mqnic_free_reg_block_list(struct mqnic_reg_block *list); 22 | 23 | #endif /* REG_BLOCK_H */ 24 | -------------------------------------------------------------------------------- /tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.24 21 | cocotbext-eth == 0.1.22 22 | cocotbext-pcie == 0.2.14 23 | scapy == 2.5.0 24 | 25 | commands = 26 | pytest {posargs:-n auto --verbose} 27 | 28 | # pytest configuration 29 | [pytest] 30 | testpaths = 31 | fpga 32 | fpga/app 33 | norecursedirs = 34 | lib 35 | app 36 | addopts = 37 | --import-mode=importlib 38 | -------------------------------------------------------------------------------- /fpga/lib/pcie/tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.24 21 | cocotbext-pcie == 0.2.14 22 | jinja2 == 3.1.2 23 | 24 | commands = 25 | pytest {posargs:-n auto --verbose} 26 | 27 | # pytest configuration 28 | [pytest] 29 | testpaths = 30 | tb 31 | example 32 | norecursedirs = 33 | lib 34 | addopts = 35 | --ignore-glob=tb/test_*.py 36 | --import-mode importlib 37 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" 2 | 3 | SRC_URI_append = " file://config file://system-user.dtsi" 4 | 5 | python () { 6 | if d.getVar("CONFIG_DISABLE"): 7 | d.setVarFlag("do_configure", "noexec", "1") 8 | } 9 | export PETALINUX 10 | do_configure_append () { 11 | script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" 12 | data=${PETALINUX}/etc/hsm/data/ 13 | eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ 14 | -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ 15 | -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" 16 | } 17 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" 2 | 3 | SRC_URI_append = " file://config file://system-user.dtsi" 4 | 5 | python () { 6 | if d.getVar("CONFIG_DISABLE"): 7 | d.setVarFlag("do_configure", "noexec", "1") 8 | } 9 | export PETALINUX 10 | do_configure_append () { 11 | script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" 12 | data=${PETALINUX}/etc/hsm/data/ 13 | eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ 14 | -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ 15 | -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" 16 | } 17 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/ML605/fpga_sgmii/coregen/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | COREGEN:=coregen 3 | XAW2VERILOG:=xaw2verilog 4 | 5 | # Source 6 | XCO:=gig_eth_pcs_pma_v11_5.xco 7 | XAW:= 8 | 9 | # Targets 10 | TARGETS += $(XCO:.xco=) 11 | TARGETS += $(XAW:.xaw=) 12 | 13 | # Rules 14 | .PHONY: all 15 | all: $(TARGETS) 16 | 17 | .PHONY: clean 18 | clean: 19 | -rm -rf $(TARGETS) 20 | 21 | %: %.xco 22 | $(eval $@_TMP := $(shell mktemp -d)) 23 | cp -a coregen.cgp $($@_TMP) 24 | cp -a $< $($@_TMP) 25 | cd $($@_TMP) && $(COREGEN) -p coregen.cgp -b $(notdir $<) 26 | mv $($@_TMP) $@ 27 | 28 | %: %.xaw 29 | $(eval $@_TMP := $(shell mktemp -d)) 30 | cp -a coregen.cgp $($@_TMP) 31 | cp -a $< $($@_TMP) 32 | cd $($@_TMP) && $(XAW2VERILOG) -st $(notdir $<) $(notdir $*) 33 | mv $($@_TMP) $@ 34 | -------------------------------------------------------------------------------- /fpga/lib/eth/tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.20 21 | cocotbext-eth == 0.1.22 22 | scapy == 2.5.0 23 | jinja2 == 3.1.2 24 | 25 | commands = 26 | pytest {posargs:-n auto --verbose} 27 | 28 | # pytest configuration 29 | [pytest] 30 | testpaths = 31 | tb 32 | example 33 | norecursedirs = 34 | lib 35 | addopts = 36 | --ignore-glob=tb/test_*.py 37 | --import-mode importlib 38 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/.gitignore: -------------------------------------------------------------------------------- 1 | */*/config.old 2 | */*/rootfs_config.old 3 | build/ 4 | images/linux/ 5 | pre-built/linux/ 6 | .petalinux/* 7 | # NOTE: At least since v2020.2 .petalinux/metadata may contain an absolute path 8 | # of the last imported .xsa file! Plus various MD5 sums. Not good for VCS! 9 | # Apparently, the file is NOT needed anymore (re-created on each build instead). 10 | # However the directory .petalinux/ has to exists. 11 | #!.petalinux/metadata 12 | !.petalinux/.gitkeep 13 | *.o 14 | *.jou 15 | *.log 16 | /components/plnx_workspace 17 | /components/yocto 18 | 19 | 20 | # skip any generated .xsa-related files 21 | /project-spec/hw-description/* 22 | !/project-spec/hw-description/metadata 23 | 24 | # Xilinx toolchain intermediate files 25 | /.Xil/ 26 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_100g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.System_Clock {No_Buffer} \ 6 | CONFIG.C0.DDR4_AxiSelection {true} \ 7 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 8 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 9 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 10 | CONFIG.C0.DDR4_TimePeriod {833} \ 11 | CONFIG.C0.DDR4_InputClockPeriod {3332} \ 12 | CONFIG.C0.DDR4_MemoryType {RDIMMs} \ 13 | CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {17} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_0] 19 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_25g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.System_Clock {No_Buffer} \ 6 | CONFIG.C0.DDR4_AxiSelection {true} \ 7 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 8 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 9 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 10 | CONFIG.C0.DDR4_TimePeriod {833} \ 11 | CONFIG.C0.DDR4_InputClockPeriod {3332} \ 12 | CONFIG.C0.DDR4_MemoryType {RDIMMs} \ 13 | CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {17} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_0] 19 | -------------------------------------------------------------------------------- /fpga/mqnic/IA_420F/fpga_100g/mac_100g.sdc: -------------------------------------------------------------------------------- 1 | # E-Tile MACs 2 | proc constrain_etile_mac_dual { inst } { 3 | puts "Inserting timing constraints for MAC dual $inst" 4 | 5 | foreach mac {mac_02_inst mac_13_inst} { 6 | set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] 7 | set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] 8 | } 9 | 10 | for {set i 0} {$i < 2} {incr i} { 11 | constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst" 12 | } 13 | } 14 | 15 | constrain_etile_mac_dual "qsfp_mac_inst" 16 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/.gitignore: -------------------------------------------------------------------------------- 1 | */*/config.old 2 | */*/rootfs_config.old 3 | build/ 4 | images/linux/ 5 | pre-built/linux/ 6 | .petalinux/* 7 | # NOTE: At least since v2020.2 .petalinux/metadata may contain an absolute path 8 | # of the last imported .xsa file! Plus various MD5 sums. Not good for VCS! 9 | # Apparently, the file is NOT needed anymore (re-created on each build instead). 10 | # However the directory .petalinux/ has to exists. 11 | #!.petalinux/metadata 12 | !.petalinux/.gitkeep 13 | *.o 14 | *.jou 15 | *.log 16 | /components/plnx_workspace 17 | /components/yocto 18 | 19 | 20 | # skip any generated .xsa-related files 21 | /project-spec/hw-description/* 22 | !/project-spec/hw-description/metadata 23 | 24 | # Xilinx toolchain intermediate files 25 | /.Xil/ 26 | -------------------------------------------------------------------------------- /fpga/mqnic/fb4CGg3/fpga_25g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {3750} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E} \ 13 | CONFIG.C0.DDR4_DataWidth {64} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {16} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_0] 19 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_100g/ip/ddr4_0_au280.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.System_Clock {No_Buffer} \ 6 | CONFIG.C0.DDR4_AxiSelection {true} \ 7 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 8 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 9 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 10 | CONFIG.C0.DDR4_TimePeriod {833} \ 11 | CONFIG.C0.DDR4_InputClockPeriod {9996} \ 12 | CONFIG.C0.DDR4_MemoryType {RDIMMs} \ 13 | CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {17} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_0] 19 | -------------------------------------------------------------------------------- /fpga/mqnic/Alveo/fpga_25g/ip/ddr4_0_au280.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.System_Clock {No_Buffer} \ 6 | CONFIG.C0.DDR4_AxiSelection {true} \ 7 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 8 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 9 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 10 | CONFIG.C0.DDR4_TimePeriod {833} \ 11 | CONFIG.C0.DDR4_InputClockPeriod {9996} \ 12 | CONFIG.C0.DDR4_MemoryType {RDIMMs} \ 13 | CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {17} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_0] 19 | -------------------------------------------------------------------------------- /fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0_xusp3s.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {9996} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A512M8HX-083} \ 13 | CONFIG.C0.DDR4_DataWidth {72} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {17} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_0] 19 | -------------------------------------------------------------------------------- /fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {3750} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E} \ 13 | CONFIG.C0.DDR4_DataWidth {64} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {16} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_0] 19 | -------------------------------------------------------------------------------- /scripts/mqnic_ddcmd.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | module=mqnic 4 | 5 | control=/proc/dynamic_debug/control 6 | 7 | if ! test -f $control; then 8 | control=/sys/kernel/debug/dynamic_debug/control 9 | fi 10 | 11 | if ! test -f $control; then 12 | >&2 echo "Error: dynamic debug control file not found" 13 | exit 1 14 | fi 15 | 16 | if [ $# -eq 0 ]; then 17 | >&2 echo "Error: no argument provided" 18 | >&2 echo "usage: $0 [stmt]" 19 | >&2 echo "Disable all debug print statements: $0 =_" 20 | >&2 echo "Enable all debug print statements: $0 =p" 21 | >&2 echo "More verbose: $0 =pflmt" 22 | >&2 echo "Pattern match: $0 format \"some-string\" =p" 23 | >&2 echo "Current configuration:" 24 | grep "\[$module\]" $control >&2 25 | exit 1 26 | fi 27 | 28 | echo module $module "${@@Q}" > $control 29 | 30 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU108/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU108 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU108 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu095-ffva2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the VCU108 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU118/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU118 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu9p-flga2104-2L-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the VCU118 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ZCU106/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ZCU106 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU106 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xczu7ev-ffvc1156-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ZCU106 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_sodimm_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_sodimm_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {3750} \ 11 | CONFIG.C0.DDR4_MemoryType {SODIMMs} \ 12 | CONFIG.C0.DDR4_MemoryPart {MTA8ATF1G64HZ-2G3} \ 13 | CONFIG.C0.DDR4_DataWidth {64} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {17} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_sodimm_0] 19 | -------------------------------------------------------------------------------- /fpga/mqnic/fb4CGg3/fpga_25g/ip/ddr4_sodimm_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_sodimm_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {3750} \ 11 | CONFIG.C0.DDR4_MemoryType {SODIMMs} \ 12 | CONFIG.C0.DDR4_MemoryPart {MTA8ATF1G64HZ-2G3} \ 13 | CONFIG.C0.DDR4_DataWidth {64} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {17} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_sodimm_0] 19 | -------------------------------------------------------------------------------- /docs/source/modules/mqnic_interface.rst: -------------------------------------------------------------------------------- 1 | .. _mod_mqnic_interface: 2 | 3 | =================== 4 | ``mqnic_interface`` 5 | =================== 6 | 7 | ``mqnic_interface`` implements one NIC interface, including the queue management logic, descriptor, completion, and event handling, transmit scheduler, and the transmit and receive datapaths. 8 | 9 | ``mqnic_interface`` integrates the following modules: 10 | 11 | * :ref:`mod_queue_manager`: transmit and receive queues 12 | * :ref:`mod_cpl_queue_manager`: transmit and receive completion queues, event queues 13 | * :ref:`mod_desc_fetch`: descriptor fetch 14 | * :ref:`mod_cpl_write`: completion write 15 | * :ref:`mod_mqnic_tx_scheduler_block`: transmit scheduler 16 | * :ref:`mod_mqnic_interface_rx`: receive datapath 17 | * :ref:`mod_mqnic_interface_tx`: transmit datapath 18 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU50/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U50 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U50 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu50-fsvh2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U50 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU1525/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU1525 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU1525 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu9p-fsgd2104-2L-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the VCU1525 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_sodimm_0_xusp3s.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_sodimm_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {1072} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {10004} \ 11 | CONFIG.C0.DDR4_MemoryType {SODIMMs} \ 12 | CONFIG.C0.DDR4_MemoryPart {MTA8ATF1G64HZ-2G3} \ 13 | CONFIG.C0.DDR4_DataWidth {64} \ 14 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 15 | CONFIG.C0.DDR4_CasLatency {13} \ 16 | CONFIG.C0.DDR4_CasWriteLatency {10} \ 17 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 18 | ] [get_ips ddr4_sodimm_0] 19 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG640/fpga/coregen/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | COREGEN:=coregen 3 | XAW2VERILOG:=xaw2verilog 4 | 5 | # Source 6 | XCO:=ten_gig_eth_pcs_pma_v2_6.xco ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco 7 | XAW:= 8 | 9 | # Targets 10 | TARGETS += $(XCO:.xco=) 11 | TARGETS += $(XAW:.xaw=) 12 | 13 | # Rules 14 | .PHONY: all 15 | all: $(TARGETS) 16 | 17 | .PHONY: clean 18 | clean: 19 | -rm -rf $(TARGETS) 20 | 21 | %: %.xco 22 | $(eval $@_TMP := $(shell mktemp -d)) 23 | cp -a coregen.cgp $($@_TMP) 24 | cp -a $< $($@_TMP) 25 | cd $($@_TMP) && $(COREGEN) -p coregen.cgp -b $(notdir $<) 26 | mv $($@_TMP) $@ 27 | 28 | %: %.xaw 29 | $(eval $@_TMP := $(shell mktemp -d)) 30 | cp -a coregen.cgp $($@_TMP) 31 | cp -a $< $($@_TMP) 32 | cd $($@_TMP) && $(XAW2VERILOG) -st $(notdir $<) $(notdir $*) 33 | mv $($@_TMP) $@ 34 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU200/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U200 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U200 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu200-fsgd2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U200 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU250/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U250 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U250 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu250-figd2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U250 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU280/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U280 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U280 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu280-fsvh2892-2L-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U280 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/app/template/modules/mqnic_app_template/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: BSD-2-Clause-Views 2 | # Copyright (c) 2022-2023 The Regents of the University of California 3 | 4 | ifneq ($(KERNELRELEASE),) 5 | 6 | KBUILD_EXTRA_SYMBOLS=$(src)/../mqnic/Module.symvers 7 | 8 | ccflags-y += -I$(src)/../mqnic/ 9 | 10 | # object files to build 11 | obj-m += mqnic_app_template.o 12 | mqnic_app_template-y += main.o 13 | 14 | else 15 | 16 | ifneq ($(KERNEL_SRC),) 17 | # alternatively to variable KDIR accept variable KERNEL_SRC as used in 18 | # PetaLinux/Yocto for example 19 | KDIR ?= $(KERNEL_SRC) 20 | endif 21 | 22 | KDIR ?= /lib/modules/$(shell uname -r)/build 23 | 24 | all: modules 25 | 26 | help modules modules_install clean: 27 | $(MAKE) -C $(KDIR) M=$(shell pwd) $@ 28 | 29 | install: modules_install 30 | 31 | endif 32 | -------------------------------------------------------------------------------- /fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | COREGEN:=coregen 3 | XAW2VERILOG:=xaw2verilog 4 | 5 | # Source 6 | XCO:=ten_gig_eth_pcs_pma_v2_6.xco ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco 7 | XAW:= 8 | 9 | # Targets 10 | TARGETS += $(XCO:.xco=) 11 | TARGETS += $(XAW:.xaw=) 12 | 13 | # Rules 14 | .PHONY: all 15 | all: $(TARGETS) 16 | 17 | .PHONY: clean 18 | clean: 19 | -rm -rf $(TARGETS) 20 | 21 | %: %.xco 22 | $(eval $@_TMP := $(shell mktemp -d)) 23 | cp -a coregen.cgp $($@_TMP) 24 | cp -a $< $($@_TMP) 25 | cd $($@_TMP) && $(COREGEN) -p coregen.cgp -b $(notdir $<) 26 | mv $($@_TMP) $@ 27 | 28 | %: %.xaw 29 | $(eval $@_TMP := $(shell mktemp -d)) 30 | cp -a coregen.cgp $($@_TMP) 31 | cp -a $< $($@_TMP) 32 | cd $($@_TMP) && $(XAW2VERILOG) -st $(notdir $<) $(notdir $*) 33 | mv $($@_TMP) $@ 34 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/DE10_Agilex/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Terasic DE10-Agilex Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Terasic DE10-Agilex. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: AGFB014R24B2E2V 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Intel Quartus Pro components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the DE10-Agilex with Quartus Pro. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ExaNIC_X25/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ExaNIC X25 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X25 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcku3p-ffvb676-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ExaNIC X25 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/init-ifupdown/interfaces: -------------------------------------------------------------------------------- 1 | # /etc/network/interfaces -- configuration file for ifup(8), ifdown(8) 2 | 3 | # The loopback interface 4 | auto lo 5 | iface lo inet loopback 6 | 7 | # Wireless interfaces 8 | iface wlan0 inet dhcp 9 | wireless_mode managed 10 | wireless_essid any 11 | wpa-driver wext 12 | wpa-conf /etc/wpa_supplicant.conf 13 | 14 | iface atml0 inet dhcp 15 | 16 | # Wired or wireless interfaces 17 | auto eth0 18 | iface eth0 inet dhcp 19 | iface eth1 inet dhcp 20 | 21 | # Ethernet/RNDIS gadget (g_ether) 22 | # ... or on host side, usbnet and random hwaddr 23 | iface usb0 inet static 24 | address 192.168.7.2 25 | netmask 255.255.255.0 26 | network 192.168.7.0 27 | gateway 192.168.7.1 28 | 29 | # Bluetooth networking 30 | iface bnep0 inet dhcp 31 | 32 | -------------------------------------------------------------------------------- /fpga/app/dma_bench/modules/mqnic_app_dma_bench/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: BSD-2-Clause-Views 2 | # Copyright (c) 2022-2023 The Regents of the University of California 3 | 4 | ifneq ($(KERNELRELEASE),) 5 | 6 | KBUILD_EXTRA_SYMBOLS=$(src)/../mqnic/Module.symvers 7 | 8 | ccflags-y += -I$(src)/../mqnic/ 9 | 10 | # object files to build 11 | obj-m += mqnic_app_dma_bench.o 12 | mqnic_app_dma_bench-y += main.o 13 | 14 | else 15 | 16 | ifneq ($(KERNEL_SRC),) 17 | # alternatively to variable KDIR accept variable KERNEL_SRC as used in 18 | # PetaLinux/Yocto for example 19 | KDIR ?= $(KERNEL_SRC) 20 | endif 21 | 22 | KDIR ?= /lib/modules/$(shell uname -r)/build 23 | 24 | all: modules 25 | 26 | help modules modules_install clean: 27 | $(MAKE) -C $(KDIR) M=$(shell pwd) $@ 28 | 29 | install: modules_install 30 | 31 | endif 32 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/520N_MX/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe BittWare 520N-MX Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the BittWare 520N-MX FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: 1SM21CHU2F53E2VG 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Intel Quartus Pro components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the 520N-MX board with Quartus Pro. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ExaNIC_X10/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ExaNIC X10 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X10 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcku035-fbva676-2-c 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado toolchain components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ExaNIC X10 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/fb2CG/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe fb2CG@KU15P Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Silicom fb2CG@KU15P FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcku15p-ffve1760-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado toolchain components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the fb2CG@KU15P board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/lib/pcie/scripts/pcie_ext_tag.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | en=$2 5 | 6 | if [ -z "$dev" ]; then 7 | echo "Error: no device specified" 8 | exit 1 9 | fi 10 | 11 | if [ -z "$en" ]; then 12 | echo "Error: must specify operation" 13 | exit 1 14 | fi 15 | 16 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 17 | dev="0000:$dev" 18 | fi 19 | 20 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 21 | echo "Error: device $dev not found" 22 | exit 1 23 | fi 24 | 25 | echo "Device control:" $(setpci -s $dev CAP_EXP+8.w) 26 | 27 | if (($en > 0)); then 28 | echo "Enabling ext tag on $dev..." 29 | setpci -s $dev CAP_EXP+8.w=0100:0100 30 | else 31 | echo "Disabling ext tag on $dev..." 32 | setpci -s $dev CAP_EXP+8.w=0000:0100 33 | fi 34 | 35 | echo "Device control:" $(setpci -s $dev CAP_EXP+8.w) 36 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU102/fpga/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {128} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {3332} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ 13 | CONFIG.C0.DDR4_DataWidth {16} \ 14 | CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ 15 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 16 | CONFIG.C0.DDR4_CasLatency {17} \ 17 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 18 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 19 | ] [get_ips ddr4_0] 20 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/configs/init-ifupdown/interfaces: -------------------------------------------------------------------------------- 1 | # /etc/network/interfaces -- configuration file for ifup(8), ifdown(8) 2 | 3 | # The loopback interface 4 | auto lo 5 | iface lo inet loopback 6 | 7 | # Wireless interfaces 8 | iface wlan0 inet dhcp 9 | wireless_mode managed 10 | wireless_essid any 11 | wpa-driver wext 12 | wpa-conf /etc/wpa_supplicant.conf 13 | 14 | iface atml0 inet dhcp 15 | 16 | # Wired or wireless interfaces 17 | auto eth0 18 | iface eth0 inet dhcp 19 | iface eth1 inet dhcp 20 | 21 | # Ethernet/RNDIS gadget (g_ether) 22 | # ... or on host side, usbnet and random hwaddr 23 | iface usb0 inet static 24 | address 192.168.7.2 25 | netmask 255.255.255.0 26 | network 192.168.7.0 27 | gateway 192.168.7.1 28 | 29 | # Bluetooth networking 30 | iface bnep0 inet dhcp 31 | 32 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ADM_PCIE_9V3/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ADM-PCIE-9V3 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu3p-ffvc1517-2-i 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ADM-PCIE-9V3 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {825} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {6187} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A1G8SA-075} \ 13 | CONFIG.C0.DDR4_DataWidth {72} \ 14 | CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ 15 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 16 | CONFIG.C0.DDR4_CasLatency {19} \ 17 | CONFIG.C0.DDR4_CasWriteLatency {14} \ 18 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 19 | ] [get_ips ddr4_0] 20 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU118/fpga_100g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {750} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {4000} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ 13 | CONFIG.C0.DDR4_DataWidth {72} \ 14 | CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ 15 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 16 | CONFIG.C0.DDR4_CasLatency {18} \ 17 | CONFIG.C0.DDR4_CasWriteLatency {14} \ 18 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 19 | ] [get_ips ddr4_0] 20 | -------------------------------------------------------------------------------- /fpga/mqnic/VCU118/fpga_25g/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {750} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {4000} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ 13 | CONFIG.C0.DDR4_DataWidth {72} \ 14 | CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ 15 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 16 | CONFIG.C0.DDR4_CasLatency {18} \ 17 | CONFIG.C0.DDR4_CasWriteLatency {14} \ 18 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 19 | ] [get_ips ddr4_0] 20 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_pcie/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {3332} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ 13 | CONFIG.C0.DDR4_DataWidth {64} \ 14 | CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ 15 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 16 | CONFIG.C0.DDR4_CasLatency {17} \ 17 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 18 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 19 | ] [get_ips ddr4_0] 20 | -------------------------------------------------------------------------------- /fpga/mqnic/ZCU106/fpga_zynqmp/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {3332} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ 13 | CONFIG.C0.DDR4_DataWidth {64} \ 14 | CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ 15 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 16 | CONFIG.C0.DDR4_CasLatency {17} \ 17 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 18 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 19 | ] [get_ips ddr4_0] 20 | -------------------------------------------------------------------------------- /fpga/mqnic/DE10_Agilex/fpga_100g/mac_100g.sdc: -------------------------------------------------------------------------------- 1 | # E-Tile MACs 2 | proc constrain_etile_mac_dual { inst } { 3 | puts "Inserting timing constraints for MAC dual $inst" 4 | 5 | foreach mac {mac_02_inst mac_13_inst} { 6 | set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] 7 | set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] 8 | } 9 | 10 | for {set i 0} {$i < 2} {incr i} { 11 | constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst" 12 | } 13 | } 14 | 15 | constrain_etile_mac_dual "qsfpdda_mac_inst" 16 | constrain_etile_mac_dual "qsfpddb_mac_inst" 17 | -------------------------------------------------------------------------------- /fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_100g.sdc: -------------------------------------------------------------------------------- 1 | # E-Tile MACs 2 | proc constrain_etile_mac_dual { inst } { 3 | puts "Inserting timing constraints for MAC dual $inst" 4 | 5 | foreach mac {mac_02_inst mac_13_inst} { 6 | set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] 7 | set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] 8 | } 9 | 10 | for {set i 0} {$i < 2} {incr i} { 11 | constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst" 12 | } 13 | } 14 | 15 | constrain_etile_mac_dual "qsfpdd0_mac_inst" 16 | constrain_etile_mac_dual "qsfpdd1_mac_inst" 17 | -------------------------------------------------------------------------------- /fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/ddr4_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.C0.DDR4_AxiSelection {true} \ 6 | CONFIG.C0.DDR4_AxiDataWidth {512} \ 7 | CONFIG.C0.DDR4_AxiIDWidth {8} \ 8 | CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ 9 | CONFIG.C0.DDR4_TimePeriod {833} \ 10 | CONFIG.C0.DDR4_InputClockPeriod {4998} \ 11 | CONFIG.C0.DDR4_MemoryType {Components} \ 12 | CONFIG.C0.DDR4_MemoryPart {MT40A512M8HX-083} \ 13 | CONFIG.C0.DDR4_DataWidth {72} \ 14 | CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ 15 | CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 16 | CONFIG.C0.DDR4_CasLatency {16} \ 17 | CONFIG.C0.DDR4_CasWriteLatency {12} \ 18 | CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} 19 | ] [get_ips ddr4_0] 20 | -------------------------------------------------------------------------------- /docs/source/glossary.rst: -------------------------------------------------------------------------------- 1 | .. _glossary: 2 | 3 | ======== 4 | Glossary 5 | ======== 6 | 7 | .. glossary:: 8 | 9 | AXI 10 | Advanced eXtensible Interface 11 | 12 | BAR 13 | Base Address Register 14 | 15 | DMA 16 | Direct Memory Access 17 | 18 | FPGA 19 | Field-Programmable Gate Array 20 | 21 | JTAG 22 | Joint Test Action Group 23 | 24 | MAC 25 | Media Access Control(ler) 26 | 27 | MSI 28 | Message-Signaled Interrupt 29 | 30 | NIC 31 | Network Interface Controller 32 | 33 | PCI 34 | Peripheral Component Interconnect 35 | 36 | PCIe 37 | PCI Express 38 | 39 | PHY 40 | PHYsical layer (interface) 41 | 42 | PTP 43 | Precision Time Protocol (IEEE 1588) 44 | 45 | RSS 46 | Receive Side Scaling 47 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU118/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU118 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcvu9p-flga2104-2L-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the VCU118 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/ZCU106/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ZCU106 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU106 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xczu7ev-ffvc1156-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the ZCU106 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/AU50/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U50 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U50 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | * FPGA: xcu50-fsvh2104-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the Alveo U50 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU108/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU108 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU108 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcvu095-ffva2104-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the VCU108 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /fpga/lib/pcie/example/VCU1525/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU1525 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU1525 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcvu9p-fsgd2104-2L-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the VCU1525 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | --------------------------------------------------------------------------------