├── .github └── workflows │ └── regression-tests.yml ├── .gitignore ├── .test_durations ├── AUTHORS ├── COPYING ├── README ├── README.md ├── rtl ├── arbiter.v ├── axis_adapter.v ├── axis_arb_mux.f ├── axis_arb_mux.v ├── axis_arb_mux_wrap.py ├── axis_async_fifo.v ├── axis_async_fifo_adapter.f ├── axis_async_fifo_adapter.v ├── axis_broadcast.v ├── axis_broadcast_wrap.py ├── axis_cobs_decode.v ├── axis_cobs_encode.f ├── axis_cobs_encode.v ├── axis_crosspoint.v ├── axis_crosspoint_wrap.py ├── axis_demux.v ├── axis_demux_wrap.py ├── axis_fifo.v ├── axis_fifo_adapter.f ├── axis_fifo_adapter.v ├── axis_frame_join.v ├── axis_frame_join_wrap.py ├── axis_frame_len.v ├── axis_frame_length_adjust.v ├── axis_frame_length_adjust_fifo.f ├── axis_frame_length_adjust_fifo.v ├── axis_ll_bridge.v ├── axis_mux.v ├── axis_mux_wrap.py ├── axis_pipeline_fifo.v ├── axis_pipeline_register.f ├── axis_pipeline_register.v ├── axis_ram_switch.f ├── axis_ram_switch.v ├── axis_ram_switch_wrap.py ├── axis_rate_limit.v ├── axis_register.v ├── axis_srl_fifo.v ├── axis_srl_register.v ├── axis_stat_counter.v ├── axis_switch.f ├── axis_switch.v ├── axis_switch_wrap.py ├── axis_tap.v ├── ll_axis_bridge.v ├── priority_encoder.v └── sync_reset.v ├── syn ├── quartus │ ├── axis_async_fifo.sdc │ └── sync_reset.sdc ├── quartus_pro │ ├── axis_async_fifo.sdc │ └── sync_reset.sdc └── vivado │ ├── axis_async_fifo.tcl │ └── sync_reset.tcl ├── tb ├── Makefile ├── axis_adapter │ ├── Makefile │ └── test_axis_adapter.py ├── axis_arb_mux │ ├── Makefile │ └── test_axis_arb_mux.py ├── axis_async_fifo │ ├── Makefile │ └── test_axis_async_fifo.py ├── axis_async_fifo_adapter │ ├── Makefile │ └── test_axis_async_fifo_adapter.py ├── axis_broadcast │ ├── Makefile │ └── test_axis_broadcast.py ├── axis_cobs_decode │ ├── Makefile │ └── test_axis_cobs_decode.py ├── axis_cobs_encode │ ├── Makefile │ └── test_axis_cobs_encode.py ├── axis_demux │ ├── Makefile │ └── test_axis_demux.py ├── axis_ep.py ├── axis_fifo │ ├── Makefile │ └── test_axis_fifo.py ├── axis_fifo_adapter │ ├── Makefile │ └── test_axis_fifo_adapter.py ├── axis_frame_length_adjust │ ├── Makefile │ └── test_axis_frame_length_adjust.py ├── axis_frame_length_adjust_fifo │ ├── Makefile │ └── test_axis_frame_length_adjust_fifo.py ├── axis_mux │ ├── Makefile │ └── test_axis_mux.py ├── axis_pipeline_fifo │ ├── Makefile │ └── test_axis_pipeline_fifo.py ├── axis_pipeline_register │ ├── Makefile │ └── test_axis_pipeline_register.py ├── axis_ram_switch │ ├── Makefile │ └── test_axis_ram_switch.py ├── axis_rate_limit │ ├── Makefile │ └── test_axis_rate_limit.py ├── axis_register │ ├── Makefile │ └── test_axis_register.py ├── axis_srl_fifo │ ├── Makefile │ └── test_axis_srl_fifo.py ├── axis_srl_register │ ├── Makefile │ └── test_axis_srl_register.py ├── axis_switch │ ├── Makefile │ └── test_axis_switch.py ├── ll_ep.py ├── test_arbiter.py ├── test_arbiter.v ├── test_arbiter_rr.py ├── test_arbiter_rr.v ├── test_axis_adapter_64_8.py ├── test_axis_adapter_64_8.v ├── test_axis_adapter_8_64.py ├── test_axis_adapter_8_64.v ├── test_axis_arb_mux_4.py ├── test_axis_arb_mux_4.v ├── test_axis_arb_mux_4_64.py ├── test_axis_arb_mux_4_64.v ├── test_axis_async_fifo.py ├── test_axis_async_fifo.v ├── test_axis_async_fifo_64.py ├── test_axis_async_fifo_64.v ├── test_axis_async_fifo_adapter_64_8.py ├── test_axis_async_fifo_adapter_64_8.v ├── test_axis_async_fifo_adapter_8_64.py ├── test_axis_async_fifo_adapter_8_64.v ├── test_axis_async_frame_fifo.py ├── test_axis_async_frame_fifo.v ├── test_axis_async_frame_fifo_64.py ├── test_axis_async_frame_fifo_64.v ├── test_axis_broadcast_4.py ├── test_axis_broadcast_4.v ├── test_axis_cobs_decode.py ├── test_axis_cobs_decode.v ├── test_axis_cobs_encode.py ├── test_axis_cobs_encode.v ├── test_axis_cobs_encode_zero_frame.py ├── test_axis_cobs_encode_zero_frame.v ├── test_axis_crosspoint_4x4.py ├── test_axis_crosspoint_4x4.v ├── test_axis_crosspoint_4x4_64.py ├── test_axis_crosspoint_4x4_64.v ├── test_axis_demux_4.py ├── test_axis_demux_4.v ├── test_axis_demux_4_64.py ├── test_axis_demux_4_64.v ├── test_axis_fifo.py ├── test_axis_fifo.v ├── test_axis_fifo_64.py ├── test_axis_fifo_64.v ├── test_axis_fifo_adapter_64_8.py ├── test_axis_fifo_adapter_64_8.v ├── test_axis_fifo_adapter_8_64.py ├── test_axis_fifo_adapter_8_64.v ├── test_axis_frame_fifo.py ├── test_axis_frame_fifo.v ├── test_axis_frame_fifo_64.py ├── test_axis_frame_fifo_64.v ├── test_axis_frame_join_4.py ├── test_axis_frame_join_4.v ├── test_axis_frame_len_64.py ├── test_axis_frame_len_64.v ├── test_axis_frame_len_8.py ├── test_axis_frame_len_8.v ├── test_axis_frame_length_adjust_64.py ├── test_axis_frame_length_adjust_64.v ├── test_axis_frame_length_adjust_8.py ├── test_axis_frame_length_adjust_8.v ├── test_axis_frame_length_adjust_fifo.py ├── test_axis_frame_length_adjust_fifo.v ├── test_axis_frame_length_adjust_fifo_64.py ├── test_axis_frame_length_adjust_fifo_64.v ├── test_axis_ll_bridge.py ├── test_axis_ll_bridge.v ├── test_axis_mux_4.py ├── test_axis_mux_4.v ├── test_axis_mux_4_64.py ├── test_axis_mux_4_64.v ├── test_axis_ram_switch_1x4_256_64.py ├── test_axis_ram_switch_1x4_256_64.v ├── test_axis_ram_switch_4x1_64_256.py ├── test_axis_ram_switch_4x1_64_256.v ├── test_axis_ram_switch_4x4_64_64.py ├── test_axis_ram_switch_4x4_64_64.v ├── test_axis_rate_limit.py ├── test_axis_rate_limit.v ├── test_axis_rate_limit_64.py ├── test_axis_rate_limit_64.v ├── test_axis_register.py ├── test_axis_register.v ├── test_axis_register_64.py ├── test_axis_register_64.v ├── test_axis_srl_fifo.py ├── test_axis_srl_fifo.v ├── test_axis_srl_fifo_64.py ├── test_axis_srl_fifo_64.v ├── test_axis_srl_register.py ├── test_axis_srl_register.v ├── test_axis_srl_register_64.py ├── test_axis_srl_register_64.v ├── test_axis_stat_counter.py ├── test_axis_stat_counter.v ├── test_axis_switch_4x4.py ├── test_axis_switch_4x4.v ├── test_axis_switch_4x4_64.py ├── test_axis_switch_4x4_64.v ├── test_axis_tap.py ├── test_axis_tap.v ├── test_axis_tap_64.py ├── test_axis_tap_64.v ├── test_ll_axis_bridge.py ├── test_ll_axis_bridge.v ├── test_priority_encoder.py └── test_priority_encoder.v └── tox.ini /.github/workflows/regression-tests.yml: -------------------------------------------------------------------------------- 1 | name: Regression Tests 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | build: 7 | name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10) 8 | runs-on: ubuntu-22.04 9 | 10 | strategy: 11 | matrix: 12 | python-version: ["3.10"] 13 | group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10] 14 | 15 | steps: 16 | - uses: actions/checkout@v3 17 | 18 | - name: Set up Python ${{ matrix.python-version }} 19 | uses: actions/setup-python@v4 20 | with: 21 | python-version: ${{ matrix.python-version }} 22 | 23 | - name: Install Icarus Verilog 24 | run: | 25 | sudo apt install -y --no-install-recommends iverilog 26 | 27 | - name: Install Python dependencies 28 | run: | 29 | python -m pip install --upgrade pip 30 | pip install tox tox-gh-actions 31 | 32 | - name: Test with tox 33 | run: tox -- -n auto --verbose --splits 10 --group ${{ matrix.group }} 34 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.lxt 3 | *.pyc 4 | *.vvp 5 | *.kate-swp 6 | 7 | -------------------------------------------------------------------------------- /AUTHORS: -------------------------------------------------------------------------------- 1 | Alex Forencich 2 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | Copyright (c) 2014-2018 Alex Forencich 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | 10 | The above copyright notice and this permission notice shall be included in 11 | all copies or substantial portions of the Software. 12 | 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | THE SOFTWARE. 20 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | README.md -------------------------------------------------------------------------------- /rtl/axis_arb_mux.f: -------------------------------------------------------------------------------- 1 | axis_arb_mux.v 2 | arbiter.v 3 | priority_encoder.v 4 | -------------------------------------------------------------------------------- /rtl/axis_async_fifo_adapter.f: -------------------------------------------------------------------------------- 1 | axis_async_fifo_adapter.v 2 | axis_async_fifo.v 3 | axis_adapter.v 4 | -------------------------------------------------------------------------------- /rtl/axis_cobs_encode.f: -------------------------------------------------------------------------------- 1 | axis_cobs_encode.v 2 | axis_fifo.v 3 | -------------------------------------------------------------------------------- /rtl/axis_fifo_adapter.f: -------------------------------------------------------------------------------- 1 | axis_fifo_adapter.v 2 | axis_fifo.v 3 | axis_adapter.v 4 | -------------------------------------------------------------------------------- /rtl/axis_frame_len.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2019 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * AXI4-Stream frame length measurement 33 | */ 34 | module axis_frame_len # 35 | ( 36 | // Width of AXI stream interfaces in bits 37 | parameter DATA_WIDTH = 64, 38 | // Propagate tkeep signal 39 | // If disabled, tkeep assumed to be 1'b1 40 | parameter KEEP_ENABLE = (DATA_WIDTH>8), 41 | // tkeep signal width (words per cycle) 42 | parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), 43 | // Width of length counter 44 | parameter LEN_WIDTH = 16 45 | ) 46 | ( 47 | input wire clk, 48 | input wire rst, 49 | 50 | /* 51 | * AXI monitor 52 | */ 53 | input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep, 54 | input wire monitor_axis_tvalid, 55 | input wire monitor_axis_tready, 56 | input wire monitor_axis_tlast, 57 | 58 | /* 59 | * Status 60 | */ 61 | output wire [LEN_WIDTH-1:0] frame_len, 62 | output wire frame_len_valid 63 | ); 64 | 65 | reg [LEN_WIDTH-1:0] frame_len_reg = 0, frame_len_next; 66 | reg frame_len_valid_reg = 1'b0, frame_len_valid_next; 67 | 68 | assign frame_len = frame_len_reg; 69 | assign frame_len_valid = frame_len_valid_reg; 70 | 71 | integer offset, i, bit_cnt; 72 | 73 | always @* begin 74 | frame_len_next = frame_len_reg; 75 | frame_len_valid_next = 1'b0; 76 | 77 | if (frame_len_valid_reg) begin 78 | frame_len_next = 0; 79 | end 80 | 81 | if (monitor_axis_tready && monitor_axis_tvalid) begin 82 | // valid transfer cycle 83 | 84 | if (monitor_axis_tlast) begin 85 | // end of frame 86 | frame_len_valid_next = 1'b1; 87 | end 88 | 89 | // increment frame length by number of words transferred 90 | if (KEEP_ENABLE) begin 91 | bit_cnt = 0; 92 | for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin 93 | if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i; 94 | end 95 | frame_len_next = frame_len_next + bit_cnt; 96 | end else begin 97 | frame_len_next = frame_len_next + 1; 98 | end 99 | end 100 | end 101 | 102 | always @(posedge clk) begin 103 | frame_len_reg <= frame_len_next; 104 | frame_len_valid_reg <= frame_len_valid_next; 105 | 106 | if (rst) begin 107 | frame_len_reg <= 0; 108 | frame_len_valid_reg <= 0; 109 | end 110 | end 111 | 112 | endmodule 113 | 114 | `resetall 115 | -------------------------------------------------------------------------------- /rtl/axis_frame_length_adjust_fifo.f: -------------------------------------------------------------------------------- 1 | axis_frame_length_adjust_fifo.v 2 | axis_frame_length_adjust.v 3 | axis_fifo.v 4 | -------------------------------------------------------------------------------- /rtl/axis_ll_bridge.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * AXI4-Stream to LocalLink bridge 33 | */ 34 | module axis_ll_bridge # 35 | ( 36 | parameter DATA_WIDTH = 8 37 | ) 38 | ( 39 | input wire clk, 40 | input wire rst, 41 | 42 | /* 43 | * AXI input 44 | */ 45 | input wire [DATA_WIDTH-1:0] s_axis_tdata, 46 | input wire s_axis_tvalid, 47 | output wire s_axis_tready, 48 | input wire s_axis_tlast, 49 | 50 | /* 51 | * LocalLink output 52 | */ 53 | output wire [DATA_WIDTH-1:0] ll_data_out, 54 | output wire ll_sof_out_n, 55 | output wire ll_eof_out_n, 56 | output wire ll_src_rdy_out_n, 57 | input wire ll_dst_rdy_in_n 58 | ); 59 | 60 | reg last_tlast = 1'b1; 61 | 62 | always @(posedge clk) begin 63 | if (rst) begin 64 | last_tlast = 1'b1; 65 | end else begin 66 | if (s_axis_tvalid && s_axis_tready) last_tlast = s_axis_tlast; 67 | end 68 | end 69 | 70 | // high for packet length 1 -> cannot set SOF and EOF in same cycle 71 | // invalid packets are discarded 72 | wire invalid = s_axis_tvalid && s_axis_tlast && last_tlast; 73 | 74 | assign s_axis_tready = !ll_dst_rdy_in_n; 75 | 76 | assign ll_data_out = s_axis_tdata; 77 | assign ll_sof_out_n = !(last_tlast && s_axis_tvalid && !invalid); 78 | assign ll_eof_out_n = !(s_axis_tlast && !invalid); 79 | assign ll_src_rdy_out_n = !(s_axis_tvalid && !invalid); 80 | 81 | endmodule 82 | 83 | `resetall 84 | -------------------------------------------------------------------------------- /rtl/axis_pipeline_register.f: -------------------------------------------------------------------------------- 1 | axis_pipeline_register.v 2 | axis_register.v 3 | -------------------------------------------------------------------------------- /rtl/axis_ram_switch.f: -------------------------------------------------------------------------------- 1 | axis_ram_switch.v 2 | axis_adapter.v 3 | arbiter.v 4 | priority_encoder.v 5 | -------------------------------------------------------------------------------- /rtl/axis_switch.f: -------------------------------------------------------------------------------- 1 | axis_switch.v 2 | axis_register.v 3 | arbiter.v 4 | priority_encoder.v 5 | -------------------------------------------------------------------------------- /rtl/ll_axis_bridge.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * LocalLink to AXI4-Stream bridge 33 | */ 34 | module ll_axis_bridge # 35 | ( 36 | parameter DATA_WIDTH = 8 37 | ) 38 | ( 39 | input wire clk, 40 | input wire rst, 41 | 42 | /* 43 | * LocalLink input 44 | */ 45 | input wire [DATA_WIDTH-1:0] ll_data_in, 46 | input wire ll_sof_in_n, 47 | input wire ll_eof_in_n, 48 | input wire ll_src_rdy_in_n, 49 | output wire ll_dst_rdy_out_n, 50 | 51 | /* 52 | * AXI output 53 | */ 54 | output wire [DATA_WIDTH-1:0] m_axis_tdata, 55 | output wire m_axis_tvalid, 56 | input wire m_axis_tready, 57 | output wire m_axis_tlast 58 | ); 59 | 60 | assign m_axis_tdata = ll_data_in; 61 | assign m_axis_tvalid = !ll_src_rdy_in_n; 62 | assign m_axis_tlast = !ll_eof_in_n; 63 | 64 | assign ll_dst_rdy_out_n = !m_axis_tready; 65 | 66 | endmodule 67 | 68 | `resetall 69 | -------------------------------------------------------------------------------- /rtl/priority_encoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2021 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * Priority encoder module 33 | */ 34 | module priority_encoder # 35 | ( 36 | parameter WIDTH = 4, 37 | // LSB priority selection 38 | parameter LSB_HIGH_PRIORITY = 0 39 | ) 40 | ( 41 | input wire [WIDTH-1:0] input_unencoded, 42 | output wire output_valid, 43 | output wire [$clog2(WIDTH)-1:0] output_encoded, 44 | output wire [WIDTH-1:0] output_unencoded 45 | ); 46 | 47 | parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1; 48 | parameter W = 2**LEVELS; 49 | 50 | // pad input to even power of two 51 | wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded}; 52 | 53 | wire [W/2-1:0] stage_valid[LEVELS-1:0]; 54 | wire [W/2-1:0] stage_enc[LEVELS-1:0]; 55 | 56 | generate 57 | genvar l, n; 58 | 59 | // process input bits; generate valid bit and encoded bit for each pair 60 | for (n = 0; n < W/2; n = n + 1) begin : loop_in 61 | assign stage_valid[0][n] = |input_padded[n*2+1:n*2]; 62 | if (LSB_HIGH_PRIORITY) begin 63 | // bit 0 is highest priority 64 | assign stage_enc[0][n] = !input_padded[n*2+0]; 65 | end else begin 66 | // bit 0 is lowest priority 67 | assign stage_enc[0][n] = input_padded[n*2+1]; 68 | end 69 | end 70 | 71 | // compress down to single valid bit and encoded bus 72 | for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels 73 | for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress 74 | assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2]; 75 | if (LSB_HIGH_PRIORITY) begin 76 | // bit 0 is highest priority 77 | assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]}; 78 | end else begin 79 | // bit 0 is lowest priority 80 | assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]}; 81 | end 82 | end 83 | end 84 | endgenerate 85 | 86 | assign output_valid = stage_valid[LEVELS-1]; 87 | assign output_encoded = stage_enc[LEVELS-1]; 88 | assign output_unencoded = 1 << output_encoded; 89 | 90 | endmodule 91 | 92 | `resetall 93 | -------------------------------------------------------------------------------- /rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2020 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset # 36 | ( 37 | // depth of synchronizer 38 | parameter N = 2 39 | ) 40 | ( 41 | input wire clk, 42 | input wire rst, 43 | output wire out 44 | ); 45 | 46 | (* srl_style = "register" *) 47 | reg [N-1:0] sync_reg = {N{1'b1}}; 48 | 49 | assign out = sync_reg[N-1]; 50 | 51 | always @(posedge clk or posedge rst) begin 52 | if (rst) begin 53 | sync_reg <= {N{1'b1}}; 54 | end else begin 55 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 56 | end 57 | end 58 | 59 | endmodule 60 | 61 | `resetall 62 | -------------------------------------------------------------------------------- /syn/quartus/axis_async_fifo.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020-2023 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # AXI stream asynchronous FIFO timing constraints 22 | 23 | proc constrain_axis_async_fifo_inst { inst } { 24 | puts "Inserting timing constraints for axis_async_fifo instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|s_rst_sync*_reg $inst|m_rst_sync*_reg"] 28 | 29 | if {[get_collection_size [get_registers -nowarn "$inst|s_rst_sync1_reg"]]} { 30 | set_max_delay -from [get_registers "$inst|s_rst_sync1_reg"] -to [get_registers "$inst|s_rst_sync2_reg"] 8.000 31 | } 32 | 33 | if {[get_collection_size [get_registers -nowarn "$inst|m_rst_sync1_reg"]]} { 34 | set_max_delay -from [get_registers "$inst|m_rst_sync1_reg"] -to [get_registers "$inst|m_rst_sync2_reg"] 8.000 35 | } 36 | 37 | # pointer synchronization 38 | set_max_delay -from [get_registers "$inst|rd_ptr_reg[*] $inst|rd_ptr_gray_reg[*]"] -to [get_registers "$inst|rd_ptr_gray_sync1_reg[*]"] 8.000 39 | set_max_delay -from [get_registers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*]"] -to [get_registers "$inst|wr_ptr_gray_sync1_reg[*]"] 8.000 40 | set_max_delay -from [get_registers "$inst|wr_ptr_sync_commit_reg[*]"] -to [get_registers "$inst|wr_ptr_commit_sync_reg[*]"] 8.000 41 | 42 | # frame FIFO pointer update synchronization 43 | set_max_delay -from [get_registers "$inst|wr_ptr_update_reg"] -to [get_registers "$inst|wr_ptr_update_sync1_reg"] 8.000 44 | set_max_delay -from [get_registers "$inst|wr_ptr_update_sync3_reg"] -to [get_registers "$inst|wr_ptr_update_ack_sync1_reg"] 8.000 45 | 46 | # status synchronization 47 | foreach i {overflow bad_frame good_frame} { 48 | if {[get_collection_size [get_registers -nowarn "$inst|${i}_sync*_reg"]]} { 49 | set_max_delay -from [get_registers "$inst|${i}_sync1_reg"] -to [get_registers "$inst|${i}_sync2_reg"] 8.000 50 | } 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /syn/quartus/sync_reset.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # reset synchronizer timing constraints 22 | 23 | proc constrain_sync_reset_inst { inst } { 24 | puts "Inserting timing constraints for sync_reset instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|sync_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /syn/quartus_pro/axis_async_fifo.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021-2023 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # AXI stream asynchronous FIFO timing constraints 22 | 23 | proc constrain_axis_async_fifo_inst { inst } { 24 | puts "Inserting timing constraints for axis_async_fifo instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|s_rst_sync*_reg $inst|m_rst_sync*_reg"] 28 | 29 | if {[get_collection_size [get_registers -nowarn "$inst|s_rst_sync1_reg"]]} { 30 | set_data_delay -from [get_registers "$inst|s_rst_sync1_reg"] -to [get_registers "$inst|s_rst_sync2_reg"] -override -get_value_from_clock_period min_clock_period -value_multiplier 0.8 31 | } 32 | 33 | if {[get_collection_size [get_registers -nowarn "$inst|m_rst_sync1_reg"]]} { 34 | set_data_delay -from [get_registers "$inst|m_rst_sync1_reg"] -to [get_registers "$inst|m_rst_sync2_reg"] -override -get_value_from_clock_period min_clock_period -value_multiplier 0.8 35 | } 36 | 37 | # pointer synchronization 38 | set_data_delay -from [get_registers "$inst|rd_ptr_reg[*] $inst|rd_ptr_gray_reg[*]"] -to [get_registers "$inst|rd_ptr_gray_sync1_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 39 | set_max_skew -from [get_keepers "$inst|rd_ptr_reg[*] $inst|rd_ptr_gray_reg[*]"] -to [get_keepers "$inst|rd_ptr_gray_sync1_reg[*]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8 40 | set_data_delay -from [get_registers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*]"] -to [get_registers "$inst|wr_ptr_gray_sync1_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 41 | set_max_skew -from [get_keepers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*]"] -to [get_keepers "$inst|wr_ptr_gray_sync1_reg[*]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8 42 | set_data_delay -from [get_registers "$inst|wr_ptr_sync_commit_reg[*]"] -to [get_registers "$inst|wr_ptr_commit_sync_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 43 | set_max_skew -from [get_keepers "$inst|wr_ptr_sync_commit_reg[*]"] -to [get_keepers "$inst|wr_ptr_commit_sync_reg[*]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8 44 | 45 | # frame FIFO pointer update synchronization 46 | set_data_delay -from [get_registers "$inst|wr_ptr_update_reg"] -to [get_registers "$inst|wr_ptr_update_sync1_reg"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 47 | set_data_delay -from [get_registers "$inst|wr_ptr_update_sync3_reg"] -to [get_registers "$inst|wr_ptr_update_ack_sync1_reg"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 48 | 49 | # status synchronization 50 | foreach i {overflow bad_frame good_frame} { 51 | if {[get_collection_size [get_registers -nowarn "$inst|${i}_sync*_reg"]]} { 52 | set_data_delay -from [get_registers "$inst|${i}_sync1_reg"] -to [get_registers "$inst|${i}_sync2_reg"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 53 | } 54 | } 55 | } 56 | -------------------------------------------------------------------------------- /syn/quartus_pro/sync_reset.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # reset synchronizer timing constraints 22 | 23 | proc constrain_sync_reset_inst { inst } { 24 | puts "Inserting timing constraints for sync_reset instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|sync_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /syn/vivado/sync_reset.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # reset synchronizer timing constraints 22 | 23 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == sync_reset || REF_NAME == sync_reset)}] { 24 | puts "Inserting timing constraints for sync_reset instance $inst" 25 | 26 | # reset synchronization 27 | set reset_ffs [get_cells -quiet -hier -regexp ".*/sync_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] 28 | 29 | set_property ASYNC_REG TRUE $reset_ffs 30 | set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}] 31 | } 32 | -------------------------------------------------------------------------------- /tb/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPTARGETS := all clean 22 | 23 | SUBDIRS := $(wildcard */.) 24 | 25 | $(TOPTARGETS): $(SUBDIRS) 26 | $(SUBDIRS): 27 | $(MAKE) -C $@ $(MAKECMDGOALS) 28 | 29 | .PHONY: $(TOPTARGETS) $(SUBDIRS) 30 | 31 | -------------------------------------------------------------------------------- /tb/axis_adapter/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_adapter 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_S_DATA_WIDTH := 8 36 | export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) 37 | export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) 38 | export PARAM_M_DATA_WIDTH := 8 39 | export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) 40 | export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) 41 | export PARAM_ID_ENABLE := 1 42 | export PARAM_ID_WIDTH := 8 43 | export PARAM_DEST_ENABLE := 1 44 | export PARAM_DEST_WIDTH := 8 45 | export PARAM_USER_ENABLE := 1 46 | export PARAM_USER_WIDTH := 1 47 | 48 | ifeq ($(SIM), icarus) 49 | PLUSARGS += -fst 50 | 51 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 52 | 53 | ifeq ($(WAVES), 1) 54 | VERILOG_SOURCES += iverilog_dump.v 55 | COMPILE_ARGS += -s iverilog_dump 56 | endif 57 | else ifeq ($(SIM), verilator) 58 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 59 | 60 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 61 | 62 | ifeq ($(WAVES), 1) 63 | COMPILE_ARGS += --trace-fst 64 | endif 65 | endif 66 | 67 | include $(shell cocotb-config --makefiles)/Makefile.sim 68 | 69 | iverilog_dump.v: 70 | echo 'module iverilog_dump();' > $@ 71 | echo 'initial begin' >> $@ 72 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 73 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 74 | echo 'end' >> $@ 75 | echo 'endmodule' >> $@ 76 | 77 | clean:: 78 | @rm -rf iverilog_dump.v 79 | @rm -rf dump.fst $(TOPLEVEL).fst 80 | -------------------------------------------------------------------------------- /tb/axis_arb_mux/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | export PORTS ?= 4 30 | 31 | DUT = axis_arb_mux 32 | WRAPPER = $(DUT)_wrap_$(PORTS) 33 | TOPLEVEL = $(WRAPPER) 34 | MODULE = test_$(DUT) 35 | VERILOG_SOURCES += $(WRAPPER).v 36 | VERILOG_SOURCES += ../../rtl/$(DUT).f 37 | 38 | # handle file list files 39 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 40 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 41 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 42 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 43 | 44 | # module parameters 45 | export PARAM_DATA_WIDTH := 8 46 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 47 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 48 | export PARAM_ID_ENABLE := 1 49 | export PARAM_S_ID_WIDTH := 8 50 | export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())") 51 | export PARAM_DEST_ENABLE := 1 52 | export PARAM_DEST_WIDTH := 8 53 | export PARAM_USER_ENABLE := 1 54 | export PARAM_USER_WIDTH := 1 55 | export PARAM_LAST_ENABLE := 1 56 | export PARAM_UPDATE_TID := 1 57 | export PARAM_ARB_TYPE_ROUND_ROBIN := 0 58 | export PARAM_ARB_LSB_HIGH_PRIORITY := 1 59 | 60 | ifeq ($(SIM), icarus) 61 | PLUSARGS += -fst 62 | 63 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 64 | 65 | ifeq ($(WAVES), 1) 66 | VERILOG_SOURCES += iverilog_dump.v 67 | COMPILE_ARGS += -s iverilog_dump 68 | endif 69 | else ifeq ($(SIM), verilator) 70 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 71 | 72 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 73 | 74 | ifeq ($(WAVES), 1) 75 | COMPILE_ARGS += --trace-fst 76 | endif 77 | endif 78 | 79 | include $(shell cocotb-config --makefiles)/Makefile.sim 80 | 81 | $(WRAPPER).v: ../../rtl/$(DUT)_wrap.py 82 | $< -p $(PORTS) 83 | 84 | iverilog_dump.v: 85 | echo 'module iverilog_dump();' > $@ 86 | echo 'initial begin' >> $@ 87 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 88 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 89 | echo 'end' >> $@ 90 | echo 'endmodule' >> $@ 91 | 92 | clean:: 93 | @rm -rf iverilog_dump.v 94 | @rm -rf dump.fst $(TOPLEVEL).fst 95 | @rm -rf *_wrap_*.v 96 | -------------------------------------------------------------------------------- /tb/axis_async_fifo/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_async_fifo 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DATA_WIDTH := 8 36 | export PARAM_KEEP_ENABLE := $(shell echo $$(( $(PARAM_DATA_WIDTH) > 8 ))) 37 | export PARAM_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_DATA_WIDTH) + 7 ) / 8 ))) 38 | export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_WIDTH) ))) 39 | export PARAM_LAST_ENABLE := 1 40 | export PARAM_ID_ENABLE := 1 41 | export PARAM_ID_WIDTH := 8 42 | export PARAM_DEST_ENABLE := 1 43 | export PARAM_DEST_WIDTH := 8 44 | export PARAM_USER_ENABLE := 1 45 | export PARAM_USER_WIDTH := 1 46 | export PARAM_RAM_PIPELINE := 1 47 | export PARAM_OUTPUT_FIFO_ENABLE := 0 48 | export PARAM_FRAME_FIFO := 1 49 | export PARAM_USER_BAD_FRAME_VALUE := 1 50 | export PARAM_USER_BAD_FRAME_MASK := 1 51 | export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) 52 | export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) 53 | export PARAM_DROP_WHEN_FULL := 0 54 | export PARAM_MARK_WHEN_FULL := 0 55 | export PARAM_PAUSE_ENABLE := 1 56 | export PARAM_FRAME_PAUSE := 1 57 | 58 | ifeq ($(SIM), icarus) 59 | PLUSARGS += -fst 60 | 61 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 62 | 63 | ifeq ($(WAVES), 1) 64 | VERILOG_SOURCES += iverilog_dump.v 65 | COMPILE_ARGS += -s iverilog_dump 66 | endif 67 | else ifeq ($(SIM), verilator) 68 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 69 | 70 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 71 | 72 | ifeq ($(WAVES), 1) 73 | COMPILE_ARGS += --trace-fst 74 | endif 75 | endif 76 | 77 | include $(shell cocotb-config --makefiles)/Makefile.sim 78 | 79 | iverilog_dump.v: 80 | echo 'module iverilog_dump();' > $@ 81 | echo 'initial begin' >> $@ 82 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 83 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 84 | echo 'end' >> $@ 85 | echo 'endmodule' >> $@ 86 | 87 | clean:: 88 | @rm -rf iverilog_dump.v 89 | @rm -rf dump.fst $(TOPLEVEL).fst 90 | -------------------------------------------------------------------------------- /tb/axis_async_fifo_adapter/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_async_fifo_adapter 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).f 33 | 34 | # handle file list files 35 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 36 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 37 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 38 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 39 | 40 | # module parameters 41 | export PARAM_S_DATA_WIDTH := 8 42 | export PARAM_S_KEEP_ENABLE := $(shell echo $$(( $(PARAM_S_DATA_WIDTH) > 8 ))) 43 | export PARAM_S_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_S_DATA_WIDTH) + 7 ) / 8 ))) 44 | export PARAM_M_DATA_WIDTH := 8 45 | export PARAM_M_KEEP_ENABLE := $(shell echo $$(( $(PARAM_M_DATA_WIDTH) > 8 ))) 46 | export PARAM_M_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_M_DATA_WIDTH) + 7 ) / 8 ))) 47 | export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_WIDTH) > $(PARAM_M_KEEP_WIDTH) ? $(PARAM_S_KEEP_WIDTH) : $(PARAM_M_KEEP_WIDTH)) ))) 48 | export PARAM_ID_ENABLE := 1 49 | export PARAM_ID_WIDTH := 8 50 | export PARAM_DEST_ENABLE := 1 51 | export PARAM_DEST_WIDTH := 8 52 | export PARAM_USER_ENABLE := 1 53 | export PARAM_USER_WIDTH := 1 54 | export PARAM_RAM_PIPELINE := 1 55 | export PARAM_OUTPUT_FIFO_ENABLE := 0 56 | export PARAM_FRAME_FIFO := 1 57 | export PARAM_USER_BAD_FRAME_VALUE := 1 58 | export PARAM_USER_BAD_FRAME_MASK := 1 59 | export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) 60 | export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) 61 | export PARAM_DROP_WHEN_FULL := 0 62 | export PARAM_MARK_WHEN_FULL := 0 63 | export PARAM_PAUSE_ENABLE := 1 64 | export PARAM_FRAME_PAUSE := 1 65 | 66 | ifeq ($(SIM), icarus) 67 | PLUSARGS += -fst 68 | 69 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 70 | 71 | ifeq ($(WAVES), 1) 72 | VERILOG_SOURCES += iverilog_dump.v 73 | COMPILE_ARGS += -s iverilog_dump 74 | endif 75 | else ifeq ($(SIM), verilator) 76 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 77 | 78 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 79 | 80 | ifeq ($(WAVES), 1) 81 | COMPILE_ARGS += --trace-fst 82 | endif 83 | endif 84 | 85 | include $(shell cocotb-config --makefiles)/Makefile.sim 86 | 87 | iverilog_dump.v: 88 | echo 'module iverilog_dump();' > $@ 89 | echo 'initial begin' >> $@ 90 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 91 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 92 | echo 'end' >> $@ 93 | echo 'endmodule' >> $@ 94 | 95 | clean:: 96 | @rm -rf iverilog_dump.v 97 | @rm -rf dump.fst $(TOPLEVEL).fst 98 | -------------------------------------------------------------------------------- /tb/axis_broadcast/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | export PORTS ?= 4 30 | 31 | DUT = axis_broadcast 32 | WRAPPER = $(DUT)_wrap_$(PORTS) 33 | TOPLEVEL = $(WRAPPER) 34 | MODULE = test_$(DUT) 35 | VERILOG_SOURCES += $(WRAPPER).v 36 | VERILOG_SOURCES += ../../rtl/$(DUT).v 37 | 38 | # module parameters 39 | export PARAM_DATA_WIDTH := 8 40 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 41 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 42 | export PARAM_LAST_ENABLE := 1 43 | export PARAM_ID_ENABLE := 1 44 | export PARAM_ID_WIDTH := 8 45 | export PARAM_DEST_ENABLE := 1 46 | export PARAM_DEST_WIDTH := 8 47 | export PARAM_USER_ENABLE := 1 48 | export PARAM_USER_WIDTH := 1 49 | 50 | ifeq ($(SIM), icarus) 51 | PLUSARGS += -fst 52 | 53 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 54 | 55 | ifeq ($(WAVES), 1) 56 | VERILOG_SOURCES += iverilog_dump.v 57 | COMPILE_ARGS += -s iverilog_dump 58 | endif 59 | else ifeq ($(SIM), verilator) 60 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 61 | 62 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 63 | 64 | ifeq ($(WAVES), 1) 65 | COMPILE_ARGS += --trace-fst 66 | endif 67 | endif 68 | 69 | include $(shell cocotb-config --makefiles)/Makefile.sim 70 | 71 | $(WRAPPER).v: ../../rtl/$(DUT)_wrap.py 72 | $< -p $(PORTS) 73 | 74 | iverilog_dump.v: 75 | echo 'module iverilog_dump();' > $@ 76 | echo 'initial begin' >> $@ 77 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 78 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 79 | echo 'end' >> $@ 80 | echo 'endmodule' >> $@ 81 | 82 | clean:: 83 | @rm -rf iverilog_dump.v 84 | @rm -rf dump.fst $(TOPLEVEL).fst 85 | @rm -rf *_wrap_*.v 86 | -------------------------------------------------------------------------------- /tb/axis_cobs_decode/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_cobs_decode 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | # export PARAM_NAME := 0 36 | 37 | ifeq ($(SIM), icarus) 38 | PLUSARGS += -fst 39 | 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 41 | 42 | ifeq ($(WAVES), 1) 43 | VERILOG_SOURCES += iverilog_dump.v 44 | COMPILE_ARGS += -s iverilog_dump 45 | endif 46 | else ifeq ($(SIM), verilator) 47 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 48 | 49 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 50 | 51 | ifeq ($(WAVES), 1) 52 | COMPILE_ARGS += --trace-fst 53 | endif 54 | endif 55 | 56 | include $(shell cocotb-config --makefiles)/Makefile.sim 57 | 58 | iverilog_dump.v: 59 | echo 'module iverilog_dump();' > $@ 60 | echo 'initial begin' >> $@ 61 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 62 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 63 | echo 'end' >> $@ 64 | echo 'endmodule' >> $@ 65 | 66 | clean:: 67 | @rm -rf iverilog_dump.v 68 | @rm -rf dump.fst $(TOPLEVEL).fst 69 | -------------------------------------------------------------------------------- /tb/axis_cobs_encode/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_cobs_encode 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).f 33 | 34 | # handle file list files 35 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 36 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 37 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 38 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 39 | 40 | # module parameters 41 | export PARAM_APPEND_ZERO := 0 42 | 43 | ifeq ($(SIM), icarus) 44 | PLUSARGS += -fst 45 | 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | VERILOG_SOURCES += iverilog_dump.v 50 | COMPILE_ARGS += -s iverilog_dump 51 | endif 52 | else ifeq ($(SIM), verilator) 53 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 54 | 55 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 56 | 57 | ifeq ($(WAVES), 1) 58 | COMPILE_ARGS += --trace-fst 59 | endif 60 | endif 61 | 62 | include $(shell cocotb-config --makefiles)/Makefile.sim 63 | 64 | iverilog_dump.v: 65 | echo 'module iverilog_dump();' > $@ 66 | echo 'initial begin' >> $@ 67 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 68 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 69 | echo 'end' >> $@ 70 | echo 'endmodule' >> $@ 71 | 72 | clean:: 73 | @rm -rf iverilog_dump.v 74 | @rm -rf dump.fst $(TOPLEVEL).fst 75 | -------------------------------------------------------------------------------- /tb/axis_demux/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | export PORTS ?= 4 30 | 31 | DUT = axis_demux 32 | WRAPPER = $(DUT)_wrap_$(PORTS) 33 | TOPLEVEL = $(WRAPPER) 34 | MODULE = test_$(DUT) 35 | VERILOG_SOURCES += $(WRAPPER).v 36 | VERILOG_SOURCES += ../../rtl/$(DUT).v 37 | 38 | # module parameters 39 | export PARAM_DATA_WIDTH := 8 40 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 41 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 42 | export PARAM_ID_ENABLE := 1 43 | export PARAM_ID_WIDTH := 8 44 | export PARAM_DEST_ENABLE := 1 45 | export PARAM_M_DEST_WIDTH := 8 46 | export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PORTS)-1).bit_length())") 47 | export PARAM_USER_ENABLE := 1 48 | export PARAM_USER_WIDTH := 1 49 | export PARAM_TDEST_ROUTE := 1 50 | 51 | ifeq ($(SIM), icarus) 52 | PLUSARGS += -fst 53 | 54 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 55 | 56 | ifeq ($(WAVES), 1) 57 | VERILOG_SOURCES += iverilog_dump.v 58 | COMPILE_ARGS += -s iverilog_dump 59 | endif 60 | else ifeq ($(SIM), verilator) 61 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 62 | 63 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 64 | 65 | ifeq ($(WAVES), 1) 66 | COMPILE_ARGS += --trace-fst 67 | endif 68 | endif 69 | 70 | include $(shell cocotb-config --makefiles)/Makefile.sim 71 | 72 | $(WRAPPER).v: ../../rtl/$(DUT)_wrap.py 73 | $< -p $(PORTS) 74 | 75 | iverilog_dump.v: 76 | echo 'module iverilog_dump();' > $@ 77 | echo 'initial begin' >> $@ 78 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 79 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 80 | echo 'end' >> $@ 81 | echo 'endmodule' >> $@ 82 | 83 | clean:: 84 | @rm -rf iverilog_dump.v 85 | @rm -rf dump.fst $(TOPLEVEL).fst 86 | @rm -rf *_wrap_*.v 87 | -------------------------------------------------------------------------------- /tb/axis_fifo/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_fifo 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DATA_WIDTH := 8 36 | export PARAM_KEEP_ENABLE := $(shell echo $$(( $(PARAM_DATA_WIDTH) > 8 ))) 37 | export PARAM_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_DATA_WIDTH) + 7 ) / 8 ))) 38 | export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_WIDTH) ))) 39 | export PARAM_LAST_ENABLE := 1 40 | export PARAM_ID_ENABLE := 1 41 | export PARAM_ID_WIDTH := 8 42 | export PARAM_DEST_ENABLE := 1 43 | export PARAM_DEST_WIDTH := 8 44 | export PARAM_USER_ENABLE := 1 45 | export PARAM_USER_WIDTH := 1 46 | export PARAM_RAM_PIPELINE := 1 47 | export PARAM_OUTPUT_FIFO_ENABLE := 0 48 | export PARAM_FRAME_FIFO := 1 49 | export PARAM_USER_BAD_FRAME_VALUE := 1 50 | export PARAM_USER_BAD_FRAME_MASK := 1 51 | export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) 52 | export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) 53 | export PARAM_DROP_WHEN_FULL := 0 54 | export PARAM_MARK_WHEN_FULL := 0 55 | export PARAM_PAUSE_ENABLE := 1 56 | export PARAM_FRAME_PAUSE := 1 57 | 58 | ifeq ($(SIM), icarus) 59 | PLUSARGS += -fst 60 | 61 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 62 | 63 | ifeq ($(WAVES), 1) 64 | VERILOG_SOURCES += iverilog_dump.v 65 | COMPILE_ARGS += -s iverilog_dump 66 | endif 67 | else ifeq ($(SIM), verilator) 68 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 69 | 70 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 71 | 72 | ifeq ($(WAVES), 1) 73 | COMPILE_ARGS += --trace-fst 74 | endif 75 | endif 76 | 77 | include $(shell cocotb-config --makefiles)/Makefile.sim 78 | 79 | iverilog_dump.v: 80 | echo 'module iverilog_dump();' > $@ 81 | echo 'initial begin' >> $@ 82 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 83 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 84 | echo 'end' >> $@ 85 | echo 'endmodule' >> $@ 86 | 87 | clean:: 88 | @rm -rf iverilog_dump.v 89 | @rm -rf dump.fst $(TOPLEVEL).fst 90 | -------------------------------------------------------------------------------- /tb/axis_fifo_adapter/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_fifo_adapter 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).f 33 | 34 | # handle file list files 35 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 36 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 37 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 38 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 39 | 40 | # module parameters 41 | export PARAM_S_DATA_WIDTH := 8 42 | export PARAM_S_KEEP_ENABLE := $(shell echo $$(( $(PARAM_S_DATA_WIDTH) > 8 ))) 43 | export PARAM_S_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_S_DATA_WIDTH) + 7 ) / 8 ))) 44 | export PARAM_M_DATA_WIDTH := 8 45 | export PARAM_M_KEEP_ENABLE := $(shell echo $$(( $(PARAM_M_DATA_WIDTH) > 8 ))) 46 | export PARAM_M_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_M_DATA_WIDTH) + 7 ) / 8 ))) 47 | export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_WIDTH) > $(PARAM_M_KEEP_WIDTH) ? $(PARAM_S_KEEP_WIDTH) : $(PARAM_M_KEEP_WIDTH)) ))) 48 | export PARAM_ID_ENABLE := 1 49 | export PARAM_ID_WIDTH := 8 50 | export PARAM_DEST_ENABLE := 1 51 | export PARAM_DEST_WIDTH := 8 52 | export PARAM_USER_ENABLE := 1 53 | export PARAM_USER_WIDTH := 1 54 | export PARAM_RAM_PIPELINE := 1 55 | export PARAM_OUTPUT_FIFO_ENABLE := 0 56 | export PARAM_FRAME_FIFO := 1 57 | export PARAM_USER_BAD_FRAME_VALUE := 1 58 | export PARAM_USER_BAD_FRAME_MASK := 1 59 | export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) 60 | export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) 61 | export PARAM_DROP_WHEN_FULL := 0 62 | export PARAM_MARK_WHEN_FULL := 0 63 | export PARAM_PAUSE_ENABLE := 1 64 | export PARAM_FRAME_PAUSE := 1 65 | 66 | ifeq ($(SIM), icarus) 67 | PLUSARGS += -fst 68 | 69 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 70 | 71 | ifeq ($(WAVES), 1) 72 | VERILOG_SOURCES += iverilog_dump.v 73 | COMPILE_ARGS += -s iverilog_dump 74 | endif 75 | else ifeq ($(SIM), verilator) 76 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 77 | 78 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 79 | 80 | ifeq ($(WAVES), 1) 81 | COMPILE_ARGS += --trace-fst 82 | endif 83 | endif 84 | 85 | include $(shell cocotb-config --makefiles)/Makefile.sim 86 | 87 | iverilog_dump.v: 88 | echo 'module iverilog_dump();' > $@ 89 | echo 'initial begin' >> $@ 90 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 91 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 92 | echo 'end' >> $@ 93 | echo 'endmodule' >> $@ 94 | 95 | clean:: 96 | @rm -rf iverilog_dump.v 97 | @rm -rf dump.fst $(TOPLEVEL).fst 98 | -------------------------------------------------------------------------------- /tb/axis_frame_length_adjust/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_frame_length_adjust 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DATA_WIDTH := 8 36 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 37 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 38 | export PARAM_ID_ENABLE := 1 39 | export PARAM_ID_WIDTH := 8 40 | export PARAM_DEST_ENABLE := 1 41 | export PARAM_DEST_WIDTH := 8 42 | export PARAM_USER_ENABLE := 1 43 | export PARAM_USER_WIDTH := 1 44 | export PARAM_LEN_WIDTH := 16 45 | 46 | ifeq ($(SIM), icarus) 47 | PLUSARGS += -fst 48 | 49 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 50 | 51 | ifeq ($(WAVES), 1) 52 | VERILOG_SOURCES += iverilog_dump.v 53 | COMPILE_ARGS += -s iverilog_dump 54 | endif 55 | else ifeq ($(SIM), verilator) 56 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 57 | 58 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 59 | 60 | ifeq ($(WAVES), 1) 61 | COMPILE_ARGS += --trace-fst 62 | endif 63 | endif 64 | 65 | include $(shell cocotb-config --makefiles)/Makefile.sim 66 | 67 | iverilog_dump.v: 68 | echo 'module iverilog_dump();' > $@ 69 | echo 'initial begin' >> $@ 70 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 71 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 72 | echo 'end' >> $@ 73 | echo 'endmodule' >> $@ 74 | 75 | clean:: 76 | @rm -rf iverilog_dump.v 77 | @rm -rf dump.fst $(TOPLEVEL).fst 78 | -------------------------------------------------------------------------------- /tb/axis_frame_length_adjust_fifo/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_frame_length_adjust_fifo 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).f 33 | 34 | # handle file list files 35 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 36 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 37 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 38 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 39 | 40 | # module parameters 41 | export PARAM_DATA_WIDTH := 8 42 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 43 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 44 | export PARAM_ID_ENABLE := 1 45 | export PARAM_ID_WIDTH := 8 46 | export PARAM_DEST_ENABLE := 1 47 | export PARAM_DEST_WIDTH := 8 48 | export PARAM_USER_ENABLE := 1 49 | export PARAM_USER_WIDTH := 1 50 | export PARAM_LEN_WIDTH := 16 51 | export PARAM_FRAME_FIFO_DEPTH := 1024 52 | export PARAM_HEADER_FIFO_DEPTH := 8 53 | 54 | ifeq ($(SIM), icarus) 55 | PLUSARGS += -fst 56 | 57 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 58 | 59 | ifeq ($(WAVES), 1) 60 | VERILOG_SOURCES += iverilog_dump.v 61 | COMPILE_ARGS += -s iverilog_dump 62 | endif 63 | else ifeq ($(SIM), verilator) 64 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 65 | 66 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 67 | 68 | ifeq ($(WAVES), 1) 69 | COMPILE_ARGS += --trace-fst 70 | endif 71 | endif 72 | 73 | include $(shell cocotb-config --makefiles)/Makefile.sim 74 | 75 | iverilog_dump.v: 76 | echo 'module iverilog_dump();' > $@ 77 | echo 'initial begin' >> $@ 78 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 79 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 80 | echo 'end' >> $@ 81 | echo 'endmodule' >> $@ 82 | 83 | clean:: 84 | @rm -rf iverilog_dump.v 85 | @rm -rf dump.fst $(TOPLEVEL).fst 86 | -------------------------------------------------------------------------------- /tb/axis_mux/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | export PORTS ?= 4 30 | 31 | DUT = axis_mux 32 | WRAPPER = $(DUT)_wrap_$(PORTS) 33 | TOPLEVEL = $(WRAPPER) 34 | MODULE = test_$(DUT) 35 | VERILOG_SOURCES += $(WRAPPER).v 36 | VERILOG_SOURCES += ../../rtl/$(DUT).v 37 | 38 | # module parameters 39 | export PARAM_DATA_WIDTH := 8 40 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 41 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 42 | export PARAM_ID_ENABLE := 1 43 | export PARAM_ID_WIDTH := 8 44 | export PARAM_DEST_ENABLE := 1 45 | export PARAM_DEST_WIDTH := 8 46 | export PARAM_USER_ENABLE := 1 47 | export PARAM_USER_WIDTH := 1 48 | 49 | ifeq ($(SIM), icarus) 50 | PLUSARGS += -fst 51 | 52 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 53 | 54 | ifeq ($(WAVES), 1) 55 | VERILOG_SOURCES += iverilog_dump.v 56 | COMPILE_ARGS += -s iverilog_dump 57 | endif 58 | else ifeq ($(SIM), verilator) 59 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 60 | 61 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 62 | 63 | ifeq ($(WAVES), 1) 64 | COMPILE_ARGS += --trace-fst 65 | endif 66 | endif 67 | 68 | include $(shell cocotb-config --makefiles)/Makefile.sim 69 | 70 | $(WRAPPER).v: ../../rtl/$(DUT)_wrap.py 71 | $< -p $(PORTS) 72 | 73 | iverilog_dump.v: 74 | echo 'module iverilog_dump();' > $@ 75 | echo 'initial begin' >> $@ 76 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 77 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 78 | echo 'end' >> $@ 79 | echo 'endmodule' >> $@ 80 | 81 | clean:: 82 | @rm -rf iverilog_dump.v 83 | @rm -rf dump.fst $(TOPLEVEL).fst 84 | @rm -rf *_wrap_*.v 85 | -------------------------------------------------------------------------------- /tb/axis_pipeline_fifo/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_pipeline_fifo 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DATA_WIDTH := 8 36 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 37 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 38 | export PARAM_LAST_ENABLE := 1 39 | export PARAM_ID_ENABLE := 1 40 | export PARAM_ID_WIDTH := 8 41 | export PARAM_DEST_ENABLE := 1 42 | export PARAM_DEST_WIDTH := 8 43 | export PARAM_USER_ENABLE := 1 44 | export PARAM_USER_WIDTH := 1 45 | export PARAM_LENGTH := 2 46 | 47 | ifeq ($(SIM), icarus) 48 | PLUSARGS += -fst 49 | 50 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 51 | 52 | ifeq ($(WAVES), 1) 53 | VERILOG_SOURCES += iverilog_dump.v 54 | COMPILE_ARGS += -s iverilog_dump 55 | endif 56 | else ifeq ($(SIM), verilator) 57 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 58 | 59 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 60 | 61 | ifeq ($(WAVES), 1) 62 | COMPILE_ARGS += --trace-fst 63 | endif 64 | endif 65 | 66 | include $(shell cocotb-config --makefiles)/Makefile.sim 67 | 68 | iverilog_dump.v: 69 | echo 'module iverilog_dump();' > $@ 70 | echo 'initial begin' >> $@ 71 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 72 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 73 | echo 'end' >> $@ 74 | echo 'endmodule' >> $@ 75 | 76 | clean:: 77 | @rm -rf iverilog_dump.v 78 | @rm -rf dump.fst $(TOPLEVEL).fst 79 | -------------------------------------------------------------------------------- /tb/axis_pipeline_register/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_pipeline_register 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).f 33 | 34 | # handle file list files 35 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 36 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 37 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 38 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 39 | 40 | # module parameters 41 | export PARAM_DATA_WIDTH := 8 42 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 43 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 44 | export PARAM_LAST_ENABLE := 1 45 | export PARAM_ID_ENABLE := 1 46 | export PARAM_ID_WIDTH := 8 47 | export PARAM_DEST_ENABLE := 1 48 | export PARAM_DEST_WIDTH := 8 49 | export PARAM_USER_ENABLE := 1 50 | export PARAM_USER_WIDTH := 1 51 | export PARAM_REG_TYPE := 2 52 | export PARAM_LENGTH := 2 53 | 54 | ifeq ($(SIM), icarus) 55 | PLUSARGS += -fst 56 | 57 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 58 | 59 | ifeq ($(WAVES), 1) 60 | VERILOG_SOURCES += iverilog_dump.v 61 | COMPILE_ARGS += -s iverilog_dump 62 | endif 63 | else ifeq ($(SIM), verilator) 64 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 65 | 66 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 67 | 68 | ifeq ($(WAVES), 1) 69 | COMPILE_ARGS += --trace-fst 70 | endif 71 | endif 72 | 73 | include $(shell cocotb-config --makefiles)/Makefile.sim 74 | 75 | iverilog_dump.v: 76 | echo 'module iverilog_dump();' > $@ 77 | echo 'initial begin' >> $@ 78 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 79 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 80 | echo 'end' >> $@ 81 | echo 'endmodule' >> $@ 82 | 83 | clean:: 84 | @rm -rf iverilog_dump.v 85 | @rm -rf dump.fst $(TOPLEVEL).fst 86 | -------------------------------------------------------------------------------- /tb/axis_ram_switch/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | export S_COUNT ?= 4 30 | export M_COUNT ?= 4 31 | 32 | DUT = axis_ram_switch 33 | WRAPPER = $(DUT)_wrap_$(S_COUNT)x$(M_COUNT) 34 | TOPLEVEL = $(WRAPPER) 35 | MODULE = test_$(DUT) 36 | VERILOG_SOURCES += $(WRAPPER).v 37 | VERILOG_SOURCES += ../../rtl/$(DUT).f 38 | 39 | # handle file list files 40 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 41 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 42 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 43 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 44 | 45 | # module parameters 46 | export PARAM_FIFO_DEPTH := 4096 47 | export PARAM_CMD_FIFO_DEPTH := 32 48 | export PARAM_SPEEDUP := 0 49 | export PARAM_S_DATA_WIDTH := 8 50 | export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) 51 | export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) 52 | export PARAM_M_DATA_WIDTH := 8 53 | export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) 54 | export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) 55 | export PARAM_ID_ENABLE := 1 56 | export PARAM_S_ID_WIDTH := 16 57 | export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") 58 | export PARAM_M_DEST_WIDTH := 8 59 | export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())") 60 | export PARAM_USER_ENABLE := 1 61 | export PARAM_USER_WIDTH := 1 62 | export PARAM_USER_BAD_FRAME_VALUE := 1 63 | export PARAM_USER_BAD_FRAME_MASK := 1 64 | export PARAM_DROP_BAD_FRAME := 0 65 | export PARAM_DROP_WHEN_FULL := 0 66 | export PARAM_UPDATE_TID := 1 67 | export PARAM_ARB_TYPE_ROUND_ROBIN := 1 68 | export PARAM_ARB_LSB_HIGH_PRIORITY := 1 69 | export PARAM_RAM_PIPELINE := 2 70 | 71 | ifeq ($(SIM), icarus) 72 | PLUSARGS += -fst 73 | 74 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 75 | 76 | ifeq ($(WAVES), 1) 77 | VERILOG_SOURCES += iverilog_dump.v 78 | COMPILE_ARGS += -s iverilog_dump 79 | endif 80 | else ifeq ($(SIM), verilator) 81 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 82 | 83 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 84 | 85 | ifeq ($(WAVES), 1) 86 | COMPILE_ARGS += --trace-fst 87 | endif 88 | endif 89 | 90 | include $(shell cocotb-config --makefiles)/Makefile.sim 91 | 92 | $(WRAPPER).v: ../../rtl/$(DUT)_wrap.py 93 | $< -p $(S_COUNT) $(M_COUNT) 94 | 95 | iverilog_dump.v: 96 | echo 'module iverilog_dump();' > $@ 97 | echo 'initial begin' >> $@ 98 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 99 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 100 | echo 'end' >> $@ 101 | echo 'endmodule' >> $@ 102 | 103 | clean:: 104 | @rm -rf iverilog_dump.v 105 | @rm -rf dump.fst $(TOPLEVEL).fst 106 | @rm -rf *_wrap_*.v 107 | -------------------------------------------------------------------------------- /tb/axis_rate_limit/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_rate_limit 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DATA_WIDTH := 8 36 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 37 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 38 | export PARAM_LAST_ENABLE := 1 39 | export PARAM_ID_ENABLE := 1 40 | export PARAM_ID_WIDTH := 8 41 | export PARAM_DEST_ENABLE := 1 42 | export PARAM_DEST_WIDTH := 8 43 | export PARAM_USER_ENABLE := 1 44 | export PARAM_USER_WIDTH := 1 45 | 46 | ifeq ($(SIM), icarus) 47 | PLUSARGS += -fst 48 | 49 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 50 | 51 | ifeq ($(WAVES), 1) 52 | VERILOG_SOURCES += iverilog_dump.v 53 | COMPILE_ARGS += -s iverilog_dump 54 | endif 55 | else ifeq ($(SIM), verilator) 56 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 57 | 58 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 59 | 60 | ifeq ($(WAVES), 1) 61 | COMPILE_ARGS += --trace-fst 62 | endif 63 | endif 64 | 65 | include $(shell cocotb-config --makefiles)/Makefile.sim 66 | 67 | iverilog_dump.v: 68 | echo 'module iverilog_dump();' > $@ 69 | echo 'initial begin' >> $@ 70 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 71 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 72 | echo 'end' >> $@ 73 | echo 'endmodule' >> $@ 74 | 75 | clean:: 76 | @rm -rf iverilog_dump.v 77 | @rm -rf dump.fst $(TOPLEVEL).fst 78 | -------------------------------------------------------------------------------- /tb/axis_register/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_register 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DATA_WIDTH := 8 36 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 37 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 38 | export PARAM_LAST_ENABLE := 1 39 | export PARAM_ID_ENABLE := 1 40 | export PARAM_ID_WIDTH := 8 41 | export PARAM_DEST_ENABLE := 1 42 | export PARAM_DEST_WIDTH := 8 43 | export PARAM_USER_ENABLE := 1 44 | export PARAM_USER_WIDTH := 1 45 | export PARAM_REG_TYPE := 2 46 | 47 | ifeq ($(SIM), icarus) 48 | PLUSARGS += -fst 49 | 50 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 51 | 52 | ifeq ($(WAVES), 1) 53 | VERILOG_SOURCES += iverilog_dump.v 54 | COMPILE_ARGS += -s iverilog_dump 55 | endif 56 | else ifeq ($(SIM), verilator) 57 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 58 | 59 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 60 | 61 | ifeq ($(WAVES), 1) 62 | COMPILE_ARGS += --trace-fst 63 | endif 64 | endif 65 | 66 | include $(shell cocotb-config --makefiles)/Makefile.sim 67 | 68 | iverilog_dump.v: 69 | echo 'module iverilog_dump();' > $@ 70 | echo 'initial begin' >> $@ 71 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 72 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 73 | echo 'end' >> $@ 74 | echo 'endmodule' >> $@ 75 | 76 | clean:: 77 | @rm -rf iverilog_dump.v 78 | @rm -rf dump.fst $(TOPLEVEL).fst 79 | -------------------------------------------------------------------------------- /tb/axis_srl_fifo/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_srl_fifo 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DEPTH := 1024 36 | export PARAM_DATA_WIDTH := 8 37 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 38 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 39 | export PARAM_ID_ENABLE := 1 40 | export PARAM_ID_WIDTH := 8 41 | export PARAM_DEST_ENABLE := 1 42 | export PARAM_DEST_WIDTH := 8 43 | export PARAM_USER_ENABLE := 1 44 | export PARAM_USER_WIDTH := 1 45 | 46 | ifeq ($(SIM), icarus) 47 | PLUSARGS += -fst 48 | 49 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 50 | 51 | ifeq ($(WAVES), 1) 52 | VERILOG_SOURCES += iverilog_dump.v 53 | COMPILE_ARGS += -s iverilog_dump 54 | endif 55 | else ifeq ($(SIM), verilator) 56 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 57 | 58 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 59 | 60 | ifeq ($(WAVES), 1) 61 | COMPILE_ARGS += --trace-fst 62 | endif 63 | endif 64 | 65 | include $(shell cocotb-config --makefiles)/Makefile.sim 66 | 67 | iverilog_dump.v: 68 | echo 'module iverilog_dump();' > $@ 69 | echo 'initial begin' >> $@ 70 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 71 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 72 | echo 'end' >> $@ 73 | echo 'endmodule' >> $@ 74 | 75 | clean:: 76 | @rm -rf iverilog_dump.v 77 | @rm -rf dump.fst $(TOPLEVEL).fst 78 | -------------------------------------------------------------------------------- /tb/axis_srl_register/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | DUT = axis_srl_register 30 | TOPLEVEL = $(DUT) 31 | MODULE = test_$(DUT) 32 | VERILOG_SOURCES += ../../rtl/$(DUT).v 33 | 34 | # module parameters 35 | export PARAM_DATA_WIDTH := 8 36 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 37 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 38 | export PARAM_LAST_ENABLE := 1 39 | export PARAM_ID_ENABLE := 1 40 | export PARAM_ID_WIDTH := 8 41 | export PARAM_DEST_ENABLE := 1 42 | export PARAM_DEST_WIDTH := 8 43 | export PARAM_USER_ENABLE := 1 44 | export PARAM_USER_WIDTH := 1 45 | 46 | ifeq ($(SIM), icarus) 47 | PLUSARGS += -fst 48 | 49 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 50 | 51 | ifeq ($(WAVES), 1) 52 | VERILOG_SOURCES += iverilog_dump.v 53 | COMPILE_ARGS += -s iverilog_dump 54 | endif 55 | else ifeq ($(SIM), verilator) 56 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 57 | 58 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 59 | 60 | ifeq ($(WAVES), 1) 61 | COMPILE_ARGS += --trace-fst 62 | endif 63 | endif 64 | 65 | include $(shell cocotb-config --makefiles)/Makefile.sim 66 | 67 | iverilog_dump.v: 68 | echo 'module iverilog_dump();' > $@ 69 | echo 'initial begin' >> $@ 70 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 71 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 72 | echo 'end' >> $@ 73 | echo 'endmodule' >> $@ 74 | 75 | clean:: 76 | @rm -rf iverilog_dump.v 77 | @rm -rf dump.fst $(TOPLEVEL).fst 78 | -------------------------------------------------------------------------------- /tb/axis_switch/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPLEVEL_LANG = verilog 22 | 23 | SIM ?= icarus 24 | WAVES ?= 0 25 | 26 | COCOTB_HDL_TIMEUNIT = 1ns 27 | COCOTB_HDL_TIMEPRECISION = 1ps 28 | 29 | export S_COUNT ?= 4 30 | export M_COUNT ?= 4 31 | 32 | DUT = axis_switch 33 | WRAPPER = $(DUT)_wrap_$(S_COUNT)x$(M_COUNT) 34 | TOPLEVEL = $(WRAPPER) 35 | MODULE = test_$(DUT) 36 | VERILOG_SOURCES += $(WRAPPER).v 37 | VERILOG_SOURCES += ../../rtl/$(DUT).f 38 | 39 | # handle file list files 40 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 41 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 42 | uniq = $(if $1,$(firstword $1) $(call uniq,$(filter-out $(firstword $1),$1))) 43 | VERILOG_SOURCES := $(call uniq,$(call process_f_files,$(VERILOG_SOURCES))) 44 | 45 | # module parameters 46 | export PARAM_DATA_WIDTH := 8 47 | export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) 48 | export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) 49 | export PARAM_ID_ENABLE := 1 50 | export PARAM_S_ID_WIDTH := 16 51 | export PARAM_M_ID_WIDTH := $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") 52 | export PARAM_M_DEST_WIDTH := 8 53 | export PARAM_S_DEST_WIDTH := $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(M_COUNT)-1).bit_length())") 54 | export PARAM_USER_ENABLE := 1 55 | export PARAM_USER_WIDTH := 1 56 | export PARAM_UPDATE_TID := 1 57 | export PARAM_S_REG_TYPE := 0 58 | export PARAM_M_REG_TYPE := 2 59 | export PARAM_ARB_TYPE_ROUND_ROBIN := 1 60 | export PARAM_ARB_LSB_HIGH_PRIORITY := 1 61 | 62 | ifeq ($(SIM), icarus) 63 | PLUSARGS += -fst 64 | 65 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 66 | 67 | ifeq ($(WAVES), 1) 68 | VERILOG_SOURCES += iverilog_dump.v 69 | COMPILE_ARGS += -s iverilog_dump 70 | endif 71 | else ifeq ($(SIM), verilator) 72 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 73 | 74 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 75 | 76 | ifeq ($(WAVES), 1) 77 | COMPILE_ARGS += --trace-fst 78 | endif 79 | endif 80 | 81 | include $(shell cocotb-config --makefiles)/Makefile.sim 82 | 83 | $(WRAPPER).v: ../../rtl/$(DUT)_wrap.py 84 | $< -p $(S_COUNT) $(M_COUNT) 85 | 86 | iverilog_dump.v: 87 | echo 'module iverilog_dump();' > $@ 88 | echo 'initial begin' >> $@ 89 | echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ 90 | echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ 91 | echo 'end' >> $@ 92 | echo 'endmodule' >> $@ 93 | 94 | clean:: 95 | @rm -rf iverilog_dump.v 96 | @rm -rf dump.fst $(TOPLEVEL).fst 97 | @rm -rf *_wrap_*.v 98 | -------------------------------------------------------------------------------- /tb/test_arbiter.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for arbiter 31 | */ 32 | module test_arbiter; 33 | 34 | // Parameters 35 | localparam PORTS = 32; 36 | localparam ARB_TYPE_ROUND_ROBIN = 0; 37 | localparam ARB_BLOCK = 1; 38 | localparam ARB_BLOCK_ACK = 0; 39 | localparam ARB_LSB_HIGH_PRIORITY = 0; 40 | 41 | // Inputs 42 | reg clk = 0; 43 | reg rst = 0; 44 | reg [7:0] current_test = 0; 45 | 46 | reg [PORTS-1:0] request = 0; 47 | reg [PORTS-1:0] acknowledge = 0; 48 | 49 | // Outputs 50 | wire [PORTS-1:0] grant; 51 | wire grant_valid; 52 | wire [$clog2(PORTS)-1:0] grant_encoded; 53 | 54 | initial begin 55 | // myhdl integration 56 | $from_myhdl( 57 | clk, 58 | rst, 59 | current_test, 60 | request, 61 | acknowledge 62 | ); 63 | $to_myhdl( 64 | grant, 65 | grant_valid, 66 | grant_encoded 67 | ); 68 | 69 | // dump file 70 | $dumpfile("test_arbiter.lxt"); 71 | $dumpvars(0, test_arbiter); 72 | end 73 | 74 | arbiter #( 75 | .PORTS(PORTS), 76 | .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN), 77 | .ARB_BLOCK(ARB_BLOCK), 78 | .ARB_BLOCK_ACK(ARB_BLOCK_ACK), 79 | .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) 80 | ) 81 | UUT ( 82 | .clk(clk), 83 | .rst(rst), 84 | .request(request), 85 | .acknowledge(acknowledge), 86 | .grant(grant), 87 | .grant_valid(grant_valid), 88 | .grant_encoded(grant_encoded) 89 | ); 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /tb/test_arbiter_rr.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for arbiter 31 | */ 32 | module test_arbiter_rr; 33 | 34 | // Parameters 35 | localparam PORTS = 32; 36 | localparam ARB_TYPE_ROUND_ROBIN = 1; 37 | localparam ARB_BLOCK = 1; 38 | localparam ARB_BLOCK_ACK = 0; 39 | localparam ARB_LSB_HIGH_PRIORITY = 0; 40 | 41 | // Inputs 42 | reg clk = 0; 43 | reg rst = 0; 44 | reg [7:0] current_test = 0; 45 | 46 | reg [PORTS-1:0] request = 0; 47 | reg [PORTS-1:0] acknowledge = 0; 48 | 49 | // Outputs 50 | wire [PORTS-1:0] grant; 51 | wire grant_valid; 52 | wire [$clog2(PORTS)-1:0] grant_encoded; 53 | 54 | initial begin 55 | // myhdl integration 56 | $from_myhdl( 57 | clk, 58 | rst, 59 | current_test, 60 | request, 61 | acknowledge 62 | ); 63 | $to_myhdl( 64 | grant, 65 | grant_valid, 66 | grant_encoded 67 | ); 68 | 69 | // dump file 70 | $dumpfile("test_arbiter_rr.lxt"); 71 | $dumpvars(0, test_arbiter_rr); 72 | end 73 | 74 | arbiter #( 75 | .PORTS(PORTS), 76 | .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN), 77 | .ARB_BLOCK(ARB_BLOCK), 78 | .ARB_BLOCK_ACK(ARB_BLOCK_ACK), 79 | .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) 80 | ) 81 | UUT ( 82 | .clk(clk), 83 | .rst(rst), 84 | .request(request), 85 | .acknowledge(acknowledge), 86 | .grant(grant), 87 | .grant_valid(grant_valid), 88 | .grant_encoded(grant_encoded) 89 | ); 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /tb/test_axis_adapter_64_8.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_adapter 31 | */ 32 | module test_axis_adapter_64_8; 33 | 34 | // Parameters 35 | parameter S_DATA_WIDTH = 64; 36 | parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8); 37 | parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8); 38 | parameter M_DATA_WIDTH = 8; 39 | parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8); 40 | parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8); 41 | parameter ID_ENABLE = 1; 42 | parameter ID_WIDTH = 8; 43 | parameter DEST_ENABLE = 1; 44 | parameter DEST_WIDTH = 8; 45 | parameter USER_ENABLE = 1; 46 | parameter USER_WIDTH = 1; 47 | 48 | // Inputs 49 | reg clk = 0; 50 | reg rst = 0; 51 | reg [7:0] current_test = 0; 52 | 53 | reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0; 54 | reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0; 55 | reg s_axis_tvalid = 0; 56 | reg s_axis_tlast = 0; 57 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 58 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 59 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 60 | reg m_axis_tready = 0; 61 | 62 | // Outputs 63 | wire s_axis_tready; 64 | wire [M_DATA_WIDTH-1:0] m_axis_tdata; 65 | wire [M_KEEP_WIDTH-1:0] m_axis_tkeep; 66 | wire m_axis_tvalid; 67 | wire m_axis_tlast; 68 | wire [ID_WIDTH-1:0] m_axis_tid; 69 | wire [DEST_WIDTH-1:0] m_axis_tdest; 70 | wire [USER_WIDTH-1:0] m_axis_tuser; 71 | 72 | initial begin 73 | // myhdl integration 74 | $from_myhdl( 75 | clk, 76 | rst, 77 | current_test, 78 | s_axis_tdata, 79 | s_axis_tkeep, 80 | s_axis_tvalid, 81 | s_axis_tlast, 82 | s_axis_tid, 83 | s_axis_tdest, 84 | s_axis_tuser, 85 | m_axis_tready 86 | ); 87 | $to_myhdl( 88 | s_axis_tready, 89 | m_axis_tdata, 90 | m_axis_tkeep, 91 | m_axis_tvalid, 92 | m_axis_tlast, 93 | m_axis_tid, 94 | m_axis_tdest, 95 | m_axis_tuser 96 | ); 97 | 98 | // dump file 99 | $dumpfile("test_axis_adapter_64_8.lxt"); 100 | $dumpvars(0, test_axis_adapter_64_8); 101 | end 102 | 103 | axis_adapter #( 104 | .S_DATA_WIDTH(S_DATA_WIDTH), 105 | .S_KEEP_ENABLE(S_KEEP_ENABLE), 106 | .S_KEEP_WIDTH(S_KEEP_WIDTH), 107 | .M_DATA_WIDTH(M_DATA_WIDTH), 108 | .M_KEEP_ENABLE(M_KEEP_ENABLE), 109 | .M_KEEP_WIDTH(M_KEEP_WIDTH), 110 | .ID_ENABLE(ID_ENABLE), 111 | .ID_WIDTH(ID_WIDTH), 112 | .DEST_ENABLE(DEST_ENABLE), 113 | .DEST_WIDTH(DEST_WIDTH), 114 | .USER_ENABLE(USER_ENABLE), 115 | .USER_WIDTH(USER_WIDTH) 116 | ) 117 | UUT ( 118 | .clk(clk), 119 | .rst(rst), 120 | // AXI input 121 | .s_axis_tdata(s_axis_tdata), 122 | .s_axis_tkeep(s_axis_tkeep), 123 | .s_axis_tvalid(s_axis_tvalid), 124 | .s_axis_tready(s_axis_tready), 125 | .s_axis_tlast(s_axis_tlast), 126 | .s_axis_tid(s_axis_tid), 127 | .s_axis_tdest(s_axis_tdest), 128 | .s_axis_tuser(s_axis_tuser), 129 | // AXI output 130 | .m_axis_tdata(m_axis_tdata), 131 | .m_axis_tkeep(m_axis_tkeep), 132 | .m_axis_tvalid(m_axis_tvalid), 133 | .m_axis_tready(m_axis_tready), 134 | .m_axis_tlast(m_axis_tlast), 135 | .m_axis_tid(m_axis_tid), 136 | .m_axis_tdest(m_axis_tdest), 137 | .m_axis_tuser(m_axis_tuser) 138 | ); 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /tb/test_axis_adapter_8_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_adapter 31 | */ 32 | module test_axis_adapter_8_64; 33 | 34 | // Parameters 35 | parameter S_DATA_WIDTH = 8; 36 | parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8); 37 | parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8); 38 | parameter M_DATA_WIDTH = 64; 39 | parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8); 40 | parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8); 41 | parameter ID_ENABLE = 1; 42 | parameter ID_WIDTH = 8; 43 | parameter DEST_ENABLE = 1; 44 | parameter DEST_WIDTH = 8; 45 | parameter USER_ENABLE = 1; 46 | parameter USER_WIDTH = 1; 47 | 48 | // Inputs 49 | reg clk = 0; 50 | reg rst = 0; 51 | reg [7:0] current_test = 0; 52 | 53 | reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0; 54 | reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0; 55 | reg s_axis_tvalid = 0; 56 | reg s_axis_tlast = 0; 57 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 58 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 59 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 60 | reg m_axis_tready = 0; 61 | 62 | // Outputs 63 | wire s_axis_tready; 64 | wire [M_DATA_WIDTH-1:0] m_axis_tdata; 65 | wire [M_KEEP_WIDTH-1:0] m_axis_tkeep; 66 | wire m_axis_tvalid; 67 | wire m_axis_tlast; 68 | wire [ID_WIDTH-1:0] m_axis_tid; 69 | wire [DEST_WIDTH-1:0] m_axis_tdest; 70 | wire [USER_WIDTH-1:0] m_axis_tuser; 71 | 72 | initial begin 73 | // myhdl integration 74 | $from_myhdl( 75 | clk, 76 | rst, 77 | current_test, 78 | s_axis_tdata, 79 | s_axis_tkeep, 80 | s_axis_tvalid, 81 | s_axis_tlast, 82 | s_axis_tid, 83 | s_axis_tdest, 84 | s_axis_tuser, 85 | m_axis_tready 86 | ); 87 | $to_myhdl( 88 | s_axis_tready, 89 | m_axis_tdata, 90 | m_axis_tkeep, 91 | m_axis_tvalid, 92 | m_axis_tlast, 93 | m_axis_tid, 94 | m_axis_tdest, 95 | m_axis_tuser 96 | ); 97 | 98 | // dump file 99 | $dumpfile("test_axis_adapter_8_64.lxt"); 100 | $dumpvars(0, test_axis_adapter_8_64); 101 | end 102 | 103 | axis_adapter #( 104 | .S_DATA_WIDTH(S_DATA_WIDTH), 105 | .S_KEEP_ENABLE(S_KEEP_ENABLE), 106 | .S_KEEP_WIDTH(S_KEEP_WIDTH), 107 | .M_DATA_WIDTH(M_DATA_WIDTH), 108 | .M_KEEP_ENABLE(M_KEEP_ENABLE), 109 | .M_KEEP_WIDTH(M_KEEP_WIDTH), 110 | .ID_ENABLE(ID_ENABLE), 111 | .ID_WIDTH(ID_WIDTH), 112 | .DEST_ENABLE(DEST_ENABLE), 113 | .DEST_WIDTH(DEST_WIDTH), 114 | .USER_ENABLE(USER_ENABLE), 115 | .USER_WIDTH(USER_WIDTH) 116 | ) 117 | UUT ( 118 | .clk(clk), 119 | .rst(rst), 120 | // AXI input 121 | .s_axis_tdata(s_axis_tdata), 122 | .s_axis_tkeep(s_axis_tkeep), 123 | .s_axis_tvalid(s_axis_tvalid), 124 | .s_axis_tready(s_axis_tready), 125 | .s_axis_tlast(s_axis_tlast), 126 | .s_axis_tid(s_axis_tid), 127 | .s_axis_tdest(s_axis_tdest), 128 | .s_axis_tuser(s_axis_tuser), 129 | // AXI output 130 | .m_axis_tdata(m_axis_tdata), 131 | .m_axis_tkeep(m_axis_tkeep), 132 | .m_axis_tvalid(m_axis_tvalid), 133 | .m_axis_tready(m_axis_tready), 134 | .m_axis_tlast(m_axis_tlast), 135 | .m_axis_tid(m_axis_tid), 136 | .m_axis_tdest(m_axis_tdest), 137 | .m_axis_tuser(m_axis_tuser) 138 | ); 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /tb/test_axis_arb_mux_4.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_arb_mux 31 | */ 32 | module test_axis_arb_mux_4; 33 | 34 | // Parameters 35 | parameter S_COUNT = 4; 36 | parameter DATA_WIDTH = 8; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | parameter LAST_ENABLE = 1; 46 | parameter ARB_TYPE_ROUND_ROBIN = 0; 47 | parameter ARB_LSB_HIGH_PRIORITY = 1; 48 | 49 | // Inputs 50 | reg clk = 0; 51 | reg rst = 0; 52 | reg [7:0] current_test = 0; 53 | 54 | reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0; 55 | reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0; 56 | reg [S_COUNT-1:0] s_axis_tvalid = 0; 57 | reg [S_COUNT-1:0] s_axis_tlast = 0; 58 | reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0; 59 | reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0; 60 | reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0; 61 | 62 | reg m_axis_tready = 0; 63 | 64 | // Outputs 65 | wire [S_COUNT-1:0] s_axis_tready; 66 | 67 | wire [DATA_WIDTH-1:0] m_axis_tdata; 68 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 69 | wire m_axis_tvalid; 70 | wire m_axis_tlast; 71 | wire [ID_WIDTH-1:0] m_axis_tid; 72 | wire [DEST_WIDTH-1:0] m_axis_tdest; 73 | wire [USER_WIDTH-1:0] m_axis_tuser; 74 | 75 | initial begin 76 | // myhdl integration 77 | $from_myhdl( 78 | clk, 79 | rst, 80 | current_test, 81 | s_axis_tdata, 82 | s_axis_tkeep, 83 | s_axis_tvalid, 84 | s_axis_tlast, 85 | s_axis_tid, 86 | s_axis_tdest, 87 | s_axis_tuser, 88 | m_axis_tready 89 | ); 90 | $to_myhdl( 91 | s_axis_tready, 92 | m_axis_tdata, 93 | m_axis_tkeep, 94 | m_axis_tvalid, 95 | m_axis_tlast, 96 | m_axis_tid, 97 | m_axis_tdest, 98 | m_axis_tuser 99 | ); 100 | 101 | // dump file 102 | $dumpfile("test_axis_arb_mux_4.lxt"); 103 | $dumpvars(0, test_axis_arb_mux_4); 104 | end 105 | 106 | axis_arb_mux #( 107 | .S_COUNT(S_COUNT), 108 | .DATA_WIDTH(DATA_WIDTH), 109 | .KEEP_ENABLE(KEEP_ENABLE), 110 | .KEEP_WIDTH(KEEP_WIDTH), 111 | .ID_ENABLE(ID_ENABLE), 112 | .ID_WIDTH(ID_WIDTH), 113 | .DEST_ENABLE(DEST_ENABLE), 114 | .DEST_WIDTH(DEST_WIDTH), 115 | .USER_ENABLE(USER_ENABLE), 116 | .USER_WIDTH(USER_WIDTH), 117 | .LAST_ENABLE(LAST_ENABLE), 118 | .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN), 119 | .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) 120 | ) 121 | UUT ( 122 | .clk(clk), 123 | .rst(rst), 124 | // AXI inputs 125 | .s_axis_tdata(s_axis_tdata), 126 | .s_axis_tkeep(s_axis_tkeep), 127 | .s_axis_tvalid(s_axis_tvalid), 128 | .s_axis_tready(s_axis_tready), 129 | .s_axis_tlast(s_axis_tlast), 130 | .s_axis_tid(s_axis_tid), 131 | .s_axis_tdest(s_axis_tdest), 132 | .s_axis_tuser(s_axis_tuser), 133 | // AXI output 134 | .m_axis_tdata(m_axis_tdata), 135 | .m_axis_tkeep(m_axis_tkeep), 136 | .m_axis_tvalid(m_axis_tvalid), 137 | .m_axis_tready(m_axis_tready), 138 | .m_axis_tlast(m_axis_tlast), 139 | .m_axis_tid(m_axis_tid), 140 | .m_axis_tdest(m_axis_tdest), 141 | .m_axis_tuser(m_axis_tuser) 142 | ); 143 | 144 | endmodule 145 | -------------------------------------------------------------------------------- /tb/test_axis_broadcast_4.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2019 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_broadcast 31 | */ 32 | module test_axis_broadcast_4; 33 | 34 | // Parameters 35 | parameter M_COUNT = 4; 36 | parameter DATA_WIDTH = 8; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter LAST_ENABLE = 1; 40 | parameter ID_ENABLE = 1; 41 | parameter ID_WIDTH = 8; 42 | parameter DEST_ENABLE = 1; 43 | parameter DEST_WIDTH = 8; 44 | parameter USER_ENABLE = 1; 45 | parameter USER_WIDTH = 1; 46 | 47 | // Inputs 48 | reg clk = 0; 49 | reg rst = 0; 50 | reg [7:0] current_test = 0; 51 | 52 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 53 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 54 | reg s_axis_tvalid = 0; 55 | reg s_axis_tlast = 0; 56 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 57 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 58 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 59 | 60 | reg [M_COUNT-1:0] m_axis_tready = 0; 61 | 62 | // Outputs 63 | wire s_axis_tready; 64 | 65 | wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata; 66 | wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep; 67 | wire [M_COUNT-1:0] m_axis_tvalid; 68 | wire [M_COUNT-1:0] m_axis_tlast; 69 | wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid; 70 | wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest; 71 | wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser; 72 | 73 | initial begin 74 | // myhdl integration 75 | $from_myhdl( 76 | clk, 77 | rst, 78 | current_test, 79 | s_axis_tdata, 80 | s_axis_tkeep, 81 | s_axis_tvalid, 82 | s_axis_tlast, 83 | s_axis_tid, 84 | s_axis_tdest, 85 | s_axis_tuser, 86 | m_axis_tready 87 | ); 88 | $to_myhdl( 89 | s_axis_tready, 90 | m_axis_tdata, 91 | m_axis_tkeep, 92 | m_axis_tvalid, 93 | m_axis_tlast, 94 | m_axis_tid, 95 | m_axis_tdest, 96 | m_axis_tuser 97 | ); 98 | 99 | // dump file 100 | $dumpfile("test_axis_broadcast_4.lxt"); 101 | $dumpvars(0, test_axis_broadcast_4); 102 | end 103 | 104 | axis_broadcast #( 105 | .M_COUNT(M_COUNT), 106 | .DATA_WIDTH(DATA_WIDTH), 107 | .KEEP_ENABLE(KEEP_ENABLE), 108 | .KEEP_WIDTH(KEEP_WIDTH), 109 | .LAST_ENABLE(LAST_ENABLE), 110 | .ID_ENABLE(ID_ENABLE), 111 | .ID_WIDTH(ID_WIDTH), 112 | .DEST_ENABLE(DEST_ENABLE), 113 | .DEST_WIDTH(DEST_WIDTH), 114 | .USER_ENABLE(USER_ENABLE), 115 | .USER_WIDTH(USER_WIDTH) 116 | ) 117 | UUT ( 118 | .clk(clk), 119 | .rst(rst), 120 | // AXI input 121 | .s_axis_tdata(s_axis_tdata), 122 | .s_axis_tkeep(s_axis_tkeep), 123 | .s_axis_tvalid(s_axis_tvalid), 124 | .s_axis_tready(s_axis_tready), 125 | .s_axis_tlast(s_axis_tlast), 126 | .s_axis_tid(s_axis_tid), 127 | .s_axis_tdest(s_axis_tdest), 128 | .s_axis_tuser(s_axis_tuser), 129 | // AXI outputs 130 | .m_axis_tdata(m_axis_tdata), 131 | .m_axis_tkeep(m_axis_tkeep), 132 | .m_axis_tvalid(m_axis_tvalid), 133 | .m_axis_tready(m_axis_tready), 134 | .m_axis_tlast(m_axis_tlast), 135 | .m_axis_tid(m_axis_tid), 136 | .m_axis_tdest(m_axis_tdest), 137 | .m_axis_tuser(m_axis_tuser) 138 | ); 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /tb/test_axis_cobs_decode.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2016-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_cobs_decode 31 | */ 32 | module test_axis_cobs_decode; 33 | 34 | // Parameters 35 | 36 | // Inputs 37 | reg clk = 0; 38 | reg rst = 0; 39 | reg [7:0] current_test = 0; 40 | 41 | reg [7:0] s_axis_tdata = 0; 42 | reg s_axis_tvalid = 0; 43 | reg s_axis_tlast = 0; 44 | reg s_axis_tuser = 0; 45 | reg m_axis_tready = 0; 46 | 47 | // Outputs 48 | wire s_axis_tready; 49 | wire [7:0] m_axis_tdata; 50 | wire m_axis_tvalid; 51 | wire m_axis_tlast; 52 | wire m_axis_tuser; 53 | 54 | initial begin 55 | // myhdl integration 56 | $from_myhdl( 57 | clk, 58 | rst, 59 | current_test, 60 | s_axis_tdata, 61 | s_axis_tvalid, 62 | s_axis_tlast, 63 | s_axis_tuser, 64 | m_axis_tready 65 | ); 66 | $to_myhdl( 67 | s_axis_tready, 68 | m_axis_tdata, 69 | m_axis_tvalid, 70 | m_axis_tlast, 71 | m_axis_tuser 72 | ); 73 | 74 | // dump file 75 | $dumpfile("test_axis_cobs_decode.lxt"); 76 | $dumpvars(0, test_axis_cobs_decode); 77 | end 78 | 79 | axis_cobs_decode 80 | UUT ( 81 | .clk(clk), 82 | .rst(rst), 83 | .s_axis_tdata(s_axis_tdata), 84 | .s_axis_tvalid(s_axis_tvalid), 85 | .s_axis_tready(s_axis_tready), 86 | .s_axis_tlast(s_axis_tlast), 87 | .s_axis_tuser(s_axis_tuser), 88 | .m_axis_tdata(m_axis_tdata), 89 | .m_axis_tvalid(m_axis_tvalid), 90 | .m_axis_tready(m_axis_tready), 91 | .m_axis_tlast(m_axis_tlast), 92 | .m_axis_tuser(m_axis_tuser) 93 | ); 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /tb/test_axis_cobs_encode.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2016-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_cobs_encode 31 | */ 32 | module test_axis_cobs_encode; 33 | 34 | // Parameters 35 | parameter APPEND_ZERO = 0; 36 | 37 | // Inputs 38 | reg clk = 0; 39 | reg rst = 0; 40 | reg [7:0] current_test = 0; 41 | 42 | reg [7:0] s_axis_tdata = 0; 43 | reg s_axis_tvalid = 0; 44 | reg s_axis_tlast = 0; 45 | reg s_axis_tuser = 0; 46 | reg m_axis_tready = 0; 47 | 48 | // Outputs 49 | wire s_axis_tready; 50 | wire [7:0] m_axis_tdata; 51 | wire m_axis_tvalid; 52 | wire m_axis_tlast; 53 | wire m_axis_tuser; 54 | 55 | initial begin 56 | // myhdl integration 57 | $from_myhdl( 58 | clk, 59 | rst, 60 | current_test, 61 | s_axis_tdata, 62 | s_axis_tvalid, 63 | s_axis_tlast, 64 | s_axis_tuser, 65 | m_axis_tready 66 | ); 67 | $to_myhdl( 68 | s_axis_tready, 69 | m_axis_tdata, 70 | m_axis_tvalid, 71 | m_axis_tlast, 72 | m_axis_tuser 73 | ); 74 | 75 | // dump file 76 | $dumpfile("test_axis_cobs_encode.lxt"); 77 | $dumpvars(0, test_axis_cobs_encode); 78 | end 79 | 80 | axis_cobs_encode #( 81 | .APPEND_ZERO(APPEND_ZERO) 82 | ) 83 | UUT ( 84 | .clk(clk), 85 | .rst(rst), 86 | .s_axis_tdata(s_axis_tdata), 87 | .s_axis_tvalid(s_axis_tvalid), 88 | .s_axis_tready(s_axis_tready), 89 | .s_axis_tlast(s_axis_tlast), 90 | .s_axis_tuser(s_axis_tuser), 91 | .m_axis_tdata(m_axis_tdata), 92 | .m_axis_tvalid(m_axis_tvalid), 93 | .m_axis_tready(m_axis_tready), 94 | .m_axis_tlast(m_axis_tlast), 95 | .m_axis_tuser(m_axis_tuser) 96 | ); 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /tb/test_axis_cobs_encode_zero_frame.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2016-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_cobs_encode 31 | */ 32 | module test_axis_cobs_encode_zero_frame; 33 | 34 | // Parameters 35 | parameter APPEND_ZERO = 1; 36 | 37 | // Inputs 38 | reg clk = 0; 39 | reg rst = 0; 40 | reg [7:0] current_test = 0; 41 | 42 | reg [7:0] s_axis_tdata = 0; 43 | reg s_axis_tvalid = 0; 44 | reg s_axis_tlast = 0; 45 | reg s_axis_tuser = 0; 46 | reg m_axis_tready = 0; 47 | 48 | // Outputs 49 | wire s_axis_tready; 50 | wire [7:0] m_axis_tdata; 51 | wire m_axis_tvalid; 52 | wire m_axis_tlast; 53 | wire m_axis_tuser; 54 | 55 | initial begin 56 | // myhdl integration 57 | $from_myhdl( 58 | clk, 59 | rst, 60 | current_test, 61 | s_axis_tdata, 62 | s_axis_tvalid, 63 | s_axis_tlast, 64 | s_axis_tuser, 65 | m_axis_tready 66 | ); 67 | $to_myhdl( 68 | s_axis_tready, 69 | m_axis_tdata, 70 | m_axis_tvalid, 71 | m_axis_tlast, 72 | m_axis_tuser 73 | ); 74 | 75 | // dump file 76 | $dumpfile("test_axis_cobs_encode_zero_frame.lxt"); 77 | $dumpvars(0, test_axis_cobs_encode_zero_frame); 78 | end 79 | 80 | axis_cobs_encode #( 81 | .APPEND_ZERO(APPEND_ZERO) 82 | ) 83 | UUT ( 84 | .clk(clk), 85 | .rst(rst), 86 | .s_axis_tdata(s_axis_tdata), 87 | .s_axis_tvalid(s_axis_tvalid), 88 | .s_axis_tready(s_axis_tready), 89 | .s_axis_tlast(s_axis_tlast), 90 | .s_axis_tuser(s_axis_tuser), 91 | .m_axis_tdata(m_axis_tdata), 92 | .m_axis_tvalid(m_axis_tvalid), 93 | .m_axis_tready(m_axis_tready), 94 | .m_axis_tlast(m_axis_tlast), 95 | .m_axis_tuser(m_axis_tuser) 96 | ); 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /tb/test_axis_crosspoint_4x4.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_crosspoint 31 | */ 32 | module test_axis_crosspoint_4x4; 33 | 34 | // Parameters 35 | parameter S_COUNT = 4; 36 | parameter M_COUNT = 4; 37 | parameter DATA_WIDTH = 8; 38 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 39 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 40 | parameter LAST_ENABLE = 1; 41 | parameter ID_ENABLE = 1; 42 | parameter ID_WIDTH = 8; 43 | parameter DEST_ENABLE = 1; 44 | parameter DEST_WIDTH = 8; 45 | parameter USER_ENABLE = 1; 46 | parameter USER_WIDTH = 1; 47 | 48 | // Inputs 49 | reg clk = 0; 50 | reg rst = 0; 51 | reg [7:0] current_test = 0; 52 | 53 | reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0; 54 | reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0; 55 | reg [S_COUNT-1:0] s_axis_tvalid = 0; 56 | reg [S_COUNT-1:0] s_axis_tlast = 0; 57 | reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0; 58 | reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0; 59 | reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0; 60 | 61 | reg [M_COUNT*$clog2(S_COUNT)-1:0] select = 0; 62 | 63 | // Outputs 64 | wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata; 65 | wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep; 66 | wire [M_COUNT-1:0] m_axis_tvalid; 67 | wire [M_COUNT-1:0] m_axis_tlast; 68 | wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid; 69 | wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest; 70 | wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser; 71 | 72 | initial begin 73 | // myhdl integration 74 | $from_myhdl( 75 | clk, 76 | rst, 77 | current_test, 78 | s_axis_tdata, 79 | s_axis_tkeep, 80 | s_axis_tvalid, 81 | s_axis_tlast, 82 | s_axis_tid, 83 | s_axis_tdest, 84 | s_axis_tuser, 85 | select 86 | ); 87 | $to_myhdl( 88 | m_axis_tdata, 89 | m_axis_tkeep, 90 | m_axis_tvalid, 91 | m_axis_tlast, 92 | m_axis_tid, 93 | m_axis_tdest, 94 | m_axis_tuser 95 | ); 96 | 97 | // dump file 98 | $dumpfile("test_axis_crosspoint_4x4.lxt"); 99 | $dumpvars(0, test_axis_crosspoint_4x4); 100 | end 101 | 102 | axis_crosspoint #( 103 | .S_COUNT(S_COUNT), 104 | .M_COUNT(M_COUNT), 105 | .DATA_WIDTH(DATA_WIDTH), 106 | .KEEP_ENABLE(KEEP_ENABLE), 107 | .KEEP_WIDTH(KEEP_WIDTH), 108 | .LAST_ENABLE(LAST_ENABLE), 109 | .ID_ENABLE(ID_ENABLE), 110 | .ID_WIDTH(ID_WIDTH), 111 | .DEST_ENABLE(DEST_ENABLE), 112 | .DEST_WIDTH(DEST_WIDTH), 113 | .USER_ENABLE(USER_ENABLE), 114 | .USER_WIDTH(USER_WIDTH) 115 | ) 116 | UUT ( 117 | .clk(clk), 118 | .rst(rst), 119 | // AXI inputs 120 | .s_axis_tdata(s_axis_tdata), 121 | .s_axis_tkeep(s_axis_tkeep), 122 | .s_axis_tvalid(s_axis_tvalid), 123 | .s_axis_tlast(s_axis_tlast), 124 | .s_axis_tid(s_axis_tid), 125 | .s_axis_tdest(s_axis_tdest), 126 | .s_axis_tuser(s_axis_tuser), 127 | // AXI output 128 | .m_axis_tdata(m_axis_tdata), 129 | .m_axis_tkeep(m_axis_tkeep), 130 | .m_axis_tvalid(m_axis_tvalid), 131 | .m_axis_tlast(m_axis_tlast), 132 | .m_axis_tid(m_axis_tid), 133 | .m_axis_tdest(m_axis_tdest), 134 | .m_axis_tuser(m_axis_tuser), 135 | // Control 136 | .select(select) 137 | ); 138 | 139 | endmodule 140 | -------------------------------------------------------------------------------- /tb/test_axis_crosspoint_4x4_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_crosspoint 31 | */ 32 | module test_axis_crosspoint_4x4_64; 33 | 34 | // Parameters 35 | parameter S_COUNT = 4; 36 | parameter M_COUNT = 4; 37 | parameter DATA_WIDTH = 64; 38 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 39 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 40 | parameter LAST_ENABLE = 1; 41 | parameter ID_ENABLE = 1; 42 | parameter ID_WIDTH = 8; 43 | parameter DEST_ENABLE = 1; 44 | parameter DEST_WIDTH = 8; 45 | parameter USER_ENABLE = 1; 46 | parameter USER_WIDTH = 1; 47 | 48 | // Inputs 49 | reg clk = 0; 50 | reg rst = 0; 51 | reg [7:0] current_test = 0; 52 | 53 | reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0; 54 | reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0; 55 | reg [S_COUNT-1:0] s_axis_tvalid = 0; 56 | reg [S_COUNT-1:0] s_axis_tlast = 0; 57 | reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0; 58 | reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0; 59 | reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0; 60 | 61 | reg [M_COUNT*$clog2(S_COUNT)-1:0] select = 0; 62 | 63 | // Outputs 64 | wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata; 65 | wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep; 66 | wire [M_COUNT-1:0] m_axis_tvalid; 67 | wire [M_COUNT-1:0] m_axis_tlast; 68 | wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid; 69 | wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest; 70 | wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser; 71 | 72 | initial begin 73 | // myhdl integration 74 | $from_myhdl( 75 | clk, 76 | rst, 77 | current_test, 78 | s_axis_tdata, 79 | s_axis_tkeep, 80 | s_axis_tvalid, 81 | s_axis_tlast, 82 | s_axis_tid, 83 | s_axis_tdest, 84 | s_axis_tuser, 85 | select 86 | ); 87 | $to_myhdl( 88 | m_axis_tdata, 89 | m_axis_tkeep, 90 | m_axis_tvalid, 91 | m_axis_tlast, 92 | m_axis_tid, 93 | m_axis_tdest, 94 | m_axis_tuser 95 | ); 96 | 97 | // dump file 98 | $dumpfile("test_axis_crosspoint_4x4_64.lxt"); 99 | $dumpvars(0, test_axis_crosspoint_4x4_64); 100 | end 101 | 102 | axis_crosspoint #( 103 | .S_COUNT(S_COUNT), 104 | .M_COUNT(M_COUNT), 105 | .DATA_WIDTH(DATA_WIDTH), 106 | .KEEP_ENABLE(KEEP_ENABLE), 107 | .KEEP_WIDTH(KEEP_WIDTH), 108 | .LAST_ENABLE(LAST_ENABLE), 109 | .ID_ENABLE(ID_ENABLE), 110 | .ID_WIDTH(ID_WIDTH), 111 | .DEST_ENABLE(DEST_ENABLE), 112 | .DEST_WIDTH(DEST_WIDTH), 113 | .USER_ENABLE(USER_ENABLE), 114 | .USER_WIDTH(USER_WIDTH) 115 | ) 116 | UUT ( 117 | .clk(clk), 118 | .rst(rst), 119 | // AXI inputs 120 | .s_axis_tdata(s_axis_tdata), 121 | .s_axis_tkeep(s_axis_tkeep), 122 | .s_axis_tvalid(s_axis_tvalid), 123 | .s_axis_tlast(s_axis_tlast), 124 | .s_axis_tid(s_axis_tid), 125 | .s_axis_tdest(s_axis_tdest), 126 | .s_axis_tuser(s_axis_tuser), 127 | // AXI output 128 | .m_axis_tdata(m_axis_tdata), 129 | .m_axis_tkeep(m_axis_tkeep), 130 | .m_axis_tvalid(m_axis_tvalid), 131 | .m_axis_tlast(m_axis_tlast), 132 | .m_axis_tid(m_axis_tid), 133 | .m_axis_tdest(m_axis_tdest), 134 | .m_axis_tuser(m_axis_tuser), 135 | // Control 136 | .select(select) 137 | ); 138 | 139 | endmodule 140 | -------------------------------------------------------------------------------- /tb/test_axis_demux_4.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_demux 31 | */ 32 | module test_axis_demux_4; 33 | 34 | // Parameters 35 | parameter M_COUNT = 4; 36 | parameter DATA_WIDTH = 8; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg s_axis_tvalid = 0; 54 | reg s_axis_tlast = 0; 55 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 58 | 59 | reg [M_COUNT-1:0] m_axis_tready = 0; 60 | 61 | reg enable = 0; 62 | reg drop = 0; 63 | reg [$clog2(M_COUNT)-1:0] select = 0; 64 | 65 | // Outputs 66 | wire s_axis_tready; 67 | 68 | wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata; 69 | wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep; 70 | wire [M_COUNT-1:0] m_axis_tvalid; 71 | wire [M_COUNT-1:0] m_axis_tlast; 72 | wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid; 73 | wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest; 74 | wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser; 75 | 76 | initial begin 77 | // myhdl integration 78 | $from_myhdl( 79 | clk, 80 | rst, 81 | current_test, 82 | s_axis_tdata, 83 | s_axis_tkeep, 84 | s_axis_tvalid, 85 | s_axis_tlast, 86 | s_axis_tid, 87 | s_axis_tdest, 88 | s_axis_tuser, 89 | m_axis_tready, 90 | enable, 91 | drop, 92 | select 93 | ); 94 | $to_myhdl( 95 | s_axis_tready, 96 | m_axis_tdata, 97 | m_axis_tkeep, 98 | m_axis_tvalid, 99 | m_axis_tlast, 100 | m_axis_tid, 101 | m_axis_tdest, 102 | m_axis_tuser 103 | ); 104 | 105 | // dump file 106 | $dumpfile("test_axis_demux_4.lxt"); 107 | $dumpvars(0, test_axis_demux_4); 108 | end 109 | 110 | axis_demux #( 111 | .M_COUNT(M_COUNT), 112 | .DATA_WIDTH(DATA_WIDTH), 113 | .KEEP_ENABLE(KEEP_ENABLE), 114 | .KEEP_WIDTH(KEEP_WIDTH), 115 | .ID_ENABLE(ID_ENABLE), 116 | .ID_WIDTH(ID_WIDTH), 117 | .DEST_ENABLE(DEST_ENABLE), 118 | .DEST_WIDTH(DEST_WIDTH), 119 | .USER_ENABLE(USER_ENABLE), 120 | .USER_WIDTH(USER_WIDTH) 121 | ) 122 | UUT ( 123 | .clk(clk), 124 | .rst(rst), 125 | // AXI input 126 | .s_axis_tdata(s_axis_tdata), 127 | .s_axis_tkeep(s_axis_tkeep), 128 | .s_axis_tvalid(s_axis_tvalid), 129 | .s_axis_tready(s_axis_tready), 130 | .s_axis_tlast(s_axis_tlast), 131 | .s_axis_tid(s_axis_tid), 132 | .s_axis_tdest(s_axis_tdest), 133 | .s_axis_tuser(s_axis_tuser), 134 | // AXI outputs 135 | .m_axis_tdata(m_axis_tdata), 136 | .m_axis_tkeep(m_axis_tkeep), 137 | .m_axis_tvalid(m_axis_tvalid), 138 | .m_axis_tready(m_axis_tready), 139 | .m_axis_tlast(m_axis_tlast), 140 | .m_axis_tid(m_axis_tid), 141 | .m_axis_tdest(m_axis_tdest), 142 | .m_axis_tuser(m_axis_tuser), 143 | // Control 144 | .enable(enable), 145 | .drop(drop), 146 | .select(select) 147 | ); 148 | 149 | endmodule 150 | -------------------------------------------------------------------------------- /tb/test_axis_demux_4_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_demux 31 | */ 32 | module test_axis_demux_4_64; 33 | 34 | // Parameters 35 | parameter M_COUNT = 4; 36 | parameter DATA_WIDTH = 64; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg s_axis_tvalid = 0; 54 | reg s_axis_tlast = 0; 55 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 58 | 59 | reg [M_COUNT-1:0] m_axis_tready = 0; 60 | 61 | reg enable = 0; 62 | reg drop = 0; 63 | reg [$clog2(M_COUNT)-1:0] select = 0; 64 | 65 | // Outputs 66 | wire s_axis_tready; 67 | 68 | wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata; 69 | wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep; 70 | wire [M_COUNT-1:0] m_axis_tvalid; 71 | wire [M_COUNT-1:0] m_axis_tlast; 72 | wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid; 73 | wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest; 74 | wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser; 75 | 76 | initial begin 77 | // myhdl integration 78 | $from_myhdl( 79 | clk, 80 | rst, 81 | current_test, 82 | s_axis_tdata, 83 | s_axis_tkeep, 84 | s_axis_tvalid, 85 | s_axis_tlast, 86 | s_axis_tid, 87 | s_axis_tdest, 88 | s_axis_tuser, 89 | m_axis_tready, 90 | enable, 91 | drop, 92 | select 93 | ); 94 | $to_myhdl( 95 | s_axis_tready, 96 | m_axis_tdata, 97 | m_axis_tkeep, 98 | m_axis_tvalid, 99 | m_axis_tlast, 100 | m_axis_tid, 101 | m_axis_tdest, 102 | m_axis_tuser 103 | ); 104 | 105 | // dump file 106 | $dumpfile("test_axis_demux_4_64.lxt"); 107 | $dumpvars(0, test_axis_demux_4_64); 108 | end 109 | 110 | axis_demux #( 111 | .M_COUNT(M_COUNT), 112 | .DATA_WIDTH(DATA_WIDTH), 113 | .KEEP_ENABLE(KEEP_ENABLE), 114 | .KEEP_WIDTH(KEEP_WIDTH), 115 | .ID_ENABLE(ID_ENABLE), 116 | .ID_WIDTH(ID_WIDTH), 117 | .DEST_ENABLE(DEST_ENABLE), 118 | .DEST_WIDTH(DEST_WIDTH), 119 | .USER_ENABLE(USER_ENABLE), 120 | .USER_WIDTH(USER_WIDTH) 121 | ) 122 | UUT ( 123 | .clk(clk), 124 | .rst(rst), 125 | // AXI input 126 | .s_axis_tdata(s_axis_tdata), 127 | .s_axis_tkeep(s_axis_tkeep), 128 | .s_axis_tvalid(s_axis_tvalid), 129 | .s_axis_tready(s_axis_tready), 130 | .s_axis_tlast(s_axis_tlast), 131 | .s_axis_tid(s_axis_tid), 132 | .s_axis_tdest(s_axis_tdest), 133 | .s_axis_tuser(s_axis_tuser), 134 | // AXI outputs 135 | .m_axis_tdata(m_axis_tdata), 136 | .m_axis_tkeep(m_axis_tkeep), 137 | .m_axis_tvalid(m_axis_tvalid), 138 | .m_axis_tready(m_axis_tready), 139 | .m_axis_tlast(m_axis_tlast), 140 | .m_axis_tid(m_axis_tid), 141 | .m_axis_tdest(m_axis_tdest), 142 | .m_axis_tuser(m_axis_tuser), 143 | // Control 144 | .enable(enable), 145 | .drop(drop), 146 | .select(select) 147 | ); 148 | 149 | endmodule 150 | -------------------------------------------------------------------------------- /tb/test_axis_frame_join_4.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_frame_join 31 | */ 32 | module test_axis_frame_join_4; 33 | 34 | // Parameters 35 | parameter S_COUNT = 4; 36 | parameter DATA_WIDTH = 8; 37 | parameter TAG_ENABLE = 1; 38 | parameter TAG_WIDTH = 16; 39 | 40 | // Inputs 41 | reg clk = 0; 42 | reg rst = 0; 43 | reg [7:0] current_test = 0; 44 | 45 | reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0; 46 | reg [S_COUNT-1:0] s_axis_tvalid = 0; 47 | reg [S_COUNT-1:0] s_axis_tlast = 0; 48 | reg [S_COUNT-1:0] s_axis_tuser = 0; 49 | reg m_axis_tready = 0; 50 | reg [TAG_WIDTH-1:0] tag = 0; 51 | 52 | // Outputs 53 | wire [S_COUNT-1:0] s_axis_tready; 54 | wire [7:0] m_axis_tdata; 55 | wire m_axis_tvalid; 56 | wire m_axis_tlast; 57 | wire m_axis_tuser; 58 | wire busy; 59 | 60 | initial begin 61 | // myhdl integration 62 | $from_myhdl( 63 | clk, 64 | rst, 65 | current_test, 66 | s_axis_tdata, 67 | s_axis_tvalid, 68 | s_axis_tlast, 69 | s_axis_tuser, 70 | m_axis_tready, 71 | tag 72 | ); 73 | $to_myhdl( 74 | s_axis_tready, 75 | m_axis_tdata, 76 | m_axis_tvalid, 77 | m_axis_tlast, 78 | m_axis_tuser, 79 | busy 80 | ); 81 | 82 | // dump file 83 | $dumpfile("test_axis_frame_join_4.lxt"); 84 | $dumpvars(0, test_axis_frame_join_4); 85 | end 86 | 87 | axis_frame_join #( 88 | .S_COUNT(S_COUNT), 89 | .DATA_WIDTH(DATA_WIDTH), 90 | .TAG_ENABLE(TAG_ENABLE), 91 | .TAG_WIDTH(TAG_WIDTH) 92 | ) 93 | UUT ( 94 | .clk(clk), 95 | .rst(rst), 96 | // axi input 97 | .s_axis_tdata(s_axis_tdata), 98 | .s_axis_tvalid(s_axis_tvalid), 99 | .s_axis_tready(s_axis_tready), 100 | .s_axis_tlast(s_axis_tlast), 101 | .s_axis_tuser(s_axis_tuser), 102 | // axi output 103 | .m_axis_tdata(m_axis_tdata), 104 | .m_axis_tvalid(m_axis_tvalid), 105 | .m_axis_tready(m_axis_tready), 106 | .m_axis_tlast(m_axis_tlast), 107 | .m_axis_tuser(m_axis_tuser), 108 | // config 109 | .tag(tag), 110 | // status 111 | .busy(busy) 112 | ); 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /tb/test_axis_frame_len_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2019 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_frame_len 31 | */ 32 | module test_axis_frame_len_64; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 64; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LEN_WIDTH = 16; 39 | 40 | // Inputs 41 | reg clk = 0; 42 | reg rst = 0; 43 | reg [7:0] current_test = 0; 44 | 45 | reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0; 46 | reg monitor_axis_tvalid = 0; 47 | reg monitor_axis_tready = 0; 48 | reg monitor_axis_tlast = 0; 49 | 50 | // Outputs 51 | wire [LEN_WIDTH-1:0] frame_len; 52 | wire frame_len_valid; 53 | 54 | initial begin 55 | // myhdl integration 56 | $from_myhdl( 57 | clk, 58 | rst, 59 | current_test, 60 | monitor_axis_tkeep, 61 | monitor_axis_tvalid, 62 | monitor_axis_tready, 63 | monitor_axis_tlast 64 | ); 65 | $to_myhdl( 66 | frame_len, 67 | frame_len_valid 68 | ); 69 | 70 | // dump file 71 | $dumpfile("test_axis_frame_len_64.lxt"); 72 | $dumpvars(0, test_axis_frame_len_64); 73 | end 74 | 75 | axis_frame_len #( 76 | .DATA_WIDTH(DATA_WIDTH), 77 | .KEEP_ENABLE(KEEP_ENABLE), 78 | .KEEP_WIDTH(KEEP_WIDTH), 79 | .LEN_WIDTH(LEN_WIDTH) 80 | ) 81 | UUT ( 82 | .clk(clk), 83 | .rst(rst), 84 | // AXI monitor 85 | .monitor_axis_tkeep(monitor_axis_tkeep), 86 | .monitor_axis_tvalid(monitor_axis_tvalid), 87 | .monitor_axis_tready(monitor_axis_tready), 88 | .monitor_axis_tlast(monitor_axis_tlast), 89 | // Status 90 | .frame_len(frame_len), 91 | .frame_len_valid(frame_len_valid) 92 | ); 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /tb/test_axis_frame_len_8.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2019 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_frame_len 31 | */ 32 | module test_axis_frame_len_8; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 8; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LEN_WIDTH = 16; 39 | 40 | // Inputs 41 | reg clk = 0; 42 | reg rst = 0; 43 | reg [7:0] current_test = 0; 44 | 45 | reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0; 46 | reg monitor_axis_tvalid = 0; 47 | reg monitor_axis_tready = 0; 48 | reg monitor_axis_tlast = 0; 49 | 50 | // Outputs 51 | wire [LEN_WIDTH-1:0] frame_len; 52 | wire frame_len_valid; 53 | 54 | initial begin 55 | // myhdl integration 56 | $from_myhdl( 57 | clk, 58 | rst, 59 | current_test, 60 | monitor_axis_tkeep, 61 | monitor_axis_tvalid, 62 | monitor_axis_tready, 63 | monitor_axis_tlast 64 | ); 65 | $to_myhdl( 66 | frame_len, 67 | frame_len_valid 68 | ); 69 | 70 | // dump file 71 | $dumpfile("test_axis_frame_len_8.lxt"); 72 | $dumpvars(0, test_axis_frame_len_8); 73 | end 74 | 75 | axis_frame_len #( 76 | .DATA_WIDTH(DATA_WIDTH), 77 | .KEEP_ENABLE(KEEP_ENABLE), 78 | .KEEP_WIDTH(KEEP_WIDTH), 79 | .LEN_WIDTH(LEN_WIDTH) 80 | ) 81 | UUT ( 82 | .clk(clk), 83 | .rst(rst), 84 | // AXI monitor 85 | .monitor_axis_tkeep(monitor_axis_tkeep), 86 | .monitor_axis_tvalid(monitor_axis_tvalid), 87 | .monitor_axis_tready(monitor_axis_tready), 88 | .monitor_axis_tlast(monitor_axis_tlast), 89 | // Status 90 | .frame_len(frame_len), 91 | .frame_len_valid(frame_len_valid) 92 | ); 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /tb/test_axis_ll_bridge.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_ll_bridge 31 | */ 32 | module test_axis_ll_bridge; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 8; 36 | 37 | // Inputs 38 | reg clk = 0; 39 | reg rst = 0; 40 | reg [7:0] current_test = 0; 41 | 42 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 43 | reg s_axis_tvalid = 0; 44 | reg s_axis_tlast = 0; 45 | reg ll_dst_rdy_in_n = 1; 46 | 47 | // Outputs 48 | wire [DATA_WIDTH-1:0] ll_data_out; 49 | wire ll_sof_out_n; 50 | wire ll_eof_out_n; 51 | wire ll_src_rdy_out_n; 52 | wire s_axis_tready; 53 | 54 | initial begin 55 | // myhdl integration 56 | $from_myhdl( 57 | clk, 58 | rst, 59 | current_test, 60 | s_axis_tdata, 61 | s_axis_tvalid, 62 | s_axis_tlast, 63 | ll_dst_rdy_in_n 64 | ); 65 | $to_myhdl( 66 | ll_data_out, 67 | ll_sof_out_n, 68 | ll_eof_out_n, 69 | ll_src_rdy_out_n, 70 | s_axis_tready 71 | ); 72 | 73 | // dump file 74 | $dumpfile("test_axis_ll_bridge.lxt"); 75 | $dumpvars(0, test_axis_ll_bridge); 76 | end 77 | 78 | axis_ll_bridge #( 79 | .DATA_WIDTH(DATA_WIDTH) 80 | ) 81 | UUT ( 82 | .clk(clk), 83 | .rst(rst), 84 | // axi input 85 | .s_axis_tdata(s_axis_tdata), 86 | .s_axis_tvalid(s_axis_tvalid), 87 | .s_axis_tready(s_axis_tready), 88 | .s_axis_tlast(s_axis_tlast), 89 | // locallink output 90 | .ll_data_out(ll_data_out), 91 | .ll_sof_out_n(ll_sof_out_n), 92 | .ll_eof_out_n(ll_eof_out_n), 93 | .ll_src_rdy_out_n(ll_src_rdy_out_n), 94 | .ll_dst_rdy_in_n(ll_dst_rdy_in_n) 95 | ); 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /tb/test_axis_mux_4.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_mux 31 | */ 32 | module test_axis_mux_4; 33 | 34 | // Parameters 35 | parameter S_COUNT = 4; 36 | parameter DATA_WIDTH = 8; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg [S_COUNT-1:0] s_axis_tvalid = 0; 54 | reg [S_COUNT-1:0] s_axis_tlast = 0; 55 | reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0; 58 | 59 | reg m_axis_tready = 0; 60 | 61 | reg enable = 0; 62 | reg [1:0] select = 0; 63 | 64 | // Outputs 65 | wire [S_COUNT-1:0] s_axis_tready; 66 | 67 | wire [DATA_WIDTH-1:0] m_axis_tdata; 68 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 69 | wire m_axis_tvalid; 70 | wire m_axis_tlast; 71 | wire [ID_WIDTH-1:0] m_axis_tid; 72 | wire [DEST_WIDTH-1:0] m_axis_tdest; 73 | wire [USER_WIDTH-1:0] m_axis_tuser; 74 | 75 | initial begin 76 | // myhdl integration 77 | $from_myhdl( 78 | clk, 79 | rst, 80 | current_test, 81 | s_axis_tdata, 82 | s_axis_tkeep, 83 | s_axis_tvalid, 84 | s_axis_tlast, 85 | s_axis_tid, 86 | s_axis_tdest, 87 | s_axis_tuser, 88 | m_axis_tready, 89 | enable, 90 | select 91 | ); 92 | $to_myhdl( 93 | s_axis_tready, 94 | m_axis_tdata, 95 | m_axis_tkeep, 96 | m_axis_tvalid, 97 | m_axis_tlast, 98 | m_axis_tid, 99 | m_axis_tdest, 100 | m_axis_tuser 101 | ); 102 | 103 | // dump file 104 | $dumpfile("test_axis_mux_4.lxt"); 105 | $dumpvars(0, test_axis_mux_4); 106 | end 107 | 108 | axis_mux #( 109 | .S_COUNT(S_COUNT), 110 | .DATA_WIDTH(DATA_WIDTH), 111 | .KEEP_ENABLE(KEEP_ENABLE), 112 | .KEEP_WIDTH(KEEP_WIDTH), 113 | .ID_ENABLE(ID_ENABLE), 114 | .ID_WIDTH(ID_WIDTH), 115 | .DEST_ENABLE(DEST_ENABLE), 116 | .DEST_WIDTH(DEST_WIDTH), 117 | .USER_ENABLE(USER_ENABLE), 118 | .USER_WIDTH(USER_WIDTH) 119 | ) 120 | UUT ( 121 | .clk(clk), 122 | .rst(rst), 123 | // AXI inputs 124 | .s_axis_tdata(s_axis_tdata), 125 | .s_axis_tkeep(s_axis_tkeep), 126 | .s_axis_tvalid(s_axis_tvalid), 127 | .s_axis_tready(s_axis_tready), 128 | .s_axis_tlast(s_axis_tlast), 129 | .s_axis_tid(s_axis_tid), 130 | .s_axis_tdest(s_axis_tdest), 131 | .s_axis_tuser(s_axis_tuser), 132 | // AXI output 133 | .m_axis_tdata(m_axis_tdata), 134 | .m_axis_tkeep(m_axis_tkeep), 135 | .m_axis_tvalid(m_axis_tvalid), 136 | .m_axis_tready(m_axis_tready), 137 | .m_axis_tlast(m_axis_tlast), 138 | .m_axis_tid(m_axis_tid), 139 | .m_axis_tdest(m_axis_tdest), 140 | .m_axis_tuser(m_axis_tuser), 141 | // Control 142 | .enable(enable), 143 | .select(select) 144 | ); 145 | 146 | endmodule 147 | -------------------------------------------------------------------------------- /tb/test_axis_mux_4_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_mux 31 | */ 32 | module test_axis_mux_4_64; 33 | 34 | // Parameters 35 | parameter S_COUNT = 4; 36 | parameter DATA_WIDTH = 64; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg [S_COUNT-1:0] s_axis_tvalid = 0; 54 | reg [S_COUNT-1:0] s_axis_tlast = 0; 55 | reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0; 58 | 59 | reg m_axis_tready = 0; 60 | 61 | reg enable = 0; 62 | reg [1:0] select = 0; 63 | 64 | // Outputs 65 | wire [S_COUNT-1:0] s_axis_tready; 66 | 67 | wire [DATA_WIDTH-1:0] m_axis_tdata; 68 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 69 | wire m_axis_tvalid; 70 | wire m_axis_tlast; 71 | wire [ID_WIDTH-1:0] m_axis_tid; 72 | wire [DEST_WIDTH-1:0] m_axis_tdest; 73 | wire [USER_WIDTH-1:0] m_axis_tuser; 74 | 75 | initial begin 76 | // myhdl integration 77 | $from_myhdl( 78 | clk, 79 | rst, 80 | current_test, 81 | s_axis_tdata, 82 | s_axis_tkeep, 83 | s_axis_tvalid, 84 | s_axis_tlast, 85 | s_axis_tid, 86 | s_axis_tdest, 87 | s_axis_tuser, 88 | m_axis_tready, 89 | enable, 90 | select 91 | ); 92 | $to_myhdl( 93 | s_axis_tready, 94 | m_axis_tdata, 95 | m_axis_tkeep, 96 | m_axis_tvalid, 97 | m_axis_tlast, 98 | m_axis_tid, 99 | m_axis_tdest, 100 | m_axis_tuser 101 | ); 102 | 103 | // dump file 104 | $dumpfile("test_axis_mux_4_64.lxt"); 105 | $dumpvars(0, test_axis_mux_4_64); 106 | end 107 | 108 | axis_mux #( 109 | .S_COUNT(S_COUNT), 110 | .DATA_WIDTH(DATA_WIDTH), 111 | .KEEP_ENABLE(KEEP_ENABLE), 112 | .KEEP_WIDTH(KEEP_WIDTH), 113 | .ID_ENABLE(ID_ENABLE), 114 | .ID_WIDTH(ID_WIDTH), 115 | .DEST_ENABLE(DEST_ENABLE), 116 | .DEST_WIDTH(DEST_WIDTH), 117 | .USER_ENABLE(USER_ENABLE), 118 | .USER_WIDTH(USER_WIDTH) 119 | ) 120 | UUT ( 121 | .clk(clk), 122 | .rst(rst), 123 | // AXI inputs 124 | .s_axis_tdata(s_axis_tdata), 125 | .s_axis_tkeep(s_axis_tkeep), 126 | .s_axis_tvalid(s_axis_tvalid), 127 | .s_axis_tready(s_axis_tready), 128 | .s_axis_tlast(s_axis_tlast), 129 | .s_axis_tid(s_axis_tid), 130 | .s_axis_tdest(s_axis_tdest), 131 | .s_axis_tuser(s_axis_tuser), 132 | // AXI output 133 | .m_axis_tdata(m_axis_tdata), 134 | .m_axis_tkeep(m_axis_tkeep), 135 | .m_axis_tvalid(m_axis_tvalid), 136 | .m_axis_tready(m_axis_tready), 137 | .m_axis_tlast(m_axis_tlast), 138 | .m_axis_tid(m_axis_tid), 139 | .m_axis_tdest(m_axis_tdest), 140 | .m_axis_tuser(m_axis_tuser), 141 | // Control 142 | .enable(enable), 143 | .select(select) 144 | ); 145 | 146 | endmodule 147 | -------------------------------------------------------------------------------- /tb/test_axis_rate_limit.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_rate_limit 31 | */ 32 | module test_axis_rate_limit; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 8; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LAST_ENABLE = 1; 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg s_axis_tvalid = 0; 54 | reg s_axis_tlast = 0; 55 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 58 | reg m_axis_tready = 0; 59 | reg [7:0] rate_num = 0; 60 | reg [7:0] rate_denom = 0; 61 | reg rate_by_frame = 0; 62 | 63 | // Outputs 64 | wire s_axis_tready; 65 | wire [DATA_WIDTH-1:0] m_axis_tdata; 66 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 67 | wire m_axis_tvalid; 68 | wire m_axis_tlast; 69 | wire [ID_WIDTH-1:0] m_axis_tid; 70 | wire [DEST_WIDTH-1:0] m_axis_tdest; 71 | wire [USER_WIDTH-1:0] m_axis_tuser; 72 | 73 | initial begin 74 | // myhdl integration 75 | $from_myhdl( 76 | clk, 77 | rst, 78 | current_test, 79 | s_axis_tdata, 80 | s_axis_tkeep, 81 | s_axis_tvalid, 82 | s_axis_tlast, 83 | s_axis_tid, 84 | s_axis_tdest, 85 | s_axis_tuser, 86 | m_axis_tready, 87 | rate_num, 88 | rate_denom, 89 | rate_by_frame 90 | ); 91 | $to_myhdl( 92 | s_axis_tready, 93 | m_axis_tdata, 94 | m_axis_tkeep, 95 | m_axis_tvalid, 96 | m_axis_tlast, 97 | m_axis_tid, 98 | m_axis_tdest, 99 | m_axis_tuser 100 | ); 101 | 102 | // dump file 103 | $dumpfile("test_axis_rate_limit.lxt"); 104 | $dumpvars(0, test_axis_rate_limit); 105 | end 106 | 107 | axis_rate_limit #( 108 | .DATA_WIDTH(DATA_WIDTH), 109 | .KEEP_ENABLE(KEEP_ENABLE), 110 | .KEEP_WIDTH(KEEP_WIDTH), 111 | .LAST_ENABLE(LAST_ENABLE), 112 | .ID_ENABLE(ID_ENABLE), 113 | .ID_WIDTH(ID_WIDTH), 114 | .DEST_ENABLE(DEST_ENABLE), 115 | .DEST_WIDTH(DEST_WIDTH), 116 | .USER_ENABLE(USER_ENABLE), 117 | .USER_WIDTH(USER_WIDTH) 118 | ) 119 | UUT ( 120 | .clk(clk), 121 | .rst(rst), 122 | // AXI input 123 | .s_axis_tdata(s_axis_tdata), 124 | .s_axis_tkeep(s_axis_tkeep), 125 | .s_axis_tvalid(s_axis_tvalid), 126 | .s_axis_tready(s_axis_tready), 127 | .s_axis_tlast(s_axis_tlast), 128 | .s_axis_tid(s_axis_tid), 129 | .s_axis_tdest(s_axis_tdest), 130 | .s_axis_tuser(s_axis_tuser), 131 | // AXI output 132 | .m_axis_tdata(m_axis_tdata), 133 | .m_axis_tkeep(m_axis_tkeep), 134 | .m_axis_tvalid(m_axis_tvalid), 135 | .m_axis_tready(m_axis_tready), 136 | .m_axis_tlast(m_axis_tlast), 137 | .m_axis_tid(m_axis_tid), 138 | .m_axis_tdest(m_axis_tdest), 139 | .m_axis_tuser(m_axis_tuser), 140 | // Configuration 141 | .rate_num(rate_num), 142 | .rate_denom(rate_denom), 143 | .rate_by_frame(rate_by_frame) 144 | ); 145 | 146 | endmodule 147 | -------------------------------------------------------------------------------- /tb/test_axis_rate_limit_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_rate_limit 31 | */ 32 | module test_axis_rate_limit_64; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 64; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LAST_ENABLE = 1; 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg s_axis_tvalid = 0; 54 | reg s_axis_tlast = 0; 55 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 58 | reg m_axis_tready = 0; 59 | reg [7:0] rate_num = 0; 60 | reg [7:0] rate_denom = 0; 61 | reg rate_by_frame = 0; 62 | 63 | // Outputs 64 | wire s_axis_tready; 65 | wire [DATA_WIDTH-1:0] m_axis_tdata; 66 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 67 | wire m_axis_tvalid; 68 | wire m_axis_tlast; 69 | wire [ID_WIDTH-1:0] m_axis_tid; 70 | wire [DEST_WIDTH-1:0] m_axis_tdest; 71 | wire [USER_WIDTH-1:0] m_axis_tuser; 72 | 73 | initial begin 74 | // myhdl integration 75 | $from_myhdl( 76 | clk, 77 | rst, 78 | current_test, 79 | s_axis_tdata, 80 | s_axis_tkeep, 81 | s_axis_tvalid, 82 | s_axis_tlast, 83 | s_axis_tid, 84 | s_axis_tdest, 85 | s_axis_tuser, 86 | m_axis_tready, 87 | rate_num, 88 | rate_denom, 89 | rate_by_frame 90 | ); 91 | $to_myhdl( 92 | s_axis_tready, 93 | m_axis_tdata, 94 | m_axis_tkeep, 95 | m_axis_tvalid, 96 | m_axis_tlast, 97 | m_axis_tid, 98 | m_axis_tdest, 99 | m_axis_tuser 100 | ); 101 | 102 | // dump file 103 | $dumpfile("test_axis_rate_limit_64.lxt"); 104 | $dumpvars(0, test_axis_rate_limit_64); 105 | end 106 | 107 | axis_rate_limit #( 108 | .DATA_WIDTH(DATA_WIDTH), 109 | .KEEP_ENABLE(KEEP_ENABLE), 110 | .KEEP_WIDTH(KEEP_WIDTH), 111 | .LAST_ENABLE(LAST_ENABLE), 112 | .ID_ENABLE(ID_ENABLE), 113 | .ID_WIDTH(ID_WIDTH), 114 | .DEST_ENABLE(DEST_ENABLE), 115 | .DEST_WIDTH(DEST_WIDTH), 116 | .USER_ENABLE(USER_ENABLE), 117 | .USER_WIDTH(USER_WIDTH) 118 | ) 119 | UUT ( 120 | .clk(clk), 121 | .rst(rst), 122 | // AXI input 123 | .s_axis_tdata(s_axis_tdata), 124 | .s_axis_tkeep(s_axis_tkeep), 125 | .s_axis_tvalid(s_axis_tvalid), 126 | .s_axis_tready(s_axis_tready), 127 | .s_axis_tlast(s_axis_tlast), 128 | .s_axis_tid(s_axis_tid), 129 | .s_axis_tdest(s_axis_tdest), 130 | .s_axis_tuser(s_axis_tuser), 131 | // AXI output 132 | .m_axis_tdata(m_axis_tdata), 133 | .m_axis_tkeep(m_axis_tkeep), 134 | .m_axis_tvalid(m_axis_tvalid), 135 | .m_axis_tready(m_axis_tready), 136 | .m_axis_tlast(m_axis_tlast), 137 | .m_axis_tid(m_axis_tid), 138 | .m_axis_tdest(m_axis_tdest), 139 | .m_axis_tuser(m_axis_tuser), 140 | // Configuration 141 | .rate_num(rate_num), 142 | .rate_denom(rate_denom), 143 | .rate_by_frame(rate_by_frame) 144 | ); 145 | 146 | endmodule 147 | -------------------------------------------------------------------------------- /tb/test_axis_register.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_register 31 | */ 32 | module test_axis_register; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 8; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LAST_ENABLE = 1; 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | parameter REG_TYPE = 2; 46 | 47 | // Inputs 48 | reg clk = 0; 49 | reg rst = 0; 50 | reg [7:0] current_test = 0; 51 | 52 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 53 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 54 | reg s_axis_tvalid = 0; 55 | reg s_axis_tlast = 0; 56 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 57 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 58 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 59 | reg m_axis_tready = 0; 60 | 61 | // Outputs 62 | wire s_axis_tready; 63 | wire [DATA_WIDTH-1:0] m_axis_tdata; 64 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 65 | wire m_axis_tvalid; 66 | wire m_axis_tlast; 67 | wire [ID_WIDTH-1:0] m_axis_tid; 68 | wire [DEST_WIDTH-1:0] m_axis_tdest; 69 | wire [USER_WIDTH-1:0] m_axis_tuser; 70 | 71 | initial begin 72 | // myhdl integration 73 | $from_myhdl( 74 | clk, 75 | rst, 76 | current_test, 77 | s_axis_tdata, 78 | s_axis_tkeep, 79 | s_axis_tvalid, 80 | s_axis_tlast, 81 | s_axis_tid, 82 | s_axis_tdest, 83 | s_axis_tuser, 84 | m_axis_tready 85 | ); 86 | $to_myhdl( 87 | s_axis_tready, 88 | m_axis_tdata, 89 | m_axis_tkeep, 90 | m_axis_tvalid, 91 | m_axis_tlast, 92 | m_axis_tid, 93 | m_axis_tdest, 94 | m_axis_tuser 95 | ); 96 | 97 | // dump file 98 | $dumpfile("test_axis_register.lxt"); 99 | $dumpvars(0, test_axis_register); 100 | end 101 | 102 | axis_register #( 103 | .DATA_WIDTH(DATA_WIDTH), 104 | .KEEP_ENABLE(KEEP_ENABLE), 105 | .KEEP_WIDTH(KEEP_WIDTH), 106 | .LAST_ENABLE(LAST_ENABLE), 107 | .ID_ENABLE(ID_ENABLE), 108 | .ID_WIDTH(ID_WIDTH), 109 | .DEST_ENABLE(DEST_ENABLE), 110 | .DEST_WIDTH(DEST_WIDTH), 111 | .USER_ENABLE(USER_ENABLE), 112 | .USER_WIDTH(USER_WIDTH), 113 | .REG_TYPE(REG_TYPE) 114 | ) 115 | UUT ( 116 | .clk(clk), 117 | .rst(rst), 118 | // AXI input 119 | .s_axis_tdata(s_axis_tdata), 120 | .s_axis_tkeep(s_axis_tkeep), 121 | .s_axis_tvalid(s_axis_tvalid), 122 | .s_axis_tready(s_axis_tready), 123 | .s_axis_tlast(s_axis_tlast), 124 | .s_axis_tid(s_axis_tid), 125 | .s_axis_tdest(s_axis_tdest), 126 | .s_axis_tuser(s_axis_tuser), 127 | // AXI output 128 | .m_axis_tdata(m_axis_tdata), 129 | .m_axis_tkeep(m_axis_tkeep), 130 | .m_axis_tvalid(m_axis_tvalid), 131 | .m_axis_tready(m_axis_tready), 132 | .m_axis_tlast(m_axis_tlast), 133 | .m_axis_tid(m_axis_tid), 134 | .m_axis_tdest(m_axis_tdest), 135 | .m_axis_tuser(m_axis_tuser) 136 | ); 137 | 138 | endmodule 139 | -------------------------------------------------------------------------------- /tb/test_axis_register_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_register 31 | */ 32 | module test_axis_register_64; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 64; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LAST_ENABLE = 1; 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | parameter REG_TYPE = 2; 46 | 47 | // Inputs 48 | reg clk = 0; 49 | reg rst = 0; 50 | reg [7:0] current_test = 0; 51 | 52 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 53 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 54 | reg s_axis_tvalid = 0; 55 | reg s_axis_tlast = 0; 56 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 57 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 58 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 59 | reg m_axis_tready = 0; 60 | 61 | // Outputs 62 | wire s_axis_tready; 63 | wire [DATA_WIDTH-1:0] m_axis_tdata; 64 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 65 | wire m_axis_tvalid; 66 | wire m_axis_tlast; 67 | wire [ID_WIDTH-1:0] m_axis_tid; 68 | wire [DEST_WIDTH-1:0] m_axis_tdest; 69 | wire [USER_WIDTH-1:0] m_axis_tuser; 70 | 71 | initial begin 72 | // myhdl integration 73 | $from_myhdl( 74 | clk, 75 | rst, 76 | current_test, 77 | s_axis_tdata, 78 | s_axis_tkeep, 79 | s_axis_tvalid, 80 | s_axis_tlast, 81 | s_axis_tid, 82 | s_axis_tdest, 83 | s_axis_tuser, 84 | m_axis_tready 85 | ); 86 | $to_myhdl( 87 | s_axis_tready, 88 | m_axis_tdata, 89 | m_axis_tkeep, 90 | m_axis_tvalid, 91 | m_axis_tlast, 92 | m_axis_tid, 93 | m_axis_tdest, 94 | m_axis_tuser 95 | ); 96 | 97 | // dump file 98 | $dumpfile("test_axis_register_64.lxt"); 99 | $dumpvars(0, test_axis_register_64); 100 | end 101 | 102 | axis_register #( 103 | .DATA_WIDTH(DATA_WIDTH), 104 | .KEEP_ENABLE(KEEP_ENABLE), 105 | .KEEP_WIDTH(KEEP_WIDTH), 106 | .LAST_ENABLE(LAST_ENABLE), 107 | .ID_ENABLE(ID_ENABLE), 108 | .ID_WIDTH(ID_WIDTH), 109 | .DEST_ENABLE(DEST_ENABLE), 110 | .DEST_WIDTH(DEST_WIDTH), 111 | .USER_ENABLE(USER_ENABLE), 112 | .USER_WIDTH(USER_WIDTH), 113 | .REG_TYPE(REG_TYPE) 114 | ) 115 | UUT ( 116 | .clk(clk), 117 | .rst(rst), 118 | // AXI input 119 | .s_axis_tdata(s_axis_tdata), 120 | .s_axis_tkeep(s_axis_tkeep), 121 | .s_axis_tvalid(s_axis_tvalid), 122 | .s_axis_tready(s_axis_tready), 123 | .s_axis_tlast(s_axis_tlast), 124 | .s_axis_tid(s_axis_tid), 125 | .s_axis_tdest(s_axis_tdest), 126 | .s_axis_tuser(s_axis_tuser), 127 | // AXI output 128 | .m_axis_tdata(m_axis_tdata), 129 | .m_axis_tkeep(m_axis_tkeep), 130 | .m_axis_tvalid(m_axis_tvalid), 131 | .m_axis_tready(m_axis_tready), 132 | .m_axis_tlast(m_axis_tlast), 133 | .m_axis_tid(m_axis_tid), 134 | .m_axis_tdest(m_axis_tdest), 135 | .m_axis_tuser(m_axis_tuser) 136 | ); 137 | 138 | endmodule 139 | -------------------------------------------------------------------------------- /tb/test_axis_srl_fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_srl_fifo 31 | */ 32 | module test_axis_srl_fifo; 33 | 34 | // Parameters 35 | parameter DEPTH = 4; 36 | parameter DATA_WIDTH = 8; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter LAST_ENABLE = 1; 40 | parameter ID_ENABLE = 1; 41 | parameter ID_WIDTH = 8; 42 | parameter DEST_ENABLE = 1; 43 | parameter DEST_WIDTH = 8; 44 | parameter USER_ENABLE = 1; 45 | parameter USER_WIDTH = 1; 46 | 47 | // Inputs 48 | reg clk = 0; 49 | reg rst = 0; 50 | reg [7:0] current_test = 0; 51 | 52 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 53 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 54 | reg s_axis_tvalid = 0; 55 | reg s_axis_tlast = 0; 56 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 57 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 58 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 59 | reg m_axis_tready = 0; 60 | 61 | // Outputs 62 | wire s_axis_tready; 63 | wire [DATA_WIDTH-1:0] m_axis_tdata; 64 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 65 | wire m_axis_tvalid; 66 | wire m_axis_tlast; 67 | wire [ID_WIDTH-1:0] m_axis_tid; 68 | wire [DEST_WIDTH-1:0] m_axis_tdest; 69 | wire [USER_WIDTH-1:0] m_axis_tuser; 70 | 71 | wire [2:0] count; 72 | 73 | initial begin 74 | // myhdl integration 75 | $from_myhdl( 76 | clk, 77 | rst, 78 | current_test, 79 | s_axis_tdata, 80 | s_axis_tkeep, 81 | s_axis_tvalid, 82 | s_axis_tlast, 83 | s_axis_tid, 84 | s_axis_tdest, 85 | s_axis_tuser, 86 | m_axis_tready 87 | ); 88 | $to_myhdl( 89 | s_axis_tready, 90 | m_axis_tdata, 91 | m_axis_tkeep, 92 | m_axis_tvalid, 93 | m_axis_tlast, 94 | m_axis_tid, 95 | m_axis_tdest, 96 | m_axis_tuser, 97 | count 98 | ); 99 | 100 | // dump file 101 | $dumpfile("test_axis_srl_fifo.lxt"); 102 | $dumpvars(0, test_axis_srl_fifo); 103 | end 104 | 105 | axis_srl_fifo #( 106 | .DEPTH(DEPTH), 107 | .DATA_WIDTH(DATA_WIDTH), 108 | .KEEP_ENABLE(KEEP_ENABLE), 109 | .KEEP_WIDTH(KEEP_WIDTH), 110 | .LAST_ENABLE(LAST_ENABLE), 111 | .ID_ENABLE(ID_ENABLE), 112 | .ID_WIDTH(ID_WIDTH), 113 | .DEST_ENABLE(DEST_ENABLE), 114 | .DEST_WIDTH(DEST_WIDTH), 115 | .USER_ENABLE(USER_ENABLE), 116 | .USER_WIDTH(USER_WIDTH) 117 | ) 118 | UUT ( 119 | .clk(clk), 120 | .rst(rst), 121 | // AXI input 122 | .s_axis_tdata(s_axis_tdata), 123 | .s_axis_tkeep(s_axis_tkeep), 124 | .s_axis_tvalid(s_axis_tvalid), 125 | .s_axis_tready(s_axis_tready), 126 | .s_axis_tlast(s_axis_tlast), 127 | .s_axis_tid(s_axis_tid), 128 | .s_axis_tdest(s_axis_tdest), 129 | .s_axis_tuser(s_axis_tuser), 130 | // AXI output 131 | .m_axis_tdata(m_axis_tdata), 132 | .m_axis_tkeep(m_axis_tkeep), 133 | .m_axis_tvalid(m_axis_tvalid), 134 | .m_axis_tready(m_axis_tready), 135 | .m_axis_tlast(m_axis_tlast), 136 | .m_axis_tid(m_axis_tid), 137 | .m_axis_tdest(m_axis_tdest), 138 | .m_axis_tuser(m_axis_tuser), 139 | // Status 140 | .count(count) 141 | ); 142 | 143 | endmodule 144 | -------------------------------------------------------------------------------- /tb/test_axis_srl_fifo_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_srl_fifo 31 | */ 32 | module test_axis_srl_fifo_64; 33 | 34 | // Parameters 35 | parameter DEPTH = 4; 36 | parameter DATA_WIDTH = 64; 37 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 38 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 39 | parameter LAST_ENABLE = 1; 40 | parameter ID_ENABLE = 1; 41 | parameter ID_WIDTH = 8; 42 | parameter DEST_ENABLE = 1; 43 | parameter DEST_WIDTH = 8; 44 | parameter USER_ENABLE = 1; 45 | parameter USER_WIDTH = 1; 46 | 47 | // Inputs 48 | reg clk = 0; 49 | reg rst = 0; 50 | reg [7:0] current_test = 0; 51 | 52 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 53 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 54 | reg s_axis_tvalid = 0; 55 | reg s_axis_tlast = 0; 56 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 57 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 58 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 59 | reg m_axis_tready = 0; 60 | 61 | // Outputs 62 | wire s_axis_tready; 63 | wire [DATA_WIDTH-1:0] m_axis_tdata; 64 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 65 | wire m_axis_tvalid; 66 | wire m_axis_tlast; 67 | wire [ID_WIDTH-1:0] m_axis_tid; 68 | wire [DEST_WIDTH-1:0] m_axis_tdest; 69 | wire [USER_WIDTH-1:0] m_axis_tuser; 70 | 71 | wire [2:0] count; 72 | 73 | initial begin 74 | // myhdl integration 75 | $from_myhdl( 76 | clk, 77 | rst, 78 | current_test, 79 | s_axis_tdata, 80 | s_axis_tkeep, 81 | s_axis_tvalid, 82 | s_axis_tlast, 83 | s_axis_tid, 84 | s_axis_tdest, 85 | s_axis_tuser, 86 | m_axis_tready 87 | ); 88 | $to_myhdl( 89 | s_axis_tready, 90 | m_axis_tdata, 91 | m_axis_tkeep, 92 | m_axis_tvalid, 93 | m_axis_tlast, 94 | m_axis_tid, 95 | m_axis_tdest, 96 | m_axis_tuser, 97 | count 98 | ); 99 | 100 | // dump file 101 | $dumpfile("test_axis_srl_fifo_64.lxt"); 102 | $dumpvars(0, test_axis_srl_fifo_64); 103 | end 104 | 105 | axis_srl_fifo #( 106 | .DEPTH(DEPTH), 107 | .DATA_WIDTH(DATA_WIDTH), 108 | .KEEP_ENABLE(KEEP_ENABLE), 109 | .KEEP_WIDTH(KEEP_WIDTH), 110 | .LAST_ENABLE(LAST_ENABLE), 111 | .ID_ENABLE(ID_ENABLE), 112 | .ID_WIDTH(ID_WIDTH), 113 | .DEST_ENABLE(DEST_ENABLE), 114 | .DEST_WIDTH(DEST_WIDTH), 115 | .USER_ENABLE(USER_ENABLE), 116 | .USER_WIDTH(USER_WIDTH) 117 | ) 118 | UUT ( 119 | .clk(clk), 120 | .rst(rst), 121 | // AXI input 122 | .s_axis_tdata(s_axis_tdata), 123 | .s_axis_tkeep(s_axis_tkeep), 124 | .s_axis_tvalid(s_axis_tvalid), 125 | .s_axis_tready(s_axis_tready), 126 | .s_axis_tlast(s_axis_tlast), 127 | .s_axis_tid(s_axis_tid), 128 | .s_axis_tdest(s_axis_tdest), 129 | .s_axis_tuser(s_axis_tuser), 130 | // AXI output 131 | .m_axis_tdata(m_axis_tdata), 132 | .m_axis_tkeep(m_axis_tkeep), 133 | .m_axis_tvalid(m_axis_tvalid), 134 | .m_axis_tready(m_axis_tready), 135 | .m_axis_tlast(m_axis_tlast), 136 | .m_axis_tid(m_axis_tid), 137 | .m_axis_tdest(m_axis_tdest), 138 | .m_axis_tuser(m_axis_tuser), 139 | // Status 140 | .count(count) 141 | ); 142 | 143 | endmodule 144 | -------------------------------------------------------------------------------- /tb/test_axis_srl_register.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_srl_register 31 | */ 32 | module test_axis_srl_register; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 8; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LAST_ENABLE = 1; 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg s_axis_tvalid = 0; 54 | reg s_axis_tlast = 0; 55 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 58 | reg m_axis_tready = 0; 59 | 60 | // Outputs 61 | wire s_axis_tready; 62 | wire [DATA_WIDTH-1:0] m_axis_tdata; 63 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 64 | wire m_axis_tvalid; 65 | wire m_axis_tlast; 66 | wire [ID_WIDTH-1:0] m_axis_tid; 67 | wire [DEST_WIDTH-1:0] m_axis_tdest; 68 | wire [USER_WIDTH-1:0] m_axis_tuser; 69 | 70 | initial begin 71 | // myhdl integration 72 | $from_myhdl( 73 | clk, 74 | rst, 75 | current_test, 76 | s_axis_tdata, 77 | s_axis_tkeep, 78 | s_axis_tvalid, 79 | s_axis_tlast, 80 | s_axis_tid, 81 | s_axis_tdest, 82 | s_axis_tuser, 83 | m_axis_tready 84 | ); 85 | $to_myhdl( 86 | s_axis_tready, 87 | m_axis_tdata, 88 | m_axis_tkeep, 89 | m_axis_tvalid, 90 | m_axis_tlast, 91 | m_axis_tid, 92 | m_axis_tdest, 93 | m_axis_tuser 94 | ); 95 | 96 | // dump file 97 | $dumpfile("test_axis_srl_register.lxt"); 98 | $dumpvars(0, test_axis_srl_register); 99 | end 100 | 101 | axis_srl_register #( 102 | .DATA_WIDTH(DATA_WIDTH), 103 | .KEEP_ENABLE(KEEP_ENABLE), 104 | .KEEP_WIDTH(KEEP_WIDTH), 105 | .LAST_ENABLE(LAST_ENABLE), 106 | .ID_ENABLE(ID_ENABLE), 107 | .ID_WIDTH(ID_WIDTH), 108 | .DEST_ENABLE(DEST_ENABLE), 109 | .DEST_WIDTH(DEST_WIDTH), 110 | .USER_ENABLE(USER_ENABLE), 111 | .USER_WIDTH(USER_WIDTH) 112 | ) 113 | UUT ( 114 | .clk(clk), 115 | .rst(rst), 116 | // AXI input 117 | .s_axis_tdata(s_axis_tdata), 118 | .s_axis_tkeep(s_axis_tkeep), 119 | .s_axis_tvalid(s_axis_tvalid), 120 | .s_axis_tready(s_axis_tready), 121 | .s_axis_tlast(s_axis_tlast), 122 | .s_axis_tid(s_axis_tid), 123 | .s_axis_tdest(s_axis_tdest), 124 | .s_axis_tuser(s_axis_tuser), 125 | // AXI output 126 | .m_axis_tdata(m_axis_tdata), 127 | .m_axis_tkeep(m_axis_tkeep), 128 | .m_axis_tvalid(m_axis_tvalid), 129 | .m_axis_tready(m_axis_tready), 130 | .m_axis_tlast(m_axis_tlast), 131 | .m_axis_tid(m_axis_tid), 132 | .m_axis_tdest(m_axis_tdest), 133 | .m_axis_tuser(m_axis_tuser) 134 | ); 135 | 136 | endmodule 137 | -------------------------------------------------------------------------------- /tb/test_axis_srl_register_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_srl_register 31 | */ 32 | module test_axis_srl_register_64; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 64; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter LAST_ENABLE = 1; 39 | parameter ID_ENABLE = 1; 40 | parameter ID_WIDTH = 8; 41 | parameter DEST_ENABLE = 1; 42 | parameter DEST_WIDTH = 8; 43 | parameter USER_ENABLE = 1; 44 | parameter USER_WIDTH = 1; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [DATA_WIDTH-1:0] s_axis_tdata = 0; 52 | reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; 53 | reg s_axis_tvalid = 0; 54 | reg s_axis_tlast = 0; 55 | reg [ID_WIDTH-1:0] s_axis_tid = 0; 56 | reg [DEST_WIDTH-1:0] s_axis_tdest = 0; 57 | reg [USER_WIDTH-1:0] s_axis_tuser = 0; 58 | reg m_axis_tready = 0; 59 | 60 | // Outputs 61 | wire s_axis_tready; 62 | wire [DATA_WIDTH-1:0] m_axis_tdata; 63 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 64 | wire m_axis_tvalid; 65 | wire m_axis_tlast; 66 | wire [ID_WIDTH-1:0] m_axis_tid; 67 | wire [DEST_WIDTH-1:0] m_axis_tdest; 68 | wire [USER_WIDTH-1:0] m_axis_tuser; 69 | 70 | initial begin 71 | // myhdl integration 72 | $from_myhdl( 73 | clk, 74 | rst, 75 | current_test, 76 | s_axis_tdata, 77 | s_axis_tkeep, 78 | s_axis_tvalid, 79 | s_axis_tlast, 80 | s_axis_tid, 81 | s_axis_tdest, 82 | s_axis_tuser, 83 | m_axis_tready 84 | ); 85 | $to_myhdl( 86 | s_axis_tready, 87 | m_axis_tdata, 88 | m_axis_tkeep, 89 | m_axis_tvalid, 90 | m_axis_tlast, 91 | m_axis_tid, 92 | m_axis_tdest, 93 | m_axis_tuser 94 | ); 95 | 96 | // dump file 97 | $dumpfile("test_axis_srl_register_64.lxt"); 98 | $dumpvars(0, test_axis_srl_register_64); 99 | end 100 | 101 | axis_srl_register #( 102 | .DATA_WIDTH(DATA_WIDTH), 103 | .KEEP_ENABLE(KEEP_ENABLE), 104 | .KEEP_WIDTH(KEEP_WIDTH), 105 | .LAST_ENABLE(LAST_ENABLE), 106 | .ID_ENABLE(ID_ENABLE), 107 | .ID_WIDTH(ID_WIDTH), 108 | .DEST_ENABLE(DEST_ENABLE), 109 | .DEST_WIDTH(DEST_WIDTH), 110 | .USER_ENABLE(USER_ENABLE), 111 | .USER_WIDTH(USER_WIDTH) 112 | ) 113 | UUT ( 114 | .clk(clk), 115 | .rst(rst), 116 | // AXI input 117 | .s_axis_tdata(s_axis_tdata), 118 | .s_axis_tkeep(s_axis_tkeep), 119 | .s_axis_tvalid(s_axis_tvalid), 120 | .s_axis_tready(s_axis_tready), 121 | .s_axis_tlast(s_axis_tlast), 122 | .s_axis_tid(s_axis_tid), 123 | .s_axis_tdest(s_axis_tdest), 124 | .s_axis_tuser(s_axis_tuser), 125 | // AXI output 126 | .m_axis_tdata(m_axis_tdata), 127 | .m_axis_tkeep(m_axis_tkeep), 128 | .m_axis_tvalid(m_axis_tvalid), 129 | .m_axis_tready(m_axis_tready), 130 | .m_axis_tlast(m_axis_tlast), 131 | .m_axis_tid(m_axis_tid), 132 | .m_axis_tdest(m_axis_tdest), 133 | .m_axis_tuser(m_axis_tuser) 134 | ); 135 | 136 | endmodule 137 | -------------------------------------------------------------------------------- /tb/test_axis_stat_counter.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_stat_counter 31 | */ 32 | module test_axis_stat_counter; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 64; 36 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 37 | parameter TAG_ENABLE = 1; 38 | parameter TAG_WIDTH = 16; 39 | parameter TICK_COUNT_ENABLE = 1; 40 | parameter TICK_COUNT_WIDTH = 32; 41 | parameter BYTE_COUNT_ENABLE = 1; 42 | parameter BYTE_COUNT_WIDTH = 32; 43 | parameter FRAME_COUNT_ENABLE = 1; 44 | parameter FRAME_COUNT_WIDTH = 32; 45 | 46 | // Inputs 47 | reg clk = 0; 48 | reg rst = 0; 49 | reg [7:0] current_test = 0; 50 | 51 | reg [DATA_WIDTH-1:0] monitor_axis_tdata = 0; 52 | reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0; 53 | reg monitor_axis_tvalid = 0; 54 | reg monitor_axis_tready = 0; 55 | reg monitor_axis_tlast = 0; 56 | reg monitor_axis_tuser = 0; 57 | reg m_axis_tready = 0; 58 | reg [TAG_WIDTH-1:0] tag = 0; 59 | reg trigger = 0; 60 | 61 | // Outputs 62 | wire [7:0] m_axis_tdata; 63 | wire m_axis_tvalid; 64 | wire m_axis_tlast; 65 | wire m_axis_tuser; 66 | wire busy; 67 | 68 | initial begin 69 | // myhdl integration 70 | $from_myhdl( 71 | clk, 72 | rst, 73 | current_test, 74 | monitor_axis_tdata, 75 | monitor_axis_tkeep, 76 | monitor_axis_tvalid, 77 | monitor_axis_tready, 78 | monitor_axis_tlast, 79 | monitor_axis_tuser, 80 | m_axis_tready, 81 | tag, 82 | trigger 83 | ); 84 | $to_myhdl( 85 | m_axis_tdata, 86 | m_axis_tvalid, 87 | m_axis_tlast, 88 | m_axis_tuser, 89 | busy 90 | ); 91 | 92 | // dump file 93 | $dumpfile("test_axis_stat_counter.lxt"); 94 | $dumpvars(0, test_axis_stat_counter); 95 | end 96 | 97 | axis_stat_counter #( 98 | .DATA_WIDTH(DATA_WIDTH), 99 | .KEEP_WIDTH(KEEP_WIDTH), 100 | .TAG_ENABLE(TAG_ENABLE), 101 | .TAG_WIDTH(TAG_WIDTH), 102 | .TICK_COUNT_ENABLE(TICK_COUNT_ENABLE), 103 | .TICK_COUNT_WIDTH(TICK_COUNT_WIDTH), 104 | .BYTE_COUNT_ENABLE(BYTE_COUNT_ENABLE), 105 | .BYTE_COUNT_WIDTH(BYTE_COUNT_WIDTH), 106 | .FRAME_COUNT_ENABLE(FRAME_COUNT_ENABLE), 107 | .FRAME_COUNT_WIDTH(FRAME_COUNT_WIDTH) 108 | ) 109 | UUT ( 110 | .clk(clk), 111 | .rst(rst), 112 | // axi monitor input 113 | .monitor_axis_tkeep(monitor_axis_tkeep), 114 | .monitor_axis_tvalid(monitor_axis_tvalid), 115 | .monitor_axis_tready(monitor_axis_tready), 116 | .monitor_axis_tlast(monitor_axis_tlast), 117 | // axi output 118 | .m_axis_tdata(m_axis_tdata), 119 | .m_axis_tvalid(m_axis_tvalid), 120 | .m_axis_tready(m_axis_tready), 121 | .m_axis_tlast(m_axis_tlast), 122 | .m_axis_tuser(m_axis_tuser), 123 | // configuration 124 | .tag(tag), 125 | .trigger(trigger), 126 | // status 127 | .busy(busy) 128 | ); 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /tb/test_axis_tap.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2015-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_tap 31 | */ 32 | module test_axis_tap; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 8; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter ID_ENABLE = 1; 39 | parameter ID_WIDTH = 8; 40 | parameter DEST_ENABLE = 1; 41 | parameter DEST_WIDTH = 8; 42 | parameter USER_ENABLE = 1; 43 | parameter USER_WIDTH = 1; 44 | parameter USER_BAD_FRAME_VALUE = 1'b1; 45 | parameter USER_BAD_FRAME_MASK = 1'b1; 46 | 47 | // Inputs 48 | reg clk = 0; 49 | reg rst = 0; 50 | reg [7:0] current_test = 0; 51 | 52 | reg [DATA_WIDTH-1:0] tap_axis_tdata = 0; 53 | reg [KEEP_WIDTH-1:0] tap_axis_tkeep = 0; 54 | reg tap_axis_tvalid = 0; 55 | reg tap_axis_tready = 0; 56 | reg tap_axis_tlast = 0; 57 | reg [ID_WIDTH-1:0] tap_axis_tid = 0; 58 | reg [DEST_WIDTH-1:0] tap_axis_tdest = 0; 59 | reg [USER_WIDTH-1:0] tap_axis_tuser = 0; 60 | reg m_axis_tready = 0; 61 | 62 | // Outputs 63 | wire [DATA_WIDTH-1:0] m_axis_tdata; 64 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 65 | wire m_axis_tvalid; 66 | wire m_axis_tlast; 67 | wire [ID_WIDTH-1:0] m_axis_tid; 68 | wire [DEST_WIDTH-1:0] m_axis_tdest; 69 | wire [USER_WIDTH-1:0] m_axis_tuser; 70 | 71 | initial begin 72 | // myhdl integration 73 | $from_myhdl( 74 | clk, 75 | rst, 76 | current_test, 77 | tap_axis_tdata, 78 | tap_axis_tkeep, 79 | tap_axis_tvalid, 80 | tap_axis_tready, 81 | tap_axis_tlast, 82 | tap_axis_tid, 83 | tap_axis_tdest, 84 | tap_axis_tuser, 85 | m_axis_tready 86 | ); 87 | $to_myhdl( 88 | m_axis_tdata, 89 | m_axis_tkeep, 90 | m_axis_tvalid, 91 | m_axis_tlast, 92 | m_axis_tid, 93 | m_axis_tdest, 94 | m_axis_tuser 95 | ); 96 | 97 | // dump file 98 | $dumpfile("test_axis_tap.lxt"); 99 | $dumpvars(0, test_axis_tap); 100 | end 101 | 102 | axis_tap #( 103 | .DATA_WIDTH(DATA_WIDTH), 104 | .KEEP_ENABLE(KEEP_ENABLE), 105 | .KEEP_WIDTH(KEEP_WIDTH), 106 | .ID_ENABLE(ID_ENABLE), 107 | .ID_WIDTH(ID_WIDTH), 108 | .DEST_ENABLE(DEST_ENABLE), 109 | .DEST_WIDTH(DEST_WIDTH), 110 | .USER_ENABLE(USER_ENABLE), 111 | .USER_WIDTH(USER_WIDTH), 112 | .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), 113 | .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK) 114 | ) 115 | UUT ( 116 | .clk(clk), 117 | .rst(rst), 118 | // AXI tap 119 | .tap_axis_tdata(tap_axis_tdata), 120 | .tap_axis_tkeep(tap_axis_tkeep), 121 | .tap_axis_tvalid(tap_axis_tvalid), 122 | .tap_axis_tready(tap_axis_tready), 123 | .tap_axis_tlast(tap_axis_tlast), 124 | .tap_axis_tid(tap_axis_tid), 125 | .tap_axis_tdest(tap_axis_tdest), 126 | .tap_axis_tuser(tap_axis_tuser), 127 | // AXI output 128 | .m_axis_tdata(m_axis_tdata), 129 | .m_axis_tkeep(m_axis_tkeep), 130 | .m_axis_tvalid(m_axis_tvalid), 131 | .m_axis_tready(m_axis_tready), 132 | .m_axis_tlast(m_axis_tlast), 133 | .m_axis_tid(m_axis_tid), 134 | .m_axis_tdest(m_axis_tdest), 135 | .m_axis_tuser(m_axis_tuser) 136 | ); 137 | 138 | endmodule 139 | -------------------------------------------------------------------------------- /tb/test_axis_tap_64.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2015-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for axis_tap 31 | */ 32 | module test_axis_tap_64; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 64; 36 | parameter KEEP_ENABLE = (DATA_WIDTH>8); 37 | parameter KEEP_WIDTH = (DATA_WIDTH/8); 38 | parameter ID_ENABLE = 1; 39 | parameter ID_WIDTH = 8; 40 | parameter DEST_ENABLE = 1; 41 | parameter DEST_WIDTH = 8; 42 | parameter USER_ENABLE = 1; 43 | parameter USER_WIDTH = 1; 44 | parameter USER_BAD_FRAME_VALUE = 1'b1; 45 | parameter USER_BAD_FRAME_MASK = 1'b1; 46 | 47 | // Inputs 48 | reg clk = 0; 49 | reg rst = 0; 50 | reg [7:0] current_test = 0; 51 | 52 | reg [DATA_WIDTH-1:0] tap_axis_tdata = 0; 53 | reg [KEEP_WIDTH-1:0] tap_axis_tkeep = 0; 54 | reg tap_axis_tvalid = 0; 55 | reg tap_axis_tready = 0; 56 | reg tap_axis_tlast = 0; 57 | reg [ID_WIDTH-1:0] tap_axis_tid = 0; 58 | reg [DEST_WIDTH-1:0] tap_axis_tdest = 0; 59 | reg [USER_WIDTH-1:0] tap_axis_tuser = 0; 60 | reg m_axis_tready = 0; 61 | 62 | // Outputs 63 | wire [DATA_WIDTH-1:0] m_axis_tdata; 64 | wire [KEEP_WIDTH-1:0] m_axis_tkeep; 65 | wire m_axis_tvalid; 66 | wire m_axis_tlast; 67 | wire [ID_WIDTH-1:0] m_axis_tid; 68 | wire [DEST_WIDTH-1:0] m_axis_tdest; 69 | wire [USER_WIDTH-1:0] m_axis_tuser; 70 | 71 | initial begin 72 | // myhdl integration 73 | $from_myhdl( 74 | clk, 75 | rst, 76 | current_test, 77 | tap_axis_tdata, 78 | tap_axis_tkeep, 79 | tap_axis_tvalid, 80 | tap_axis_tready, 81 | tap_axis_tlast, 82 | tap_axis_tid, 83 | tap_axis_tdest, 84 | tap_axis_tuser, 85 | m_axis_tready 86 | ); 87 | $to_myhdl( 88 | m_axis_tdata, 89 | m_axis_tkeep, 90 | m_axis_tvalid, 91 | m_axis_tlast, 92 | m_axis_tid, 93 | m_axis_tdest, 94 | m_axis_tuser 95 | ); 96 | 97 | // dump file 98 | $dumpfile("test_axis_tap_64.lxt"); 99 | $dumpvars(0, test_axis_tap_64); 100 | end 101 | 102 | axis_tap #( 103 | .DATA_WIDTH(DATA_WIDTH), 104 | .KEEP_ENABLE(KEEP_ENABLE), 105 | .KEEP_WIDTH(KEEP_WIDTH), 106 | .ID_ENABLE(ID_ENABLE), 107 | .ID_WIDTH(ID_WIDTH), 108 | .DEST_ENABLE(DEST_ENABLE), 109 | .DEST_WIDTH(DEST_WIDTH), 110 | .USER_ENABLE(USER_ENABLE), 111 | .USER_WIDTH(USER_WIDTH), 112 | .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), 113 | .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK) 114 | ) 115 | UUT ( 116 | .clk(clk), 117 | .rst(rst), 118 | // AXI tap 119 | .tap_axis_tdata(tap_axis_tdata), 120 | .tap_axis_tkeep(tap_axis_tkeep), 121 | .tap_axis_tvalid(tap_axis_tvalid), 122 | .tap_axis_tready(tap_axis_tready), 123 | .tap_axis_tlast(tap_axis_tlast), 124 | .tap_axis_tid(tap_axis_tid), 125 | .tap_axis_tdest(tap_axis_tdest), 126 | .tap_axis_tuser(tap_axis_tuser), 127 | // AXI output 128 | .m_axis_tdata(m_axis_tdata), 129 | .m_axis_tkeep(m_axis_tkeep), 130 | .m_axis_tvalid(m_axis_tvalid), 131 | .m_axis_tready(m_axis_tready), 132 | .m_axis_tlast(m_axis_tlast), 133 | .m_axis_tid(m_axis_tid), 134 | .m_axis_tdest(m_axis_tdest), 135 | .m_axis_tuser(m_axis_tuser) 136 | ); 137 | 138 | endmodule 139 | -------------------------------------------------------------------------------- /tb/test_ll_axis_bridge.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for ll_axis_bridge 31 | */ 32 | module test_ll_axis_bridge; 33 | 34 | // Parameters 35 | parameter DATA_WIDTH = 8; 36 | 37 | // Inputs 38 | reg clk = 0; 39 | reg rst = 0; 40 | reg [7:0] current_test = 0; 41 | 42 | reg [DATA_WIDTH-1:0] ll_data_in = 0; 43 | reg ll_sof_in_n = 1; 44 | reg ll_eof_in_n = 1; 45 | reg ll_src_rdy_in_n = 1; 46 | reg m_axis_tready = 0; 47 | 48 | // Outputs 49 | wire ll_dst_rdy_out_n; 50 | wire [DATA_WIDTH-1:0] m_axis_tdata; 51 | wire m_axis_tvalid; 52 | wire m_axis_tlast; 53 | 54 | initial begin 55 | // myhdl integration 56 | $from_myhdl( 57 | clk, 58 | rst, 59 | current_test, 60 | ll_data_in, 61 | ll_sof_in_n, 62 | ll_eof_in_n, 63 | ll_src_rdy_in_n, 64 | m_axis_tready 65 | ); 66 | $to_myhdl( 67 | m_axis_tdata, 68 | m_axis_tvalid, 69 | m_axis_tlast, 70 | ll_dst_rdy_out_n 71 | ); 72 | 73 | // dump file 74 | $dumpfile("test_ll_axis_bridge.lxt"); 75 | $dumpvars(0, test_ll_axis_bridge); 76 | end 77 | 78 | ll_axis_bridge #( 79 | .DATA_WIDTH(DATA_WIDTH) 80 | ) 81 | UUT ( 82 | .clk(clk), 83 | .rst(rst), 84 | // locallink input 85 | .ll_data_in(ll_data_in), 86 | .ll_sof_in_n(ll_sof_in_n), 87 | .ll_eof_in_n(ll_eof_in_n), 88 | .ll_src_rdy_in_n(ll_src_rdy_in_n), 89 | .ll_dst_rdy_out_n(ll_dst_rdy_out_n), 90 | // axi output 91 | .m_axis_tdata(m_axis_tdata), 92 | .m_axis_tvalid(m_axis_tvalid), 93 | .m_axis_tready(m_axis_tready), 94 | .m_axis_tlast(m_axis_tlast) 95 | ); 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /tb/test_priority_encoder.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | """ 3 | 4 | Copyright (c) 2014-2018 Alex Forencich 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in 14 | all copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | THE SOFTWARE. 23 | 24 | """ 25 | 26 | from myhdl import * 27 | import os 28 | 29 | module = 'priority_encoder' 30 | testbench = 'test_%s' % module 31 | 32 | srcs = [] 33 | 34 | srcs.append("../rtl/%s.v" % module) 35 | srcs.append("%s.v" % testbench) 36 | 37 | src = ' '.join(srcs) 38 | 39 | build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) 40 | 41 | def bench(): 42 | 43 | # Parameters 44 | WIDTH = 32 45 | LSB_HIGH_PRIORITY = 0 46 | 47 | # Inputs 48 | clk = Signal(bool(0)) 49 | rst = Signal(bool(0)) 50 | current_test = Signal(intbv(0)[8:]) 51 | 52 | input_unencoded = Signal(intbv(0)[WIDTH:]) 53 | 54 | # Outputs 55 | output_valid = Signal(bool(0)) 56 | output_encoded = Signal(intbv(0)[5:]) 57 | output_unencoded = Signal(intbv(0)[WIDTH:]) 58 | 59 | # DUT 60 | if os.system(build_cmd): 61 | raise Exception("Error running build command") 62 | 63 | dut = Cosimulation( 64 | "vvp -m myhdl %s.vvp -lxt2" % testbench, 65 | clk=clk, 66 | rst=rst, 67 | current_test=current_test, 68 | 69 | input_unencoded=input_unencoded, 70 | 71 | output_valid=output_valid, 72 | output_encoded=output_encoded, 73 | output_unencoded=output_unencoded 74 | ) 75 | 76 | @always(delay(4)) 77 | def clkgen(): 78 | clk.next = not clk 79 | 80 | @instance 81 | def check(): 82 | yield delay(100) 83 | yield clk.posedge 84 | rst.next = 1 85 | yield clk.posedge 86 | rst.next = 0 87 | yield clk.posedge 88 | yield delay(100) 89 | yield clk.posedge 90 | 91 | yield clk.posedge 92 | 93 | print("test 1: one bit") 94 | current_test.next = 1 95 | 96 | for i in range(32): 97 | input_unencoded.next = 1 << i 98 | 99 | yield clk.posedge 100 | 101 | assert output_encoded == i 102 | assert output_unencoded == 1 << i 103 | 104 | yield delay(100) 105 | 106 | yield clk.posedge 107 | 108 | print("test 2: two bits") 109 | current_test.next = 2 110 | 111 | for i in range(32): 112 | for j in range(32): 113 | 114 | input_unencoded.next = (1 << i) | (1 << j) 115 | 116 | yield clk.posedge 117 | 118 | assert output_encoded == max(i,j) 119 | assert output_unencoded == 1 << max(i,j) 120 | 121 | yield delay(100) 122 | 123 | raise StopSimulation 124 | 125 | return instances() 126 | 127 | def test_bench(): 128 | os.chdir(os.path.dirname(os.path.abspath(__file__))) 129 | sim = Simulation(bench()) 130 | sim.run() 131 | 132 | if __name__ == '__main__': 133 | print("Running test...") 134 | test_bench() 135 | 136 | -------------------------------------------------------------------------------- /tb/test_priority_encoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog 2001 26 | 27 | `timescale 1ns / 1ps 28 | 29 | /* 30 | * Testbench for priority_encoder 31 | */ 32 | module test_priority_encoder; 33 | 34 | // Parameters 35 | localparam WIDTH = 32; 36 | localparam LSB_HIGH_PRIORITY = 0; 37 | 38 | // Inputs 39 | reg clk = 0; 40 | reg rst = 0; 41 | reg [7:0] current_test = 0; 42 | 43 | reg [WIDTH-1:0] input_unencoded = 0; 44 | 45 | // Outputs 46 | wire output_valid; 47 | wire [$clog2(WIDTH)-1:0] output_encoded; 48 | wire [WIDTH-1:0] output_unencoded; 49 | 50 | initial begin 51 | // myhdl integration 52 | $from_myhdl( 53 | clk, 54 | rst, 55 | current_test, 56 | input_unencoded 57 | ); 58 | $to_myhdl( 59 | output_valid, 60 | output_encoded, 61 | output_unencoded 62 | ); 63 | 64 | // dump file 65 | $dumpfile("test_priority_encoder.lxt"); 66 | $dumpvars(0, test_priority_encoder); 67 | end 68 | 69 | priority_encoder #( 70 | .WIDTH(WIDTH), 71 | .LSB_HIGH_PRIORITY(LSB_HIGH_PRIORITY) 72 | ) 73 | UUT ( 74 | .input_unencoded(input_unencoded), 75 | .output_valid(output_valid), 76 | .output_encoded(output_encoded), 77 | .output_unencoded(output_unencoded) 78 | ); 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.20 21 | jinja2 == 3.1.2 22 | 23 | commands = 24 | pytest {posargs:-n auto --verbose} 25 | 26 | # pytest configuration 27 | [pytest] 28 | testpaths = 29 | tb 30 | addopts = 31 | --ignore-glob=tb/test_*.py 32 | --import-mode importlib 33 | --------------------------------------------------------------------------------