├── .gitignore ├── .travis.yml ├── AUTHORS ├── COPYING ├── README ├── README.md ├── rtl ├── arbiter.v ├── axis_wb_master.v ├── priority_encoder.v ├── wb_adapter.v ├── wb_arbiter.py ├── wb_arbiter_2.v ├── wb_async_reg.v ├── wb_dp_ram.v ├── wb_mux.py ├── wb_mux_2.v ├── wb_ram.v └── wb_reg.v └── tb ├── axis_ep.py ├── test_arbiter.py ├── test_arbiter.v ├── test_arbiter_rr.py ├── test_arbiter_rr.v ├── test_axis_wb_master_8_32.py ├── test_axis_wb_master_8_32.v ├── test_axis_wb_master_8_32_16.py ├── test_axis_wb_master_8_32_16.v ├── test_axis_wb_master_8_32_imp.py ├── test_axis_wb_master_8_32_imp.v ├── test_priority_encoder.py ├── test_priority_encoder.v ├── test_wb.py ├── test_wb_16.py ├── test_wb_adapter_16_32.py ├── test_wb_adapter_16_32.v ├── test_wb_adapter_32_16.py ├── test_wb_adapter_32_16.v ├── test_wb_adapter_32_8.py ├── test_wb_adapter_32_8.v ├── test_wb_adapter_8_32.py ├── test_wb_adapter_8_32.v ├── test_wb_arbiter_2.py ├── test_wb_arbiter_2.v ├── test_wb_async_reg.py ├── test_wb_async_reg.v ├── test_wb_dp_ram.py ├── test_wb_dp_ram.v ├── test_wb_mux_2.py ├── test_wb_mux_2.v ├── test_wb_ram.py ├── test_wb_ram.v ├── test_wb_ram_model.py ├── test_wb_reg.py ├── test_wb_reg.v └── wb.py /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/.gitignore -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/.travis.yml -------------------------------------------------------------------------------- /AUTHORS: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/AUTHORS -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/COPYING -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | README.md -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/README.md -------------------------------------------------------------------------------- /rtl/arbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/arbiter.v -------------------------------------------------------------------------------- /rtl/axis_wb_master.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/axis_wb_master.v -------------------------------------------------------------------------------- /rtl/priority_encoder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/priority_encoder.v -------------------------------------------------------------------------------- /rtl/wb_adapter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_adapter.v -------------------------------------------------------------------------------- /rtl/wb_arbiter.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_arbiter.py -------------------------------------------------------------------------------- /rtl/wb_arbiter_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_arbiter_2.v -------------------------------------------------------------------------------- /rtl/wb_async_reg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_async_reg.v -------------------------------------------------------------------------------- /rtl/wb_dp_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_dp_ram.v -------------------------------------------------------------------------------- /rtl/wb_mux.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_mux.py -------------------------------------------------------------------------------- /rtl/wb_mux_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_mux_2.v -------------------------------------------------------------------------------- /rtl/wb_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_ram.v -------------------------------------------------------------------------------- /rtl/wb_reg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/rtl/wb_reg.v -------------------------------------------------------------------------------- /tb/axis_ep.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/axis_ep.py -------------------------------------------------------------------------------- /tb/test_arbiter.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_arbiter.py -------------------------------------------------------------------------------- /tb/test_arbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_arbiter.v -------------------------------------------------------------------------------- /tb/test_arbiter_rr.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_arbiter_rr.py -------------------------------------------------------------------------------- /tb/test_arbiter_rr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_arbiter_rr.v -------------------------------------------------------------------------------- /tb/test_axis_wb_master_8_32.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_axis_wb_master_8_32.py -------------------------------------------------------------------------------- /tb/test_axis_wb_master_8_32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_axis_wb_master_8_32.v -------------------------------------------------------------------------------- /tb/test_axis_wb_master_8_32_16.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_axis_wb_master_8_32_16.py -------------------------------------------------------------------------------- /tb/test_axis_wb_master_8_32_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_axis_wb_master_8_32_16.v -------------------------------------------------------------------------------- /tb/test_axis_wb_master_8_32_imp.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_axis_wb_master_8_32_imp.py -------------------------------------------------------------------------------- /tb/test_axis_wb_master_8_32_imp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_axis_wb_master_8_32_imp.v -------------------------------------------------------------------------------- /tb/test_priority_encoder.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_priority_encoder.py -------------------------------------------------------------------------------- /tb/test_priority_encoder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_priority_encoder.v -------------------------------------------------------------------------------- /tb/test_wb.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb.py -------------------------------------------------------------------------------- /tb/test_wb_16.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_16.py -------------------------------------------------------------------------------- /tb/test_wb_adapter_16_32.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_16_32.py -------------------------------------------------------------------------------- /tb/test_wb_adapter_16_32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_16_32.v -------------------------------------------------------------------------------- /tb/test_wb_adapter_32_16.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_32_16.py -------------------------------------------------------------------------------- /tb/test_wb_adapter_32_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_32_16.v -------------------------------------------------------------------------------- /tb/test_wb_adapter_32_8.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_32_8.py -------------------------------------------------------------------------------- /tb/test_wb_adapter_32_8.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_32_8.v -------------------------------------------------------------------------------- /tb/test_wb_adapter_8_32.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_8_32.py -------------------------------------------------------------------------------- /tb/test_wb_adapter_8_32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_adapter_8_32.v -------------------------------------------------------------------------------- /tb/test_wb_arbiter_2.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_arbiter_2.py -------------------------------------------------------------------------------- /tb/test_wb_arbiter_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_arbiter_2.v -------------------------------------------------------------------------------- /tb/test_wb_async_reg.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_async_reg.py -------------------------------------------------------------------------------- /tb/test_wb_async_reg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_async_reg.v -------------------------------------------------------------------------------- /tb/test_wb_dp_ram.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_dp_ram.py -------------------------------------------------------------------------------- /tb/test_wb_dp_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_dp_ram.v -------------------------------------------------------------------------------- /tb/test_wb_mux_2.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_mux_2.py -------------------------------------------------------------------------------- /tb/test_wb_mux_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_mux_2.v -------------------------------------------------------------------------------- /tb/test_wb_ram.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_ram.py -------------------------------------------------------------------------------- /tb/test_wb_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_ram.v -------------------------------------------------------------------------------- /tb/test_wb_ram_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_ram_model.py -------------------------------------------------------------------------------- /tb/test_wb_reg.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_reg.py -------------------------------------------------------------------------------- /tb/test_wb_reg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/test_wb_reg.v -------------------------------------------------------------------------------- /tb/wb.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/alexforencich/verilog-wishbone/HEAD/tb/wb.py --------------------------------------------------------------------------------