├── 1024Mb_ddr3_parameters.vh ├── README.md ├── ddr3.v ├── ddr3_controller.sv ├── defs.svh ├── intf.svh ├── sg093.v ├── st_defs.svh └── top.sv /1024Mb_ddr3_parameters.vh: -------------------------------------------------------------------------------- 1 | //a given parameter for ddr3.v 2 | 3 | /**************************************************************************************** 4 | * 5 | * Disclaimer This software code and all associated documentation, comments or other 6 | * of Warranty: information (collectively "Software") is provided "AS IS" without 7 | * warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 8 | * DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 9 | * TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 10 | * OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 11 | * WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 12 | * OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 13 | * FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 14 | * THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 15 | * ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 16 | * OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 17 | * ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 18 | * INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 19 | * WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 20 | * OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 21 | * THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 22 | * DAMAGES. Because some jurisdictions prohibit the exclusion or 23 | * limitation of liability for consequential or incidental damages, the 24 | * above limitation may not apply to you. 25 | * 26 | * Copyright 2003 Micron Technology, Inc. All rights reserved. 27 | * 28 | ****************************************************************************************/ 29 | 30 | // Timing parameters based on 1Gb_DDR3_SDRAM.cdf - Rev. L 09/12 EN 31 | 32 | // SYMBOL UNITS DESCRIPTION 33 | // ------ ----- ----------- 34 | `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin 35 | parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time 36 | parameter TJIT_PER = 50; // tJIT(per) ps Period JItter 37 | parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter 38 | parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) 39 | parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) 40 | parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) 41 | parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) 42 | parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) 43 | parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) 44 | parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) 45 | parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) 46 | parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) 47 | parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) 48 | parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) 49 | parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS 50 | parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS 51 | parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 52 | parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 53 | parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) 54 | parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) 55 | parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# 56 | parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width 57 | parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width 58 | parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width 59 | parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width 60 | parameter TIS = 35; // tIS ps Input Setup Time 61 | parameter TIH = 75; // tIH ps Input Hold Time 62 | parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time 63 | parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time 64 | parameter TRCD = 13090; // tRCD ps Active to Read/Write command time 65 | parameter TRP = 13090; // tRP ps Precharge command period 66 | parameter TXP = 6000; // tXP ps Exit power down to a valid command 67 | parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width 68 | parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference 69 | parameter TWLS = 122; // tWLS ps Setup time for tDQS flop 70 | parameter TWLH = 122; // tWLH ps Hold time of tDQS flop 71 | parameter TWLO = 7500; // tWLO ps Write levelization output delay 72 | parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data 73 | parameter CL_TIME = 13090; // CL ps Minimum CAS Latency 74 | `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin 75 | parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time 76 | parameter TJIT_PER = 60; // tJIT(per) ps Period JItter 77 | parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter 78 | parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) 79 | parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) 80 | parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) 81 | parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) 82 | parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) 83 | parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) 84 | parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) 85 | parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) 86 | parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) 87 | parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) 88 | parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) 89 | parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS 90 | parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS 91 | parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 92 | parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 93 | parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) 94 | parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) 95 | parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# 96 | parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width 97 | parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width 98 | parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width 99 | parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width 100 | parameter TIS = 50; // tIS ps Input Setup Time 101 | parameter TIH = 100; // tIH ps Input Hold Time 102 | parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time 103 | parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time 104 | parameter TRCD = 13910; // tRCD ps Active to Read/Write command time 105 | parameter TRP = 13910; // tRP ps Precharge command period 106 | parameter TXP = 6000; // tXP ps Exit power down to a valid command 107 | parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width 108 | parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference 109 | parameter TWLS = 140; // tWLS ps Setup time for tDQS flop 110 | parameter TWLH = 140; // tWLH ps Hold time of tDQS flop 111 | parameter TWLO = 7500; // tWLO ps Write levelization output delay 112 | parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data 113 | parameter CL_TIME = 13910; // CL ps Minimum CAS Latency 114 | `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin 115 | parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time 116 | parameter TJIT_PER = 70; // tJIT(per) ps Period JItter 117 | parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter 118 | parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) 119 | parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) 120 | parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) 121 | parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) 122 | parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) 123 | parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) 124 | parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) 125 | parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) 126 | parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) 127 | parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) 128 | parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) 129 | parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS 130 | parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS 131 | parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 132 | parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 133 | parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) 134 | parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) 135 | parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# 136 | parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width 137 | parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width 138 | parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width 139 | parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width 140 | parameter TIS = 170; // tIS ps Input Setup Time 141 | parameter TIH = 120; // tIH ps Input Hold Time 142 | parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time 143 | parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time 144 | parameter TRCD = 13750; // tRCD ps Active to Read/Write command time 145 | parameter TRP = 13750; // tRP ps Precharge command period 146 | parameter TXP = 6000; // tXP ps Exit power down to a valid command 147 | parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width 148 | parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference 149 | parameter TWLS = 165; // tWLS ps Setup time for tDQS flop 150 | parameter TWLH = 165; // tWLH ps Hold time of tDQS flop 151 | parameter TWLO = 7500; // tWLO ps Write levelization output delay 152 | parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data 153 | parameter CL_TIME = 13750; // CL ps Minimum CAS Latency 154 | `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin 155 | parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time 156 | parameter TJIT_PER = 80; // tJIT(per) ps Period JItter 157 | parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter 158 | parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) 159 | parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) 160 | parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) 161 | parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) 162 | parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) 163 | parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) 164 | parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) 165 | parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) 166 | parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) 167 | parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) 168 | parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) 169 | parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS 170 | parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS 171 | parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 172 | parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 173 | parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) 174 | parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) 175 | parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# 176 | parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width 177 | parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width 178 | parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width 179 | parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width 180 | parameter TIS = 190; // tIS ps Input Setup Time 181 | parameter TIH = 140; // tIH ps Input Hold Time 182 | parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time 183 | parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time 184 | parameter TRCD = 13500; // tRCD ps Active to Read/Write command time 185 | parameter TRP = 13500; // tRP ps Precharge command period 186 | parameter TXP = 6000; // tXP ps Exit power down to a valid command 187 | parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width 188 | parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference 189 | parameter TWLS = 195; // tWLS ps Setup time for tDQS flop 190 | parameter TWLH = 195; // tWLH ps Hold time of tDQS flop 191 | parameter TWLO = 9000; // tWLO ps Write levelization output delay 192 | parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data 193 | parameter CL_TIME = 13500; // CL ps Minimum CAS Latency 194 | `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin 195 | parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time 196 | parameter TJIT_PER = 80; // tJIT(per) ps Period JItter 197 | parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter 198 | parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) 199 | parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) 200 | parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) 201 | parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) 202 | parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) 203 | parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) 204 | parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) 205 | parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) 206 | parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) 207 | parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) 208 | parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) 209 | parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS 210 | parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS 211 | parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 212 | parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 213 | parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) 214 | parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) 215 | parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# 216 | parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width 217 | parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width 218 | parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width 219 | parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width 220 | parameter TIS = 190; // tIS ps Input Setup Time 221 | parameter TIH = 140; // tIH ps Input Hold Time 222 | parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time 223 | parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time 224 | parameter TRCD = 15000; // tRCD ps Active to Read/Write command time 225 | parameter TRP = 15000; // tRP ps Precharge command period 226 | parameter TXP = 6000; // tXP ps Exit power down to a valid command 227 | parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width 228 | parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference 229 | parameter TWLS = 195; // tWLS ps Setup time for tDQS flop 230 | parameter TWLH = 195; // tWLH ps Hold time of tDQS flop 231 | parameter TWLO = 9000; // tWLO ps Write levelization output delay 232 | parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data 233 | parameter CL_TIME = 15000; // CL ps Minimum CAS Latency 234 | `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin 235 | parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time 236 | parameter TJIT_PER = 90; // tJIT(per) ps Period JItter 237 | parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter 238 | parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) 239 | parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) 240 | parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) 241 | parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) 242 | parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) 243 | parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) 244 | parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) 245 | parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) 246 | parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) 247 | parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) 248 | parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) 249 | parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS 250 | parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS 251 | parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 252 | parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 253 | parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) 254 | parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) 255 | parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# 256 | parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width 257 | parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width 258 | parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width 259 | parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width 260 | parameter TIS = 275; // tIS ps Input Setup Time 261 | parameter TIH = 200; // tIH ps Input Hold Time 262 | parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time 263 | parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time 264 | parameter TRCD = 13125; // tRCD ps Active to Read/Write command time 265 | parameter TRP = 13125; // tRP ps Precharge command period 266 | parameter TXP = 7500; // tXP ps Exit power down to a valid command 267 | parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width 268 | parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference 269 | parameter TWLS = 245; // tWLS ps Setup time for tDQS flop 270 | parameter TWLH = 245; // tWLH ps Hold time of tDQS flop 271 | parameter TWLO = 9000; // tWLO ps Write levelization output delay 272 | parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data 273 | parameter CL_TIME = 13125; // CL ps Minimum CAS Latency 274 | `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin 275 | parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time 276 | parameter TJIT_PER = 90; // tJIT(per) ps Period JItter 277 | parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter 278 | parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) 279 | parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) 280 | parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) 281 | parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) 282 | parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) 283 | parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) 284 | parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) 285 | parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) 286 | parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) 287 | parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) 288 | parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) 289 | parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS 290 | parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS 291 | parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 292 | parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 293 | parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) 294 | parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) 295 | parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# 296 | parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width 297 | parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width 298 | parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width 299 | parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width 300 | parameter TIS = 275; // tIS ps Input Setup Time 301 | parameter TIH = 200; // tIH ps Input Hold Time 302 | parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time 303 | parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time 304 | parameter TRCD = 15000; // tRCD ps Active to Read/Write command time 305 | parameter TRP = 15000; // tRP ps Precharge command period 306 | parameter TXP = 7500; // tXP ps Exit power down to a valid command 307 | parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width 308 | parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference 309 | parameter TWLS = 245; // tWLS ps Setup time for tDQS flop 310 | parameter TWLH = 245; // tWLH ps Hold time of tDQS flop 311 | parameter TWLO = 9000; // tWLO ps Write levelization output delay 312 | parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data 313 | parameter CL_TIME = 15000; // CL ps Minimum CAS Latency 314 | `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800E (5-5-5) speed bin 315 | parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time 316 | parameter TJIT_PER = 100; // tJIT(per) ps Period JItter 317 | parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter 318 | parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) 319 | parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) 320 | parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) 321 | parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) 322 | parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) 323 | parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) 324 | parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) 325 | parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) 326 | parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) 327 | parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) 328 | parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) 329 | parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS 330 | parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS 331 | parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 332 | parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 333 | parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) 334 | parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) 335 | parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# 336 | parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width 337 | parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width 338 | parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width 339 | parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width 340 | parameter TIS = 350; // tIS ps Input Setup Time 341 | parameter TIH = 275; // tIH ps Input Hold Time 342 | parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time 343 | parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time 344 | parameter TRCD = 12500; // tRCD ps Active to Read/Write command time 345 | parameter TRP = 12500; // tRP ps Precharge command period 346 | parameter TXP = 7500; // tXP ps Exit power down to a valid command 347 | parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width 348 | parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference 349 | parameter TWLS = 325; // tWLS ps Setup time for tDQS flop 350 | parameter TWLH = 325; // tWLH ps Hold time of tDQS flop 351 | parameter TWLO = 9000; // tWLO ps Write levelization output delay 352 | parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data 353 | parameter CL_TIME = 12500; // CL ps Minimum CAS Latency 354 | `else 355 | `define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin 356 | parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time 357 | parameter TJIT_PER = 100; // tJIT(per) ps Period JItter 358 | parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter 359 | parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) 360 | parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) 361 | parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) 362 | parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) 363 | parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) 364 | parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) 365 | parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) 366 | parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) 367 | parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) 368 | parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) 369 | parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) 370 | parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS 371 | parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS 372 | parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 373 | parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 374 | parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) 375 | parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) 376 | parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# 377 | parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width 378 | parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width 379 | parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width 380 | parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width 381 | parameter TIS = 350; // tIS ps Input Setup Time 382 | parameter TIH = 275; // tIH ps Input Hold Time 383 | parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time 384 | parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time 385 | parameter TRCD = 15000; // tRCD ps Active to Read/Write command time 386 | parameter TRP = 15000; // tRP ps Precharge command period 387 | parameter TXP = 7500; // tXP ps Exit power down to a valid command 388 | parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width 389 | parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference 390 | parameter TWLS = 325; // tWLS ps Setup time for tDQS flop 391 | parameter TWLH = 325; // tWLH ps Hold time of tDQS flop 392 | parameter TWLO = 9000; // tWLO ps Write levelization output delay 393 | parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data 394 | parameter CL_TIME = 15000; // CL ps Minimum CAS Latency 395 | `endif 396 | 397 | parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed 398 | 399 | `ifdef x16 400 | `ifdef sg093 401 | parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time 402 | parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window 403 | `elsif sg107 404 | parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time 405 | parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window 406 | `elsif sg125 407 | parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time 408 | parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window 409 | `elsif sg15E 410 | parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time 411 | parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window 412 | `elsif sg15 413 | parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time 414 | parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window 415 | `elsif sg187E 416 | parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time 417 | parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window 418 | `elsif sg187 419 | parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time 420 | parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window 421 | `elsif sg25E 422 | parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time 423 | parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window 424 | `else // sg25 425 | parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time 426 | parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window 427 | `endif 428 | `else // x4, x8 429 | `ifdef sg093 430 | parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 431 | parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window 432 | `elsif sg107 433 | parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 434 | parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window 435 | `elsif sg125 436 | parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 437 | parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window 438 | `elsif sg15E 439 | parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 440 | parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window 441 | `elsif sg15 442 | parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 443 | parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window 444 | `elsif sg187E 445 | parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time 446 | parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window 447 | `elsif sg187 448 | parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time 449 | parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window 450 | `elsif sg25E 451 | parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 452 | parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window 453 | `else // sg25 454 | parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 455 | parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window 456 | `endif 457 | `endif 458 | 459 | // Timing Parameters 460 | 461 | // Mode Register 462 | parameter CL_MIN = 5; // CL tCK Minimum CAS Latency 463 | parameter CL_MAX = 14; // CL tCK Maximum CAS Latency 464 | parameter AL_MIN = 0; // AL tCK Minimum Additive Latency 465 | parameter AL_MAX = 2; // AL tCK Maximum Additive Latency 466 | parameter WR_MIN = 5; // WR tCK Minimum Write Recovery 467 | parameter WR_MAX = 16; // WR tCK Maximum Write Recovery 468 | parameter BL_MIN = 4; // BL tCK Minimum Burst Length 469 | parameter BL_MAX = 8; // BL tCK Minimum Burst Length 470 | parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency 471 | parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency 472 | 473 | // Clock 474 | parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time 475 | parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width 476 | parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width 477 | parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width 478 | parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width 479 | parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width 480 | parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width 481 | parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width 482 | parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data 483 | 484 | // Data OUT 485 | parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# 486 | // Data Strobe OUT 487 | parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble 488 | parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble 489 | // Data Strobe IN 490 | parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width 491 | parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width 492 | parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble 493 | parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble 494 | // Command and Address 495 | integer TZQCS; // tZQCS tCK ZQ Cal (Short) time 496 | integer TZQINIT; // tZQinit tCK ZQ Cal (Long) time 497 | integer TZQOPER; // tZQoper tCK ZQ Cal (Long) time 498 | parameter TCCD = 4; // tCCD tCK Cas to Cas command delay 499 | parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group 500 | parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time 501 | parameter TWR = 15000; // tWR ps Write recovery time 502 | parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time 503 | parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time 504 | parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time 505 | parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time 506 | parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group 507 | parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group 508 | parameter TRTP = 7500; // tRTP ps Read to Precharge command delay 509 | parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay 510 | parameter TWTR = 7500; // tWTR ps Write to Read command delay 511 | parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group 512 | parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay 513 | parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group 514 | parameter TDLLK = 512; // tDLLK tCK DLL locking time 515 | // Refresh - 1Gb 516 | parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value 517 | parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value 518 | // Power Down 519 | parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command 520 | parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) 521 | parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) 522 | parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry 523 | parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry 524 | parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry 525 | parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay 526 | parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing 527 | parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command 528 | parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command 529 | // Self Refresh 530 | parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command 531 | parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command 532 | parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command 533 | parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. 534 | parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) 535 | parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) 536 | parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) 537 | parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) 538 | parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing 539 | // ODT 540 | parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference 541 | parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) 542 | parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) 543 | parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) 544 | parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) 545 | parameter TADC = 0.7; // tADC tCK RTT dynamic change skew 546 | // Write Levelization 547 | parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed 548 | parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed 549 | parameter TWLOE = 2000; // tWLOE ps Write levelization output error 550 | 551 | // Size Parameters based on Part Width 552 | 553 | `ifdef x4 554 | parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used 555 | parameter ADDR_BITS = 14; // MAX Address Bits 556 | parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used 557 | parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used 558 | parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** 559 | parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used 560 | `elsif x8 561 | parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used 562 | parameter ADDR_BITS = 14; // MAX Address Bits 563 | parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used 564 | parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used 565 | parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** 566 | parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used 567 | `else 568 | `define x16 569 | parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used 570 | parameter ADDR_BITS = 13; // MAX Address Bits 571 | parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used 572 | parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used 573 | parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** 574 | parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used 575 | `endif 576 | 577 | // Size Parameters 578 | parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used 579 | parameter MEM_BITS = 10; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. 580 | parameter AP = 10; // the address bit that controls auto-precharge and precharge-all 581 | parameter BC = 12; // the address bit that controls burst chop 582 | parameter BL_BITS = 3; // the number of bits required to count to BL_MAX 583 | parameter BO_BITS = 2; // the number of Burst Order Bits 584 | 585 | `ifdef QUAD_RANK 586 | parameter CS_BITS = 4; // Number of Chip Select Bits 587 | parameter RANKS = 4; // Number of Chip Selects 588 | `elsif DUAL_RANK 589 | parameter CS_BITS = 2; // Number of Chip Select Bits 590 | parameter RANKS = 2; // Number of Chip Selects 591 | `else 592 | parameter CS_BITS = 1; // Number of Chip Select Bits 593 | parameter RANKS = 1; // Number of Chip Selects 594 | `endif 595 | 596 | // Simulation parameters 597 | parameter RZQ = 240; // termination resistance 598 | parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout 599 | parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors 600 | parameter DEBUG = 1; // Turn on Debug messages 601 | parameter BUS_DELAY = 0; // delay in nanoseconds 602 | parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads 603 | parameter RANDOM_SEED = 31913; //seed value for random generator. 604 | 605 | parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe 606 | parameter RDQSEN_PST = 1; // DQS driving time after last read strobe 607 | parameter RDQS_PRE = 2; // DQS low time prior to first read strobe 608 | parameter RDQS_PST = 1; // DQS low time after last read strobe 609 | parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data 610 | parameter RDQEN_PST = 0; // DQ/DM driving time after last read data 611 | parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe 612 | parameter WDQS_PST = 1; // DQS half clock periods after last write strobe 613 | 614 | // check for legal cas latency based on the cas write latency 615 | function valid_cl; 616 | input [3:0] cl; 617 | input [3:0] cwl; 618 | 619 | case ({cwl, cl}) 620 | `ifdef sg093 621 | {4'd5 , 4'd5 }, 622 | {4'd5 , 4'd6 }, 623 | {4'd6 , 4'd7 }, 624 | {4'd6 , 4'd8 }, 625 | {4'd7 , 4'd9 }, 626 | {4'd7 , 4'd10}, 627 | {4'd8 , 4'd11}, 628 | {4'd9 , 4'd13}, 629 | {4'd10, 4'd14}: valid_cl = 1; 630 | `elsif sg107 631 | {4'd5, 4'd5 }, 632 | {4'd5, 4'd6 }, 633 | {4'd6, 4'd7 }, 634 | {4'd6, 4'd8 }, 635 | {4'd7, 4'd9 }, 636 | {4'd7, 4'd10}, 637 | {4'd8, 4'd11}, 638 | {4'd9, 4'd13}: valid_cl = 1; 639 | `elsif sg125 640 | {4'd5, 4'd5 }, 641 | {4'd5, 4'd6 }, 642 | {4'd6, 4'd7 }, 643 | {4'd6, 4'd8 }, 644 | {4'd7, 4'd9 }, 645 | {4'd7, 4'd10}, 646 | {4'd8, 4'd11}: valid_cl = 1; 647 | `elsif sg15E 648 | {4'd5, 4'd5 }, 649 | {4'd5, 4'd6 }, 650 | {4'd6, 4'd7 }, 651 | {4'd6, 4'd8 }, 652 | {4'd7, 4'd9 }, 653 | {4'd7, 4'd10}: valid_cl = 1; 654 | `elsif sg15 655 | {4'd5, 4'd5 }, 656 | {4'd5, 4'd6 }, 657 | {4'd6, 4'd8 }, 658 | {4'd7, 4'd10}: valid_cl = 1; 659 | `elsif sg187E 660 | {4'd5, 4'd5 }, 661 | {4'd5, 4'd6 }, 662 | {4'd6, 4'd7 }, 663 | {4'd6, 4'd8 }: valid_cl = 1; 664 | `elsif sg187 665 | {4'd5, 4'd5 }, 666 | {4'd5, 4'd6 }, 667 | {4'd6, 4'd8 }: valid_cl = 1; 668 | `elsif sg25E 669 | {4'd5, 4'd5 }, 670 | {4'd5, 4'd6 }: valid_cl = 1; 671 | `elsif sg25 672 | {4'd5, 4'd5 }, 673 | {4'd5, 4'd6 }: valid_cl = 1; 674 | `endif 675 | default : valid_cl = 0; 676 | endcase 677 | endfunction 678 | 679 | // find the minimum valid cas write latency 680 | function [3:0] min_cwl; 681 | input period; 682 | real period; 683 | min_cwl = (period >= 2500.0) ? 5: 684 | (period >= 1875.0) ? 6: 685 | (period >= 1500.0) ? 7: 686 | (period >= 1250.0) ? 8: 687 | (period >= 1071.0) ? 9: 688 | 10; // (period >= 938) 689 | endfunction 690 | 691 | // find the minimum valid cas latency 692 | function [3:0] min_cl; 693 | input period; 694 | real period; 695 | reg [3:0] cwl; 696 | reg [3:0] cl; 697 | begin 698 | cwl = min_cwl(period); 699 | for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin 700 | if (valid_cl(cl, cwl)) begin 701 | min_cl = cl; 702 | end 703 | end 704 | end 705 | endfunction 706 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SystemVerilog-Implementation-of-DDR3-Controller 2 | This is a group project. The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface. 3 | 4 | 5 | - top.sv top module 6 | - ddr3_controller.sv a ddr3 memory controller 7 | - st_defs.svh a parameter for ddr3_controller.sv, controller states 8 | - intf.sv an interface to connect ddr3_controller.sv and ddr3.v 9 | 10 | - ddr3.v a given ddr3 memory 11 | - 1024Mb_ddr3_parameters.vh a given parameter for ddr3.v 12 | - sg093.v a given parameter for ddr3.v 13 | - defs.svh a given parameter for ddr3.v 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /ddr3_controller.sv: -------------------------------------------------------------------------------- 1 | //a ddr3 memory controller 2 | 3 | `timescale 1ps/1ps 4 | 5 | `include "intf.svh" 6 | module ddr3_controller ( intf.cntrl ix,iftb.cntrl ixtb); 7 | `include "defs.svh" 8 | `include "st_defs.svh" 9 | /*`ifdef den1024Mb 10 | `include "1024Mb_ddr3_parameters.vh" 11 | `elsif den2048Mb 12 | `include "2048Mb_ddr3_parameters.vh" 13 | `elsif den4096Mb 14 | `include "4096Mb_ddr3_parameters.vh" 15 | `elsif den8192Mb 16 | `include "8192Mb_ddr3_parameters.vh" 17 | `else 18 | // NOTE: Intentionally cause a compile fail here to force the users 19 | // to select the correct component density before continuing 20 | ERROR: You must specify component density with +define+den____Mb. 21 | `endif*/ 22 | 23 | 24 | //Intermediate Registers 25 | wire ck; 26 | reg rst_n; 27 | reg cke; 28 | reg cs_n; 29 | reg ras_n; 30 | reg cas_n; 31 | reg we_n; 32 | reg [BA_BITS-1:0] ba; 33 | reg [ADDR_BITS-1:0] addr; 34 | wire [BA_BITS-1:0] ba_in; 35 | logic active_banks[BA_BITS-1:0]; 36 | reg [BA_BITS-1:0] prev_bank; 37 | wire [ADDR_BITS-1:0] addr_in; 38 | wire [DQ_BITS-1:0] dq; 39 | wire [DQS_BITS-1:0] tdqs_n; 40 | wire [COL_BITS-1:0] col; 41 | wire [COL_BITS-1:0] row; 42 | reg [COL_BITS-1:0] prev_row; 43 | reg [ADDR_BITS-1:0] a [BA_BITS-1:0]; 44 | reg [COL_BITS-1:0] col_incr; 45 | reg [COL_BITS-1:0] col_start; 46 | 47 | //state assignment regs/command regs 48 | reg [31:0] cnt,counter,wcnt,index; 49 | reg cnt_en,c_en,init_phase; 50 | reg [31:0] bcnt; 51 | integer lock; 52 | reg cmd_en = 1'b1; 53 | integer done ; 54 | reg [4:0] cmd,prev_cmd; //enum for ddr3 commands 55 | reg [3:0] rd_cmd; //enum for read options 56 | reg [3:0] wr_cmd; //write options 57 | integer ap; //Auto Precharge 58 | integer bc; //Burst Chop 59 | integer rlen; 60 | integer i; 61 | reg pwr_on; 62 | integer en = 0; 63 | reg pl = 1'b1; 64 | reg [31:0] cnt_p; 65 | reg cnt_p_en,nlock,tlock,nop_run; 66 | int nxt_state; 67 | //reg st_en; 68 | time_st st_tm; 69 | //state 70 | int st,prev_state,next_state; 71 | 72 | 73 | 74 | // dq transmit 75 | reg dq_en; 76 | reg [DM_BITS-1:0] dm_out; 77 | reg [DQ_BITS-1:0] dq_out; 78 | reg dqs_en; 79 | reg [DQS_BITS-1:0] dqs_out; 80 | 81 | 82 | 83 | //To and from memory<-->controller interface 84 | /*THIS IS ASSIGNED IN CONTROLLER*/ 85 | assign ix.rst_n = rst_n; 86 | assign ck = ix.ck; 87 | assign ix.ck_n = ~ix.ck; 88 | assign ix.cke = cke; 89 | assign ix.cs_n = cs_n; 90 | assign ix.ras_n = ras_n; 91 | assign ix.cas_n = cas_n; 92 | assign dq = ix.dq0; 93 | assign ix.we_n = we_n; 94 | assign ix.dm = dq_en ? dm_out :{DM_BITS{1'bz}}; 95 | assign ix.ba = ba; 96 | assign ix.addr = addr; 97 | assign ix.dq = dq_en ? dq_out : {DQ_BITS{1'bz}}; //data is sent to memory using dq_out 98 | assign ix.dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}}; 99 | assign ix.dqs_n = dqs_en ? ~dqs_out : {DQS_BITS{1'bz}}; 100 | assign ix.odt = odt_out & !odt_fifo[0]; 101 | 102 | 103 | //from and to testbench<-->controller interface 104 | assign dq_in = ixtb.dq; //dq passed to controller from testbench using dq_in 105 | assign dm_in = ixtb.dm; 106 | assign ba_in = ixtb.ba; 107 | assign addr_in = ixtb.addr; 108 | assign row = ixtb.row; 109 | assign col = ixtb.col; 110 | assign ixtb.cmd_en = cmd_en; //to test bench 111 | assign cmd = ixtb.cmd ; 112 | assign rd_cmd = ixtb.rd_cmd; 113 | assign bc = ixtb.wr_cmd; 114 | assign ap = ixtb.ap; 115 | assign wr_cmd = ixtb.wr_cmd; 116 | assign rlen = ixtb.rlen; 117 | assign nxt_state = ixtb.next_state; 118 | //assign odt_fifo = !ix.ck ? odt_fifo>>1:odt_fifo; 119 | //initial begin 120 | 121 | // $monitor($time,"\tcntrl:command == %d",cmd); 122 | 123 | //end 124 | 125 | reg [31:0] nop_cnt; 126 | reg nop_cnt_en; 127 | logic [31:0] rw_cnt; 128 | logic rw_cnt_en; 129 | integer npt; 130 | 131 | //always @ (ix.ck) begin 132 | //if (!ix.ck) 133 | //odt_fifo <= odt_fifo>>1; 134 | //end 135 | 136 | always @(negedge ix.ck)begin//* //slower clock with period = tck_min (ddr3 clock) 137 | if (nop_cnt_en) nop_cnt <= nop_cnt +1; 138 | else begin 139 | //$display($time,"\tcntrl: counter = %d",counter); 140 | nop_cnt <= 1'b0; 141 | end 142 | end 143 | 144 | always @(negedge ixtb.clk)begin//* 145 | if (rw_cnt_en) rw_cnt <= rw_cnt +1; 146 | else begin 147 | //$display($time,"\tcntrl: counter = %d",counter); 148 | rw_cnt <= 1'b0; 149 | end 150 | end 151 | 152 | 153 | 154 | always @(negedge ix.ck or negedge ixtb.rst) begin 155 | 156 | 157 | if (ixtb.rst==0) 158 | begin 159 | ba<=000; 160 | addr<=0; 161 | rst_n<=0; 162 | //ck=0; 163 | cke <= 0; 164 | cs_n<=0; 165 | ras_n<=0; 166 | cas_n<=0; 167 | we_n<=0; 168 | counter <= 0; 169 | cnt <= 0; 170 | prev_state <= st; 171 | dq_en <= 1'b0; 172 | dqs_en <= 1'b0; 173 | odt_fifo <= 1'b0; 174 | init_phase <= 1'b0; 175 | nlock <= 1'b0; 176 | tlock <= 1'b0; 177 | nop_run <= 0; 178 | en <= 1'b1; 179 | st <= initialize; 180 | end 181 | else 182 | begin 183 | //if(pwr_on) begin 184 | if(cmd == pwr_up && pl == 1)begin 185 | st <= power_up; 186 | en <= 1'b1; 187 | cmd_en <= 1'b0; 188 | pl <= 1'b0; 189 | end else begin 190 | odt_fifo <= odt_fifo>>1; 191 | 192 | case (st) 193 | power_up: begin 194 | if (en)begin 195 | cmd_en <= 1'b0; 196 | done <= 1'b0; 197 | lock <= 1'b1; 198 | c_en <= 1'b0; 199 | nop_cnt_en <= 1'b0; 200 | $display($time,"\tcntrl: NOW IN POWER UP STATE"); 201 | rst_n <= 1'b0; //cross check this 202 | cke <= 1'b0; 203 | ras_n <= 1'b1; 204 | cas_n <= 1'b1; 205 | we_n <= 1'b1; 206 | odt_out <= 1'b0; 207 | ba <= {BA_BITS{1'bz}}; 208 | addr <= {ADDR_BITS{1'bz}}; 209 | dq_en <= 1'b0; 210 | dqs_en <= 1'b0; 211 | odt_fifo <= 1'b0; 212 | init_phase <= 1'b1; 213 | nlock <= 1'b0; 214 | tlock <= 1'b0; 215 | counter <= 1'b0; 216 | nop_run <= 1'b0; 217 | prev_state <= st; 218 | st_tm <= t_0; 219 | en <= 1'b0; 220 | end 221 | if (cnt < 20000) begin 222 | cnt <= cnt +1;//RESET# must be LOW for at least 200μs #200000000 to begin the initialization process. 223 | end else begin 224 | st <= initialize; 225 | cnt <= 1'b0; 226 | $display($time,"\tcntrl: POWER UP SUCCESSFUL!"); 227 | end 228 | end 229 | initialize: begin 230 | //BEGIN INITIALIZATION 231 | 232 | if((prev_state != power_up)&&(!nop_run))begin// RESET needs to be maintianed for 100ns when doing reset with no power interruption 233 | if (cnt < int'(100000/tck)+1)begin 234 | cnt <= cnt +1; 235 | end else begin 236 | cnt <= 1'b0; 237 | cke <= 1'b0; 238 | st_tm <= t_0; 239 | lock <= 1'b1; 240 | prev_state <= power_up; 241 | end 242 | end else begin 243 | case (st_tm) 244 | t_0:begin 245 | cke <= 1'b0; 246 | odt_out <= 1'b0; 247 | cmd_en <= 1'b0; 248 | rst_n <= 1'b0; 249 | cs_n <= 1'b1; 250 | en <= 1'b1; 251 | if (cnt <= int'(10000/tck)+1) cnt <= cnt +1; // CKE must be LOW 10ns prior to RESET# transitioning HIGH. 252 | else begin 253 | st_tm <= t_1; 254 | cnt <= 1'b0; 255 | end 256 | end 257 | t_1:begin //RESET transitions high 258 | cke <= 1'b0; 259 | rst_n <= 1'b1; 260 | if (cnt <= int'(10000/tck)+1) cnt <= cnt +1; // CKE must be LOW 10ns prior to RESET# transitioning HIGH. 261 | else begin 262 | cnt <= 1'b0; 263 | st_tm <= t_2; 264 | end 265 | end 266 | t_2:begin//trigger nop 267 | next_state <= zq_calibr_long; //so nop goes to zq_calib next 268 | nop_run <= 1; 269 | npt <= int'(TXPR/tck) + 1; 270 | nop_des <= nop; 271 | st <= deno; 272 | done <= 1'b0; 273 | init_phase <= 1'b1; 274 | end 275 | endcase 276 | end 277 | end 278 | init_mrs: begin 279 | 280 | case (st_tm) 281 | t_0:begin 282 | //LOAD MR2 283 | cs_n <= 1'b0; 284 | ras_n <= 1'b0; 285 | cas_n <= 1'b0; 286 | we_n <= 1'b0; 287 | ba <= 3'd2; 288 | addr <= 14'b0001000_101_000;////cas write latency[5:3]001 = 6ck, dynamic odt[9:10] = RZQ/4 289 | mode_reg2 <= 14'b0001000_101_000; //14'b0001000_001_000; 290 | st_tm <= t_1; 291 | next_state <= st; 292 | npt <= TMRD; 293 | nop_des <= nop; 294 | st <= deno; 295 | st_tm <= t_1; 296 | done <= 1'b0; 297 | cnt <= 1'b0; 298 | en <= 1'b1; 299 | end 300 | t_1:begin //MR3 301 | cs_n <= 1'b0; 302 | ras_n <= 1'b0; 303 | cas_n <= 1'b0; 304 | we_n <= 1'b0; 305 | ba <= 3'd3; 306 | addr <= 14'b00000000000000; 307 | next_state <= st; 308 | npt <= TMRD-1; 309 | nop_des <= nop; 310 | st_tm <= t_2; 311 | st <= deno; 312 | done <= 1'b0; 313 | cnt <= 1'b0; 314 | en <= 1'b1; 315 | end 316 | 317 | t_2:begin 318 | //MR1 319 | cs_n <= 1'b0; 320 | ras_n <= 1'b0; 321 | cas_n <= 1'b0; 322 | we_n <= 1'b0; 323 | ba <= 1'd1; 324 | addr <= 14'b0000_0_00_0_0_10_1_1_0; //DLL Enabled[0], RTT[2][6][9] = RZQ/4, output drive strength[1][5] =RZQ/7,AL(Additive Latency)[3:4] = CL -2 325 | mode_reg1 <= 14'b0000_0_00_0_0_10_1_1_0; 326 | next_state <= st; 327 | npt <= TMRD-1; 328 | nop_des <= nop; 329 | st <= deno; 330 | st_tm <= t_3; 331 | done <= 1'b0; 332 | cnt <= 1'b0; 333 | en <= 1'b1; 334 | end 335 | 336 | t_3:begin //MR0 337 | cs_n <= 1'b0; 338 | ras_n <= 1'b0; 339 | cas_n <= 1'b0; 340 | we_n <= 1'b0; 341 | ba <= 1'd0; 342 | //addr = 14'b00100_1_0_100_1_0_00; //burst fixed[0:1],DLL Reset[8], cl[2][4:6] = 8, burst type[3] = interleaved, write_recovery[9:11] = 8 343 | addr <= 14'b00000_1_0_010_1_1_10; //cl = 10 344 | mode_reg0 <= 14'b00000_1_0_010_1_1_10; 345 | en <= 1'b1; 346 | next_state <= st; 347 | npt <= (ix.tzqinit > TDLLK)? ix.tzqinit:TDLLK; 348 | nop_des <= nop; 349 | st <= deno; 350 | st_tm <= t_4; 351 | done <= 1'b0; 352 | cnt <= 1'b0; 353 | end 354 | t_4:begin //turn on odt 355 | 356 | // turn on odt 357 | if (cnt < 10)begin 358 | cke <= 1; 359 | odt_out <= 1'b1; 360 | cnt <= cnt + 1; 361 | cs_n <= 1'b0; 362 | ras_n <= 1'b1; 363 | cas_n <= 1'b1; 364 | we_n <= 1'b1; 365 | end else begin 366 | st <= idle; 367 | en <= 1'b1; 368 | cnt <= 32'b0; 369 | st_tm <= t_1; 370 | done <= 1'b0; 371 | init_phase <= 0; 372 | cmd_en <= 1; 373 | end 374 | end 375 | endcase 376 | end 377 | 378 | 379 | zq_calibr_long: begin 380 | done <= 1'b0; 381 | cmd_en <= 1'b0; 382 | cke <= 1'b1; 383 | cs_n <= 1'b0; 384 | ras_n <= 1'b1; 385 | cas_n <= 1'b1; 386 | we_n <= 1'b0; 387 | ba <= {BA_BITS{1'b0}}; 388 | addr <= 1<<10; 389 | if(init_phase)begin 390 | st <= init_mrs; 391 | // init_phase <= 1'b0; 392 | cnt <= 1'b0; 393 | en <= 1'b1; 394 | st_tm <= t_0; 395 | end else begin 396 | st <= idle; 397 | cnt <= 1'b0; 398 | en <= 1'b1; 399 | end 400 | end 401 | 402 | zq_calibr_short:begin 403 | 404 | cnt <= cnt + 1; 405 | en <= 1'b0; 406 | cmd_en <= 1'b0; 407 | cke <= 1'b1; 408 | cs_n <= 1'b0; 409 | ras_n <= 1'b1; 410 | cas_n <= 1'b1; 411 | we_n <= 1'b0; 412 | ba <= {BA_BITS{1'b0}}; 413 | addr <= 0<<10; 414 | if (cnt<(ix.tzqcs+tck+TIH)) cnt <= cnt + 1; 415 | else begin 416 | st <= idle; 417 | cnt <= 1'b0; 418 | en <= 1'b1; 419 | end 420 | end 421 | idle:begin 422 | 423 | en <=1; 424 | case(cmd) 425 | reset:begin 426 | cmd_en <= 1'b0; 427 | counter <= 1'b0; 428 | st <= initialize; 429 | done <= 1'b0; 430 | 431 | end 432 | act:begin 433 | st <= activating; //bank activate 434 | ba <= ba_in; 435 | addr <= row; 436 | counter <= 1'b0; 437 | done <= 1'b0; 438 | cmd_en <= 0; 439 | end 440 | refr:begin 441 | st<= refrs; //refresh 442 | counter <= 1'b0; 443 | done <= 1'b0; 444 | end 445 | sre:begin 446 | st <= sref; //self refresh entry 447 | counter <= 1'b0; 448 | done <= 1'b0; 449 | st_tm <= t_1; 450 | odt_out <= 1'b0; 451 | end 452 | srx:begin 453 | counter <= 1'b0; 454 | done <= 1'b0; 455 | st <= srfx; //self refresh exit 456 | 457 | end 458 | mrs:begin 459 | st <= mode_reg_set; //mode register set 460 | counter <= 1'b0; 461 | done <= 1'b0; 462 | 463 | end 464 | pde:begin 465 | st <= pwd_e; //precharge power-down entry 466 | counter <= 1'b0; 467 | done <= 1'b0; 468 | odt_out <= 1'b0; 469 | end 470 | //pdx:st = pwd_x; //precharge power-down exit 471 | //mpr:st = mp_reg; //multiplurpose register 472 | zqcs:begin 473 | st <= zq_calibr_short;//zq_calibration short 474 | counter <= 1'b0; 475 | done <= 1'b0; 476 | end 477 | zqcl:begin 478 | st <= zq_calibr_long;//zq_calibration long 479 | counter <= 1'b0; 480 | done <= 1'b0; 481 | end 482 | //nops is passed desired timing parameters from testbench 483 | nops:begin 484 | next_state <= st; 485 | nop_des <= nop; 486 | npt <= ixtb.t; 487 | st <= deno; 488 | cnt <= 1'b0; 489 | counter <= 1'b0; 490 | done <= 1'b0; 491 | cmd_en <= 1; 492 | end 493 | rd,r_ap,wr,w_ap,wr_ap_wrap, 494 | rd_ap_wrap,rd_wrap,wr_wrap: st <= activating; 495 | default:begin 496 | cmd_en <= 1'b0;//assert 497 | counter <= 1'b0; 498 | end 499 | endcase 500 | // end 501 | // end else begin 502 | // $display($time,"\tcntrl: .....Waiting for Command......."); 503 | // end 504 | end 505 | 506 | 507 | 508 | activating:begin 509 | cmd_en <= 1'b1; 510 | // $display($time,"\tcntrl: NOW ACTIVATING"); 511 | cke <= 1'b1; 512 | cs_n <= 1'b0; 513 | ras_n <= 1'b0; 514 | cas_n <= 1'b1; 515 | we_n <= 1'b1; 516 | ba <= ba_in; 517 | active_banks[ba] <= 1'b1; 518 | addr <= row; 519 | prev_bank <= ba; 520 | prev_row <= row; 521 | next_state <= nxt_state; 522 | npt <= ixtb.t;//# of tck to remain in nop 523 | nop_des <= nop; 524 | st <= deno;//deno;//trigger nop 525 | cnt <= 1'b0; 526 | counter <= 1'b0; 527 | done <= 1'b0; 528 | lock <=1'b0; 529 | en <= 1'b1; 530 | end 531 | bank_active:begin 532 | 533 | en <= 1'b1; 534 | cmd_en <= 1'b0; 535 | case(cmd) 536 | reset:begin 537 | st <= initialize; 538 | cmd_en <= 1'b0; 539 | done <= 1'b0; 540 | lock <=1'b0; 541 | counter <= 1'b0; 542 | end 543 | rd:begin 544 | st <= read; 545 | cnt <= 1'b0; 546 | done <= 1'b0; 547 | lock <=1'b0; 548 | counter <= 1'b0; 549 | 550 | end 551 | wr:begin 552 | cnt <= 1'b0; 553 | counter <= 1'b0; 554 | done <= 1'b0; 555 | lock <=1'b0; 556 | st <= write; 557 | end 558 | pre:begin 559 | st <= prec; //precharge 560 | done <= 1'b0; 561 | lock <=1'b0; 562 | counter <= 1'b0; 563 | end 564 | prea:begin 565 | st <= preca; //precharge 566 | done <= 1'b0; 567 | lock <=1'b0; 568 | counter <= 1'b0; 569 | end 570 | pde:begin 571 | st <= pwd_e; //power-down entry 572 | counter <= 1'b0; 573 | done <= 1'b0; 574 | lock <=1'b0; 575 | end 576 | wr_wrap:begin 577 | st <= write_wrap; 578 | done <= 1'b0; 579 | lock <=1'b0; 580 | counter <= 1'b0; 581 | end 582 | rd_wrap:begin 583 | counter <= 1'b0; 584 | lock <=1'b0; 585 | st <= read_wrap; 586 | end 587 | nops: begin 588 | 589 | next_state <= st; 590 | nop_des <= nop; 591 | npt <= ixtb.t; 592 | st <= deno; 593 | cnt <= 1'b0; 594 | counter <= 1'b0; 595 | done <= 1'b0; 596 | cmd_en <= 1'b0; 597 | lock <=1'b0; 598 | end 599 | default:begin 600 | counter <= 1'b0; 601 | done <= 1'b0; 602 | lock <=1'b0; 603 | cmd_en <= 1'b0; 604 | end 605 | endcase 606 | end 607 | 608 | 609 | 610 | //requires 4 inputs from test bench, {bank,col,cmd,length} 611 | 612 | read: begin 613 | cmd_en <= 1'b0; 614 | cke <= 1'b1; 615 | cs_n <= 1'b0; 616 | ras_n <= 1'b1; 617 | cas_n <= 1'b0; 618 | we_n <= 1'b1; 619 | ba <= ba_in; 620 | a[0] = col & 10'h3ff; 621 | a[1] = ((col>>10) & 1'h1)<<11; 622 | a[2] = (col>>11)<<13; 623 | addr <= a[0] | a[1] | a[2] | (ap<<10) | (bc<<12); 624 | 625 | /* MR0[1:0] 626 | 0 0 Fixed BL8 627 | 0 1 4 or 8(on-the-fly via A12) 628 | 1 0 Fixed BC4 (chop) 629 | 1 1 Reserved*/ 630 | casex ({bc, mode_reg0[1:0]}) 631 | 3'bx00, 3'b101:bl<=8; 632 | 3'bx1x, 3'b001:bl<=4; 633 | endcase 634 | st <= read_latency; 635 | end 636 | read_latency: 637 | begin 638 | cnt <= cnt +1; 639 | if(cnt <= bl/2 + 2)begin 640 | odt_fifo[rl-wl + cnt] <= 1'b1; 641 | st <= read_latency; 642 | //$display($time,"\tcntrl: Write Latency Complete!"); 643 | end 644 | else 645 | begin 646 | cnt <= 0; 647 | //st <= dqs_w; 648 | next_state <= bank_active; 649 | npt <= ixtb.t; //wl + int'(bl/2) + TWTR_TCK;//int'(TRCD/tck)+1; 650 | nop_des <= nop; 651 | st <= deno; 652 | cnt <= 1'b0; 653 | cmd_en <= 1; 654 | end 655 | end 656 | 657 | read_wrap: begin 658 | cmd_en <= 1'b0; 659 | cs_n <= 1'b0; 660 | ras_n <= 1'b1; 661 | cas_n <= 1'b0; 662 | we_n <= 1'b1; 663 | ba <= ba_in; 664 | col_start <= col; 665 | st <= r_update; 666 | end 667 | r_update: 668 | begin 669 | col_incr <= col + counter; 670 | addr <= (col_incr & 10'h3ff) |(((col_incr>>10) & 1'h1)<<11)|((col_incr>>11)<<13) | (ap<<10) | (bc<<12); 671 | /* MR0[1:0] 672 | 0 0 Fixed BL8 673 | 0 1 4 or 8(on-the-fly via A12) 674 | 1 0 Fixed BC4 (chop) 675 | 1 1 Reserved*/ 676 | casex ({bc, mode_reg0[1:0]}) 677 | 3'bx00, 3'b101:bl<=8; 678 | 3'bx1x, 3'b001:bl<=4; 679 | endcase 680 | st <= r_latency; 681 | end 682 | r_latency: 683 | begin 684 | cnt <= cnt +1; 685 | if(cnt >= bl/2 + 2)begin //wl = 22 686 | odt_fifo[rl-wl + cnt] <= 1'b1; 687 | st <= read_latency; 688 | //$display($time,"\tcntrl: Write Latency Complete!"); 689 | end 690 | else 691 | begin 692 | cnt <= 0; 693 | st <= wrap_; 694 | 695 | end 696 | end 697 | wrap_: 698 | begin 699 | if (index < rlen) begin 700 | if(col_incr < {COL_BITS{1'b1}})begin 701 | counter <= counter + 1;//bl; 702 | index <= index + 1; 703 | st <= r_update; 704 | end else begin// if (ba < 3'b111) begin //not sure we need to increment bank or just column? 705 | counter <= 0; 706 | index <= index + 1; 707 | st <= r_update; 708 | end 709 | end else begin 710 | counter <= 1'b0; 711 | index <= 1'b0; 712 | cnt <= 1'b0; 713 | st <= read_done; 714 | end 715 | end 716 | read_done: 717 | begin 718 | next_state <= bank_active; 719 | npt <= ixtb.t; 720 | nop_des <= nop; 721 | st <= deno; 722 | cnt <= 1'b0; 723 | cmd_en <= 1; 724 | end 725 | 726 | 727 | 728 | 729 | 730 | 731 | //requires 5 inputs from test bench, {bank,col,dm,dq,wr_cmd} 732 | write: begin 733 | cmd_en <= 1'b0; 734 | cke <= 1'b1; 735 | cs_n <= 1'b0; 736 | ras_n <= 1'b1; 737 | cas_n <= 1'b0; 738 | we_n <= 1'b0; 739 | ba <= ba_in; 740 | a[0] = col & 10'h3ff; 741 | a[1] = ((col>>10) & 1'h1)<<11; 742 | a[2] = (col>>11)<<13; 743 | addr <= a[0] | a[1] | a[2] | (ap<<10) | (bc<<12); 744 | 745 | /* MR0[1:0] 746 | 0 0 Fixed BL8 747 | 0 1 4 or 8(on-the-fly via A12) 748 | 1 0 Fixed BC4 (chop) 749 | 1 1 Reserved*/ 750 | casex ({bc, mode_reg0[1:0]}) 751 | 3'bx00, 3'b101:bl<=8; 752 | 3'bx1x, 3'b001:bl<=4; 753 | endcase 754 | st <= write_latency; 755 | end 756 | write_latency: 757 | begin 758 | cnt <= cnt +1; 759 | // rw_cnt_en <= 1; 760 | // if(rw_cnt < wl*tck - half_tck)begin//wl = 22 761 | if(cnt != 1)begin//wl = 22 762 | st <= write_latency; 763 | end 764 | else 765 | begin 766 | rw_cnt_en <= 0; 767 | cnt <= 0; 768 | st <= dqs_w; 769 | $display($time,"\tcntrl: Write Latency Complete!"); 770 | end 771 | end 772 | dqs_w: 773 | begin 774 | dqs_en <= 1'b1; 775 | rw_cnt_en <= 0; 776 | dqs_out <= {DQS_BITS{1'b1}}; 777 | st <= burst_w; 778 | counter <=0; 779 | lock <= 0; 780 | end 781 | burst_w: 782 | begin 783 | //cnt <= cnt +1; 784 | if(rw_cnt < int'(counter*tck/2)) 785 | begin 786 | rw_cnt_en <= 1; //uses a 1ps clock to count 787 | if (counter != bl) 788 | lock <= 0; 789 | st <= burst_w; 790 | end 791 | else 792 | begin 793 | cnt <= 0; 794 | // rw_cnt_en <= 0; 795 | lock <= 1; 796 | end 797 | if (lock ==1 ) 798 | begin 799 | //counter++; 800 | lock <= 0; 801 | dqs_en <= 1'b1; 802 | if (counter%2==0) 803 | dqs_out <= {DQS_BITS{1'b0}}; 804 | else 805 | dqs_out <= {DQS_BITS{1'b1}}; 806 | st <= dm_set_delay; 807 | rw_cnt_en <= 0; 808 | end 809 | //if (counter == bl) 810 | //begin 811 | // counter <=0; 812 | // cnt <=0; 813 | // st <= dm_set_delay; 814 | //end 815 | end 816 | dm_set_delay: 817 | begin 818 | rw_cnt_en <= 1; 819 | if(rw_cnt < int'(tck/4)+1) 820 | st <= dm_set_delay; 821 | else 822 | begin 823 | cnt <= 0; 824 | rw_cnt_en <= 0; 825 | st <= dm_set; 826 | end 827 | end 828 | dm_set: 829 | begin 830 | dq_en <= 1'b1; 831 | dm_out <= dm_in >>counter*DM_BITS; 832 | dq_out <= dq_in >>counter*DQ_BITS; 833 | counter <= counter + 1; 834 | if (counter == bl) 835 | begin 836 | counter <= 0; 837 | cnt <= 0; 838 | st <= dq_en_off; 839 | end 840 | else 841 | st <= burst_w; 842 | end 843 | dq_en_off: 844 | begin 845 | dq_en <= 1'b0; 846 | //cnt <= cnt + 1; 847 | rw_cnt_en <= 1; 848 | if(rw_cnt < int'(tck/4)+1) //1/4(tck) 849 | st <= dq_en_off; 850 | else 851 | begin 852 | cnt <= 0; 853 | rw_cnt_en <= 0; 854 | st <= dqs_en_off; 855 | end 856 | end 857 | dqs_en_off:begin 858 | dqs_en <= 1'b0; 859 | next_state <= bank_active; 860 | npt <= ixtb.t; //wl + int'(bl/2) + TWTR_TCK;//int'(TRCD/tck)+1; 861 | nop_des <= nop; 862 | st <= deno; 863 | cnt <= 1'b0; 864 | counter <= 1'b0; 865 | done <= 1'b0; 866 | lock <=1'b0; 867 | en <= 1'b1; 868 | cmd_en <= 1; 869 | end 870 | 871 | //requires 5 inputs from test bench, {bank,col,dm,dq,wr_cmd,rlen(amount of wrapping)} 872 | 873 | 874 | write_wrap: begin 875 | cmd_en <= 1'b0; 876 | cke <= 1'b1; 877 | cs_n <= 1'b0; 878 | ras_n <= 1'b1; 879 | cas_n <= 1'b0; 880 | we_n <= 1'b0; 881 | ba <= ba_in; 882 | /* MR0[1:0] 883 | 0 0 Fixed BL8 884 | 0 1 4 or 8(on-the-fly via A12) 885 | 1 0 Fixed BC4 (chop) 886 | 1 1 Reserved*/ 887 | casex ({bc, mode_reg0[1:0]}) 888 | 3'bx00, 3'b101:bl<=8; 889 | 3'bx1x, 3'b001:bl<=4; 890 | endcase 891 | st <= w_update; 892 | end 893 | 894 | w_update: 895 | begin 896 | col_incr <= col + wcnt; 897 | addr <= (col_incr & 10'h3ff) |(((col_incr>>10) & 1'h1)<<11)|((col_incr>>11)<<13) | (ap<<10) | (bc<<12); 898 | /* MR0[1:0] 899 | 0 0 Fixed BL8 900 | 0 1 4 or 8(on-the-fly via A12) 901 | 1 0 Fixed BC4 (chop) 902 | 1 1 Reserved*/ 903 | casex ({bc, mode_reg0[1:0]}) 904 | 3'bx00, 3'b101:bl<=8; 905 | 3'bx1x, 3'b001:bl<=4; 906 | endcase 907 | st <= w_latency; 908 | end 909 | 910 | w_latency: 911 | begin 912 | cnt <= cnt +1; 913 | if(cnt != wl)begin//wl = 22 914 | st <= w_latency; 915 | $display($time,"\tcntrl: Write Latency Complete!"); 916 | end 917 | else 918 | begin 919 | cnt <= 0; 920 | st <= dqs_ww; 921 | $display($time,"\tcntrl: Write Latency Complete!"); 922 | end 923 | end 924 | dqs_ww: 925 | begin 926 | dqs_en <= 1'b1; 927 | dqs_out <= {DQS_BITS{1'b1}}; 928 | st <= burst_ww; 929 | counter <=0; 930 | lock <= 0; 931 | end 932 | burst_ww: 933 | begin 934 | //cnt <= cnt +1; 935 | if(rw_cnt < int'(counter*tck/2)) 936 | begin 937 | rw_cnt_en <= 1; //uses a 1ps clock to count 938 | if (counter != bl) 939 | lock <= 0; 940 | st <= burst_ww; 941 | end 942 | else 943 | begin 944 | cnt <= 0; 945 | // rw_cnt_en <= 0; 946 | lock <= 1; 947 | end 948 | if (lock ==1 ) 949 | begin 950 | //counter++; 951 | lock <= 0; 952 | dqs_en <= 1'b1; 953 | if (counter%2==0) 954 | dqs_out <= {DQS_BITS{1'b0}}; 955 | else 956 | dqs_out <= {DQS_BITS{1'b1}}; 957 | st <= dm_set_delayw; 958 | rw_cnt_en <= 0; 959 | end 960 | //if (counter == bl) 961 | //begin 962 | // counter <=0; 963 | // cnt <=0; 964 | // st <= dm_set_delay; 965 | //end 966 | end 967 | dm_set_delayw: 968 | begin 969 | //if(rw_cnt < int'(tck/4)+1) 970 | if(cnt != 1) //quarter tck 971 | begin 972 | cnt <= cnt + 1; 973 | st <= dm_set_delayw; 974 | end 975 | else 976 | begin 977 | cnt <= 0; 978 | st <= dm_setw; 979 | end 980 | end 981 | dm_setw: 982 | begin 983 | dq_en <= 1'b1; 984 | dm_out <= dm_in >>counter*DM_BITS; 985 | dq_out <= dq_in >>counter*DQ_BITS; 986 | counter <= counter + 1; 987 | if (counter == bl) 988 | begin 989 | counter <= 0; 990 | cnt <= 0; 991 | st <= wrap_w; 992 | end 993 | else 994 | st <= burst_ww; 995 | end 996 | wrap_w: 997 | begin 998 | if (index < rlen) begin 999 | if(col_incr < {COL_BITS{1'b1}})begin 1000 | wcnt <= wcnt + 1;//bl; 1001 | index <= index + 1; 1002 | st <= r_update; 1003 | end else begin// 1004 | wcnt <= 0; 1005 | index <= index + 1; 1006 | st <= w_update; 1007 | end 1008 | end else begin 1009 | lock <= 1'b1; 1010 | counter <= 1'b0; 1011 | index <= 1'b0; 1012 | bcnt <= 1'b0; 1013 | cnt <= 1'b0; 1014 | st <= dq_en_offw; 1015 | end 1016 | end 1017 | dq_en_offw: 1018 | begin 1019 | dq_en <= 1'b0; 1020 | cnt <= cnt + 1; 1021 | if(cnt != 1) //quarter tck round up 1022 | st <= dq_en_offw; 1023 | else 1024 | begin 1025 | cnt <= 0; 1026 | st <= dqs_en_offw; 1027 | end 1028 | end 1029 | dqs_en_offw:begin 1030 | dqs_en <= 1'b0; 1031 | next_state <= bank_active; 1032 | npt <= ixtb.t; //wl + int'(bl/2) + TWTR_TCK;//int'(TRCD/tck)+1; 1033 | nop_des <= nop; 1034 | st <= deno; 1035 | cnt <= 1'b0; 1036 | // cmd_en <= 1'b0; 1037 | counter <= 1'b0; 1038 | done <= 1'b0; 1039 | lock <=1'b0; 1040 | en <= 1'b1; 1041 | cmd_en <= 1; 1042 | end 1043 | 1044 | 1045 | 1046 | 1047 | 1048 | //requires bank input from tb 1049 | prec, 1050 | preca: 1051 | begin// $display($time,"\tcntrl: IN PRECHARGE STATE"); 1052 | cmd_en <= 1'b1; 1053 | en <= 1'b0; 1054 | cke <= 1'b1; 1055 | cs_n <= 1'b0; 1056 | ras_n <= 1'b0; 1057 | cas_n <= 1'b1; 1058 | we_n <= 1'b0; 1059 | ba <= ba_in; 1060 | next_state <= idle; 1061 | npt <= int'(TRP/tck) + 1; 1062 | nop_des <= nop; 1063 | st <= deno; 1064 | end 1065 | 1066 | 1067 | 1068 | 1069 | //requires no input from tb 1070 | refrs: 1071 | begin 1072 | cmd_en <= 1; 1073 | // $display($time,"\tcntrl: NOW IN REFRESH STATE"); 1074 | cke <= 1'b1; 1075 | cs_n <= 1'b0; 1076 | ras_n <= 1'b0; 1077 | cas_n <= 1'b0; 1078 | we_n <= 1'b1; 1079 | next_state <= idle; 1080 | npt <= int'(TRFC_MIN/tck)+1; 1081 | nop_des <= nop; 1082 | st <= deno; 1083 | end 1084 | 1085 | 1086 | sref: 1087 | begin 1088 | cmd_en <= 1'b1; 1089 | // $display($time,"\tcntrl: NOW IN SELF REFRESH STATE"); 1090 | case(st_tm) 1091 | t_1: 1092 | begin 1093 | next_state <= sref; 1094 | npt <= TXP_TCK; 1095 | nop_des <= nop; 1096 | st <= deno; 1097 | st_tm <= t_0; 1098 | end 1099 | t_0: 1100 | begin 1101 | cke <= 1'b0; 1102 | cs_n <= 1'b0; 1103 | ras_n <= 1'b0; 1104 | cas_n <= 1'b0; 1105 | we_n <= 1'b1; 1106 | if(cnt < 1) 1107 | cnt <= cnt + 1; 1108 | else 1109 | begin 1110 | cnt <= 0; 1111 | cs_n <= 1'b1; 1112 | ras_n <= 1'b1; 1113 | cas_n <= 1'b1; 1114 | we_n <= 1'b1; 1115 | st_tm <= t_2; 1116 | end 1117 | end 1118 | t_2: 1119 | begin 1120 | if(cnt < ixtb.t) 1121 | cnt <= cnt + 1; 1122 | else 1123 | begin 1124 | st <= idle; //srfx; 1125 | cnt <= 0; 1126 | // next_state <= idle; 1127 | // nop_des <= nop; //...NOP or DES must be issued for tXS time. 1128 | // st <= deno; 1129 | // npt <= int'(TRFC_MIN/tck)+1; 1130 | end 1131 | end 1132 | endcase 1133 | end 1134 | srfx: begin 1135 | cmd_en <= 0; 1136 | next_state <= idle; 1137 | nop_des <= nop; //...NOP or DES must be issued for tXS time. 1138 | st <= deno; 1139 | npt <= TXS_TCK; //read to precharge command delay 1140 | cnt <= 0; 1141 | done <= 1'b0; 1142 | end 1143 | 1144 | 1145 | /*Input from test bench is bank and address*/ 1146 | mode_reg_set: begin 1147 | cmd_en <= 0; 1148 | cke <= 1'b1; 1149 | cs_n <= 1'b0; 1150 | ras_n <= 1'b0; 1151 | cas_n <= 1'b0; 1152 | we_n <= 1'b0; 1153 | case (ba_in) 1154 | 0: mode_reg0 <= addr_in; 1155 | 1: mode_reg1 <= addr_in; 1156 | 2: mode_reg2 <= addr_in; 1157 | endcase 1158 | ba <= ba_in; 1159 | addr <= addr_in; 1160 | next_state <= idle; 1161 | npt <= TMOD_TCK + ixtb.t; 1162 | nop_des <= nop; 1163 | st <= deno; 1164 | done <= 1'b0; 1165 | $display($time,"\tcntrl: MODE REG SUCCESSFULLY CONFIGURED"); 1166 | end 1167 | //receives parameter for time in power-down entry 1168 | pwd_e: begin 1169 | $display($time,"\tcntrl: NOW IN POWER DOWN ENTRY STATE"); 1170 | cke <= 1'b0; 1171 | cs_n <= 1'b0; 1172 | ras_n <= 1'b1; 1173 | cas_n <= 1'b1; 1174 | we_n <= 1'b1; 1175 | cmd_en <= 1; 1176 | st <= nxt_state; 1177 | end 1178 | pwd_x: begin 1179 | cmd_en <= 1; 1180 | next_state <= bank_active; 1181 | nop_des <= nop; 1182 | st <= deno; 1183 | npt <= TXP_TCK; 1184 | cnt <= 0; 1185 | done <= 1'b0; 1186 | st <= bank_active; 1187 | end 1188 | 1189 | deno: begin 1190 | case (nop_des) 1191 | /*The DESELT (DES) command (CS# HIGH) prevents new commands from being executed 1192 | by the DRAM. Operations already in progress are not affected.*/ 1193 | des: begin 1194 | cke <= 1'b1; 1195 | cs_n <= 1'b1; 1196 | ras_n <= 1'bx; 1197 | cas_n <= 1'bx; 1198 | we_n <= 1'bx; 1199 | if(nop_cnt < npt)begin 1200 | nop_cnt_en <= 1'b1; 1201 | done <= 1'b0; 1202 | end else begin 1203 | done <= 1'b1; 1204 | nop_cnt_en <= 1'b0; 1205 | $display($time,"\tcntrl: des "); 1206 | st <= next_state; 1207 | cmd_en <= 0; 1208 | end 1209 | end 1210 | 1211 | /*The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from 1212 | being registered during idle or wait states. Operations already in progress are not affected.*/ 1213 | nop: begin 1214 | cke <= 1'b1; 1215 | cs_n <= 1'b0; 1216 | ras_n <= 1'b1; 1217 | cas_n <= 1'b1; 1218 | we_n <= 1'b1; 1219 | if(nop_cnt < npt)begin 1220 | nop_cnt_en <= 1'b1; 1221 | done <= 1'b0; 1222 | end else begin 1223 | done <= 1'b1; 1224 | nop_cnt_en <= 1'b0; 1225 | $display($time,"\tcntrl: nop"); 1226 | st <= next_state; 1227 | nlock <= 1'b0; 1228 | cmd_en <= 1'b0; 1229 | end 1230 | end 1231 | zero: done <= 1'b0; 1232 | default: st <= next_state; 1233 | endcase 1234 | end 1235 | default: begin 1236 | rst_n <= 1'b0; //rst_n keeps all ddr inputs at z-impedence (disables) 1237 | cnt <= 1'b0; 1238 | end 1239 | endcase 1240 | end 1241 | end 1242 | end 1243 | endmodule 1244 | 1245 | 1246 | -------------------------------------------------------------------------------- /defs.svh: -------------------------------------------------------------------------------- 1 | //a given parameter for ddr3.v 2 | 3 | // `include "sg187.v" 4 | `include "sg093.v" 5 | //`include "intf.svh" 6 | //controller states /configuration params 7 | //controller states 8 | 9 | //parameter des = 1, //deselect 10 | //nop = 2; //no operation 11 | 12 | enum integer{zero,nop =1,des}nop_des; 13 | 14 | parameter ap_on = 1; 15 | parameter ap_off = 0; 16 | parameter bc_on = 1; 17 | parameter bc_off = 0; 18 | parameter on = 1; 19 | parameter off = 0; 20 | 21 | //timing params 22 | parameter tck = TCK_MIN; //should be real and add one is real > integer 23 | parameter tXPR = int'(TXPR/tck) + 1; 24 | parameter half_tck = int'(tck/2);//tck >>1; 25 | parameter quarter_tck = int'(tck/4)+1;//tck >>2; 26 | //reg [15:0] wl_tck = wl*tck; 27 | 28 | parameter pwr_up=0,desel=1,nops=2,reset=3,zqcs=4,zqcl=5,act=6,rd=7,wr=8,r_ap=9,w_ap=10, 29 | rd_wrap=11,wr_wrap=12,rd_ap_wrap=13,wr_ap_wrap=14,pre=15,prea=16,refr=17,sre=18,srx=19,mrs=20,pde=21,pdx=22,mpr=23; 30 | 31 | parameter wr_mrs = 0,wr_bc4 = 0,wr_bl8 = 1; 32 | parameter rd_mrs = 0,rd_bc4 = 0,rd_bl8 = 1; 33 | 34 | //typedef enum integer {pwr_up,desel,nops,reset,zqcs,zqcl,act,rd,wr,r_ap,w_ap,rd_wrap,wr_wrap,rd_ap_wrap,wr_ap_wrap,pre,prea,refr,sre,srx,mrs,pde,pdx,mpr}ddr3_cmd; 35 | 36 | typedef enum integer {t_1,t_2,t_3,t_4,t_5,t_6,t_7,t_8,t_0}time_st; 37 | //typedef enum integer {wr_mrs,wr_bc4,wr_bl8}write_cmd; 38 | //typedef enum integer {rd_mrs,rd_bc4,rd_bl8}read_cmd; 39 | 40 | 41 | // mode registers 42 | reg [ADDR_BITS-1:0] mode_reg0; //Mode Register 43 | reg [ADDR_BITS-1:0] mode_reg1; //Extended Mode Register 44 | reg [ADDR_BITS-1:0] mode_reg2; //Extended Mode Register 2 45 | wire [3:0] cl = {mode_reg0[2], mode_reg0[6:4]} + 4; //CAS Latency 46 | wire bo = mode_reg0[3]; //Burst Order 47 | reg [3:0] bl; //Burst Length 48 | wire [3:0] cwl = mode_reg2[5:3] + 5; //CAS Write Latency 49 | wire [3:0] al = (mode_reg1[4:3] == 2'b00) ? 4'h0 : cl - mode_reg1[4:3]; //Additive Latency 50 | wire [4:0] rl = cl + al; //Read Latency 51 | wire [4:0] wl = cwl + al; //Write Latency 52 | 53 | // dq receive 54 | reg [DM_BITS-1:0] dm_fifo [4*CL_MAX+BL_MAX+2:0]; 55 | reg [DQ_BITS-1:0] dq_fifo [4*CL_MAX+BL_MAX+2:0]; 56 | wire [8*DQ_BITS-1:0] dq_in; //from tb 57 | wire [8*DM_BITS-1:0] dm_in; //from tb 58 | wire [DQ_BITS-1:0] q0, q1, q2, q3; 59 | reg ptr_rst_n; 60 | reg [1:0] burst_cntr; 61 | // odt 62 | reg odt_out; 63 | reg [(AL_MAX+CL_MAX):0] odt_fifo; 64 | 65 | 66 | 67 | // assign cl = {mode_reg0[2], mode_reg0[6:4]} + 4; //CAS Latency = 8 68 | // assign bo = mode_reg0[3]; //Burst Order = 1 (interleved) 69 | // assign cwl = mode_reg2[5:3] + 5; //CAS Write Latency = 6 70 | // assign al = (mode_reg1[4:3] == 2'b00) ? 4'h0 : cl - mode_reg1[4:3]; //Additive Latency = 7 //changed case equality from triple 71 | // assign rl = cl + al; //Read Latency =15 72 | // assign wl = cwl + al; //Write Latency = 13 //22 73 | // assign wl_tck = wl*tck; //24375 74 | 75 | 76 | -------------------------------------------------------------------------------- /intf.svh: -------------------------------------------------------------------------------- 1 | //an interface to connect ddr3_controller.sv and ddr3.v 2 | 3 | interface intf; 4 | //`include "sg187.v" 5 | //`include "1024Mb_ddr3_parameters.vh" 6 | `include "sg093.v" 7 | //`include "defs.svh" 8 | logic rst_n; 9 | logic ck; 10 | logic ck_n; 11 | logic cke; 12 | logic cs_n; 13 | logic ras_n; 14 | logic cas_n; 15 | logic we_n; 16 | logic [BA_BITS-1:0] ba; 17 | logic [ADDR_BITS-1:0] addr; 18 | logic odt; 19 | logic [DM_BITS-1:0] dm; 20 | logic [DQ_BITS-1:0] dq; //data from controller to memory 21 | logic [DQS_BITS-1:0] dqs; //data control signal: dq will be written or read at dqs edge 22 | logic [DQS_BITS-1:0] dqs_n; 23 | logic [DQ_BITS-1:0] dq0; //data from memory to controller 24 | logic [DQS_BITS-1:0] dqs0; //dq0 control signal 25 | logic [DQS_BITS-1:0] dqs0_n; 26 | logic [DQS_BITS-1:0] tdqs_n; 27 | integer tzqcs; 28 | integer tzqinit; 29 | integer tzqoper; 30 | 31 | 32 | modport cntrl( 33 | output rst_n, 34 | input ck, 35 | output ck_n, 36 | output cke, 37 | output cs_n, 38 | output ras_n, 39 | output cas_n, 40 | output we_n, 41 | output ba, 42 | output addr, 43 | output odt, 44 | output dm, 45 | output dq, 46 | output dqs, 47 | output dqs_n, 48 | input dq0, 49 | input dqs0, 50 | input dqs0_n, 51 | input tdqs_n, 52 | input tzqcs, 53 | input tzqinit, 54 | input tzqoper 55 | ); 56 | 57 | modport mem( 58 | input rst_n, 59 | input ck, 60 | input ck_n, 61 | input cke, 62 | input cs_n, 63 | input ras_n, 64 | input cas_n, 65 | input we_n, 66 | input dm, 67 | input ba, 68 | input addr, 69 | input odt, 70 | input dq, 71 | input dqs, 72 | input dqs_n, 73 | output dq0, 74 | output dqs0, 75 | output dqs0_n, 76 | output tdqs_n, 77 | output tzqcs, 78 | output tzqinit, 79 | output tzqoper 80 | );// 81 | 82 | 83 | endinterface 84 | 85 | 86 | interface iftb; 87 | //`include "defs.svh" 88 | // `include "sg187.v" 89 | // `include "st_defs.svh" 90 | // `include "1024Mb_ddr3_parameters.vh" 91 | `include "sg093.v" 92 | /*THIS IS THE INTERFACE BETWEEN TESTBENCH AND CONTROLLER*/ 93 | reg [BA_BITS-1:0] ba; 94 | reg [COL_BITS-1:0] col; 95 | reg [ROW_BITS-1:0] row; 96 | reg [ADDR_BITS-1:0] addr; 97 | logic [4:0] prev_cmd; 98 | logic [4:0] cmd; 99 | logic [1:0] wr_cmd; // 100 | logic [1:0] rd_cmd; 101 | parameter ap_on = 1'b1; //enable autoprecharge 102 | parameter ap_off = 1'b0; //disable auto precharge 103 | parameter bc_on = 1'b1; 104 | parameter bc_off = 1'b0; 105 | reg [31:0] t,rlen; //t = desired time for nop //rlen desired number of incremental busrts for wrapping 106 | logic cmd_en; 107 | reg [8*DM_BITS-1:0] dm; //data mask must be kept low except dq data is to be ignored by mem 108 | reg [8*DQ_BITS-1:0] dq; //data from testbench to controller which will be sent to 109 | logic ap; //mem by controller. 110 | logic clk,rst; 111 | int next_state; 112 | //enum integer {wr_mrs,wr_bc4,wr_bl8}write_cmd; //choose between burst length 8(fixed mode),burst lenght 4(chop mode)or set in mr0 113 | //enum integer {rd_mrs,rd_bc4,rd_bl8}read_cmd;//choose between burst lenght 8(fixed mode),burst lenght 4(chop mode)or set in mr0 114 | //enum integer {pwr_up,desel,nops,reset,zqcs,zqcl,act,rd,wr,r_ap,w_ap,rd_wrap,rd_ap_wrap,pre,prea,refr,sre,srx,mrs,pde,pdx,mpr}ddr3_cmd; 115 | //ddr3_cmd prev_cmd; 116 | //ddr3_cmd cmd; 117 | //write_cmd wr_cmd; 118 | //read_cmd rd_cmd; 119 | // modport tb(input ba,input col, input dq, input dm,input row,input addr,input t,input rlen,input cmd,input prev_cmd,input rd_cmd,input wr_cmd,output cmd_en); 120 | modport cntrl(input ba,input col, input clk, input rst,input dq, input dm,input row,input addr, 121 | input t,input rlen,input cmd,input prev_cmd,input rd_cmd,input wr_cmd,input ap,output cmd_en,input next_state); 122 | endinterface 123 | 124 | interface AHBIF; 125 | logic mHBUSREQ,mHGRANT,HREADY,mHREADY; 126 | logic [1:0] HRESP,mHRESP; 127 | logic HRESET; 128 | logic HCLK; 129 | logic [31:0] HRDATA,mHRDATA; 130 | logic [31:0] HWDATA,mHWDATA; 131 | logic HLOCK; // Not used 132 | logic [1:0] HTRANS,mHTRANS; 133 | logic [31:0] HADDR,mHADDR; 134 | logic HWRITE,mHWRITE; 135 | logic [2:0] HSIZE,mHSIZE; 136 | logic [2:0] HBURST,mHBURST; 137 | logic [3:0] HPROT; // Not used 138 | logic HSEL; // slave select 139 | logic [3:0] HMASTER; // Not used 140 | logic HMASTLOCK; // not used 141 | 142 | 143 | 144 | clocking cb @(posedge(HCLK)); 145 | 146 | endclocking : cb 147 | 148 | modport AHBM( input mHGRANT, output mHBUSREQ, 149 | input mHREADY,input mHRESP, 150 | input mHRDATA,output mHTRANS, output mHADDR, 151 | output mHWRITE, output mHSIZE, output mHBURST); 152 | 153 | modport AHBS( input HSEL, input HADDR, 154 | input HWRITE, input HTRANS, 155 | input HSIZE, input HBURST, input HWDATA, 156 | output HREADY, 157 | output HRESP, output HRDATA); 158 | 159 | 160 | modport AHBCLKS( input HCLK, input HRESET); 161 | 162 | 163 | endinterface : AHBIF 164 | 165 | -------------------------------------------------------------------------------- /sg093.v: -------------------------------------------------------------------------------- 1 | parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time 2 | parameter TJIT_PER = 50; // tJIT(per) ps Period JItter 3 | parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter 4 | parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) 5 | parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) 6 | parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) 7 | parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) 8 | parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) 9 | parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) 10 | parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) 11 | parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) 12 | parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) 13 | parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) 14 | parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) 15 | parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS 16 | parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS 17 | parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access 18 | parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition 19 | parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) 20 | parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) 21 | parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# 22 | parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width 23 | parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width 24 | parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width 25 | parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width 26 | parameter TIS = 35; // tIS ps Input Setup Time 27 | parameter TIH = 75; // tIH ps Input Hold Time 28 | parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time 29 | parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time 30 | parameter TRCD = 13090; // tRCD ps Active to Read/Write command time 31 | parameter TRP = 13090; // tRP ps Precharge command period 32 | parameter TXP = 6000; // tXP ps Exit power down to a valid command 33 | parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width 34 | parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference 35 | parameter TWLS = 122; // tWLS ps Setup time for tDQS flop 36 | parameter TWLH = 122; // tWLH ps Hold time of tDQS flop 37 | parameter TWLO = 7500; // tWLO ps Write levelization output delay 38 | parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data 39 | parameter CL_TIME = 13090; // CL ps Minimum CAS Latency 40 | 41 | parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed 42 | 43 | parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time 44 | parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window 45 | 46 | // Timing Parameters 47 | 48 | // Mode Register 49 | parameter CL_MIN = 5; // CL tCK Minimum CAS Latency 50 | parameter CL_MAX = 14; // CL tCK Maximum CAS Latency 51 | parameter AL_MIN = 0; // AL tCK Minimum Additive Latency 52 | parameter AL_MAX = 2; // AL tCK Maximum Additive Latency 53 | parameter WR_MIN = 5; // WR tCK Minimum Write Recovery 54 | parameter WR_MAX = 16; // WR tCK Maximum Write Recovery 55 | parameter BL_MIN = 4; // BL tCK Minimum Burst Length 56 | parameter BL_MAX = 8; // BL tCK Minimum Burst Length 57 | parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency 58 | parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency 59 | 60 | // Clock 61 | parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time 62 | parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width 63 | parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width 64 | parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width 65 | parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width 66 | parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width 67 | parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width 68 | parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width 69 | parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data 70 | 71 | // Data OUT 72 | parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# 73 | // Data Strobe OUT 74 | parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble 75 | parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble 76 | // Data Strobe IN 77 | parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width 78 | parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width 79 | parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble 80 | parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble 81 | // Command and Address 82 | integer TZQCS; // tZQCS tCK ZQ Cal (Short) time 83 | integer TZQINIT; // tZQinit tCK ZQ Cal (Long) time 84 | integer TZQOPER; // tZQoper tCK ZQ Cal (Long) time 85 | parameter TCCD = 4; // tCCD tCK Cas to Cas command delay 86 | parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group 87 | parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time 88 | parameter TWR = 15000; // tWR ps Write recovery time 89 | parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time 90 | parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time 91 | parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time 92 | parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time 93 | parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group 94 | parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group 95 | parameter TRTP = 7500; // tRTP ps Read to Precharge command delay 96 | parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay 97 | parameter TWTR = 7500; // tWTR ps Write to Read command delay 98 | parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group 99 | parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay 100 | parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group 101 | parameter TDLLK = 512; // tDLLK tCK DLL locking time 102 | // Refresh - 2Gb 103 | parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value 104 | parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value 105 | // Power Down 106 | parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command 107 | parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) 108 | parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) 109 | parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry 110 | parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry 111 | parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry 112 | parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay 113 | parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing 114 | parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command 115 | parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command 116 | // Self Refresh 117 | parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command 118 | parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command 119 | parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command 120 | parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. 121 | parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) 122 | parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) 123 | parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) 124 | parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) 125 | parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing 126 | // ODT 127 | parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference 128 | parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) 129 | parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) 130 | parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) 131 | parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) 132 | parameter TADC = 0.7; // tADC tCK RTT dynamic change skew 133 | // Write Levelization 134 | parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed 135 | parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed 136 | parameter TWLOE = 2000; // tWLOE ps Write levelization output error 137 | 138 | // Size Parameters based on Part Width 139 | parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used 140 | parameter ADDR_BITS = 15; // MAX Address Bits 141 | parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used 142 | parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used 143 | parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** 144 | parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used 145 | 146 | 147 | // Size Parameters 148 | parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used 149 | parameter MEM_BITS = 10; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. 150 | parameter AP = 10; // the address bit that controls auto-precharge and precharge-all 151 | parameter BC = 12; // the address bit that controls burst chop 152 | parameter BL_BITS = 3; // the number of bits required to count to BL_MAX 153 | parameter BO_BITS = 2; // the number of Burst Order Bits 154 | 155 | `ifdef QUAD_RANK 156 | parameter CS_BITS = 4; // Number of Chip Select Bits 157 | parameter RANKS = 4; // Number of Chip Selects 158 | `elsif DUAL_RANK 159 | parameter CS_BITS = 2; // Number of Chip Select Bits 160 | parameter RANKS = 2; // Number of Chip Selects 161 | `else 162 | parameter CS_BITS = 1; // Number of Chip Select Bits 163 | parameter RANKS = 1; // Number of Chip Selects 164 | `endif 165 | 166 | // Simulation parameters 167 | parameter RZQ = 240; // termination resistance 168 | parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout 169 | parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors 170 | parameter DEBUG = 1; // Turn on Debug messages 171 | parameter BUS_DELAY = 0; // delay in nanoseconds 172 | parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads 173 | parameter RANDOM_SEED = 31913; //seed value for random generator. 174 | 175 | parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe 176 | parameter RDQSEN_PST = 1; // DQS driving time after last read strobe 177 | parameter RDQS_PRE = 2; // DQS low time prior to first read strobe 178 | parameter RDQS_PST = 1; // DQS low time after last read strobe 179 | parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data 180 | parameter RDQEN_PST = 0; // DQ/DM driving time after last read data 181 | parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe 182 | parameter WDQS_PST = 1; // DQS half clock periods after last write strobe 183 | -------------------------------------------------------------------------------- /st_defs.svh: -------------------------------------------------------------------------------- 1 | //a parameter for ddr3_controller.sv, controller states 2 | 3 | //typedef enum logic [5:0]{ 4 | parameter power_up = 0, //power up, begin initialization 5 | initialize = 1, 6 | init_mrs = 2, //initialization MRS load mode 7 | zq_calibr_short = 3, //zq_calibration short 8 | zq_calibr_long =30,//zq_calibration long 9 | idle = 4, 10 | activating = 5, //activating 11 | bank_active = 6, 12 | read = 7, //rd 13 | read_latency = 31, 14 | r_update = 32, 15 | r_latency = 35, 16 | read_done = 33, 17 | wrap_ = 34, 18 | //read_ap, //read ap 19 | read_wrap = 8, 20 | after_activate = 9, 21 | nop_exit_write = 10, 22 | //read_ap_wrap, 23 | write = 11, //wr 24 | //write_ap,//write auto precharge 25 | //write_ap_wrap, 26 | write_wrap = 12, 27 | //wr_burst, 28 | dqs_en_off = 13, 29 | dq_en_off = 14, 30 | dm_set = 15, 31 | dm_set_delay = 16, 32 | burst_w = 17, 33 | dqs_w = 18, 34 | write_latency = 19, 35 | dqs_en_offw = 51, 36 | dq_en_offw = 52, 37 | wrap_w = 53, 38 | dm_setw= 54, 39 | dm_set_delayw = 56, 40 | burst_ww = 57, 41 | dqs_ww = 58, 42 | w_latency = 59, 43 | w_update = 60, 44 | prec = 20,//precharge 45 | preca = 21,//precharge all 46 | refrs = 22, //refresh 47 | sref = 23, //self refresh entry 48 | srfx = 24, //self refresh exit 49 | mode_reg_set = 25, //mode register set 50 | pwd_e = 26, //power-down entry 51 | pwd_x = 27, //power-down exit 52 | mp_reg = 28, //multiplurpose register 53 | deno = 29; 54 | //}state; 55 | -------------------------------------------------------------------------------- /top.sv: -------------------------------------------------------------------------------- 1 | //top module 2 | 3 | // `include "1024Mb_ddr3_parameters.svh" 4 | 5 | // `include "sg187.v" 6 | /*`include "defs.svh" 7 | `ifdef den1024Mb 8 | `include "1024Mb_ddr3_parameters.vh" 9 | `elsif den2048Mb 10 | `include "2048Mb_ddr3_parameters.vh" 11 | `elsif den4096Mb 12 | `include "4096Mb_ddr3_parameters.vh" 13 | `elsif den8192Mb 14 | `include "8192Mb_ddr3_parameters.vh" 15 | `else 16 | // NOTE: Intentionally cause a compile fail here to force the users 17 | // to select the correct component density before continuing 18 | ERROR: You must specify component density with +define+den____Mb. 19 | `endif*/ 20 | 21 | `timescale 1ps / 1ps 22 | //`include "intf.svh" 23 | //`include "st_defs.svh" 24 | 25 | module top(); 26 | `include "st_defs.svh" 27 | `include "defs.svh" 28 | //`include "sg187.v" 29 | //int next_state; 30 | intf infx(); 31 | iftb itb(); 32 | ddr3 mem(infx.mem); 33 | ddr3_controller ctrl(infx.cntrl,itb.cntrl); //,next_state 34 | 35 | integer i, j; 36 | reg [8*DQ_BITS-1:0] d0, d1, d2, d3; 37 | parameter [31:0] DAT = DQ_BITS/8.0; 38 | reg clock; 39 | 40 | 41 | 42 | 43 | //generate clock 44 | initial begin 45 | $display($time,"\tStarting the simulation"); 46 | clock = 1'b0; 47 | #400; 48 | infx.ck <=1'b1; 49 | itb.clk <= 1'b1; 50 | forever #400 clock = ~clock; 51 | end 52 | 53 | initial begin 54 | forever @(posedge itb.clk)begin 55 | itb.clk <= #(1/2) 1'b0; 56 | itb.clk <= #1 1'b1; 57 | end 58 | end 59 | initial begin 60 | forever @(posedge infx.ck) begin //ddr3 clock at tck_min = 938ps 61 | infx.ck <= #(tck/2) 1'b0; 62 | infx.ck <= #(tck) 1'b1; 63 | end 64 | end 65 | 66 | initial begin 67 | 68 | //Power Up 69 | itb.cmd = pwr_up; 70 | itb.next_state = activating; 71 | $display($time,"\ttb: Power Up Command Asserted"); 72 | 73 | 74 | //Bank Activate 75 | @(posedge itb.cmd_en); 76 | itb.cmd = act; 77 | itb.next_state = prec; 78 | itb.t = int'(TRAS_MIN/tck) + 1; //activate to precharge command time 79 | itb.ba = 3;//$urandom_range (8); 80 | itb.row = $urandom_range (1<