├── .gitignore ├── Makefile ├── README.md ├── a10_soc_devkit_ghrd_pro ├── .gitignore ├── Makefile ├── README.md ├── construct_subsys_dp.tcl ├── construct_subsys_jtag_master.tcl ├── construct_subsys_mixer.tcl ├── construct_subsys_pcie.tcl ├── construct_subsys_peripheral.tcl ├── construct_subsys_pr_region.tcl ├── construct_subsys_sgmii.tcl ├── construct_subsys_tse.tcl ├── create_ghrd_qsys.tcl ├── create_ghrd_quartus.tcl ├── create_ghrd_top.tcl ├── create_pr_revision.tcl ├── custom_ip │ ├── ack_delay_logic │ │ └── ack_delay_logic.sv │ ├── altera_a10_gmii_to_sgmii │ │ └── altera_gmii_to_sgmii_converter_hw.tcl │ ├── debounce │ │ └── debounce.v │ ├── diffin │ │ └── construct_diffin.tcl │ └── edge_detect │ │ └── altera_edge_detector.v ├── design_config.tcl ├── fpga_dp.sdc ├── fpga_niosii.sdc ├── fpga_pcie.sdc ├── fpga_pr.sdc ├── fpga_sgmii.sdc ├── ghrd_reset.tcl ├── ghrd_sc_script.tcl ├── ghrd_timing.sdc ├── hps_sgmii.sdc ├── jtag.sdc ├── top_level_template.v.terp ├── update_sysid.tcl └── utils.tcl ├── agilex5_soc_devkit_ghrd ├── .gitignore ├── Makefile ├── Makefile.old ├── README.md ├── arguments_solver.tcl ├── board │ ├── Makefile │ ├── board_DK-A5E065BB32AES1_config.tcl │ ├── board_DK-A5E065BB32AES1_emif_setting.tcl │ ├── board_DK-A5E065BB32AES1_make_config.inc │ ├── board_DK-A5E065BB32AES1_pin_assignment_table.tcl │ ├── board_MK-A5E065BB32AES1_config.tcl │ ├── board_MK-A5E065BB32AES1_emif_setting.tcl │ ├── board_MK-A5E065BB32AES1_make_config.inc │ ├── board_MK-A5E065BB32AES1_pin_assignment_table.tcl │ ├── board_bbr_config.tcl │ ├── board_bbr_emif_setting.tcl │ ├── board_bbr_make_config.inc │ ├── board_bbr_pin_assignment_table.tcl │ ├── board_cvr_config.tcl │ ├── board_cvr_emif_setting.tcl │ ├── board_cvr_make_config.inc │ ├── board_cvr_pin_assignment_table.tcl │ ├── board_lbm_config.tcl │ ├── board_lbm_emif_setting.tcl │ ├── board_lbm_make_config.inc │ ├── board_lbm_pin_assignment_table.tcl │ └── preset_files │ │ ├── ddr4 │ │ ├── DDR4-1600L_800MHz_CL12_alloff_component_1CS_1D_16Gb_1Gx16.qprs │ │ ├── DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs │ │ ├── DDR4-1866M_933MHz_CL13_alloff_component_1CS_1D_16Gb_1Gx16.qprs │ │ ├── DDR4-1866M_933MHz_CL13_alloff_component_1CS_1D_16Gb_2Gx8.qprs │ │ ├── DDR4-1866M_933MHz_CL13_alloff_component_1CS_DDP_32Gb_2Gx16.qprs │ │ ├── DDR4-2133R_1066MHz_CL16_alloff_component_1CS_1D_16Gb_1Gx16.qprs │ │ ├── DDR4-2133R_1066MHz_CL16_alloff_component_1CS_1D_16Gb_2Gx8.qprs │ │ ├── DDR4-2133R_1066MHz_CL16_alloff_component_1CS_DDP_16Gb_1Gx16.qprs │ │ ├── DDR4-2133R_1066MHz_CL16_alloff_component_1CS_DDP_32Gb_2Gx16.qprs │ │ ├── DDR4-2400P_1200MHz_CL15_alloff_component_1CS_1D_16Gb_1Gx16.qprs │ │ ├── DDR4-2400P_1200MHz_CL15_alloff_component_1CS_1D_16Gb_2Gx8.qprs │ │ ├── DDR4-2400P_1200MHz_CL15_alloff_component_1CS_DDP_16Gb_1Gx16.qprs │ │ └── DDR4-2400P_1200MHz_CL15_alloff_component_1CS_DDP_32Gb_2Gx16.qprs │ │ ├── lpddr4 │ │ ├── LPDDR4-1600_CL14_Component_Single-Channel_1R_1CPR_8Gb(8GbTotal)_x8_CK_800MHz.qprs │ │ ├── LPDDR4-2133_CL20_Component_Single-Channel-1R-1CPR-8Gb(8Gb_Total)_x8_CK_1066MHz.qprs │ │ ├── LPDDR4-2133_CL20_Component_Single-Channel-1R-2CPR-16Gb(32Gb_Total)_x32_CK_1066MHz.qprs │ │ ├── LPDDR4-2133_CL20_Component_Single-Channel-1R-2CPR-16Gb(32Gb_Total)_x32_CK_1066MHz.qprs~ │ │ ├── LPDDR4-2133_CL20_Component_Single-Channel-1R-2CPR-16Gb(32Gb_Total)_x32_CK_933MHz.qprs │ │ ├── LPDDR4-2133_CL20_Component_Single-Channel-1R-2CPR-8Gb(16Gb_Total)_x16_CK_1066MHz.qprs │ │ ├── LPDDR4-2133_CL20_Component_Single-Channel-1R-2CPR-8Gb(16Gb_Total)_x16_CK_933MHz.qprs │ │ ├── LPDDR4-2133_CL20_Component_Single-Channel_1R_1CPR_8Gb(8GbTotal)_x8_CK_933MHz.qprs │ │ ├── LPDDR4-2400_CL24_Component_Single-Channel_1R_2CPR_16Gb(32Gb_Total)x32_CK_1200MHz.qprs │ │ ├── LPDDR4-2400_CL24_Component_Single-Channel_1R_2CPR_16Gb(32Gb_Total)x32_CK_1200MHz.qprs~ │ │ ├── LPDDR4-2400_CL24_Component_Single-Channel_1R_2CPR_8Gb(16Gb_Total)x16_CK_1200MHz.qprs │ │ └── LPDDR4-2667_CL24_Component_Single-Channel_1R_1CPR_8Gb(8Gb_Total)x8_CK_1200MHz.qprs │ │ └── lpddr5 │ │ ├── LPDDR5-1600_CL5_Component_Dual-Channel-1R-1CPR-16Gb(32GbTotal)_x16_WCK_800MHz.qprs │ │ ├── LPDDR5-1600_CL5_Component_Single-Channel-1R-1CPR-16Gb_(16GbTotal)_x16_WCK_800MHz.qprs │ │ ├── LPDDR5-2133_CL6_Component_Dual-Channel-1R-1CPR-16Gb_(32GbTotal)_x16_WCK_1066MHz.qprs │ │ ├── LPDDR5-2133_CL6_Component_Dual-Channel-1R-1CPR-16Gb_(32GbTotal)_x16_WCK_933MHz.qprs │ │ ├── LPDDR5-2133_CL6_Component_Single-Channel-1R-1CPR-16Gb_(16GbTotal)_x16_WCK_1066MHz.qprs │ │ ├── LPDDR5-2133_CL6_Component_Single-Channel-1R-1CPR-16Gb_(16GbTotal)_x16_WCK_933MHz.qprs │ │ ├── LPDDR5-2750_CL8_Component_Dual-Channel-1R-1CPR-16Gb_(32GbTotal)_x16_WCK_1200MHz.qprs │ │ └── LPDDR5-2750_CL8_Component_Single-Channel-1R-1CPR-16Gb_(16GbTotal)_x16_WCK_1200MHz.qprs ├── build.module ├── construct_agilex_emif.tcl ├── create_ghrd_qsys.tcl ├── create_ghrd_quartus.tcl ├── create_ghrd_top.tcl ├── custom_ip │ ├── Makefile │ ├── debounce │ │ └── debounce.v │ ├── f2sdram_adapter │ │ └── f2sdram_adapter_hw.tcl │ └── reset_sync │ │ └── altera_reset_synchronizer.v ├── design_config.tcl ├── fpga_rgmii_subsys │ ├── Makefile │ ├── alt_construct_subsys_fpga_rgmii.tcl │ └── construct_subsys_fpga_rgmii.tcl ├── hps_subsys │ ├── Makefile │ ├── agilex_hps_io48_delay_chain_solver.tcl │ ├── agilex_hps_parameter_solver.tcl │ ├── agilex_hps_pinmux_solver.tcl │ ├── agilex_io48.tcl │ ├── construct_subsys_hps.tcl │ └── hw_flow.sh ├── issp_reset.tcl ├── jtag.sdc ├── jtag_subsys │ ├── Makefile │ ├── construct_subsys_jtag_master.tcl │ └── hw_flow.sh ├── peripheral_subsys │ ├── Makefile │ ├── construct_subsys_peripheral.tcl │ └── hw_flow.sh ├── scripts │ ├── config_fmt.awk │ └── config_parzer.awk ├── software │ └── hps_debug │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README.md │ │ ├── build.sh │ │ └── hps_wipe.s ├── top_level_sdc_template.sdc.terp ├── top_level_template.v.terp ├── update_sysid.tcl └── utils.tcl ├── agilex_soc_devkit_ghrd ├── Makefile ├── README.md ├── add_sdc_post_qsys.tcl ├── agilex_hps_io48_delay_chain_solver.tcl ├── agilex_hps_parameter_solver.tcl ├── agilex_hps_pinmux_solver.tcl ├── agilex_io48.tcl ├── arguments_solver.tcl ├── board │ ├── board_DK-DEV-AGF023FA_config.tcl │ ├── board_DK-DEV-AGF023FA_emif_setting.tcl │ ├── board_DK-DEV-AGF023FA_make_config.inc │ ├── board_DK-DEV-AGF023FA_pin_assignment_table.tcl │ ├── board_DK-SI-AGF014E_config.tcl │ ├── board_DK-SI-AGF014E_emif_setting.tcl │ ├── board_DK-SI-AGF014E_make_config.inc │ ├── board_DK-SI-AGF014E_pin_assignment_table.tcl │ ├── board_devkit_fm86_config.tcl │ ├── board_devkit_fm86_emif_setting.tcl │ ├── board_devkit_fm86_make_config.inc │ ├── board_devkit_fm86_pin_assignment_table.tcl │ ├── board_devkit_fm87_config.tcl │ ├── board_devkit_fm87_emif_setting.tcl │ ├── board_devkit_fm87_make_config.inc │ ├── board_devkit_fm87_pin_assignment_table.tcl │ ├── board_devkit_fp82_config.tcl │ ├── board_devkit_fp82_emif_setting.tcl │ ├── board_devkit_fp82_make_config.inc │ └── board_devkit_fp82_pin_assignment_table.tcl ├── construct_agilex_emif.tcl ├── construct_hps.tcl ├── construct_subsys_etile_25gbe.tcl ├── construct_subsys_etile_25gbe_1588_ctrl.tcl ├── construct_subsys_etile_25gbe_rx_dma.tcl ├── construct_subsys_etile_25gbe_tx_dma.tcl ├── construct_subsys_etile_tod.tcl ├── construct_subsys_hbm.tcl ├── construct_subsys_jtag_master.tcl ├── construct_subsys_niosv.tcl ├── construct_subsys_pcie.tcl ├── construct_subsys_peripheral.tcl ├── construct_subsys_pr_region.tcl ├── construct_subsys_sgmii.tcl ├── create_ghrd_qsys.tcl ├── create_ghrd_quartus.tcl ├── create_ghrd_top.tcl ├── create_pr_revision.tcl ├── custom_ip │ ├── ack_delay_logic │ │ └── ack_delay_logic.sv │ ├── agilex_etile_hip_adapter │ │ ├── etile_hip_adapter.v │ │ └── etile_hip_adapter_hw.tcl │ ├── altera_eth_fifo_pause_ctrl_adapter │ │ ├── altera_eth_fifo_pause_ctrl_adapter.v │ │ └── altera_eth_fifo_pause_ctrl_adapter_hw.tcl │ ├── debounce │ │ └── debounce.v │ ├── edge_detect │ │ └── altera_edge_detector.v │ ├── eth_tod_load_off │ │ ├── eth_tod_load_off.v │ │ └── eth_tod_load_off_hw.tcl │ ├── ethernet_ptp_ip │ │ ├── eth_rx_timestamp_adapter │ │ │ ├── eth_rx_timestamp_adapter.v │ │ │ └── eth_rx_timestamp_adapter_hw.tcl │ │ ├── eth_tod_distributor │ │ │ ├── eth_tod_distributor.v │ │ │ └── eth_tod_distributor_hw.tcl │ │ ├── eth_ts_fingerprint_compare │ │ │ ├── eth_ts_fingerprint_compare.v │ │ │ └── eth_ts_fingerprint_compare_hw.tcl │ │ ├── eth_tx_dma_timestamp_req │ │ │ ├── eth_tx_dma_timestamp_req.v │ │ │ └── eth_tx_dma_timestamp_req_hw.tcl │ │ ├── eth_tx_timestamp_adapter │ │ │ ├── eth_tx_timestamp_adapter.v │ │ │ └── eth_tx_timestamp_adapter_hw.tcl │ │ ├── start_tod_sync │ │ │ ├── start_tod_sync.v │ │ │ └── start_tod_sync_hw.tcl │ │ └── tod_mux │ │ │ ├── tod_mux.v │ │ │ └── tod_mux_hw.tcl │ ├── hps_adapter │ │ ├── hps_adapter.sv │ │ ├── hps_adapter_dcfifo_s.sv │ │ ├── hps_adapter_hw.tcl │ │ └── hps_adapter_util.sv │ ├── prefetcher_ts_insert │ │ ├── altera_msgdma_prefetcher_ts_insert.v │ │ └── altera_msgdma_prefetcher_ts_insert_hw.tcl │ ├── reset_sync │ │ └── altera_reset_synchronizer.v │ └── sgpio_slave │ │ └── sgpio_slave.v ├── design_config.tcl ├── etile_10gbe_da_drc.dawf ├── etile_25gbe.sdc ├── etile_25gbe_da_drc.dawf ├── etile_dr_da_drc.dawf ├── fpga_pcie.sdc ├── fpga_pr.sdc ├── issp_reset.tcl ├── jtag.sdc ├── pin_assign_agilex_emif.tcl ├── sgmii_timing.sdc ├── software │ └── hps_debug │ │ ├── Makefile │ │ ├── Makefile_ARMCLANG.inc │ │ ├── Makefile_GCC.inc │ │ ├── README.md │ │ ├── hps_debug.S │ │ └── scatter.scat ├── top_level_sdc_template.sdc.terp ├── top_level_template.v.terp ├── update_sysid.tcl └── utils.tcl ├── cv_soc_devkit_ghrd ├── Makefile ├── README.md ├── construct_subsys_pcie.tcl ├── create_ghrd_qsys.tcl ├── create_ghrd_quartus.tcl ├── create_ghrd_top.tcl ├── design_config.tcl ├── ds5 │ └── altera_avalon_pio_led.ds ├── fpga_pcie.sdc ├── ghrd_reset.tcl ├── ghrd_sc_script.tcl ├── ip │ ├── debounce │ │ └── debounce.v │ ├── edge_detect │ │ └── altera_edge_detector.v │ └── reset_synchronizer │ │ ├── custom_reset_synchronizer_hw.tcl │ │ ├── reset_sync_block.sdc │ │ └── reset_sync_block.v ├── soc_system_timing.sdc └── top_level_template.v.terp ├── license.txt ├── requirements.txt └── s10_soc_devkit_ghrd ├── Makefile ├── README.md ├── add_sdc_post_qsys.tcl ├── arguments_solver.tcl ├── board ├── emif_configuration_devkit.tcl ├── emif_pin_assignment_table_devkit.tcl └── pin_assignment_table_devkit.tcl ├── construct_hps.tcl ├── construct_ip_alt_mge_10gbe_1588.tcl ├── construct_niosii.tcl ├── construct_s10_emif.tcl ├── construct_subsys_10gbe_addr_decoder.tcl ├── construct_subsys_jtag_master.tcl ├── construct_subsys_mge.tcl ├── construct_subsys_mge_10gbe_1588_ctrl.tcl ├── construct_subsys_mge_10gbe_1588_dma.tcl ├── construct_subsys_mge_rx_dma.tcl ├── construct_subsys_mge_tx_dma.tcl ├── construct_subsys_pcie.tcl ├── construct_subsys_peripheral.tcl ├── construct_subsys_pr_region.tcl ├── create_ghrd_qsys.tcl ├── create_ghrd_quartus.tcl ├── create_ghrd_top.tcl ├── create_pr_revision.tcl ├── custom_ip ├── ack_delay_logic │ └── ack_delay_logic.sv ├── altera_eth_fifo_pause_ctrl_adapter │ ├── altera_eth_fifo_pause_ctrl_adapter.v │ └── altera_eth_fifo_pause_ctrl_adapter_hw.tcl ├── avmm_feedthrough_bridge │ ├── avmm_feedthough_bridge.v │ └── avmm_feedthrough_bridge_hw.tcl ├── debounce │ └── debounce.v ├── edge_detect │ └── altera_edge_detector.v ├── ethernet_ptp_ip │ ├── eth_rx_timestamp_adapter │ │ ├── eth_rx_timestamp_adapter.v │ │ └── eth_rx_timestamp_adapter_hw.tcl │ ├── eth_ts_fingerprint_compare │ │ ├── eth_ts_fingerprint_compare.v │ │ └── eth_ts_fingerprint_compare_hw.tcl │ ├── eth_tx_dma_timestamp_req │ │ ├── eth_tx_dma_timestamp_req.v │ │ └── eth_tx_dma_timestamp_req_hw.tcl │ └── eth_tx_timestamp_adapter │ │ ├── eth_tx_timestamp_adapter.v │ │ └── eth_tx_timestamp_adapter_hw.tcl ├── prefetcher_ts_insert │ ├── altera_msgdma_prefetcher_ts_insert.v │ └── altera_msgdma_prefetcher_ts_insert_hw.tcl ├── reset_sync │ └── altera_reset_synchronizer.v └── s10_acp_adapter │ ├── s10_axi_bridge_for_acp_128.v │ └── s10_axi_bridge_for_acp_128_hw.tcl ├── design_config.tcl ├── fpga_i2c.sdc ├── fpga_mge.sdc ├── fpga_mge_10g.sdc ├── fpga_pcie.sdc ├── fpga_pr.sdc ├── issp_reset.tcl ├── jtag.sdc ├── pin_assign_s10_emif.tcl ├── s10_hps_io48_delay_chain_solver.tcl ├── s10_hps_parameter_solver.tcl ├── s10_hps_pinmux_solver.tcl ├── s10_io48.tcl ├── software ├── devicetree │ └── socfpga_stratix10_ghrd.dtsi └── hps_debug │ ├── Makefile │ ├── Makefile_ARMCLANG.inc │ ├── Makefile_GCC.inc │ ├── README.md │ ├── hps_debug.S │ └── scatter.scat ├── top_level_sdc_template.sdc.terp ├── top_level_template.v.terp ├── update_sysid.tcl └── utils.tcl /.gitignore: -------------------------------------------------------------------------------- 1 | /venv/ 2 | /install/ 3 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Golden Hardware Reference Design (GHRD) Build Scripts 2 | 3 | GHRD is a reference design for Intel System On Chip (SoC) FPGA. The GHRD works together with Golden Software Reference design (GSRD) for complete solution to boot Uboot and Linux with Intel SoC Development board. 4 | 5 | This reference design demonstrating the following system integration between Hard Processor System (HPS) and FPGA IPs: 6 | - Hard Processor System enablement and configuration 7 | - HPS Peripheral and I/O (eg, NAND, SD/MMC, EMAC, USB, SPI, I2C, UART, and GPIO) 8 | - HPS Clock and Reset 9 | - HPS FPGA Bridge and Interrupt 10 | - HPS EMIF configuration 11 | - System integration with FPGA IPs 12 | - SYSID 13 | - Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs) 14 | - FPGA On-Chip Memory 15 | - PCIe Rootport IP 16 | - Ethernet IP 17 | 18 | ## This repository hosts build scripts for all GHRD. Build scripts are organized according to the Intel SoC FPGA Family: 19 | ### GHRD for Intel Quartus Prime Pro Edition 20 | * agilex_soc_devkit_ghrd 21 | * agilex5_soc_devkit_ghrd 22 | * s10_soc_devkit_ghrd 23 | * a10_soc_devkit_ghrd_pro 24 | 25 | ### GHRD for Intel Quartus Prime Standard Edtion 26 | * a10_soc_devkit_ghrd_std 27 | * cv_soc_devkit_ghrd 28 | 29 | ## Build Steps: 30 | Refer to the README in repective folder for build steps. 31 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/.gitignore: -------------------------------------------------------------------------------- 1 | dni/ 2 | output_files/ 3 | qdb/ 4 | tmp-clearbox/ 5 | 6 | intel_custom_ip/ 7 | ip/ 8 | hps_isw_handoff/ 9 | qsys_top/ 10 | 11 | ghrd_10as066n2.qpf 12 | ghrd_10as066n2.qsf 13 | ghrd_a10_top.v 14 | qsys_generate_qsys 15 | qsys_top.qsys 16 | qsys_top.qsys.legacy 17 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/README.md: -------------------------------------------------------------------------------- 1 | # Arria 10 (A10) Golden Hardware Reference Design (GHRD) Build Scripts 2 | 3 | A10 GHRD is a reference design for Intel A10 System On Chip (SoC) FPGA. The GHRD works together with Golden Software Reference design (GSRD) for complete solution to boot Uboot and Linux with Intel SoC Development board. 4 | 5 | This reference design demonstrating the following system integration between Hard Processor System (HPS) and FPGA IPs: 6 | - Hard Processor System enablement and configuration 7 | - HPS Peripheral and I/O (eg, NAND, SD/MMC, EMAC, USB, SPI, I2C, UART, and GPIO) 8 | - HPS Clock and Reset 9 | - HPS FPGA Bridge and Interrupt 10 | - HPS EMIF configuration 11 | - System integration with FPGA IPs 12 | - SYSID 13 | - Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs) 14 | - FPGA On-Chip Memory 15 | - PCIe RootPort IP 16 | - SGMII with HPS EMAC and Triple-Speed Ethernet Intel FPGA IP (PHY) 17 | - SGMII with Triple-Speed Ethernet Intel FPGA IP (MAC + PHY) 18 | - Partial Reconfiguration 19 | 20 | This repository hosts build scripts for S10 GHRD. 21 | 22 | ## Dependency 23 | * Intel Quartus Prime 23.3 24 | * Intel Custom IP will be download automatically from rocketboard.org by the Makefile. The download link will be updated to the Makefile for the latest version. 25 | * Supported Board 26 | - Intel Arria 10 SoC Development Kit 27 | 28 | ## Tested Platform for the GHRD Make flow 29 | * Red Hat Enterprise Linux Server release 6.10 30 | 31 | ## Available Make Target: 32 | The GHRD is built with Makefile. Here are the supported Make Targets: 33 | ********************* 34 | * Target: `generate_from_tcl` 35 | * Generate the Quartus Project source files from tcl script source 36 | ********************* 37 | * Target: `help` 38 | * Displays this info (i.e. the available targets) 39 | ********************* 40 | * Target: `qsys_edit` 41 | * Launch Platform Designer GUI 42 | ********************* 43 | * Target: `quartus_edit` 44 | * Launch Quartus Prime GUI 45 | ********************* 46 | * Target: `scrub_clean` 47 | * Restore design to its barebones state 48 | ********************* 49 | * Target: `sof` 50 | * QSys generate & Quartus compile this design 51 | ********************* 52 | * Target: `tgz` 53 | * Create a tarball with the barebones source files that comprise this design 54 | ********************* 55 | 56 | ## Build Steps 57 | 1) Customize the GHRD settings in Makefile. [Not necessary if the default option is good] 58 | 2) Generate the Quartus Project and source files. 59 | - $ `make generate_from_tcl` 60 | 3) Compile Quartus Project and generate the configuration file 61 | - $ `make sof` or $ `make all` 62 | 63 | ## GHRD Customization in Makefile 64 | Here are the list of custom settings support in Makefile. 65 | - `QUARTUS_DEVICE` : Device OPN 66 | - 10AS066N3F40E2SG (Default - BOARD_REV:C), 10AS066N3F40E2SGE2 (BOARD_REV:B), 10AS066N2F40I2SGES (BOARD_REV:A) 67 | - `BOARD_REV` : Board Revision 68 | - C (Default), B, A 69 | - `HPS_BOOT_DEVICE` : HPS BOOT DEVICE. 70 | - SDMMC (Default), QSPI, NAND 71 | - `ENABLE_EARLY_IO_RELEASE` : Enable Early IO Release 72 | - 0, 1 (Default) 73 | - `ENABLE_HPS_EMIF_ECC` : Enable HPS EMIF ECC. REVA Agilex doesnt support ECC Enable. 74 | - 0, 1 (Default) 75 | 76 | ### Enable only one of the below at a time. Work in progress to enable them at once. 77 | - `HPS_ENABLE_SGMII` : Enable SGMII (1GbE, 100MbE, 10MbE) design (HPS EMAC + Triple-Speed Ethernet Intel FPGA IP). 78 | - 0 (Default), 1 79 | - `HPS_ENABLE_TSE` : Enable SGMII (1GbE, 100MbE, 10MbE) with TSE MAC (Triple-Speed Ethernet Intel FPGA IP - both MAC and PHY). 80 | - 0 (Default), 1 81 | - `ENABLE_PCIE` : Enable Gen2x8 PCIe Design. 82 | - 0 (Default), 1 83 | - `ENABLE_PARTIAL_RECONFIGURATION` : Enable Partial Reconfiguration Design. 84 | - 0 (Default), 1 85 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/custom_ip/ack_delay_logic/ack_delay_logic.sv: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2016-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // ack delay logic 9 | // 10 | //**************************************************************************** 11 | 12 | module ack_delay_logic ( 13 | input wire [31:0] delay_ack_pio, 14 | input wire ack_in, 15 | output wire ack_delay_out, 16 | input wire clk, 17 | input wire reset 18 | ); 19 | 20 | wire ack_loopback_delay_ver; 21 | reg [1:0] state, next_state; 22 | reg [31:0] ack_delay_counter; 23 | reg start_ack_count; 24 | reg en_ack_loopback; 25 | reg reset_ack_count; 26 | 27 | localparam [1:0] IDLE = 2'b00; 28 | localparam [1:0] ACK_DELAY_COUNT = 2'b01; 29 | localparam [1:0] ENABLE_ACK_LOOPBACK = 2'b10; 30 | localparam [1:0] RESET_ACK_DELAY_COUNT = 2'b11; 31 | 32 | always @(posedge clk or posedge reset) begin 33 | if (reset) begin 34 | ack_delay_counter <= 32'd0; 35 | end 36 | else begin 37 | if (start_ack_count) begin 38 | ack_delay_counter <= ack_delay_counter + 32'd1; 39 | end 40 | if (reset_ack_count) begin 41 | ack_delay_counter <= 32'd0; 42 | end 43 | end 44 | end 45 | 46 | always @(posedge clk or posedge reset) begin 47 | if (reset) begin 48 | state <= IDLE; 49 | end else begin 50 | state <= next_state; 51 | end 52 | end 53 | 54 | always @* begin 55 | case (state) 56 | IDLE: begin 57 | if (ack_in) begin 58 | if (delay_ack_pio == 0) begin 59 | next_state = ENABLE_ACK_LOOPBACK; 60 | end else begin 61 | next_state = ACK_DELAY_COUNT; 62 | end 63 | end 64 | else begin 65 | next_state = IDLE; 66 | end 67 | end 68 | 69 | ACK_DELAY_COUNT: begin 70 | if (ack_delay_counter == delay_ack_pio) begin 71 | next_state = ENABLE_ACK_LOOPBACK; 72 | end 73 | else begin 74 | next_state = ACK_DELAY_COUNT; 75 | end 76 | end 77 | 78 | ENABLE_ACK_LOOPBACK: begin 79 | if (~ack_in) begin 80 | next_state = RESET_ACK_DELAY_COUNT; 81 | end 82 | else begin 83 | next_state = ENABLE_ACK_LOOPBACK; 84 | end 85 | end 86 | 87 | RESET_ACK_DELAY_COUNT: begin 88 | next_state = IDLE; 89 | end 90 | 91 | default: begin 92 | next_state = 2'bxx; 93 | end 94 | endcase 95 | end 96 | 97 | always @(next_state) begin 98 | if (next_state == ACK_DELAY_COUNT) begin 99 | start_ack_count <= 1'b1; 100 | end else 101 | start_ack_count <= 1'b0; 102 | end 103 | 104 | always @(next_state) begin 105 | if (next_state == ENABLE_ACK_LOOPBACK) begin 106 | en_ack_loopback <= 1'b1; 107 | end else 108 | en_ack_loopback <= 1'b0; 109 | end 110 | 111 | always @(next_state) begin 112 | if (next_state == RESET_ACK_DELAY_COUNT || next_state == IDLE) begin 113 | reset_ack_count <= 1'b1; 114 | end else 115 | reset_ack_count <= 1'b0; 116 | end 117 | 118 | assign ack_delay_out = (en_ack_loopback) ? ack_in : 1'b0; 119 | 120 | endmodule 121 | 122 | 123 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/custom_ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // debouce 9 | // 10 | //**************************************************************************** 11 | 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/custom_ip/diffin/construct_diffin.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2016-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script construct diffin qsys component for GHRD with Display Port enabled 9 | # command to run: create the qsys file: qsys-script --script=./ip/diffin/construct_diffin.tcl to create the qsys file, to generate qsys library: qsys-generate --synthesis=VERILOG diffin.qsys --output-directory=./../diffin/ 10 | # 11 | #**************************************************************************** 12 | 13 | # source ./../../design_config.tcl 14 | set DEVICE_FAMILY "Arria 10" 15 | set FPGA_DEVICE 10AS066N3F40E2SG 16 | 17 | if { ![ info exists devicefamily ] } { 18 | set devicefamily $DEVICE_FAMILY 19 | } else { 20 | puts "-- Accepted parameter \$devicefamily = $devicefamily" 21 | } 22 | 23 | if { ![ info exists device ] } { 24 | set device $FPGA_DEVICE 25 | } else { 26 | puts "-- Accepted parameter \$device = $device" 27 | } 28 | 29 | package require -exact qsys 14.1 30 | 31 | create_system {diffin} 32 | 33 | set_project_property DEVICE_FAMILY $devicefamily 34 | set_project_property DEVICE $device 35 | 36 | # Instances and instance parameters 37 | # (disabled instances are intentionally culled) 38 | add_instance diffin altera_gpio 39 | set_instance_parameter_value diffin {PIN_TYPE_GUI} {Input} 40 | set_instance_parameter_value diffin {SIZE} {1} 41 | set_instance_parameter_value diffin {gui_enable_migratable_port_names} {1} 42 | set_instance_parameter_value diffin {gui_diff_buff} {1} 43 | set_instance_parameter_value diffin {gui_pseudo_diff} {0} 44 | set_instance_parameter_value diffin {gui_bus_hold} {0} 45 | set_instance_parameter_value diffin {gui_open_drain} {0} 46 | set_instance_parameter_value diffin {gui_use_oe} {0} 47 | set_instance_parameter_value diffin {gui_enable_termination_ports} {0} 48 | set_instance_parameter_value diffin {gui_io_reg_mode} {none} 49 | set_instance_parameter_value diffin {gui_sreset_mode} {None} 50 | set_instance_parameter_value diffin {gui_areset_mode} {None} 51 | set_instance_parameter_value diffin {gui_enable_cke} {0} 52 | set_instance_parameter_value diffin {gui_hr_logic} {0} 53 | set_instance_parameter_value diffin {gui_separate_io_clks} {0} 54 | set_instance_parameter_value diffin {EXT_DRIVER_PARAM} {0} 55 | set_instance_parameter_value diffin {GENERATE_SDC_FILE} {0} 56 | set_instance_parameter_value diffin {IP_MIGRATE_PORT_MAP_FILE} {altiobuf_in_port_map.csv} 57 | 58 | # exported interfaces 59 | set_instance_property diffin AUTO_EXPORT {true} 60 | 61 | # interconnect requirements 62 | set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {HANDSHAKE} 63 | set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {1} 64 | set_interconnect_requirement {$system} {qsys_mm.enableEccProtection} {FALSE} 65 | set_interconnect_requirement {$system} {qsys_mm.insertDefaultSlave} {FALSE} 66 | 67 | save_system {diffin.qsys} 68 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/custom_ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Intel Edge Detector 9 | // 10 | //**************************************************************************** 11 | 12 | module altera_edge_detector #( 13 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 14 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 15 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 16 | ) ( 17 | input clk, 18 | input rst_n, 19 | input signal_in, 20 | output pulse_out 21 | ); 22 | 23 | localparam IDLE = 0, ARM = 1, CAPT = 2; 24 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 25 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 26 | 27 | reg [1:0] state, next_state; 28 | reg pulse_detect; 29 | wire busy_pulsing; 30 | 31 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 32 | assign reset_qual_n = rst_n | busy_pulsing; 33 | 34 | generate 35 | if (PULSE_EXT > 1) begin: pulse_extend 36 | integer i; 37 | reg [PULSE_EXT-1:0] extend_pulse; 38 | always @(posedge clk or negedge reset_qual_n) begin 39 | if (!reset_qual_n) 40 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 41 | else begin 42 | for (i = 1; i < PULSE_EXT; i = i+1) begin 43 | extend_pulse[i] <= extend_pulse[i-1]; 44 | end 45 | extend_pulse[0] <= pulse_detect; 46 | end 47 | end 48 | assign pulse_out = |extend_pulse; 49 | end 50 | else begin: single_pulse 51 | reg pulse_reg; 52 | always @(posedge clk or negedge reset_qual_n) begin 53 | if (!reset_qual_n) 54 | pulse_reg <= 1'b0; 55 | else 56 | pulse_reg <= pulse_detect; 57 | end 58 | assign pulse_out = pulse_reg; 59 | end 60 | endgenerate 61 | 62 | always @(posedge clk) begin 63 | if (!rst_n) 64 | state <= IDLE; 65 | else 66 | state <= next_state; 67 | end 68 | 69 | // edge detect 70 | always @(*) begin 71 | next_state = state; 72 | pulse_detect = 1'b0; 73 | case (state) 74 | IDLE : begin 75 | pulse_detect = 1'b0; 76 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 77 | else next_state = IDLE; 78 | end 79 | ARM : begin 80 | pulse_detect = 1'b0; 81 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 82 | else next_state = ARM; 83 | end 84 | CAPT : begin 85 | pulse_detect = 1'b1; 86 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 87 | else next_state = IDLE; 88 | end 89 | default : begin 90 | pulse_detect = 1'b0; 91 | next_state = IDLE; 92 | end 93 | endcase 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/fpga_dp.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2015-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. Targeting Display Port. 9 | # 10 | #**************************************************************************** 11 | 12 | # Clock Group 13 | # create_clock -name DP_REFCLK -period 3.703 [get_ports dp_refclk] 14 | derive_pll_clocks -create_base_clocks 15 | derive_clock_uncertainty 16 | 17 | # Clock Group 18 | # set_clock_groups -exclusive \ 19 | # -group [get_clocks {MAIN_CLOCK}] \ 20 | # -group [get_clocks {DP_REFCLK}] \ 21 | # -group [get_clocks {soc_inst|dp_0|tx_clkout}] \ 22 | # -group [get_clocks {soc_inst|dp_0|*|outclk0 soc_inst|dp_0|*|outclk1 soc_inst|dp_0|*|outclk2}] 23 | set_clock_groups -exclusive \ 24 | -group [get_clocks {MAIN_CLOCK}] \ 25 | -group [get_clocks {soc_inst|dp_0|*|tx_clkout}] \ 26 | -group [get_clocks {soc_inst|dp_0|*|outclk0 soc_inst|dp_0|*|outclk1 soc_inst|dp_0|*|outclk2}] 27 | 28 | set_output_delay -clock { soc_inst|dp_0|*|outclk1 } 0.5 [get_ports {dp_aux_ch_p}] 29 | set_output_delay -clock { soc_inst|dp_0|*|outclk1 } 0.5 [get_ports {dp_aux_ch_n}] 30 | set_input_delay -clock { soc_inst|dp_0|*|outclk1 } 0.5 [get_ports {dp_aux_ch_p}] 31 | set_input_delay -clock { soc_inst|dp_0|*|outclk1 } 0.5 [get_ports {dp_aux_ch_n}] 32 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/fpga_niosii.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2016-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. Targeting NIOS II. 9 | # 10 | #**************************************************************************** 11 | 12 | # 100MHz board input clock, 133.3333MHz for EMIF refclk 13 | create_clock -name EMIF_REFCLOCK -period 7.5 [get_ports a10_emif_pll_ref_clk_clock_clk] 14 | 15 | derive_pll_clocks -create_base_clocks 16 | 17 | # UART 18 | set_false_path -from * -to [get_ports {uart_tx}] 19 | 20 | ##ASMI2 21 | # create_generated_clock -name {DCLK} -source [get_nets {soc_inst|qspi_pll|qspi_pll|altera_iopll_i|twentynm_pll|outclk[0]}] -master_clock {soc_inst|qspi_pll|qspi_pll|outclk0} 22 | # # ncs 23 | # set tSLCH 4 24 | # set tCHSL 4 25 | # # asdata 26 | # set tCLQV 6 27 | # set tCLQX 1 28 | 29 | # set tDVCH 2 30 | # set tCHDX 3 31 | 32 | # set tBRD_CK_max 1.0 33 | # set tBRD_CK_min 0.5 34 | # set tBRD_DT_max 1.0 35 | # set tBRD_DT_min 0.5 36 | 37 | # set_output_delay -clock DCLK -max [expr $tSLCH + $tBRD_DT_max - $tBRD_CK_min] [get_ports NCS*] 38 | # set_output_delay -clock DCLK -min [expr -$tCHSL + $tBRD_DT_min - $tBRD_CK_max] [get_ports NCS*] 39 | 40 | # set_input_delay -clock DCLK -clock_fall -max [expr $tCLQV + $tBRD_CK_max + $tBRD_DT_max] [get_ports AS_DATA*] 41 | # set_input_delay -clock DCLK -clock_fall -min [expr $tCLQX + $tBRD_CK_min + $tBRD_DT_min] [get_ports AS_DATA*] 42 | 43 | # set_output_delay -clock DCLK -max [expr $tDVCH + $tBRD_DT_max - $tBRD_CK_min] [get_ports AS_DATA*] 44 | # set_output_delay -clock DCLK -min [expr -$tCHDX + $tBRD_DT_min - $tBRD_CK_max] [get_ports AS_DATA*] 45 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/fpga_pcie.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2015-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. Targeting PCIE component. 9 | # 10 | #**************************************************************************** 11 | 12 | # Clock Group 13 | # create_clock -name PCIE_REFCLK -period 10 [get_ports pcie_refclk_100] 14 | derive_pll_clocks -create_base_clocks 15 | derive_clock_uncertainty 16 | 17 | set_false_path -from [ get_ports {pcie_a10_hip_npor_pin_perst}] 18 | set_clock_groups -asynchronous -group [get_clocks {MAIN_CLOCK}] -group [get_clocks {soc_inst|pcie_0|*|wys~CORE_CLK_OUT}] 19 | 20 | #to false path the reset output into the reset synchronizer input port due to new reset requirement(synchronous assert & de-assertion) of mSGDMA 21 | set_false_path -from {soc_inst|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out} -to [get_registers {soc_inst|pcie_0|rst_controller_*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]}] 22 | set_false_path -from {soc_inst|*|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[0]} -to [get_registers {soc_inst|pcie_0|rst_controller_*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]}] -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/fpga_pr.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2016-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. Targeting PR component. 9 | # 10 | #**************************************************************************** 11 | 12 | # False path to the PIO instances for acknowledgement delay testing only 13 | create_clock -name frz_ack_pio -period 10.000 [get_registers {soc_inst|frz_ack_pio|frz_ack_pio|data_out[0]}] 14 | set_false_path -from [get_clocks {frz_ack_pio}] -to * 15 | set_false_path -from * -to [get_clocks {frz_ack_pio}] 16 | 17 | create_clock -name stop_ack_pio -period 10.000 [get_registers {soc_inst|stop_ack_pio|stop_ack_pio|data_out[0]}] 18 | set_false_path -from [get_clocks {stop_ack_pio}] -to * 19 | set_false_path -from * -to [get_clocks {stop_ack_pio}] 20 | 21 | create_clock -name start_ack_pio -period 10.000 [get_registers {soc_inst|start_ack_pio|start_ack_pio|data_out[0]}] 22 | set_false_path -from [get_clocks {start_ack_pio}] -to * 23 | set_false_path -from * -to [get_clocks {start_ack_pio}] -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/fpga_sgmii.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2015-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. Targeting FPGA SGMII (TSE MAC and PHY). 9 | # 10 | #**************************************************************************** 11 | 12 | # Clock Group 13 | # create_clock -name PCS_REFLCLK -period 8.000 [get_ports {pcs_clk_125}] 14 | derive_pll_clocks -create_base_clocks 15 | derive_clock_uncertainty 16 | # set_clock_groups -asynchronous -group [get_clocks {MAIN_CLOCK}] -group [get_clocks {PCS_REFLCLK}] -group [get_clocks {mac1_fpga_mdc}] -group [get_clocks {mac0_fpga_mdc}] 17 | set_max_skew -to [get_ports "mac0_fpga_mdc"] 2 18 | set_max_skew -to [get_ports "mac1_fpga_mdc"] 2 19 | set_max_skew -to [get_ports "mac0_fpga_mdio"] 2 20 | set_max_skew -to [get_ports "mac1_fpga_mdio"] 2 21 | set_false_path -from * -to [ get_ports sgmii0_phy_reset_n ] 22 | set_false_path -from * -to [ get_ports sgmii1_phy_reset_n ] 23 | set_false_path -from [get_ports {sgmii0_phy_irq_n}] -to * 24 | set_false_path -from [get_ports {sgmii1_phy_irq_n}] -to * 25 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/ghrd_reset.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2014-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample HPS reset trigger script 9 | # to run this script using quartus_stp 10 | # quartus_stp -t ghrd_reset.tcl --cable-name <> --device-index <> --cold-reset 11 | # 12 | #**************************************************************************** 13 | 14 | package require cmdline 15 | 16 | # Command line processing 17 | set parameters { 18 | {-cable-name.arg "" "Name of JTAG cable connected to system to reset. Defaults to value of $BOARD_CABLE."} 19 | {-device-index.arg "" "Device index of the FPGA in JTAG chain. Defaults to value of $BOARD_DEVICE_INDEX."} 20 | {-cold-reset "Cold reset the system. This is the default operation."} 21 | {-warm-reset "Warm reset the system."} 22 | {-debug-reset "Reset the system's debug core."} 23 | } 24 | array set opts [cmdline::getoptions argv $parameters] 25 | 26 | if {[string length $opts(-cable-name)] == 0} { 27 | if {[info exists ::env(BOARD_CABLE)]} { 28 | array set opts [list -cable-name $::env(BOARD_CABLE)] 29 | } else { 30 | puts stderr "Unable to determine board cable to use for reset. Do you have a board resource, or have you specified --cable-name?" 31 | exit 1 32 | } 33 | } 34 | 35 | if {[string length $opts(-device-index)] == 0} { 36 | if {[info exists ::env(BOARD_DEVICE_INDEX)]} { 37 | array set opts [list -device-index $::env(BOARD_DEVICE_INDEX)] 38 | } else { 39 | puts stderr "Unable to determine FPGA device index to use for reset. Do you have a board resource, or have you specified --device-index?" 40 | exit 1 41 | } 42 | } 43 | 44 | if {!$opts(-debug-reset) && !$opts(-warm-reset)} { 45 | # If no operation specified, default to cold reset. 46 | array set opts {-cold-reset 1} 47 | } 48 | 49 | # Helper functions 50 | proc get_device_name { cable_name device_index } { 51 | foreach device_name [get_device_names -hardware_name $cable_name] { 52 | if { [string match "@$device_index:*" $device_name] } { 53 | return $device_name 54 | } 55 | } 56 | } 57 | 58 | proc get_reset_source_instance { cable_name device_name } { 59 | foreach instance [get_insystem_source_probe_instance_info -hardware_name $cable_name -device_name $device_name] { 60 | if { [string match "RST" [lindex $instance 3]] } { 61 | return [lindex $instance 0] 62 | } 63 | } 64 | } 65 | 66 | proc source_write_sequence { cable_name device_name source_instance data_sequence } { 67 | start_insystem_source_probe -hardware_name $cable_name -device_name $device_name 68 | 69 | foreach value $data_sequence { 70 | write_source_data -instance_index $source_instance -value $value -value_in_hex 71 | } 72 | 73 | end_insystem_source_probe 74 | } 75 | 76 | # Look up additional parameters 77 | set device_name [get_device_name $opts(-cable-name) $opts(-device-index)] 78 | set source_instance [get_reset_source_instance $opts(-cable-name) $device_name] 79 | if {![info exists device_name] && ![info exists source_instance]} { 80 | puts stderr "Unable to find device or source index to drive reset. Is the FPGA configured with a design that allows HPS reset?" 81 | exit 1 82 | } 83 | 84 | # Finally, do the reset(s) 85 | if {$opts(-debug-reset)} { 86 | source_write_sequence $opts(-cable-name) $device_name $source_instance {0x0 0x4} 87 | } 88 | 89 | if {$opts(-warm-reset)} { 90 | source_write_sequence $opts(-cable-name) $device_name $source_instance {0x0 0x2} 91 | } 92 | 93 | if {$opts(-cold-reset)} { 94 | source_write_sequence $opts(-cable-name) $device_name $source_instance {0x0 0x1} 95 | } 96 | 97 | exit 0 98 | 99 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/ghrd_timing.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2014-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. 9 | # 10 | #**************************************************************************** 11 | 12 | set_time_format -unit ns -decimal_places 3 13 | 14 | # 100MHz board input clock, 133.3333MHz for EMIF refclk 15 | create_clock -name MAIN_CLOCK -period 10 [get_ports fpga_clk_100] 16 | create_clock -name EMIF_REF_CLOCK -period 7.5 [get_ports emif_ref_clk] 17 | 18 | set_false_path -from [get_ports {fpga_reset_n}] 19 | set_input_delay -clock MAIN_CLOCK 1 [get_ports {fpga_reset_n}] 20 | 21 | # sourcing JTAG related SDC 22 | source ./jtag.sdc 23 | 24 | # FPGA IO port constraints 25 | set_false_path -from [get_ports {fpga_button_pio[0]}] -to * 26 | set_false_path -from [get_ports {fpga_button_pio[1]}] -to * 27 | set_false_path -from [get_ports {fpga_button_pio[2]}] -to * 28 | set_false_path -from [get_ports {fpga_button_pio[3]}] -to * 29 | set_false_path -from [get_ports {fpga_dipsw_pio[0]}] -to * 30 | set_false_path -from [get_ports {fpga_dipsw_pio[1]}] -to * 31 | set_false_path -from [get_ports {fpga_dipsw_pio[2]}] -to * 32 | set_false_path -from [get_ports {fpga_dipsw_pio[3]}] -to * 33 | set_false_path -from [get_ports {fpga_led_pio[0]}] -to * 34 | set_false_path -from [get_ports {fpga_led_pio[1]}] -to * 35 | set_false_path -from [get_ports {fpga_led_pio[2]}] -to * 36 | set_false_path -from [get_ports {fpga_led_pio[3]}] -to * 37 | set_false_path -from * -to [get_ports {fpga_led_pio[0]}] 38 | set_false_path -from * -to [get_ports {fpga_led_pio[1]}] 39 | set_false_path -from * -to [get_ports {fpga_led_pio[2]}] 40 | set_false_path -from * -to [get_ports {fpga_led_pio[3]}] 41 | 42 | 43 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/hps_sgmii.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2015-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. Targeting HPS SGMII (HPS MAC + TSE PHY). 9 | # 10 | #**************************************************************************** 11 | 12 | # Clock Group 13 | create_clock -name PCS_REFLCLK -period 8.000 [get_ports {pcs_clk_125}] 14 | derive_pll_clocks -create_base_clocks 15 | derive_clock_uncertainty 16 | 17 | set_clock_groups -asynchronous -group [get_clocks {MAIN_CLOCK}] -group [get_clocks {PCS_REFLCLK}] -group [get_clocks {hps_emac2_gtx_clk}] -group [get_clocks {hps_emac1_gtx_clk}] -group [get_clocks {soc_inst|sgmii_*|tx_clkout}] 18 | create_clock -name emac1_fpga_mdc -period 400.000 [get_keepers {*~emac1_gmii_mdc_o_1.reg}] 19 | create_clock -name emac2_fpga_mdc -period 400.000 [get_keepers {*~emac2_gmii_mdc_o_1.reg}] 20 | set_output_delay -clock { emac1_fpga_mdc } 30 [get_ports {emac1_fpga_mdio}] 21 | set_input_delay -clock { emac1_fpga_mdc } 30 [get_ports {emac1_fpga_mdio}] 22 | set_output_delay -clock { emac2_fpga_mdc } 30 [get_ports {emac2_fpga_mdio}] 23 | set_input_delay -clock { emac2_fpga_mdc } 30 [get_ports {emac2_fpga_mdio}] 24 | set_false_path -from * -to [ get_ports sgmii1_phy_reset_n ] 25 | set_false_path -from * -to [ get_ports sgmii2_phy_reset_n ] 26 | set_false_path -from * -to [ get_ports emac1_fpga_mdc ] 27 | set_false_path -from * -to [ get_ports emac2_fpga_mdc ] 28 | set_false_path -from [get_ports {sgmii1_phy_irq_n}] -to * 29 | set_false_path -from [get_ports {sgmii2_phy_irq_n}] -to * 30 | set_false_path -from [get_registers {*|a10_hps|fpga_interfaces|peripheral_emac*~soc_top/emac*_clk_rx_i.reg}] -to [get_registers {*|gmii2sgmii|gmii_to_sgmii_adapter_0|u_reset_blk|u_mac_rst_rx_pcs|din_sync_*}] 31 | -------------------------------------------------------------------------------- /a10_soc_devkit_ghrd_pro/update_sysid.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script update the GHRD SYSID 9 | # To execute this script using qsys-script 10 | # qsys-script --qpf=none --script=update_sysid.tcl --system-file= 11 | # 12 | #**************************************************************************** 13 | 14 | package require -exact qsys 17.1 15 | 16 | set epoch_time [clock seconds] 17 | set sysid_type "altera_avalon_sysid_qsys" 18 | set generic_component_type "altera_generic_component" 19 | set dot_ip_extension ".ip" 20 | set found_sysid_ip_files [list] 21 | 22 | set qsys_file_path [get_module_property FILE] 23 | set qsys_file_directory [file dirname ${qsys_file_path}] 24 | 25 | foreach inst [get_instances] { 26 | set inst_type [get_instance_property $inst CLASS_NAME] 27 | #puts "$inst_type" 28 | if {$inst_type==$generic_component_type} { 29 | load_component $inst 30 | set component_file [get_instantiation_property IP_FILE] 31 | set extension [file extension ${component_file}] 32 | #puts "$extension" 33 | if {$extension==$dot_ip_extension} { 34 | set type [get_component_property CLASS_NAME] 35 | #puts "$inst: $type" 36 | if {$type==$sysid_type} { 37 | set absolute_ip_file [file join ${qsys_file_directory} ${component_file}] 38 | #puts $absolute_ip_file 39 | lappend found_sysid_ip_files ${absolute_ip_file} 40 | } 41 | } 42 | } 43 | } 44 | 45 | foreach sysid $found_sysid_ip_files { 46 | load_system ${sysid} 47 | #puts [get_module_property GENERATION_ID] 48 | set_module_property GENERATION_ID $epoch_time 49 | #puts [get_module_property GENERATION_ID] 50 | validate_system 51 | save_system ${sysid} 52 | } 53 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/.gitignore: -------------------------------------------------------------------------------- 1 | /tmp-clearbox/ 2 | /qdb/ 3 | /dni/ 4 | /output_files/ 5 | /build/ 6 | 7 | /custom_ip/iopll/iopll_comp/ 8 | 9 | hps_subsys/hps_subsys/ 10 | /hps_subsys/ip/hps_subsys/agilex_hps/ 11 | /hps_subsys/ip/hps_subsys/f2sdram_adapter/ 12 | /hps_subsys/ip/qsys_top/emif_io96b_hps/ 13 | 14 | /jtag_subsys/jtag_subsys/ 15 | /jtag_subsys/ip/jtag_subsys/jtag_clk/ 16 | /jtag_subsys/ip/jtag_subsys/jtag_rst_in/ 17 | /jtag_subsys/ip/jtag_subsys/hps_f2sdram/ 18 | /jtag_subsys/ip/jtag_subsys/fpga_m/ 19 | /jtag_subsys/ip/jtag_subsys/hps_m/ 20 | 21 | /peripheral_subsys/peripheral_subsys/ 22 | /peripheral_subsys/ip/peripheral_subsys/periph_clk/ 23 | /peripheral_subsys/ip/peripheral_subsys/periph_rst_in/ 24 | /peripheral_subsys/ip/peripheral_subsys/sysid/ 25 | /peripheral_subsys/ip/peripheral_subsys/button_pio/ 26 | /peripheral_subsys/ip/peripheral_subsys/dipsw_pio/ 27 | /peripheral_subsys/ip/peripheral_subsys/led_pio/ 28 | /peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/ 29 | 30 | /qsys_top/ 31 | /ip/qsys_top/clk_100/ 32 | /ip/qsys_top/rst_in/ 33 | /ip/qsys_top/user_rst_clkgate_0/ 34 | /ip/qsys_top/ocm/ 35 | /ip/qsys_top/gts_inst/ 36 | /ip/qsys_top/altera_ace5lite_cache_coherency_translator_0/ 37 | /ip/qsys_top/ext_hps_f2sdram_master/ 38 | 39 | ghrd_a5ed065bb32ae6sr0.qpf 40 | ghrd_a5ed065bb32ae6sr0.qsf 41 | ghrd_agilex5_top.v 42 | hps_subsys/hps_subsys.qsys 43 | hps_subsys/hps_subsys.qsys.legacy 44 | hps_subsys/ip/hps_subsys/agilex_hps.ip 45 | hps_subsys/ip/hps_subsys/f2sdram_adapter.ip 46 | hps_subsys/ip/qsys_top/emif_io96b_hps.ip 47 | ip/qsys_top/altera_ace5lite_cache_coherency_translator_0.ip 48 | ip/qsys_top/clk_100.ip 49 | ip/qsys_top/ext_hps_f2sdram_master.ip 50 | ip/qsys_top/gts_inst.ip 51 | ip/qsys_top/ocm.ip 52 | ip/qsys_top/rst_in.ip 53 | ip/qsys_top/user_rst_clkgate_0.ip 54 | jtag_subsys/ip/jtag_subsys/fpga_m.ip 55 | jtag_subsys/ip/jtag_subsys/hps_f2sdram.ip 56 | jtag_subsys/ip/jtag_subsys/hps_m.ip 57 | jtag_subsys/ip/jtag_subsys/jtag_clk.ip 58 | jtag_subsys/ip/jtag_subsys/jtag_rst_in.ip 59 | jtag_subsys/jtag_subsys.qsys 60 | jtag_subsys/jtag_subsys.qsys.legacy 61 | peripheral_subsys/ip/peripheral_subsys/button_pio.ip 62 | peripheral_subsys/ip/peripheral_subsys/dipsw_pio.ip 63 | peripheral_subsys/ip/peripheral_subsys/led_pio.ip 64 | peripheral_subsys/ip/peripheral_subsys/pb_cpu_0.ip 65 | peripheral_subsys/ip/peripheral_subsys/periph_clk.ip 66 | peripheral_subsys/ip/peripheral_subsys/periph_rst_in.ip 67 | peripheral_subsys/ip/peripheral_subsys/sysid.ip 68 | peripheral_subsys/peripheral_subsys.qsys 69 | peripheral_subsys/peripheral_subsys.qsys.legacy 70 | qsys_generate_qsys 71 | qsys_top.qsys 72 | qsys_top.qsys.legacy 73 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/board/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | MAKE := make 4 | 5 | 6 | MODULES += qsys_top 7 | MODULES += subsys_hps 8 | MODULES += subsys_jtg_mst 9 | MODULES += subsys_periph 10 | 11 | 12 | .PHONY: $(MODULES) 13 | $(MODULES): 14 | $(MAKE) -C $@ 15 | 16 | 17 | .PHONY: all 18 | all: $(MODULES) 19 | $(warning $?) 20 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/board/board_DK-A5E065BB32AES1_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "PCIE Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #SM 14 | DEVICE ?= A5ED065BB32AE6SR0 15 | 16 | #HPS EMIF Reference Clock 17 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "33.333" 18 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/board/board_MK-A5E065BB32AES1_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "PCIE Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #SM 14 | DEVICE ?= A5ED065BB32AE5SR0 15 | 16 | #HPS EMIF Reference Clock 17 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "33.333" 18 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/board/board_bbr_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "PCIE Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #SM 14 | QUARTUS_DEVICE ?= A5ED065BB32AE5SR0 15 | 16 | #HPS EMIF Reference Clock 17 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "166.625" 18 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/board/board_cvr_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "PCIE Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #SM 14 | DEVICE ?= A5ED065BB32AE5SR0 15 | 16 | #HPS EMIF Reference Clock 17 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "166.625" 18 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/board/board_lbm_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "PCIE Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #SM 14 | DEVICE ?= A5ED065BB32AE5SR0 15 | 16 | #HPS EMIF Reference Clock 17 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "33.333" 18 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/build.module: -------------------------------------------------------------------------------- 1 | hps_subsys 2 | jtag_subsys 3 | peripheral_subsys 4 | fpga_rgmii_subsys 5 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/custom_ip/Makefile: -------------------------------------------------------------------------------- 1 | ######################################################################## 2 | # copyright 3 | # 4 | # 5 | ######################################################################## 6 | 7 | 8 | ################## USER TOPLEVEL CONFIGURATION ########################## 9 | # 10 | # CUSTOM_IP : 11 | # - 0: disable 12 | # - 1: enable [default] 13 | # 14 | ######################################################################### 15 | 16 | 17 | MAKE := make 18 | PWD := $(shell pwd) 19 | EMPTY := 20 | 21 | 22 | PROJECT_ROOT := $(PWD)/../ 23 | GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.custom_ip 24 | GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.custome_ip 25 | GHRD_SCRIPT_FILE := $(PROJECT_ROOT)/scripts/config_parzer.awk 26 | 27 | .PHONY: all 28 | all: 29 | $(shell echo) 30 | 31 | .PHONY: config 32 | config: 33 | @awk -v config_file=$(GHRD_CONFIG_FILE) -v help_file=$(GHRD_HELP_FILE) -f $(GHRD_SCRIPT_FILE) Makefile 34 | 35 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/custom_ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // debouce 9 | // 10 | //**************************************************************************** 11 | 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/custom_ip/reset_sync/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2014 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/main/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#11 $ 15 | // $Revision: #11 $ 16 | // $Date: 2011/08/09 $ 17 | // $Author: aferrucc $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/fpga_rgmii_subsys/Makefile: -------------------------------------------------------------------------------- 1 | ######################################################################## 2 | # copyright 3 | # 4 | # 5 | ######################################################################## 6 | 7 | 8 | ################## USER TOPLEVEL CONFIGURATION ########################## 9 | # 10 | # <- 11 | # SUB_FPGA_RGMII_EN : 12 | # - 0: disable [default] 13 | # - 1: enable 14 | # -> 15 | # 16 | ######################################################################### 17 | 18 | MAKE := make 19 | PWD := $(shell pwd) 20 | EMPTY := 21 | ENABLE := 1 22 | DISABLE := 0 23 | SPACE := 24 | SLASH := / 25 | 26 | CURRENT_FOLDER := $(lastword $(subst $(SLASH), $(SPACE),$(PWD))) 27 | PROJECT_ROOT := $(PWD)/../ 28 | GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.$(CURRENT_FOLDER) 29 | GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.$(CURRENT_FOLDER) 30 | GHRD_SCRIPT_FILE := $(PROJECT_ROOT)/scripts/config_parzer.awk 31 | 32 | 33 | .PHONY: generate_from_tcl 34 | generate_from_tcl: 35 | ifeq ($(SUB_FPGA_RGMII_EN), $(ENABLE)) 36 | @qsys-script $(shell echo $(QSYS_ARGS) | sed 's/quartus-project=/quartus-project=..\//g') --script=./construct_subsys_fpga_rgmii.tcl --cmd="$(QSYS_TCL_ARGS)" 37 | else 38 | @echo "$(CURRENT_FOLDER) does not be enabled, skip." 39 | endif 40 | @echo "generate_from_tcl for $(CURRENT_FOLDER)!" 41 | 42 | .PHONY: config 43 | config: 44 | @awk -v config_file=$(GHRD_CONFIG_FILE) -v help_file=$(GHRD_HELP_FILE) -f $(GHRD_SCRIPT_FILE) Makefile 45 | 46 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/fpga_rgmii_subsys/construct_subsys_fpga_rgmii.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2023 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script construct Peripherals subsystem for higher level integration later. 9 | # The Makefile in $prjroot folder will pass in variable needed by this TCL as defined 10 | # in the subsystem Makefile automatically. User will have the ability to modify the 11 | # defined variable dynamically during (MAKE) target flow of generate_from_tcl. 12 | # 13 | #**************************************************************************** 14 | set currentdir [pwd] 15 | set foldername [file tail $currentdir] 16 | puts "\[GHRD:info\] Directory name: $foldername" 17 | 18 | puts "\[GHRD:info\] \$prjroot = ${prjroot} " 19 | source ${prjroot}/arguments_solver.tcl 20 | source ${prjroot}/utils.tcl 21 | 22 | if {$board == "cvr"} { 23 | source $prjroot/board/board_cvr_config.tcl 24 | } else { 25 | source $prjroot/board/board_DK-A5E065BB32AES1_config.tcl 26 | } 27 | 28 | set subsys_name $foldername 29 | 30 | package require -exact qsys 23.4 31 | 32 | #proc do_create_bbb {} { 33 | #global subsys_name 34 | #global device 35 | #global device_family 36 | 37 | # create the system 38 | create_system $subsys_name 39 | #set_project_property BOARD {default} 40 | set_project_property DEVICE $device 41 | set_project_property DEVICE_FAMILY $device_family 42 | # set_project_property HIDE_FROM_IP_CATALOG {false} 43 | # set_use_testbench_naming_pattern 0 {} 44 | 45 | # add HDL parameters 46 | 47 | add_component_param "altera_clock_bridge clock_in 48 | IP_FILE_PATH ip/$subsys_name/clock_in.ip 49 | EXPLICIT_CLOCK_RATE 100000000 50 | NUM_CLOCK_OUTPUTS 1 51 | " 52 | 53 | add_component_param "intel_gmii_to_rgmii_converter intel_gmii_to_rgmii_converter_0 54 | IP_FILE_PATH ip/$subsys_name/intel_gmii_to_rgmii_converter_0.ip 55 | RX_PIPELINE_DEPTH 5 56 | TX_PIPELINE_DEPTH 2 57 | " 58 | 59 | add_component_param "altera_iopll iopll_0 60 | IP_FILE_PATH ip/$subsys_name/iopll_0.ip 61 | gui_number_of_clocks 2 62 | gui_clock_name_string0 outclk0 63 | gui_output_clock_frequency0 25.0 64 | gui_clock_name_string1 outclk1 65 | gui_output_clock_frequency1 2.5 66 | " 67 | 68 | add_component_param "altera_reset_bridge reset_in 69 | IP_FILE_PATH ip/$subsys_name/reset_in.ip 70 | SYNC_RESET 0 71 | NUM_RESET_OUTPUTS 1 72 | " 73 | 74 | # Add the connection 75 | connect " clock_in.out_clk intel_gmii_to_rgmii_converter_0.peri_clock 76 | clock_in.out_clk iopll_0.refclk 77 | clock_in.out_clk reset_in.clk 78 | iopll_0.outclk0 intel_gmii_to_rgmii_converter_0.pll_25m_clock 79 | iopll_0.outclk1 intel_gmii_to_rgmii_converter_0.pll_2_5m_clock 80 | iopll_0.locked intel_gmii_to_rgmii_converter_0.locked_pll_tx 81 | reset_in.out_reset intel_gmii_to_rgmii_converter_0.peri_reset 82 | reset_in.out_reset iopll_0.reset 83 | " 84 | 85 | # Add the exports 86 | 87 | export clock_in in_clk clk 88 | export reset_in in_reset reset 89 | export intel_gmii_to_rgmii_converter_0 phy_rgmii phy_rgmii 90 | export intel_gmii_to_rgmii_converter_0 hps_gmii hps_gmii 91 | 92 | # save the system 93 | sync_sysinfo_parameters 94 | save_system ${subsys_name}.qsys 95 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/hps_subsys/agilex_hps_io48_delay_chain_solver.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This file means to solve chain delay assignment to all IO48 pins 9 | # 10 | #**************************************************************************** 11 | 12 | # Initialize IO48 chain delay assignment based on port properties 13 | set io48_output_pin [list "JTAG:TDO" "SDMMC:CCLK" "USB*:STP" "EMAC*:TX_CLK" "EMAC*:TX_CTL" "EMAC*:TXD0" "EMAC*:TXD1" "EMAC*:TXD2" "EMAC*:TXD3" "MDIO*:MDC" \ 14 | "SPIM0:CLK" "SPIM0:MOSI" "SPIM0:SS0_N" "SPIS0:MISO" "UART0:TX" "UART0:RTS_N" "NAND:ALE" "NAND:CE_N" "NAND:CLE" "NAND:WE_N" "NAND:RE_N" "NAND:WP_N" \ 15 | ] 16 | set io48_input_pin [list "JTAG:TCK" "JTAG:TMS" "JTAG:TDI" "USB*:CLK" "USB*:DIR" "USB*:NXT" "EMAC*:RX_CLK" "EMAC*:RX_CTL" "EMAC*:RXD0" "EMAC*:RXD1" "EMAC*:RXD2" "EMAC*:RXD3" \ 17 | "SPIM0:MISO" "SPIS0:CLK" "SPIS0:MOSI" "SPIS0:SS0_N" "UART0:RX" "UART0:CTS_N" "NAND:RB" "HPS_OSC_CLK" "TRACE:CLK" "TRACE:D0" "TRACE:D1" "TRACE:D2" "TRACE:D3" \ 18 | "TRACE:D10" "TRACE:D9" "TRACE:D8" "TRACE:D7" "TRACE:D6" "TRACE:D15" "TRACE:D14" "TRACE:D13" "TRACE:D12" "TRACE:D11" \ 19 | ] 20 | set io48_bidirect_pin [list "SDMMC:CMD" "SDMMC:D0" "SDMMC:D1" "SDMMC:D2" "SDMMC:D3" "SDMMC:D4" "SDMMC:D5" "SDMMC:D6" "SDMMC:D7" "I2CEMAC*:SDA" "I2CEMAC*:SCL" \ 21 | "USB*:DATA0" "USB*:DATA1" "USB*:DATA2" "USB*:DATA3" "USB*:DATA4" "USB*:DATA5" "USB*:DATA6" "USB*:DATA7" "I2C*:SDA" "I2C*:SCL" \ 22 | "MDIO*:MDIO" "NAND:ADQ0" "NAND:ADQ1" "NAND:ADQ2" "NAND:ADQ3" "NAND:ADQ4" "NAND:ADQ5" "NAND:ADQ6" "NAND:ADQ7" "NAND:ADQ8" "NAND:ADQ9" \ 23 | "NAND:ADQ10" "NAND:ADQ11" "NAND:ADQ12" "NAND:ADQ13" "NAND:ADQ14" "NAND:ADQ15" "GPIO" \ 24 | ] 25 | 26 | set io48_pinmux_assignment [list $io48_q1_assignment $io48_q2_assignment $io48_q3_assignment $io48_q4_assignment] 27 | set count 0 28 | array set output_dly_chain_io48 [] 29 | array set input_dly_chain_io48 [] 30 | foreach io_quadrant $io48_pinmux_assignment { 31 | foreach io_pin $io_quadrant { 32 | if [string match [lindex $io48_output_pin 3] $io_pin] { 33 | set output_dly_chain_io48($count) 21 34 | set input_dly_chain_io48($count) -1 35 | } elseif [string match [lindex $io48_input_pin 6] $io_pin] { 36 | set output_dly_chain_io48($count) -1 37 | set input_dly_chain_io48($count) 21 38 | } elseif [string match [lindex $io48_bidirect_pin 3] $io_pin] { 39 | set output_dly_chain_io48($count) -1 40 | set input_dly_chain_io48($count) -1 41 | } else { 42 | set output_dly_chain_io48($count) -1 43 | set input_dly_chain_io48($count) -1 44 | } 45 | incr count 46 | } 47 | } 48 | 49 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/hps_subsys/hw_flow.sh: -------------------------------------------------------------------------------- 1 | qsys-script --quartus_project=../ghrd_a5ed065bb32ae5sr0.qpf --script=construct_subsys_hps.tcl \ 2 | --cmd="set devicefamily Agilex5; set project_name ghrd_a5ed065bb32ae5sr0; set subsys_name subsys_hps; set device A5ED065BB32AE5SR0; set board hidden; set hps_emif_ecc_en 0; set fpga_first_en 0; set daughter_card devkit_dc_oobe; set hps_emif_en 0; set f2h_width 0;" 3 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/issp_reset.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | #use this tcl script to perform a reset assertion & deassertion to the whole design system for AGILEX GHRD 9 | #the reset assertion and deassertion here are done via ISSP(In System Source & Probe) after device is programmed successfully 10 | # 11 | #**************************************************************************** 12 | 13 | set issp [lindex [get_service_paths issp] 0] 14 | set issp_m [claim_service issp $issp claimGroup] 15 | 16 | set current_source_data [issp_read_source_data $issp_m] 17 | puts "src_reset_n value: $current_source_data" 18 | #assert reset 19 | puts "assert src_reset_n via issp" 20 | set source_data 0x0 21 | issp_write_source_data $issp_m $source_data 22 | set current_source_data [issp_read_source_data $issp_m] 23 | puts "src_reset_n value: $current_source_data" 24 | after 500 25 | puts "deassert src_reset_n via issp" 26 | #deassert reset 27 | set source_data 0x1 28 | issp_write_source_data $issp_m $source_data 29 | set current_source_data [issp_read_source_data $issp_m] 30 | puts "src_reset_n value: $current_source_data" 31 | 32 | close_service issp $issp_m 33 | puts "\nInfo: Closed ISSP Service\n\n" -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/jtag_subsys/Makefile: -------------------------------------------------------------------------------- 1 | ######################################################################## 2 | # copyright 3 | # 4 | # 5 | ######################################################################## 6 | 7 | 8 | ################## USER TOPLEVEL CONFIGURATION ########################## 9 | # 10 | # <- 11 | # SUB_DEBUG_EN : 12 | # - 0: disable 13 | # - 1: enable [default] 14 | # -> 15 | # 16 | ######################################################################### 17 | 18 | 19 | MAKE := make 20 | PWD := $(shell pwd) 21 | EMPTY := 22 | ENABLE := 1 23 | DISABLE := 0 24 | SLASH := / 25 | SPACE := 26 | 27 | CURRENT_FOLDER := $(lastword $(subst $(SLASH), $(SPACE),$(PWD))) 28 | PROJECT_ROOT := $(PWD)/../ 29 | GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.$(CURRENT_FOLDER) 30 | GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.$(CURRENT_FOLDER) 31 | GHRD_SCRIPT_FILE := $(PROJECT_ROOT)/scripts/config_parzer.awk 32 | 33 | 34 | #SUB_QSYS_TCL_ARG += set current_folder $(CURRENT_FOLDER); 35 | #QSYS_TCL_ARGS += set current_folder $(CURRENT_FOLDER); 36 | #$(info ammended qsys_tcl_arg is $(QSYS_TCL_ARGS)) 37 | 38 | .PHONY: generate_from_tcl 39 | generate_from_tcl: 40 | ifeq ($(SUB_DEBUG_EN), $(ENABLE)) 41 | @qsys-script $(shell echo $(QSYS_ARGS) | sed 's/quartus-project=/quartus-project=..\//g') --script=./construct_subsys_jtag_master.tcl --cmd="$(QSYS_TCL_ARGS)" 42 | else 43 | @echo "$(CURRENT_FOLDER) does not be enabled, skip." 44 | endif 45 | @echo "generate_from_tcl for $(CURRENT_FOLDER)!" 46 | 47 | .PHONY: config 48 | config: 49 | @awk -v config_file=$(GHRD_CONFIG_FILE) -v help_file=$(GHRD_HELP_FILE) -f $(GHRD_SCRIPT_FILE) Makefile 50 | 51 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/jtag_subsys/hw_flow.sh: -------------------------------------------------------------------------------- 1 | qsys-script --quartus_project=../ghrd_a5ed065bb32ae5sr0.qpf --script=construct_subsys_jtag_master.tcl \ 2 | --cmd="set devicefamily Agilex5; set project_name ghrd_a5ed065bb32ae5sr0; set subsys_name subsys_jtg_mst; set device A5ED065BB32AE5SR0; set board hidden; set daughter_card devkit_dc_oobe; set f2h_width 0;" 3 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/peripheral_subsys/Makefile: -------------------------------------------------------------------------------- 1 | ######################################################################## 2 | # copyright 3 | # 4 | # 5 | ######################################################################## 6 | 7 | 8 | ################## USER TOPLEVEL CONFIGURATION ########################## 9 | # 10 | # <- 11 | # SUB_PERI_EN : 12 | # - 0: disable 13 | # - 1: enable [default] 14 | # FPGA_DATA_MOVER_EN : 15 | # - 0: disable [default] 16 | # - 1: enable 17 | # 18 | # -> 19 | # 20 | ######################################################################### 21 | 22 | MAKE := make 23 | PWD := $(shell pwd) 24 | EMPTY := 25 | ENABLE := 1 26 | DISABLE := 0 27 | SPACE := 28 | SLASH := / 29 | 30 | CURRENT_FOLDER := $(lastword $(subst $(SLASH), $(SPACE),$(PWD))) 31 | PROJECT_ROOT := $(PWD)/../ 32 | GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.$(CURRENT_FOLDER) 33 | GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.$(CURRENT_FOLDER) 34 | GHRD_SCRIPT_FILE := $(PROJECT_ROOT)/scripts/config_parzer.awk 35 | 36 | 37 | .PHONY: generate_from_tcl 38 | generate_from_tcl: 39 | ifeq ($(SUB_PERI_EN), $(ENABLE)) 40 | @qsys-script $(shell echo $(QSYS_ARGS) | sed 's/quartus-project=/quartus-project=..\//g') --script=./construct_subsys_peripheral.tcl --cmd="$(QSYS_TCL_ARGS)" 41 | else 42 | @echo "$(CURRENT_FOLDER) does not be enabled, skip." 43 | endif 44 | @echo "generate_from_tcl for $(CURRENT_FOLDER)!" 45 | 46 | .PHONY: config 47 | config: 48 | @awk -v config_file=$(GHRD_CONFIG_FILE) -v help_file=$(GHRD_HELP_FILE) -f $(GHRD_SCRIPT_FILE) Makefile 49 | 50 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/peripheral_subsys/hw_flow.sh: -------------------------------------------------------------------------------- 1 | qsys-script --quartus_project=../ghrd_a5ed065bb32ae5sr0.qpf --script=construct_subsys_peripheral.tcl \ 2 | --cmd="set devicefamily Agilex5; set project_name ghrd_a5ed065bb32ae5sr0; set subsys_name subsys_periph; set device A5ED065BB32AE5SR0; set board hidden; set daughter_card devkit_dc_oobe; set f2h_width 0;" 3 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/scripts/config_fmt.awk: -------------------------------------------------------------------------------- 1 | BEGIN{ 2 | FS=" " 3 | config_str = ""; 4 | OUTPUT_FILE = output; 5 | }{ 6 | for (i = 1; i <= NF; i++) { 7 | if (match($i, /(.+)=(.+)/, var)) { 8 | config_str = config_str "" sprintf("%-30s=%5s%s\n", var[1], " ", var[2]); 9 | } 10 | } 11 | }END{ 12 | print config_str > OUTPUT_FILE 13 | } 14 | 15 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/scripts/config_parzer.awk: -------------------------------------------------------------------------------- 1 | #!/usr/bin/awk -f 2 | #=============================================================================== 3 | # Description: parze user configuraion from Makefile 4 | # Author: 5 | # Organization: intel 6 | # Version: 1.0 7 | # Created: 07/25/23 17:13:40 8 | # Revision: 1.0 9 | # License: Copyright (c) 2023 10 | #=============================================================================== 11 | 12 | function get_help_str(strin, nameorval) { 13 | s = substr(strin, 2); 14 | # strip spaces 15 | gsub(/^\s*/, "", s); 16 | gsub(/\s*$/, "", s); 17 | 18 | if (nameorval == "name") { 19 | str_out = sprintf("%-4s%s", " ", s); 20 | } else if (nameorval == "val") { 21 | str_out = sprintf("%-8s%s", " ", s); 22 | } 23 | 24 | return str_out; 25 | } 26 | 27 | BEGIN{ 28 | is_block_start = 0; 29 | is_new_var = 0; 30 | 31 | help_str = ""; 32 | config_str = ""; 33 | 34 | HELP_FILE = help_file; # external variable 35 | CONFIG_FILE = config_file; 36 | } { 37 | 38 | # demo config block 39 | # <- 40 | # HPS_EMIF_EN : 41 | # - 0: enable hps emif [default] 42 | # - 1: disable hps emif module 43 | # HPS_EMIF_ECC_EN : 44 | # - 0: enable hps emif ecc [default] 45 | # - 1: disable hps emif module 46 | # HPS_HBME_EN : 47 | # - 0: enable hps emif [default] 48 | # - 1: disable hps emif module 49 | # -> 50 | 51 | if ($0 ~/^#\s+<-.*$/) { 52 | is_block_start = 1; 53 | next; 54 | } 55 | 56 | if ($0 ~/^#\s+->.*$/) { 57 | is_block_start = 0; 58 | exit; 59 | } 60 | 61 | if (is_block_start == 1) { 62 | if (match($0, /^#\s+(.+)\s*:\s*$/, var_name)) { 63 | str = get_help_str($0, "name"); 64 | help_str = help_str ""str"\n"; 65 | 66 | config_str = config_str "" sprintf("%-30s=", var_name[1]); 67 | 68 | } else if (match($0, /^#\s+-\s*([a-zA-Z0-9\._-]+)\s*:\s*.+$/, var_val)) { 69 | str = get_help_str($0, "val"); 70 | help_str = help_str ""str"\n"; 71 | 72 | if (match(str, /default/)) { 73 | config_str = config_str "" sprintf("%5s%s\n", "", var_val[1]); 74 | } 75 | } 76 | } 77 | 78 | } END{ 79 | 80 | print help_str > HELP_FILE 81 | print config_str > CONFIG_FILE 82 | 83 | } 84 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/software/hps_debug/.gitignore: -------------------------------------------------------------------------------- 1 | /gcc-arm/ 2 | hps_wipe.bin 3 | hps_wipe.elf 4 | hps_wipe.ihex 5 | hps_wipe.objdump 6 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/software/hps_debug/Makefile: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2023 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Makefile for HPS Wipe Firmware 9 | # 10 | ################################################ 11 | 12 | # Environment check 13 | ifeq ($(CROSS_COMPILE),) 14 | $(error CORSS_COMPILE not defined) 15 | endif 16 | 17 | CC:= $(CROSS_COMPILE)as 18 | OBJCOPY := $(CROSS_COMPILE)objcopy 19 | OBJDUMP := $(CROSS_COMPILE)objdump 20 | 21 | SRC := hps_wipe.s 22 | ENTRY_POINT:=0x0 23 | 24 | IHEX := $(patsubst %.s,%.ihex,$(SRC)) 25 | ELF := $(patsubst %.s,%.elf,$(SRC)) 26 | BIN := $(patsubst %.s,%.bin,$(SRC)) 27 | OBJDUMP_FILE = $(patsubst %.s,%.objdump,$(SRC)) 28 | 29 | OBJ_FLAG := -I binary -O ihex --change-address $(ENTRY_POINT) 30 | 31 | RM := rm -rf 32 | 33 | .PHONY: all 34 | all: $(ELF) $(BIN) $(IHEX) $(OBJDUMP_FILE) 35 | 36 | clean: 37 | $(RM) $(ELF) $(IHEX) $(BIN) $(OBJDUMP_FILE) 38 | 39 | $(ELF): $(SRC) 40 | $(CC) $(SRC) -o $@ 41 | 42 | $(BIN): $(ELF) 43 | $(OBJCOPY) -O binary $< $@ 44 | 45 | $(IHEX): $(BIN) 46 | $(OBJCOPY) $(OBJ_FLAG) $< $@ 47 | 48 | $(OBJDUMP_FILE): $(ELF) 49 | $(OBJDUMP) --disassemble $< > $@ 50 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/software/hps_debug/README.md: -------------------------------------------------------------------------------- 1 | # HPS Content Wipe Program 2 | 3 | The HPS content wipe program is a small program that is invoked by SDM when there is a security breach event detected or during a cold reset. The intention of this program is to clear HPS content, especially in cache. This memory might contain sensitive data. Besides that, this programm also creates a wait loop for the arm debugger to kick in. 4 | 5 | ## How to build 6 | User can build the HPS wipe by running the build.sh. 7 | The script will automatically download the ARM Toolchain and compile hps_wipe.ihex. 8 | 9 | > cd software/hps debug\ 10 | > ./build.sh 11 | 12 | ## Compile manually 13 | If user already have the ARM Toolchain installed, the version can be specified with the CROSS_COMPILE option. 14 | ### version 7 15 | > $make CROSS_COMPILE=aarch64-linux-gnu- 16 | ### version 9 17 | > $make CROSS_COMPILE=aarch64-none-linux-gnu- 18 | 19 | ## To clean 20 | > $make clean CROSS_COMPILE=aarch64-linux-gnu-\ 21 | > $make clean CROSS_COMPILE=aarch64-none-linux-gnu- 22 | 23 | ## Build from project dir: agilex5_soc_devkit_ghrd 24 | If ARM Toolchain is included in PATH, the Makefile will detect that, build and inject the hps_wipe.ihex to the sof automatically.\ 25 | \ 26 | If Toolchain PATH is included and user would like to inject this programm after compiling the sof with quartus GUI, the following can be called at agilex5_soc_devkit_ghrd folder: 27 | > $make debug_sof 28 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/software/hps_debug/build.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | set -e 4 | 5 | CROSS_COMPILE_VERSION_NUM=11.2-2022.02 6 | CROSS_COMPILE_FILENAME=gcc-arm-$CROSS_COMPILE_VERSION_NUM-x86_64-aarch64-none-linux-gnu 7 | 8 | 9 | if [ ! -d "gcc-arm" ]; then 10 | # Download the ARM Toolchain 11 | wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/$CROSS_COMPILE_FILENAME.tar.xz 12 | 13 | # Unpack the ARM Toolchain 14 | tar xf $CROSS_COMPILE_FILENAME.tar.xz 15 | rm -f $CROSS_COMPILE_FILENAME.tar.xz 16 | mv $CROSS_COMPILE_FILENAME gcc-arm 17 | fi 18 | 19 | # Set required environment variables 20 | export PATH=`pwd`/gcc-arm/bin:$PATH 21 | export ARCH=arm64 22 | export CROSS_COMPILE=aarch64-none-linux-gnu- 23 | 24 | # Build the HPS Debug application 25 | make 26 | -------------------------------------------------------------------------------- /agilex5_soc_devkit_ghrd/update_sysid.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script update the GHRD SYSID 9 | # To execute this script using qsys-script 10 | # qsys-script --qpf=none --script=update_sysid.tcl --system-file= 11 | # 12 | #**************************************************************************** 13 | package require -exact qsys 18.1 14 | 15 | set epoch_time [clock seconds] 16 | set sysid_type "altera_avalon_sysid_qsys" 17 | set generic_component_type "altera_generic_component" 18 | set dot_ip_extension ".ip" 19 | set found_sysid_ip_files [list] 20 | 21 | set qsys_file_path [get_module_property FILE] 22 | set qsys_file_directory [file dirname ${qsys_file_path}] 23 | 24 | foreach inst [get_instances] { 25 | set inst_type [get_instance_property $inst CLASS_NAME] 26 | #puts "$inst_type" 27 | if {$inst_type==$generic_component_type} { 28 | load_component $inst 29 | set component_file [get_instantiation_property IP_FILE] 30 | set extension [file extension ${component_file}] 31 | #puts "$extension" 32 | if {$extension==$dot_ip_extension} { 33 | set type [get_component_property CLASS_NAME] 34 | #puts "$inst: $type" 35 | if {$type==$sysid_type} { 36 | set absolute_ip_file [file join ${qsys_file_directory} ${component_file}] 37 | #puts $absolute_ip_file 38 | lappend found_sysid_ip_files ${absolute_ip_file} 39 | } 40 | } 41 | } 42 | } 43 | 44 | foreach sysid $found_sysid_ip_files { 45 | load_system ${sysid} 46 | #puts [get_module_property GENERATION_ID] 47 | set_module_property GENERATION_ID $epoch_time 48 | #puts [get_module_property GENERATION_ID] 49 | validate_system 50 | save_system ${sysid} 51 | } 52 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/add_sdc_post_qsys.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script generates the Partial Reconfiguration Revision for the PR GHRD. 9 | # To execute this script using quartus_sh for generating PR revision QSF accordingly 10 | # quartus_sh --script=add_sdc_post_qsys.tcl -projectname $(QUARTUS_BASE) -revision $(QUARTUS_BASE_REVISION) -hps_enable_sgmii $(HPS_ENABLE_SGMII) 11 | # 12 | #**************************************************************************** 13 | 14 | package require cmdline 15 | 16 | set options {\ 17 | { "projectname.arg" "" "Project name" } \ 18 | { "hps_enable_sgmii.arg" "" "HPS SGMII ENABLE" } 19 | } 20 | array set opts [::cmdline::getoptions quartus(args) $options] 21 | 22 | project_open $opts(projectname) -current_revision 23 | 24 | if {$opts(hps_enable_sgmii) == 1} { 25 | set_global_assignment -name SDC_FILE sgmii_timing.sdc 26 | } 27 | project_close -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/agilex_hps_io48_delay_chain_solver.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This file means to solve chain delay assignment to all IO48 pins 9 | # 10 | #**************************************************************************** 11 | 12 | # Initialize IO48 chain delay assignment based on port properties 13 | set io48_output_pin [list "JTAG:TDO" "SDMMC:CCLK" "USB*:STP" "EMAC*:TX_CLK" "EMAC*:TX_CTL" "EMAC*:TXD0" "EMAC*:TXD1" "EMAC*:TXD2" "EMAC*:TXD3" "MDIO*:MDC" \ 14 | "SPIM0:CLK" "SPIM0:MOSI" "SPIM0:SS0_N" "SPIS0:MISO" "UART0:TX" "UART0:RTS_N" "NAND:ALE" "NAND:CE_N" "NAND:CLE" "NAND:WE_N" "NAND:RE_N" "NAND:WP_N" \ 15 | ] 16 | set io48_input_pin [list "JTAG:TCK" "JTAG:TMS" "JTAG:TDI" "USB*:CLK" "USB*:DIR" "USB*:NXT" "EMAC*:RX_CLK" "EMAC*:RX_CTL" "EMAC*:RXD0" "EMAC*:RXD1" "EMAC*:RXD2" "EMAC*:RXD3" \ 17 | "SPIM0:MISO" "SPIS0:CLK" "SPIS0:MOSI" "SPIS0:SS0_N" "UART0:RX" "UART0:CTS_N" "NAND:RB" "HPS_OSC_CLK" "TRACE:CLK" "TRACE:D0" "TRACE:D1" "TRACE:D2" "TRACE:D3" \ 18 | "TRACE:D10" "TRACE:D9" "TRACE:D8" "TRACE:D7" "TRACE:D6" "TRACE:D15" "TRACE:D14" "TRACE:D13" "TRACE:D12" "TRACE:D11" \ 19 | ] 20 | set io48_bidirect_pin [list "SDMMC:CMD" "SDMMC:D0" "SDMMC:D1" "SDMMC:D2" "SDMMC:D3" "SDMMC:D4" "SDMMC:D5" "SDMMC:D6" "SDMMC:D7" "I2CEMAC*:SDA" "I2CEMAC*:SCL" \ 21 | "USB*:DATA0" "USB*:DATA1" "USB*:DATA2" "USB*:DATA3" "USB*:DATA4" "USB*:DATA5" "USB*:DATA6" "USB*:DATA7" "I2C*:SDA" "I2C*:SCL" \ 22 | "MDIO*:MDIO" "NAND:ADQ0" "NAND:ADQ1" "NAND:ADQ2" "NAND:ADQ3" "NAND:ADQ4" "NAND:ADQ5" "NAND:ADQ6" "NAND:ADQ7" "NAND:ADQ8" "NAND:ADQ9" \ 23 | "NAND:ADQ10" "NAND:ADQ11" "NAND:ADQ12" "NAND:ADQ13" "NAND:ADQ14" "NAND:ADQ15" "GPIO" \ 24 | ] 25 | 26 | set io48_pinmux_assignment [list $io48_q1_assignment $io48_q2_assignment $io48_q3_assignment $io48_q4_assignment] 27 | set count 0 28 | array set output_dly_chain_io48 [] 29 | array set input_dly_chain_io48 [] 30 | foreach io_quadrant $io48_pinmux_assignment { 31 | foreach io_pin $io_quadrant { 32 | if [string match [lindex $io48_output_pin 3] $io_pin] { 33 | set output_dly_chain_io48($count) 45 34 | set input_dly_chain_io48($count) 0 35 | } elseif [string match [lindex $io48_input_pin 3] $io_pin] { 36 | set output_dly_chain_io48($count) 0 37 | set input_dly_chain_io48($count) 0 38 | } elseif [string match [lindex $io48_bidirect_pin 3] $io_pin] { 39 | set output_dly_chain_io48($count) 0 40 | set input_dly_chain_io48($count) 0 41 | } else { 42 | set output_dly_chain_io48($count) 0 43 | set input_dly_chain_io48($count) 0 44 | } 45 | incr count 46 | } 47 | } 48 | 49 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/agilex_io48.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2021 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This file host all the enabled HPS Daugther Card 9 | # 10 | #**************************************************************************** 11 | 12 | if {$daughter_card == "devkit_dc_oobe"} { 13 | set hps_usb0_en 1 14 | set hps_emac0_rgmii_en 1 15 | set hps_uart0_q3_en 1 16 | set hps_i2c1_q3_en 1 17 | set hps_sdmmc4b_q4_en 1 18 | set hps_mdio0_q4_en 1 19 | set hps_cm_q 4 20 | set hps_cm_io 7 21 | set hps_jtag_en 1 22 | set hps_gpio1_en 1 23 | set hps_gpio1_list "0 1 4 5 19 20 21" 24 | 25 | } elseif {$daughter_card == "devkit_dc2"} { 26 | set hps_sdmmc4b_q1_en 1 27 | set hps_mdio0_q1_en 1 28 | set hps_mdio2_q1_en 1 29 | set hps_i2c_emac1_q1_en 1 30 | set hps_emac0_rgmii_en 1 31 | set hps_emac2_rgmii_en 1 32 | set hps_spim1_q3_en 1 33 | set hps_uart1_q3_en 1 34 | set hps_cm_q 3 35 | set hps_cm_io 5 36 | set hps_jtag_en 1 37 | set hps_gpio1_en 1 38 | set hps_gpio1_list "5" 39 | 40 | } elseif {$daughter_card == "devkit_dc_nand"} { 41 | set hps_nand_q12_en 1 42 | set hps_nand_16b_en 1 43 | set hps_cm_q 2 44 | set hps_cm_io 4 45 | set hps_i2c1_q3_en 1 46 | set hps_emac2_rgmii_en 1 47 | set hps_uart0_q3_en 1 48 | set hps_mdio2_q3_en 1 49 | set hps_gpio1_en 1 50 | set hps_gpio1_list "0 1 4 5 10 11" 51 | 52 | } elseif {$daughter_card == "devkit_dc4"} { 53 | set hps_cm_q 4 54 | set hps_cm_io 3 55 | set hps_uart1_q1_en 1 56 | set hps_sdmmc4b_q1_en 1 57 | set hps_mdio0_q1_en 1 58 | set hps_emac0_rgmii_en 1 59 | set hps_spim1_q3_en 1 60 | set hps_i2c1_q3_en 1 61 | set hps_trace_q34_en 1 62 | set hps_trace_8b_en 1 63 | set hps_jtag_en 1 64 | set hps_gpio0_en 1 65 | set hps_gpio0_list "8 9" 66 | set hps_gpio1_en 1 67 | set hps_gpio1_list "4 5 12 13" 68 | 69 | } elseif {$daughter_card == "devkit_dc_emmc"} { 70 | set hps_sdmmc8b_q1_en 1 71 | set hps_cm_q 2 72 | set hps_cm_io 4 73 | set hps_i2c1_q3_en 1 74 | set hps_emac2_rgmii_en 1 75 | set hps_uart0_q3_en 1 76 | set hps_mdio2_q3_en 1 77 | set hps_gpio1_en 1 78 | set hps_gpio1_list "0 1 4 5 10 11" 79 | 80 | } elseif {$daughter_card == "hps_dc8"} { 81 | set hps_usb0_en 1 82 | set hps_usb1_en 1 83 | set hps_uart0_q3_en 1 84 | set hps_uart0_fc_en 1 85 | set hps_gpio1_en 1 86 | set hps_gpio1_list "4 5" 87 | set hps_jtag_en 1 88 | set hps_sdmmc4b_q4_en 1 89 | set hps_sdmmc4b_q4_pwr_en 1 90 | set hps_cm_q 4 91 | set hps_cm_io 7 92 | 93 | } elseif {$daughter_card == "hps_dc9"} { 94 | set hps_uart0_q1_en 1 95 | set hps_uart0_fc_en 1 96 | set hps_mdio0_q1_en 1 97 | set hps_mdio1_q1_en 1 98 | set hps_emac0_rgmii_en 1 99 | set hps_emac1_rmii_en 1 100 | set hps_jtag_en 1 101 | set hps_sdmmc4b_q4_en 1 102 | set hps_sdmmc4b_q4_pwr_en 1 103 | set hps_cm_q 4 104 | set hps_cm_io 7 105 | 106 | } elseif {$daughter_card == "hps_dc10"} { 107 | set hps_sdmmc8b_q1_en 1 108 | set hps_emac0_rgmii_en 1 109 | set hps_uart0_q3_en 1 110 | set hps_uart0_fc_en 1 111 | set hps_jtag_en 1 112 | set hps_cm_q 4 113 | set hps_cm_io 7 114 | set hps_mdio0_q4_en 1 115 | 116 | } elseif {$daughter_card == "hps_dc13"} { 117 | set hps_nand_q12_en 1 118 | set hps_nand_16b_en 1 119 | set hps_uart0_q3_en 1 120 | set hps_uart0_fc_en 1 121 | set hps_gpio1_en 1 122 | set hps_gpio1_list "4" 123 | set hps_jtag_en 1 124 | set hps_cm_q 4 125 | set hps_cm_io 7 126 | 127 | } elseif {$daughter_card == "none"} { 128 | puts "Disable all HPS IO48 IO" 129 | set hps_io_off 1 130 | } else { 131 | puts "Inserted daughter_card variant: $daughter_card NOT supported" 132 | } 133 | 134 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/board/board_DK-DEV-AGF023FA_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | 14 | #FM76 15 | QUARTUS_DEVICE ?= AGFD023R24C2E1VC 16 | 17 | #HPS EMIF Reference Clock 18 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "166.625" 19 | HPS_EMIF_MEM_CLK_FREQ_MHZ ?= "1333.0" 20 | HPS_EMIF_WIDTH ?= "32" 21 | HPS_EMIF_BANK_GP_WIDTH ?= "2" 22 | HPS_EMIF_COMP_PRESET ?= "DDR4-3200AA CL22 Component 1CS 8Gb (1Gb x8)" 23 | 24 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/board/board_DK-SI-AGF014E_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #FM61 (devkit, mUDV1, mUDV2, char) (Default OPN release to customer) 14 | QUARTUS_DEVICE ?= AGFB014R24B2E2V 15 | #QUARTUS_DEVICE ?= AGFB014R24A2E3VR0 16 | 17 | #HPS EMIF Reference Clock 18 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "100.0" 19 | 20 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/board/board_devkit_fm86_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #FM86 revA(lookout, pyramid, mcgowan); Default OPN release to customer 14 | QUARTUS_DEVICE ?= AGFB027R24C2E2V 15 | 16 | #FM86 revB(lookout, pyramid, mcgowan) 17 | #QUARTUS_DEVICE ?= AGFB027R24C2E2VR2 18 | 19 | #HPS EMIF Reference Clock 20 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "166.625" 21 | HPS_EMIF_MEM_CLK_FREQ_MHZ ?= "1333.0" 22 | HPS_EMIF_WIDTH ?= "32" 23 | HPS_EMIF_BANK_GP_WIDTH ?= "2" 24 | HPS_EMIF_COMP_PRESET ?= "DDR4-3200AA CL22 Component 1CS 8Gb (1Gb x8)" 25 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/board/board_devkit_fm87_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | #FM87 (devkit, mUDV1, mUDV2, char) 14 | #QUARTUS_DEVICE ?= AGIB027R31B1E1VAA 15 | #QUARTUS_DEVICE ?= AGFB014R24A3E3VR0 16 | 17 | #FM87 Rev C (Default OPN release to customer) 18 | QUARTUS_DEVICE ?= AGIB027R31B1E1VB 19 | 20 | #HPS EMIF Reference Clock 21 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "166.666" 22 | 23 | # Option to set HPS EMIF CLK frequency in MHz 24 | HPS_EMIF_MEM_CLK_FREQ_MHZ ?= "1333.33" 25 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/board/board_devkit_fp82_config.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2022 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script hosts board requirements and Quartus settings for the Agilex SoC Devkit board. 9 | # 10 | #**************************************************************************** 11 | 12 | ## Indicate the Pins Availablility for boards 13 | # Set available if there is 14 | # Peripheral pins (LEDs, DIPSW, Push Button) 15 | set isPeriph_pins_available 1 16 | set isSgpio_pins_available 1 17 | set isPCIE_pins_available 1 18 | set isETILE_pins_available 1 19 | 20 | ## Set IO Widths 21 | set fpga_led_pio_width 4 22 | set fpga_dipsw_pio_width 0 23 | set fpga_button_pio_width 0 24 | 25 | #devkit uses the DDR4 HiLo based on x16 components. By JEDEC spec, DDR4 x16 components doesn't requires emif_hps_mem_mem_bg[1] 26 | set hps_emif_bank_gp_default_width 1 27 | 28 | # Quartus settings for SDMIOs 29 | proc config_sdmio {} { 30 | set_global_assignment -name USE_HPS_COLD_RESET SDM_IO9 31 | set_global_assignment -name USE_CONF_DONE SDM_IO5 32 | } 33 | 34 | # Quartus settings for Power Management 35 | proc config_pwrmgt {} { 36 | global board_pwrmgt 37 | if {$board_pwrmgt == "linear"} { 38 | # Linear tech 39 | set_global_assignment -name INI_VARS "ASM_ENABLE_ADVANCED_DEVICES=ON;" 40 | set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" 41 | set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 42 | set_global_assignment -name USE_PWRMGT_SDA SDM_IO16 43 | set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" 44 | set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 45 | set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 1 46 | set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 55 47 | set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" 48 | set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12" 49 | set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS 50 | set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON 51 | set_global_assignment -name PWRMGT_PAGE_COMMAND_PAYLOAD 0 52 | 53 | } 54 | } 55 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/board/board_devkit_fp82_make_config.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Make include file for Board "Devkit" 9 | # This file define the supported configuration 10 | # 11 | ################################################ 12 | 13 | # FP82 OPN default. 14 | QUARTUS_DEVICE ?= AGMF039R47A1E2VR0 15 | 16 | #HPS EMIF Reference Clock 17 | HPS_EMIF_REF_CLK_FREQ_MHZ ?= "100.0" 18 | 19 | # Option to set HPS EMIF CLK frequency in MHz 20 | HPS_EMIF_MEM_CLK_FREQ_MHZ ?= "1600" 21 | 22 | HPS_EMIF_TYPE ?= ddr5 23 | 24 | # HPS_EMIF_WIDTH 25 | HPS_EMIF_WIDTH ?= 32 26 | 27 | # F2H_WIDTH 28 | F2H_WIDTH ?= 256 29 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/construct_subsys_jtag_master.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script construct JTAG AVMM MAster sub system for higher level integration 9 | # The GHRD create_ghrd_qsys.tcl will call each of those subsystem construct script 10 | # automatically based on the corresponding parameter argument defined 11 | # 12 | #**************************************************************************** 13 | 14 | source ./arguments_solver.tcl 15 | source ./utils.tcl 16 | set sub_qsys_jtag subsys_jtg_mst 17 | 18 | create_system $sub_qsys_jtag 19 | 20 | set_project_property DEVICE_FAMILY $device_family 21 | set_project_property DEVICE $device 22 | set_validation_property AUTOMATIC_VALIDATION false 23 | 24 | add_component_param "altera_clock_bridge jtag_clk 25 | IP_FILE_PATH ip/$sub_qsys_jtag/jtag_clk.ip 26 | EXPLICIT_CLOCK_RATE 100000000 27 | NUM_CLOCK_OUTPUTS 1 28 | " 29 | 30 | add_component_param "altera_reset_bridge jtag_rst_in 31 | IP_FILE_PATH ip/$sub_qsys_jtag/jtag_rst_in.ip 32 | ACTIVE_LOW_RESET 1 33 | SYNCHRONOUS_EDGES both 34 | NUM_RESET_OUTPUTS 1 35 | USE_RESET_REQUEST 0 36 | " 37 | 38 | add_component_param "altera_jtag_avalon_master hps_m 39 | IP_FILE_PATH ip/$sub_qsys_jtag/hps_m.ip 40 | " 41 | 42 | add_component_param "altera_jtag_avalon_master fpga_m 43 | IP_FILE_PATH ip/$sub_qsys_jtag/fpga_m.ip 44 | " 45 | 46 | # connections and connection parameters 47 | connect " jtag_clk.out_clk fpga_m.clk 48 | jtag_clk.out_clk jtag_rst_in.clk 49 | jtag_rst_in.out_reset fpga_m.clk_reset 50 | " 51 | 52 | connect " jtag_clk.out_clk hps_m.clk 53 | jtag_rst_in.out_reset hps_m.clk_reset 54 | " 55 | 56 | # exported interfaces 57 | export jtag_rst_in in_reset reset 58 | export jtag_clk in_clk clk 59 | export fpga_m master fpga_m_master 60 | export hps_m master hps_m_master 61 | 62 | 63 | # interconnect requirements 64 | set_domain_assignment {$system} {qsys_mm.clockCrossingAdapter} {AUTO} 65 | set_domain_assignment {$system} {qsys_mm.maxAdditionalLatency} {1} 66 | set_domain_assignment {$system} {qsys_mm.enableEccProtection} {FALSE} 67 | set_domain_assignment {$system} {qsys_mm.insertDefaultSlave} {FALSE} 68 | 69 | sync_sysinfo_parameters 70 | 71 | save_system ${sub_qsys_jtag}.qsys 72 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/create_pr_revision.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script generates the Partial Reconfiguration Revision for the PR GHRD. 9 | # To execute this script using quartus_sh for generating PR revision QSF accordingly 10 | # quartus_sh --script=create_pr_revision.tcl -projectname $(QUARTUS_BASE) -revision $(QUARTUS_BASE_REVISION) -pr_revision $(PR_REV) -pr_partition $(QSYS_SUBSYS_PR) 11 | # 12 | #**************************************************************************** 13 | 14 | package require cmdline 15 | 16 | source ./arguments_solver.tcl 17 | 18 | set options {\ 19 | { "projectname.arg" "" "Project name" } \ 20 | { "revision.arg" "" "Revision name" } \ 21 | { "pr_revision.arg" "" "PR Revision name" } \ 22 | { "revision_type.arg" "" "Revision type" } \ 23 | { "pr_partition.arg" "" "PR Partition name" } 24 | { "pr_hierarchy.arg" "" "PR Hierarchy name" } 25 | } 26 | array set opts [::cmdline::getoptions quartus(args) $options] 27 | 28 | if {[project_exists $opts(projectname)]} { 29 | if {[string equal "" $opts(revision)]} { 30 | project_open $opts(projectname) -current_revision 31 | } else { 32 | project_open $opts(projectname) -revision $opts(revision) 33 | } 34 | } else { 35 | post_message -type error "Project $opts(projectname) does not exist" 36 | exit 37 | } 38 | set base_revision $opts(revision) 39 | set pr_revision $opts(pr_revision) 40 | set revision_type $opts(revision_type) 41 | set pr_partition $opts(pr_partition) 42 | set pr_hierarchy $opts(pr_hierarchy) 43 | 44 | ################################################################################ 45 | # Partial Reconfiguration System 46 | ################################################################################ 47 | namespace eval create_pr_revision { 48 | ################################################################################ 49 | # Core procs 50 | ################################################################################ 51 | 52 | ################################################################################ 53 | # Usage: 54 | # create_pr_revision::create_revision -reconfigurable 55 | ################################################################################ 56 | proc create_revision { typeopt revision base } { 57 | global pr_partition 58 | global pr_hierarchy 59 | 60 | # Error checking 61 | if {![::revision_exists $base]} { 62 | ::post_message -type error "Revision \"$base\" does not exist. Specify a valid base revision for the project." 63 | return 0 64 | } 65 | 66 | if [::revision_exists $revision] { 67 | ::post_message -type error "Revision \"$revision\" already exist. Specify a new reconfigurable revision for the project." 68 | return 0 69 | } 70 | 71 | # Option processing 72 | set type {} 73 | if {$typeopt == "-implementation"} { 74 | set type "PR_IMPL" 75 | } else { 76 | ::post_message -type error "Invalid project revision type \"$type\" specified." 77 | return 0 78 | } 79 | 80 | if {$typeopt == "-implementation"} { 81 | # Extract the reconfigurable partitions from the base revision 82 | set curr_revision [get_current_revision] 83 | ::set_current_revision $base 84 | 85 | ::create_revision -based_on $base -set_current $revision 86 | 87 | set_global_assignment -name REVISION_TYPE PR_IMPL 88 | set_instance_assignment -name QDB_FILE_PARTITION base_static.qdb -to | 89 | set_global_assignment -name ENABLE_SIGNALTAP OFF 90 | set_instance_assignment -name ENTITY_REBINDING $pr_partition -to $pr_hierarchy 91 | } 92 | } 93 | } 94 | 95 | create_pr_revision::create_revision -implementation $pr_revision $base_revision 96 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/ack_delay_logic/ack_delay_logic.sv: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2016-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // ack delay logic 9 | // 10 | //**************************************************************************** 11 | 12 | module ack_delay_logic ( 13 | input wire [31:0] delay_ack_pio, 14 | input wire ack_in, 15 | output wire ack_delay_out, 16 | input wire clk, 17 | input wire reset 18 | ); 19 | 20 | wire ack_loopback_delay_ver; 21 | reg [1:0] state, next_state; 22 | reg [31:0] ack_delay_counter; 23 | reg start_ack_count; 24 | reg en_ack_loopback; 25 | reg reset_ack_count; 26 | 27 | localparam [1:0] IDLE = 2'b00; 28 | localparam [1:0] ACK_DELAY_COUNT = 2'b01; 29 | localparam [1:0] ENABLE_ACK_LOOPBACK = 2'b10; 30 | localparam [1:0] RESET_ACK_DELAY_COUNT = 2'b11; 31 | 32 | always @(posedge clk or posedge reset) begin 33 | if (reset) begin 34 | ack_delay_counter <= 32'd0; 35 | end 36 | else begin 37 | if (start_ack_count) begin 38 | ack_delay_counter <= ack_delay_counter + 32'd1; 39 | end 40 | if (reset_ack_count) begin 41 | ack_delay_counter <= 32'd0; 42 | end 43 | end 44 | end 45 | 46 | always @(posedge clk or posedge reset) begin 47 | if (reset) begin 48 | state <= IDLE; 49 | end else begin 50 | state <= next_state; 51 | end 52 | end 53 | 54 | always @* begin 55 | case (state) 56 | IDLE: begin 57 | if (ack_in) begin 58 | if (delay_ack_pio == 0) begin 59 | next_state = ENABLE_ACK_LOOPBACK; 60 | end else begin 61 | next_state = ACK_DELAY_COUNT; 62 | end 63 | end 64 | else begin 65 | next_state = IDLE; 66 | end 67 | end 68 | 69 | ACK_DELAY_COUNT: begin 70 | if (ack_delay_counter == delay_ack_pio) begin 71 | next_state = ENABLE_ACK_LOOPBACK; 72 | end 73 | else begin 74 | next_state = ACK_DELAY_COUNT; 75 | end 76 | end 77 | 78 | ENABLE_ACK_LOOPBACK: begin 79 | if (~ack_in) begin 80 | next_state = RESET_ACK_DELAY_COUNT; 81 | end 82 | else begin 83 | next_state = ENABLE_ACK_LOOPBACK; 84 | end 85 | end 86 | 87 | RESET_ACK_DELAY_COUNT: begin 88 | next_state = IDLE; 89 | end 90 | 91 | default: begin 92 | next_state = 2'bxx; 93 | end 94 | endcase 95 | end 96 | 97 | always @(next_state) begin 98 | if (next_state == ACK_DELAY_COUNT) begin 99 | start_ack_count <= 1'b1; 100 | end else 101 | start_ack_count <= 1'b0; 102 | end 103 | 104 | always @(next_state) begin 105 | if (next_state == ENABLE_ACK_LOOPBACK) begin 106 | en_ack_loopback <= 1'b1; 107 | end else 108 | en_ack_loopback <= 1'b0; 109 | end 110 | 111 | always @(next_state) begin 112 | if (next_state == RESET_ACK_DELAY_COUNT || next_state == IDLE) begin 113 | reset_ack_count <= 1'b1; 114 | end else 115 | reset_ack_count <= 1'b0; 116 | end 117 | 118 | assign ack_delay_out = (en_ack_loopback) ? ack_in : 1'b0; 119 | 120 | endmodule 121 | 122 | 123 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/altera_eth_fifo_pause_ctrl_adapter/altera_eth_fifo_pause_ctrl_adapter.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2001-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // altera_eth_fifo_pause_ctrl_adapter 9 | // This module generate pause control signal (pause_ctrl_src_data) to MAC when 10 | // when the eth fifo is almost full and release pause when the eth fifo is 11 | // almost empty. 12 | //**************************************************************************** 13 | 14 | // altera message_off 10230 15 | 16 | module altera_eth_fifo_pause_ctrl_adapter 17 | ( 18 | //global 19 | clk, 20 | reset, 21 | //Almost full Data Sink 22 | data_sink_almost_full, 23 | //Almost empty Data Sink 24 | data_sink_almost_empty, 25 | //LL10GMAC PAUSE Source 26 | pause_ctrl_src_data, 27 | //Etile HIP PAUSE Source 28 | pause_ctrl_etile_src_data, 29 | o_sl_rx_pause 30 | ); 31 | 32 | // =head2 Clock and reset interface 33 | input clk; 34 | input reset; 35 | 36 | // =head2 Avalon ST DataIn (Sink) Interface 37 | input data_sink_almost_full; 38 | 39 | // =head2 Avalon ST DataIn (Sink) Interface 40 | input data_sink_almost_empty; 41 | 42 | // =head2 Avalon ST DataOut (Source) Interface 43 | output [1:0] pause_ctrl_src_data; 44 | 45 | // Etile HIP PAUSE Source 46 | output pause_ctrl_etile_src_data; 47 | input o_sl_rx_pause; 48 | 49 | reg hold_almost_full; 50 | reg hold_almost_full_1; 51 | reg reg_data_sink_almost_full; 52 | reg reg_data_sink_almost_empty; 53 | 54 | always @ (posedge clk or posedge reset) 55 | begin 56 | if(reset == 1'b1) 57 | begin 58 | hold_almost_full <= 1'b0; 59 | reg_data_sink_almost_full <= 1'b0; 60 | reg_data_sink_almost_empty <= 1'b0; 61 | hold_almost_full_1 <= 1'b0; 62 | end 63 | else 64 | begin 65 | if(data_sink_almost_empty == 1'b1) 66 | begin 67 | hold_almost_full <= 1'b0; 68 | end 69 | else if(data_sink_almost_full == 1'b1) 70 | begin 71 | hold_almost_full <=1'b1; 72 | end 73 | reg_data_sink_almost_full <= data_sink_almost_full; 74 | reg_data_sink_almost_empty <= data_sink_almost_empty; 75 | hold_almost_full_1 <= hold_almost_full; 76 | end 77 | end 78 | 79 | assign pause_ctrl_src_data[1] = reg_data_sink_almost_full; 80 | assign pause_ctrl_src_data[0] = hold_almost_full_1 & reg_data_sink_almost_empty; 81 | 82 | assign pause_ctrl_etile_src_data = hold_almost_full_1; 83 | 84 | endmodule 85 | 86 | 87 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // debouce 9 | // 10 | //**************************************************************************** 11 | 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Intel Edge Detector 9 | // 10 | //**************************************************************************** 11 | 12 | module altera_edge_detector #( 13 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 14 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 15 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 16 | ) ( 17 | input clk, 18 | input rst_n, 19 | input signal_in, 20 | output pulse_out 21 | ); 22 | 23 | localparam IDLE = 0, ARM = 1, CAPT = 2; 24 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 25 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 26 | 27 | reg [1:0] state, next_state; 28 | reg pulse_detect; 29 | wire busy_pulsing; 30 | 31 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 32 | assign reset_qual_n = rst_n | busy_pulsing; 33 | 34 | generate 35 | if (PULSE_EXT > 1) begin: pulse_extend 36 | integer i; 37 | reg [PULSE_EXT-1:0] extend_pulse; 38 | always @(posedge clk or negedge reset_qual_n) begin 39 | if (!reset_qual_n) 40 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 41 | else begin 42 | for (i = 1; i < PULSE_EXT; i = i+1) begin 43 | extend_pulse[i] <= extend_pulse[i-1]; 44 | end 45 | extend_pulse[0] <= pulse_detect; 46 | end 47 | end 48 | assign pulse_out = |extend_pulse; 49 | end 50 | else begin: single_pulse 51 | reg pulse_reg; 52 | always @(posedge clk or negedge reset_qual_n) begin 53 | if (!reset_qual_n) 54 | pulse_reg <= 1'b0; 55 | else 56 | pulse_reg <= pulse_detect; 57 | end 58 | assign pulse_out = pulse_reg; 59 | end 60 | endgenerate 61 | 62 | always @(posedge clk) begin 63 | if (!rst_n) 64 | state <= IDLE; 65 | else 66 | state <= next_state; 67 | end 68 | 69 | // edge detect 70 | always @(*) begin 71 | next_state = state; 72 | pulse_detect = 1'b0; 73 | case (state) 74 | IDLE : begin 75 | pulse_detect = 1'b0; 76 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 77 | else next_state = IDLE; 78 | end 79 | ARM : begin 80 | pulse_detect = 1'b0; 81 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 82 | else next_state = ARM; 83 | end 84 | CAPT : begin 85 | pulse_detect = 1'b1; 86 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 87 | else next_state = IDLE; 88 | end 89 | default : begin 90 | pulse_detect = 1'b0; 91 | next_state = IDLE; 92 | end 93 | endcase 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/eth_tod_load_off/eth_tod_load_off.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2001-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // eth_tod_load_off.v 9 | // This module terminate the TOD Load input with 0 10 | //**************************************************************************** 11 | 12 | 13 | `timescale 1ns / 1ns 14 | module eth_tod_load_off #( 15 | parameter CONDUIT_DATA_WIDTH = 96 16 | ) ( 17 | //time_of_day_load 18 | output [CONDUIT_DATA_WIDTH-1:0] time_of_day_load_data, 19 | output time_of_day_load_valid 20 | ); 21 | 22 | assign time_of_day_load_data = {CONDUIT_DATA_WIDTH{1'b0}}; 23 | assign time_of_day_load_valid = 1'd0; 24 | 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/eth_tod_load_off/eth_tod_load_off_hw.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2001-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # TCL File Generated by Component Editor 16.1 9 | # DO NOT MODIFY 10 | # 11 | # eth_tod_load_off "eth_tod_load_off" v1.0 12 | # 13 | # request TCL package from ACDS 16.1 14 | #**************************************************************************** 15 | 16 | package require -exact qsys 16.1 17 | 18 | 19 | # 20 | # module eth_tod_load_off 21 | # 22 | set_module_property DESCRIPTION "" 23 | set_module_property NAME eth_tod_load_off 24 | set_module_property VERSION 1.0.0 25 | set_module_property INTERNAL false 26 | set_module_property OPAQUE_ADDRESS_MAP true 27 | set_module_property AUTHOR "Intel Corporation" 28 | set_module_property GROUP "Example Designs/Ethernet/Misc" 29 | set_module_property DISPLAY_NAME "Terminate TOD Load input with 0" 30 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 31 | set_module_property EDITABLE true 32 | set_module_property REPORT_TO_TALKBACK false 33 | set_module_property ALLOW_GREYBOX_GENERATION false 34 | set_module_property REPORT_HIERARCHY false 35 | 36 | 37 | # 38 | # file sets 39 | # 40 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 41 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL eth_tod_load_off 42 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 43 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 44 | add_fileset_file eth_tod_load_off.v VERILOG PATH eth_tod_load_off.v TOP_LEVEL_FILE 45 | 46 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 47 | set_fileset_property SIM_VERILOG TOP_LEVEL eth_tod_load_off 48 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 49 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 50 | add_fileset_file eth_tod_load_off.v VERILOG PATH eth_tod_load_off.v 51 | 52 | 53 | # 54 | # parameters 55 | # 56 | add_parameter CONDUIT_DATA_WIDTH INTEGER 96 "" 57 | set_parameter_property CONDUIT_DATA_WIDTH DEFAULT_VALUE 96 58 | set_parameter_property CONDUIT_DATA_WIDTH DISPLAY_NAME time_of_day_load 59 | set_parameter_property CONDUIT_DATA_WIDTH TYPE INTEGER 60 | set_parameter_property CONDUIT_DATA_WIDTH UNITS None 61 | set_parameter_property CONDUIT_DATA_WIDTH ALLOWED_RANGES {"64" "96"} 62 | set_parameter_property CONDUIT_DATA_WIDTH DESCRIPTION "" 63 | set_parameter_property CONDUIT_DATA_WIDTH HDL_PARAMETER true 64 | 65 | 66 | # 67 | # display items 68 | # 69 | 70 | 71 | # 72 | # connection point time_of_day_load 73 | # 74 | add_interface time_of_day_load avalon_streaming source 75 | set_interface_property time_of_day_load associatedClock "" 76 | set_interface_property time_of_day_load associatedReset "" 77 | set_interface_property time_of_day_load ENABLED true 78 | set_interface_property time_of_day_load EXPORT_OF "" 79 | set_interface_property time_of_day_load PORT_NAME_MAP "" 80 | set_interface_property time_of_day_load CMSIS_SVD_VARIABLES "" 81 | set_interface_property time_of_day_load SVD_ADDRESS_GROUP "" 82 | 83 | add_interface_port time_of_day_load time_of_day_load_data data Output CONDUIT_DATA_WIDTH 84 | add_interface_port time_of_day_load time_of_day_load_valid valid Output 1 85 | 86 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/eth_rx_timestamp_adapter/eth_rx_timestamp_adapter.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Ethernet RX timestamp adapter IP 9 | // RX Timestamp Adapter for Intel PSG Ethernet IP 10 | // 11 | //**************************************************************************** 12 | 13 | module eth_rx_timestamp_adapter 14 | 15 | ( 16 | input wire clock, 17 | input wire reset, 18 | 19 | //Timestamp input 20 | input timestamp_valid, 21 | input [95:0] timestamp_data, 22 | 23 | //Timestamp AVST Output 24 | output reg aso_timestamp_valid, 25 | output reg [95:0] aso_timestamp, 26 | input aso_timestamp_ready 27 | ); 28 | 29 | /* 30 | * timestamp_fp_valid should be valid for 1 cycle and valid 31 | * only once during a transmit packet 32 | */ 33 | 34 | always@(posedge clock) 35 | begin 36 | if(reset) 37 | begin 38 | aso_timestamp_valid <= 1'b0; 39 | aso_timestamp <= 96'h0; 40 | end 41 | else 42 | begin 43 | if(timestamp_valid) 44 | aso_timestamp <= timestamp_data; 45 | 46 | if(timestamp_valid) 47 | aso_timestamp_valid <= 1'b1; 48 | else if(aso_timestamp_ready) 49 | aso_timestamp_valid <= 1'b0; 50 | 51 | end 52 | end 53 | 54 | endmodule -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/eth_tod_distributor/eth_tod_distributor.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2001-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // eth_tod_distributor 9 | // This component is an ToD distributor IP 10 | //**************************************************************************** 11 | 12 | module eth_tod_distributor #(parameter OUTPUT_PORT_SIZE) ( 13 | //Wirelevel tx_tod_sync_data and rx_tod_sync_data 14 | input [95:0] tod_in, // Avalon streaming sink 15 | output [95:0] tod_out0 , // conduit 16 | output [95:0] tod_out1 , // conduit 17 | output [95:0] tod_out2 , // conduit 18 | output [95:0] tod_out3 , // conduit 19 | output [95:0] tod_out4 , // conduit 20 | output [95:0] tod_out5 , // conduit 21 | output [95:0] tod_out6 , // conduit 22 | output [95:0] tod_out7 , // conduit 23 | output [95:0] tod_out8 , // conduit 24 | output [95:0] tod_out9 , // conduit 25 | output [95:0] tod_out10, // conduit 26 | output [95:0] tod_out11, // conduit 27 | output [95:0] tod_out12, // conduit 28 | output [95:0] tod_out13, // conduit 29 | output [95:0] tod_out14, // conduit 30 | output [95:0] tod_out15, // conduit 31 | output [95:0] tod_out16 // conduit 32 | ); 33 | 34 | assign tod_out0 = tod_in; 35 | assign tod_out1 = tod_in; 36 | assign tod_out2 = tod_in; 37 | assign tod_out3 = tod_in; 38 | assign tod_out4 = tod_in; 39 | assign tod_out5 = tod_in; 40 | assign tod_out6 = tod_in; 41 | assign tod_out7 = tod_in; 42 | assign tod_out8 = tod_in; 43 | assign tod_out9 = tod_in; 44 | assign tod_out10 = tod_in; 45 | assign tod_out11 = tod_in; 46 | assign tod_out12 = tod_in; 47 | assign tod_out13 = tod_in; 48 | assign tod_out14 = tod_in; 49 | assign tod_out15 = tod_in; 50 | assign tod_out16 = tod_in; 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/eth_ts_fingerprint_compare/eth_ts_fingerprint_compare.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Ethernet timestamp fingerprint compare IP 9 | // Timestamp Fingerprint Comparator for Timestamp Filtering 10 | // 11 | //**************************************************************************** 12 | 13 | module eth_ts_fingerprint_compare 14 | ( 15 | input wire clock, 16 | input wire reset, 17 | 18 | //Fingerprint AVST Input 19 | input asi_fingerprint_valid, 20 | input [7:0] asi_fingerprint, 21 | output reg asi_fingerprint_ready, 22 | 23 | //Timestamp AVST Input 24 | input asi_timestamp_fp_valid, 25 | input [103:0] asi_timestamp_fp, 26 | output reg asi_timestamp_fp_ready, 27 | 28 | //Timestamp AVST Output 29 | output reg aso_timestamp_valid, 30 | output [95:0] aso_timestamp, 31 | input aso_timestamp_ready 32 | ); 33 | 34 | assign aso_timestamp = asi_timestamp_fp[95:0]; 35 | 36 | localparam [1:0] IDLE = 2'b00; 37 | localparam [1:0] VALID = 2'b01; 38 | localparam [1:0] ASO_OUT = 2'b10; 39 | localparam [1:0] POP = 2'b11; 40 | 41 | reg [3:0] state, next_state; 42 | reg match; 43 | 44 | always @(posedge clock) 45 | begin 46 | if (reset) 47 | state <= IDLE; 48 | else 49 | state <= next_state; 50 | end 51 | 52 | always @* 53 | begin 54 | case (state) 55 | IDLE: begin 56 | if (asi_fingerprint_valid & asi_timestamp_fp_valid) 57 | next_state <= VALID; 58 | else 59 | next_state <= IDLE; 60 | end 61 | VALID: begin 62 | if (match) 63 | next_state <= ASO_OUT; 64 | else 65 | next_state <= POP; 66 | end 67 | ASO_OUT: begin 68 | if (aso_timestamp_ready) 69 | next_state <= POP; 70 | else 71 | next_state <= ASO_OUT; 72 | end 73 | POP: begin 74 | next_state <= IDLE; 75 | end 76 | endcase 77 | end 78 | 79 | always @(posedge clock) 80 | begin 81 | if (reset) 82 | begin 83 | asi_timestamp_fp_ready <= 1'b0; 84 | asi_fingerprint_ready <= 1'b0; 85 | end 86 | else 87 | begin 88 | if (next_state == POP) 89 | asi_timestamp_fp_ready <= 1'b1; 90 | else 91 | asi_timestamp_fp_ready <= 1'b0; 92 | 93 | if (next_state == POP) 94 | asi_fingerprint_ready <= match; 95 | else 96 | asi_fingerprint_ready <= 1'b0; 97 | end 98 | end 99 | 100 | //aso valid 101 | always @(posedge clock) 102 | begin 103 | if (reset) 104 | aso_timestamp_valid <= 1'b0; 105 | else 106 | if ((state == ASO_OUT) & !aso_timestamp_ready) 107 | aso_timestamp_valid <= 1'b1; 108 | else 109 | aso_timestamp_valid <= 1'b0; 110 | end 111 | 112 | 113 | always @(posedge clock) 114 | begin 115 | if (reset) 116 | match <= 1'b0; 117 | else 118 | if (asi_fingerprint == asi_timestamp_fp[103:96]) 119 | match <= 1'b1; 120 | else 121 | match <= 1'b0; 122 | end 123 | endmodule -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/eth_tx_timestamp_adapter/eth_tx_timestamp_adapter.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Ethernet TX timestamp adapter IP 9 | // TX Timestamp Adapter for Intel PSG Ethernet IP 10 | // 11 | //**************************************************************************** 12 | 13 | module eth_tx_timestamp_adapter 14 | 15 | ( 16 | input wire clock, 17 | input wire reset, 18 | 19 | //Timestamp input 20 | input timestamp_fp_valid, 21 | input [95:0] timestamp_fp_data, 22 | input [7:0] timestamp_fp_fingerprint, 23 | 24 | //Timestamp AVST Output 25 | output reg aso_timestamp_fp_valid, 26 | output reg [103:0] aso_timestamp_fp, 27 | input aso_timestamp_fp_ready 28 | ); 29 | 30 | /* 31 | * timestamp_fp_valid should be valid for 1 cycle and valid 32 | * only once during a transmit packet 33 | */ 34 | 35 | always@(posedge clock) 36 | begin 37 | if(reset) 38 | begin 39 | aso_timestamp_fp_valid <= 1'b0; 40 | aso_timestamp_fp <= 104'h0; 41 | end 42 | else 43 | begin 44 | if(timestamp_fp_valid) 45 | aso_timestamp_fp <= {timestamp_fp_fingerprint,timestamp_fp_data}; 46 | 47 | if(timestamp_fp_valid) 48 | aso_timestamp_fp_valid <= 1'b1; 49 | else if(aso_timestamp_fp_ready) 50 | aso_timestamp_fp_valid <= 1'b0; 51 | 52 | end 53 | end 54 | 55 | endmodule -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/start_tod_sync/start_tod_sync.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2001-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // etile_tod 9 | // This component set 1'b1 to the "start_tod_sync" for ETILE TOD SUBSYSTEM 10 | //**************************************************************************** 11 | 12 | module start_tod_sync( 13 | 14 | output tx_tod_25gbe_start_tod_sync, 15 | output rx_tod_25gbe_start_tod_sync, 16 | output tx_tod_10gbe_start_tod_sync, 17 | output rx_tod_10gbe_start_tod_sync 18 | ); 19 | 20 | // RX & TX TOD's start_tod_sync 21 | assign tx_tod_25gbe_start_tod_sync = 1'b1; 22 | assign rx_tod_25gbe_start_tod_sync = 1'b1; 23 | assign tx_tod_10gbe_start_tod_sync = 1'b1; 24 | assign rx_tod_10gbe_start_tod_sync = 1'b1; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/tod_mux/tod_mux.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // tod_mux.v 9 | // This component is an ToD mux for ETILE 10G / 25G 10 | // sel =0 -> tod10g; sel =1 -> tod25g 11 | //**************************************************************************** 12 | 13 | module tod_mux(tx_tod_out, rx_tod_out, tx_tod10g, rx_tod10g, tx_tod25g, rx_tod25g, sel); 14 | 15 | output [95:0] tx_tod_out; 16 | output [95:0] rx_tod_out; 17 | input [95:0] tx_tod10g; 18 | input [95:0] rx_tod10g; 19 | input [95:0] tx_tod25g; 20 | input [95:0] rx_tod25g; 21 | input sel; 22 | 23 | assign tx_tod_out =(sel)?tx_tod25g:tx_tod10g; 24 | assign rx_tod_out =(sel)?rx_tod25g:rx_tod10g; 25 | 26 | endmodule -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/prefetcher_ts_insert/altera_msgdma_prefetcher_ts_insert.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2022 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // msgdma prefetcher timestamp insert 9 | // Timestamp Insert for Intel PSG MSGDMA Prefetcher IP 10 | // 11 | //**************************************************************************** 12 | 13 | module altera_msgdma_prefetcher_ts_insert ( 14 | clk, 15 | reset, 16 | 17 | snk_response_data, 18 | snk_response_valid, 19 | snk_response_ready, 20 | 21 | snk_timestamp_valid, 22 | snk_timestamp_ready, 23 | snk_timestamp, 24 | 25 | src_response_data, 26 | src_response_valid, 27 | src_response_ready 28 | 29 | ); 30 | 31 | input clk; 32 | input reset; 33 | 34 | input wire snk_response_valid; 35 | output wire snk_response_ready; 36 | input wire [255:0] snk_response_data; 37 | 38 | input wire snk_timestamp_valid; 39 | output wire snk_timestamp_ready; 40 | input wire [95:0] snk_timestamp; 41 | 42 | output wire [255:0] src_response_data; 43 | output wire src_response_valid; 44 | input wire src_response_ready; 45 | 46 | 47 | assign src_response_data[159:0] = snk_response_data[127:0]; 48 | assign src_response_data[255:160] = snk_timestamp[95:0]; 49 | 50 | assign snk_response_ready = src_response_ready; 51 | assign snk_timestamp_ready = src_response_ready; 52 | 53 | assign src_response_valid = snk_response_valid & snk_timestamp_valid; 54 | 55 | endmodule -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/reset_sync/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2014 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/main/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#11 $ 15 | // $Revision: #11 $ 16 | // $Date: 2011/08/09 $ 17 | // $Author: aferrucc $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/custom_ip/sgpio_slave/sgpio_slave.v: -------------------------------------------------------------------------------- 1 | //Filename: sgpio_slave.v 2 | //Anthor: Anna Gu 3 | //Description: synchronized serial interface with four signals, act as slave 4 | //revision: 1.0 5 | //revision history: 21-3-1 6 | 7 | module sgpio_slave ( 8 | input i_rstn, 9 | output[7:0] o_user_sw, //the value of user_sw that slave gets from master 10 | input[7:0] i_user_led, //the value of user_led that slave intends to drive 11 | output o_user_sw_valid, //=1: o_user_sw is the active value driven by master. 12 | output o_miso, //master input slave output of the synchronized serial interface 13 | input i_clk, //clock of the synchronized serial interface 14 | input i_sync, //frame start of the synchronized serial interface, =1: the start of a frame 15 | input i_mosi //master output slave input of the synchronized serial interface 16 | ); 17 | 18 | reg [7:0] S_o_data_shift; 19 | reg [7:0] S_i_data_shift; 20 | reg [7:0] S_o_user_sw; 21 | reg [1:0] S_o_user_sw_valid; 22 | 23 | 24 | assign o_miso = S_o_data_shift[0]; 25 | assign o_user_sw = S_o_user_sw; 26 | assign o_user_sw_valid = S_o_user_sw_valid[1]; 27 | 28 | always @(posedge i_clk or negedge i_rstn) 29 | begin 30 | if(!i_rstn) 31 | S_o_user_sw <= 8'd0; 32 | else if (i_sync) 33 | S_o_user_sw <= S_i_data_shift; 34 | else 35 | S_o_user_sw <= S_o_user_sw; 36 | end 37 | 38 | always @(posedge i_clk or negedge i_rstn) 39 | begin 40 | if(!i_rstn) 41 | S_i_data_shift <= 8'd0; 42 | else 43 | S_i_data_shift <= {i_mosi, S_i_data_shift[7:1]}; 44 | end 45 | 46 | always @(posedge i_clk or negedge i_rstn) 47 | begin 48 | if(!i_rstn) 49 | S_o_user_sw_valid <= 2'b00; 50 | else if (i_sync && (!S_o_user_sw_valid[1])) 51 | S_o_user_sw_valid <= S_o_user_sw_valid + 1'b1; 52 | else 53 | S_o_user_sw_valid <= S_o_user_sw_valid; 54 | end 55 | 56 | always @(posedge i_clk or negedge i_rstn) 57 | begin 58 | if(!i_rstn) 59 | S_o_data_shift <= 8'b11111111; 60 | else if (i_sync) 61 | S_o_data_shift <= i_user_led; 62 | else 63 | S_o_data_shift <= {1'b1, S_o_data_shift[7:1]}; 64 | end 65 | 66 | 67 | endmodule 68 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/fpga_pcie.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for Agilex GHRD. Targeting PCIE component. 9 | # 10 | #**************************************************************************** 11 | 12 | # Clock Group 13 | # create_clock -name PCIE_REFCLK -period 10 [get_ports pcie_refclk_100] 14 | derive_clock_uncertainty 15 | 16 | set_false_path -from [ get_ports {pcie_hip_npor_pin_perst}] 17 | 18 | set_false_path -from {soc_inst|*|axi_bridge_for_acp_128_inst|csr_*} -to {soc_inst|s10_hps|altera_stratix10_hps_inst|*} -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/fpga_pr.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for Agilex GHRD. Targeting PR component. 9 | # 10 | #**************************************************************************** 11 | 12 | # False path to the PIO instances for acknowledgement delay testing only 13 | create_clock -name frz_ack_pio -period 10.000 [get_registers {soc_inst|frz_ack_pio|frz_ack_pio|data_out[0]}] 14 | set_false_path -from [get_clocks {frz_ack_pio}] -to * 15 | set_false_path -from * -to [get_clocks {frz_ack_pio}] 16 | 17 | create_clock -name stop_ack_pio -period 10.000 [get_registers {soc_inst|stop_ack_pio|stop_ack_pio|data_out[0]}] 18 | set_false_path -from [get_clocks {stop_ack_pio}] -to * 19 | set_false_path -from * -to [get_clocks {stop_ack_pio}] 20 | 21 | create_clock -name start_ack_pio -period 10.000 [get_registers {soc_inst|start_ack_pio|start_ack_pio|data_out[0]}] 22 | set_false_path -from [get_clocks {start_ack_pio}] -to * 23 | set_false_path -from * -to [get_clocks {start_ack_pio}] -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/issp_reset.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | #use this tcl script to perform a reset assertion & deassertion to the whole design system for AGILEX GHRD 9 | #the reset assertion and deassertion here are done via ISSP(In System Source & Probe) after device is programmed successfully 10 | # 11 | #**************************************************************************** 12 | 13 | set issp [lindex [get_service_paths issp] 0] 14 | set issp_m [claim_service issp $issp claimGroup] 15 | 16 | set current_source_data [issp_read_source_data $issp_m] 17 | puts "src_reset_n value: $current_source_data" 18 | #assert reset 19 | puts "assert src_reset_n via issp" 20 | set source_data 0x0 21 | issp_write_source_data $issp_m $source_data 22 | set current_source_data [issp_read_source_data $issp_m] 23 | puts "src_reset_n value: $current_source_data" 24 | after 500 25 | puts "deassert src_reset_n via issp" 26 | #deassert reset 27 | set source_data 0x1 28 | issp_write_source_data $issp_m $source_data 29 | set current_source_data [issp_read_source_data $issp_m] 30 | puts "src_reset_n value: $current_source_data" 31 | 32 | close_service issp $issp_m 33 | puts "\nInfo: Closed ISSP Service\n\n" -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/pin_assign_agilex_emif.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This file contains pin assignments of EMIF port to suite different boards 9 | # Currently planned board of support are AGILEX SoC devkit and PE Board revC 10 | 11 | # Pin Support Matrix for AGILEX SoC Devkit 12 | # note that we have to perform a logical remapping of pins to support the HPS hard pinout. 13 | # The DQ* Bits within each byte lane can be swizzled between the DevKit and UDV. This has no impact on GHRD. The GHRD can just use the example design/pinout below. 14 | # 15 | #**************************************************************************** 16 | 17 | ## -------------------------- 18 | # "pin_matrix" is set in "board_${board}_pin_assignment_table.tcl" 19 | ## -------------------------- 20 | 21 | if {$hps_emif_en} { 22 | if {$board == "devkit_fp82"} { 23 | # FP82 GHRD unable to test ECC feature 24 | set key fp82 25 | 26 | } else { 27 | set ranks r1 28 | set width $hps_emif_width 29 | set ecc $hps_emif_ecc_en 30 | 31 | if {$ecc} { 32 | incr width 8 33 | } 34 | set key "x${width}_$ranks" 35 | } 36 | 37 | 38 | # Search for key in the first line 39 | set key_line [lindex $pin_matrix 0] 40 | set idx [lsearch $key_line $key] 41 | 42 | if {$idx < 0} { 43 | error "Could not locate configuration $key for EMIF generation" 44 | } 45 | 46 | set mem_type_idx [lsearch $key_line "MEM"] 47 | 48 | if {$mem_type_idx < 0} { 49 | error "Could not locate memory type specifier in pinout matrix for EMIF generation" 50 | } 51 | 52 | puts "key = $key" 53 | puts "board = $board" 54 | puts "mem_type = $hps_emif_type" 55 | 56 | # Now add all items 57 | set skip_first 1 58 | foreach key_line $pin_matrix { 59 | if {$skip_first} { 60 | set skip_first 0 61 | } else { 62 | set pin [lindex $key_line $idx] 63 | set mem_type [lindex $key_line $mem_type_idx] 64 | 65 | if {$pin != "unused" && (($mem_type == $hps_emif_type) || ($mem_type == "both"))} { 66 | set_location_assignment $pin -to [lindex $key_line 0] 67 | puts "Setting: set_location_assignment $pin -to [lindex $key_line 0]" 68 | } 69 | } 70 | } 71 | } 72 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/sgmii_timing.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for Agilex HPS SGMII GHRD. 9 | # 10 | #**************************************************************************** 11 | 12 | set_false_path -from * -to [get_keepers {*|sgmii_debug_status_pio|altera_avalon_pio_inst|d1_data_in[*]}] 13 | set_false_path -from * -to [get_keepers {*|sgmii_debug_status_pio|altera_avalon_pio_inst|readdata[*]}] 14 | 15 | # False path to COL for duplex SGMII Mode 16 | set_false_path -from [get_keepers -no_duplicates {soc_inst|*|altera_eth_tse_inst|i_tse_pcs_0|altera_tse_top_1000_base_x_inst|U_SGMII|U_COL|state}] -to [get_keepers -no_duplicates {soc_inst|agilex_hps|*|s2f_module~soc_hps_wrapper/s0_b_28__vio_lab_core_periphery__clk[*].reg}] 17 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/software/hps_debug/Makefile: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2020 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Makefile for HPS Wipe Firmware 9 | # 10 | ################################################ 11 | 12 | #COMPILER ?= GCC 13 | #COMPILER ?= ARMCLANG 14 | 15 | WHICH = which 16 | 17 | #Check GCC Version 18 | GCCVERSION_7 := $(shell $(WHICH) aarch64-linux-gnu-gcc 2>/dev/null) 19 | GCCVERSION_9 := $(shell $(WHICH) aarch64-none-linux-gnu-gcc 2>/dev/null) 20 | 21 | ifneq ($(GCCVERSION_9),) 22 | CROSS_COMPILE ?= "aarch64-none-linux-gnu-" 23 | else ifneq ($(GCCVERSION_7),) 24 | CROSS_COMPILE ?= "aarch64-linux-gnu-" 25 | else 26 | CROSS_COMPILE = "NOT_FOUND" 27 | endif 28 | 29 | ifndef COMPILER 30 | #If no COMPILER defined Try GCC First, then try ARMCLANG 31 | 32 | ifneq ($(CROSS_COMPILE), "NOT_FOUND") 33 | include Makefile_GCC.inc 34 | else ifneq ($(shell $(WHICH) armclang 2>/dev/null),) 35 | include Makefile_ARMCLANG.inc 36 | else 37 | $(error "ERROR :: GCC or ARMCLANG Compiler not found, please install either one of the compiler to continue") 38 | endif 39 | 40 | else ifeq ("$(COMPILER)","GCC") 41 | 42 | ifneq ($(CROSS_COMPILE), "NOT_FOUND") 43 | include Makefile_GCC.inc 44 | else 45 | $(error "ERROR :: COMPILER=GCC is chosen, please install gcc compiler to continue or try COMPILER=ARMCC") 46 | endif 47 | 48 | else ifeq ("$(COMPILER)","ARMCLANG") 49 | 50 | ifneq ("$(shell $(WHICH) armclang 2>/dev/null)", "") 51 | include Makefile_ARMCLANG.inc 52 | else 53 | $(error "ERROR :: COMPILER=ARMCLANG is chosen, please install arm compiler to continue or try COMPILER=GCC") 54 | endif 55 | 56 | else 57 | 58 | $(error "ERROR :: Invalid Compiler option, choose only GCC or ARMCLANG") 59 | 60 | endif 61 | 62 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/software/hps_debug/Makefile_ARMCLANG.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Makefile for HPS Wipe Firmware ARMCLANG 9 | # 10 | ################################################ 11 | 12 | AS := armasm 13 | CC := armclang 14 | LD := armlink 15 | OD := fromelf 16 | OBJCOPY := objcopy 17 | 18 | TARGET_PROCESSOR := aarch64-arm-none-eabi 19 | 20 | AXF := hps_debug.axf 21 | IHEX := $(patsubst %.axf,%.ihex,$(AXF)) 22 | OBJDUMP_FILE := $(patsubst %.axf,%.objdump,$(AXF)) 23 | 24 | SRC := hps_debug.S 25 | SCATTER_FILE := scatter.scat 26 | 27 | CC_FLAGS := -g --target=$(TARGET_PROCESSOR) -mcpu=Cortex-A53 28 | LD_FLAGS := --scatter=$(SCATTER_FILE) --entry=0xffe00000 29 | 30 | OBJ.S := $(patsubst %.S,%.o,$(filter %.S,$(SRC))) 31 | 32 | OBJ := $(OBJ.S) 33 | 34 | RM := rm -rf 35 | 36 | .PHONY: all 37 | all: $(AXF) $(IHEX) $(OBJDUMP_FILE) 38 | 39 | clean: 40 | $(RM) *.o 41 | $(RM) $(AXF) $(IHEX) $(OBJDUMP_FILE) 42 | 43 | $(AXF): $(OBJ) $(SCATTER_FILE) 44 | $(LD) $(LD_FLAGS) $(OBJ) -o $@ 45 | 46 | $(OBJDUMP_FILE): %.objdump: %.axf 47 | $(OD) -s -t --disassemble $< > $@ 48 | 49 | $(IHEX): %.ihex: %.axf 50 | $(OBJCOPY) -O ihex $< $@ 51 | 52 | $(OBJ.S): %.o: %.S 53 | $(CC) -c $(CC_FLAGS) $< -o $@ 54 | 55 | 56 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/software/hps_debug/Makefile_GCC.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2020 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Makefile for HPS Wipe Firmware GCC 9 | # 10 | ################################################ 11 | 12 | CC:= $(CROSS_COMPILE)as 13 | OBJCOPY := $(CROSS_COMPILE)objcopy 14 | OBJDUMP := $(CROSS_COMPILE)objdump 15 | 16 | SRC := hps_debug.S 17 | ENTRY_POINT:=0xffe00000 18 | 19 | IHEX := $(patsubst %.S,%.ihex,$(SRC)) 20 | ELF := $(patsubst %.S,%.elf,$(SRC)) 21 | BIN := $(patsubst %.S,%.bin,$(SRC)) 22 | OBJDUMP_FILE = $(patsubst %.S,%.objdump,$(SRC)) 23 | 24 | OBJ_FLAG := -I binary -O ihex --change-address $(ENTRY_POINT) 25 | 26 | RM := rm -rf 27 | 28 | .PHONY: all 29 | all: $(ELF) $(BIN) $(IHEX) $(OBJDUMP_FILE) 30 | 31 | clean: 32 | $(RM) $(ELF) $(IHEX) $(BIN) $(OBJDUMP_FILE) 33 | 34 | $(ELF): $(SRC) 35 | $(CC) $(SRC) -o $@ 36 | 37 | $(BIN): $(ELF) 38 | $(OBJCOPY) -O binary $< $@ 39 | 40 | $(IHEX): $(BIN) 41 | $(OBJCOPY) $(OBJ_FLAG) $< $@ 42 | 43 | $(OBJDUMP_FILE): $(ELF) 44 | $(OBJDUMP) --disassemble $< > $@ 45 | 46 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/software/hps_debug/README.md: -------------------------------------------------------------------------------- 1 | # HPS Content Wipe Program 2 | 3 | The HPS content wipe program is a small program that is invoked by SDM when there is a security breach event detected or during a cold reset. The intention of this program is to clear HPS content, especially in cache. This memory might contain sensitive data. 4 | 5 | ## How to build 6 | User can build the HPS wipe with two different compilers, which are GCC and ARMCLANG 7 | 8 | ### GCC compiler 9 | > $make COMPILER=GCC 10 | 11 | User can specify the CROSS_COMPILE option, since in linaro version 9, the binary name of the compiler changed. 12 | > $make COMPILER=GCC CROSS_COMPILE=aarch64-linux-gnu- 13 | > $make COMPILER=GCC CROSS_COMPILE=aarch64-none-linux-gnu- 14 | 15 | ### ARMCLANG Compiler 16 | > $make COMPILER=ARMCLANG 17 | 18 | ## To clean 19 | > $make clean COMPILER=GCC 20 | > $make clean COMPILER=ARMCLANG 21 | 22 | 23 | ## Prerequisite 24 | ### Compile with GCC 25 | Please download GCC compiler from 26 | https://releases.linaro.org/components/toolchain/binaries/7.5-2019.12/aarch64-linux-gnu/ 27 | 28 | ### Compile with ARMCLANG 29 | Please download ARM Development Studio from 30 | https://www.arm.com/ 31 | 32 | ### For Windows user 33 | Please download MSYS2 from 34 | https://www.msys2.org/ 35 | 36 | ### Export Environment 37 | Please export the installation path of the bin folder for the compilers 38 | Examples: 39 | 40 | GCC 41 | > export PATH=$PATH:/c/gcc-linaro-7.5.0-2019.12-i686-mingw32_aarch64-linux-gnu/gcc/bin 42 | 43 | ARMCLANG 44 | > export PATH=$PATH:/c/Program\ Files/Arm/Development\ Studio\ 2021.0/sw/ARMCompiler6.16/bin 45 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/software/hps_debug/hps_debug.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/altera-opensource/ghrd-socfpga/e3bd58392f0b70b470c3afe67fd5e45f9ac5b00b/agilex_soc_devkit_ghrd/software/hps_debug/hps_debug.S -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/software/hps_debug/scatter.scat: -------------------------------------------------------------------------------- 1 | OCRAM 0xFFE00000 0x20000 2 | { 3 | APP_CODE +0 ABSOLUTE 4 | { 5 | * (+RO, +RW, +ZI) 6 | } 7 | 8 | ARM_LIB_STACKHEAP +0 ALIGN 64 EMPTY 0x4000 {} 9 | EL3_STACKS +0 ALIGN 64 EMPTY 0x1000 {} 10 | } 11 | -------------------------------------------------------------------------------- /agilex_soc_devkit_ghrd/update_sysid.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script update the GHRD SYSID 9 | # To execute this script using qsys-script 10 | # qsys-script --qpf=none --script=update_sysid.tcl --system-file= 11 | # 12 | #**************************************************************************** 13 | package require -exact qsys 18.1 14 | 15 | set epoch_time [clock seconds] 16 | set sysid_type "altera_avalon_sysid_qsys" 17 | set generic_component_type "altera_generic_component" 18 | set dot_ip_extension ".ip" 19 | set found_sysid_ip_files [list] 20 | 21 | set qsys_file_path [get_module_property FILE] 22 | set qsys_file_directory [file dirname ${qsys_file_path}] 23 | 24 | foreach inst [get_instances] { 25 | set inst_type [get_instance_property $inst CLASS_NAME] 26 | #puts "$inst_type" 27 | if {$inst_type==$generic_component_type} { 28 | load_component $inst 29 | set component_file [get_instantiation_property IP_FILE] 30 | set extension [file extension ${component_file}] 31 | #puts "$extension" 32 | if {$extension==$dot_ip_extension} { 33 | set type [get_component_property CLASS_NAME] 34 | #puts "$inst: $type" 35 | if {$type==$sysid_type} { 36 | set absolute_ip_file [file join ${qsys_file_directory} ${component_file}] 37 | #puts $absolute_ip_file 38 | lappend found_sysid_ip_files ${absolute_ip_file} 39 | } 40 | } 41 | } 42 | } 43 | 44 | foreach sysid $found_sysid_ip_files { 45 | load_system ${sysid} 46 | #puts [get_module_property GENERATION_ID] 47 | set_module_property GENERATION_ID $epoch_time 48 | #puts [get_module_property GENERATION_ID] 49 | validate_system 50 | save_system ${sysid} 51 | } 52 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/README.md: -------------------------------------------------------------------------------- 1 | # Cyclone V (CV) Golden Hardware Reference Design (GHRD) Build Scripts 2 | 3 | CV GHRD is a reference design for Intel CV System On Chip (SoC) FPGA. The GHRD works together with Golden Software Reference design (GSRD) for complete solution to boot Uboot and Linux with Intel SoC Development board. 4 | 5 | This reference design demonstrating the following system integration between Hard Processor System (HPS) and FPGA IPs: 6 | - Hard Processor System enablement and configuration 7 | - HPS Peripheral and I/O (eg, NAND, SD/MMC, EMAC, USB, SPI, I2C, UART, and GPIO) 8 | - HPS Clock and Reset 9 | - HPS FPGA Bridge and Interrupt 10 | - HPS EMIF configuration 11 | - System integration with FPGA IPs 12 | - SYSID 13 | - Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs) 14 | - FPGA On-Chip Memory 15 | - PCIe RootPort IP 16 | 17 | This repository hosts build scripts for S10 GHRD. 18 | 19 | ## Dependency 20 | * Intel Quartus Prime 24.1std 21 | * Supported Board 22 | - Intel Cyclone V SoC Development Kit 23 | 24 | ## Tested Platform for the GHRD Make flow 25 | * Red Hat Enterprise Linux Server release 6.10 26 | 27 | ## Available Make Target: 28 | The GHRD is built with Makefile. Here are the supported Make Targets: 29 | ********************* 30 | * Target: `generate_from_tcl` 31 | * Generate the Quartus Project source files from tcl script source 32 | ********************* 33 | * Target: `help` 34 | * Displays this info (i.e. the available targets) 35 | ********************* 36 | * Target: `program_fpga` 37 | * Quartus program sof to your attached dev board 38 | ********************* 39 | * Target: `qsys_edit` 40 | * Launch Platform Designer GUI 41 | ********************* 42 | * Target: `quartus_edit` 43 | * Launch Quartus Prime Standard GUI 44 | ********************* 45 | * Target: `scrub_clean` 46 | * Restore design to its barebones state 47 | ********************* 48 | * Target: `sof` 49 | * QSys generate & Quartus compile this design 50 | ********************* 51 | * Target: `tgz` 52 | * Create a tarball with the barebones source files that comprise this design 53 | ********************* 54 | 55 | ## Build Steps 56 | 1) Customize the GHRD settings in Makefile. [Not necessary if the default option is good] 57 | 2) Generate the Quartus Project and source files. 58 | - $ make `generate_from_tcl` 59 | 3) Compile Quartus Project and generate the configuration file 60 | - $ `make sof` or $ `make all` 61 | 62 | ## GHRD Customization in Makefile 63 | - `ENABLE_PCIE` : Enable Gen1x4 PCIE Design. 64 | - 0 (Default), 1 65 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/create_ghrd_top.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script generates the top level RTL for the GHRD 9 | # to use this script, 10 | # example command to execute this script file 11 | # tclsh create_ghrd_top.tcl 12 | # fpga_pcie : enable PCIe in FPGA 13 | # 1 = enable, or 14 | # 0 = disable 15 | # 16 | # example command to execute this script file 17 | # tclsh create_ghrd_qsys.tcl hps_sdram D9PZN 18 | # 19 | #**************************************************************************** 20 | 21 | 22 | source $::env(QUARTUS_ROOTDIR)/../ip/altera/common/hw_tcl_packages/altera_terp.tcl 23 | 24 | #package require altera_terp 25 | 26 | source ./design_config.tcl 27 | 28 | proc show_cmd_args {} { 29 | global PCIE_ENABLE 30 | 31 | foreach {name val} $::argv { 32 | puts "-> Accepted parameter: $name, \tValue: $val" 33 | if {$name == "fpga_pcie"} { 34 | set PCIE_ENABLE $val 35 | #puts "$PCIE_ENABLE is inserted" 36 | } 37 | } 38 | 39 | } 40 | show_cmd_args 41 | 42 | 43 | # path to the TERP template 44 | set template_path "top_level_template.v.terp" 45 | # file handle for template 46 | set template_fh [open $template_path] 47 | # template contents 48 | set template [read $template_fh] 49 | # we are done with the file so we should close it 50 | close $template_fh 51 | 52 | # construct parameters value used in terp file 53 | # set param(SYS_TOP_NAME) $SYS_TOP_NAME 54 | # set param(QSYS_NAME) $QSYS_NAME 55 | set param(PCIE_ENABLE) $PCIE_ENABLE 56 | 57 | 58 | set content [altera_terp $template param] 59 | set fo [open "./ghrd_top.v" "w"] 60 | puts $fo $content 61 | close $fo 62 | 63 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/design_config.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2013-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # USAGE OF THIS FILE 8 | # ------------------ 9 | # Parameters set in this file are served as default value to configure GHRD for generation. 10 | # Higher level sripts that call upon create_ghrd_*.tcl can over-write value of parameters 11 | # by arguments to be passed in during execution of script. 12 | # 13 | #**************************************************************************** 14 | set QSYS_NAME soc_system 15 | set QUARTUS_NAME soc_system 16 | set SYS_TOP_NAME ghrd_top 17 | set DEVICE_FAMILY "CYCLONEV" 18 | set FPGA_DEVICE 5CSXFC6D6F31C6 19 | 20 | # # 21 | ################################################# 22 | 23 | ################################################# 24 | # GHRD features enable # 25 | 26 | # existance of PCIe 27 | set PCIE_ENABLE 0 28 | 29 | 30 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/ds5/altera_avalon_pio_led.ds: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright Altera 2013 3 | # All Rights Reserved 4 | # File: altera_avalon_pio_led.ds 5 | # 6 | 7 | # Turn LEDS OFF 8 | define altera_avalon_pio_leds_off 9 | set var $Peripherals::$altera_avalon_pio_led_pio_s1::$altera_avalon_pio_led_pio_s1_DATA = 0xffffffff 10 | end 11 | 12 | # Turn LEDS ON 13 | define altera_avalon_pio_leds_on 14 | set var $Peripherals::$altera_avalon_pio_led_pio_s1::$altera_avalon_pio_led_pio_s1_DATA = 0x0 15 | end -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/fpga_pcie.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2016-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for CV GHRD. Targeting PCIE component. 9 | # 10 | #**************************************************************************** 11 | #create_clock -period "125 MHz" -name {coreclk} {*coreclk*} 12 | # False path for reset inputs 13 | set_false_path -from [get_ports pcie_npor_pin_perst] -to * 14 | set_false_path -from [get_ports pcie_npor_npor] -to * 15 | #False path for reset output 16 | set_false_path -from * -to [get_ports pcie_perstn_out] 17 | set_output_delay -clock {fpga_clk_50} -add_delay 10 [get_ports pcie_perstn_out] 18 | ############################################################################ 19 | # derive_pll_clock is used to calculate all clock derived from PCIe refclk 20 | # the derive_pll_clocks and derive clock_uncertainty should only 21 | # be applied once across all of the SDC files used in a project 22 | create_clock -period "100MHz" -name {refclk_pci_express} {*refclk_*} 23 | derive_pll_clocks -create_base_clocks 24 | derive_clock_uncertainty 25 | ############################################################################## 26 | # PHY IP reconfig controller constraints 27 | # Set reconfig_xcvr clock 28 | # this line will likely need to be modified to match the actual clock pin name 29 | # used for this clock, and also changed to have the correct period set for the actually used clock 30 | create_clock -period "125 MHz" -name {reconfig_xcvr_clk} {*reconfig_xcvr_clk*} 31 | 32 | ###################################################################### 33 | # HIP Soft reset controller SDC constraints 34 | set_false_path -to [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]] 35 | set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*] 36 | 37 | # HIP testin pins SDC constraints 38 | set_false_path -from [get_pins -compatibility_mode *hip_ctrl*] 39 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/ghrd_reset.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2013-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample HPS reset trigger script 9 | # to run this script using quartus_stp 10 | # quartus_stp -t ghrd_reset.tcl --cable-name <> --device-index <> --cold-reset 11 | # 12 | #**************************************************************************** 13 | 14 | package require cmdline 15 | 16 | # Command line processing 17 | set parameters { 18 | {-cable-name.arg "" "Name of JTAG cable connected to system to reset. Defaults to value of $BOARD_CABLE."} 19 | {-device-index.arg "" "Device index of the FPGA in JTAG chain. Defaults to value of $BOARD_DEVICE_INDEX."} 20 | {-cold-reset "Cold reset the system. This is the default operation."} 21 | {-warm-reset "Warm reset the system."} 22 | {-debug-reset "Reset the system's debug core."} 23 | } 24 | array set opts [cmdline::getoptions argv $parameters] 25 | 26 | if {[string length $opts(-cable-name)] == 0} { 27 | if {[info exists ::env(BOARD_CABLE)]} { 28 | array set opts [list -cable-name $::env(BOARD_CABLE)] 29 | } else { 30 | puts stderr "Unable to determine board cable to use for reset. Do you have a board resource, or have you specified --cable-name?" 31 | exit 1 32 | } 33 | } 34 | 35 | if {[string length $opts(-device-index)] == 0} { 36 | if {[info exists ::env(BOARD_DEVICE_INDEX)]} { 37 | array set opts [list -device-index $::env(BOARD_DEVICE_INDEX)] 38 | } else { 39 | puts stderr "Unable to determine FPGA device index to use for reset. Do you have a board resource, or have you specified --device-index?" 40 | exit 1 41 | } 42 | } 43 | 44 | if {!$opts(-debug-reset) && !$opts(-warm-reset)} { 45 | # If no operation specified, default to cold reset. 46 | array set opts {-cold-reset 1} 47 | } 48 | 49 | # Helper functions 50 | proc get_device_name { cable_name device_index } { 51 | foreach device_name [get_device_names -hardware_name $cable_name] { 52 | if { [string match "@$device_index:*" $device_name] } { 53 | return $device_name 54 | } 55 | } 56 | } 57 | 58 | proc get_reset_source_instance { cable_name device_name } { 59 | foreach instance [get_insystem_source_probe_instance_info -hardware_name $cable_name -device_name $device_name] { 60 | if { [string match "RST" [lindex $instance 3]] } { 61 | return [lindex $instance 0] 62 | } 63 | } 64 | } 65 | 66 | proc source_write_sequence { cable_name device_name source_instance data_sequence } { 67 | start_insystem_source_probe -hardware_name $cable_name -device_name $device_name 68 | 69 | foreach value $data_sequence { 70 | write_source_data -instance_index $source_instance -value $value -value_in_hex 71 | } 72 | 73 | end_insystem_source_probe 74 | } 75 | 76 | # Look up additional parameters 77 | set device_name [get_device_name $opts(-cable-name) $opts(-device-index)] 78 | set source_instance [get_reset_source_instance $opts(-cable-name) $device_name] 79 | if {![info exists device_name] && ![info exists source_instance]} { 80 | puts stderr "Unable to find device or source index to drive reset. Is the FPGA configured with a design that allows HPS reset?" 81 | exit 1 82 | } 83 | 84 | # Finally, do the reset(s) 85 | if {$opts(-debug-reset)} { 86 | source_write_sequence $opts(-cable-name) $device_name $source_instance {0x0 0x4} 87 | } 88 | 89 | if {$opts(-warm-reset)} { 90 | source_write_sequence $opts(-cable-name) $device_name $source_instance {0x0 0x2} 91 | } 92 | 93 | if {$opts(-cold-reset)} { 94 | source_write_sequence $opts(-cable-name) $device_name $source_instance {0x0 0x1} 95 | } 96 | 97 | exit 0 98 | 99 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // debouce 9 | // 10 | //**************************************************************************** 11 | 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Intel Edge Detector 9 | // 10 | //**************************************************************************** 11 | 12 | module altera_edge_detector #( 13 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 14 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 15 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 16 | ) ( 17 | input clk, 18 | input rst_n, 19 | input signal_in, 20 | output pulse_out 21 | ); 22 | 23 | localparam IDLE = 0, ARM = 1, CAPT = 2; 24 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 25 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 26 | 27 | reg [1:0] state, next_state; 28 | reg pulse_detect; 29 | wire busy_pulsing; 30 | 31 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 32 | assign reset_qual_n = rst_n | busy_pulsing; 33 | 34 | generate 35 | if (PULSE_EXT > 1) begin: pulse_extend 36 | integer i; 37 | reg [PULSE_EXT-1:0] extend_pulse; 38 | always @(posedge clk or negedge reset_qual_n) begin 39 | if (!reset_qual_n) 40 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 41 | else begin 42 | for (i = 1; i < PULSE_EXT; i = i+1) begin 43 | extend_pulse[i] <= extend_pulse[i-1]; 44 | end 45 | extend_pulse[0] <= pulse_detect; 46 | end 47 | end 48 | assign pulse_out = |extend_pulse; 49 | end 50 | else begin: single_pulse 51 | reg pulse_reg; 52 | always @(posedge clk or negedge reset_qual_n) begin 53 | if (!reset_qual_n) 54 | pulse_reg <= 1'b0; 55 | else 56 | pulse_reg <= pulse_detect; 57 | end 58 | assign pulse_out = pulse_reg; 59 | end 60 | endgenerate 61 | 62 | always @(posedge clk) begin 63 | if (!rst_n) 64 | state <= IDLE; 65 | else 66 | state <= next_state; 67 | end 68 | 69 | // edge detect 70 | always @(*) begin 71 | next_state = state; 72 | pulse_detect = 1'b0; 73 | case (state) 74 | IDLE : begin 75 | pulse_detect = 1'b0; 76 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 77 | else next_state = IDLE; 78 | end 79 | ARM : begin 80 | pulse_detect = 1'b0; 81 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 82 | else next_state = ARM; 83 | end 84 | CAPT : begin 85 | pulse_detect = 1'b1; 86 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 87 | else next_state = IDLE; 88 | end 89 | default : begin 90 | pulse_detect = 1'b0; 91 | next_state = IDLE; 92 | end 93 | endcase 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /cv_soc_devkit_ghrd/ip/reset_synchronizer/reset_sync_block.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2018-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for custom_reset_synchronizer 9 | # 10 | #**************************************************************************** 11 | 12 | #these constraints cut the asynchronous clear path into both pipelines inside the synchronizer block 13 | #set_false_path -to [get_pins -compatibility_mode -nocase -nowarn *|reset_sync_block|synchronizer_reg*|aclr] 14 | #set_false_path -to [get_pins -compatibility_mode -nocase -nowarn *|reset_sync_block|output_pipeline_reg*|aclr] 15 | 16 | #these constraints cut the synchronous clear path into both pipelines inside the synchronizer block 17 | #set_false_path -to [get_pins -compatibility_mode -nocase -nowarn *|reset_sync_block|synchronizer_reg*|sclr] 18 | #set_false_path -to [get_pins -compatibility_mode -nocase -nowarn *|reset_sync_block|output_pipeline_reg*|sclr] 19 | 20 | #Since the synchronizer will resync the reset input we are cutting the input reset into the resync register. 21 | set_false_path -to [get_pins -compatibility_mode -nocase -nowarn *|reset_sync_block*|synchronizer_reg*] 22 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/altera-opensource/ghrd-socfpga/e3bd58392f0b70b470c3afe67fd5e45f9ac5b00b/requirements.txt -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/add_sdc_post_qsys.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script generates the Partial Reconfiguration Revision for the PR GHRD. 9 | # To execute this script using quartus_sh for generating PR revision QSF accordingly 10 | # quartus_sh --script=add_sdc_post_qsys.tcl -projectname $(QUARTUS_BASE) -revision $(QUARTUS_BASE_REVISION) -hps_enable_sgmii $(HPS_ENABLE_SGMII) -hps_enable_10gbe $(HPS_ENABLE_10GbE) 11 | # 12 | #**************************************************************************** 13 | 14 | package require cmdline 15 | 16 | set options {\ 17 | { "projectname.arg" "" "Project name" } \ 18 | { "hps_enable_sgmii.arg" "" "HPS MGE ENABLE" } \ 19 | { "hps_enable_10gbe.arg" "" "HPS MGE 10GbE 1588 ENABLE" } 20 | } 21 | array set opts [::cmdline::getoptions quartus(args) $options] 22 | 23 | project_open $opts(projectname) -current_revision 24 | 25 | if {$opts(hps_enable_sgmii) == 1} { 26 | set_global_assignment -name SDC_FILE fpga_mge.sdc 27 | } 28 | 29 | if {$opts(hps_enable_10gbe) == 1} { 30 | set_global_assignment -name SDC_FILE fpga_mge_10g.sdc 31 | } 32 | project_close -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/construct_s10_emif.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This file contains S10 HPS EMIF configuration and export of signals/ports 9 | # Tentatively, planned support to S10 SoC Devkit and S10 PE board revC 10 | # DDR4 is currently planned for both boards stated above, DDR3 is also supported on the devkit. 11 | # This file will be source by GHRD construct_hps.tcl 12 | 13 | #**************************************************************************** 14 | source ./utils.tcl 15 | 16 | if {$hps_emif_en == 1} { 17 | set total_hps_emif_width $hps_emif_width 18 | if {$hps_emif_ecc_en} { 19 | incr total_hps_emif_width 8 20 | } 21 | } 22 | if {$fpga_emif_en == 1} { 23 | set total_fpga_emif_width $fpga_emif_width 24 | if {$fpga_emif_ecc_en} { 25 | incr total_fpga_emif_width 8 26 | } 27 | } 28 | 29 | set emif_configuration_file "./board/emif_configuration_${board}.tcl" 30 | if {[file exist $emif_configuration_file]} { 31 | source $emif_configuration_file 32 | } else { 33 | error "$emif_configuration_file not exist!! Please make sure the board settings files are included in folder ./board/" 34 | } 35 | 36 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/create_pr_revision.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script generates the Partial Reconfiguration Revision for the PR GHRD. 9 | # To execute this script using quartus_sh for generating PR revision QSF accordingly 10 | # quartus_sh --script=create_pr_revision.tcl -projectname $(QUARTUS_BASE) -revision $(QUARTUS_BASE_REVISION) -pr_revision $(PR_REV) -pr_partition $(QSYS_SUBSYS_PR) 11 | # 12 | #**************************************************************************** 13 | 14 | package require cmdline 15 | 16 | source ./arguments_solver.tcl 17 | 18 | set options {\ 19 | { "projectname.arg" "" "Project name" } \ 20 | { "revision.arg" "" "Revision name" } \ 21 | { "pr_revision.arg" "" "PR Revision name" } \ 22 | { "revision_type.arg" "" "Revision type" } \ 23 | { "pr_partition.arg" "" "PR Partition name" } 24 | { "pr_hierarchy.arg" "" "PR Hierarchy name" } 25 | } 26 | array set opts [::cmdline::getoptions quartus(args) $options] 27 | 28 | if {[project_exists $opts(projectname)]} { 29 | if {[string equal "" $opts(revision)]} { 30 | project_open $opts(projectname) -current_revision 31 | } else { 32 | project_open $opts(projectname) -revision $opts(revision) 33 | } 34 | } else { 35 | post_message -type error "Project $opts(projectname) does not exist" 36 | exit 37 | } 38 | set base_revision $opts(revision) 39 | set pr_revision $opts(pr_revision) 40 | set revision_type $opts(revision_type) 41 | set pr_partition $opts(pr_partition) 42 | set pr_hierarchy $opts(pr_hierarchy) 43 | 44 | ################################################################################ 45 | # Partial Reconfiguration System 46 | ################################################################################ 47 | namespace eval create_pr_revision { 48 | ################################################################################ 49 | # Core procs 50 | ################################################################################ 51 | 52 | ################################################################################ 53 | # Usage: 54 | # create_pr_revision::create_revision -reconfigurable 55 | ################################################################################ 56 | proc create_revision { typeopt revision base } { 57 | global pr_partition 58 | global pr_hierarchy 59 | 60 | # Error checking 61 | if {![::revision_exists $base]} { 62 | ::post_message -type error "Revision \"$base\" does not exist. Specify a valid base revision for the project." 63 | return 0 64 | } 65 | 66 | if [::revision_exists $revision] { 67 | ::post_message -type error "Revision \"$revision\" already exist. Specify a new reconfigurable revision for the project." 68 | return 0 69 | } 70 | 71 | # Option processing 72 | set type {} 73 | if {$typeopt == "-implementation"} { 74 | set type "PR_IMPL" 75 | } else { 76 | ::post_message -type error "Invalid project revision type \"$type\" specified." 77 | return 0 78 | } 79 | 80 | if {$typeopt == "-implementation"} { 81 | # Extract the reconfigurable partitions from the base revision 82 | set curr_revision [get_current_revision] 83 | ::set_current_revision $base 84 | 85 | ::create_revision -based_on $base -set_current $revision 86 | 87 | set_global_assignment -name REVISION_TYPE PR_IMPL 88 | set_instance_assignment -name QDB_FILE_PARTITION base_static.qdb -to | 89 | set_global_assignment -name ENABLE_SIGNALTAP OFF 90 | set_instance_assignment -name ENTITY_REBINDING $pr_partition -to $pr_hierarchy 91 | } 92 | } 93 | } 94 | 95 | create_pr_revision::create_revision -implementation $pr_revision $base_revision 96 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/ack_delay_logic/ack_delay_logic.sv: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2016-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // ack delay logic 9 | // 10 | //**************************************************************************** 11 | 12 | module ack_delay_logic ( 13 | input wire [31:0] delay_ack_pio, 14 | input wire ack_in, 15 | output wire ack_delay_out, 16 | input wire clk, 17 | input wire reset 18 | ); 19 | 20 | wire ack_loopback_delay_ver; 21 | reg [1:0] state, next_state; 22 | reg [31:0] ack_delay_counter; 23 | reg start_ack_count; 24 | reg en_ack_loopback; 25 | reg reset_ack_count; 26 | 27 | localparam [1:0] IDLE = 2'b00; 28 | localparam [1:0] ACK_DELAY_COUNT = 2'b01; 29 | localparam [1:0] ENABLE_ACK_LOOPBACK = 2'b10; 30 | localparam [1:0] RESET_ACK_DELAY_COUNT = 2'b11; 31 | 32 | always @(posedge clk or posedge reset) begin 33 | if (reset) begin 34 | ack_delay_counter <= 32'd0; 35 | end 36 | else begin 37 | if (start_ack_count) begin 38 | ack_delay_counter <= ack_delay_counter + 32'd1; 39 | end 40 | if (reset_ack_count) begin 41 | ack_delay_counter <= 32'd0; 42 | end 43 | end 44 | end 45 | 46 | always @(posedge clk or posedge reset) begin 47 | if (reset) begin 48 | state <= IDLE; 49 | end else begin 50 | state <= next_state; 51 | end 52 | end 53 | 54 | always @* begin 55 | case (state) 56 | IDLE: begin 57 | if (ack_in) begin 58 | if (delay_ack_pio == 0) begin 59 | next_state = ENABLE_ACK_LOOPBACK; 60 | end else begin 61 | next_state = ACK_DELAY_COUNT; 62 | end 63 | end 64 | else begin 65 | next_state = IDLE; 66 | end 67 | end 68 | 69 | ACK_DELAY_COUNT: begin 70 | if (ack_delay_counter == delay_ack_pio) begin 71 | next_state = ENABLE_ACK_LOOPBACK; 72 | end 73 | else begin 74 | next_state = ACK_DELAY_COUNT; 75 | end 76 | end 77 | 78 | ENABLE_ACK_LOOPBACK: begin 79 | if (~ack_in) begin 80 | next_state = RESET_ACK_DELAY_COUNT; 81 | end 82 | else begin 83 | next_state = ENABLE_ACK_LOOPBACK; 84 | end 85 | end 86 | 87 | RESET_ACK_DELAY_COUNT: begin 88 | next_state = IDLE; 89 | end 90 | 91 | default: begin 92 | next_state = 2'bxx; 93 | end 94 | endcase 95 | end 96 | 97 | always @(next_state) begin 98 | if (next_state == ACK_DELAY_COUNT) begin 99 | start_ack_count <= 1'b1; 100 | end else 101 | start_ack_count <= 1'b0; 102 | end 103 | 104 | always @(next_state) begin 105 | if (next_state == ENABLE_ACK_LOOPBACK) begin 106 | en_ack_loopback <= 1'b1; 107 | end else 108 | en_ack_loopback <= 1'b0; 109 | end 110 | 111 | always @(next_state) begin 112 | if (next_state == RESET_ACK_DELAY_COUNT || next_state == IDLE) begin 113 | reset_ack_count <= 1'b1; 114 | end else 115 | reset_ack_count <= 1'b0; 116 | end 117 | 118 | assign ack_delay_out = (en_ack_loopback) ? ack_in : 1'b0; 119 | 120 | endmodule 121 | 122 | 123 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/altera_eth_fifo_pause_ctrl_adapter/altera_eth_fifo_pause_ctrl_adapter.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2001-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // altera_eth_fifo_pause_ctrl_adapter 9 | // This module generate pause control signal (pause_ctrl_src_data) to MAC when 10 | // when the eth fifo is almost full and release pause when the eth fifo is 11 | // almost empty. 12 | //**************************************************************************** 13 | 14 | // altera message_off 10230 15 | 16 | module altera_eth_fifo_pause_ctrl_adapter 17 | ( 18 | //global 19 | clk, 20 | reset, 21 | 22 | 23 | //Almost full Data Sink 24 | data_sink_almost_full, 25 | 26 | //Almost empty Data Sink 27 | data_sink_almost_empty, 28 | 29 | //Av-ST Data Source 30 | pause_ctrl_src_data 31 | 32 | ); 33 | 34 | // =head2 Clock and reset interface 35 | input clk; 36 | input reset; 37 | 38 | // =head2 Avalon ST DataIn (Sink) Interface 39 | input data_sink_almost_full; 40 | 41 | // =head2 Avalon ST DataIn (Sink) Interface 42 | input data_sink_almost_empty; 43 | 44 | // =head2 Avalon ST DataOut (Source) Interface 45 | output [1:0] pause_ctrl_src_data; 46 | 47 | reg hold_almost_full; 48 | reg hold_almost_full_1; 49 | reg reg_data_sink_almost_full; 50 | reg reg_data_sink_almost_empty; 51 | 52 | always @ (posedge clk or posedge reset) 53 | begin 54 | if(reset == 1'b1) 55 | begin 56 | hold_almost_full <= 1'b0; 57 | reg_data_sink_almost_full <= 1'b0; 58 | reg_data_sink_almost_empty <= 1'b0; 59 | hold_almost_full_1 <= 1'b0; 60 | end 61 | else 62 | begin 63 | if(data_sink_almost_empty == 1'b1) 64 | begin 65 | hold_almost_full <= 1'b0; 66 | end 67 | else if(data_sink_almost_full == 1'b1) 68 | begin 69 | hold_almost_full <=1'b1; 70 | end 71 | reg_data_sink_almost_full <= data_sink_almost_full; 72 | reg_data_sink_almost_empty <= data_sink_almost_empty; 73 | hold_almost_full_1 <= hold_almost_full; 74 | end 75 | end 76 | 77 | assign pause_ctrl_src_data[1] = reg_data_sink_almost_full; 78 | assign pause_ctrl_src_data[0] = hold_almost_full_1 & reg_data_sink_almost_empty; 79 | 80 | 81 | endmodule 82 | 83 | 84 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/avmm_feedthrough_bridge/avmm_feedthough_bridge.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2016-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // This component is a simple AVMM Feedthough Bridge for importing RTL simple AVMM port to QSYS 9 | // Limited support 10 | // 11 | //**************************************************************************** 12 | 13 | module avmm_feedthough_bridge #( 14 | parameter ADDRESS_WIDTH = 32, 15 | parameter DATA_WIDTH = 32 16 | )( 17 | input clk, // clock 18 | input reset, // reset 19 | 20 | input [ADDRESS_WIDTH-1:0] s0_addr, // avalon_slave 21 | input s0_read, // avalon_slave 22 | input s0_write, // avalon_slave 23 | input [DATA_WIDTH-1:0] s0_writedata, // avalon_slave 24 | output [DATA_WIDTH-1:0] s0_readdata, // avalon_slave 25 | // output s0_readdatavalid, // avalon_slave 26 | output s0_waitrequest, // avalon_slave 27 | 28 | output [ADDRESS_WIDTH-1:0] m0_addr, // avalon_master 29 | output m0_read, // avalon_master 30 | output m0_write, // avalon_master 31 | output [DATA_WIDTH-1:0] m0_writedata, // avalon_master 32 | input [DATA_WIDTH-1:0] m0_readdata, // avalon_master 33 | // input m0_readdatavalid, // avalon_master 34 | input m0_waitrequest // avalon_master 35 | ); 36 | 37 | assign m0_addr = s0_addr; 38 | assign m0_read = s0_read; 39 | assign m0_write = s0_write; 40 | assign m0_writedata = s0_writedata; 41 | assign s0_readdata = m0_readdata; 42 | //assign s0_readdatavalid = m0_readdatavalid; 43 | assign s0_waitrequest = m0_waitrequest; 44 | 45 | endmodule -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // debouce 9 | // 10 | //**************************************************************************** 11 | 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2013-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Intel Edge Detector 9 | // 10 | //**************************************************************************** 11 | 12 | module altera_edge_detector #( 13 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 14 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 15 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 16 | ) ( 17 | input clk, 18 | input rst_n, 19 | input signal_in, 20 | output pulse_out 21 | ); 22 | 23 | localparam IDLE = 0, ARM = 1, CAPT = 2; 24 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 25 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 26 | 27 | reg [1:0] state, next_state; 28 | reg pulse_detect; 29 | wire busy_pulsing; 30 | 31 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 32 | assign reset_qual_n = rst_n | busy_pulsing; 33 | 34 | generate 35 | if (PULSE_EXT > 1) begin: pulse_extend 36 | integer i; 37 | reg [PULSE_EXT-1:0] extend_pulse; 38 | always @(posedge clk or negedge reset_qual_n) begin 39 | if (!reset_qual_n) 40 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 41 | else begin 42 | for (i = 1; i < PULSE_EXT; i = i+1) begin 43 | extend_pulse[i] <= extend_pulse[i-1]; 44 | end 45 | extend_pulse[0] <= pulse_detect; 46 | end 47 | end 48 | assign pulse_out = |extend_pulse; 49 | end 50 | else begin: single_pulse 51 | reg pulse_reg; 52 | always @(posedge clk or negedge reset_qual_n) begin 53 | if (!reset_qual_n) 54 | pulse_reg <= 1'b0; 55 | else 56 | pulse_reg <= pulse_detect; 57 | end 58 | assign pulse_out = pulse_reg; 59 | end 60 | endgenerate 61 | 62 | always @(posedge clk) begin 63 | if (!rst_n) 64 | state <= IDLE; 65 | else 66 | state <= next_state; 67 | end 68 | 69 | // edge detect 70 | always @(*) begin 71 | next_state = state; 72 | pulse_detect = 1'b0; 73 | case (state) 74 | IDLE : begin 75 | pulse_detect = 1'b0; 76 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 77 | else next_state = IDLE; 78 | end 79 | ARM : begin 80 | pulse_detect = 1'b0; 81 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 82 | else next_state = ARM; 83 | end 84 | CAPT : begin 85 | pulse_detect = 1'b1; 86 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 87 | else next_state = IDLE; 88 | end 89 | default : begin 90 | pulse_detect = 1'b0; 91 | next_state = IDLE; 92 | end 93 | endcase 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/eth_rx_timestamp_adapter/eth_rx_timestamp_adapter.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Ethernet RX timestamp adapter IP 9 | // RX Timestamp Adapter for Intel PSG Ethernet IP 10 | // 11 | //**************************************************************************** 12 | 13 | module eth_rx_timestamp_adapter 14 | 15 | ( 16 | input wire clock, 17 | input wire reset, 18 | 19 | //Timestamp input 20 | input timestamp_valid, 21 | input [95:0] timestamp_data, 22 | 23 | //Timestamp AVST Output 24 | output reg aso_timestamp_valid, 25 | output reg [95:0] aso_timestamp, 26 | input aso_timestamp_ready 27 | ); 28 | 29 | /* 30 | * timestamp_fp_valid should be valid for 1 cycle and valid 31 | * only once during a transmit packet 32 | */ 33 | 34 | always@(posedge clock) 35 | begin 36 | if(reset) 37 | begin 38 | aso_timestamp_valid <= 1'b0; 39 | aso_timestamp <= 96'h0; 40 | end 41 | else 42 | begin 43 | if(timestamp_valid) 44 | aso_timestamp <= timestamp_data; 45 | 46 | if(timestamp_valid) 47 | aso_timestamp_valid <= 1'b1; 48 | else if(aso_timestamp_ready) 49 | aso_timestamp_valid <= 1'b0; 50 | 51 | end 52 | end 53 | 54 | endmodule -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/eth_ts_fingerprint_compare/eth_ts_fingerprint_compare.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Ethernet timestamp fingerprint compare IP 9 | // Timestamp Fingerprint Comparator for Timestamp Filtering 10 | // 11 | //**************************************************************************** 12 | 13 | module eth_ts_fingerprint_compare 14 | ( 15 | input wire clock, 16 | input wire reset, 17 | 18 | //Fingerprint AVST Input 19 | input asi_fingerprint_valid, 20 | input [7:0] asi_fingerprint, 21 | output reg asi_fingerprint_ready, 22 | 23 | //Timestamp AVST Input 24 | input asi_timestamp_fp_valid, 25 | input [103:0] asi_timestamp_fp, 26 | output reg asi_timestamp_fp_ready, 27 | 28 | //Timestamp AVST Output 29 | output reg aso_timestamp_valid, 30 | output [95:0] aso_timestamp, 31 | input aso_timestamp_ready 32 | ); 33 | 34 | assign aso_timestamp = asi_timestamp_fp[95:0]; 35 | 36 | localparam [1:0] IDLE = 2'b00; 37 | localparam [1:0] VALID = 2'b01; 38 | localparam [1:0] ASO_OUT = 2'b10; 39 | localparam [1:0] POP = 2'b11; 40 | 41 | reg [3:0] state, next_state; 42 | reg match; 43 | 44 | always @(posedge clock) 45 | begin 46 | if (reset) 47 | state <= IDLE; 48 | else 49 | state <= next_state; 50 | end 51 | 52 | always @* 53 | begin 54 | case (state) 55 | IDLE: begin 56 | if (asi_fingerprint_valid & asi_timestamp_fp_valid) 57 | next_state <= VALID; 58 | else 59 | next_state <= IDLE; 60 | end 61 | VALID: begin 62 | if (match) 63 | next_state <= ASO_OUT; 64 | else 65 | next_state <= POP; 66 | end 67 | ASO_OUT: begin 68 | if (aso_timestamp_ready) 69 | next_state <= POP; 70 | else 71 | next_state <= ASO_OUT; 72 | end 73 | POP: begin 74 | next_state <= IDLE; 75 | end 76 | endcase 77 | end 78 | 79 | always @(posedge clock) 80 | begin 81 | if (reset) 82 | begin 83 | asi_timestamp_fp_ready <= 1'b0; 84 | asi_fingerprint_ready <= 1'b0; 85 | end 86 | else 87 | begin 88 | if (next_state == POP) 89 | asi_timestamp_fp_ready <= 1'b1; 90 | else 91 | asi_timestamp_fp_ready <= 1'b0; 92 | 93 | if (next_state == POP) 94 | asi_fingerprint_ready <= match; 95 | else 96 | asi_fingerprint_ready <= 1'b0; 97 | end 98 | end 99 | 100 | //aso valid 101 | always @(posedge clock) 102 | begin 103 | if (reset) 104 | aso_timestamp_valid <= 1'b0; 105 | else 106 | if ((state == ASO_OUT) & !aso_timestamp_ready) 107 | aso_timestamp_valid <= 1'b1; 108 | else 109 | aso_timestamp_valid <= 1'b0; 110 | end 111 | 112 | 113 | always @(posedge clock) 114 | begin 115 | if (reset) 116 | match <= 1'b0; 117 | else 118 | if (asi_fingerprint == asi_timestamp_fp[103:96]) 119 | match <= 1'b1; 120 | else 121 | match <= 1'b0; 122 | end 123 | endmodule -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/ethernet_ptp_ip/eth_tx_timestamp_adapter/eth_tx_timestamp_adapter.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // Ethernet TX timestamp adapter IP 9 | // TX Timestamp Adapter for Intel PSG Ethernet IP 10 | // 11 | //**************************************************************************** 12 | 13 | module eth_tx_timestamp_adapter 14 | 15 | ( 16 | input wire clock, 17 | input wire reset, 18 | 19 | //Timestamp input 20 | input timestamp_fp_valid, 21 | input [95:0] timestamp_fp_data, 22 | input [7:0] timestamp_fp_fingerprint, 23 | 24 | //Timestamp AVST Output 25 | output reg aso_timestamp_fp_valid, 26 | output reg [103:0] aso_timestamp_fp, 27 | input aso_timestamp_fp_ready 28 | ); 29 | 30 | /* 31 | * timestamp_fp_valid should be valid for 1 cycle and valid 32 | * only once during a transmit packet 33 | */ 34 | 35 | always@(posedge clock) 36 | begin 37 | if(reset) 38 | begin 39 | aso_timestamp_fp_valid <= 1'b0; 40 | aso_timestamp_fp <= 104'h0; 41 | end 42 | else 43 | begin 44 | if(timestamp_fp_valid) 45 | aso_timestamp_fp <= {timestamp_fp_fingerprint,timestamp_fp_data}; 46 | 47 | if(timestamp_fp_valid) 48 | aso_timestamp_fp_valid <= 1'b1; 49 | else if(aso_timestamp_fp_ready) 50 | aso_timestamp_fp_valid <= 1'b0; 51 | 52 | end 53 | end 54 | 55 | endmodule -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/prefetcher_ts_insert/altera_msgdma_prefetcher_ts_insert.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************** 2 | // 3 | // SPDX-License-Identifier: MIT-0 4 | // Copyright(c) 2018-2020 Intel Corporation. 5 | // 6 | //**************************************************************************** 7 | // 8 | // msgdma prefetcher timestamp insert 9 | // Timestamp Insert for Intel PSG MSGDMA Prefetcher IP 10 | // 11 | //**************************************************************************** 12 | 13 | module altera_msgdma_prefetcher_ts_insert ( 14 | clk, 15 | reset, 16 | 17 | snk_response_data, 18 | snk_response_valid, 19 | snk_response_ready, 20 | 21 | snk_timestamp_valid, 22 | snk_timestamp_ready, 23 | snk_timestamp, 24 | 25 | src_response_data, 26 | src_response_valid, 27 | src_response_ready 28 | 29 | ); 30 | 31 | input clk; 32 | input reset; 33 | 34 | input wire snk_response_valid; 35 | output wire snk_response_ready; 36 | input wire [255:0] snk_response_data; 37 | 38 | input wire snk_timestamp_valid; 39 | output wire snk_timestamp_ready; 40 | input wire [95:0] snk_timestamp; 41 | 42 | output wire [255:0] src_response_data; 43 | output wire src_response_valid; 44 | input wire src_response_ready; 45 | 46 | 47 | assign src_response_data[159:0] = snk_response_data[127:0]; 48 | assign src_response_data[255:160] = snk_timestamp[95:0]; 49 | 50 | assign snk_response_ready = src_response_ready; 51 | assign snk_timestamp_ready = src_response_ready; 52 | 53 | assign src_response_valid = snk_response_valid & snk_timestamp_valid; 54 | 55 | endmodule -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/custom_ip/reset_sync/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2014 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/main/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#11 $ 15 | // $Revision: #11 $ 16 | // $Date: 2011/08/09 $ 17 | // $Author: aferrucc $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/fpga_i2c.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2021-2021 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for S10 GHRD. Targeting FPGA I2C. 9 | # 10 | #**************************************************************************** 11 | 12 | set_false_path -to [get_ports {fpga_i2c_scl fpga_i2c_sda}] 13 | set_false_path -from [get_ports {fpga_i2c_scl fpga_i2c_sda}] -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/fpga_mge.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for S10 GHRD. Targeting MGE component. 9 | # 10 | #**************************************************************************** 11 | 12 | #False path for PIO 13 | set_false_path -from {*|alt_mge_phy_inst|mge_pcs|GMII_PCS.gmii_pcs|*} -to {*|altera_avalon_pio_inst|d1_data_in[*]} 14 | set_false_path -from {*|alt_mge_phy_inst|mge_pcs|GMII_PCS.gmii_pcs|*} -to {*|altera_avalon_pio_inst|readdata[*]} 15 | set_false_path -from {*|altera_xcvr_reset_control_s10_inst|*} -to {*|altera_avalon_pio_inst|d1_data_in[*]} 16 | set_false_path -from {*|altera_xcvr_reset_control_s10_inst|*} -to {*|altera_avalon_pio_inst|readdata[*]} 17 | set_false_path -from {*|mge_rcfg_inst|mge_rcfg_fsm_i|status[*]} -to {*|altera_avalon_pio_inst|d1_data_in[*]} 18 | set_false_path -from {*|mge_rcfg_inst|mge_rcfg_fsm_i|status[*]} -to {*|altera_avalon_pio_inst|readdata[*]} 19 | 20 | ##Remove clock related to MGE 2.5Gbps mode 21 | #remove_clock [get_clocks {*|alt_mge_phy_inst|profile1|*}] 22 | 23 | set_clock_groups -asynchronous -group [get_clocks {*|enet_iopll_0|*outclk0}] -group [get_clocks {*|enet_iopll_0|*outclk1}] -group [get_clocks {*|enet_iopll_0|*outclk2}] -group [get_clocks {hps_emac*_gtx_clk}] 24 | 25 | #False path as tx_d, tx_en, tx_err is clocked with posedge of hps_emac*_gtx_clk for HPS EMAC Hard IP 26 | set_false_path -fall_from [get_clocks {hps_emac*_gtx_clk}] -to {*|u_hps_to_mge_gmii_adapter_core|mac_tx*_d*} 27 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/fpga_pcie.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for S10 GHRD. Targeting PCIE component. 9 | # 10 | #**************************************************************************** 11 | 12 | # Clock Group 13 | # create_clock -name PCIE_REFCLK -period 10 [get_ports pcie_refclk_100] 14 | derive_clock_uncertainty 15 | 16 | set_false_path -from [ get_ports {pcie_hip_npor_pin_perst}] 17 | 18 | set_false_path -from {*|pcie_s10|altera_pcie_s10_hip_avmm_bridge_inst|hip|*} -to {*|altera_avalon_pio_inst|d1_data_in[*]} 19 | set_false_path -from {*|pcie_s10|altera_pcie_s10_hip_avmm_bridge_inst|hip|*} -to {*|altera_avalon_pio_inst|readdata[*]} 20 | 21 | #temporary workaround to waive ISSP reset timing violations in PCIe system 22 | #set_false_path -from {soc_inst|src_prb_rst|altera_in_system_sources_probes_inst|issp_impl|*|metastable_l2_reg[0]} -to {soc_inst|rst_controller_*|alt_rst_sync_*|altera_reset_synchronizer_int_chain[1]} 23 | #set_false_path -from {soc_inst|src_prb_rst|altera_in_system_sources_probes_inst|issp_impl|*|metastable_l2_reg[0]} -to {soc_inst|pcie_0|pcie_s10|altera_pcie_s10_hip_avmm_bridge_inst|hip|altera_pcie_s10_hip_ast_pipen1b_inst|npor_sync_altera_pcie_s10_reset_delay_sync|sync|din_s1} 24 | #set_false_path -from {soc_inst|src_prb_rst|altera_in_system_sources_probes_inst|issp_impl|*|metastable_l2_reg[0]} -to {soc_inst|pcie_0|pcie_s10|altera_pcie_s10_hip_avmm_bridge_inst|hip|altera_pcie_s10_hip_ast_pipen1b_inst|npor_sync_altera_pcie_s10_reset_delay_sync|sync|dreg[1]} 25 | #set_false_path -from {soc_inst|src_prb_rst|altera_in_system_sources_probes_inst|issp_impl|*|metastable_l2_reg[0]} -to {soc_inst|pcie_0|pcie_s10|altera_pcie_s10_hip_avmm_bridge_inst|hip|altera_pcie_s10_hip_ast_pipen1b_inst|npor_sync_altera_pcie_s10_reset_delay_sync|sync|dreg[0]} 26 | #set_clock_groups -asynchronous -group [get_clocks {MAIN_CLOCK}] -group [get_clocks {soc_inst|*|phy_g3x8|xcvr_hip_native|ch0} 27 | 28 | set_false_path -from {soc_inst|*axi_bridge_for_acp_128_inst|csr_*} -to {soc_inst|s10_hps|altera_stratix10_hps_inst|*} -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/fpga_pr.sdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for S10 GHRD. Targeting PR component. 9 | # 10 | #**************************************************************************** 11 | 12 | # False path to the PIO instances for acknowledgement delay testing only 13 | create_clock -name frz_ack_pio -period 10.000 [get_registers {soc_inst|frz_ack_pio|frz_ack_pio|data_out[0]}] 14 | set_false_path -from [get_clocks {frz_ack_pio}] -to * 15 | set_false_path -from * -to [get_clocks {frz_ack_pio}] 16 | 17 | create_clock -name stop_ack_pio -period 10.000 [get_registers {soc_inst|stop_ack_pio|stop_ack_pio|data_out[0]}] 18 | set_false_path -from [get_clocks {stop_ack_pio}] -to * 19 | set_false_path -from * -to [get_clocks {stop_ack_pio}] 20 | 21 | create_clock -name start_ack_pio -period 10.000 [get_registers {soc_inst|start_ack_pio|start_ack_pio|data_out[0]}] 22 | set_false_path -from [get_clocks {start_ack_pio}] -to * 23 | set_false_path -from * -to [get_clocks {start_ack_pio}] -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/issp_reset.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | #use this tcl script to perform a reset assertion & deassertion to the whole design system for S10 GHRD 9 | #the reset assertion and deassertion here are done via ISSP(In System Source & Probe) after device is programmed successfully 10 | set issp [lindex [get_service_paths issp] 0] 11 | set issp_m [claim_service issp $issp claimGroup] 12 | 13 | set current_source_data [issp_read_source_data $issp_m] 14 | puts "src_reset_n value: $current_source_data" 15 | #assert reset 16 | puts "assert src_reset_n via issp" 17 | set source_data 0x0 18 | issp_write_source_data $issp_m $source_data 19 | set current_source_data [issp_read_source_data $issp_m] 20 | puts "src_reset_n value: $current_source_data" 21 | after 500 22 | puts "deassert src_reset_n via issp" 23 | #deassert reset 24 | set source_data 0x1 25 | issp_write_source_data $issp_m $source_data 26 | set current_source_data [issp_read_source_data $issp_m] 27 | puts "src_reset_n value: $current_source_data" 28 | 29 | close_service issp $issp_m 30 | puts "\nInfo: Closed ISSP Service\n\n" -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/pin_assign_s10_emif.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This file contains pin assignments of EMIF port to suite different boards 9 | # Currently planned board of support are S10 SoC devkit, PE Board revC, klamath, atso12 and ashfield 10 | # 11 | #**************************************************************************** 12 | 13 | 14 | set emif_name "emif_hps" 15 | 16 | set emif_pin_assignement_file "./board/emif_pin_assignment_table_${board}.tcl" 17 | if {[file exist $emif_pin_assignement_file]} { 18 | source $emif_pin_assignement_file 19 | } else { 20 | error "$emif_pin_assignement_file not exist!! Please make sure the board settings files are included in folder ./board/" 21 | } 22 | 23 | if {$hps_emif_en} { 24 | set ranks r1 25 | set width $hps_emif_width 26 | set ecc $hps_emif_ecc_en 27 | 28 | if {$ecc} { 29 | incr width 8 30 | } 31 | 32 | set key "x${width}_$ranks" 33 | 34 | # Search for key in the first line 35 | set key_line [lindex $pin_matrix 0] 36 | set idx [lsearch $key_line $key] 37 | 38 | if {$idx < 0} { 39 | error "Could not locate configuration $key for EMIF generation" 40 | } 41 | 42 | set mem_type_idx [lsearch $key_line "MEM"] 43 | 44 | if {$mem_type_idx < 0} { 45 | error "Could not locate memory type specifier in pinout matrix for EMIF generation" 46 | } 47 | 48 | puts "key = $key" 49 | puts "board = $board" 50 | puts "mem_type = $hps_emif_type" 51 | 52 | # Now add all items 53 | set skip_first 1 54 | foreach key_line $pin_matrix { 55 | if {$skip_first} { 56 | set skip_first 0 57 | } else { 58 | set pin [lindex $key_line $idx] 59 | set mem_type [lindex $key_line $mem_type_idx] 60 | 61 | if {$pin != "unused" && (($mem_type == $hps_emif_type) || ($mem_type == "both"))} { 62 | set_location_assignment $pin -to [lindex $key_line 0] 63 | puts "Setting: set_location_assignment $pin -to [lindex $key_line 0]" 64 | } 65 | } 66 | } 67 | } 68 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/s10_hps_io48_delay_chain_solver.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This file means to solve chain delay assignment to all IO48 pins 9 | # 10 | #**************************************************************************** 11 | 12 | # Initialize IO48 chain delay assignment based on port properties 13 | set io48_output_pin [list "JTAG:TDO" "SDMMC:CCLK" "USB*:STP" "EMAC*:TX_CLK" "EMAC*:TX_CTL" "EMAC*:TXD0" "EMAC*:TXD1" "EMAC*:TXD2" "EMAC*:TXD3" "MDIO*:MDC" \ 14 | "SPIM0:CLK" "SPIM0:MOSI" "SPIM0:SS0_N" "SPIS0:MISO" "UART0:TX" "UART0:RTS_N" "NAND:ALE" "NAND:CE_N" "NAND:CLE" "NAND:WE_N" "NAND:RE_N" "NAND:WP_N" \ 15 | ] 16 | set io48_input_pin [list "JTAG:TCK" "JTAG:TMS" "JTAG:TDI" "USB*:CLK" "USB*:DIR" "USB*:NXT" "EMAC*:RX_CLK" "EMAC*:RX_CTL" "EMAC*:RXD0" "EMAC*:RXD1" "EMAC*:RXD2" "EMAC*:RXD3" \ 17 | "SPIM0:MISO" "SPIS0:CLK" "SPIS0:MOSI" "SPIS0:SS0_N" "UART0:RX" "UART0:CTS_N" "NAND:RB" "HPS_OSC_CLK" "TRACE:CLK" "TRACE:D0" "TRACE:D1" "TRACE:D2" "TRACE:D3" \ 18 | "TRACE:D10" "TRACE:D9" "TRACE:D8" "TRACE:D7" "TRACE:D6" "TRACE:D15" "TRACE:D14" "TRACE:D13" "TRACE:D12" "TRACE:D11" \ 19 | ] 20 | set io48_bidirect_pin [list "SDMMC:CMD" "SDMMC:D0" "SDMMC:D1" "SDMMC:D2" "SDMMC:D3" "SDMMC:D4" "SDMMC:D5" "SDMMC:D6" "SDMMC:D7" "I2CEMAC*:SDA" "I2CEMAC*:SCL" \ 21 | "USB*:DATA0" "USB*:DATA1" "USB*:DATA2" "USB*:DATA3" "USB*:DATA4" "USB*:DATA5" "USB*:DATA6" "USB*:DATA7" "I2C*:SDA" "I2C*:SCL" \ 22 | "MDIO*:MDIO" "NAND:ADQ0" "NAND:ADQ1" "NAND:ADQ2" "NAND:ADQ3" "NAND:ADQ4" "NAND:ADQ5" "NAND:ADQ6" "NAND:ADQ7" "NAND:ADQ8" "NAND:ADQ9" \ 23 | "NAND:ADQ10" "NAND:ADQ11" "NAND:ADQ12" "NAND:ADQ13" "NAND:ADQ14" "NAND:ADQ15" "GPIO" \ 24 | ] 25 | 26 | set io48_pinmux_assignment [list $io48_q1_assignment $io48_q2_assignment $io48_q3_assignment $io48_q4_assignment] 27 | set count 0 28 | array set output_dly_chain_io48 [] 29 | array set input_dly_chain_io48 [] 30 | foreach io_quadrant $io48_pinmux_assignment { 31 | foreach io_pin $io_quadrant { 32 | if [string match [lindex $io48_output_pin 3] $io_pin] { 33 | set output_dly_chain_io48($count) 17 34 | set input_dly_chain_io48($count) 0 35 | } elseif [string match [lindex $io48_input_pin 3] $io_pin] { 36 | set output_dly_chain_io48($count) 0 37 | set input_dly_chain_io48($count) 0 38 | } elseif [string match [lindex $io48_bidirect_pin 3] $io_pin] { 39 | set output_dly_chain_io48($count) 0 40 | set input_dly_chain_io48($count) 0 41 | } else { 42 | set output_dly_chain_io48($count) 0 43 | set input_dly_chain_io48($count) 0 44 | } 45 | incr count 46 | } 47 | } 48 | 49 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/software/devicetree/socfpga_stratix10_ghrd.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Add this piece of dtsi fragment as #include "socfpga_stratis10_ghrd.dtsi" 3 | * in the file socfpga_stratix10_socdk.dts. Compile it in the kernel along with 4 | * socfpga_stratix10.dtsi. 5 | */ 6 | 7 | /{ 8 | soc { 9 | 10 | led_pio: gpio@1080 { 11 | compatible = "altr,pio-1.0"; 12 | reg = <0xf9001080 0x8>; 13 | altr,gpio-bank-width = <4>; 14 | #gpio-cells = <2>; 15 | gpio-controller; 16 | resetvalue = <0>; 17 | }; 18 | 19 | button_pio: gpio@1060 { 20 | compatible = "altr,pio-1.0"; 21 | reg = <0xf9001060 0x10>; 22 | altr,gpio-bank-width = <4>; 23 | #gpio-cells = <2>; 24 | gpio-controller; 25 | resetvalue = <0>; 26 | }; 27 | 28 | dipsw_pio: gpio@1070 { 29 | compatible = "altr,pio-1.0"; 30 | reg = <0xf9001070 0x10>; 31 | altr,gpio-bank-width = <4>; 32 | #gpio-cells = <2>; 33 | gpio-controller; 34 | resetvalue = <0>; 35 | }; 36 | 37 | trigger_pio: gpio@1040 { 38 | compatible = "altr,pio-1.0"; 39 | reg = <0xf9001040 0x20>; 40 | altr,gpio-bank-width = <4>; 41 | #gpio-cells = <2>; 42 | gpio-controller; 43 | resetvalue = <0>; 44 | }; 45 | 46 | soc_leds: leds { 47 | compatible = "gpio-leds"; 48 | 49 | led_fpga0: fpga0 { 50 | label = "fpga_led0"; 51 | gpios = <&led_pio 0 0>; 52 | }; //end fpga0 (led_fpga0) 53 | 54 | led_fpga1: fpga1 { 55 | label = "fpga_led1"; 56 | gpios = <&led_pio 1 0>; 57 | }; //end fpga1 (led_fpga1) 58 | 59 | led_fpga2: fpga2 { 60 | label = "fpga_led2"; 61 | gpios = <&led_pio 2 0>; 62 | }; //end fpga2 (led_fpga2) 63 | 64 | led_fpga3: fpga3 { 65 | label = "fpga_led3"; 66 | gpios = <&led_pio 3 0>; 67 | }; //end fpga3 (led_fpga3) 68 | }; 69 | }; 70 | }; 71 | 72 | 73 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/software/hps_debug/Makefile: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2020 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Makefile for HPS Wipe Firmware 9 | # 10 | ################################################ 11 | 12 | #COMPILER ?= GCC 13 | #COMPILER ?= ARMCLANG 14 | 15 | WHICH = which 16 | 17 | #Check GCC Version 18 | GCCVERSION_7 := $(shell $(WHICH) aarch64-linux-gnu-gcc 2>/dev/null) 19 | GCCVERSION_9 := $(shell $(WHICH) aarch64-none-linux-gnu-gcc 2>/dev/null) 20 | 21 | ifneq ($(GCCVERSION_9),) 22 | CROSS_COMPILE ?= "aarch64-none-linux-gnu-" 23 | else ifneq ($(GCCVERSION_7),) 24 | CROSS_COMPILE ?= "aarch64-linux-gnu-" 25 | else 26 | CROSS_COMPILE = "NOT_FOUND" 27 | endif 28 | 29 | ifndef COMPILER 30 | #If no COMPILER defined Try GCC First, then try ARMCLANG 31 | 32 | ifneq ($(CROSS_COMPILE), "NOT_FOUND") 33 | include Makefile_GCC.inc 34 | else ifneq ($(shell $(WHICH) armclang 2>/dev/null),) 35 | include Makefile_ARMCLANG.inc 36 | else 37 | $(error "ERROR :: GCC or ARMCLANG Compiler not found, please install either one of the compiler to continue") 38 | endif 39 | 40 | else ifeq ("$(COMPILER)","GCC") 41 | 42 | ifneq ($(CROSS_COMPILE), "NOT_FOUND") 43 | include Makefile_GCC.inc 44 | else 45 | $(error "ERROR :: COMPILER=GCC is chosen, please install gcc compiler to continue or try COMPILER=ARMCC") 46 | endif 47 | 48 | else ifeq ("$(COMPILER)","ARMCLANG") 49 | 50 | ifneq ("$(shell $(WHICH) armclang 2>/dev/null)", "") 51 | include Makefile_ARMCLANG.inc 52 | else 53 | $(error "ERROR :: COMPILER=ARMCLANG is chosen, please install arm compiler to continue or try COMPILER=GCC") 54 | endif 55 | 56 | else 57 | 58 | $(error "ERROR :: Invalid Compiler option, choose only GCC or ARMCLANG") 59 | 60 | endif 61 | 62 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/software/hps_debug/Makefile_ARMCLANG.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Makefile for HPS Wipe Firmware ARMCLANG 9 | # 10 | ################################################ 11 | 12 | AS := armasm 13 | CC := armclang 14 | LD := armlink 15 | OD := fromelf 16 | OBJCOPY := objcopy 17 | 18 | TARGET_PROCESSOR := aarch64-arm-none-eabi 19 | 20 | AXF := hps_debug.axf 21 | IHEX := $(patsubst %.axf,%.ihex,$(AXF)) 22 | OBJDUMP_FILE := $(patsubst %.axf,%.objdump,$(AXF)) 23 | 24 | SRC := hps_debug.S 25 | SCATTER_FILE := scatter.scat 26 | 27 | CC_FLAGS := -g --target=$(TARGET_PROCESSOR) -mcpu=Cortex-A53 28 | LD_FLAGS := --scatter=$(SCATTER_FILE) --entry=0xffe00000 29 | 30 | OBJ.S := $(patsubst %.S,%.o,$(filter %.S,$(SRC))) 31 | 32 | OBJ := $(OBJ.S) 33 | 34 | RM := rm -rf 35 | 36 | .PHONY: all 37 | all: $(AXF) $(IHEX) $(OBJDUMP_FILE) 38 | 39 | clean: 40 | $(RM) *.o 41 | $(RM) $(AXF) $(IHEX) $(OBJDUMP_FILE) 42 | 43 | $(AXF): $(OBJ) $(SCATTER_FILE) 44 | $(LD) $(LD_FLAGS) $(OBJ) -o $@ 45 | 46 | $(OBJDUMP_FILE): %.objdump: %.axf 47 | $(OD) -s -t --disassemble $< > $@ 48 | 49 | $(IHEX): %.ihex: %.axf 50 | $(OBJCOPY) -O ihex $< $@ 51 | 52 | $(OBJ.S): %.o: %.S 53 | $(CC) -c $(CC_FLAGS) $< -o $@ 54 | 55 | 56 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/software/hps_debug/Makefile_GCC.inc: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2020 Intel Corporation. 5 | # 6 | ################################################ 7 | # 8 | # Makefile for HPS Wipe Firmware GCC 9 | # 10 | ################################################ 11 | 12 | CC:= $(CROSS_COMPILE)as 13 | OBJCOPY := $(CROSS_COMPILE)objcopy 14 | OBJDUMP := $(CROSS_COMPILE)objdump 15 | 16 | SRC := hps_debug.S 17 | ENTRY_POINT:=0xffe00000 18 | 19 | IHEX := $(patsubst %.S,%.ihex,$(SRC)) 20 | ELF := $(patsubst %.S,%.elf,$(SRC)) 21 | BIN := $(patsubst %.S,%.bin,$(SRC)) 22 | OBJDUMP_FILE = $(patsubst %.S,%.objdump,$(SRC)) 23 | 24 | OBJ_FLAG := -I binary -O ihex --change-address $(ENTRY_POINT) 25 | 26 | RM := rm -rf 27 | 28 | .PHONY: all 29 | all: $(ELF) $(BIN) $(IHEX) $(OBJDUMP_FILE) 30 | 31 | clean: 32 | $(RM) $(ELF) $(IHEX) $(BIN) $(OBJDUMP_FILE) 33 | 34 | $(ELF): $(SRC) 35 | $(CC) $(SRC) -o $@ 36 | 37 | $(BIN): $(ELF) 38 | $(OBJCOPY) -O binary $< $@ 39 | 40 | $(IHEX): $(BIN) 41 | $(OBJCOPY) $(OBJ_FLAG) $< $@ 42 | 43 | $(OBJDUMP_FILE): $(ELF) 44 | $(OBJDUMP) --disassemble $< > $@ 45 | 46 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/software/hps_debug/README.md: -------------------------------------------------------------------------------- 1 | # HPS Content Wipe Program 2 | 3 | The HPS content wipe program is a small program that is invoked by SDM when there is a security breach event detected or during a cold reset. The intention of this program is to clear HPS content, especially in cache. This memory might contain sensitive data. 4 | 5 | ## How to build 6 | User can build the HPS wipe with two different compilers, which are GCC and ARMCLANG 7 | 8 | ### GCC compiler 9 | > $make COMPILER=GCC 10 | 11 | User can specify the CROSS_COMPILE option, since in linaro version 9, the binary name of the compiler changed. 12 | > $make COMPILER=GCC CROSS_COMPILE=aarch64-linux-gnu- 13 | > $make COMPILER=GCC CROSS_COMPILE=aarch64-none-linux-gnu- 14 | 15 | ### ARMCLANG Compiler 16 | > $make COMPILER=ARMCLANG 17 | 18 | ## To clean 19 | > $make clean COMPILER=GCC 20 | > $make clean COMPILER=ARMCLANG 21 | 22 | 23 | ## Prerequisite 24 | ### Compile with GCC 25 | Please download GCC compiler from 26 | https://releases.linaro.org/components/toolchain/binaries/7.5-2019.12/aarch64-linux-gnu/ 27 | 28 | ### Compile with ARMCLANG 29 | Please download ARM Development Studio from 30 | https://www.arm.com/ 31 | 32 | ### For Windows user 33 | Please download MSYS2 from 34 | https://www.msys2.org/ 35 | 36 | ### Export Environment 37 | Please export the installation path of the bin folder for the compilers 38 | Examples: 39 | 40 | GCC 41 | > export PATH=$PATH:/c/gcc-linaro-7.5.0-2019.12-i686-mingw32_aarch64-linux-gnu/gcc/bin 42 | 43 | ARMCLANG 44 | > export PATH=$PATH:/c/Program\ Files/Arm/Development\ Studio\ 2021.0/sw/ARMCompiler6.16/bin 45 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/software/hps_debug/hps_debug.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/altera-opensource/ghrd-socfpga/e3bd58392f0b70b470c3afe67fd5e45f9ac5b00b/s10_soc_devkit_ghrd/software/hps_debug/hps_debug.S -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/software/hps_debug/scatter.scat: -------------------------------------------------------------------------------- 1 | OCRAM 0xFFE00000 0x20000 2 | { 3 | APP_CODE +0 ABSOLUTE 4 | { 5 | * (+RO, +RW, +ZI) 6 | } 7 | 8 | ARM_LIB_STACKHEAP +0 ALIGN 64 EMPTY 0x4000 {} 9 | EL3_STACKS +0 ALIGN 64 EMPTY 0x1000 {} 10 | } 11 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/top_level_sdc_template.sdc.terp: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2019-2021 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for Agilex GHRD. 9 | # 10 | #**************************************************************************** 11 | 12 | set_time_format -unit ns -decimal_places 3 13 | 14 | # 100MHz board input clock, 133.3333MHz for EMIF refclk 15 | create_clock -name MAIN_CLOCK -period 10 [get_ports fpga_clk_100[0]] 16 | create_clock -name EMIF_REF_CLOCK -period 7.5 [get_ports emif_hps_pll_ref_clk] 17 | 18 | @@if {$hps_mge_en == 1 || $hps_mge_10gbe_1588_en == 1} { 19 | create_clock -name PCS_CLOCK -period 8 [get_ports enet_refclk] 20 | @@} 21 | 22 | # sourcing JTAG related SDC 23 | source ./jtag.sdc 24 | 25 | @@if {$hps_mge_10gbe_1588_en == 1} { 26 | create_clock -period "125 MHz" -name {refclk_125m} [get_ports mge_refclk_125m] 27 | create_clock -period "644.53125 MHz" -name {refclk_10g} [get_ports mge_refclk_10g] 28 | @@} 29 | 30 | # FPGA IO port constraints 31 | set_false_path -from [get_ports {fpga_button_pio[0]}] -to * 32 | set_false_path -from [get_ports {fpga_button_pio[1]}] -to * 33 | set_false_path -from [get_ports {fpga_button_pio[2]}] -to * 34 | set_false_path -from [get_ports {fpga_button_pio[3]}] -to * 35 | set_false_path -from [get_ports {fpga_dipsw_pio[0]}] -to * 36 | set_false_path -from [get_ports {fpga_dipsw_pio[1]}] -to * 37 | set_false_path -from [get_ports {fpga_dipsw_pio[2]}] -to * 38 | set_false_path -from [get_ports {fpga_dipsw_pio[3]}] -to * 39 | set_false_path -from * -to [get_ports {fpga_led_pio[0]}] 40 | set_false_path -from * -to [get_ports {fpga_led_pio[1]}] 41 | set_false_path -from * -to [get_ports {fpga_led_pio[2]}] 42 | set_false_path -from * -to [get_ports {fpga_led_pio[3]}] 43 | 44 | @@if {$hps_mdio1_q1_en == 1 || $hps_mdio1_q4_en == 1} { 45 | set_max_skew -to [get_ports "emac1_mdc"] 2 46 | set_max_skew -to [get_ports "emac1_mdio"] 2 47 | @@} 48 | 49 | @@if {$hps_mdio2_q1_en == 1 || $hps_mdio2_q3_en == 1} { 50 | set_max_skew -to [get_ports "emac2_mdc"] 2 51 | set_max_skew -to [get_ports "emac2_mdio"] 2 52 | @@} 53 | 54 | @@if {$hps_mge_en == 1} { 55 | @@ for {set x 1} {$x<=$sgmii_count} {incr x} { 56 | set_false_path -from * -to [ get_ports emac${x}_phy_rst_n ] 57 | set_output_delay -clock MAIN_CLOCK 5 [ get_ports emac${x}_phy_rst_n ] -add_delay 58 | @@} 59 | @@} 60 | 61 | set_output_delay -clock MAIN_CLOCK 5 [get_ports {fpga_led_pio[3]}] -add_delay 62 | 63 | set_false_path -from [get_ports {fpga_reset_n[0]}] -to * 64 | 65 | set_false_path -from * -to {soc_inst|rst_controller_*altera_reset_synchronizer_int_chain[1]} 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | -------------------------------------------------------------------------------- /s10_soc_devkit_ghrd/update_sysid.tcl: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2017-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # This script update the GHRD SYSID 9 | # To execute this script using qsys-script 10 | # qsys-script --qpf=none --script=update_sysid.tcl --system-file= 11 | # 12 | #**************************************************************************** 13 | package require -exact qsys 18.1 14 | 15 | set epoch_time [clock seconds] 16 | set sysid_type "altera_avalon_sysid_qsys" 17 | set generic_component_type "altera_generic_component" 18 | set dot_ip_extension ".ip" 19 | set found_sysid_ip_files [list] 20 | 21 | set qsys_file_path [get_module_property FILE] 22 | set qsys_file_directory [file dirname ${qsys_file_path}] 23 | 24 | foreach inst [get_instances] { 25 | set inst_type [get_instance_property $inst CLASS_NAME] 26 | #puts "$inst_type" 27 | if {$inst_type==$generic_component_type} { 28 | load_component $inst 29 | set component_file [get_instantiation_property IP_FILE] 30 | set extension [file extension ${component_file}] 31 | #puts "$extension" 32 | if {$extension==$dot_ip_extension} { 33 | set type [get_component_property CLASS_NAME] 34 | #puts "$inst: $type" 35 | if {$type==$sysid_type} { 36 | set absolute_ip_file [file join ${qsys_file_directory} ${component_file}] 37 | #puts $absolute_ip_file 38 | lappend found_sysid_ip_files ${absolute_ip_file} 39 | } 40 | } 41 | } 42 | } 43 | 44 | foreach sysid $found_sysid_ip_files { 45 | load_system ${sysid} 46 | #puts [get_module_property GENERATION_ID] 47 | set_module_property GENERATION_ID $epoch_time 48 | #puts [get_module_property GENERATION_ID] 49 | validate_system 50 | save_system ${sysid} 51 | } 52 | --------------------------------------------------------------------------------