├── tests ├── __init__.py └── amdgpu_pptable │ ├── __init__.py │ ├── 5700xt_aorus │ ├── pp_dpm_fclk │ ├── pp_dpm_sclk │ ├── pp_dpm_dcefclk │ ├── pp_dpm_socclk │ ├── pp_dpm_mclk │ ├── pp_table │ ├── pp_od_clk_voltage │ └── sensors │ ├── 5700xt_gaming_x │ ├── pp_dpm_dcefclk │ ├── pp_dpm_fclk │ ├── pp_dpm_sclk │ ├── pp_dpm_socclk │ ├── pp_dpm_mclk │ ├── pp_table │ ├── pp_od_clk_voltage │ └── sensors │ ├── 5700xt_nitro_se │ ├── pp_dpm_dcefclk │ ├── pp_dpm_fclk │ ├── pp_dpm_sclk │ ├── pp_dpm_socclk │ ├── pp_dpm_mclk │ ├── pp_table │ └── sensors │ ├── rx580_pulse_pp_table │ ├── vega64_nitro_oc_pp_table │ ├── test_pptable_navi10.py │ ├── test_version_detect.py │ ├── test_pptable_v1_0.py │ └── test_vega10_pptable.py ├── src └── amdgpu_pptable │ ├── __init__.py │ ├── generated │ ├── __init__.py │ ├── smu_v11_0_pptable_navi10.py │ ├── pptable_v1_0.py │ └── vega10_pptable.py │ ├── version_detect.py │ ├── dump.py │ ├── smu_v11_0_pptable_navi10.py │ ├── pptable_v1_0.py │ └── vega10_pptable.py ├── .git_archival.txt ├── .gitattributes ├── pyproject.toml ├── setup.cfg ├── .github └── workflows │ ├── flake8.yml │ ├── publish-to-pypi.yml │ ├── publish-to-test-pypi.yml │ └── test.yml ├── tox.ini ├── LICENSE.txt ├── setup.py ├── README.rst ├── .gitignore └── generate_ctypes.py /tests/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /.git_archival.txt: -------------------------------------------------------------------------------- 1 | ref-names: HEAD -> master -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | .git_archival.txt export-subst -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/pp_dpm_fclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 950Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/pp_dpm_sclk: -------------------------------------------------------------------------------- 1 | 0: 300Mhz 2 | 1: 800Mhz * 3 | 2: 2035Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/pp_dpm_dcefclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 542Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/pp_dpm_socclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 950Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/pp_dpm_dcefclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 542Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/pp_dpm_fclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 950Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/pp_dpm_sclk: -------------------------------------------------------------------------------- 1 | 0: 300Mhz 2 | 1: 800Mhz * 3 | 2: 2080Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/pp_dpm_socclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 950Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_nitro_se/pp_dpm_dcefclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 542Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_nitro_se/pp_dpm_fclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 950Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_nitro_se/pp_dpm_sclk: -------------------------------------------------------------------------------- 1 | 0: 300Mhz 2 | 1: 800Mhz * 3 | 2: 2100Mhz 4 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_nitro_se/pp_dpm_socclk: -------------------------------------------------------------------------------- 1 | 0: 506Mhz 2 | 1: 950Mhz * 3 | 2: 1266Mhz 4 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/generated/__init__.py: -------------------------------------------------------------------------------- 1 | # Modules in this package are generated from kernel headers 2 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/pp_dpm_mclk: -------------------------------------------------------------------------------- 1 | 0: 100Mhz 2 | 1: 500Mhz 3 | 2: 625Mhz 4 | 3: 875Mhz * 5 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/pp_dpm_mclk: -------------------------------------------------------------------------------- 1 | 0: 100Mhz 2 | 1: 500Mhz 3 | 2: 625Mhz 4 | 3: 875Mhz * 5 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_nitro_se/pp_dpm_mclk: -------------------------------------------------------------------------------- 1 | 0: 100Mhz 2 | 1: 500Mhz 3 | 2: 625Mhz 4 | 3: 900Mhz * 5 | -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = ["setuptools>=40.8.0", "wheel", "setuptools_scm", "setuptools_scm_git_archive"] 3 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/pp_table: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/amezin/amdgpu-pptable/HEAD/tests/amdgpu_pptable/5700xt_aorus/pp_table -------------------------------------------------------------------------------- /tests/amdgpu_pptable/rx580_pulse_pp_table: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/amezin/amdgpu-pptable/HEAD/tests/amdgpu_pptable/rx580_pulse_pp_table -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/pp_table: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/amezin/amdgpu-pptable/HEAD/tests/amdgpu_pptable/5700xt_gaming_x/pp_table -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_nitro_se/pp_table: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/amezin/amdgpu-pptable/HEAD/tests/amdgpu_pptable/5700xt_nitro_se/pp_table -------------------------------------------------------------------------------- /tests/amdgpu_pptable/vega64_nitro_oc_pp_table: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/amezin/amdgpu-pptable/HEAD/tests/amdgpu_pptable/vega64_nitro_oc_pp_table -------------------------------------------------------------------------------- /setup.cfg: -------------------------------------------------------------------------------- 1 | [metadata] 2 | license_file = LICENSE.txt 3 | 4 | [flake8] 5 | exclude = .git,__pycache__,.tox,*.pyc,build,dist,src/amdgpu_pptable/generated 6 | extend-ignore = F403,F405 7 | max-line-length = 120 8 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/pp_od_clk_voltage: -------------------------------------------------------------------------------- 1 | OD_SCLK: 2 | 0: 800Mhz 3 | 1: 2034Mhz 4 | OD_MCLK: 5 | 0: 875MHz 6 | OD_VDDC_CURVE: 7 | 0: 800MHz @ 0mV 8 | 1: 1417MHz @ 0mV 9 | 2: 2034MHz @ 0mV 10 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/pp_od_clk_voltage: -------------------------------------------------------------------------------- 1 | OD_SCLK: 2 | 0: 800Mhz 3 | 1: 2079Mhz 4 | OD_MCLK: 5 | 0: 875MHz 6 | OD_VDDC_CURVE: 7 | 0: 800MHz @ 0mV 8 | 1: 1439MHz @ 0mV 9 | 2: 2079MHz @ 0mV 10 | -------------------------------------------------------------------------------- /.github/workflows/flake8.yml: -------------------------------------------------------------------------------- 1 | name: flake8 lint 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | lint: 7 | runs-on: ubuntu-latest 8 | steps: 9 | - uses: actions/checkout@v1 10 | - uses: actions/setup-python@v1 11 | with: 12 | python-version: '3.x' 13 | - run: pip install tox 14 | - run: tox -e flake8 15 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/test_pptable_navi10.py: -------------------------------------------------------------------------------- 1 | import pkg_resources 2 | import pytest 3 | 4 | import amdgpu_pptable.smu_v11_0_pptable_navi10 5 | 6 | 7 | @pytest.mark.parametrize('table', ['5700xt_aorus', '5700xt_gaming_x', '5700xt_nitro_se']) 8 | def test_parse_navi10(table): 9 | with open(pkg_resources.resource_filename(__name__, table + '/pp_table'), 'rb') as f: 10 | orig_buffer = f.read() 11 | 12 | buffer = bytearray(orig_buffer) 13 | amdgpu_pptable.smu_v11_0_pptable_navi10.parse(buffer) 14 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_aorus/sensors: -------------------------------------------------------------------------------- 1 | amdgpu-pci-6700 2 | Adapter: PCI adapter 3 | vddgfx: 750.00 mV 4 | fan1: 0 RPM (min = 0 RPM, max = 4200 RPM) 5 | edge: +55.0°C (crit = +118.0°C, hyst = -273.1°C) 6 | (emerg = +99.0°C) 7 | junction: +55.0°C (crit = +99.0°C, hyst = -273.1°C) 8 | (emerg = +99.0°C) 9 | mem: +58.0°C (crit = +99.0°C, hyst = -273.1°C) 10 | (emerg = +99.0°C) 11 | power1: 34.00 W (cap = 220.00 W) 12 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_gaming_x/sensors: -------------------------------------------------------------------------------- 1 | amdgpu-pci-6700 2 | Adapter: PCI adapter 3 | vddgfx: 725.00 mV 4 | fan1: 0 RPM (min = 0 RPM, max = 2970 RPM) 5 | edge: +66.0°C (crit = +118.0°C, hyst = -273.1°C) 6 | (emerg = +99.0°C) 7 | junction: +66.0°C (crit = +99.0°C, hyst = -273.1°C) 8 | (emerg = +99.0°C) 9 | mem: +66.0°C (crit = +99.0°C, hyst = -273.1°C) 10 | (emerg = +99.0°C) 11 | power1: 35.00 W (cap = 210.00 W) 12 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/5700xt_nitro_se/sensors: -------------------------------------------------------------------------------- 1 | amdgpu-pci-6700 2 | Adapter: PCI adapter 3 | vddgfx: 725.00 mV 4 | fan1: 1169 RPM (min = 0 RPM, max = 3400 RPM) 5 | edge: +49.0°C (crit = +118.0°C, hyst = -273.1°C) 6 | (emerg = +99.0°C) 7 | junction: +50.0°C (crit = +99.0°C, hyst = -273.1°C) 8 | (emerg = +99.0°C) 9 | mem: +54.0°C (crit = +99.0°C, hyst = -273.1°C) 10 | (emerg = +99.0°C) 11 | power1: 30.00 W (cap = 240.00 W) 12 | -------------------------------------------------------------------------------- /.github/workflows/publish-to-pypi.yml: -------------------------------------------------------------------------------- 1 | name: Publish to pypi 2 | 3 | on: 4 | push: 5 | tags-ignore: 6 | - 'pre-*' 7 | 8 | jobs: 9 | publish: 10 | runs-on: ubuntu-latest 11 | steps: 12 | - uses: actions/checkout@v1 13 | - uses: actions/setup-python@v1 14 | with: 15 | python-version: '3.x' 16 | - run: pip install tox 17 | - run: tox -e sdist,wheel 18 | - uses: pypa/gh-action-pypi-publish@master 19 | with: 20 | user: __token__ 21 | password: ${{ secrets.pypi_token }} 22 | -------------------------------------------------------------------------------- /.github/workflows/publish-to-test-pypi.yml: -------------------------------------------------------------------------------- 1 | name: Publish to test pypi 2 | 3 | on: 4 | push: 5 | tags: 6 | - 'pre-*' 7 | 8 | jobs: 9 | publish: 10 | runs-on: ubuntu-latest 11 | steps: 12 | - uses: actions/checkout@v1 13 | - uses: actions/setup-python@v1 14 | with: 15 | python-version: '3.x' 16 | - run: pip install tox 17 | - run: tox -e sdist,wheel 18 | - uses: pypa/gh-action-pypi-publish@master 19 | with: 20 | repository_url: https://test.pypi.org/legacy/ 21 | user: __token__ 22 | password: ${{ secrets.test_pypi_token }} 23 | -------------------------------------------------------------------------------- /tox.ini: -------------------------------------------------------------------------------- 1 | [tox] 2 | envlist = py36,py37,py38,flake8 3 | 4 | [testenv] 5 | deps = pytest 6 | commands = pytest {posargs} 7 | 8 | [testenv:generate-ctypes] 9 | basepython = python3 10 | sitepackages = true 11 | deps = ctypeslib2 12 | skip_install = true 13 | commands = {envpython} generate_ctypes.py {posargs} 14 | 15 | [testenv:flake8] 16 | basepython = python3 17 | skip_install = true 18 | deps = flake8 >= 3.6.0 19 | commands = flake8 {posargs} 20 | 21 | [testenv:sdist] 22 | basepython = python3 23 | skip_install = true 24 | commands = {envpython} setup.py sdist {posargs} 25 | 26 | [testenv:wheel] 27 | basepython = python3 28 | skip_install = true 29 | commands = {envpython} setup.py bdist_wheel {posargs} 30 | -------------------------------------------------------------------------------- /.github/workflows/test.yml: -------------------------------------------------------------------------------- 1 | name: Tests 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | test: 7 | runs-on: ubuntu-latest 8 | strategy: 9 | matrix: 10 | python_version: 11 | - '3.6' 12 | - '3.7' 13 | - '3.8' 14 | include: 15 | - python_version: '3.6' 16 | toxenv: py36 17 | - python_version: '3.7' 18 | toxenv: py37 19 | - python_version: '3.8' 20 | toxenv: py38 21 | steps: 22 | - uses: actions/checkout@v1 23 | - uses: actions/setup-python@v1 24 | with: 25 | python-version: ${{ matrix.python_version }} 26 | - run: pip install tox 27 | - run: tox -e ${{ matrix.toxenv }} 28 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/version_detect.py: -------------------------------------------------------------------------------- 1 | from . import pptable_v1_0, vega10_pptable, smu_v11_0_pptable_navi10 2 | 3 | 4 | class UnknownTableRevision(KeyError): 5 | pass 6 | 7 | 8 | def parse(buffer): 9 | header = pptable_v1_0.struct__ATOM_COMMON_TABLE_HEADER.from_buffer(buffer) 10 | 11 | if header.ucTableFormatRevision == pptable_v1_0.ATOM_Tonga_TABLE_REVISION_TONGA: 12 | return pptable_v1_0.parse(buffer) 13 | 14 | if header.ucTableFormatRevision == vega10_pptable.ATOM_Vega10_TABLE_REVISION_VEGA10: 15 | return vega10_pptable.parse(buffer) 16 | 17 | if header.ucTableFormatRevision == smu_v11_0_pptable_navi10.SMU_11_0_TABLE_FORMAT_REVISION: 18 | return smu_v11_0_pptable_navi10.parse(buffer) 19 | 20 | raise UnknownTableRevision(header.ucTableFormatRevision) 21 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/test_version_detect.py: -------------------------------------------------------------------------------- 1 | import pkg_resources 2 | 3 | import pytest 4 | 5 | import amdgpu_pptable.version_detect 6 | import amdgpu_pptable.vega10_pptable 7 | import amdgpu_pptable.pptable_v1_0 8 | import amdgpu_pptable.smu_v11_0_pptable_navi10 9 | 10 | 11 | @pytest.mark.parametrize('pptable_file,expected_type', [ 12 | ('rx580_pulse_pp_table', amdgpu_pptable.pptable_v1_0.ATOM_Tonga_POWERPLAYTABLE), 13 | ('vega64_nitro_oc_pp_table', amdgpu_pptable.vega10_pptable.ATOM_Vega10_POWERPLAYTABLE), 14 | ('5700xt_gaming_x/pp_table', amdgpu_pptable.smu_v11_0_pptable_navi10.struct_smu_11_0_powerplay_table), 15 | ('5700xt_nitro_se/pp_table', amdgpu_pptable.smu_v11_0_pptable_navi10.struct_smu_11_0_powerplay_table) 16 | ]) 17 | def test_type(pptable_file, expected_type): 18 | with open(pkg_resources.resource_filename(__name__, pptable_file), 'rb') as f: 19 | orig_buffer = f.read() 20 | 21 | buffer = bytearray(orig_buffer) 22 | pptable = amdgpu_pptable.version_detect.parse(buffer) 23 | 24 | assert type(pptable.Main) is expected_type 25 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 Aleksandr Mezin 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | import setuptools 2 | 3 | 4 | with open('README.rst') as fp: 5 | long_description = fp.read() 6 | 7 | 8 | setuptools.setup( 9 | name='amdgpu-pptable', 10 | packages=setuptools.find_packages('src'), 11 | package_dir={'': 'src'}, 12 | setup_requires=['setuptools_scm', 'setuptools_scm_git_archive'], 13 | python_requires='>=3.6', 14 | use_scm_version={'write_to': 'src/amdgpu_pptable/version.py'}, 15 | description='AMDGPU PowerPlay table parser', 16 | long_description=long_description, 17 | url='https://github.com/amezin/amdgpu-pptable', 18 | keywords='amdgpu radeon powerplay', 19 | author='Aleksandr Mezin', 20 | author_email='mezin.alexander@gmail.com', 21 | classifiers=[ 22 | 'License :: OSI Approved :: MIT License', 23 | 'Programming Language :: Python :: 3', 24 | 'Programming Language :: Python :: 3.6', 25 | 'Programming Language :: Python :: 3.7', 26 | 'Programming Language :: Python :: 3.8', 27 | 'Development Status :: 4 - Beta', 28 | 'Intended Audience :: Developers', 29 | 'Topic :: Software Development :: Libraries', 30 | 'Topic :: System :: Hardware' 31 | ] 32 | ) 33 | -------------------------------------------------------------------------------- /README.rst: -------------------------------------------------------------------------------- 1 | |Tests badge| |flake8 lint badge| |pypi badge| 2 | 3 | AMDGPU PowerPlay table parser 4 | ============================= 5 | 6 | A Python library that converts AMDGPU PowerPlay tables to ctypes structs. 7 | 8 | Uses code generated from MIT-licensed AMDGPU Linux driver headers. 9 | 10 | For a Qt GUI editor see `amdgpu-pptable-editor-qt `_ 11 | 12 | Generating ctypes structs 13 | ------------------------- 14 | 15 | Generated code is tracked in git, it is located in ``src/amdgpu_pptable/generated``. 16 | 17 | To re-generate it (with, maybe, different kernel sources):: 18 | 19 | $ tox -e generate-ctypes -- -k path/to/kernel/sources 20 | 21 | 22 | .. |Tests badge| image:: https://github.com/amezin/amdgpu-pptable/workflows/Tests/badge.svg 23 | :target: https://github.com/amezin/amdgpu-pptable/actions?query=workflow%3ATests 24 | .. |flake8 lint badge| image:: https://github.com/amezin/amdgpu-pptable/workflows/flake8%20lint/badge.svg 25 | :target: https://github.com/amezin/amdgpu-pptable/actions?query=workflow%3A%22flake8+lint%22 26 | .. |pypi badge| image:: https://img.shields.io/pypi/v/amdgpu-pptable 27 | :target: https://pypi.org/project/amdgpu-pptable/ 28 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/test_pptable_v1_0.py: -------------------------------------------------------------------------------- 1 | import pkg_resources 2 | 3 | import amdgpu_pptable.pptable_v1_0 4 | 5 | 6 | def test_load(): 7 | with open(pkg_resources.resource_filename(__name__, 'rx580_pulse_pp_table'), 'rb') as f: 8 | orig_buffer = f.read() 9 | 10 | buffer = bytearray(orig_buffer) 11 | pptable = amdgpu_pptable.pptable_v1_0.parse(buffer) 12 | 13 | assert orig_buffer == buffer 14 | 15 | assert type(pptable.FanTable) is amdgpu_pptable.pptable_v1_0.ATOM_Fiji_Fan_Table 16 | assert type(pptable.SclkDependencyTable.entries[0]) is \ 17 | amdgpu_pptable.pptable_v1_0.ATOM_Polaris_SCLK_Dependency_Record 18 | assert type(pptable.PCIETable.entries[0]) is amdgpu_pptable.pptable_v1_0.ATOM_Polaris10_PCIE_Record 19 | 20 | assert pptable.PowerTuneTable.usSoftwareShutdownTemp == 94 21 | assert pptable.PowerTuneTable.usMaximumPowerDeliveryLimit == 155 22 | assert pptable.ThermalController.ucFanMaxRPM == 32 23 | 24 | assert list(e.ulMclk / 100 for e in pptable.MclkDependencyTable.entries) == [300, 1000, 2000] 25 | assert list(e.ulSclk / 100 for e in pptable.SclkDependencyTable.entries) == \ 26 | [300, 600, 900, 1145, 1215, 1257, 1300, 1366] 27 | 28 | pptable.FanTable.ucMinimumPWMLimit = 14 29 | 30 | assert orig_buffer != buffer 31 | -------------------------------------------------------------------------------- /tests/amdgpu_pptable/test_vega10_pptable.py: -------------------------------------------------------------------------------- 1 | import pkg_resources 2 | 3 | import amdgpu_pptable.vega10_pptable 4 | 5 | 6 | def test_load(): 7 | with open(pkg_resources.resource_filename(__name__, 'vega64_nitro_oc_pp_table'), 'rb') as f: 8 | orig_buffer = f.read() 9 | 10 | buffer = bytearray(orig_buffer) 11 | pptable = amdgpu_pptable.vega10_pptable.parse(buffer) 12 | 13 | assert orig_buffer == buffer 14 | 15 | assert pptable.FanTable.ucRevId == 11 16 | assert pptable.FanTable.usFanAcousticLimitRpm == 1500 17 | 18 | assert len(pptable.SocclkDependencyTable.entries) == pptable.SocclkDependencyTable.ucNumEntries 19 | assert pptable.SocclkDependencyTable.entries[0].ulClk == 60000 20 | assert pptable.SocclkDependencyTable.entries[7].ulClk == 110700 21 | assert pptable.GfxclkDependencyTable.entries[7].ulClk == 163000 22 | assert pptable.GfxclkDependencyTable.entries[7].ucVddInd == 7 23 | 24 | assert pptable.PowerTuneTable.usSoftwareShutdownTemp == 91 25 | assert pptable.FanTable.ucFanMinRPM == 3 26 | assert pptable.FanTable.ucFanMaxRPM == 33 27 | 28 | assert list(e.ulMemClk / 100 for e in pptable.MclkDependencyTable.entries) == [167, 500, 800, 945] 29 | assert list(e.ulClk / 100 for e in pptable.GfxclkDependencyTable.entries) == \ 30 | [852, 991, 1084, 1138, 1200, 1401, 1536, 1630] 31 | 32 | pptable.FanTable.usMinimumPWMLimit = 14 33 | pptable.FanTable.ucEnableZeroRPM = 0 34 | 35 | assert orig_buffer != buffer 36 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/dump.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import collections.abc 3 | import ctypes 4 | import enum 5 | import json 6 | import sys 7 | 8 | from . import version_detect, version 9 | 10 | 11 | def make_serializable(obj): 12 | if isinstance(obj, collections.abc.MutableMapping): 13 | 14 | def key_to_str(key): 15 | return key.name if isinstance(key, enum.Enum) else str(key) 16 | 17 | return {key_to_str(key): make_serializable(value) for key, value in obj.items()} 18 | 19 | if isinstance(obj, ctypes.Structure): 20 | return {field: make_serializable(getattr(obj, field)) for field, _ in obj._fields_} 21 | 22 | if isinstance(obj, ctypes.Array): 23 | return [make_serializable(e) for e in obj] 24 | 25 | return obj 26 | 27 | 28 | def dump(pptable_file, output, indent=None): 29 | pptable = version_detect.parse(bytearray(pptable_file.read())) 30 | json.dump({k: make_serializable(v) for k, v in pptable._asdict().items()}, output, indent=indent) 31 | 32 | 33 | def main(args=None): 34 | cmdline = argparse.ArgumentParser() 35 | cmdline.add_argument('pptable_file', type=argparse.FileType('rb')) 36 | cmdline.add_argument('-o', '--output', type=argparse.FileType('wt'), default=sys.stdout) 37 | cmdline.add_argument('--indent', type=int) 38 | cmdline.add_argument('--version', action='version', version=f'%(prog)s {version.version}') 39 | dump(**vars(cmdline.parse_args(args))) 40 | 41 | 42 | if __name__ == '__main__': 43 | main() 44 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Generated version file 2 | src/amdgpu_pptable/version.py 3 | 4 | # PyCharm 5 | .idea/ 6 | 7 | # Byte-compiled / optimized / DLL files 8 | __pycache__/ 9 | *.py[cod] 10 | *$py.class 11 | 12 | # C extensions 13 | *.so 14 | 15 | # Distribution / packaging 16 | .Python 17 | build/ 18 | develop-eggs/ 19 | dist/ 20 | downloads/ 21 | eggs/ 22 | .eggs/ 23 | lib/ 24 | lib64/ 25 | parts/ 26 | sdist/ 27 | var/ 28 | wheels/ 29 | *.egg-info/ 30 | .installed.cfg 31 | *.egg 32 | MANIFEST 33 | 34 | # PyInstaller 35 | # Usually these files are written by a python script from a template 36 | # before PyInstaller builds the exe, so as to inject date/other infos into it. 37 | *.manifest 38 | *.spec 39 | 40 | # Installer logs 41 | pip-log.txt 42 | pip-delete-this-directory.txt 43 | 44 | # Unit test / coverage reports 45 | htmlcov/ 46 | .tox/ 47 | .nox/ 48 | .coverage 49 | .coverage.* 50 | .cache 51 | nosetests.xml 52 | coverage.xml 53 | *.cover 54 | .hypothesis/ 55 | .pytest_cache/ 56 | 57 | # Translations 58 | *.mo 59 | *.pot 60 | 61 | # Django stuff: 62 | *.log 63 | local_settings.py 64 | db.sqlite3 65 | 66 | # Flask stuff: 67 | instance/ 68 | .webassets-cache 69 | 70 | # Scrapy stuff: 71 | .scrapy 72 | 73 | # Sphinx documentation 74 | docs/_build/ 75 | 76 | # PyBuilder 77 | target/ 78 | 79 | # Jupyter Notebook 80 | .ipynb_checkpoints 81 | 82 | # IPython 83 | profile_default/ 84 | ipython_config.py 85 | 86 | # pyenv 87 | .python-version 88 | 89 | # celery beat schedule file 90 | celerybeat-schedule 91 | 92 | # SageMath parsed files 93 | *.sage.py 94 | 95 | # Environments 96 | .env 97 | .venv 98 | env/ 99 | venv/ 100 | ENV/ 101 | env.bak/ 102 | venv.bak/ 103 | 104 | # Spyder project settings 105 | .spyderproject 106 | .spyproject 107 | 108 | # Rope project settings 109 | .ropeproject 110 | 111 | # mkdocs documentation 112 | /site 113 | 114 | # mypy 115 | .mypy_cache/ 116 | .dmypy.json 117 | dmypy.json 118 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/smu_v11_0_pptable_navi10.py: -------------------------------------------------------------------------------- 1 | import collections 2 | import enum 3 | import logging 4 | 5 | from .generated import smu_v11_0_pptable_navi10 as gen 6 | from .generated.smu_v11_0_pptable_navi10 import * # noqa: F401 7 | 8 | 9 | LOG = logging.getLogger(__name__) 10 | 11 | 12 | def _make_enum(name): 13 | return enum.IntEnum( 14 | name, 15 | {v: k for k, v in getattr(gen, f'{name}__enumvalues').items()}, 16 | module=__name__ 17 | ) 18 | 19 | 20 | SMU_11_0_ODFEATURE_CAP = _make_enum('SMU_11_0_ODFEATURE_CAP') 21 | SMU_11_0_ODSETTING_ID = _make_enum('SMU_11_0_ODSETTING_ID') 22 | SMU_11_0_PPCLOCK_ID = _make_enum('SMU_11_0_PPCLOCK_ID') 23 | 24 | 25 | class ArrayDictAdapter(collections.abc.MutableMapping): 26 | index_type = int 27 | 28 | def __init__(self, array): 29 | self.data = array 30 | 31 | def __getitem__(self, key): 32 | return self.data[key] 33 | 34 | def __setitem__(self, key, value): 35 | self.data[key] = value 36 | 37 | def __delitem__(self, key): 38 | del self.data[key] 39 | 40 | def __len__(self): 41 | return len(self.data) 42 | 43 | def __iter__(self): 44 | for key in range(len(self)): 45 | try: 46 | yield self.index_type(key) 47 | except ValueError: 48 | yield key 49 | 50 | @classmethod 51 | def make(cls, array, index_t=index_type): 52 | class DerivedArrayDictAdapter(cls): 53 | index_type = index_t 54 | wrapped_type = type(array) 55 | 56 | return DerivedArrayDictAdapter(array) 57 | 58 | 59 | class struct_smu_11_0_overdrive_table(gen.struct_smu_11_0_overdrive_table): 60 | @property 61 | def min(self): 62 | return ArrayDictAdapter.make(super().min, SMU_11_0_ODSETTING_ID) 63 | 64 | @property 65 | def max(self): 66 | return ArrayDictAdapter.make(super().max, SMU_11_0_ODSETTING_ID) 67 | 68 | @property 69 | def cap(self): 70 | return ArrayDictAdapter.make(super().cap, SMU_11_0_ODFEATURE_CAP) 71 | 72 | 73 | class struct_smu_11_0_power_saving_clock_table(gen.struct_smu_11_0_power_saving_clock_table): 74 | @property 75 | def min(self): 76 | return ArrayDictAdapter.make(super().min, SMU_11_0_PPCLOCK_ID) 77 | 78 | @property 79 | def max(self): 80 | return ArrayDictAdapter.make(super().max, SMU_11_0_PPCLOCK_ID) 81 | 82 | 83 | class struct_smu_11_0_powerplay_table(gen.struct_smu_11_0_powerplay_table): 84 | @property 85 | def overdrive_table(self): 86 | return struct_smu_11_0_overdrive_table.from_buffer(super().overdrive_table) 87 | 88 | @property 89 | def power_saving_clock(self): 90 | return struct_smu_11_0_power_saving_clock_table.from_buffer(super().power_saving_clock) 91 | 92 | 93 | def parse(buffer): 94 | main_table = struct_smu_11_0_powerplay_table.from_buffer(buffer) 95 | parse_result = {'Main': main_table} 96 | return collections.namedtuple('ParseResult', parse_result.keys())(**parse_result) 97 | 98 | 99 | __all__ = gen.__all__ + [ 100 | 'parse' 101 | ] 102 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/pptable_v1_0.py: -------------------------------------------------------------------------------- 1 | import collections 2 | import ctypes 3 | import logging 4 | 5 | from .generated.pptable_v1_0 import * 6 | 7 | 8 | LOG = logging.getLogger(__name__) 9 | 10 | 11 | def parse_table(buffer, offset, type_select): 12 | header = PPTable_Generic_SubTable_Header.from_buffer(buffer, offset) 13 | return type_select(header.ucRevId).from_buffer(buffer, offset) 14 | 15 | 16 | def parse_array_table(buffer, offset, type_select=None): 17 | table = parse_table(buffer, offset, type_select) 18 | 19 | entries_name, entries_type = table.__class__._fields_[-1] 20 | assert entries_type._length_ == 1 21 | 22 | class DynamicArrayTable(ctypes.LittleEndianStructure): 23 | _pack_ = table.__class__._pack_ 24 | _fields_ = table.__class__._fields_[:-1] + [(entries_name, entries_type._type_ * table.ucNumEntries)] 25 | wrapped_type = table.__class__ 26 | 27 | return DynamicArrayTable.from_buffer(buffer, offset) 28 | 29 | 30 | def fan_table_type(rev_id): 31 | if rev_id < 8: 32 | return ATOM_Tonga_Fan_Table 33 | else: 34 | return ATOM_Fiji_Fan_Table 35 | 36 | 37 | def sclk_table_type(rev_id): 38 | if rev_id < 1: 39 | return ATOM_Tonga_SCLK_Dependency_Table 40 | else: 41 | return ATOM_Polaris_SCLK_Dependency_Table 42 | 43 | 44 | def powertune_table_type(rev_id): 45 | if rev_id < 3: 46 | return ATOM_Tonga_PowerTune_Table 47 | else: 48 | return ATOM_Fiji_PowerTune_Table 49 | 50 | 51 | def pcie_table_type(rev_id): 52 | if rev_id < 1: 53 | return ATOM_Tonga_PCIE_Table 54 | else: 55 | return ATOM_Polaris10_PCIE_Table 56 | 57 | 58 | def parse(buffer): 59 | main_table = ATOM_Tonga_POWERPLAYTABLE.from_buffer(buffer) 60 | parse_result = {'Main': main_table} 61 | 62 | def table(name, parse_func, *args, **kwargs): 63 | offset = getattr(main_table, f'us{name}Offset') 64 | if offset > 0: 65 | parse_result[name] = parse_func(buffer, offset, *args, **kwargs) 66 | 67 | table('StateArray', parse_array_table, lambda _: ATOM_Tonga_State_Array) 68 | table('SclkDependencyTable', parse_array_table, sclk_table_type) 69 | table('MclkDependencyTable', parse_array_table, lambda _: ATOM_Tonga_MCLK_Dependency_Table) 70 | table('MMDependencyTable', parse_array_table, lambda _: ATOM_Tonga_MM_Dependency_Table) 71 | table('VddcLookupTable', parse_array_table, lambda _: ATOM_Tonga_Voltage_Lookup_Table) 72 | table('VddgfxLookupTable', parse_array_table, lambda _: ATOM_Tonga_Voltage_Lookup_Table) 73 | table('VCEStateTable', parse_array_table, lambda _: ATOM_Tonga_VCE_State_Table) 74 | table('HardLimitTable', parse_array_table, lambda _: ATOM_Tonga_Hard_Limit_Table) 75 | table('PCIETable', parse_array_table, pcie_table_type) 76 | 77 | table('FanTable', parse_table, fan_table_type) 78 | table('PowerTuneTable', parse_table, powertune_table_type) 79 | table('ThermalController', parse_table, lambda _: ATOM_Tonga_Thermal_Controller) 80 | table('PPMTable', parse_table, lambda _: ATOM_Tonga_PPM_Table) 81 | table('GPIOTable', parse_table, lambda _: ATOM_Tonga_GPIO_Table) 82 | 83 | return collections.namedtuple('ParseResult', parse_result.keys())(*parse_result.values()) 84 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/vega10_pptable.py: -------------------------------------------------------------------------------- 1 | import collections 2 | import ctypes 3 | import logging 4 | 5 | from .generated.vega10_pptable import * 6 | 7 | 8 | LOG = logging.getLogger(__name__) 9 | 10 | 11 | class UnknownRevId(KeyError): 12 | pass 13 | 14 | 15 | def parse_table(buffer, offset, type_select): 16 | header = Vega10_PPTable_Generic_SubTable_Header.from_buffer(buffer, offset) 17 | return type_select(header.ucRevId).from_buffer(buffer, offset) 18 | 19 | 20 | def parse_array_table(buffer, offset, table_type, type_select=None): 21 | entries_name, entries_type = table_type._fields_[-1] 22 | assert entries_type._length_ == 1 23 | 24 | header = table_type.from_buffer(buffer, offset) 25 | 26 | if type_select is None: 27 | entry_type = entries_type._type_ 28 | else: 29 | entry_type = type_select(header.ucRevId) 30 | 31 | class DynamicArrayTable(ctypes.LittleEndianStructure): 32 | _pack_ = table_type._pack_ 33 | _fields_ = table_type._fields_[:-1] + [(entries_name, entry_type * header.ucNumEntries)] 34 | wrapped_type = table_type 35 | 36 | return DynamicArrayTable.from_buffer(buffer, offset) 37 | 38 | 39 | def fan_table_type(rev_id): 40 | if rev_id == 10: 41 | return ATOM_Vega10_Fan_Table 42 | elif rev_id == 0xb: 43 | return ATOM_Vega10_Fan_Table_V2 44 | elif rev_id > 0xb: 45 | return ATOM_Vega10_Fan_Table_V3 46 | else: 47 | raise UnknownRevId(rev_id) 48 | 49 | 50 | def powertune_table_type(rev_id): 51 | if rev_id == 5: 52 | return ATOM_Vega10_PowerTune_Table 53 | elif rev_id == 6: 54 | return ATOM_Vega10_PowerTune_Table_V2 55 | else: 56 | return ATOM_Vega10_PowerTune_Table_V3 57 | 58 | 59 | def gfxclk_record_type(rev_id): 60 | if rev_id == 0: 61 | return ATOM_Vega10_GFXCLK_Dependency_Record 62 | elif rev_id == 1: 63 | return ATOM_Vega10_GFXCLK_Dependency_Record_V2 64 | else: 65 | raise UnknownRevId(rev_id) 66 | 67 | 68 | def parse(buffer): 69 | main_table = ATOM_Vega10_POWERPLAYTABLE.from_buffer(buffer) 70 | parse_result = {'Main': main_table} 71 | 72 | def table(name, parse_func, *args, **kwargs): 73 | offset = getattr(main_table, f'us{name}Offset') 74 | if offset > 0: 75 | try: 76 | parse_result[name] = parse_func(buffer, offset, *args, **kwargs) 77 | except UnknownRevId as ex: 78 | LOG.warning("%s: unknown ucRevId: %s", name, ex.args[0]) 79 | 80 | table('StateArray', parse_array_table, ATOM_Vega10_State_Array) 81 | table('SocclkDependencyTable', parse_array_table, ATOM_Vega10_SOCCLK_Dependency_Table) 82 | table('MclkDependencyTable', parse_array_table, ATOM_Vega10_MCLK_Dependency_Table) 83 | table('GfxclkDependencyTable', parse_array_table, ATOM_Vega10_GFXCLK_Dependency_Table, gfxclk_record_type) 84 | table('DcefclkDependencyTable', parse_array_table, ATOM_Vega10_DCEFCLK_Dependency_Table) 85 | table('PixclkDependencyTable', parse_array_table, ATOM_Vega10_PIXCLK_Dependency_Table) 86 | table('DispClkDependencyTable', parse_array_table, ATOM_Vega10_DISPCLK_Dependency_Table) 87 | table('PhyClkDependencyTable', parse_array_table, ATOM_Vega10_PHYCLK_Dependency_Table) 88 | table('VddcLookupTable', parse_array_table, ATOM_Vega10_Voltage_Lookup_Table) 89 | table('VddmemLookupTable', parse_array_table, ATOM_Vega10_Voltage_Lookup_Table) 90 | table('VddciLookupTable', parse_array_table, ATOM_Vega10_Voltage_Lookup_Table) 91 | table('MMDependencyTable', parse_array_table, ATOM_Vega10_MM_Dependency_Table) 92 | table('VCEStateTable', parse_array_table, ATOM_Vega10_VCE_State_Table) 93 | table('HardLimitTable', parse_array_table, ATOM_Vega10_Hard_Limit_Table) 94 | table('PCIETable', parse_array_table, ATOM_Vega10_PCIE_Table) 95 | 96 | table('FanTable', parse_table, fan_table_type) 97 | table('PowerTuneTable', parse_table, powertune_table_type) 98 | table('ThermalController', parse_table, lambda _: ATOM_Vega10_Thermal_Controller) 99 | 100 | return collections.namedtuple('ParseResult', parse_result.keys())(*parse_result.values()) 101 | -------------------------------------------------------------------------------- /generate_ctypes.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import io 3 | import logging 4 | import os 5 | import tokenize 6 | 7 | import ctypeslib.codegen.codegenerator 8 | import ctypeslib.codegen.typedesc 9 | 10 | 11 | def rewrite_ctypes_little_endian(readline): 12 | prev_tokens = [None, None] 13 | 14 | def rewrite_token(token): 15 | if prev_tokens[0] is None or prev_tokens[1] is None: 16 | return token 17 | 18 | if prev_tokens[0].string != '.' or prev_tokens[1].string != 'ctypes': 19 | return token 20 | 21 | if token.string == 'Structure': 22 | return (token.type, 'LittleEndianStructure') + token[2:] 23 | elif token.string == 'Union': 24 | return (token.type, 'LittleEndianUnion') + token[2:] 25 | else: 26 | return token 27 | 28 | for token in tokenize.tokenize(readline): 29 | yield rewrite_token(token) 30 | 31 | prev_tokens[1] = prev_tokens[0] 32 | prev_tokens[0] = token 33 | 34 | 35 | def generate_ctypes(header_file, py_file, cpp_flags): 36 | logging.info("Generating %s from %s", py_file, header_file) 37 | 38 | buffer = io.StringIO() 39 | ctypeslib.codegen.codegenerator.generate_code([header_file], buffer, 40 | types=(ctypeslib.codegen.typedesc.Alias, 41 | ctypeslib.codegen.typedesc.Structure, 42 | ctypeslib.codegen.typedesc.Variable, 43 | ctypeslib.codegen.typedesc.Enumeration, 44 | ctypeslib.codegen.typedesc.Function, 45 | ctypeslib.codegen.typedesc.Macro, 46 | ctypeslib.codegen.typedesc.Typedef, 47 | ctypeslib.codegen.typedesc.Union), 48 | filter_location=True, 49 | flags=cpp_flags) 50 | 51 | bytes_buffer = io.BytesIO(buffer.getvalue().encode()) 52 | bytes = tokenize.untokenize(rewrite_ctypes_little_endian(bytes_buffer.readline)) 53 | 54 | with open(py_file, 'wb') as outfile: 55 | outfile.write(bytes) 56 | 57 | 58 | def run(kernel_dir, log_level): 59 | logging.basicConfig(level=log_level) 60 | 61 | kernel_dir = os.path.abspath(kernel_dir) 62 | out_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)), 'src', 'amdgpu_pptable', 'generated') 63 | 64 | powerplay_old_dir = os.path.join(kernel_dir, 'drivers/gpu/drm/amd/powerplay') 65 | powerplay_new_dir = os.path.join(kernel_dir, 'drivers/gpu/drm/amd/pm/powerplay') 66 | 67 | powerplay_dir = powerplay_old_dir if os.path.exists(powerplay_old_dir) else powerplay_new_dir 68 | 69 | powerplay_inc_old_dir = os.path.join(powerplay_old_dir, 'inc') 70 | powerplay_inc_new_dir = os.path.join(kernel_dir, 'drivers/gpu/drm/amd/pm/inc') 71 | 72 | powerplay_inc_dir = powerplay_inc_old_dir if os.path.exists(powerplay_inc_old_dir) else powerplay_inc_new_dir 73 | 74 | header_file = os.path.join(powerplay_dir, 'hwmgr/vega10_pptable.h') 75 | includes = [ 76 | os.path.join(kernel_dir, 'drivers/gpu/drm/amd/include/atom-types.h'), 77 | os.path.join(kernel_dir, 'drivers/gpu/drm/amd/include/atomfirmware.h') 78 | ] 79 | py_file = os.path.join(out_dir, 'vega10_pptable.py') 80 | 81 | cpp_flags = ['-include', 'stdint.h'] 82 | for inc in includes: 83 | cpp_flags.extend(('-include', inc)) 84 | 85 | generate_ctypes(header_file, py_file, cpp_flags) 86 | 87 | header_file = os.path.join(powerplay_dir, 'hwmgr/pptable_v1_0.h') 88 | py_file = os.path.join(out_dir, 'pptable_v1_0.py') 89 | includes = [ 90 | os.path.join(kernel_dir, 'drivers/gpu/drm/amd/include/atom-types.h'), 91 | os.path.join(kernel_dir, 'drivers/gpu/drm/amd/include/atombios.h') 92 | ] 93 | cpp_flags = ['-include', 'stdint.h'] 94 | for inc in includes: 95 | cpp_flags.extend(('-include', inc)) 96 | 97 | generate_ctypes(header_file, py_file, cpp_flags) 98 | 99 | header_file = os.path.join(powerplay_inc_dir, 'smu_v11_0_pptable.h') 100 | py_file = os.path.join(out_dir, 'smu_v11_0_pptable_navi10.py') 101 | includes = [ 102 | os.path.join(kernel_dir, 'drivers/gpu/drm/amd/include/atom-types.h'), 103 | os.path.join(kernel_dir, 'drivers/gpu/drm/amd/include/atomfirmware.h'), 104 | os.path.join(powerplay_inc_dir, 'smu11_driver_if_navi10.h') 105 | ] 106 | cpp_flags = ['-include', 'stdint.h'] 107 | for inc in includes: 108 | cpp_flags.extend(('-include', inc)) 109 | 110 | generate_ctypes(header_file, py_file, cpp_flags) 111 | 112 | 113 | def main(): 114 | parser = argparse.ArgumentParser( 115 | description="Generate Python modules from kernel headers" 116 | ) 117 | parser.add_argument( 118 | "-k", "--kernel-dir", required=True, help="kernel source directory" 119 | ) 120 | parser.add_argument( 121 | "--log-level", type=logging.getLevelName, default=logging.INFO 122 | ) 123 | run(**vars(parser.parse_args())) 124 | 125 | 126 | if __name__ == '__main__': 127 | main() 128 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/generated/smu_v11_0_pptable_navi10.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # 3 | # TARGET arch is: ['-include', 'stdint.h', '-include', '/home/amezin/linux/drivers/gpu/drm/amd/include/atom-types.h', '-include', '/home/amezin/linux/drivers/gpu/drm/amd/include/atomfirmware.h', '-include', '/home/amezin/linux/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h'] 4 | # WORD_SIZE is: 8 5 | # POINTER_SIZE is: 8 6 | # LONGDOUBLE_SIZE is: 16 7 | # 8 | import ctypes 9 | 10 | 11 | 12 | 13 | class struct_atom_common_table_header(ctypes.LittleEndianStructure): 14 | _pack_ = True # source:False 15 | _fields_ = [ 16 | ('structuresize', ctypes.c_uint16), 17 | ('format_revision', ctypes.c_ubyte), 18 | ('content_revision', ctypes.c_ubyte), 19 | ] 20 | 21 | class struct_c__SA_I2cControllerConfig_t(ctypes.LittleEndianStructure): 22 | _pack_ = True # source:False 23 | _fields_ = [ 24 | ('Enabled', ctypes.c_ubyte), 25 | ('Speed', ctypes.c_ubyte), 26 | ('Padding', ctypes.c_ubyte * 2), 27 | ('SlaveAddress', ctypes.c_uint32), 28 | ('ControllerPort', ctypes.c_ubyte), 29 | ('ControllerName', ctypes.c_ubyte), 30 | ('ThermalThrotter', ctypes.c_ubyte), 31 | ('I2cProtocol', ctypes.c_ubyte), 32 | ] 33 | 34 | class struct_c__SA_QuadraticInt_t(ctypes.LittleEndianStructure): 35 | _pack_ = True # source:False 36 | _fields_ = [ 37 | ('a', ctypes.c_uint32), 38 | ('b', ctypes.c_uint32), 39 | ('c', ctypes.c_uint32), 40 | ] 41 | 42 | class struct_c__SA_LinearInt_t(ctypes.LittleEndianStructure): 43 | _pack_ = True # source:False 44 | _fields_ = [ 45 | ('m', ctypes.c_uint32), 46 | ('b', ctypes.c_uint32), 47 | ] 48 | 49 | class struct_c__SA_DroopInt_t(ctypes.LittleEndianStructure): 50 | _pack_ = True # source:False 51 | _fields_ = [ 52 | ('a', ctypes.c_uint32), 53 | ('b', ctypes.c_uint32), 54 | ('c', ctypes.c_uint32), 55 | ] 56 | 57 | class struct_c__SA_DpmDescriptor_t(ctypes.LittleEndianStructure): 58 | _pack_ = True # source:False 59 | _fields_ = [ 60 | ('VoltageMode', ctypes.c_ubyte), 61 | ('SnapToDiscrete', ctypes.c_ubyte), 62 | ('NumDiscreteLevels', ctypes.c_ubyte), 63 | ('Padding', ctypes.c_ubyte), 64 | ('ConversionToAvfsClk', struct_c__SA_LinearInt_t), 65 | ('SsCurve', struct_c__SA_QuadraticInt_t), 66 | ] 67 | 68 | class struct_c__SA_PPTable_t(ctypes.LittleEndianStructure): 69 | _pack_ = True # source:False 70 | _fields_ = [ 71 | ('Version', ctypes.c_uint32), 72 | ('FeaturesToRun', ctypes.c_uint32 * 2), 73 | ('SocketPowerLimitAc', ctypes.c_uint16 * 4), 74 | ('SocketPowerLimitAcTau', ctypes.c_uint16 * 4), 75 | ('SocketPowerLimitDc', ctypes.c_uint16 * 4), 76 | ('SocketPowerLimitDcTau', ctypes.c_uint16 * 4), 77 | ('TdcLimitSoc', ctypes.c_uint16), 78 | ('TdcLimitSocTau', ctypes.c_uint16), 79 | ('TdcLimitGfx', ctypes.c_uint16), 80 | ('TdcLimitGfxTau', ctypes.c_uint16), 81 | ('TedgeLimit', ctypes.c_uint16), 82 | ('ThotspotLimit', ctypes.c_uint16), 83 | ('TmemLimit', ctypes.c_uint16), 84 | ('Tvr_gfxLimit', ctypes.c_uint16), 85 | ('Tvr_mem0Limit', ctypes.c_uint16), 86 | ('Tvr_mem1Limit', ctypes.c_uint16), 87 | ('Tvr_socLimit', ctypes.c_uint16), 88 | ('Tliquid0Limit', ctypes.c_uint16), 89 | ('Tliquid1Limit', ctypes.c_uint16), 90 | ('TplxLimit', ctypes.c_uint16), 91 | ('FitLimit', ctypes.c_uint32), 92 | ('PpmPowerLimit', ctypes.c_uint16), 93 | ('PpmTemperatureThreshold', ctypes.c_uint16), 94 | ('ThrottlerControlMask', ctypes.c_uint32), 95 | ('FwDStateMask', ctypes.c_uint32), 96 | ('UlvVoltageOffsetSoc', ctypes.c_uint16), 97 | ('UlvVoltageOffsetGfx', ctypes.c_uint16), 98 | ('GceaLinkMgrIdleThreshold', ctypes.c_ubyte), 99 | ('paddingRlcUlvParams', ctypes.c_ubyte * 3), 100 | ('UlvSmnclkDid', ctypes.c_ubyte), 101 | ('UlvMp1clkDid', ctypes.c_ubyte), 102 | ('UlvGfxclkBypass', ctypes.c_ubyte), 103 | ('Padding234', ctypes.c_ubyte), 104 | ('MinVoltageUlvGfx', ctypes.c_uint16), 105 | ('MinVoltageUlvSoc', ctypes.c_uint16), 106 | ('MinVoltageGfx', ctypes.c_uint16), 107 | ('MinVoltageSoc', ctypes.c_uint16), 108 | ('MaxVoltageGfx', ctypes.c_uint16), 109 | ('MaxVoltageSoc', ctypes.c_uint16), 110 | ('LoadLineResistanceGfx', ctypes.c_uint16), 111 | ('LoadLineResistanceSoc', ctypes.c_uint16), 112 | ('DpmDescriptor', struct_c__SA_DpmDescriptor_t * 9), 113 | ('FreqTableGfx', ctypes.c_uint16 * 16), 114 | ('FreqTableVclk', ctypes.c_uint16 * 8), 115 | ('FreqTableDclk', ctypes.c_uint16 * 8), 116 | ('FreqTableSocclk', ctypes.c_uint16 * 8), 117 | ('FreqTableUclk', ctypes.c_uint16 * 4), 118 | ('FreqTableDcefclk', ctypes.c_uint16 * 8), 119 | ('FreqTableDispclk', ctypes.c_uint16 * 8), 120 | ('FreqTablePixclk', ctypes.c_uint16 * 8), 121 | ('FreqTablePhyclk', ctypes.c_uint16 * 8), 122 | ('Paddingclks', ctypes.c_uint32 * 16), 123 | ('DcModeMaxFreq', ctypes.c_uint16 * 9), 124 | ('Padding8_Clks', ctypes.c_uint16), 125 | ('FreqTableUclkDiv', ctypes.c_ubyte * 4), 126 | ('Mp0clkFreq', ctypes.c_uint16 * 2), 127 | ('Mp0DpmVoltage', ctypes.c_uint16 * 2), 128 | ('MemVddciVoltage', ctypes.c_uint16 * 4), 129 | ('MemMvddVoltage', ctypes.c_uint16 * 4), 130 | ('GfxclkFgfxoffEntry', ctypes.c_uint16), 131 | ('GfxclkFinit', ctypes.c_uint16), 132 | ('GfxclkFidle', ctypes.c_uint16), 133 | ('GfxclkSlewRate', ctypes.c_uint16), 134 | ('GfxclkFopt', ctypes.c_uint16), 135 | ('Padding567', ctypes.c_ubyte * 2), 136 | ('GfxclkDsMaxFreq', ctypes.c_uint16), 137 | ('GfxclkSource', ctypes.c_ubyte), 138 | ('Padding456', ctypes.c_ubyte), 139 | ('LowestUclkReservedForUlv', ctypes.c_ubyte), 140 | ('paddingUclk', ctypes.c_ubyte * 3), 141 | ('MemoryType', ctypes.c_ubyte), 142 | ('MemoryChannels', ctypes.c_ubyte), 143 | ('PaddingMem', ctypes.c_ubyte * 2), 144 | ('PcieGenSpeed', ctypes.c_ubyte * 2), 145 | ('PcieLaneCount', ctypes.c_ubyte * 2), 146 | ('LclkFreq', ctypes.c_uint16 * 2), 147 | ('EnableTdpm', ctypes.c_uint16), 148 | ('TdpmHighHystTemperature', ctypes.c_uint16), 149 | ('TdpmLowHystTemperature', ctypes.c_uint16), 150 | ('GfxclkFreqHighTempLimit', ctypes.c_uint16), 151 | ('FanStopTemp', ctypes.c_uint16), 152 | ('FanStartTemp', ctypes.c_uint16), 153 | ('FanGainEdge', ctypes.c_uint16), 154 | ('FanGainHotspot', ctypes.c_uint16), 155 | ('FanGainLiquid0', ctypes.c_uint16), 156 | ('FanGainLiquid1', ctypes.c_uint16), 157 | ('FanGainVrGfx', ctypes.c_uint16), 158 | ('FanGainVrSoc', ctypes.c_uint16), 159 | ('FanGainVrMem0', ctypes.c_uint16), 160 | ('FanGainVrMem1', ctypes.c_uint16), 161 | ('FanGainPlx', ctypes.c_uint16), 162 | ('FanGainMem', ctypes.c_uint16), 163 | ('FanPwmMin', ctypes.c_uint16), 164 | ('FanAcousticLimitRpm', ctypes.c_uint16), 165 | ('FanThrottlingRpm', ctypes.c_uint16), 166 | ('FanMaximumRpm', ctypes.c_uint16), 167 | ('FanTargetTemperature', ctypes.c_uint16), 168 | ('FanTargetGfxclk', ctypes.c_uint16), 169 | ('FanTempInputSelect', ctypes.c_ubyte), 170 | ('FanPadding', ctypes.c_ubyte), 171 | ('FanZeroRpmEnable', ctypes.c_ubyte), 172 | ('FanTachEdgePerRev', ctypes.c_ubyte), 173 | ('FuzzyFan_ErrorSetDelta', ctypes.c_int16), 174 | ('FuzzyFan_ErrorRateSetDelta', ctypes.c_int16), 175 | ('FuzzyFan_PwmSetDelta', ctypes.c_int16), 176 | ('FuzzyFan_Reserved', ctypes.c_uint16), 177 | ('OverrideAvfsGb', ctypes.c_ubyte * 2), 178 | ('Padding8_Avfs', ctypes.c_ubyte * 2), 179 | ('qAvfsGb', struct_c__SA_QuadraticInt_t * 2), 180 | ('dBtcGbGfxPll', struct_c__SA_DroopInt_t), 181 | ('dBtcGbGfxDfll', struct_c__SA_DroopInt_t), 182 | ('dBtcGbSoc', struct_c__SA_DroopInt_t), 183 | ('qAgingGb', struct_c__SA_LinearInt_t * 2), 184 | ('qStaticVoltageOffset', struct_c__SA_QuadraticInt_t * 2), 185 | ('DcTol', ctypes.c_uint16 * 2), 186 | ('DcBtcEnabled', ctypes.c_ubyte * 2), 187 | ('Padding8_GfxBtc', ctypes.c_ubyte * 2), 188 | ('DcBtcMin', ctypes.c_uint16 * 2), 189 | ('DcBtcMax', ctypes.c_uint16 * 2), 190 | ('DebugOverrides', ctypes.c_uint32), 191 | ('ReservedEquation0', struct_c__SA_QuadraticInt_t), 192 | ('ReservedEquation1', struct_c__SA_QuadraticInt_t), 193 | ('ReservedEquation2', struct_c__SA_QuadraticInt_t), 194 | ('ReservedEquation3', struct_c__SA_QuadraticInt_t), 195 | ('TotalPowerConfig', ctypes.c_ubyte), 196 | ('TotalPowerSpare1', ctypes.c_ubyte), 197 | ('TotalPowerSpare2', ctypes.c_uint16), 198 | ('PccThresholdLow', ctypes.c_uint16), 199 | ('PccThresholdHigh', ctypes.c_uint16), 200 | ('MGpuFanBoostLimitRpm', ctypes.c_uint32), 201 | ('PaddingAPCC', ctypes.c_uint32 * 5), 202 | ('VDDGFX_TVmin', ctypes.c_uint16), 203 | ('VDDSOC_TVmin', ctypes.c_uint16), 204 | ('VDDGFX_Vmin_HiTemp', ctypes.c_uint16), 205 | ('VDDGFX_Vmin_LoTemp', ctypes.c_uint16), 206 | ('VDDSOC_Vmin_HiTemp', ctypes.c_uint16), 207 | ('VDDSOC_Vmin_LoTemp', ctypes.c_uint16), 208 | ('VDDGFX_TVminHystersis', ctypes.c_uint16), 209 | ('VDDSOC_TVminHystersis', ctypes.c_uint16), 210 | ('BtcConfig', ctypes.c_uint32), 211 | ('SsFmin', ctypes.c_uint16 * 10), 212 | ('DcBtcGb', ctypes.c_uint16 * 2), 213 | ('Reserved', ctypes.c_uint32 * 8), 214 | ('I2cControllers', struct_c__SA_I2cControllerConfig_t * 8), 215 | ('MaxVoltageStepGfx', ctypes.c_uint16), 216 | ('MaxVoltageStepSoc', ctypes.c_uint16), 217 | ('VddGfxVrMapping', ctypes.c_ubyte), 218 | ('VddSocVrMapping', ctypes.c_ubyte), 219 | ('VddMem0VrMapping', ctypes.c_ubyte), 220 | ('VddMem1VrMapping', ctypes.c_ubyte), 221 | ('GfxUlvPhaseSheddingMask', ctypes.c_ubyte), 222 | ('SocUlvPhaseSheddingMask', ctypes.c_ubyte), 223 | ('ExternalSensorPresent', ctypes.c_ubyte), 224 | ('Padding8_V', ctypes.c_ubyte), 225 | ('GfxMaxCurrent', ctypes.c_uint16), 226 | ('GfxOffset', ctypes.c_byte), 227 | ('Padding_TelemetryGfx', ctypes.c_ubyte), 228 | ('SocMaxCurrent', ctypes.c_uint16), 229 | ('SocOffset', ctypes.c_byte), 230 | ('Padding_TelemetrySoc', ctypes.c_ubyte), 231 | ('Mem0MaxCurrent', ctypes.c_uint16), 232 | ('Mem0Offset', ctypes.c_byte), 233 | ('Padding_TelemetryMem0', ctypes.c_ubyte), 234 | ('Mem1MaxCurrent', ctypes.c_uint16), 235 | ('Mem1Offset', ctypes.c_byte), 236 | ('Padding_TelemetryMem1', ctypes.c_ubyte), 237 | ('AcDcGpio', ctypes.c_ubyte), 238 | ('AcDcPolarity', ctypes.c_ubyte), 239 | ('VR0HotGpio', ctypes.c_ubyte), 240 | ('VR0HotPolarity', ctypes.c_ubyte), 241 | ('VR1HotGpio', ctypes.c_ubyte), 242 | ('VR1HotPolarity', ctypes.c_ubyte), 243 | ('GthrGpio', ctypes.c_ubyte), 244 | ('GthrPolarity', ctypes.c_ubyte), 245 | ('LedPin0', ctypes.c_ubyte), 246 | ('LedPin1', ctypes.c_ubyte), 247 | ('LedPin2', ctypes.c_ubyte), 248 | ('padding8_4', ctypes.c_ubyte), 249 | ('PllGfxclkSpreadEnabled', ctypes.c_ubyte), 250 | ('PllGfxclkSpreadPercent', ctypes.c_ubyte), 251 | ('PllGfxclkSpreadFreq', ctypes.c_uint16), 252 | ('DfllGfxclkSpreadEnabled', ctypes.c_ubyte), 253 | ('DfllGfxclkSpreadPercent', ctypes.c_ubyte), 254 | ('DfllGfxclkSpreadFreq', ctypes.c_uint16), 255 | ('UclkSpreadEnabled', ctypes.c_ubyte), 256 | ('UclkSpreadPercent', ctypes.c_ubyte), 257 | ('UclkSpreadFreq', ctypes.c_uint16), 258 | ('SoclkSpreadEnabled', ctypes.c_ubyte), 259 | ('SocclkSpreadPercent', ctypes.c_ubyte), 260 | ('SocclkSpreadFreq', ctypes.c_uint16), 261 | ('TotalBoardPower', ctypes.c_uint16), 262 | ('BoardPadding', ctypes.c_uint16), 263 | ('MvddRatio', ctypes.c_uint32), 264 | ('RenesesLoadLineEnabled', ctypes.c_ubyte), 265 | ('GfxLoadlineResistance', ctypes.c_ubyte), 266 | ('SocLoadlineResistance', ctypes.c_ubyte), 267 | ('Padding8_Loadline', ctypes.c_ubyte), 268 | ('BoardReserved', ctypes.c_uint32 * 8), 269 | ('MmHubPadding', ctypes.c_uint32 * 8), 270 | ] 271 | 272 | SMU_11_0_PPTABLE_H = True # macro 273 | SMU_11_0_TABLE_FORMAT_REVISION = 12 # macro 274 | SMU_11_0_PP_PLATFORM_CAP_POWERPLAY = 0x1 # macro 275 | SMU_11_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE = 0x2 # macro 276 | SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC = 0x4 # macro 277 | SMU_11_0_PP_PLATFORM_CAP_BACO = 0x8 # macro 278 | SMU_11_0_PP_PLATFORM_CAP_MACO = 0x10 # macro 279 | SMU_11_0_PP_PLATFORM_CAP_SHADOWPSTATE = 0x20 # macro 280 | SMU_11_0_PP_THERMALCONTROLLER_NONE = 0 # macro 281 | SMU_11_0_PP_OVERDRIVE_VERSION = 0x0800 # macro 282 | SMU_11_0_PP_POWERSAVINGCLOCK_VERSION = 0x0100 # macro 283 | 284 | # values for enumeration 'SMU_11_0_ODFEATURE_CAP' 285 | SMU_11_0_ODFEATURE_CAP__enumvalues = { 286 | 0: 'SMU_11_0_ODCAP_GFXCLK_LIMITS', 287 | 1: 'SMU_11_0_ODCAP_GFXCLK_CURVE', 288 | 2: 'SMU_11_0_ODCAP_UCLK_MAX', 289 | 3: 'SMU_11_0_ODCAP_POWER_LIMIT', 290 | 4: 'SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT', 291 | 5: 'SMU_11_0_ODCAP_FAN_SPEED_MIN', 292 | 6: 'SMU_11_0_ODCAP_TEMPERATURE_FAN', 293 | 7: 'SMU_11_0_ODCAP_TEMPERATURE_SYSTEM', 294 | 8: 'SMU_11_0_ODCAP_MEMORY_TIMING_TUNE', 295 | 9: 'SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL', 296 | 10: 'SMU_11_0_ODCAP_AUTO_UV_ENGINE', 297 | 11: 'SMU_11_0_ODCAP_AUTO_OC_ENGINE', 298 | 12: 'SMU_11_0_ODCAP_AUTO_OC_MEMORY', 299 | 13: 'SMU_11_0_ODCAP_FAN_CURVE', 300 | 14: 'SMU_11_0_ODCAP_COUNT', 301 | } 302 | SMU_11_0_ODCAP_GFXCLK_LIMITS = 0 303 | SMU_11_0_ODCAP_GFXCLK_CURVE = 1 304 | SMU_11_0_ODCAP_UCLK_MAX = 2 305 | SMU_11_0_ODCAP_POWER_LIMIT = 3 306 | SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT = 4 307 | SMU_11_0_ODCAP_FAN_SPEED_MIN = 5 308 | SMU_11_0_ODCAP_TEMPERATURE_FAN = 6 309 | SMU_11_0_ODCAP_TEMPERATURE_SYSTEM = 7 310 | SMU_11_0_ODCAP_MEMORY_TIMING_TUNE = 8 311 | SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL = 9 312 | SMU_11_0_ODCAP_AUTO_UV_ENGINE = 10 313 | SMU_11_0_ODCAP_AUTO_OC_ENGINE = 11 314 | SMU_11_0_ODCAP_AUTO_OC_MEMORY = 12 315 | SMU_11_0_ODCAP_FAN_CURVE = 13 316 | SMU_11_0_ODCAP_COUNT = 14 317 | SMU_11_0_ODFEATURE_CAP = ctypes.c_int # enum 318 | 319 | # values for enumeration 'SMU_11_0_ODFEATURE_ID' 320 | SMU_11_0_ODFEATURE_ID__enumvalues = { 321 | 1: 'SMU_11_0_ODFEATURE_GFXCLK_LIMITS', 322 | 2: 'SMU_11_0_ODFEATURE_GFXCLK_CURVE', 323 | 4: 'SMU_11_0_ODFEATURE_UCLK_MAX', 324 | 8: 'SMU_11_0_ODFEATURE_POWER_LIMIT', 325 | 16: 'SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT', 326 | 32: 'SMU_11_0_ODFEATURE_FAN_SPEED_MIN', 327 | 64: 'SMU_11_0_ODFEATURE_TEMPERATURE_FAN', 328 | 128: 'SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM', 329 | 256: 'SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE', 330 | 512: 'SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL', 331 | 1024: 'SMU_11_0_ODFEATURE_AUTO_UV_ENGINE', 332 | 2048: 'SMU_11_0_ODFEATURE_AUTO_OC_ENGINE', 333 | 4096: 'SMU_11_0_ODFEATURE_AUTO_OC_MEMORY', 334 | 8192: 'SMU_11_0_ODFEATURE_FAN_CURVE', 335 | 14: 'SMU_11_0_ODFEATURE_COUNT', 336 | } 337 | SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 1 338 | SMU_11_0_ODFEATURE_GFXCLK_CURVE = 2 339 | SMU_11_0_ODFEATURE_UCLK_MAX = 4 340 | SMU_11_0_ODFEATURE_POWER_LIMIT = 8 341 | SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 16 342 | SMU_11_0_ODFEATURE_FAN_SPEED_MIN = 32 343 | SMU_11_0_ODFEATURE_TEMPERATURE_FAN = 64 344 | SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM = 128 345 | SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE = 256 346 | SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 512 347 | SMU_11_0_ODFEATURE_AUTO_UV_ENGINE = 1024 348 | SMU_11_0_ODFEATURE_AUTO_OC_ENGINE = 2048 349 | SMU_11_0_ODFEATURE_AUTO_OC_MEMORY = 4096 350 | SMU_11_0_ODFEATURE_FAN_CURVE = 8192 351 | SMU_11_0_ODFEATURE_COUNT = 14 352 | SMU_11_0_ODFEATURE_ID = ctypes.c_int # enum 353 | SMU_11_0_MAX_ODFEATURE = 32 # macro 354 | 355 | # values for enumeration 'SMU_11_0_ODSETTING_ID' 356 | SMU_11_0_ODSETTING_ID__enumvalues = { 357 | 0: 'SMU_11_0_ODSETTING_GFXCLKFMAX', 358 | 1: 'SMU_11_0_ODSETTING_GFXCLKFMIN', 359 | 2: 'SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1', 360 | 3: 'SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1', 361 | 4: 'SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2', 362 | 5: 'SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2', 363 | 6: 'SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3', 364 | 7: 'SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3', 365 | 8: 'SMU_11_0_ODSETTING_UCLKFMAX', 366 | 9: 'SMU_11_0_ODSETTING_POWERPERCENTAGE', 367 | 10: 'SMU_11_0_ODSETTING_FANRPMMIN', 368 | 11: 'SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT', 369 | 12: 'SMU_11_0_ODSETTING_FANTARGETTEMPERATURE', 370 | 13: 'SMU_11_0_ODSETTING_OPERATINGTEMPMAX', 371 | 14: 'SMU_11_0_ODSETTING_ACTIMING', 372 | 15: 'SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL', 373 | 16: 'SMU_11_0_ODSETTING_AUTOUVENGINE', 374 | 17: 'SMU_11_0_ODSETTING_AUTOOCENGINE', 375 | 18: 'SMU_11_0_ODSETTING_AUTOOCMEMORY', 376 | 19: 'SMU_11_0_ODSETTING_COUNT', 377 | } 378 | SMU_11_0_ODSETTING_GFXCLKFMAX = 0 379 | SMU_11_0_ODSETTING_GFXCLKFMIN = 1 380 | SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1 = 2 381 | SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1 = 3 382 | SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2 = 4 383 | SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2 = 5 384 | SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3 = 6 385 | SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3 = 7 386 | SMU_11_0_ODSETTING_UCLKFMAX = 8 387 | SMU_11_0_ODSETTING_POWERPERCENTAGE = 9 388 | SMU_11_0_ODSETTING_FANRPMMIN = 10 389 | SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT = 11 390 | SMU_11_0_ODSETTING_FANTARGETTEMPERATURE = 12 391 | SMU_11_0_ODSETTING_OPERATINGTEMPMAX = 13 392 | SMU_11_0_ODSETTING_ACTIMING = 14 393 | SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL = 15 394 | SMU_11_0_ODSETTING_AUTOUVENGINE = 16 395 | SMU_11_0_ODSETTING_AUTOOCENGINE = 17 396 | SMU_11_0_ODSETTING_AUTOOCMEMORY = 18 397 | SMU_11_0_ODSETTING_COUNT = 19 398 | SMU_11_0_ODSETTING_ID = ctypes.c_int # enum 399 | SMU_11_0_MAX_ODSETTING = 32 # macro 400 | class struct_smu_11_0_overdrive_table(ctypes.LittleEndianStructure): 401 | _pack_ = True # source:True 402 | _fields_ = [ 403 | ('revision', ctypes.c_ubyte), 404 | ('reserve', ctypes.c_ubyte * 3), 405 | ('feature_count', ctypes.c_uint32), 406 | ('setting_count', ctypes.c_uint32), 407 | ('cap', ctypes.c_ubyte * 32), 408 | ('max', ctypes.c_uint32 * 32), 409 | ('min', ctypes.c_uint32 * 32), 410 | ] 411 | 412 | 413 | # values for enumeration 'SMU_11_0_PPCLOCK_ID' 414 | SMU_11_0_PPCLOCK_ID__enumvalues = { 415 | 0: 'SMU_11_0_PPCLOCK_GFXCLK', 416 | 1: 'SMU_11_0_PPCLOCK_VCLK', 417 | 2: 'SMU_11_0_PPCLOCK_DCLK', 418 | 3: 'SMU_11_0_PPCLOCK_ECLK', 419 | 4: 'SMU_11_0_PPCLOCK_SOCCLK', 420 | 5: 'SMU_11_0_PPCLOCK_UCLK', 421 | 6: 'SMU_11_0_PPCLOCK_DCEFCLK', 422 | 7: 'SMU_11_0_PPCLOCK_DISPCLK', 423 | 8: 'SMU_11_0_PPCLOCK_PIXCLK', 424 | 9: 'SMU_11_0_PPCLOCK_PHYCLK', 425 | 10: 'SMU_11_0_PPCLOCK_COUNT', 426 | } 427 | SMU_11_0_PPCLOCK_GFXCLK = 0 428 | SMU_11_0_PPCLOCK_VCLK = 1 429 | SMU_11_0_PPCLOCK_DCLK = 2 430 | SMU_11_0_PPCLOCK_ECLK = 3 431 | SMU_11_0_PPCLOCK_SOCCLK = 4 432 | SMU_11_0_PPCLOCK_UCLK = 5 433 | SMU_11_0_PPCLOCK_DCEFCLK = 6 434 | SMU_11_0_PPCLOCK_DISPCLK = 7 435 | SMU_11_0_PPCLOCK_PIXCLK = 8 436 | SMU_11_0_PPCLOCK_PHYCLK = 9 437 | SMU_11_0_PPCLOCK_COUNT = 10 438 | SMU_11_0_PPCLOCK_ID = ctypes.c_int # enum 439 | SMU_11_0_MAX_PPCLOCK = 16 # macro 440 | class struct_smu_11_0_power_saving_clock_table(ctypes.LittleEndianStructure): 441 | _pack_ = True # source:True 442 | _fields_ = [ 443 | ('revision', ctypes.c_ubyte), 444 | ('reserve', ctypes.c_ubyte * 3), 445 | ('count', ctypes.c_uint32), 446 | ('max', ctypes.c_uint32 * 16), 447 | ('min', ctypes.c_uint32 * 16), 448 | ] 449 | 450 | class struct_smu_11_0_powerplay_table(ctypes.LittleEndianStructure): 451 | _pack_ = True # source:True 452 | _fields_ = [ 453 | ('header', struct_atom_common_table_header), 454 | ('table_revision', ctypes.c_ubyte), 455 | ('table_size', ctypes.c_uint16), 456 | ('golden_pp_id', ctypes.c_uint32), 457 | ('golden_revision', ctypes.c_uint32), 458 | ('format_id', ctypes.c_uint16), 459 | ('platform_caps', ctypes.c_uint32), 460 | ('thermal_controller_type', ctypes.c_ubyte), 461 | ('small_power_limit1', ctypes.c_uint16), 462 | ('small_power_limit2', ctypes.c_uint16), 463 | ('boost_power_limit', ctypes.c_uint16), 464 | ('od_turbo_power_limit', ctypes.c_uint16), 465 | ('od_power_save_power_limit', ctypes.c_uint16), 466 | ('software_shutdown_temp', ctypes.c_uint16), 467 | ('reserve', ctypes.c_uint16 * 6), 468 | ('power_saving_clock', struct_smu_11_0_power_saving_clock_table), 469 | ('overdrive_table', struct_smu_11_0_overdrive_table), 470 | ('smc_pptable', struct_c__SA_PPTable_t), 471 | ] 472 | 473 | __all__ =\ 474 | ['SMU_11_0_MAX_ODFEATURE', 'SMU_11_0_MAX_ODSETTING', 475 | 'SMU_11_0_MAX_PPCLOCK', 'SMU_11_0_ODCAP_AUTO_OC_ENGINE', 476 | 'SMU_11_0_ODCAP_AUTO_OC_MEMORY', 'SMU_11_0_ODCAP_AUTO_UV_ENGINE', 477 | 'SMU_11_0_ODCAP_COUNT', 'SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT', 478 | 'SMU_11_0_ODCAP_FAN_CURVE', 'SMU_11_0_ODCAP_FAN_SPEED_MIN', 479 | 'SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL', 480 | 'SMU_11_0_ODCAP_GFXCLK_CURVE', 'SMU_11_0_ODCAP_GFXCLK_LIMITS', 481 | 'SMU_11_0_ODCAP_MEMORY_TIMING_TUNE', 'SMU_11_0_ODCAP_POWER_LIMIT', 482 | 'SMU_11_0_ODCAP_TEMPERATURE_FAN', 483 | 'SMU_11_0_ODCAP_TEMPERATURE_SYSTEM', 'SMU_11_0_ODCAP_UCLK_MAX', 484 | 'SMU_11_0_ODFEATURE_AUTO_OC_ENGINE', 485 | 'SMU_11_0_ODFEATURE_AUTO_OC_MEMORY', 486 | 'SMU_11_0_ODFEATURE_AUTO_UV_ENGINE', 'SMU_11_0_ODFEATURE_CAP', 487 | 'SMU_11_0_ODFEATURE_COUNT', 488 | 'SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT', 489 | 'SMU_11_0_ODFEATURE_FAN_CURVE', 490 | 'SMU_11_0_ODFEATURE_FAN_SPEED_MIN', 491 | 'SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL', 492 | 'SMU_11_0_ODFEATURE_GFXCLK_CURVE', 493 | 'SMU_11_0_ODFEATURE_GFXCLK_LIMITS', 'SMU_11_0_ODFEATURE_ID', 494 | 'SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE', 495 | 'SMU_11_0_ODFEATURE_POWER_LIMIT', 496 | 'SMU_11_0_ODFEATURE_TEMPERATURE_FAN', 497 | 'SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM', 498 | 'SMU_11_0_ODFEATURE_UCLK_MAX', 'SMU_11_0_ODSETTING_ACTIMING', 499 | 'SMU_11_0_ODSETTING_AUTOOCENGINE', 500 | 'SMU_11_0_ODSETTING_AUTOOCMEMORY', 501 | 'SMU_11_0_ODSETTING_AUTOUVENGINE', 'SMU_11_0_ODSETTING_COUNT', 502 | 'SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT', 503 | 'SMU_11_0_ODSETTING_FANRPMMIN', 504 | 'SMU_11_0_ODSETTING_FANTARGETTEMPERATURE', 505 | 'SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL', 506 | 'SMU_11_0_ODSETTING_GFXCLKFMAX', 'SMU_11_0_ODSETTING_GFXCLKFMIN', 507 | 'SMU_11_0_ODSETTING_ID', 'SMU_11_0_ODSETTING_OPERATINGTEMPMAX', 508 | 'SMU_11_0_ODSETTING_POWERPERCENTAGE', 509 | 'SMU_11_0_ODSETTING_UCLKFMAX', 510 | 'SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1', 511 | 'SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2', 512 | 'SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3', 513 | 'SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1', 514 | 'SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2', 515 | 'SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3', 516 | 'SMU_11_0_PPCLOCK_COUNT', 'SMU_11_0_PPCLOCK_DCEFCLK', 517 | 'SMU_11_0_PPCLOCK_DCLK', 'SMU_11_0_PPCLOCK_DISPCLK', 518 | 'SMU_11_0_PPCLOCK_ECLK', 'SMU_11_0_PPCLOCK_GFXCLK', 519 | 'SMU_11_0_PPCLOCK_ID', 'SMU_11_0_PPCLOCK_PHYCLK', 520 | 'SMU_11_0_PPCLOCK_PIXCLK', 'SMU_11_0_PPCLOCK_SOCCLK', 521 | 'SMU_11_0_PPCLOCK_UCLK', 'SMU_11_0_PPCLOCK_VCLK', 522 | 'SMU_11_0_PPTABLE_H', 'SMU_11_0_PP_OVERDRIVE_VERSION', 523 | 'SMU_11_0_PP_PLATFORM_CAP_BACO', 524 | 'SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC', 525 | 'SMU_11_0_PP_PLATFORM_CAP_MACO', 526 | 'SMU_11_0_PP_PLATFORM_CAP_POWERPLAY', 527 | 'SMU_11_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE', 528 | 'SMU_11_0_PP_PLATFORM_CAP_SHADOWPSTATE', 529 | 'SMU_11_0_PP_POWERSAVINGCLOCK_VERSION', 530 | 'SMU_11_0_PP_THERMALCONTROLLER_NONE', 531 | 'SMU_11_0_TABLE_FORMAT_REVISION', 532 | 'struct_atom_common_table_header', 'struct_c__SA_DpmDescriptor_t', 533 | 'struct_c__SA_DroopInt_t', 'struct_c__SA_I2cControllerConfig_t', 534 | 'struct_c__SA_LinearInt_t', 'struct_c__SA_PPTable_t', 535 | 'struct_c__SA_QuadraticInt_t', 'struct_smu_11_0_overdrive_table', 536 | 'struct_smu_11_0_power_saving_clock_table', 537 | 'struct_smu_11_0_powerplay_table'] 538 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/generated/pptable_v1_0.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # 3 | # TARGET arch is: ['-include', 'stdint.h', '-include', '/home/amezin/linux/drivers/gpu/drm/amd/include/atom-types.h', '-include', '/home/amezin/linux/drivers/gpu/drm/amd/include/atombios.h'] 4 | # WORD_SIZE is: 8 5 | # POINTER_SIZE is: 8 6 | # LONGDOUBLE_SIZE is: 16 7 | # 8 | import ctypes 9 | 10 | 11 | 12 | 13 | class struct__ATOM_COMMON_TABLE_HEADER(ctypes.LittleEndianStructure): 14 | _pack_ = True # source:False 15 | _fields_ = [ 16 | ('usStructureSize', ctypes.c_uint16), 17 | ('ucTableFormatRevision', ctypes.c_ubyte), 18 | ('ucTableContentRevision', ctypes.c_ubyte), 19 | ] 20 | 21 | TONGA_PPTABLE_H = True # macro 22 | ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK = 0x0f # macro 23 | ATOM_TONGA_PP_FANPARAMETERS_NOFAN = 0x80 # macro 24 | ATOM_TONGA_PP_THERMALCONTROLLER_NONE = 0 # macro 25 | ATOM_TONGA_PP_THERMALCONTROLLER_LM96163 = 17 # macro 26 | ATOM_TONGA_PP_THERMALCONTROLLER_TONGA = 21 # macro 27 | ATOM_TONGA_PP_THERMALCONTROLLER_FIJI = 22 # macro 28 | ATOM_TONGA_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL = 0x89 # macro 29 | ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL = 0x8D # macro 30 | ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL = 0x1 # macro 31 | ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY = 0x2 # macro 32 | ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE = 0x4 # macro 33 | ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND = 0x8 # macro 34 | ____RETIRE16____ = 0x10 # macro 35 | ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC = 0x20 # macro 36 | ____RETIRE64____ = 0x40 # macro 37 | ____RETIRE128____ = 0x80 # macro 38 | ____RETIRE256____ = 0x100 # macro 39 | ____RETIRE512____ = 0x200 # macro 40 | ____RETIRE1024____ = 0x400 # macro 41 | ____RETIRE2048____ = 0x800 # macro 42 | ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL = 0x1000 # macro 43 | ____RETIRE2000____ = 0x2000 # macro 44 | ____RETIRE4000____ = 0x4000 # macro 45 | ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL = 0x8000 # macro 46 | ____RETIRE10000____ = 0x10000 # macro 47 | ATOM_TONGA_PP_PLATFORM_CAP_BACO = 0x20000 # macro 48 | ATOM_TONGA_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 = 0x100000 # macro 49 | ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL = 0x1000000 # macro 50 | ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE = 0x2000000 # macro 51 | ATOM_PPLIB_CLASSIFICATION_UI_MASK = 0x0007 # macro 52 | ATOM_PPLIB_CLASSIFICATION_UI_SHIFT = 0 # macro 53 | ATOM_PPLIB_CLASSIFICATION_UI_NONE = 0 # macro 54 | ATOM_PPLIB_CLASSIFICATION_UI_BATTERY = 1 # macro 55 | ATOM_PPLIB_CLASSIFICATION_UI_BALANCED = 3 # macro 56 | ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE = 5 # macro 57 | ATOM_PPLIB_CLASSIFICATION_BOOT = 0x0008 # macro 58 | ATOM_PPLIB_CLASSIFICATION_THERMAL = 0x0010 # macro 59 | ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE = 0x0020 # macro 60 | ATOM_PPLIB_CLASSIFICATION_REST = 0x0040 # macro 61 | ATOM_PPLIB_CLASSIFICATION_FORCED = 0x0080 # macro 62 | ATOM_PPLIB_CLASSIFICATION_ACPI = 0x1000 # macro 63 | ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 = 0x0001 # macro 64 | ATOM_Tonga_DISALLOW_ON_DC = 0x00004000 # macro 65 | ATOM_Tonga_ENABLE_VARIBRIGHT = 0x00008000 # macro 66 | ATOM_Tonga_TABLE_REVISION_TONGA = 7 # macro 67 | class struct__ATOM_Tonga_POWERPLAYTABLE(ctypes.LittleEndianStructure): 68 | _pack_ = True # source:False 69 | _fields_ = [ 70 | ('sHeader', struct__ATOM_COMMON_TABLE_HEADER), 71 | ('ucTableRevision', ctypes.c_ubyte), 72 | ('usTableSize', ctypes.c_uint16), 73 | ('ulGoldenPPID', ctypes.c_uint32), 74 | ('ulGoldenRevision', ctypes.c_uint32), 75 | ('usFormatID', ctypes.c_uint16), 76 | ('usVoltageTime', ctypes.c_uint16), 77 | ('ulPlatformCaps', ctypes.c_uint32), 78 | ('ulMaxODEngineClock', ctypes.c_uint32), 79 | ('ulMaxODMemoryClock', ctypes.c_uint32), 80 | ('usPowerControlLimit', ctypes.c_uint16), 81 | ('usUlvVoltageOffset', ctypes.c_uint16), 82 | ('usStateArrayOffset', ctypes.c_uint16), 83 | ('usFanTableOffset', ctypes.c_uint16), 84 | ('usThermalControllerOffset', ctypes.c_uint16), 85 | ('usReserv', ctypes.c_uint16), 86 | ('usMclkDependencyTableOffset', ctypes.c_uint16), 87 | ('usSclkDependencyTableOffset', ctypes.c_uint16), 88 | ('usVddcLookupTableOffset', ctypes.c_uint16), 89 | ('usVddgfxLookupTableOffset', ctypes.c_uint16), 90 | ('usMMDependencyTableOffset', ctypes.c_uint16), 91 | ('usVCEStateTableOffset', ctypes.c_uint16), 92 | ('usPPMTableOffset', ctypes.c_uint16), 93 | ('usPowerTuneTableOffset', ctypes.c_uint16), 94 | ('usHardLimitTableOffset', ctypes.c_uint16), 95 | ('usPCIETableOffset', ctypes.c_uint16), 96 | ('usGPIOTableOffset', ctypes.c_uint16), 97 | ('usReserved', ctypes.c_uint16 * 6), 98 | ] 99 | 100 | ATOM_Tonga_POWERPLAYTABLE = struct__ATOM_Tonga_POWERPLAYTABLE 101 | class struct__ATOM_Tonga_State(ctypes.LittleEndianStructure): 102 | _pack_ = True # source:False 103 | _fields_ = [ 104 | ('ucEngineClockIndexHigh', ctypes.c_ubyte), 105 | ('ucEngineClockIndexLow', ctypes.c_ubyte), 106 | ('ucMemoryClockIndexHigh', ctypes.c_ubyte), 107 | ('ucMemoryClockIndexLow', ctypes.c_ubyte), 108 | ('ucPCIEGenLow', ctypes.c_ubyte), 109 | ('ucPCIEGenHigh', ctypes.c_ubyte), 110 | ('ucPCIELaneLow', ctypes.c_ubyte), 111 | ('ucPCIELaneHigh', ctypes.c_ubyte), 112 | ('usClassification', ctypes.c_uint16), 113 | ('ulCapsAndSettings', ctypes.c_uint32), 114 | ('usClassification2', ctypes.c_uint16), 115 | ('ucUnused', ctypes.c_ubyte * 4), 116 | ] 117 | 118 | ATOM_Tonga_State = struct__ATOM_Tonga_State 119 | class struct__ATOM_Tonga_State_Array(ctypes.LittleEndianStructure): 120 | _pack_ = True # source:False 121 | _fields_ = [ 122 | ('ucRevId', ctypes.c_ubyte), 123 | ('ucNumEntries', ctypes.c_ubyte), 124 | ('entries', struct__ATOM_Tonga_State * 1), 125 | ] 126 | 127 | ATOM_Tonga_State_Array = struct__ATOM_Tonga_State_Array 128 | class struct__ATOM_Tonga_MCLK_Dependency_Record(ctypes.LittleEndianStructure): 129 | _pack_ = True # source:False 130 | _fields_ = [ 131 | ('ucVddcInd', ctypes.c_ubyte), 132 | ('usVddci', ctypes.c_uint16), 133 | ('usVddgfxOffset', ctypes.c_uint16), 134 | ('usMvdd', ctypes.c_uint16), 135 | ('ulMclk', ctypes.c_uint32), 136 | ('usReserved', ctypes.c_uint16), 137 | ] 138 | 139 | ATOM_Tonga_MCLK_Dependency_Record = struct__ATOM_Tonga_MCLK_Dependency_Record 140 | class struct__ATOM_Tonga_MCLK_Dependency_Table(ctypes.LittleEndianStructure): 141 | _pack_ = True # source:False 142 | _fields_ = [ 143 | ('ucRevId', ctypes.c_ubyte), 144 | ('ucNumEntries', ctypes.c_ubyte), 145 | ('entries', struct__ATOM_Tonga_MCLK_Dependency_Record * 1), 146 | ] 147 | 148 | ATOM_Tonga_MCLK_Dependency_Table = struct__ATOM_Tonga_MCLK_Dependency_Table 149 | class struct__ATOM_Tonga_SCLK_Dependency_Record(ctypes.LittleEndianStructure): 150 | _pack_ = True # source:False 151 | _fields_ = [ 152 | ('ucVddInd', ctypes.c_ubyte), 153 | ('usVddcOffset', ctypes.c_uint16), 154 | ('ulSclk', ctypes.c_uint32), 155 | ('usEdcCurrent', ctypes.c_uint16), 156 | ('ucReliabilityTemperature', ctypes.c_ubyte), 157 | ('ucCKSVOffsetandDisable', ctypes.c_ubyte), 158 | ] 159 | 160 | ATOM_Tonga_SCLK_Dependency_Record = struct__ATOM_Tonga_SCLK_Dependency_Record 161 | class struct__ATOM_Tonga_SCLK_Dependency_Table(ctypes.LittleEndianStructure): 162 | _pack_ = True # source:False 163 | _fields_ = [ 164 | ('ucRevId', ctypes.c_ubyte), 165 | ('ucNumEntries', ctypes.c_ubyte), 166 | ('entries', struct__ATOM_Tonga_SCLK_Dependency_Record * 1), 167 | ] 168 | 169 | ATOM_Tonga_SCLK_Dependency_Table = struct__ATOM_Tonga_SCLK_Dependency_Table 170 | class struct__ATOM_Polaris_SCLK_Dependency_Record(ctypes.LittleEndianStructure): 171 | _pack_ = True # source:False 172 | _fields_ = [ 173 | ('ucVddInd', ctypes.c_ubyte), 174 | ('usVddcOffset', ctypes.c_uint16), 175 | ('ulSclk', ctypes.c_uint32), 176 | ('usEdcCurrent', ctypes.c_uint16), 177 | ('ucReliabilityTemperature', ctypes.c_ubyte), 178 | ('ucCKSVOffsetandDisable', ctypes.c_ubyte), 179 | ('ulSclkOffset', ctypes.c_uint32), 180 | ] 181 | 182 | ATOM_Polaris_SCLK_Dependency_Record = struct__ATOM_Polaris_SCLK_Dependency_Record 183 | class struct__ATOM_Polaris_SCLK_Dependency_Table(ctypes.LittleEndianStructure): 184 | _pack_ = True # source:False 185 | _fields_ = [ 186 | ('ucRevId', ctypes.c_ubyte), 187 | ('ucNumEntries', ctypes.c_ubyte), 188 | ('entries', struct__ATOM_Polaris_SCLK_Dependency_Record * 1), 189 | ] 190 | 191 | ATOM_Polaris_SCLK_Dependency_Table = struct__ATOM_Polaris_SCLK_Dependency_Table 192 | class struct__ATOM_Tonga_PCIE_Record(ctypes.LittleEndianStructure): 193 | _pack_ = True # source:False 194 | _fields_ = [ 195 | ('ucPCIEGenSpeed', ctypes.c_ubyte), 196 | ('usPCIELaneWidth', ctypes.c_ubyte), 197 | ('ucReserved', ctypes.c_ubyte * 2), 198 | ] 199 | 200 | ATOM_Tonga_PCIE_Record = struct__ATOM_Tonga_PCIE_Record 201 | class struct__ATOM_Tonga_PCIE_Table(ctypes.LittleEndianStructure): 202 | _pack_ = True # source:False 203 | _fields_ = [ 204 | ('ucRevId', ctypes.c_ubyte), 205 | ('ucNumEntries', ctypes.c_ubyte), 206 | ('entries', struct__ATOM_Tonga_PCIE_Record * 1), 207 | ] 208 | 209 | ATOM_Tonga_PCIE_Table = struct__ATOM_Tonga_PCIE_Table 210 | class struct__ATOM_Polaris10_PCIE_Record(ctypes.LittleEndianStructure): 211 | _pack_ = True # source:False 212 | _fields_ = [ 213 | ('ucPCIEGenSpeed', ctypes.c_ubyte), 214 | ('usPCIELaneWidth', ctypes.c_ubyte), 215 | ('ucReserved', ctypes.c_ubyte * 2), 216 | ('ulPCIE_Sclk', ctypes.c_uint32), 217 | ] 218 | 219 | ATOM_Polaris10_PCIE_Record = struct__ATOM_Polaris10_PCIE_Record 220 | class struct__ATOM_Polaris10_PCIE_Table(ctypes.LittleEndianStructure): 221 | _pack_ = True # source:False 222 | _fields_ = [ 223 | ('ucRevId', ctypes.c_ubyte), 224 | ('ucNumEntries', ctypes.c_ubyte), 225 | ('entries', struct__ATOM_Polaris10_PCIE_Record * 1), 226 | ] 227 | 228 | ATOM_Polaris10_PCIE_Table = struct__ATOM_Polaris10_PCIE_Table 229 | class struct__ATOM_Tonga_MM_Dependency_Record(ctypes.LittleEndianStructure): 230 | _pack_ = True # source:False 231 | _fields_ = [ 232 | ('ucVddcInd', ctypes.c_ubyte), 233 | ('usVddgfxOffset', ctypes.c_uint16), 234 | ('ulDClk', ctypes.c_uint32), 235 | ('ulVClk', ctypes.c_uint32), 236 | ('ulEClk', ctypes.c_uint32), 237 | ('ulAClk', ctypes.c_uint32), 238 | ('ulSAMUClk', ctypes.c_uint32), 239 | ] 240 | 241 | ATOM_Tonga_MM_Dependency_Record = struct__ATOM_Tonga_MM_Dependency_Record 242 | class struct__ATOM_Tonga_MM_Dependency_Table(ctypes.LittleEndianStructure): 243 | _pack_ = True # source:False 244 | _fields_ = [ 245 | ('ucRevId', ctypes.c_ubyte), 246 | ('ucNumEntries', ctypes.c_ubyte), 247 | ('entries', struct__ATOM_Tonga_MM_Dependency_Record * 1), 248 | ] 249 | 250 | ATOM_Tonga_MM_Dependency_Table = struct__ATOM_Tonga_MM_Dependency_Table 251 | class struct__ATOM_Tonga_Voltage_Lookup_Record(ctypes.LittleEndianStructure): 252 | _pack_ = True # source:False 253 | _fields_ = [ 254 | ('usVdd', ctypes.c_uint16), 255 | ('usCACLow', ctypes.c_uint16), 256 | ('usCACMid', ctypes.c_uint16), 257 | ('usCACHigh', ctypes.c_uint16), 258 | ] 259 | 260 | ATOM_Tonga_Voltage_Lookup_Record = struct__ATOM_Tonga_Voltage_Lookup_Record 261 | class struct__ATOM_Tonga_Voltage_Lookup_Table(ctypes.LittleEndianStructure): 262 | _pack_ = True # source:False 263 | _fields_ = [ 264 | ('ucRevId', ctypes.c_ubyte), 265 | ('ucNumEntries', ctypes.c_ubyte), 266 | ('entries', struct__ATOM_Tonga_Voltage_Lookup_Record * 1), 267 | ] 268 | 269 | ATOM_Tonga_Voltage_Lookup_Table = struct__ATOM_Tonga_Voltage_Lookup_Table 270 | class struct__ATOM_Tonga_Fan_Table(ctypes.LittleEndianStructure): 271 | _pack_ = True # source:False 272 | _fields_ = [ 273 | ('ucRevId', ctypes.c_ubyte), 274 | ('ucTHyst', ctypes.c_ubyte), 275 | ('usTMin', ctypes.c_uint16), 276 | ('usTMed', ctypes.c_uint16), 277 | ('usTHigh', ctypes.c_uint16), 278 | ('usPWMMin', ctypes.c_uint16), 279 | ('usPWMMed', ctypes.c_uint16), 280 | ('usPWMHigh', ctypes.c_uint16), 281 | ('usTMax', ctypes.c_uint16), 282 | ('ucFanControlMode', ctypes.c_ubyte), 283 | ('usFanPWMMax', ctypes.c_uint16), 284 | ('usFanOutputSensitivity', ctypes.c_uint16), 285 | ('usFanRPMMax', ctypes.c_uint16), 286 | ('ulMinFanSCLKAcousticLimit', ctypes.c_uint32), 287 | ('ucTargetTemperature', ctypes.c_ubyte), 288 | ('ucMinimumPWMLimit', ctypes.c_ubyte), 289 | ('usReserved', ctypes.c_uint16), 290 | ] 291 | 292 | ATOM_Tonga_Fan_Table = struct__ATOM_Tonga_Fan_Table 293 | class struct__ATOM_Fiji_Fan_Table(ctypes.LittleEndianStructure): 294 | _pack_ = True # source:False 295 | _fields_ = [ 296 | ('ucRevId', ctypes.c_ubyte), 297 | ('ucTHyst', ctypes.c_ubyte), 298 | ('usTMin', ctypes.c_uint16), 299 | ('usTMed', ctypes.c_uint16), 300 | ('usTHigh', ctypes.c_uint16), 301 | ('usPWMMin', ctypes.c_uint16), 302 | ('usPWMMed', ctypes.c_uint16), 303 | ('usPWMHigh', ctypes.c_uint16), 304 | ('usTMax', ctypes.c_uint16), 305 | ('ucFanControlMode', ctypes.c_ubyte), 306 | ('usFanPWMMax', ctypes.c_uint16), 307 | ('usFanOutputSensitivity', ctypes.c_uint16), 308 | ('usFanRPMMax', ctypes.c_uint16), 309 | ('ulMinFanSCLKAcousticLimit', ctypes.c_uint32), 310 | ('ucTargetTemperature', ctypes.c_ubyte), 311 | ('ucMinimumPWMLimit', ctypes.c_ubyte), 312 | ('usFanGainEdge', ctypes.c_uint16), 313 | ('usFanGainHotspot', ctypes.c_uint16), 314 | ('usFanGainLiquid', ctypes.c_uint16), 315 | ('usFanGainVrVddc', ctypes.c_uint16), 316 | ('usFanGainVrMvdd', ctypes.c_uint16), 317 | ('usFanGainPlx', ctypes.c_uint16), 318 | ('usFanGainHbm', ctypes.c_uint16), 319 | ('usReserved', ctypes.c_uint16), 320 | ] 321 | 322 | ATOM_Fiji_Fan_Table = struct__ATOM_Fiji_Fan_Table 323 | class struct__ATOM_Tonga_Thermal_Controller(ctypes.LittleEndianStructure): 324 | _pack_ = True # source:False 325 | _fields_ = [ 326 | ('ucRevId', ctypes.c_ubyte), 327 | ('ucType', ctypes.c_ubyte), 328 | ('ucI2cLine', ctypes.c_ubyte), 329 | ('ucI2cAddress', ctypes.c_ubyte), 330 | ('ucFanParameters', ctypes.c_ubyte), 331 | ('ucFanMinRPM', ctypes.c_ubyte), 332 | ('ucFanMaxRPM', ctypes.c_ubyte), 333 | ('ucReserved', ctypes.c_ubyte), 334 | ('ucFlags', ctypes.c_ubyte), 335 | ] 336 | 337 | ATOM_Tonga_Thermal_Controller = struct__ATOM_Tonga_Thermal_Controller 338 | class struct__ATOM_Tonga_VCE_State_Record(ctypes.LittleEndianStructure): 339 | _pack_ = True # source:False 340 | _fields_ = [ 341 | ('ucVCEClockIndex', ctypes.c_ubyte), 342 | ('ucFlag', ctypes.c_ubyte), 343 | ('ucSCLKIndex', ctypes.c_ubyte), 344 | ('ucMCLKIndex', ctypes.c_ubyte), 345 | ] 346 | 347 | ATOM_Tonga_VCE_State_Record = struct__ATOM_Tonga_VCE_State_Record 348 | class struct__ATOM_Tonga_VCE_State_Table(ctypes.LittleEndianStructure): 349 | _pack_ = True # source:False 350 | _fields_ = [ 351 | ('ucRevId', ctypes.c_ubyte), 352 | ('ucNumEntries', ctypes.c_ubyte), 353 | ('entries', struct__ATOM_Tonga_VCE_State_Record * 1), 354 | ] 355 | 356 | ATOM_Tonga_VCE_State_Table = struct__ATOM_Tonga_VCE_State_Table 357 | class struct__ATOM_Tonga_PowerTune_Table(ctypes.LittleEndianStructure): 358 | _pack_ = True # source:False 359 | _fields_ = [ 360 | ('ucRevId', ctypes.c_ubyte), 361 | ('usTDP', ctypes.c_uint16), 362 | ('usConfigurableTDP', ctypes.c_uint16), 363 | ('usTDC', ctypes.c_uint16), 364 | ('usBatteryPowerLimit', ctypes.c_uint16), 365 | ('usSmallPowerLimit', ctypes.c_uint16), 366 | ('usLowCACLeakage', ctypes.c_uint16), 367 | ('usHighCACLeakage', ctypes.c_uint16), 368 | ('usMaximumPowerDeliveryLimit', ctypes.c_uint16), 369 | ('usTjMax', ctypes.c_uint16), 370 | ('usPowerTuneDataSetID', ctypes.c_uint16), 371 | ('usEDCLimit', ctypes.c_uint16), 372 | ('usSoftwareShutdownTemp', ctypes.c_uint16), 373 | ('usClockStretchAmount', ctypes.c_uint16), 374 | ('usReserve', ctypes.c_uint16 * 2), 375 | ] 376 | 377 | ATOM_Tonga_PowerTune_Table = struct__ATOM_Tonga_PowerTune_Table 378 | class struct__ATOM_Fiji_PowerTune_Table(ctypes.LittleEndianStructure): 379 | _pack_ = True # source:False 380 | _fields_ = [ 381 | ('ucRevId', ctypes.c_ubyte), 382 | ('usTDP', ctypes.c_uint16), 383 | ('usConfigurableTDP', ctypes.c_uint16), 384 | ('usTDC', ctypes.c_uint16), 385 | ('usBatteryPowerLimit', ctypes.c_uint16), 386 | ('usSmallPowerLimit', ctypes.c_uint16), 387 | ('usLowCACLeakage', ctypes.c_uint16), 388 | ('usHighCACLeakage', ctypes.c_uint16), 389 | ('usMaximumPowerDeliveryLimit', ctypes.c_uint16), 390 | ('usTjMax', ctypes.c_uint16), 391 | ('usPowerTuneDataSetID', ctypes.c_uint16), 392 | ('usEDCLimit', ctypes.c_uint16), 393 | ('usSoftwareShutdownTemp', ctypes.c_uint16), 394 | ('usClockStretchAmount', ctypes.c_uint16), 395 | ('usTemperatureLimitHotspot', ctypes.c_uint16), 396 | ('usTemperatureLimitLiquid1', ctypes.c_uint16), 397 | ('usTemperatureLimitLiquid2', ctypes.c_uint16), 398 | ('usTemperatureLimitVrVddc', ctypes.c_uint16), 399 | ('usTemperatureLimitVrMvdd', ctypes.c_uint16), 400 | ('usTemperatureLimitPlx', ctypes.c_uint16), 401 | ('ucLiquid1_I2C_address', ctypes.c_ubyte), 402 | ('ucLiquid2_I2C_address', ctypes.c_ubyte), 403 | ('ucLiquid_I2C_Line', ctypes.c_ubyte), 404 | ('ucVr_I2C_address', ctypes.c_ubyte), 405 | ('ucVr_I2C_Line', ctypes.c_ubyte), 406 | ('ucPlx_I2C_address', ctypes.c_ubyte), 407 | ('ucPlx_I2C_Line', ctypes.c_ubyte), 408 | ('usReserved', ctypes.c_uint16), 409 | ] 410 | 411 | ATOM_Fiji_PowerTune_Table = struct__ATOM_Fiji_PowerTune_Table 412 | ATOM_PPM_A_A = 1 # macro 413 | ATOM_PPM_A_I = 2 # macro 414 | class struct__ATOM_Tonga_PPM_Table(ctypes.LittleEndianStructure): 415 | _pack_ = True # source:False 416 | _fields_ = [ 417 | ('ucRevId', ctypes.c_ubyte), 418 | ('ucPpmDesign', ctypes.c_ubyte), 419 | ('usCpuCoreNumber', ctypes.c_uint16), 420 | ('ulPlatformTDP', ctypes.c_uint32), 421 | ('ulSmallACPlatformTDP', ctypes.c_uint32), 422 | ('ulPlatformTDC', ctypes.c_uint32), 423 | ('ulSmallACPlatformTDC', ctypes.c_uint32), 424 | ('ulApuTDP', ctypes.c_uint32), 425 | ('ulDGpuTDP', ctypes.c_uint32), 426 | ('ulDGpuUlvPower', ctypes.c_uint32), 427 | ('ulTjmax', ctypes.c_uint32), 428 | ] 429 | 430 | ATOM_Tonga_PPM_Table = struct__ATOM_Tonga_PPM_Table 431 | class struct__ATOM_Tonga_Hard_Limit_Record(ctypes.LittleEndianStructure): 432 | _pack_ = True # source:False 433 | _fields_ = [ 434 | ('ulSCLKLimit', ctypes.c_uint32), 435 | ('ulMCLKLimit', ctypes.c_uint32), 436 | ('usVddcLimit', ctypes.c_uint16), 437 | ('usVddciLimit', ctypes.c_uint16), 438 | ('usVddgfxLimit', ctypes.c_uint16), 439 | ] 440 | 441 | ATOM_Tonga_Hard_Limit_Record = struct__ATOM_Tonga_Hard_Limit_Record 442 | class struct__ATOM_Tonga_Hard_Limit_Table(ctypes.LittleEndianStructure): 443 | _pack_ = True # source:False 444 | _fields_ = [ 445 | ('ucRevId', ctypes.c_ubyte), 446 | ('ucNumEntries', ctypes.c_ubyte), 447 | ('entries', struct__ATOM_Tonga_Hard_Limit_Record * 1), 448 | ] 449 | 450 | ATOM_Tonga_Hard_Limit_Table = struct__ATOM_Tonga_Hard_Limit_Table 451 | class struct__ATOM_Tonga_GPIO_Table(ctypes.LittleEndianStructure): 452 | _pack_ = True # source:False 453 | _fields_ = [ 454 | ('ucRevId', ctypes.c_ubyte), 455 | ('ucVRHotTriggeredSclkDpmIndex', ctypes.c_ubyte), 456 | ('ucReserve', ctypes.c_ubyte * 5), 457 | ] 458 | 459 | ATOM_Tonga_GPIO_Table = struct__ATOM_Tonga_GPIO_Table 460 | class struct__PPTable_Generic_SubTable_Header(ctypes.LittleEndianStructure): 461 | _pack_ = True # source:False 462 | _fields_ = [ 463 | ('ucRevId', ctypes.c_ubyte), 464 | ] 465 | 466 | PPTable_Generic_SubTable_Header = struct__PPTable_Generic_SubTable_Header 467 | __all__ =\ 468 | ['ATOM_Fiji_Fan_Table', 'ATOM_Fiji_PowerTune_Table', 469 | 'ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2', 470 | 'ATOM_PPLIB_CLASSIFICATION_ACPI', 471 | 'ATOM_PPLIB_CLASSIFICATION_BOOT', 472 | 'ATOM_PPLIB_CLASSIFICATION_FORCED', 473 | 'ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE', 474 | 'ATOM_PPLIB_CLASSIFICATION_REST', 475 | 'ATOM_PPLIB_CLASSIFICATION_THERMAL', 476 | 'ATOM_PPLIB_CLASSIFICATION_UI_BALANCED', 477 | 'ATOM_PPLIB_CLASSIFICATION_UI_BATTERY', 478 | 'ATOM_PPLIB_CLASSIFICATION_UI_MASK', 479 | 'ATOM_PPLIB_CLASSIFICATION_UI_NONE', 480 | 'ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE', 481 | 'ATOM_PPLIB_CLASSIFICATION_UI_SHIFT', 'ATOM_PPM_A_A', 482 | 'ATOM_PPM_A_I', 'ATOM_Polaris10_PCIE_Record', 483 | 'ATOM_Polaris10_PCIE_Table', 484 | 'ATOM_Polaris_SCLK_Dependency_Record', 485 | 'ATOM_Polaris_SCLK_Dependency_Table', 486 | 'ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE', 487 | 'ATOM_TONGA_PP_FANPARAMETERS_NOFAN', 488 | 'ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK', 489 | 'ATOM_TONGA_PP_PLATFORM_CAP_BACO', 490 | 'ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND', 491 | 'ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC', 492 | 'ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL', 493 | 'ATOM_TONGA_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17', 494 | 'ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY', 495 | 'ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE', 496 | 'ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL', 497 | 'ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL', 498 | 'ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL', 499 | 'ATOM_TONGA_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL', 500 | 'ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL', 501 | 'ATOM_TONGA_PP_THERMALCONTROLLER_FIJI', 502 | 'ATOM_TONGA_PP_THERMALCONTROLLER_LM96163', 503 | 'ATOM_TONGA_PP_THERMALCONTROLLER_NONE', 504 | 'ATOM_TONGA_PP_THERMALCONTROLLER_TONGA', 505 | 'ATOM_Tonga_DISALLOW_ON_DC', 'ATOM_Tonga_ENABLE_VARIBRIGHT', 506 | 'ATOM_Tonga_Fan_Table', 'ATOM_Tonga_GPIO_Table', 507 | 'ATOM_Tonga_Hard_Limit_Record', 'ATOM_Tonga_Hard_Limit_Table', 508 | 'ATOM_Tonga_MCLK_Dependency_Record', 509 | 'ATOM_Tonga_MCLK_Dependency_Table', 510 | 'ATOM_Tonga_MM_Dependency_Record', 511 | 'ATOM_Tonga_MM_Dependency_Table', 'ATOM_Tonga_PCIE_Record', 512 | 'ATOM_Tonga_PCIE_Table', 'ATOM_Tonga_POWERPLAYTABLE', 513 | 'ATOM_Tonga_PPM_Table', 'ATOM_Tonga_PowerTune_Table', 514 | 'ATOM_Tonga_SCLK_Dependency_Record', 515 | 'ATOM_Tonga_SCLK_Dependency_Table', 'ATOM_Tonga_State', 516 | 'ATOM_Tonga_State_Array', 'ATOM_Tonga_TABLE_REVISION_TONGA', 517 | 'ATOM_Tonga_Thermal_Controller', 'ATOM_Tonga_VCE_State_Record', 518 | 'ATOM_Tonga_VCE_State_Table', 'ATOM_Tonga_Voltage_Lookup_Record', 519 | 'ATOM_Tonga_Voltage_Lookup_Table', 520 | 'PPTable_Generic_SubTable_Header', 'TONGA_PPTABLE_H', 521 | '____RETIRE10000____', '____RETIRE1024____', '____RETIRE128____', 522 | '____RETIRE16____', '____RETIRE2000____', '____RETIRE2048____', 523 | '____RETIRE256____', '____RETIRE4000____', '____RETIRE512____', 524 | '____RETIRE64____', 'struct__ATOM_COMMON_TABLE_HEADER', 525 | 'struct__ATOM_Fiji_Fan_Table', 526 | 'struct__ATOM_Fiji_PowerTune_Table', 527 | 'struct__ATOM_Polaris10_PCIE_Record', 528 | 'struct__ATOM_Polaris10_PCIE_Table', 529 | 'struct__ATOM_Polaris_SCLK_Dependency_Record', 530 | 'struct__ATOM_Polaris_SCLK_Dependency_Table', 531 | 'struct__ATOM_Tonga_Fan_Table', 'struct__ATOM_Tonga_GPIO_Table', 532 | 'struct__ATOM_Tonga_Hard_Limit_Record', 533 | 'struct__ATOM_Tonga_Hard_Limit_Table', 534 | 'struct__ATOM_Tonga_MCLK_Dependency_Record', 535 | 'struct__ATOM_Tonga_MCLK_Dependency_Table', 536 | 'struct__ATOM_Tonga_MM_Dependency_Record', 537 | 'struct__ATOM_Tonga_MM_Dependency_Table', 538 | 'struct__ATOM_Tonga_PCIE_Record', 'struct__ATOM_Tonga_PCIE_Table', 539 | 'struct__ATOM_Tonga_POWERPLAYTABLE', 540 | 'struct__ATOM_Tonga_PPM_Table', 541 | 'struct__ATOM_Tonga_PowerTune_Table', 542 | 'struct__ATOM_Tonga_SCLK_Dependency_Record', 543 | 'struct__ATOM_Tonga_SCLK_Dependency_Table', 544 | 'struct__ATOM_Tonga_State', 'struct__ATOM_Tonga_State_Array', 545 | 'struct__ATOM_Tonga_Thermal_Controller', 546 | 'struct__ATOM_Tonga_VCE_State_Record', 547 | 'struct__ATOM_Tonga_VCE_State_Table', 548 | 'struct__ATOM_Tonga_Voltage_Lookup_Record', 549 | 'struct__ATOM_Tonga_Voltage_Lookup_Table', 550 | 'struct__PPTable_Generic_SubTable_Header'] 551 | -------------------------------------------------------------------------------- /src/amdgpu_pptable/generated/vega10_pptable.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # 3 | # TARGET arch is: ['-include', 'stdint.h', '-include', '/home/amezin/linux/drivers/gpu/drm/amd/include/atom-types.h', '-include', '/home/amezin/linux/drivers/gpu/drm/amd/include/atomfirmware.h'] 4 | # WORD_SIZE is: 8 5 | # POINTER_SIZE is: 8 6 | # LONGDOUBLE_SIZE is: 16 7 | # 8 | import ctypes 9 | 10 | 11 | 12 | 13 | class struct_atom_common_table_header(ctypes.LittleEndianStructure): 14 | _pack_ = True # source:False 15 | _fields_ = [ 16 | ('structuresize', ctypes.c_uint16), 17 | ('format_revision', ctypes.c_ubyte), 18 | ('content_revision', ctypes.c_ubyte), 19 | ] 20 | 21 | _VEGA10_PPTABLE_H_ = True # macro 22 | ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK = 0x0f # macro 23 | ATOM_VEGA10_PP_FANPARAMETERS_NOFAN = 0x80 # macro 24 | ATOM_VEGA10_PP_THERMALCONTROLLER_NONE = 0 # macro 25 | ATOM_VEGA10_PP_THERMALCONTROLLER_LM96163 = 17 # macro 26 | ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 = 24 # macro 27 | ATOM_VEGA10_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL = 0x89 # macro 28 | ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL = 0x8D # macro 29 | ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY = 0x1 # macro 30 | ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE = 0x2 # macro 31 | ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC = 0x4 # macro 32 | ATOM_VEGA10_PP_PLATFORM_CAP_BACO = 0x8 # macro 33 | ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL = 0x10 # macro 34 | ATOM_PPLIB_CLASSIFICATION_UI_MASK = 0x0007 # macro 35 | ATOM_PPLIB_CLASSIFICATION_UI_SHIFT = 0 # macro 36 | ATOM_PPLIB_CLASSIFICATION_UI_NONE = 0 # macro 37 | ATOM_PPLIB_CLASSIFICATION_UI_BATTERY = 1 # macro 38 | ATOM_PPLIB_CLASSIFICATION_UI_BALANCED = 3 # macro 39 | ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE = 5 # macro 40 | ATOM_PPLIB_CLASSIFICATION_BOOT = 0x0008 # macro 41 | ATOM_PPLIB_CLASSIFICATION_THERMAL = 0x0010 # macro 42 | ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE = 0x0020 # macro 43 | ATOM_PPLIB_CLASSIFICATION_REST = 0x0040 # macro 44 | ATOM_PPLIB_CLASSIFICATION_FORCED = 0x0080 # macro 45 | ATOM_PPLIB_CLASSIFICATION_ACPI = 0x1000 # macro 46 | ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 = 0x0001 # macro 47 | ATOM_Vega10_DISALLOW_ON_DC = 0x00004000 # macro 48 | ATOM_Vega10_ENABLE_VARIBRIGHT = 0x00008000 # macro 49 | ATOM_Vega10_TABLE_REVISION_VEGA10 = 8 # macro 50 | ATOM_Vega10_VoltageMode_AVFS_Interpolate = 0 # macro 51 | ATOM_Vega10_VoltageMode_AVFS_WorstCase = 1 # macro 52 | ATOM_Vega10_VoltageMode_Static = 2 # macro 53 | class struct__ATOM_Vega10_POWERPLAYTABLE(ctypes.LittleEndianStructure): 54 | _pack_ = True # source:False 55 | _fields_ = [ 56 | ('sHeader', struct_atom_common_table_header), 57 | ('ucTableRevision', ctypes.c_ubyte), 58 | ('usTableSize', ctypes.c_uint16), 59 | ('ulGoldenPPID', ctypes.c_uint32), 60 | ('ulGoldenRevision', ctypes.c_uint32), 61 | ('usFormatID', ctypes.c_uint16), 62 | ('ulPlatformCaps', ctypes.c_uint32), 63 | ('ulMaxODEngineClock', ctypes.c_uint32), 64 | ('ulMaxODMemoryClock', ctypes.c_uint32), 65 | ('usPowerControlLimit', ctypes.c_uint16), 66 | ('usUlvVoltageOffset', ctypes.c_uint16), 67 | ('usUlvSmnclkDid', ctypes.c_uint16), 68 | ('usUlvMp1clkDid', ctypes.c_uint16), 69 | ('usUlvGfxclkBypass', ctypes.c_uint16), 70 | ('usGfxclkSlewRate', ctypes.c_uint16), 71 | ('ucGfxVoltageMode', ctypes.c_ubyte), 72 | ('ucSocVoltageMode', ctypes.c_ubyte), 73 | ('ucUclkVoltageMode', ctypes.c_ubyte), 74 | ('ucUvdVoltageMode', ctypes.c_ubyte), 75 | ('ucVceVoltageMode', ctypes.c_ubyte), 76 | ('ucMp0VoltageMode', ctypes.c_ubyte), 77 | ('ucDcefVoltageMode', ctypes.c_ubyte), 78 | ('usStateArrayOffset', ctypes.c_uint16), 79 | ('usFanTableOffset', ctypes.c_uint16), 80 | ('usThermalControllerOffset', ctypes.c_uint16), 81 | ('usSocclkDependencyTableOffset', ctypes.c_uint16), 82 | ('usMclkDependencyTableOffset', ctypes.c_uint16), 83 | ('usGfxclkDependencyTableOffset', ctypes.c_uint16), 84 | ('usDcefclkDependencyTableOffset', ctypes.c_uint16), 85 | ('usVddcLookupTableOffset', ctypes.c_uint16), 86 | ('usVddmemLookupTableOffset', ctypes.c_uint16), 87 | ('usMMDependencyTableOffset', ctypes.c_uint16), 88 | ('usVCEStateTableOffset', ctypes.c_uint16), 89 | ('usReserve', ctypes.c_uint16), 90 | ('usPowerTuneTableOffset', ctypes.c_uint16), 91 | ('usHardLimitTableOffset', ctypes.c_uint16), 92 | ('usVddciLookupTableOffset', ctypes.c_uint16), 93 | ('usPCIETableOffset', ctypes.c_uint16), 94 | ('usPixclkDependencyTableOffset', ctypes.c_uint16), 95 | ('usDispClkDependencyTableOffset', ctypes.c_uint16), 96 | ('usPhyClkDependencyTableOffset', ctypes.c_uint16), 97 | ] 98 | 99 | ATOM_Vega10_POWERPLAYTABLE = struct__ATOM_Vega10_POWERPLAYTABLE 100 | class struct__ATOM_Vega10_State(ctypes.LittleEndianStructure): 101 | _pack_ = True # source:False 102 | _fields_ = [ 103 | ('ucSocClockIndexHigh', ctypes.c_ubyte), 104 | ('ucSocClockIndexLow', ctypes.c_ubyte), 105 | ('ucGfxClockIndexHigh', ctypes.c_ubyte), 106 | ('ucGfxClockIndexLow', ctypes.c_ubyte), 107 | ('ucMemClockIndexHigh', ctypes.c_ubyte), 108 | ('ucMemClockIndexLow', ctypes.c_ubyte), 109 | ('usClassification', ctypes.c_uint16), 110 | ('ulCapsAndSettings', ctypes.c_uint32), 111 | ('usClassification2', ctypes.c_uint16), 112 | ] 113 | 114 | ATOM_Vega10_State = struct__ATOM_Vega10_State 115 | class struct__ATOM_Vega10_State_Array(ctypes.LittleEndianStructure): 116 | _pack_ = True # source:False 117 | _fields_ = [ 118 | ('ucRevId', ctypes.c_ubyte), 119 | ('ucNumEntries', ctypes.c_ubyte), 120 | ('states', struct__ATOM_Vega10_State * 1), 121 | ] 122 | 123 | ATOM_Vega10_State_Array = struct__ATOM_Vega10_State_Array 124 | class struct__ATOM_Vega10_CLK_Dependency_Record(ctypes.LittleEndianStructure): 125 | _pack_ = True # source:False 126 | _fields_ = [ 127 | ('ulClk', ctypes.c_uint32), 128 | ('ucVddInd', ctypes.c_ubyte), 129 | ] 130 | 131 | ATOM_Vega10_CLK_Dependency_Record = struct__ATOM_Vega10_CLK_Dependency_Record 132 | class struct__ATOM_Vega10_GFXCLK_Dependency_Record(ctypes.LittleEndianStructure): 133 | _pack_ = True # source:False 134 | _fields_ = [ 135 | ('ulClk', ctypes.c_uint32), 136 | ('ucVddInd', ctypes.c_ubyte), 137 | ('usCKSVOffsetandDisable', ctypes.c_uint16), 138 | ('usAVFSOffset', ctypes.c_uint16), 139 | ] 140 | 141 | ATOM_Vega10_GFXCLK_Dependency_Record = struct__ATOM_Vega10_GFXCLK_Dependency_Record 142 | class struct__ATOM_Vega10_GFXCLK_Dependency_Record_V2(ctypes.LittleEndianStructure): 143 | _pack_ = True # source:False 144 | _fields_ = [ 145 | ('ulClk', ctypes.c_uint32), 146 | ('ucVddInd', ctypes.c_ubyte), 147 | ('usCKSVOffsetandDisable', ctypes.c_uint16), 148 | ('usAVFSOffset', ctypes.c_uint16), 149 | ('ucACGEnable', ctypes.c_ubyte), 150 | ('ucReserved', ctypes.c_ubyte * 3), 151 | ] 152 | 153 | ATOM_Vega10_GFXCLK_Dependency_Record_V2 = struct__ATOM_Vega10_GFXCLK_Dependency_Record_V2 154 | class struct__ATOM_Vega10_MCLK_Dependency_Record(ctypes.LittleEndianStructure): 155 | _pack_ = True # source:False 156 | _fields_ = [ 157 | ('ulMemClk', ctypes.c_uint32), 158 | ('ucVddInd', ctypes.c_ubyte), 159 | ('ucVddMemInd', ctypes.c_ubyte), 160 | ('ucVddciInd', ctypes.c_ubyte), 161 | ] 162 | 163 | ATOM_Vega10_MCLK_Dependency_Record = struct__ATOM_Vega10_MCLK_Dependency_Record 164 | class struct__ATOM_Vega10_GFXCLK_Dependency_Table(ctypes.LittleEndianStructure): 165 | _pack_ = True # source:False 166 | _fields_ = [ 167 | ('ucRevId', ctypes.c_ubyte), 168 | ('ucNumEntries', ctypes.c_ubyte), 169 | ('entries', struct__ATOM_Vega10_GFXCLK_Dependency_Record * 1), 170 | ] 171 | 172 | ATOM_Vega10_GFXCLK_Dependency_Table = struct__ATOM_Vega10_GFXCLK_Dependency_Table 173 | class struct__ATOM_Vega10_MCLK_Dependency_Table(ctypes.LittleEndianStructure): 174 | _pack_ = True # source:False 175 | _fields_ = [ 176 | ('ucRevId', ctypes.c_ubyte), 177 | ('ucNumEntries', ctypes.c_ubyte), 178 | ('entries', struct__ATOM_Vega10_MCLK_Dependency_Record * 1), 179 | ] 180 | 181 | ATOM_Vega10_MCLK_Dependency_Table = struct__ATOM_Vega10_MCLK_Dependency_Table 182 | class struct__ATOM_Vega10_SOCCLK_Dependency_Table(ctypes.LittleEndianStructure): 183 | _pack_ = True # source:False 184 | _fields_ = [ 185 | ('ucRevId', ctypes.c_ubyte), 186 | ('ucNumEntries', ctypes.c_ubyte), 187 | ('entries', struct__ATOM_Vega10_CLK_Dependency_Record * 1), 188 | ] 189 | 190 | ATOM_Vega10_SOCCLK_Dependency_Table = struct__ATOM_Vega10_SOCCLK_Dependency_Table 191 | class struct__ATOM_Vega10_DCEFCLK_Dependency_Table(ctypes.LittleEndianStructure): 192 | _pack_ = True # source:False 193 | _fields_ = [ 194 | ('ucRevId', ctypes.c_ubyte), 195 | ('ucNumEntries', ctypes.c_ubyte), 196 | ('entries', struct__ATOM_Vega10_CLK_Dependency_Record * 1), 197 | ] 198 | 199 | ATOM_Vega10_DCEFCLK_Dependency_Table = struct__ATOM_Vega10_DCEFCLK_Dependency_Table 200 | class struct__ATOM_Vega10_PIXCLK_Dependency_Table(ctypes.LittleEndianStructure): 201 | _pack_ = True # source:False 202 | _fields_ = [ 203 | ('ucRevId', ctypes.c_ubyte), 204 | ('ucNumEntries', ctypes.c_ubyte), 205 | ('entries', struct__ATOM_Vega10_CLK_Dependency_Record * 1), 206 | ] 207 | 208 | ATOM_Vega10_PIXCLK_Dependency_Table = struct__ATOM_Vega10_PIXCLK_Dependency_Table 209 | class struct__ATOM_Vega10_DISPCLK_Dependency_Table(ctypes.LittleEndianStructure): 210 | _pack_ = True # source:False 211 | _fields_ = [ 212 | ('ucRevId', ctypes.c_ubyte), 213 | ('ucNumEntries', ctypes.c_ubyte), 214 | ('entries', struct__ATOM_Vega10_CLK_Dependency_Record * 1), 215 | ] 216 | 217 | ATOM_Vega10_DISPCLK_Dependency_Table = struct__ATOM_Vega10_DISPCLK_Dependency_Table 218 | class struct__ATOM_Vega10_PHYCLK_Dependency_Table(ctypes.LittleEndianStructure): 219 | _pack_ = True # source:False 220 | _fields_ = [ 221 | ('ucRevId', ctypes.c_ubyte), 222 | ('ucNumEntries', ctypes.c_ubyte), 223 | ('entries', struct__ATOM_Vega10_CLK_Dependency_Record * 1), 224 | ] 225 | 226 | ATOM_Vega10_PHYCLK_Dependency_Table = struct__ATOM_Vega10_PHYCLK_Dependency_Table 227 | class struct__ATOM_Vega10_MM_Dependency_Record(ctypes.LittleEndianStructure): 228 | _pack_ = True # source:False 229 | _fields_ = [ 230 | ('ucVddcInd', ctypes.c_ubyte), 231 | ('ulDClk', ctypes.c_uint32), 232 | ('ulVClk', ctypes.c_uint32), 233 | ('ulEClk', ctypes.c_uint32), 234 | ('ulPSPClk', ctypes.c_uint32), 235 | ] 236 | 237 | ATOM_Vega10_MM_Dependency_Record = struct__ATOM_Vega10_MM_Dependency_Record 238 | class struct__ATOM_Vega10_MM_Dependency_Table(ctypes.LittleEndianStructure): 239 | _pack_ = True # source:False 240 | _fields_ = [ 241 | ('ucRevId', ctypes.c_ubyte), 242 | ('ucNumEntries', ctypes.c_ubyte), 243 | ('entries', struct__ATOM_Vega10_MM_Dependency_Record * 1), 244 | ] 245 | 246 | ATOM_Vega10_MM_Dependency_Table = struct__ATOM_Vega10_MM_Dependency_Table 247 | class struct__ATOM_Vega10_PCIE_Record(ctypes.LittleEndianStructure): 248 | _pack_ = True # source:False 249 | _fields_ = [ 250 | ('ulLCLK', ctypes.c_uint32), 251 | ('ucPCIEGenSpeed', ctypes.c_ubyte), 252 | ('ucPCIELaneWidth', ctypes.c_ubyte), 253 | ] 254 | 255 | ATOM_Vega10_PCIE_Record = struct__ATOM_Vega10_PCIE_Record 256 | class struct__ATOM_Vega10_PCIE_Table(ctypes.LittleEndianStructure): 257 | _pack_ = True # source:False 258 | _fields_ = [ 259 | ('ucRevId', ctypes.c_ubyte), 260 | ('ucNumEntries', ctypes.c_ubyte), 261 | ('entries', struct__ATOM_Vega10_PCIE_Record * 1), 262 | ] 263 | 264 | ATOM_Vega10_PCIE_Table = struct__ATOM_Vega10_PCIE_Table 265 | class struct__ATOM_Vega10_Voltage_Lookup_Record(ctypes.LittleEndianStructure): 266 | _pack_ = True # source:False 267 | _fields_ = [ 268 | ('usVdd', ctypes.c_uint16), 269 | ] 270 | 271 | ATOM_Vega10_Voltage_Lookup_Record = struct__ATOM_Vega10_Voltage_Lookup_Record 272 | class struct__ATOM_Vega10_Voltage_Lookup_Table(ctypes.LittleEndianStructure): 273 | _pack_ = True # source:False 274 | _fields_ = [ 275 | ('ucRevId', ctypes.c_ubyte), 276 | ('ucNumEntries', ctypes.c_ubyte), 277 | ('entries', struct__ATOM_Vega10_Voltage_Lookup_Record * 1), 278 | ] 279 | 280 | ATOM_Vega10_Voltage_Lookup_Table = struct__ATOM_Vega10_Voltage_Lookup_Table 281 | class struct__ATOM_Vega10_Fan_Table(ctypes.LittleEndianStructure): 282 | _pack_ = True # source:False 283 | _fields_ = [ 284 | ('ucRevId', ctypes.c_ubyte), 285 | ('usFanOutputSensitivity', ctypes.c_uint16), 286 | ('usFanRPMMax', ctypes.c_uint16), 287 | ('usThrottlingRPM', ctypes.c_uint16), 288 | ('usFanAcousticLimit', ctypes.c_uint16), 289 | ('usTargetTemperature', ctypes.c_uint16), 290 | ('usMinimumPWMLimit', ctypes.c_uint16), 291 | ('usTargetGfxClk', ctypes.c_uint16), 292 | ('usFanGainEdge', ctypes.c_uint16), 293 | ('usFanGainHotspot', ctypes.c_uint16), 294 | ('usFanGainLiquid', ctypes.c_uint16), 295 | ('usFanGainVrVddc', ctypes.c_uint16), 296 | ('usFanGainVrMvdd', ctypes.c_uint16), 297 | ('usFanGainPlx', ctypes.c_uint16), 298 | ('usFanGainHbm', ctypes.c_uint16), 299 | ('ucEnableZeroRPM', ctypes.c_ubyte), 300 | ('usFanStopTemperature', ctypes.c_uint16), 301 | ('usFanStartTemperature', ctypes.c_uint16), 302 | ] 303 | 304 | ATOM_Vega10_Fan_Table = struct__ATOM_Vega10_Fan_Table 305 | class struct__ATOM_Vega10_Fan_Table_V2(ctypes.LittleEndianStructure): 306 | _pack_ = True # source:False 307 | _fields_ = [ 308 | ('ucRevId', ctypes.c_ubyte), 309 | ('usFanOutputSensitivity', ctypes.c_uint16), 310 | ('usFanAcousticLimitRpm', ctypes.c_uint16), 311 | ('usThrottlingRPM', ctypes.c_uint16), 312 | ('usTargetTemperature', ctypes.c_uint16), 313 | ('usMinimumPWMLimit', ctypes.c_uint16), 314 | ('usTargetGfxClk', ctypes.c_uint16), 315 | ('usFanGainEdge', ctypes.c_uint16), 316 | ('usFanGainHotspot', ctypes.c_uint16), 317 | ('usFanGainLiquid', ctypes.c_uint16), 318 | ('usFanGainVrVddc', ctypes.c_uint16), 319 | ('usFanGainVrMvdd', ctypes.c_uint16), 320 | ('usFanGainPlx', ctypes.c_uint16), 321 | ('usFanGainHbm', ctypes.c_uint16), 322 | ('ucEnableZeroRPM', ctypes.c_ubyte), 323 | ('usFanStopTemperature', ctypes.c_uint16), 324 | ('usFanStartTemperature', ctypes.c_uint16), 325 | ('ucFanParameters', ctypes.c_ubyte), 326 | ('ucFanMinRPM', ctypes.c_ubyte), 327 | ('ucFanMaxRPM', ctypes.c_ubyte), 328 | ] 329 | 330 | ATOM_Vega10_Fan_Table_V2 = struct__ATOM_Vega10_Fan_Table_V2 331 | class struct__ATOM_Vega10_Fan_Table_V3(ctypes.LittleEndianStructure): 332 | _pack_ = True # source:False 333 | _fields_ = [ 334 | ('ucRevId', ctypes.c_ubyte), 335 | ('usFanOutputSensitivity', ctypes.c_uint16), 336 | ('usFanAcousticLimitRpm', ctypes.c_uint16), 337 | ('usThrottlingRPM', ctypes.c_uint16), 338 | ('usTargetTemperature', ctypes.c_uint16), 339 | ('usMinimumPWMLimit', ctypes.c_uint16), 340 | ('usTargetGfxClk', ctypes.c_uint16), 341 | ('usFanGainEdge', ctypes.c_uint16), 342 | ('usFanGainHotspot', ctypes.c_uint16), 343 | ('usFanGainLiquid', ctypes.c_uint16), 344 | ('usFanGainVrVddc', ctypes.c_uint16), 345 | ('usFanGainVrMvdd', ctypes.c_uint16), 346 | ('usFanGainPlx', ctypes.c_uint16), 347 | ('usFanGainHbm', ctypes.c_uint16), 348 | ('ucEnableZeroRPM', ctypes.c_ubyte), 349 | ('usFanStopTemperature', ctypes.c_uint16), 350 | ('usFanStartTemperature', ctypes.c_uint16), 351 | ('ucFanParameters', ctypes.c_ubyte), 352 | ('ucFanMinRPM', ctypes.c_ubyte), 353 | ('ucFanMaxRPM', ctypes.c_ubyte), 354 | ('usMGpuThrottlingRPM', ctypes.c_uint16), 355 | ] 356 | 357 | ATOM_Vega10_Fan_Table_V3 = struct__ATOM_Vega10_Fan_Table_V3 358 | class struct__ATOM_Vega10_Thermal_Controller(ctypes.LittleEndianStructure): 359 | _pack_ = True # source:False 360 | _fields_ = [ 361 | ('ucRevId', ctypes.c_ubyte), 362 | ('ucType', ctypes.c_ubyte), 363 | ('ucI2cLine', ctypes.c_ubyte), 364 | ('ucI2cAddress', ctypes.c_ubyte), 365 | ('ucFanParameters', ctypes.c_ubyte), 366 | ('ucFanMinRPM', ctypes.c_ubyte), 367 | ('ucFanMaxRPM', ctypes.c_ubyte), 368 | ('ucFlags', ctypes.c_ubyte), 369 | ] 370 | 371 | ATOM_Vega10_Thermal_Controller = struct__ATOM_Vega10_Thermal_Controller 372 | class struct__ATOM_Vega10_VCE_State_Record(ctypes.LittleEndianStructure): 373 | _pack_ = True # source:False 374 | _fields_ = [ 375 | ('ucVCEClockIndex', ctypes.c_ubyte), 376 | ('ucFlag', ctypes.c_ubyte), 377 | ('ucSCLKIndex', ctypes.c_ubyte), 378 | ('ucMCLKIndex', ctypes.c_ubyte), 379 | ] 380 | 381 | ATOM_Vega10_VCE_State_Record = struct__ATOM_Vega10_VCE_State_Record 382 | class struct__ATOM_Vega10_VCE_State_Table(ctypes.LittleEndianStructure): 383 | _pack_ = True # source:False 384 | _fields_ = [ 385 | ('ucRevId', ctypes.c_ubyte), 386 | ('ucNumEntries', ctypes.c_ubyte), 387 | ('entries', struct__ATOM_Vega10_VCE_State_Record * 1), 388 | ] 389 | 390 | ATOM_Vega10_VCE_State_Table = struct__ATOM_Vega10_VCE_State_Table 391 | class struct__ATOM_Vega10_PowerTune_Table(ctypes.LittleEndianStructure): 392 | _pack_ = True # source:False 393 | _fields_ = [ 394 | ('ucRevId', ctypes.c_ubyte), 395 | ('usSocketPowerLimit', ctypes.c_uint16), 396 | ('usBatteryPowerLimit', ctypes.c_uint16), 397 | ('usSmallPowerLimit', ctypes.c_uint16), 398 | ('usTdcLimit', ctypes.c_uint16), 399 | ('usEdcLimit', ctypes.c_uint16), 400 | ('usSoftwareShutdownTemp', ctypes.c_uint16), 401 | ('usTemperatureLimitHotSpot', ctypes.c_uint16), 402 | ('usTemperatureLimitLiquid1', ctypes.c_uint16), 403 | ('usTemperatureLimitLiquid2', ctypes.c_uint16), 404 | ('usTemperatureLimitHBM', ctypes.c_uint16), 405 | ('usTemperatureLimitVrSoc', ctypes.c_uint16), 406 | ('usTemperatureLimitVrMem', ctypes.c_uint16), 407 | ('usTemperatureLimitPlx', ctypes.c_uint16), 408 | ('usLoadLineResistance', ctypes.c_uint16), 409 | ('ucLiquid1_I2C_address', ctypes.c_ubyte), 410 | ('ucLiquid2_I2C_address', ctypes.c_ubyte), 411 | ('ucVr_I2C_address', ctypes.c_ubyte), 412 | ('ucPlx_I2C_address', ctypes.c_ubyte), 413 | ('ucLiquid_I2C_LineSCL', ctypes.c_ubyte), 414 | ('ucLiquid_I2C_LineSDA', ctypes.c_ubyte), 415 | ('ucVr_I2C_LineSCL', ctypes.c_ubyte), 416 | ('ucVr_I2C_LineSDA', ctypes.c_ubyte), 417 | ('ucPlx_I2C_LineSCL', ctypes.c_ubyte), 418 | ('ucPlx_I2C_LineSDA', ctypes.c_ubyte), 419 | ('usTemperatureLimitTedge', ctypes.c_uint16), 420 | ] 421 | 422 | ATOM_Vega10_PowerTune_Table = struct__ATOM_Vega10_PowerTune_Table 423 | class struct__ATOM_Vega10_PowerTune_Table_V2(ctypes.LittleEndianStructure): 424 | _pack_ = True # source:False 425 | _fields_ = [ 426 | ('ucRevId', ctypes.c_ubyte), 427 | ('usSocketPowerLimit', ctypes.c_uint16), 428 | ('usBatteryPowerLimit', ctypes.c_uint16), 429 | ('usSmallPowerLimit', ctypes.c_uint16), 430 | ('usTdcLimit', ctypes.c_uint16), 431 | ('usEdcLimit', ctypes.c_uint16), 432 | ('usSoftwareShutdownTemp', ctypes.c_uint16), 433 | ('usTemperatureLimitHotSpot', ctypes.c_uint16), 434 | ('usTemperatureLimitLiquid1', ctypes.c_uint16), 435 | ('usTemperatureLimitLiquid2', ctypes.c_uint16), 436 | ('usTemperatureLimitHBM', ctypes.c_uint16), 437 | ('usTemperatureLimitVrSoc', ctypes.c_uint16), 438 | ('usTemperatureLimitVrMem', ctypes.c_uint16), 439 | ('usTemperatureLimitPlx', ctypes.c_uint16), 440 | ('usLoadLineResistance', ctypes.c_uint16), 441 | ('ucLiquid1_I2C_address', ctypes.c_ubyte), 442 | ('ucLiquid2_I2C_address', ctypes.c_ubyte), 443 | ('ucLiquid_I2C_Line', ctypes.c_ubyte), 444 | ('ucVr_I2C_address', ctypes.c_ubyte), 445 | ('ucVr_I2C_Line', ctypes.c_ubyte), 446 | ('ucPlx_I2C_address', ctypes.c_ubyte), 447 | ('ucPlx_I2C_Line', ctypes.c_ubyte), 448 | ('usTemperatureLimitTedge', ctypes.c_uint16), 449 | ] 450 | 451 | ATOM_Vega10_PowerTune_Table_V2 = struct__ATOM_Vega10_PowerTune_Table_V2 452 | class struct__ATOM_Vega10_PowerTune_Table_V3(ctypes.LittleEndianStructure): 453 | _pack_ = True # source:False 454 | _fields_ = [ 455 | ('ucRevId', ctypes.c_ubyte), 456 | ('usSocketPowerLimit', ctypes.c_uint16), 457 | ('usBatteryPowerLimit', ctypes.c_uint16), 458 | ('usSmallPowerLimit', ctypes.c_uint16), 459 | ('usTdcLimit', ctypes.c_uint16), 460 | ('usEdcLimit', ctypes.c_uint16), 461 | ('usSoftwareShutdownTemp', ctypes.c_uint16), 462 | ('usTemperatureLimitHotSpot', ctypes.c_uint16), 463 | ('usTemperatureLimitLiquid1', ctypes.c_uint16), 464 | ('usTemperatureLimitLiquid2', ctypes.c_uint16), 465 | ('usTemperatureLimitHBM', ctypes.c_uint16), 466 | ('usTemperatureLimitVrSoc', ctypes.c_uint16), 467 | ('usTemperatureLimitVrMem', ctypes.c_uint16), 468 | ('usTemperatureLimitPlx', ctypes.c_uint16), 469 | ('usLoadLineResistance', ctypes.c_uint16), 470 | ('ucLiquid1_I2C_address', ctypes.c_ubyte), 471 | ('ucLiquid2_I2C_address', ctypes.c_ubyte), 472 | ('ucLiquid_I2C_Line', ctypes.c_ubyte), 473 | ('ucVr_I2C_address', ctypes.c_ubyte), 474 | ('ucVr_I2C_Line', ctypes.c_ubyte), 475 | ('ucPlx_I2C_address', ctypes.c_ubyte), 476 | ('ucPlx_I2C_Line', ctypes.c_ubyte), 477 | ('usTemperatureLimitTedge', ctypes.c_uint16), 478 | ('usBoostStartTemperature', ctypes.c_uint16), 479 | ('usBoostStopTemperature', ctypes.c_uint16), 480 | ('ulBoostClock', ctypes.c_uint32), 481 | ('Reserved', ctypes.c_uint32 * 2), 482 | ] 483 | 484 | ATOM_Vega10_PowerTune_Table_V3 = struct__ATOM_Vega10_PowerTune_Table_V3 485 | class struct__ATOM_Vega10_Hard_Limit_Record(ctypes.LittleEndianStructure): 486 | _pack_ = True # source:False 487 | _fields_ = [ 488 | ('ulSOCCLKLimit', ctypes.c_uint32), 489 | ('ulGFXCLKLimit', ctypes.c_uint32), 490 | ('ulMCLKLimit', ctypes.c_uint32), 491 | ('usVddcLimit', ctypes.c_uint16), 492 | ('usVddciLimit', ctypes.c_uint16), 493 | ('usVddMemLimit', ctypes.c_uint16), 494 | ] 495 | 496 | ATOM_Vega10_Hard_Limit_Record = struct__ATOM_Vega10_Hard_Limit_Record 497 | class struct__ATOM_Vega10_Hard_Limit_Table(ctypes.LittleEndianStructure): 498 | _pack_ = True # source:False 499 | _fields_ = [ 500 | ('ucRevId', ctypes.c_ubyte), 501 | ('ucNumEntries', ctypes.c_ubyte), 502 | ('entries', struct__ATOM_Vega10_Hard_Limit_Record * 1), 503 | ] 504 | 505 | ATOM_Vega10_Hard_Limit_Table = struct__ATOM_Vega10_Hard_Limit_Table 506 | class struct__Vega10_PPTable_Generic_SubTable_Header(ctypes.LittleEndianStructure): 507 | _pack_ = True # source:False 508 | _fields_ = [ 509 | ('ucRevId', ctypes.c_ubyte), 510 | ] 511 | 512 | Vega10_PPTable_Generic_SubTable_Header = struct__Vega10_PPTable_Generic_SubTable_Header 513 | __all__ =\ 514 | ['ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2', 515 | 'ATOM_PPLIB_CLASSIFICATION_ACPI', 516 | 'ATOM_PPLIB_CLASSIFICATION_BOOT', 517 | 'ATOM_PPLIB_CLASSIFICATION_FORCED', 518 | 'ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE', 519 | 'ATOM_PPLIB_CLASSIFICATION_REST', 520 | 'ATOM_PPLIB_CLASSIFICATION_THERMAL', 521 | 'ATOM_PPLIB_CLASSIFICATION_UI_BALANCED', 522 | 'ATOM_PPLIB_CLASSIFICATION_UI_BATTERY', 523 | 'ATOM_PPLIB_CLASSIFICATION_UI_MASK', 524 | 'ATOM_PPLIB_CLASSIFICATION_UI_NONE', 525 | 'ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE', 526 | 'ATOM_PPLIB_CLASSIFICATION_UI_SHIFT', 527 | 'ATOM_VEGA10_PP_FANPARAMETERS_NOFAN', 528 | 'ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK', 529 | 'ATOM_VEGA10_PP_PLATFORM_CAP_BACO', 530 | 'ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC', 531 | 'ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY', 532 | 'ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE', 533 | 'ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL', 534 | 'ATOM_VEGA10_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL', 535 | 'ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL', 536 | 'ATOM_VEGA10_PP_THERMALCONTROLLER_LM96163', 537 | 'ATOM_VEGA10_PP_THERMALCONTROLLER_NONE', 538 | 'ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10', 539 | 'ATOM_Vega10_CLK_Dependency_Record', 540 | 'ATOM_Vega10_DCEFCLK_Dependency_Table', 541 | 'ATOM_Vega10_DISALLOW_ON_DC', 542 | 'ATOM_Vega10_DISPCLK_Dependency_Table', 543 | 'ATOM_Vega10_ENABLE_VARIBRIGHT', 'ATOM_Vega10_Fan_Table', 544 | 'ATOM_Vega10_Fan_Table_V2', 'ATOM_Vega10_Fan_Table_V3', 545 | 'ATOM_Vega10_GFXCLK_Dependency_Record', 546 | 'ATOM_Vega10_GFXCLK_Dependency_Record_V2', 547 | 'ATOM_Vega10_GFXCLK_Dependency_Table', 548 | 'ATOM_Vega10_Hard_Limit_Record', 'ATOM_Vega10_Hard_Limit_Table', 549 | 'ATOM_Vega10_MCLK_Dependency_Record', 550 | 'ATOM_Vega10_MCLK_Dependency_Table', 551 | 'ATOM_Vega10_MM_Dependency_Record', 552 | 'ATOM_Vega10_MM_Dependency_Table', 'ATOM_Vega10_PCIE_Record', 553 | 'ATOM_Vega10_PCIE_Table', 'ATOM_Vega10_PHYCLK_Dependency_Table', 554 | 'ATOM_Vega10_PIXCLK_Dependency_Table', 555 | 'ATOM_Vega10_POWERPLAYTABLE', 'ATOM_Vega10_PowerTune_Table', 556 | 'ATOM_Vega10_PowerTune_Table_V2', 557 | 'ATOM_Vega10_PowerTune_Table_V3', 558 | 'ATOM_Vega10_SOCCLK_Dependency_Table', 'ATOM_Vega10_State', 559 | 'ATOM_Vega10_State_Array', 'ATOM_Vega10_TABLE_REVISION_VEGA10', 560 | 'ATOM_Vega10_Thermal_Controller', 'ATOM_Vega10_VCE_State_Record', 561 | 'ATOM_Vega10_VCE_State_Table', 562 | 'ATOM_Vega10_VoltageMode_AVFS_Interpolate', 563 | 'ATOM_Vega10_VoltageMode_AVFS_WorstCase', 564 | 'ATOM_Vega10_VoltageMode_Static', 565 | 'ATOM_Vega10_Voltage_Lookup_Record', 566 | 'ATOM_Vega10_Voltage_Lookup_Table', 567 | 'Vega10_PPTable_Generic_SubTable_Header', '_VEGA10_PPTABLE_H_', 568 | 'struct__ATOM_Vega10_CLK_Dependency_Record', 569 | 'struct__ATOM_Vega10_DCEFCLK_Dependency_Table', 570 | 'struct__ATOM_Vega10_DISPCLK_Dependency_Table', 571 | 'struct__ATOM_Vega10_Fan_Table', 572 | 'struct__ATOM_Vega10_Fan_Table_V2', 573 | 'struct__ATOM_Vega10_Fan_Table_V3', 574 | 'struct__ATOM_Vega10_GFXCLK_Dependency_Record', 575 | 'struct__ATOM_Vega10_GFXCLK_Dependency_Record_V2', 576 | 'struct__ATOM_Vega10_GFXCLK_Dependency_Table', 577 | 'struct__ATOM_Vega10_Hard_Limit_Record', 578 | 'struct__ATOM_Vega10_Hard_Limit_Table', 579 | 'struct__ATOM_Vega10_MCLK_Dependency_Record', 580 | 'struct__ATOM_Vega10_MCLK_Dependency_Table', 581 | 'struct__ATOM_Vega10_MM_Dependency_Record', 582 | 'struct__ATOM_Vega10_MM_Dependency_Table', 583 | 'struct__ATOM_Vega10_PCIE_Record', 584 | 'struct__ATOM_Vega10_PCIE_Table', 585 | 'struct__ATOM_Vega10_PHYCLK_Dependency_Table', 586 | 'struct__ATOM_Vega10_PIXCLK_Dependency_Table', 587 | 'struct__ATOM_Vega10_POWERPLAYTABLE', 588 | 'struct__ATOM_Vega10_PowerTune_Table', 589 | 'struct__ATOM_Vega10_PowerTune_Table_V2', 590 | 'struct__ATOM_Vega10_PowerTune_Table_V3', 591 | 'struct__ATOM_Vega10_SOCCLK_Dependency_Table', 592 | 'struct__ATOM_Vega10_State', 'struct__ATOM_Vega10_State_Array', 593 | 'struct__ATOM_Vega10_Thermal_Controller', 594 | 'struct__ATOM_Vega10_VCE_State_Record', 595 | 'struct__ATOM_Vega10_VCE_State_Table', 596 | 'struct__ATOM_Vega10_Voltage_Lookup_Record', 597 | 'struct__ATOM_Vega10_Voltage_Lookup_Table', 598 | 'struct__Vega10_PPTable_Generic_SubTable_Header', 599 | 'struct_atom_common_table_header'] 600 | --------------------------------------------------------------------------------