├── .gitattributes ├── nau8822 └── nau8822 │ ├── main.cpp │ ├── src │ ├── nau8822_code │ │ ├── nau8822.c │ │ ├── nau8822_hardware.h │ │ ├── NAU8822_hardware.cpp │ │ ├── nau8822.h │ │ ├── nau8822_map_reg.h │ │ └── nau8822_types.h │ ├── delay.cpp │ ├── delay.h │ ├── gpio.h │ ├── i2c │ │ ├── i2c_soft_gpio.h │ │ └── i2c_soft_gpio.cpp │ ├── interfaces │ │ ├── serial │ │ │ ├── serial.h │ │ │ └── serial.cpp │ │ └── i2c │ │ │ ├── i2c_soft.h │ │ │ └── i2c_soft.cpp │ └── gpio.cpp │ └── Debug │ └── Makefile ├── .gitignore ├── README.md └── nau8822 PCM spec /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /nau8822/nau8822/main.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analityk/nau8822/HEAD/nau8822/nau8822/main.cpp -------------------------------------------------------------------------------- /nau8822/nau8822/src/nau8822_code/nau8822.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analityk/nau8822/HEAD/nau8822/nau8822/src/nau8822_code/nau8822.c -------------------------------------------------------------------------------- /nau8822/nau8822/src/delay.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #ifdef __cplusplus 4 | extern "C" { 5 | #endif 6 | 7 | void delay(uint32_t volatile t){ 8 | while(t--){}; 9 | }; 10 | 11 | #ifdef __cplusplus 12 | } 13 | 14 | #endif 15 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/delay.h: -------------------------------------------------------------------------------- 1 | #ifndef delay_h__ 2 | #define delay_h__ 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | 11 | void delay(uint32_t volatile t); 12 | 13 | #ifdef __cplusplus 14 | } 15 | #endif 16 | 17 | #endif // delay_h__ 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.debug 2 | *.atsuo 3 | *.xml 4 | *.cppproj 5 | *.eep 6 | *.elf 7 | *.hex 8 | *.lss 9 | *.map 10 | *.srec 11 | *.mk 12 | *.d 13 | *.slo 14 | *.o 15 | *.obj 16 | *.gch 17 | *.pch 18 | *.so 19 | *.dylib 20 | *.dll 21 | *.mod 22 | *.smod 23 | *.lai 24 | *.la 25 | *.a 26 | *.lib 27 | *.exe 28 | *.out 29 | *.app 30 | *.atsln 31 | debug/** 32 | release/** 33 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/nau8822_code/nau8822_hardware.h: -------------------------------------------------------------------------------- 1 | #ifndef nau8822_hardware_h__ 2 | #define nau8822_hardware_h__ 3 | 4 | #include 5 | #include 6 | #ifdef __cplusplus 7 | extern "C"{ 8 | #endif 9 | 10 | uint8_t nau8822_register_write(uint8_t reg_number, uint16_t reg_value); 11 | 12 | 13 | #ifdef __cplusplus 14 | } 15 | #endif 16 | 17 | #endif // nau8822_hardware_h__ 18 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/nau8822_code/NAU8822_hardware.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #ifdef __cplusplus 4 | extern "C" { 5 | #endif 6 | 7 | uint8_t nau8822_register_write(uint8_t reg_number, uint16_t reg_value) 8 | { 9 | #ifdef NAU8822_INTERFACE_I2C 10 | return i2c_codec_write(reg_number, reg_value); 11 | #elif NAU8822_INTERFACE_SPI 12 | #else 13 | #error "you should choos interface to communicate with your codec" 14 | #endif 15 | 16 | } 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef gpio_h__ 2 | #define gpio_h__ 3 | 4 | #include 5 | 6 | class GPIO { 7 | public: 8 | volatile uint8_t* port; 9 | volatile uint8_t pin; 10 | 11 | GPIO(); 12 | GPIO(volatile uint8_t* port, uint8_t pin); 13 | 14 | void set(void); 15 | 16 | void i2c_set(void); 17 | void i2c_clr(void); 18 | 19 | void clear(void); 20 | 21 | void release(void); 22 | 23 | void flip(void); 24 | 25 | uint8_t read(void); 26 | 27 | uint8_t readOpenDrain(void); 28 | uint8_t readPullUp(void); 29 | }; 30 | 31 | 32 | #endif // gpio_h__ 33 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/i2c/i2c_soft_gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef i2c_soft_gpio_h__ 2 | #define i2c_soft_gpio_h__ 3 | 4 | #include 5 | #include 6 | #include 7 | 8 | class i2c_soft_gpio{ 9 | public: 10 | 11 | GPIO* sda; 12 | GPIO* scl; 13 | uint16_t i2c_delay; 14 | 15 | i2c_soft_gpio(GPIO* gpio_sda, GPIO* gpio_scl, uint16_t wait); 16 | 17 | void init(void); 18 | void start(void); 19 | void stop(void); 20 | void write(uint8_t b); 21 | 22 | uint8_t i2c_ack(void); 23 | 24 | uint8_t i2c_codec_write(uint8_t adr, uint16_t data); 25 | uint8_t get_sda(void); 26 | }; 27 | 28 | 29 | #endif // i2c_soft_gpio_h__ 30 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/interfaces/serial/serial.h: -------------------------------------------------------------------------------- 1 | #ifndef serial_h__ 2 | #define serial_h__ 3 | 4 | #include 5 | #include 6 | 7 | class serial{ 8 | public: 9 | serial(void); 10 | 11 | void SetUbrr(uint16_t ubrr); 12 | void Enable(void); 13 | void Disable(void); 14 | void InterruptEnable_RX(void); 15 | void InterruptDisable_RX(void); 16 | void write(uint8_t* buff, uint8_t size); 17 | void write(const char* s, uint8_t size); 18 | void write(char* t); 19 | void write(const char* s); 20 | void write(uint8_t byte); 21 | //void write(array &data); 22 | uint8_t readByte(void); 23 | }; 24 | 25 | extern serial Serial; 26 | 27 | 28 | 29 | #endif // serial_h__ -------------------------------------------------------------------------------- /nau8822/nau8822/src/interfaces/i2c/i2c_soft.h: -------------------------------------------------------------------------------- 1 | #ifndef i2c_soft_h__ 2 | #define i2c_soft_h__ 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | #define I2C_SDA_DDR (DDRD) 11 | #define I2C_SDA_PORT (PORTD) 12 | #define I2C_SDA_PIN (PIND) 13 | 14 | #define I2C_SCL_DDR (DDRD) 15 | #define I2C_SCL_PORT (PORTD) 16 | 17 | #define I2C_SDA (PIND4) 18 | #define I2C_SCL (PIND5) 19 | 20 | #define I2C_DELAY 70 21 | 22 | 23 | #ifdef SAM_UC 24 | #define CLR_SDA { pio_clear(I2C_SDA_PIO, I2C_SDA); } 25 | #define SET_SDA { pio_set(I2C_SDA_PIO, I2C_SDA); } 26 | #define CLR_SCL { pio_clear(I2C_SCL_PIO, I2C_SCL); } 27 | #define SET_SCL { pio_set(I2C_SCL_PIO, I2C_SCL); } 28 | #elif AVR_UC 29 | #define CLR_SDA { I2C_SDA_DDR |= (1< 2 | #include 3 | #include 4 | #include 5 | 6 | 7 | i2c_soft_gpio::i2c_soft_gpio(GPIO* gpio_sda, GPIO* gpio_scl, uint16_t wait): 8 | sda(gpio_sda), 9 | scl(gpio_scl), 10 | i2c_delay(wait) 11 | {}; 12 | 13 | void i2c_soft_gpio::init(void) 14 | { 15 | scl->i2c_set(); 16 | sda->i2c_set(); 17 | delay(i2c_delay); 18 | }; 19 | 20 | 21 | 22 | void i2c_soft_gpio::start(void) 23 | { 24 | sda->i2c_clr(); 25 | delay(i2c_delay); 26 | scl->i2c_clr(); 27 | delay(i2c_delay); 28 | }; 29 | 30 | void i2c_soft_gpio::stop(void) 31 | { 32 | sda->i2c_clr(); 33 | delay(i2c_delay); 34 | scl->i2c_set(); 35 | delay(i2c_delay); 36 | sda->i2c_set(); 37 | delay(i2c_delay); 38 | }; 39 | 40 | void i2c_soft_gpio::write(uint8_t b) 41 | { 42 | 43 | uint8_t volatile i = 0x80; 44 | for(uint8_t volatile t = 0x80; t>0; t >>= 1) 45 | { 46 | if(b & t){ 47 | sda->i2c_set(); 48 | }else{ 49 | sda->i2c_clr(); 50 | }; 51 | 52 | delay(i2c_delay); 53 | scl->i2c_set(); 54 | delay(i2c_delay); 55 | scl->i2c_clr(); 56 | delay(i2c_delay); 57 | }; 58 | 59 | sda->i2c_set(); 60 | delay(i2c_delay); 61 | }; 62 | 63 | uint8_t i2c_soft_gpio::i2c_ack(void) 64 | { 65 | uint8_t volatile t = 0; 66 | scl->i2c_set(); 67 | delay(i2c_delay); 68 | if(get_sda() == 1){ 69 | t = 1; 70 | }; 71 | scl->i2c_clr(); 72 | delay(i2c_delay); 73 | return t; 74 | }; 75 | 76 | uint8_t i2c_soft_gpio::get_sda(void) 77 | { 78 | sda->i2c_set(); 79 | 80 | uint8_t volatile u = sda->readPullUp(); 81 | 82 | if(u > 0){ 83 | return 1; 84 | }; 85 | 86 | return 0; 87 | }; -------------------------------------------------------------------------------- /nau8822/nau8822/src/interfaces/serial/serial.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | serial::serial(void){ 4 | this->Enable(); 5 | this->SetUbrr(19); 6 | }; 7 | 8 | void serial::SetUbrr(uint16_t ubrr){ 9 | UBRR0H = (uint8_t)(ubrr >> 8); 10 | UBRR0L = (uint8_t)(ubrr); 11 | }; 12 | 13 | void serial::Enable(void) 14 | { 15 | UCSR0B = (1< &data) 65 | //{ 66 | //for(uint8_t i=0; i 2 | 3 | GPIO::GPIO(volatile uint8_t* port, uint8_t pin) 4 | { 5 | this->port = port; 6 | this->pin = pin; 7 | }; 8 | 9 | GPIO::GPIO() 10 | { 11 | this->port = 0; 12 | this->pin = 0; 13 | }; 14 | 15 | void GPIO::set(void) 16 | { 17 | *this->port |= (1<port-1) |= (1<port-1) &=~ (1<port |= (1<port-1) |= (1<port &=~ (1<port &=~(1<port-1) |= (1<port &=~ (1<port-1) &=~ (1<port ^= (1<port-1) |= (1<port-2) & (1<port &=~(1<port-1) &=~ (1<port-2) & (1<port |= (1<port-1) &=~(1<port-2) & (1< 2 | 3 | #ifdef __cplusplus 4 | extern "C" { 5 | #endif 6 | 7 | uint8_t GET_SDA(void) 8 | { 9 | SET_SDA; // hi-z 10 | 11 | uint8_t volatile t = I2C_SDA_PIN; 12 | uint8_t volatile u = t & (1< 0){ 15 | return 1; 16 | }; 17 | 18 | return 0; 19 | 20 | return 0; 21 | }; 22 | 23 | void i2c_init(void){ 24 | SET_SCL; 25 | SET_SDA; 26 | delay(I2C_DELAY); 27 | }; 28 | 29 | 30 | void i2c_start(void) 31 | { 32 | CLR_SDA; 33 | delay(I2C_DELAY); 34 | CLR_SCL; 35 | delay(I2C_DELAY); 36 | }; 37 | 38 | void i2c_stop(void) 39 | { 40 | CLR_SDA; 41 | delay(I2C_DELAY); 42 | SET_SCL; 43 | delay(I2C_DELAY); 44 | SET_SDA; 45 | delay(I2C_DELAY); 46 | }; 47 | 48 | void i2c_write(uint8_t b) 49 | { 50 | uint8_t i = 0x80; 51 | 52 | for(; i; i >>= 1) 53 | { 54 | if(b & i){ SET_SDA; } else { CLR_SDA; }; 55 | 56 | delay(I2C_DELAY); 57 | SET_SCL; 58 | delay(I2C_DELAY); 59 | CLR_SCL; 60 | delay(I2C_DELAY); 61 | }; 62 | 63 | SET_SDA; 64 | delay(I2C_DELAY); 65 | }; 66 | 67 | 68 | uint8_t i2c_ack(void) 69 | { 70 | uint8_t volatile t = 0; 71 | SET_SCL; 72 | delay(I2C_DELAY); 73 | if(GET_SDA() == 1){ 74 | t = 1; 75 | }; 76 | CLR_SCL; 77 | delay(I2C_DELAY); 78 | return t; 79 | }; 80 | 81 | uint8_t i2c_codec_write(uint8_t adr, uint16_t data) 82 | { 83 | uint8_t data_tx = data & 0xFF; 84 | 85 | uint8_t b8 = (data & 0x0100) >> 8; 86 | 87 | uint8_t cd =(uint8_t)((adr << 1) | b8); 88 | 89 | uint8_t acks = 0; 90 | 91 | i2c_start(); 92 | i2c_write(0x34); 93 | i2c_ack(); 94 | i2c_write(cd); 95 | i2c_ack(); 96 | i2c_write(data_tx); 97 | i2c_ack(); 98 | i2c_stop(); 99 | 100 | return acks; 101 | }; 102 | 103 | #ifdef __cplusplus 104 | } 105 | #endif -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # NAU8822 2 | 8 analog inputs; 3 | 4 | I2S/PCM/a/b/time slot; 5 | 6 | 32b 48kHz ADC and DAC; 7 | 8 | digital high pass filter; 9 | 10 | automatic gain control for left and right differential (mic)/line input; 11 | 12 | notch filter; 13 | 14 | 5 band equalizer; 15 | 16 | 3D enchancement; 17 | 18 | DAC Dither; 19 | 20 | 6 analog mixers + 1 for differential output (power up to 1W); 21 | 22 | PLL - clock input from 8MHz to 33MHz; 23 | 24 | low noise bias current for electret mic; 25 | 26 | controlled by simple I2C interface; 27 | 28 | https://www.nuvoton.com/resource-files/NAU8822LDataSheetRev1.9.pdf 29 | 30 | Here you have simple piece of code for use this chip with, i believe, can be used for any uC architecture. Currently i test it on avr - on arduino nano. 31 | 32 | What you can build with this chip? If you will use simple uC - without i2s - this chip may be used as audio preamplifier with excellent sound quality. Moreover you are able to use sound equalizer - add a few rotary encoder to uC and drive codec in real time. You may to change sound source, volume on each source, you can mix it together or swap sound in left and right channel. You may choose active output - you have two, two-channels outputs (speakers and headphones) plus additional two auxiliary (single chanler or better - nonchannel) output from aux mixers. You may use simple and cheap ecm mic and if you connect it to differential input you can use ALC - automatic level (loudness) control features. 33 | 34 | I think all this features can be used with near any arduino. 35 | 36 | But here we have I2S. I've built with this chip ethernet audio streamer. I used this chip and Atmel SAM E70 Xplained board. Data from pc was sended in UDP packets into SAM E70 uC and from here into codec by I2S. This chip is cheap and awesome and if you want to try it without build own pcb - you can use (in near future, currently is under tests) my board and my drivers. 37 | 38 | Have a nice day! 39 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/nau8822_code/nau8822.h: -------------------------------------------------------------------------------- 1 | #ifndef nau8822_h__ 2 | #define nau8822_h__ 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | 9 | extern ts_nau8822 snau8822; 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | 16 | void nau8822_mute_all(void); 17 | 18 | void nau8822_power_up(void); 19 | 20 | uint16_t nau8822_gain(enum e_gains g); 21 | 22 | uint16_t nau8822_mic_bias_voltage(enum e_mic_bias_levels mbl); // voltage is equal to vdda times setting factor 23 | uint16_t nau8822_3d_enhancement(uint8_t level); // 0 - off, 15 - max; 24 | 25 | uint16_t nau8822_equ_src(enum e_equ_src es); // adc or dac 26 | uint16_t nau8822_equ_band_1(enum e_equ_band_1 eb1, int8_t level); // level <-12 .. 11> 27 | uint16_t nau8822_equ_band_2(enum e_equ_band_2 eb2, int8_t level); // level <-12 .. 11> 28 | uint16_t nau8822_equ_band_3(enum e_equ_band_3 eb3, int8_t level); // level <-12 .. 11> 29 | uint16_t nau8822_equ_band_4(enum e_equ_band_4 eb4, int8_t level); // level <-12 .. 11> 30 | uint16_t nau8822_equ_band_5(enum e_equ_band_5 eb5, int8_t level); // level <-12 .. 11> 31 | 32 | // outputs volumes 33 | uint16_t nau8822_headphone_volume(uint8_t left, uint8_t right); // level <0 .. 63> 34 | uint16_t nau8822_speaker_volume(uint8_t left, uint8_t right); // leve; <0 .. 63> 35 | 36 | // analog inputs 37 | uint16_t nau8822_left_in_mix_src(enum e_left_in_mix_srcs ms, uint8_t gain); // pga, lin or aux 38 | uint16_t nau8822_left_pga_in_src(enum e_left_pga_src ms, uint8_t gain); // mic or lin - can be gained by alc 39 | uint16_t nau8822_right_in_mix_src(enum e_right_in_mix_srcs ms, uint8_t gain); // pga, lin or aux 40 | uint16_t nau8822_right_pga_in_src(enum e_right_pga_src ms, uint8_t gain); // mix or lin - can be gained by alc 41 | 42 | // internal mixers 43 | uint16_t nau8822_left_main_mix_src(enum e_left_main_mix_srcs ms, uint8_t gain); // ldac, rdac, aux, in_mix stage 44 | uint16_t nau8822_right_main_mix_src(enum e_right_main_mix_srcs ms, uint8_t gain); // rdac, ldac, aux, in_mix stage 45 | uint16_t nau8822_aux_1_mix_src(enum e_aux_1_mix_srcs ms); // rinmix, ldac, rdac, lmix, rmix 46 | uint16_t nau8822_aux_2_mix_src(enum e_aux_2_mix_srcs ms); // aux1(!), linmix, ldac, lmix 47 | uint16_t nau8822_rspk_submix_src(enum e_submix_srcs ms); // rauxin or rmix 48 | 49 | // alc - automatic level control 50 | // this stuff can automatic set up gain on mic input (pga) or lin pga input 51 | // and hold the output stage signal on ~constant level (if sound source is resonably loud). 52 | // but it is a bit hard to proper setup, even if you work with datasheet, you propably will spent 53 | // here a more time. Anyway it is worth, output signal can be free of distorion and dynamic range 54 | // is wider than you think. I tested this future with signal gen and oscilloscope. 55 | // With input signal in range 15mV - 500mV output signal was constant on goal level about ~1Vp-p with 56 | // small deviation about 50mV WITHOUT distorion - just dynamic change of input gain 57 | // https://www.youtube.com/watch?v=RilggJd1_LY - this guy use alc in his mic. He is loud but never too 58 | // in 3 word: cool awsome nice future that you have to buy now... 59 | // lets back on ground 60 | // because you have to know how it work and how to setup it in your enviroment 61 | // i don't write here any high level api 62 | // lets look at example 63 | 64 | // but this function get your 4 register param and set it to proper register 65 | // however you may do it yourself 66 | void nau8822_set_alc(void); 67 | 68 | uint16_t nau8822_set_power_1(s_power_1* pw); // ok 69 | uint16_t nau8822_set_power_2(s_power_2* pw); // ok 70 | uint16_t nau8822_set_power_3(s_power_3* pw); 71 | uint16_t nau8822_set_power_4(s_power_4* pw); 72 | uint16_t nau8822_set_audio_interface(s_audio_interface* ai); 73 | uint16_t nau8822_set_companding(s_companding* c); 74 | uint16_t nau8822_set_clock_control_1(s_clock_control_1* c); 75 | uint16_t nau8822_set_clock_control_2(s_clock_control_2* c); 76 | uint16_t nau8822_set_gpio(s_gpio* g); 77 | uint16_t nau8822_set_jack_detect_1(s_jack_detect_1* j); 78 | uint16_t nau8822_set_dac_control(s_dac_control* d); 79 | uint16_t nau8822_set_left_dac_vol(s_left_dac_volume* d); 80 | uint16_t nau8822_set_right_dac_vol(s_right_dac_volume* d); 81 | uint16_t nau8822_set_jack_detect_2(s_jack_detect_2* j); 82 | uint16_t nau8822_set_adc_control(s_adc_control* c); 83 | uint16_t nau8822_set_left_adc_vol(s_left_adc_volume* c); 84 | uint16_t nau8822_set_right_adc_vol(s_right_adc_volume* c); 85 | uint16_t nau8822_set_eq1(s_eq1* e); 86 | uint16_t nau8822_set_eq2(s_eq2* e); 87 | uint16_t nau8822_set_eq3(s_eq3* e); 88 | uint16_t nau8822_set_eq4(s_eq4* e); 89 | uint16_t nau8822_set_eq5(s_eq5* e); 90 | uint16_t nau8822_set_dac_lim_1(s_dac_limiter_1* d); 91 | uint16_t nau8822_set_dac_lim_2(s_dac_limiter_2* d); 92 | uint16_t nau8822_set_notch_1(s_notch_filter_1* n); 93 | uint16_t nau8822_set_notch_2(s_notch_filter_2* n); 94 | uint16_t nau8822_set_notch_3(s_notch_filter_3* n); 95 | uint16_t nau8822_set_notch_4(s_notch_filter_4* n); 96 | uint16_t nau8822_set_alc_1(s_alc_control_1* a); 97 | uint16_t nau8822_set_alc_2(s_alc_control_2* a); 98 | uint16_t nau8822_set_alc_3(s_alc_control_3* a); 99 | uint16_t nau8822_set_noise_gate(s_noise_gate* n); 100 | uint16_t nau8822_set_plln(s_pll_n* p); 101 | uint16_t nau8822_set_pllk1(s_pll_k1* k); 102 | uint16_t nau8822_set_pllk2(s_pll_k2* k); 103 | uint16_t nau8822_set_pllk3(s_pll_k3* k); 104 | uint16_t nau8822_set_3d_depth(s_depth_3d* k); 105 | uint16_t nau8822_set_right_speaker_submixer(s_right_speaker_submixer* s); 106 | uint16_t nau8822_set_input_control(s_input_control* c); 107 | uint16_t nau8822_set_left_pga(s_left_input_pga* p); 108 | uint16_t nau8822_set_right_pga(s_right_input_pga* p); 109 | uint16_t nau8822_set_left_adc_boost(s_left_adc_boost* b); 110 | uint16_t nau8822_set_right_adc_boost(s_right_adc_boost* b); 111 | uint16_t nau8822_set_output_control(s_output_control* c); 112 | uint16_t nau8822_set_left_main_mixer(s_left_mixer* m); 113 | uint16_t nau8822_set_right_main_mixer(s_right_mixer* m); 114 | uint16_t nau8822_set_lhp_vol(s_lhp_volume* v); 115 | uint16_t nau8822_set_rhp_vol(s_rhp_volume* v); 116 | uint16_t nau8822_set_lspkout_vol(s_lspkput_volume* v); 117 | uint16_t nau8822_set_rspkout_vol(s_rspkput_volume* v); 118 | uint16_t nau8822_set_aux_2_mix(s_aux_2_mixer* m); 119 | uint16_t nau8822_set_aux_1_mix(s_aux_1_mixer* m); 120 | uint16_t nau8822_set_left_time_slot(s_left_time_slot* t); 121 | uint16_t nau8822_set_right_time_slot(s_right_time_slot* t); 122 | uint16_t nau8822_set_misc(s_misc* m); 123 | uint16_t nau8822_set_alc_enh_1(s_alc_enhancement_1* e); 124 | uint16_t nau8822_set_alc_enh_2(s_alc_enhancement_2* e); 125 | uint16_t nau8822_set_oversampling(s_sampling_192khz* s); 126 | uint16_t nau8822_set_misc_ctrl(s_misc_controls* m); 127 | uint16_t nau8822_set_tieoff_1(s_tieoff_1* c); 128 | uint16_t nau8822_set_tieoff_2(s_tieoff_2* c); 129 | uint16_t nau8822_set_tieoff_3(s_tieoff_3* c); 130 | uint16_t nau8822_set_automute(s_automute_control* m); 131 | 132 | 133 | #ifdef __cplusplus 134 | }; 135 | #endif 136 | 137 | #endif // nau8822_h__ 138 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/nau8822_code/nau8822_map_reg.h: -------------------------------------------------------------------------------- 1 | #ifndef nau8822_map_reg_h__ 2 | #define nau8822_map_reg_h__ 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | #define POWER_MANAGMENT_1 (1) 11 | #define DCBUFEN (8) 12 | #define AUX1MXEN (7) 13 | #define AUX2MXEN (6) 14 | #define PLLEN (5) 15 | #define MICBIASEN (4) 16 | #define ABIASEN (3) 17 | #define IOBUFEN (2) 18 | #define REFIMP (0) 19 | #define REFIMP_OFF (0) 20 | #define REFIMP_80k (1) 21 | #define REFIMP_300k (2) 22 | #define REFIMP_3k (3) 23 | 24 | #define POWER_MANAGMENT_2 (2) 25 | #define RHPEN (8) 26 | #define LHPEN (7) 27 | #define SLEEP (6) 28 | #define RBSTEN (5) 29 | #define LBSTEN (4) 30 | #define RPGAEN (3) 31 | #define LPGAEN (2) 32 | #define RADCEN (1) 33 | #define LADCEN (0) 34 | 35 | #define POWER_MANAGMENT_3 (3) 36 | #define AUXOUT1EN (8) 37 | #define AUXOUT2EN (7) 38 | #define LSPKEN (6) 39 | #define RSPKEN (5) 40 | #define RMIXEN (3) 41 | #define LMIXEN (2) 42 | #define RDACEN (1) 43 | #define LDACEN (0) 44 | 45 | #define AUDIO_INTERFACE (4) 46 | #define BCLKP (8) 47 | #define LRP (7) 48 | #define WLEN (5) 49 | #define WLEN_32 (3) 50 | #define WLEN_24 (2) 51 | #define WLEN_20 (1) 52 | #define WLEN_16 (0) 53 | #define AIFMT (3) 54 | #define RIGHT_JUST (0) 55 | #define LEFT_JUST (1) 56 | #define I2S_STANDARD (2) 57 | #define PCMAB (3) 58 | #define DACPHS (2) 59 | #define ADCPHS (1) 60 | #define MONO (0) 61 | 62 | #define COMPANDING (5) 63 | #define CMB8 (5) 64 | #define DACCM (3) 65 | #define COMPANDING_OFF (0) 66 | #define DAC_U_LAW_COMPANDING (2) 67 | #define DAC_A_LAW_COMPANDING (3) 68 | #define ADCCM (1) 69 | #define ADC_COMPANDING_OFF (0) 70 | #define ADC_U_LAW_COMPANDING (2) 71 | #define ADC_A_LAW_COMPANDING (3) 72 | #define ADDAP (0) 73 | 74 | #define CLOCK_CONTROL_1 (6) 75 | #define CLKM (8) 76 | #define MCLKSEL (5) 77 | #define MCK_DIV_1 (0) 78 | #define MCK_DIV_1_5 (1) 79 | #define MCK_DIV_2 (2) 80 | #define MCK_DIV_3 (3) 81 | #define MCK_DIV_4 (4) 82 | #define MCK_DIV_6 (5) 83 | #define MCK_DIV_8 (6) 84 | #define MCK_DIV_12 (7) 85 | #define BCLKSEL (2) 86 | #define BCLK_DIV_1 (0) 87 | #define BCLK_DIV_2 (1) 88 | #define BCLK_DIV_4 (2) 89 | #define BCLK_DIV_8 (3) 90 | #define BCLK_DIV_16 (4) 91 | #define BCLK_DIV_32 (5) 92 | #define CLKIOEN (0) 93 | 94 | #define CLOCK_CONTROL_2 (7) 95 | #define WSPIEN_4 (8) 96 | #define SMPLR (1) 97 | #define FILTER_SAMPLE_RATE_48KHZ (0) 98 | #define FILTER_SAMPLE_RATE_32KHZ (1) 99 | #define FILTER_SAMPLE_RATE_24KHZ (2) 100 | #define FILTER_SAMPLE_RATE_16KHZ (3) 101 | #define FILTER_SAMPLE_RATE_8KHZ (5) 102 | #define SCLKEN (0) 103 | 104 | #define NAU_GPIO (8) 105 | #define GPIO1PLL (4) 106 | #define GPIOPLL_DIV_1 (0) 107 | #define GPIOPLL_DIV_2 (1) 108 | #define GPIOPLL_DIV_3 (2) 109 | #define GPIOPLL_DIV_4 (3) 110 | #define GPIO1PL (3) 111 | #define GPIO1SEL (0) 112 | #define GPIO1_INPUT (0) 113 | #define GPIO1_TEMP_OK (2) 114 | #define GPIO1_DAC_AUTOMUTE_STATUS (3) 115 | #define GPIO1_OUT_PLL (4) 116 | #define GIPO1_PLL_LOCK_STATUS (5) 117 | #define GPIO1_SET_OUTPUT_HIGH (6) 118 | #define GPIO1_SET_OUTPUT_LOW (7) 119 | 120 | #define JACK_DETECT_1 (9) 121 | #define JCKMIDEN (7) 122 | #define JACDEN (6) 123 | #define JCKDIO (4) 124 | 125 | #define DAC_CONTROL (10) 126 | #define SOFTMT (6) 127 | #define DACOS (3) 128 | #define AUTOMT (2) 129 | #define RDACPL (1) 130 | #define LDACPL (0) 131 | 132 | #define LEFT_DAC_VOLUME (11) 133 | #define LDACVU (8) 134 | #define LDACGAIN (0) 135 | 136 | #define RIGHT_DAC_VOLUME (12) 137 | #define RDACVU (8) 138 | #define RDACGAIN (0) 139 | 140 | #define JACK_DETECT_2 (13) 141 | #define JCKDOEN1 (4) 142 | #define JCKDOEN0 (0) 143 | 144 | 145 | #define ADC_CONTROL (14) 146 | #define HPFEN (8) 147 | #define HPFAM (7) 148 | #define HPF (4) 149 | #define ADCOS (3) 150 | #define RADCPL (1) 151 | #define LADCPL (0) 152 | 153 | 154 | #define LEFT_ADC_VOLUME (15) 155 | #define LADCVU (8) 156 | #define LADCGAIN (0) 157 | 158 | #define RIGHT_ADC_VOLUME (16) 159 | #define RADCVU (8) 160 | #define RADCGAIN (0) 161 | 162 | #define EQ_1_LOW_CUTOFF (18) 163 | #define EQM (8) 164 | #define EQ1CF (5) 165 | #define EQ1GC (0) 166 | 167 | #define EQ_2_PEAK_1 (19) 168 | #define EQ2BW (8) 169 | #define EQ2CF (5) 170 | #define EQ2GC (0) 171 | 172 | #define EQ_3_PEAK_2 (20) 173 | #define EQ3BW (8) 174 | #define EQ3CF (5) 175 | #define EQ3GC (0) 176 | 177 | #define EQ_4_PEAK_3 (21) 178 | #define EQ4BW (8) 179 | #define EQ4CF (5) 180 | #define EQ4GC (0) 181 | 182 | #define EQ5_HIGH_CUTOFF (22) 183 | #define EQ5CF (5) 184 | #define EQ5GC (0) 185 | 186 | #define DAC_LIMITER_1 (24) 187 | #define DACLIMEN (8) 188 | #define DACLIMDCY (4) 189 | #define DACLIMATK (0) 190 | 191 | #define DAC_LIMITER_2 (25) 192 | #define DACLIMTHL (4) 193 | #define DACLIMBST (0) 194 | 195 | #define NOTCH_FILTER_1 (27) 196 | #define NFCU1 (8) 197 | #define NFCEN (7) 198 | #define NFCA0H (0) 199 | 200 | #define NOTCH_FILTER_2 (28) 201 | #define NFCU2 (8) 202 | #define NFCA0L (0) 203 | 204 | #define NOTCH_FILTER_3 (29) 205 | #define NFCU3 (8) 206 | #define NFCA1H (0) 207 | 208 | #define NOTCH_FILTER_4 (30) 209 | #define NFCU4 (8) 210 | #define NFCA1L (0) 211 | 212 | #define ALC_CONTROL_1 (32) 213 | #define ALCEN (7) 214 | #define ALCEN_DISABLE (0) 215 | #define ALCEN_RIGHT_EN (1) 216 | #define ALCEN_LEFT_EN (2) 217 | #define ALCEN_BOOTH_EN (3) 218 | #define ALCMXGAIN (3) 219 | #define ALCMNGAIN (0) 220 | 221 | #define ALC_CONTROL_2 (33) 222 | #define ALCHT (4) 223 | #define ALCSL (0) 224 | 225 | #define ALC_CONTROL_3 (34) 226 | #define ALCM (8) 227 | #define ALCDCY (4) 228 | #define ALCATK (0) 229 | 230 | #define NOISE_GATE (35) 231 | #define ALCNEN (3) 232 | #define ALCNTH (0) 233 | 234 | #define PLLN_N (36) 235 | #define PLLMCLK (4) 236 | #define PLLN (0) 237 | 238 | #define PLL_K_1 (37) 239 | #define PLL_K_2 (38) 240 | #define PLL_K_3 (39) 241 | 242 | #define CONTROL_3D (41) 243 | #define DEPTH_3D (0) 244 | 245 | #define RIGHT_SPEAKER_SUBMIXER (43) 246 | #define RMIXMUT (5) 247 | #define RSUBBYP (4) 248 | #define RAUXRSUBG (1) 249 | #define RAUXMUT (0) 250 | 251 | #define INPUT_CONTROL (44) 252 | #define MICBIASV (7) 253 | #define RLINRPGA (6) 254 | #define RMICNRPGA (5) 255 | #define RMICPRPGA (4) 256 | #define LLINLPGA (2) 257 | #define LMICNLPGA (1) 258 | #define LMICPLPGA (0) 259 | 260 | #define LEFT_INPUT_PGA_GAIN (45) 261 | #define LPGAU (8) 262 | #define LPGAZC (7) 263 | #define LPGAMT (6) 264 | #define LPGAGAIN (0) 265 | 266 | #define RIGHT_INPUT_PGA_GAIN (46) 267 | #define RPGAU (8) 268 | #define RPGAZC (7) 269 | #define RPGAMT (6) 270 | #define RPGAGAIN (0) 271 | 272 | #define LEFT_ADC_BOOST (47) 273 | #define LPGABST (8) 274 | #define LPGABSTGAIN (4) 275 | #define LAUXBSTGAIN (0) 276 | 277 | #define RIGHT_ADC_BOOST (48) 278 | #define RPGABST (8) 279 | #define RPGABSTGAIN (4) 280 | #define RAUXBSTGAIN (0) 281 | 282 | #define OUTPUT_CONTROL (49) 283 | #define LDACRMX (6) 284 | #define RDACLMX (5) 285 | #define AUX1BST (4) 286 | #define AUX2BST (3) 287 | #define SPKBST (2) 288 | #define TSEN (1) 289 | #define AOUTIMP (0) 290 | 291 | #define LEFT_MIXER (50) 292 | #define LAUXMXGAIN (6) 293 | #define LAUXLMX (5) 294 | #define LBYPMXGAIN (2) 295 | #define LBYPLMX (1) 296 | #define LDACLMX (0) 297 | 298 | #define RIGHT_MIXER (51) 299 | #define RAUXMXGAIN (6) 300 | #define RAUXRMX (5) 301 | #define RBYPMXGAIN (2) 302 | #define RBYPRMX (1) 303 | #define RDACRMX (0) 304 | 305 | #define LHP_VOLUME (52) 306 | #define LHPVU (8) 307 | #define LHPZC (7) 308 | #define LHPMUTE (6) 309 | #define LHPGAIN (0) 310 | 311 | #define RHP_VOLUME (53) 312 | #define RHPVU (8) 313 | #define RHPZC (7) 314 | #define RHPMUTE (6) 315 | #define RHPGAIN (0) 316 | 317 | #define LSPKOUT_VOLUME (54) 318 | #define LSPKVU (8) 319 | #define LSPKZC (7) 320 | #define LSPKMUTE (6) 321 | #define LSPKGAIN (0) 322 | 323 | #define RSPKOUT_VOLUME (55) 324 | #define RSPKVU (8) 325 | #define RSPKZC (7) 326 | #define RSPKMUTE (6) 327 | #define RSPKGAIN (0) 328 | 329 | #define AUX2MIXER (56) 330 | #define AUXOUT2MT (6) 331 | #define AUX1MIX2 (3) 332 | #define LADCAUX2 (2) 333 | #define LMIXAUX2 (1) 334 | #define LDACAUX2 (0) 335 | 336 | #define AUX1MIXER (57) 337 | #define AUXOUT1MT (6) 338 | #define AUX1HALF (5) 339 | #define LMIXAUX1 (4) 340 | #define LDACAUX1 (3) 341 | #define RADCAUX1 (2) 342 | #define RMIXAUX1 (1) 343 | #define RDACAUX1 (0) 344 | 345 | #define POWER_MANAGMENT_4 (58) 346 | #define LPDAC (8) 347 | #define LPIPBST (7) 348 | #define LPADC (6) 349 | #define LPSPKD (5) 350 | #define MICBIASM (4) 351 | #define REGVOLT (2) 352 | #define IBADJ (0) 353 | 354 | #define LEFT_TIME_SLOT (59) 355 | 356 | #define MISC (60) 357 | #define PCMTSEN (8) 358 | #define TRI (7) 359 | #define PCM8BIT (6) 360 | #define PUDEN (5) 361 | #define PUDPE (4) 362 | #define PUDPS (3) 363 | #define RTSLOT (1) 364 | #define LTSLOT (0) 365 | 366 | #define RIGHT_TIME_SLOT (61) 367 | 368 | #define DEVICE_REVISION_NUMBER (62) 369 | #define DEVICE_ID (63) 370 | 371 | #define DAC_DITHER (65) 372 | #define MOD_DITHER (4) 373 | #define ANALOG_DITHER (0) 374 | 375 | #define ALC_ENHANCEMENT_1 (70) 376 | #define ALCTBLSEL (8) 377 | #define ALCPKSEL (7) 378 | #define ALCNGSEL (6) 379 | #define ALCGAINL (0) 380 | 381 | #define ALC_ENHANCEMENT_2 (71) 382 | #define PKLIMENA (8) 383 | #define ALCGAINR (0) 384 | 385 | #define SAMPLING_192KHZ (72) 386 | #define ADCB_OVER (4) 387 | #define PLL49MOUT (2) 388 | #define DAC_OSR32x (1) 389 | #define ADC_OSR32x (0) 390 | 391 | 392 | #define MISC_CONTROLS (73) 393 | #define SPIENA_4W (8) 394 | #define FSERRVAL (6) 395 | #define FSERFLSH (5) 396 | #define FSERRENA (4) 397 | #define NOTCHDLY (3) 398 | #define DACINMUTE (2) 399 | #define PLLLOCKBP (1) 400 | #define DACOSR256 (0) 401 | 402 | #define INPUT_TIE_OFF (74) 403 | #define MANINENA (8) 404 | #define MANRAUX (7) 405 | #define MANRLIN (6) 406 | #define MANRMICN (5) 407 | #define MANRMICP (4) 408 | #define MANLAUX (3) 409 | #define MANLLIN (2) 410 | #define MANLMICN (1) 411 | #define MANLMICP (0) 412 | 413 | #define POWER_REDUCTION (75) 414 | #define IBTHALFI (8) 415 | #define IBT500UP (6) 416 | #define IBT250DN (5) 417 | #define MANINBBP (4) 418 | #define MANINPAD (3) 419 | #define MANVREFH (2) 420 | #define MANVREFM (1) 421 | #define MANVREFL (0) 422 | 423 | #define AGC_PP_READOUT (76) 424 | #define AGC_PP_DETECTOR (77) 425 | 426 | #define STATUS_READOUT (78) 427 | #define AMUTCTRL (5) 428 | #define HVDET (4) 429 | #define NSGATE (3) 430 | #define ANAMUTE (2) 431 | #define DIGMUTEL (1) 432 | #define DIGMUTER (0) 433 | 434 | #define OUTPUT_TIE_OFF (79) 435 | #define MANOUTEN (8) 436 | #define SHRTBUFH (7) 437 | #define SHRTBUFL (6) 438 | #define SHRTLSPK (5) 439 | #define SHRTRSPK (4) 440 | #define SHRTAUX1 (3) 441 | #define SHRTAUX2 (2) 442 | #define SHRTLHP (1) 443 | #define SHRTRHP (0) 444 | 445 | #define SPI1_REGISTER (87) 446 | #define SPI1_VAL (0x0115) 447 | 448 | #define SPI2_REGISTER (108) 449 | #define SPI2_VAL (0x003B) 450 | 451 | #define SPI3_REGISTER (115) 452 | #define SPI3_VAL (0x0129) 453 | 454 | 455 | #ifdef __cplusplus 456 | } 457 | #endif 458 | 459 | #endif // nau8822_map_reg_h__ 460 | -------------------------------------------------------------------------------- /nau8822/nau8822/Debug/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | ################################################################################ 4 | 5 | SHELL := cmd.exe 6 | RM := rm -rf 7 | 8 | USER_OBJS := 9 | 10 | LIBS := 11 | PROJ := 12 | 13 | O_SRCS := 14 | C_SRCS := 15 | S_SRCS := 16 | S_UPPER_SRCS := 17 | OBJ_SRCS := 18 | ASM_SRCS := 19 | PREPROCESSING_SRCS := 20 | OBJS := 21 | OBJS_AS_ARGS := 22 | C_DEPS := 23 | C_DEPS_AS_ARGS := 24 | EXECUTABLES := 25 | OUTPUT_FILE_PATH := 26 | OUTPUT_FILE_PATH_AS_ARGS := 27 | AVR_APP_PATH :=$$$AVR_APP_PATH$$$ 28 | QUOTE := " 29 | ADDITIONAL_DEPENDENCIES:= 30 | OUTPUT_FILE_DEP:= 31 | LIB_DEP:= 32 | LINKER_SCRIPT_DEP:= 33 | 34 | # Every subdirectory with source files must be described here 35 | SUBDIRS := 36 | 37 | 38 | # Add inputs and outputs from these tool invocations to the build variables 39 | C_SRCS += \ 40 | ../main.cpp \ 41 | ../src/delay.cpp \ 42 | ../src/gpio.cpp \ 43 | ../src/i2c/i2c_soft_gpio.cpp \ 44 | ../src/interfaces/i2c/i2c_soft.cpp \ 45 | ../src/interfaces/serial/serial.cpp \ 46 | ../src/nau8822_code/nau8822.c \ 47 | ../src/nau8822_code/NAU8822_hardware.cpp 48 | 49 | 50 | PREPROCESSING_SRCS += 51 | 52 | 53 | ASM_SRCS += 54 | 55 | 56 | OBJS += \ 57 | main.o \ 58 | delay.o \ 59 | gpio.o \ 60 | i2c_soft_gpio.o \ 61 | i2c_soft.o \ 62 | serial.o \ 63 | nau8822.o \ 64 | NAU8822_hardware.o 65 | 66 | OBJS_AS_ARGS += \ 67 | main.o \ 68 | delay.o \ 69 | gpio.o \ 70 | i2c_soft_gpio.o \ 71 | i2c_soft.o \ 72 | serial.o \ 73 | nau8822.o \ 74 | NAU8822_hardware.o 75 | 76 | C_DEPS += \ 77 | main.d \ 78 | delay.d \ 79 | gpio.d \ 80 | i2c_soft_gpio.d \ 81 | i2c_soft.d \ 82 | serial.d \ 83 | nau8822.d \ 84 | NAU8822_hardware.d 85 | 86 | C_DEPS_AS_ARGS += \ 87 | main.d \ 88 | delay.d \ 89 | gpio.d \ 90 | i2c_soft_gpio.d \ 91 | i2c_soft.d \ 92 | serial.d \ 93 | nau8822.d \ 94 | NAU8822_hardware.d 95 | 96 | OUTPUT_FILE_PATH +=nau8822.elf 97 | 98 | OUTPUT_FILE_PATH_AS_ARGS +=nau8822.elf 99 | 100 | ADDITIONAL_DEPENDENCIES:= 101 | 102 | OUTPUT_FILE_DEP:= ./makedep.mk 103 | 104 | LIB_DEP+= 105 | 106 | LINKER_SCRIPT_DEP+= 107 | 108 | 109 | # AVR32/GNU C Compiler 110 | ./main.o: .././main.cpp 111 | @echo Building file: $< 112 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 113 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=c++03 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 114 | @echo Finished building: $< 115 | 116 | 117 | ./delay.o: ../src/delay.cpp 118 | @echo Building file: $< 119 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 120 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=c++03 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 121 | @echo Finished building: $< 122 | 123 | 124 | ./gpio.o: ../src/gpio.cpp 125 | @echo Building file: $< 126 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 127 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=c++03 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 128 | @echo Finished building: $< 129 | 130 | 131 | ./i2c_soft_gpio.o: ../src/i2c/i2c_soft_gpio.cpp 132 | @echo Building file: $< 133 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 134 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=c++03 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 135 | @echo Finished building: $< 136 | 137 | 138 | ./i2c_soft.o: ../src/interfaces/i2c/i2c_soft.cpp 139 | @echo Building file: $< 140 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 141 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=c++03 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 142 | @echo Finished building: $< 143 | 144 | 145 | ./serial.o: ../src/interfaces/serial/serial.cpp 146 | @echo Building file: $< 147 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 148 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=c++03 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 149 | @echo Finished building: $< 150 | 151 | 152 | ./nau8822.o: ../src/nau8822_code/nau8822.c 153 | @echo Building file: $< 154 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 155 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=gnu99 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 156 | @echo Finished building: $< 157 | 158 | 159 | ./NAU8822_hardware.o: ../src/nau8822_code/NAU8822_hardware.cpp 160 | @echo Building file: $< 161 | @echo Invoking: AVR8/GNU C Compiler : 5.4.0 162 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -funsigned-char -funsigned-bitfields -DDEBUG -DNAU8822_INTERFACE_I2C -DAVR_UC -DLEVEL_HIGH_API -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\include" -I"../src" -I"../src/interfaces" -I"../src/interfaces/i2c" -I"../src/interfaces/spi" -I"../src/nau8822_code" -I"../src/interfaces/serial" -I"../src/i2c" -Os -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -Wall -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" -c -std=c++03 -v -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" 163 | @echo Finished building: $< 164 | 165 | 166 | 167 | 168 | 169 | # AVR32/GNU Preprocessing Assembler 170 | 171 | 172 | 173 | # AVR32/GNU Assembler 174 | 175 | 176 | 177 | 178 | ifneq ($(MAKECMDGOALS),clean) 179 | ifneq ($(strip $(C_DEPS)),) 180 | -include $(C_DEPS) 181 | endif 182 | endif 183 | 184 | # Add inputs and outputs from these tool invocations to the build variables 185 | 186 | # All Target 187 | all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) 188 | 189 | $(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) 190 | @echo Building target: $@ 191 | @echo Invoking: AVR8/GNU Linker : 5.4.0 192 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="nau8822.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atmega328p -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.4.351\gcc\dev\atmega328p" 193 | @echo Finished building target: $@ 194 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "nau8822.elf" "nau8822.hex" 195 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "nau8822.elf" "nau8822.eep" || exit 0 196 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "nau8822.elf" > "nau8822.lss" 197 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "nau8822.elf" "nau8822.srec" 198 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "nau8822.elf" 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | # Other Targets 207 | clean: 208 | -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) 209 | -$(RM) $(C_DEPS_AS_ARGS) 210 | rm -rf "nau8822.elf" "nau8822.a" "nau8822.hex" "nau8822.lss" "nau8822.eep" "nau8822.map" "nau8822.srec" "nau8822.usersignatures" 211 | -------------------------------------------------------------------------------- /nau8822/nau8822/src/nau8822_code/nau8822_types.h: -------------------------------------------------------------------------------- 1 | #ifndef nau8822_types_h__ 2 | #define nau8822_types_h__ 3 | 4 | #include 5 | 6 | enum e_gains{ gain_lauxin_to_lmainmix, gain_linmix_to_lmainmix, gain_lpga, gain_llin, }; 7 | 8 | enum e_left_pga_src{ e_left_pga_mic, e_left_pga_lin }; 9 | enum e_right_pga_src{ e_right_pga_mic, e_right_pga_lin }; 10 | enum e_left_in_mix_srcs{ e_lim_Left_PGA, e_lim_LeftLine, e_lim_LeftAux }; 11 | enum e_right_in_mix_srcs{ e_rim_Right_PGA, e_rim_RightLine, e_rim_RightAux }; 12 | enum e_left_main_mix_srcs{ e_lmm_LeftAux, e_lmm_LeftInputMixer, e_lmm_LeftDAC, e_lmm_RightDAC }; 13 | enum e_right_main_mix_srcs{ e_rmm_RightAux, e_rmm_RightInputMixer, e_rmm_RightDAC, e_rmm_LeftDAC }; 14 | enum e_aux_1_mix_srcs{ e_a1m_LeftMainMixer, e_a1m_RightDAC, e_a1m_LeftDAC, e_a1m_RightInputMixer }; 15 | // warning - aux2mixer is permanently connected to aux1mixer output 16 | enum e_aux_2_mix_srcs{ e_a2m_LeftInputMixer, e_a2m_LeftDAC, e_a2m_LeftMainMixer }; 17 | enum e_submix_srcs{ e_rs_RightMainMixer, e_rs_RightAux }; 18 | enum e_mic_bias_levels{ e_mbl_off, e_mbl_85, e_mbl_70, e_mbl_60, e_mbl_50 }; // Vdda x _85 = 3.3V * 0.85 = 2.805V on mic bias pin 19 | enum e_high_pass_filter{ e_hps_off, e_hps_113, e_hps_141, e_hpf_180, e_hpf_225, e_hpf_281, e_hpf_360, e_hpf_450, e_hpf_563 }; // cut-off freq for 44.1kHz operation 20 | enum e_equ_band_1{ e_eb1_80, e_eb1_105, e_eb1_135, e_eb1_175 }; 21 | enum e_equ_band_2{ e_eb2_230, e_eb2_300, e_eb2_385, e_eb2_500 }; 22 | enum e_equ_band_3{ e_eb3_650, e_eb3_850, e_eb3_1100, e_eb3_1400 }; 23 | enum e_equ_band_4{ e_eb4_1800, e_eb4_2400, e_eb4_3200, e_eb4_4100 }; 24 | enum e_equ_band_5{ e_eb5_5300, e_eb5_6900, e_eb5_9000, e_eb5_11700 }; 25 | enum e_equ_src{ e_es_ADC, e_es_DAC }; 26 | enum e_alc_channels{ e_alc_off, e_alc_left, e_alc_right, e_alc_booth }; 27 | 28 | enum e_power_blocks{e_pb_dcbufen, e_pb_aux1mxen, e_pb_aux2mxen, e_pb_pllen, e_pb_micbiasen, e_pb_abiasen, e_pb_iobufen, e_pb_refimp_off, e_pb_refimp_3k, 29 | e_pb_refimp_80k, e_pb_refimp_300k, e_pb_rhpen, e_pb_lhpen, e_pb_sleep, e_pb_rbesten, e_pb_lbesten, e_pb_rpgaen, e_pb_lpgaen, 30 | e_pb_radcen, e_pb_ladcen, e_pb_auxout1en, e_pb_auxout2en, e_pb_lspken, e_pb_rspken, e_pb_rmixen, e_pb_lmixen, e_pb_rdacen, e_pb_ldacen }; 31 | 32 | typedef struct { 33 | uint8_t dcbufen : 1; 34 | uint8_t aux1mxen : 1; 35 | uint8_t aux2mxen : 1; 36 | uint8_t pllen : 1; 37 | uint8_t micbiasen : 1; 38 | uint8_t abiasen : 1; 39 | uint8_t iobufen : 1; 40 | uint8_t refimp : 2; 41 | }s_power_1; 42 | 43 | typedef struct { 44 | uint8_t rhpen : 1; 45 | uint8_t lhpen : 1; 46 | uint8_t sleep : 1; 47 | uint8_t rbsten : 1; 48 | uint8_t lbsten : 1; 49 | uint8_t rpgaen : 1; 50 | uint8_t lpgaen : 1; 51 | uint8_t radcen : 1; 52 | uint8_t ladcen : 1; 53 | }s_power_2; 54 | 55 | typedef struct { 56 | uint8_t auxout1en : 1; 57 | uint8_t auxout2en : 1; 58 | uint8_t lspken : 1; 59 | uint8_t rspken : 1; 60 | uint8_t rmixen : 1; 61 | uint8_t lmixen : 1; 62 | uint8_t rdacen : 1; 63 | uint8_t ldacen : 1; 64 | }s_power_3; 65 | 66 | typedef struct { 67 | uint8_t bclkp : 1; 68 | uint8_t lrp : 1; 69 | uint8_t wlen : 2; 70 | uint8_t aifmt : 2; 71 | uint8_t dacphs : 1; 72 | uint8_t adcphs : 1; 73 | uint8_t mono : 1; 74 | }s_audio_interface; 75 | 76 | typedef struct { 77 | uint8_t cmb8 : 1; 78 | uint8_t daccm : 2; 79 | uint8_t adccm : 2; 80 | uint8_t addap : 1; 81 | }s_companding; 82 | 83 | typedef struct { 84 | uint8_t clkm : 1; 85 | uint8_t mclksel : 3; 86 | uint8_t bclksel : 3; 87 | uint8_t clkioen : 1; 88 | }s_clock_control_1; 89 | 90 | typedef struct { 91 | uint8_t wspien4 : 1; 92 | uint8_t smplr : 3; 93 | uint8_t sclken : 1; 94 | }s_clock_control_2; 95 | 96 | typedef struct { 97 | uint8_t gpio1pll: 2; 98 | uint8_t gpio1pl : 1; 99 | uint8_t gpio1sel: 3; 100 | }s_gpio; 101 | 102 | typedef struct { 103 | uint8_t jckmiden : 2; 104 | uint8_t jacden : 1; 105 | uint8_t jckdio : 2; 106 | }s_jack_detect_1; 107 | 108 | typedef struct { 109 | uint8_t softmt : 1; 110 | uint8_t dacos : 1; 111 | uint8_t automt : 1; 112 | uint8_t rdacpl : 1; 113 | uint8_t ldacpl : 1; 114 | }s_dac_control; 115 | 116 | typedef struct { 117 | uint8_t ldacvu : 1; 118 | uint8_t ldacgain: 8; 119 | }s_left_dac_volume; 120 | 121 | typedef struct { 122 | uint8_t rdacvu : 1; 123 | uint8_t rdacgain: 8; 124 | }s_right_dac_volume; 125 | 126 | typedef struct { 127 | uint8_t jckdoen1 : 4; 128 | uint8_t jckdoen0 : 4; 129 | }s_jack_detect_2; 130 | 131 | typedef struct { 132 | uint8_t hpfen : 1; 133 | uint8_t hpfam : 1; 134 | uint8_t hpf : 3; 135 | uint8_t adcos : 1; 136 | uint8_t radcpl : 1; 137 | uint8_t ladcpl : 1; 138 | }s_adc_control; 139 | 140 | typedef struct { 141 | uint8_t ladcvu : 1; 142 | uint8_t ladcgain: 8; 143 | }s_left_adc_volume; 144 | 145 | typedef struct { 146 | uint8_t radcvu : 1; 147 | uint8_t radcgain: 8; 148 | }s_right_adc_volume; 149 | 150 | typedef struct { 151 | uint8_t eqm : 1; 152 | uint8_t eq1cf : 2; 153 | uint8_t eq1gc : 5; 154 | }s_eq1; 155 | 156 | typedef struct { 157 | uint8_t eq2bw : 1; 158 | uint8_t eq2cf : 2; 159 | uint8_t eq2gc : 5; 160 | }s_eq2; 161 | 162 | typedef struct { 163 | uint8_t eq3bw : 1; 164 | uint8_t eq3cf : 2; 165 | uint8_t eq3gc : 5; 166 | }s_eq3; 167 | 168 | typedef struct { 169 | uint8_t eq4bw : 1; 170 | uint8_t eq4cf : 2; 171 | uint8_t eq4gc : 5; 172 | }s_eq4; 173 | 174 | typedef struct { 175 | uint8_t eq5cf : 2; 176 | uint8_t eq5gc : 5; 177 | }s_eq5; 178 | 179 | typedef struct { 180 | uint8_t daclimen : 1; 181 | uint8_t daclimdcy : 4; 182 | uint8_t daclimatk : 4; 183 | }s_dac_limiter_1; 184 | 185 | typedef struct { 186 | uint8_t daclimthl : 3; 187 | uint8_t daclimbst : 4; 188 | }s_dac_limiter_2; 189 | 190 | typedef struct { 191 | uint8_t nfcu1 : 1; 192 | uint8_t nfcen : 1; 193 | uint8_t nfca0h : 7; 194 | }s_notch_filter_1; 195 | 196 | typedef struct { 197 | uint8_t nfcu2 : 1; 198 | uint8_t nfca0l: 7; 199 | }s_notch_filter_2; 200 | 201 | typedef struct { 202 | uint8_t nfcu3 : 1; 203 | uint8_t nfca1h: 7; 204 | }s_notch_filter_3; 205 | 206 | typedef struct { 207 | uint8_t nfcu4 : 1; 208 | uint8_t nfca1l: 7; 209 | }s_notch_filter_4; 210 | 211 | typedef struct { 212 | uint8_t alcen : 2; 213 | uint8_t alcmxgain : 3; 214 | uint8_t alcmngain : 3; 215 | }s_alc_control_1; 216 | 217 | typedef struct { 218 | uint8_t alcht : 4; 219 | uint8_t alcsl : 4; 220 | }s_alc_control_2; 221 | 222 | typedef struct { 223 | uint8_t alcm : 1; 224 | uint8_t alcdcy : 4; 225 | uint8_t alcatk : 4; 226 | }s_alc_control_3; 227 | 228 | typedef struct { 229 | uint8_t alcnen : 1; 230 | uint8_t alcnth : 4; 231 | }s_noise_gate; 232 | 233 | typedef struct { 234 | uint8_t pllmclk : 1; 235 | uint8_t plln : 4; 236 | }s_pll_n; 237 | 238 | typedef struct { 239 | uint8_t pllk1 : 6; 240 | }s_pll_k1; 241 | 242 | typedef struct { 243 | uint16_t pllk2 : 9; 244 | }s_pll_k2; 245 | 246 | typedef struct { 247 | uint16_t pllk3 : 9; 248 | }s_pll_k3; 249 | 250 | typedef struct { 251 | uint8_t depth3d : 4; 252 | }s_depth_3d; 253 | 254 | typedef struct { 255 | uint8_t rmixmut : 1; 256 | uint8_t rsubbyp : 1; 257 | uint8_t rauxrsubg : 3; 258 | uint8_t rauxmut : 1; 259 | }s_right_speaker_submixer; 260 | 261 | typedef struct { 262 | uint8_t micbiasv : 2; 263 | uint8_t rlinrpga : 1; 264 | uint8_t rmicnrpga : 1; 265 | uint8_t rmicprpga : 1; 266 | uint8_t llinlpga : 1; 267 | uint8_t lmicnlpga : 1; 268 | uint8_t lmicplpga : 1; 269 | }s_input_control; 270 | 271 | typedef struct { 272 | uint8_t lpgau : 1; 273 | uint8_t lpgazc : 1; 274 | uint8_t lpgamt : 1; 275 | uint8_t lpgagain : 6; 276 | }s_left_input_pga; 277 | 278 | typedef struct { 279 | uint8_t rpgau : 1; 280 | uint8_t rpgazc : 1; 281 | uint8_t rpgamt : 1; 282 | uint8_t rpgagain : 6; 283 | }s_right_input_pga; 284 | 285 | typedef struct { 286 | uint8_t lpgabst : 1; 287 | uint8_t lpgabstgain : 3; 288 | uint8_t lauxbstgain : 3; 289 | }s_left_adc_boost; 290 | 291 | typedef struct { 292 | uint8_t rpgabst : 1; 293 | uint8_t rpgabstgain : 3; 294 | uint8_t rauxbstgain : 3; 295 | }s_right_adc_boost; 296 | 297 | typedef struct { 298 | uint8_t ldacrmx : 1; 299 | uint8_t rdaclmx : 1; 300 | uint8_t aux1bst : 1; 301 | uint8_t aux2bst : 1; 302 | uint8_t spkbst : 1; 303 | uint8_t tsen : 1; 304 | uint8_t aoutimp : 1; 305 | }s_output_control; 306 | 307 | typedef struct { 308 | uint8_t lauxmxgain : 3; 309 | uint8_t lauxlmx : 1; 310 | uint8_t lbypmxgain : 3; 311 | uint8_t lbyplmx : 1; 312 | uint8_t ldaclmx : 1; 313 | }s_left_mixer; 314 | 315 | typedef struct { 316 | uint8_t rauxmxgain : 3; 317 | uint8_t rauxrmx : 1; 318 | uint8_t rbypmxgain : 3; 319 | uint8_t rbyprmx : 1; 320 | uint8_t rdacrmx : 1; 321 | }s_right_mixer; 322 | 323 | typedef struct { 324 | uint8_t lhpvu : 1; 325 | uint8_t lhpzc : 1; 326 | uint8_t lhpmute : 1; 327 | uint8_t lhpgain : 6; 328 | }s_lhp_volume; 329 | 330 | typedef struct { 331 | uint8_t rhpvu : 1; 332 | uint8_t rhpzc : 1; 333 | uint8_t rhpmute : 1; 334 | uint8_t rhpgain : 6; 335 | }s_rhp_volume; 336 | 337 | typedef struct { 338 | uint8_t lspkvu : 1; 339 | uint8_t lspkzc : 1; 340 | uint8_t lspkmute : 1; 341 | uint8_t lspkgain : 6; 342 | }s_lspkput_volume; 343 | 344 | typedef struct { 345 | uint8_t rspkvu : 1; 346 | uint8_t rspkzc : 1; 347 | uint8_t rspkmute : 1; 348 | uint8_t rspkgain : 6; 349 | }s_rspkput_volume; 350 | 351 | typedef struct { 352 | uint8_t auxout2mt : 1; 353 | uint8_t aux1mix2 : 1; 354 | uint8_t ladcaux2 : 1; 355 | uint8_t lmixaux2 : 1; 356 | uint8_t ldacaux2 : 1; 357 | }s_aux_2_mixer; 358 | 359 | typedef struct { 360 | uint8_t auxout1mt : 1; 361 | uint8_t aux1half : 1; 362 | uint8_t lmixaux1 : 1; 363 | uint8_t ldacaux1 : 1; 364 | uint8_t radcaux1 : 1; 365 | uint8_t rmixaux1 : 1; 366 | uint8_t rdacaux1 : 1; 367 | }s_aux_1_mixer; 368 | 369 | typedef struct{ 370 | uint8_t lpdac : 1; 371 | uint8_t lpipbst : 1; 372 | uint8_t lpadc : 1; 373 | uint8_t lpspkd : 1; 374 | uint8_t micbiasm : 1; 375 | uint8_t regvolt : 2; 376 | uint8_t ibadj : 2; 377 | }s_power_4; 378 | 379 | typedef struct { 380 | uint16_t left_slot : 9; 381 | }s_left_time_slot; 382 | 383 | typedef struct { 384 | uint8_t pcmtsen : 1; 385 | uint8_t tri : 1; 386 | uint8_t pcm8bit : 1; 387 | uint8_t puden : 1; 388 | uint8_t pudpe : 1; 389 | uint8_t pudps : 1; 390 | uint8_t rtslot : 1; 391 | uint8_t ltslot : 1; 392 | }s_misc; 393 | 394 | typedef struct { 395 | uint16_t right_slot : 9; 396 | }s_right_time_slot; 397 | 398 | typedef struct { 399 | uint8_t mod_dither : 4; 400 | uint8_t analog_dither : 4; 401 | }s_dac_dither; 402 | 403 | typedef struct { 404 | uint8_t alctblsel : 1; 405 | uint8_t alcpksel : 1; 406 | uint8_t alcngsel : 1; 407 | uint8_t alcgainl : 6; // ro 408 | }s_alc_enhancement_1; 409 | 410 | typedef struct { 411 | uint8_t pklimena : 1; 412 | uint8_t alcgainr : 6; // ro 413 | }s_alc_enhancement_2; 414 | 415 | typedef struct{ 416 | uint8_t adcb_over : 1; 417 | uint8_t pll49mout : 1; 418 | uint8_t dac_osr32x : 1; 419 | uint8_t adc_osr32x : 1; 420 | }s_sampling_192khz; 421 | 422 | typedef struct { 423 | uint8_t spiena_4w : 1; 424 | uint8_t fserrval : 2; 425 | uint8_t fserflsh : 1; 426 | uint8_t fserrena : 1; 427 | uint8_t notchdly : 1; 428 | uint8_t dacinmute : 1; 429 | uint8_t plllockbp : 1; 430 | uint8_t dacosr256 : 1; 431 | }s_misc_controls; 432 | 433 | typedef struct { 434 | uint8_t maninena : 1; 435 | uint8_t manraux : 1; 436 | uint8_t manrlin : 1; 437 | uint8_t manrmicn : 1; 438 | uint8_t manrmicp : 1; 439 | uint8_t manlaux : 1; 440 | uint8_t manllin : 1; 441 | uint8_t manlmicn : 1; 442 | uint8_t manlmicp : 1; 443 | }s_tieoff_1; 444 | 445 | typedef struct { 446 | uint8_t ibthalfi : 1; 447 | uint8_t ibt500up : 1; 448 | uint8_t ibt250dn : 1; 449 | uint8_t maninbbp : 1; 450 | uint8_t maninpad : 1; 451 | uint8_t manvrefh : 1; 452 | uint8_t manvrefm : 1; 453 | uint8_t manvrefl : 1; 454 | }s_tieoff_2; 455 | 456 | typedef struct { 457 | uint8_t amutctrl : 1; 458 | uint8_t hvdet : 1; 459 | uint8_t nsgate : 1; 460 | uint8_t anamute : 1; 461 | uint8_t digmutel : 1; 462 | uint8_t digmuter : 1; 463 | }s_automute_control; 464 | 465 | typedef struct { 466 | uint8_t manouten : 1; 467 | uint8_t shrtbufh : 1; 468 | uint8_t shrtbufl : 1; 469 | uint8_t shrtlspk : 1; 470 | uint8_t shrtrspk : 1; 471 | uint8_t shrtaux1 : 1; 472 | uint8_t shrtaux2 : 1; 473 | uint8_t shrtlhp : 1; 474 | uint8_t shrtrhp : 1; 475 | }s_tieoff_3; 476 | 477 | typedef struct { 478 | uint16_t spi1 : 9; 479 | }s_spi_1; 480 | 481 | typedef struct { 482 | uint16_t spi2 : 9; 483 | }s_spi_2; 484 | 485 | typedef struct { 486 | uint16_t spi3 : 9; 487 | }s_spi_3; 488 | 489 | typedef struct { 490 | s_power_1 power_1; 491 | s_power_2 power_2; 492 | s_power_3 power_3; 493 | s_audio_interface audio_interface; 494 | s_companding companding; 495 | s_clock_control_1 clock_contorl_1; 496 | s_clock_control_2 clock_control_2; 497 | s_gpio gpio; 498 | s_jack_detect_1 jack_detect_1; 499 | s_dac_control dac_control; 500 | s_left_dac_volume left_dac_volume; 501 | s_right_dac_volume right_dac_volume; 502 | s_jack_detect_2 jack_detect_2; 503 | s_adc_control adc_control; 504 | s_left_adc_volume left_adc_volume; 505 | s_right_adc_volume right_adc_volume; 506 | s_eq1 eq1; 507 | s_eq2 eq2; 508 | s_eq3 eq3; 509 | s_eq4 eq4; 510 | s_eq5 eq5; 511 | s_dac_limiter_1 dac_limiter_1; 512 | s_dac_limiter_2 dac_limiter_2; 513 | s_notch_filter_1 notch_filter_1; 514 | s_notch_filter_2 notch_filter_2; 515 | s_notch_filter_3 notch_filter_3; 516 | s_notch_filter_4 notch_filter_4; 517 | s_alc_control_1 alc_control_1; 518 | s_alc_control_2 alc_control_2; 519 | s_alc_control_3 alc_control_3; 520 | s_noise_gate noise_gate; 521 | s_pll_n pll_n; 522 | s_pll_k1 pll_k1; 523 | s_pll_k2 pll_k2; 524 | s_pll_k3 pll_k3; 525 | s_depth_3d depth_3d; 526 | s_right_speaker_submixer right_speaker_submixer; 527 | s_input_control input_control; 528 | s_left_input_pga left_input_pga; 529 | s_right_input_pga right_input_pga; 530 | s_left_adc_boost left_adc_boost; 531 | s_right_adc_boost right_adc_boost; 532 | s_output_control output_control; 533 | s_left_mixer left_mixer; 534 | s_right_mixer right_mixer; 535 | s_lhp_volume lhp_volume; 536 | s_rhp_volume rhp_volume; 537 | s_lspkput_volume lspkput_volume; 538 | s_rspkput_volume rspkput_volume; 539 | s_aux_2_mixer aux_2_mixer; 540 | s_aux_1_mixer aux_1_mixer; 541 | s_power_4 power_4; 542 | s_left_time_slot left_time_slot; 543 | s_misc misc; 544 | s_right_time_slot right_time_slot; 545 | s_dac_dither dac_dither; 546 | s_alc_enhancement_1 alc_enhancement_1; 547 | s_alc_enhancement_2 alc_enhancement_2; 548 | s_sampling_192khz sampling_192khz; 549 | s_misc_controls misc_controls; 550 | s_tieoff_1 tie_of_1; 551 | s_tieoff_2 tie_of_2; 552 | s_automute_control automute_control; 553 | s_tieoff_3 tie_of_3; 554 | s_spi_1 spi_1; 555 | s_spi_2 spi_2; 556 | s_spi_3 spi_3; 557 | }ts_nau8822; 558 | 559 | 560 | #endif // nau8822_types_h__ 561 | -------------------------------------------------------------------------------- /nau8822 PCM spec: -------------------------------------------------------------------------------- 1 | /* 2 | * GccApplication2.cpp 3 | * uC - ATSAME70Q21A, https://uk.farnell.com/microchip/atsame70-xpld/eval-board-atsame70-32bit-mcu/dp/2508321 4 | * Created: 2020-01-16 19:36:51 5 | * Author : Szymon 6 | */ 7 | 8 | #include "conf_eth.h" 9 | #include "mini_ip.h" 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | 20 | #define BITS_BY_SLOT 16 21 | #define TOTAL_BUFFERS 2 22 | 23 | #define XDMA_SSC_TX_CH 0 24 | #define XDMA_SSC_RX_CH 1 25 | 26 | #define JEDENKODEK 1 27 | //#define DWAKODEKI 1 28 | 29 | //#define MAX_DMA_SIZE 500 30 | 31 | #define MAX_DMA_SIZE 1000 32 | 33 | 34 | uint32_t volatile xdmac_chan_0_status = 0; 35 | uint32_t volatile xdmac_chan_1_status = 0; 36 | 37 | uint8_t volatile manage_byte = 0; 38 | 39 | uint8_t volatile record = 0; 40 | 41 | uint8_t head_vol = 10; 42 | uint8_t pc_vol = 7; 43 | 44 | COMPILER_ALIGNED(8) 45 | lld_view1 linklist_write[TOTAL_BUFFERS]; 46 | lld_view1 linklist_read[TOTAL_BUFFERS]; 47 | 48 | 49 | COMPILER_ALIGNED(8) 50 | int16_t TxAudioBuffer[TOTAL_BUFFERS][MAX_DMA_SIZE * (BITS_BY_SLOT/8)]; 51 | int16_t RxAudioBuffer[TOTAL_BUFFERS][MAX_DMA_SIZE * (BITS_BY_SLOT/8)]; 52 | COMPILER_PACK_RESET(); 53 | 54 | void delay(uint32_t volatile t) 55 | { 56 | while (t--) { 57 | }; 58 | }; 59 | 60 | DTCM uint8_t gs_uc_mac_address[] = { 61 | ETHERNET_CONF_ETHADDR0, ETHERNET_CONF_ETHADDR1, ETHERNET_CONF_ETHADDR2, 62 | ETHERNET_CONF_ETHADDR3, ETHERNET_CONF_ETHADDR4, ETHERNET_CONF_ETHADDR5 63 | }; 64 | 65 | DTCM uint8_t gs_uc_ip_address[] = { 192, 168, 0, 20 }; 66 | 67 | /** The GMAC driver instance */ 68 | DTCM gmac_device_t gs_gmac_dev; 69 | 70 | /** Buffer for ethernet packets */ 71 | DTCM volatile uint8_t gs_uc_eth_buffer_a[GMAC_FRAME_LENTGH_MAX]; 72 | 73 | DTCM volatile uint8_t temp_udp_header[42]; 74 | 75 | DTCM volatile uint8_t bc = 0; 76 | 77 | DTCM volatile uint32_t del = 0x4FFFFF; 78 | 79 | DTCM uint16_t volatile ptr_a = 0; 80 | DTCM uint16_t volatile ptr_b = 0; 81 | 82 | DTCM uint8_t volatile active_read_buffer = 0; 83 | 84 | DTCM volatile uint8_t ba_lock = 0; 85 | DTCM volatile uint8_t bb_lock = 1; 86 | 87 | uint8_t volatile tx_swch = 0; 88 | uint8_t volatile rx_swch = 0; 89 | 90 | uint8_t volatile rx_ba = 0; 91 | uint8_t volatile rx_bb = 0; 92 | 93 | 94 | uint32_t volatile long_time = 0; 95 | uint8_t volatile ledstate = 0; 96 | 97 | uint16_t gmac_icmp_checksum(uint16_t* p_buff, uint32_t ul_len) 98 | { 99 | uint32_t i, ul_tmp; 100 | 101 | for (i = 0, ul_tmp = 0; i < ul_len; i++, p_buff++) { 102 | ul_tmp += SWAP16(*p_buff); 103 | }; 104 | ul_tmp = (ul_tmp & 0xffff) + (ul_tmp >> 16); 105 | 106 | return (uint16_t)(~ul_tmp); 107 | }; 108 | 109 | uint16_t gmac_ip_checksum(p_ip_header_t ph) 110 | { 111 | // how many 4B words is in ip header -> words is two times more 112 | uint16_t words = 2 * (ph->ip_hl_v & 0x0F); 113 | // don't include actual checksum of ip header 114 | ph->ip_sum = 0; 115 | // ip header is always 4 byte multiplies, use pointer to memory like uint16_t 116 | uint16_t* p_buff = (uint16_t*)ph; 117 | 118 | uint32_t i, ul_tmp = 0; 119 | 120 | for (i = 0; i < words; i++, p_buff++) { 121 | ul_tmp += SWAP16(*p_buff); 122 | }; 123 | ul_tmp = (ul_tmp & 0xffff) + (ul_tmp >> 16); 124 | ul_tmp = (ul_tmp & 0xffff) + (ul_tmp >> 16); 125 | return (uint16_t)(~ul_tmp); 126 | }; 127 | 128 | uint16_t udp_new_packet_length(uint8_t* p_uc_data, uint16_t new_payload_size) 129 | { 130 | 131 | p_ip_header_t ip_header = (p_ip_header_t)(p_uc_data + ETH_HEADER_SIZE); 132 | p_udp_header_t udp_header = (p_udp_header_t)(p_uc_data + ETH_HEADER_SIZE + ETH_IP_HEADER_SIZE); 133 | 134 | // udp frame = udp header size plus udp payload 135 | uint16_t udp_frame_size = ETH_UDP_HEADER_SIZE + new_payload_size; 136 | 137 | // total bytes for by mac = eth header + ip_total_len (ip header + udp header + udp payload) 138 | uint16_t gmac_payload = ETH_HEADER_SIZE + ETH_IP_HEADER_SIZE + udp_frame_size; 139 | 140 | // ip frame size = ip header + udp header + udp payload 141 | uint16_t ip_frame_size = udp_frame_size + ETH_IP_HEADER_SIZE; 142 | 143 | uint16_t udp_datalen = udp_frame_size - ETH_UDP_HEADER_SIZE; 144 | 145 | ip_header->ip_len = SWAP16(ip_frame_size); 146 | 147 | udp_header->length = SWAP16(udp_frame_size); 148 | 149 | uint16_t crc = gmac_ip_checksum(ip_header); 150 | ip_header->ip_sum = SWAP16(crc); 151 | 152 | return gmac_payload; 153 | }; 154 | 155 | uint8_t volatile pck_rec = 0; 156 | 157 | void gmac_process_udp_packet(uint8_t* p_uc_data, uint32_t ul_size) 158 | { 159 | UNUSED(ul_size); 160 | 161 | p_ethernet_header_t p_eth = (p_ethernet_header_t)p_uc_data; 162 | p_ip_header_t ip_header = (p_ip_header_t)(p_uc_data + ETH_HEADER_SIZE); 163 | p_udp_header_t udp_header = (p_udp_header_t)(p_uc_data + ETH_HEADER_SIZE + ETH_IP_HEADER_SIZE); 164 | uint8_t* udp_pdata = (uint8_t*)(p_uc_data + ETH_HEADER_SIZE + ETH_IP_HEADER_SIZE + ETH_UDP_HEADER_SIZE); 165 | uint16_t raw_data_payload = SWAP16(udp_header->length) - ETH_UDP_HEADER_SIZE; 166 | 167 | /* Swap the UDP port destination and source */ 168 | uint16_t rp = udp_header->scr_port; 169 | udp_header->scr_port = udp_header->dst_port; 170 | udp_header->dst_port = rp; 171 | 172 | /* Swap the IP destination address and the IP source address */ 173 | for (uint8_t i = 0; i < 4; i++) { 174 | ip_header->ip_dst[i] = ip_header->ip_src[i]; 175 | ip_header->ip_src[i] = gs_uc_ip_address[i]; 176 | }; 177 | 178 | /* Swap ethernet destination address and ethernet source address */ 179 | for (uint8_t i = 0; i < 6; i++) { 180 | /* Swap ethernet destination address and ethernet source address */ 181 | p_eth->et_dest[i] = p_eth->et_src[i]; 182 | p_eth->et_src[i] = gs_uc_mac_address[i]; 183 | }; 184 | 185 | // port numbers was swaped 186 | if(SWAP16(udp_header->scr_port) != 52001)return; 187 | 188 | while((ba_lock == 1) && (bb_lock == 1)){}; 189 | 190 | if( ba_lock == 0 ){ 191 | 192 | 193 | //#ifdef JEDENKODEK 194 | //uint16_t volatile rdo = 0; 195 | //for(uint16_t i=0; i<500; i++){ 196 | //TxAudioBuffer[0][i] = (udp_pdata[rdo + 1] << 8) | (udp_pdata[rdo]); 197 | //rdo += 2; 198 | //}; 199 | //#endif 200 | 201 | uint16_t volatile tabn = 0; 202 | uint16_t volatile udpn = 0; 203 | for(uint16_t volatile i=0; i<500; i++){ 204 | TxAudioBuffer[0][tabn + 0] = (udp_pdata[udpn + 1] << 8) | (udp_pdata[udpn + 0]); 205 | TxAudioBuffer[0][tabn + 1] = (udp_pdata[udpn + 3] << 8) | (udp_pdata[udpn + 2]); 206 | TxAudioBuffer[0][tabn + 2] = TxAudioBuffer[0][tabn + 0]; 207 | TxAudioBuffer[0][tabn + 3] = TxAudioBuffer[0][tabn + 1]; 208 | tabn += 4; 209 | udpn += 4; 210 | }; 211 | 212 | ba_lock = 1; 213 | }; 214 | 215 | if( bb_lock == 0 ){ 216 | //#ifdef JEDENKODEK 217 | //uint16_t volatile rdo = 0; 218 | //for(uint16_t i=0; i<500; i++){ 219 | //TxAudioBuffer[1][i] = (udp_pdata[rdo + 1] << 8) | (udp_pdata[rdo]); 220 | //rdo += 2; 221 | //}; 222 | //#endif 223 | 224 | uint16_t volatile tabn = 0; 225 | uint16_t volatile udpn = 0; 226 | for(uint16_t volatile i=0; i<500; i++){ 227 | TxAudioBuffer[1][tabn + 0] = (udp_pdata[udpn + 1] << 8) | (udp_pdata[udpn + 0]); 228 | TxAudioBuffer[1][tabn + 1] = (udp_pdata[udpn + 3] << 8) | (udp_pdata[udpn + 2]); 229 | TxAudioBuffer[1][tabn + 2] = TxAudioBuffer[1][tabn + 0]; 230 | TxAudioBuffer[1][tabn + 3] = TxAudioBuffer[1][tabn + 1]; 231 | tabn += 4; 232 | udpn += 4; 233 | }; 234 | 235 | bb_lock = 1; 236 | }; 237 | 238 | manage_byte = udp_pdata[1000]; 239 | 240 | if(pck_rec == 0){ 241 | //ssc_enable_tx(SSC); 242 | //xdmac_channel_enable(XDMAC, XDMA_SSC_TX_CH); 243 | pck_rec = 1; 244 | }; 245 | 246 | uint16_t gmac_payload = udp_new_packet_length(p_uc_data, 4); 247 | 248 | udp_header->crc = 0; 249 | 250 | udp_pdata[0] = xdmac_chan_0_status; 251 | udp_pdata[1] = xdmac_chan_0_status << 8; 252 | udp_pdata[2] = xdmac_chan_0_status << 16; 253 | udp_pdata[3] = manage_byte; 254 | 255 | gmac_dev_write(&gs_gmac_dev, GMAC_QUE_0, p_uc_data, gmac_payload, NULL); 256 | 257 | if(pck_rec == 1){ 258 | long_time = 0; 259 | }; 260 | }; 261 | 262 | void gmac_process_ip_packet(uint8_t* p_uc_data, uint32_t ul_size) 263 | { 264 | uint32_t i; 265 | uint32_t ul_icmp_len; 266 | int32_t ul_rc = GMAC_OK; 267 | 268 | /* avoid Cppcheck Warning */ 269 | UNUSED(ul_size); 270 | 271 | p_ethernet_header_t p_eth = (p_ethernet_header_t)p_uc_data; 272 | p_ip_header_t p_ip_header = (p_ip_header_t)(p_uc_data + ETH_HEADER_SIZE); 273 | 274 | p_icmp_echo_header_t p_icmp_echo = (p_icmp_echo_header_t)((int8_t*)p_ip_header + ETH_IP_HEADER_SIZE); 275 | 276 | switch (p_ip_header->ip_p) { 277 | case IP_PROT_UDP: { 278 | 279 | gmac_process_udp_packet(p_uc_data, ul_size); 280 | 281 | break; 282 | }; 283 | case IP_PROT_ICMP: 284 | if (p_icmp_echo->type == ICMP_ECHO_REQUEST) { 285 | p_icmp_echo->type = ICMP_ECHO_REPLY; 286 | p_icmp_echo->code = 0; 287 | p_icmp_echo->cksum = 0; 288 | 289 | /* Checksum of the ICMP message */ 290 | ul_icmp_len = (SWAP16(p_ip_header->ip_len) - ETH_IP_HEADER_SIZE); 291 | if (ul_icmp_len % 2) { 292 | *((uint8_t*)p_icmp_echo + ul_icmp_len) = 0; 293 | ul_icmp_len++; 294 | } 295 | ul_icmp_len = ul_icmp_len / sizeof(uint16_t); 296 | 297 | p_icmp_echo->cksum = SWAP16(gmac_icmp_checksum((uint16_t*)p_icmp_echo, ul_icmp_len)); 298 | /* Swap the IP destination address and the IP source address */ 299 | for (i = 0; i < 4; i++) { 300 | p_ip_header->ip_dst[i] = p_ip_header->ip_src[i]; 301 | p_ip_header->ip_src[i] = gs_uc_ip_address[i]; 302 | } 303 | /* Swap ethernet destination address and ethernet source address */ 304 | for (i = 0; i < 6; i++) { 305 | /* Swap ethernet destination address and ethernet source address */ 306 | p_eth->et_dest[i] = p_eth->et_src[i]; 307 | p_eth->et_src[i] = gs_uc_mac_address[i]; 308 | } 309 | /* Send the echo_reply */ 310 | 311 | ul_rc = gmac_dev_write(&gs_gmac_dev, GMAC_QUE_0, p_uc_data, SWAP16(p_ip_header->ip_len) + ETH_HEADER_SIZE, NULL); 312 | 313 | if (ul_rc != GMAC_OK) { 314 | printf("E: ICMP Send - 0x%x\n\r", ul_rc); 315 | } 316 | } 317 | break; 318 | 319 | default: 320 | break; 321 | } 322 | } 323 | 324 | DTCM uint8_t volatile arp_rec = 0; 325 | 326 | void gmac_process_arp_packet(uint8_t* p_uc_data, uint32_t ul_size) 327 | { 328 | uint32_t i; 329 | uint8_t ul_rc = GMAC_OK; 330 | 331 | p_ethernet_header_t p_eth = (p_ethernet_header_t)p_uc_data; 332 | p_arp_header_t p_arp = (p_arp_header_t)(p_uc_data + ETH_HEADER_SIZE); 333 | 334 | if (SWAP16(p_arp->ar_op) == ARP_REQUEST) { 335 | 336 | /* ARP reply operation */ 337 | p_arp->ar_op = SWAP16(ARP_REPLY); 338 | 339 | /* Fill the destination address and source address */ 340 | for (i = 0; i < 6; i++) { 341 | /* Swap ethernet destination address and ethernet source address */ 342 | p_eth->et_dest[i] = p_eth->et_src[i]; 343 | p_eth->et_src[i] = gs_uc_mac_address[i]; 344 | p_arp->ar_tha[i] = p_arp->ar_sha[i]; 345 | p_arp->ar_sha[i] = gs_uc_mac_address[i]; 346 | } 347 | /* Swap the source IP address and the destination IP address */ 348 | for (i = 0; i < 4; i++) { 349 | p_arp->ar_tpa[i] = p_arp->ar_spa[i]; 350 | p_arp->ar_spa[i] = gs_uc_ip_address[i]; 351 | } 352 | 353 | ul_rc = gmac_dev_write(&gs_gmac_dev, GMAC_QUE_0, p_uc_data, ul_size, NULL); 354 | if (arp_rec == 0) { 355 | arp_rec = 1; 356 | for (uint8_t i = 0; i < 3; i++) { 357 | delay(0x8FFFFF); 358 | pio_set(PIOC, PIO_PC8); 359 | delay(0x8FFFFF); 360 | pio_clear(PIOC, PIO_PC8); 361 | }; 362 | }; 363 | }; 364 | }; 365 | 366 | static void gmac_process_eth_packet(uint8_t* p_uc_data, uint32_t ul_size) 367 | { 368 | uint16_t us_pkt_format; 369 | 370 | p_ethernet_header_t p_eth = (p_ethernet_header_t)(p_uc_data); 371 | us_pkt_format = SWAP16(p_eth->et_protlen); 372 | 373 | switch (us_pkt_format) { 374 | /* ARP Packet format */ 375 | case ETH_PROT_ARP: 376 | /* Process the ARP packet */ 377 | gmac_process_arp_packet(p_uc_data, ul_size); 378 | 379 | break; 380 | 381 | /* IP protocol frame */ 382 | case ETH_PROT_IP: 383 | /* Process the IP packet */ 384 | gmac_process_ip_packet(p_uc_data, ul_size); 385 | 386 | break; 387 | 388 | default: 389 | break; 390 | }; 391 | }; 392 | 393 | void GMAC_Handler(void) 394 | { 395 | gmac_handler(&gs_gmac_dev, GMAC_QUE_0); 396 | } 397 | 398 | /** 399 | * \brief XDMAC interrupt handler. 400 | */ 401 | 402 | uint8_t volatile swch = 0; 403 | 404 | void XDMAC_Handler(void) 405 | { 406 | uint32_t volatile xdmac_gis = xdmac_get_interrupt_status(XDMAC); 407 | UNUSED(xdmac_gis); 408 | 409 | xdmac_chan_0_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_SSC_TX_CH); 410 | if( xdmac_chan_0_status == 1){ 411 | if(tx_swch == 0){ 412 | tx_swch = 1; 413 | ba_lock = 0; 414 | }else{ 415 | tx_swch = 0; 416 | bb_lock = 0; 417 | }; 418 | }; 419 | 420 | xdmac_chan_1_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_SSC_RX_CH); 421 | if( xdmac_chan_0_status == 1){ 422 | if(rx_swch == 0){ 423 | rx_swch = 1; 424 | rx_ba = 0; 425 | }else{ 426 | rx_swch = 0; 427 | rx_bb = 0; 428 | }; 429 | }; 430 | }; 431 | 432 | xdmac_channel_config_t xdmac_ssc_tx_cfg = {0}; 433 | xdmac_channel_config_t xdmac_ssc_rx_cfg = {0}; 434 | 435 | GPIO sdaa(PIOA, PIO_PA4); 436 | GPIO scla(PIOA, PIO_PA3); 437 | 438 | GPIO sclb(PIOA, PIO_PA17); 439 | GPIO sdab(PIOC, PIO_PC9); 440 | 441 | GPIO led(PIOC, PIO_PC8); 442 | 443 | class_i2c interface_kodek_a(&sdaa, &scla); 444 | 445 | class_i2c interface_kodek_b(&sdab, &sclb); 446 | 447 | class_nau8822 kodek_a(&interface_kodek_a); 448 | class_nau8822 kodek_b(&interface_kodek_b); 449 | 450 | int main(void) 451 | { 452 | /* Initialize the SAM system */ 453 | 454 | sysclk_init(); 455 | 456 | board_init(); 457 | 458 | interface_kodek_a.init(); 459 | interface_kodek_b.init(); 460 | 461 | pio_configure(PIOC, PIO_OUTPUT_0, PIO_PC8, PIO_PULLUP); 462 | 463 | pio_configure(PIOD, PIO_PERIPH_B, PIO_PD26, 0); // TD, per b 464 | pio_configure(PIOB, PIO_PERIPH_D, PIO_PB1, 0); // TK, per d 465 | pio_configure(PIOB, PIO_PERIPH_D, PIO_PB0, 0); // TF, per d 466 | pio_configure(PIOB, PIO_PERIPH_B, PIO_PB13, 0); 467 | 468 | // 12MHz output for nau8822 MCLK 469 | pmc_switch_pck_to_mainck(0, 1); 470 | pmc_enable_pck(0); 471 | 472 | pio_clear(PIOC, PIO_PC8); 473 | 474 | pmc_enable_periph_clk(ID_SSC); 475 | ssc_reset(SSC); 476 | 477 | ssc_disable_tx(SSC); 478 | ssc_disable_rx(SSC); 479 | 480 | ssc_set_clock_divider(SSC, 5769231ul, 150000000ul); 481 | 482 | clock_opt_t tx_clk_option; 483 | data_frame_opt_t tx_data_frame_option; 484 | 485 | tx_clk_option.ul_cks = SSC_TCMR_CKS_TK; 486 | tx_clk_option.ul_cko = SSC_TCMR_CKO_NONE; 487 | tx_clk_option.ul_cki = 0;//SSC_TCMR_CKI; 488 | tx_clk_option.ul_ckg = SSC_TCMR_CKG_CONTINUOUS; 489 | tx_clk_option.ul_start_sel = SSC_TCMR_START_TF_RISING; 490 | tx_clk_option.ul_sttdly = 0; 491 | tx_clk_option.ul_period = 63; 492 | 493 | tx_data_frame_option.ul_datlen = 15; 494 | tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF; 495 | tx_data_frame_option.ul_datnb = 3; 496 | tx_data_frame_option.ul_fslen_ext = 0; 497 | tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NONE; 498 | tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE; 499 | tx_data_frame_option.ul_fslen = 0; 500 | 501 | kodek_a.reset(); 502 | kodek_a.mute_all(); 503 | kodek_a.power_up(); 504 | kodek_a.mute_all(); 505 | 506 | kodek_b.reset(); 507 | kodek_b.mute_all(); 508 | kodek_b.power_up(); 509 | kodek_b.mute_all(); 510 | 511 | kodek_a.iface->write(6, 0x0145); // 0x0145 6.4MHz -> 44.1 smplr x (64b x 1) / 2 ch 512 | kodek_a.iface->write(NAU_GPIO, 0x0014); // 0x0014 513 | 514 | kodek_b.iface->write(6, 0x0140); 515 | kodek_b.iface->write(NAU_GPIO, 0x0014); // 0x0014 imclk on csb 516 | 517 | // abcdef 0x b1 3b 19 518 | // 0b 1011 0001 0011 1011 0001 1001 519 | 520 | uint16_t pllpk1 = 0x002C; 521 | uint16_t pllpk2 = 0x009D; 522 | uint16_t pllpk3 = 0x0113; 523 | 524 | kodek_a.iface->write(PLL_K_1, pllpk1); 525 | kodek_a.iface->write(PLL_K_2, pllpk2); 526 | kodek_a.iface->write(PLL_K_3, pllpk3); 527 | 528 | kodek_b.iface->write(PLL_K_1, pllpk1); 529 | kodek_b.iface->write(PLL_K_2, pllpk2); 530 | kodek_b.iface->write(PLL_K_3, pllpk3); 531 | 532 | 533 | kodek_a.passthru_adc(0); 534 | kodek_b.passthru_adc(0); 535 | 536 | // time slot MSB valid on second BCLK edge after rising edge of FS 537 | kodek_a.iface->write(MISC, (1<write(AUDIO_INTERFACE, (3 << AIFMT)); 539 | kodek_a.iface->write(LEFT_TIME_SLOT, 32); 540 | kodek_a.iface->write(RIGHT_TIME_SLOT, 48); 541 | 542 | kodek_b.iface->write(MISC, (1<write(AUDIO_INTERFACE, (0<write(LEFT_TIME_SLOT, 16); 545 | kodek_b.iface->write(RIGHT_TIME_SLOT, 0); 546 | 547 | kodek_a.eq_stream_src(eq_DAC); 548 | kodek_b.eq_stream_src(eq_DAC); 549 | 550 | kodek_a.eq_config(EQ1, EQ_80HZ, 8); // 23 551 | kodek_a.eq_config(EQ2, EQ_230HZ, 12); // 19 552 | kodek_a.eq_config(EQ3, EQ_650HZ, 12); // 12 553 | kodek_a.eq_config(EQ4, EQ_3k2HZ, 12); // 12 554 | kodek_a.eq_config(EQ5, EQ_9k0HZ, 8); // 20 555 | 556 | kodek_b.eq_config(EQ1, EQ_80HZ, 8); // 23 557 | kodek_b.eq_config(EQ2, EQ_230HZ, 12); // 19 558 | kodek_b.eq_config(EQ3, EQ_650HZ, 12); // 12 559 | kodek_b.eq_config(EQ4, EQ_3k2HZ, 12); // 12 560 | kodek_b.eq_config(EQ5, EQ_9k0HZ, 8); // 20 561 | 562 | //kodek_a.left_input_mixer_attach(im_AuxL, 7); 563 | //kodek_a.right_input_mixer_attach(im_AuxR, 7); 564 | 565 | kodek_a.left_main_mixer_attach(mm_LdacL, 222); 566 | kodek_a.right_main_mixer_attach(mm_RdacR, 222); 567 | 568 | kodek_b.left_main_mixer_attach(mm_LdacL, 222); 569 | kodek_b.right_main_mixer_attach(mm_RdacR, 222); 570 | 571 | kodek_a.left_headphone_gain(head_vol); 572 | kodek_a.right_headphone_gain(head_vol); 573 | 574 | kodek_b.left_headphone_gain(head_vol); 575 | kodek_b.right_headphone_gain(head_vol); 576 | 577 | 578 | ssc_set_transmitter(SSC, &tx_clk_option, &tx_data_frame_option); 579 | 580 | uint16_t b = 3; 581 | uint16_t c = 4; 582 | 583 | uint32_t ul_frm_size; 584 | volatile uint32_t ul_delay; 585 | gmac_options_t gmac_option; 586 | 587 | /* Enable GMAC clock */ 588 | pmc_enable_periph_clk(ID_GMAC); 589 | 590 | gmac_option.uc_copy_all_frame = 0; 591 | gmac_option.uc_no_boardcast = 0; 592 | 593 | memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); 594 | 595 | gs_gmac_dev.p_hw = GMAC; 596 | 597 | /* Init GMAC driver structure */ 598 | gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); 599 | delay(0x5FFfffF); 600 | 601 | /* Initialize DMA controller */ 602 | pmc_enable_periph_clk(ID_XDMAC); 603 | 604 | xdmac_channel_disable(XDMAC, XDMA_SSC_TX_CH); 605 | xdmac_channel_disable(XDMAC, XDMA_SSC_RX_CH); 606 | 607 | xdmac_ssc_tx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN 608 | | XDMAC_CC_MBSIZE_SINGLE 609 | | XDMAC_CC_DSYNC_MEM2PER 610 | | XDMAC_CC_CSIZE_CHK_1 611 | | XDMAC_CC_DWIDTH_HALFWORD 612 | | XDMAC_CC_SWREQ_HWR_CONNECTED 613 | | XDMAC_CC_SIF_AHB_IF0 614 | | XDMAC_CC_DIF_AHB_IF1 615 | | XDMAC_CC_SAM_INCREMENTED_AM 616 | | XDMAC_CC_DAM_FIXED_AM 617 | | XDMAC_CC_PERID(XDMAC_CHANNEL_HWID_SSC_TX); 618 | 619 | xdmac_ssc_rx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN 620 | | XDMAC_CC_MBSIZE_SINGLE 621 | | XDMAC_CC_DSYNC_PER2MEM 622 | | XDMAC_CC_CSIZE_CHK_1 623 | | XDMAC_CC_DWIDTH_HALFWORD 624 | | XDMAC_CC_SWREQ_HWR_CONNECTED 625 | | XDMAC_CC_SIF_AHB_IF0 626 | | XDMAC_CC_DIF_AHB_IF1 627 | | XDMAC_CC_SAM_FIXED_AM 628 | | XDMAC_CC_DAM_INCREMENTED_AM 629 | | XDMAC_CC_PERID(XDMAC_CHANNEL_HWID_SSC_RX); 630 | 631 | xdmac_configure_transfer(XDMAC, XDMA_SSC_TX_CH, &xdmac_ssc_tx_cfg); 632 | //xdmac_configure_transfer(XDMAC, XDMA_SSC_RX_CH, &xdmac_ssc_rx_cfg); 633 | 634 | for(uint32_t i = 0; i < TOTAL_BUFFERS; i++){ 635 | linklist_write[i].mbr_ubc = XDMAC_UBC_NVIEW_NDV1 | 636 | XDMAC_UBC_NDE_FETCH_EN | 637 | XDMAC_UBC_NSEN_UPDATED | 638 | XDMAC_UBC_NDEN_UNCHANGED | 639 | XDMAC_CUBC_UBLEN(MAX_DMA_SIZE); 640 | 641 | linklist_write[i].mbr_sa = (uint32_t)(& TxAudioBuffer[i]); 642 | linklist_write[i].mbr_da = (uint32_t)&(SSC->SSC_THR); 643 | 644 | if(i == (TOTAL_BUFFERS - 1)){ 645 | linklist_write[i].mbr_nda = ((uint32_t)&linklist_write[0]); 646 | }else{ 647 | linklist_write[i].mbr_nda = ((uint32_t)&linklist_write[i + 1]); 648 | }; 649 | }; 650 | 651 | 652 | for(uint32_t i = 0; i < TOTAL_BUFFERS; i++){ 653 | linklist_read[i].mbr_ubc = XDMAC_UBC_NVIEW_NDV1 | 654 | XDMAC_UBC_NDE_FETCH_EN | 655 | XDMAC_UBC_NSEN_UNCHANGED | 656 | XDMAC_UBC_NDEN_UPDATED | 657 | XDMAC_CUBC_UBLEN(MAX_DMA_SIZE); 658 | 659 | linklist_read[i].mbr_sa = (uint32_t)&(SSC->SSC_RHR); 660 | linklist_read[i].mbr_da = (uint32_t)(& RxAudioBuffer[i]); 661 | 662 | if( i == (TOTAL_BUFFERS - 1)){ 663 | linklist_read[i].mbr_nda = ((uint32_t)&linklist_read[0]); 664 | }else{ 665 | linklist_read[i].mbr_nda = ((uint32_t)&linklist_read[i + 1]); 666 | }; 667 | }; 668 | 669 | xdmac_channel_set_descriptor_addr(XDMAC, XDMA_SSC_TX_CH, (uint32_t)(&linklist_write[0]), 0); 670 | //xdmac_channel_set_descriptor_addr(XDMAC, XDMA_SSC_RX_CH, (uint32_t)(&linklist_read[0]), 0); 671 | 672 | 673 | xdmac_channel_set_descriptor_control(XDMAC, XDMA_SSC_TX_CH, XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED); 674 | //xdmac_channel_set_descriptor_control(XDMAC, XDMA_SSC_RX_CH, XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED); 675 | 676 | xdmac_enable_interrupt(XDMAC, XDMA_SSC_TX_CH); 677 | //xdmac_enable_interrupt(XDMAC, XDMA_SSC_RX_CH); 678 | 679 | xdmac_channel_enable_interrupt(XDMAC, XDMA_SSC_TX_CH, XDMAC_CIE_BIE | XDMAC_CIE_LIE | XDMAC_CIE_DIE | XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE); 680 | //xdmac_channel_enable_interrupt(XDMAC, XDMA_SSC_RX_CH, XDMAC_CIE_BIE | XDMAC_CIE_LIE | XDMAC_CIE_DIE | XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE); 681 | 682 | xdmac_channel_software_flush_request(XDMAC, XDMA_SSC_TX_CH); 683 | //xdmac_channel_software_flush_request(XDMAC, XDMA_SSC_RX_CH); 684 | 685 | ssc_enable_tx(SSC); 686 | xdmac_channel_enable(XDMAC, XDMA_SSC_TX_CH); 687 | 688 | irq_initialize_vectors(); 689 | 690 | irq_register_handler(XDMAC_IRQn, 1); 691 | irq_register_handler(GMAC_IRQn, 3); 692 | 693 | Enable_global_interrupt(); 694 | 695 | /* Init MAC PHY driver */ 696 | if (ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()) != GMAC_OK) { 697 | bc = 3; 698 | }; 699 | 700 | /* Auto Negotiate, work in RMII mode */ 701 | if (ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR) != GMAC_OK) { 702 | bc = 4; 703 | } 704 | 705 | /* Establish ethernet link */ 706 | while (ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1) != GMAC_OK) { 707 | bc = 5; 708 | }; 709 | 710 | /* Replace with your application code */ 711 | while (1) 712 | { 713 | if( GMAC_OK == gmac_dev_read(&gs_gmac_dev, GMAC_QUE_0, (uint8_t *) gs_uc_eth_buffer_a, sizeof(gs_uc_eth_buffer_a), &ul_frm_size) ){ 714 | if (ul_frm_size > 0) { 715 | gmac_process_eth_packet((uint8_t *) gs_uc_eth_buffer_a, ul_frm_size); 716 | }; 717 | }; 718 | 719 | if(manage_byte > 0){ 720 | switch(manage_byte){ 721 | case 1:{ 722 | head_vol += 2; 723 | if(head_vol > 63){ 724 | head_vol = 63; 725 | }; 726 | kodek_a.left_headphone_gain(head_vol); 727 | kodek_a.right_headphone_gain(head_vol); 728 | 729 | kodek_b.left_headphone_gain(head_vol); 730 | kodek_b.right_headphone_gain(head_vol); 731 | 732 | manage_byte = 0; 733 | break; 734 | }; 735 | case 2:{ 736 | if(head_vol > 2){ 737 | head_vol -= 2; 738 | }; 739 | 740 | kodek_a.left_headphone_gain(head_vol); 741 | kodek_a.right_headphone_gain(head_vol); 742 | 743 | kodek_b.left_headphone_gain(head_vol); 744 | kodek_b.right_headphone_gain(head_vol); 745 | 746 | manage_byte = 0; 747 | break; 748 | }; 749 | 750 | 751 | case 4:{ 752 | pc_vol += 1; 753 | if(pc_vol > 7){ 754 | pc_vol = 7; 755 | }; 756 | 757 | pllpk3++; 758 | kodek_a.iface->write(PLL_K_3, pllpk3); 759 | 760 | //kodek_a.left_main_mixer_attach(mm_AuxL, pc_vol); 761 | //kodek_a.right_main_mixer_attach(mm_AuxR, pc_vol); 762 | 763 | //kodek_b.left_main_mixer_attach(mm_AuxL, pc_vol); 764 | //kodek_b.right_main_mixer_attach(mm_AuxR, pc_vol); 765 | 766 | manage_byte = 0; 767 | break; 768 | }; 769 | 770 | case 5:{ 771 | if(pc_vol > 2){ 772 | pc_vol -= 1; 773 | }; 774 | 775 | pllpk3--; 776 | kodek_a.iface->write(PLL_K_3, pllpk3); 777 | 778 | //kodek_a.left_main_mixer_attach(mm_AuxL, pc_vol); 779 | //kodek_a.right_main_mixer_attach(mm_AuxR, pc_vol); 780 | 781 | //kodek_b.left_main_mixer_attach(mm_AuxL, pc_vol); 782 | //kodek_b.right_main_mixer_attach(mm_AuxR, pc_vol); 783 | 784 | manage_byte = 0; 785 | break; 786 | }; 787 | 788 | 789 | case 3:{ 790 | pck_rec = 0; 791 | ssc_disable_tx(SSC); 792 | xdmac_channel_enable(XDMAC, 0); 793 | ba_lock = 0; 794 | bb_lock = 0; 795 | manage_byte = 0; 796 | break; 797 | }; 798 | default:break; 799 | }; 800 | 801 | }; 802 | 803 | }; 804 | }; 805 | --------------------------------------------------------------------------------