├── +adi ├── +AD9144 │ ├── Base.m │ └── Tx.m ├── +AD9361 │ ├── Base.m │ ├── Rx.m │ ├── TuneAGC.m │ └── Tx.m ├── +AD9363 │ ├── Rx.m │ └── Tx.m ├── +AD9364 │ ├── Rx.m │ └── Tx.m ├── +AD9371 │ ├── Base.m │ ├── ORx.m │ ├── Rx.m │ └── Tx.m ├── +AD9680 │ ├── Base.m │ └── Rx.m ├── +ADRV9009 │ ├── Base.m │ ├── Rx.m │ └── Tx.m ├── +ADRV9361Z7035 │ ├── Rx.m │ └── Tx.m ├── +ADRV9364Z7020 │ ├── Rx.m │ └── Tx.m ├── +ADRV9371 │ ├── Rx.m │ └── Tx.m ├── +DAQ2 │ ├── Rx.m │ └── Tx.m ├── +FMComms2 │ ├── Rx.m │ └── Tx.m ├── +FMComms3 │ ├── Rx.m │ └── Tx.m ├── +FMComms4 │ ├── Rx.m │ └── Tx.m ├── +PackRF │ ├── Rx.m │ └── Tx.m ├── +Pluto │ ├── Rx.m │ └── Tx.m ├── +common │ ├── Attribute.m │ ├── DDS.m │ ├── DebugAttribute.m │ ├── RegisterReadWrite.m │ ├── Rx.m │ ├── RxTx.m │ └── Tx.m ├── +utils │ ├── ADIWorkFlow.m │ ├── ConnectHardware.m │ ├── Downloader.m │ ├── InstallDriverBase.m │ ├── InstallDriverLinux.m │ ├── Step1.m │ ├── Step2.m │ ├── Step3.m │ ├── StepBase.m │ └── libad9361.m ├── Contents.m └── Version.m ├── .gitignore ├── .gitlab-ci.yml ├── CI ├── doc │ ├── ADI_Logo_AWP_Large.png │ ├── Examples.mlx │ ├── Support.mlx │ ├── SupportedHardware.mlx │ ├── SystemObjects.mlx │ ├── adi_bsp.mlx │ ├── genhtml.m │ └── parts │ │ └── adi.ad9361.rx.mlx ├── ip │ └── analog.com_user_util_mux_1.0.zip ├── projects │ ├── adrv9009 │ │ ├── Makefile │ │ ├── common │ │ │ ├── adrv9009_bd.tcl │ │ │ └── config_rxtx.tcl │ │ └── zcu102 │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ ├── u-boot-zcu.elf │ │ │ ├── uEnv.txt │ │ │ └── zynqmp.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project.tcl │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ ├── adrv9361z7035 │ │ ├── ccbob_cmos │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rx.tcl │ │ │ ├── config_rx_tx.tcl │ │ │ ├── config_tx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ ├── system_project_tx.tcl │ │ │ └── system_top.v │ │ ├── ccbob_lvds │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rx.tcl │ │ │ ├── config_rx_tx.tcl │ │ │ ├── config_tx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ ├── system_project_tx.tcl │ │ │ └── system_top.v │ │ ├── ccbox_lvds │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rx.tcl │ │ │ ├── config_rx_tx.tcl │ │ │ ├── config_tx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ ├── system_project_tx.tcl │ │ │ └── system_top.v │ │ ├── ccbox_lvds_modem │ │ │ ├── boot │ │ │ │ ├── devicetree.dtb │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ ├── uImage │ │ │ │ └── zynq.bif │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ └── system_top.v │ │ ├── ccfmc_lvds │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rx.tcl │ │ │ ├── config_rx_tx.tcl │ │ │ ├── config_tx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ ├── system_project_tx.tcl │ │ │ └── system_top.v │ │ └── common │ │ │ ├── adrv9361z7035_bd.tcl │ │ │ ├── adrv9361z7035_constr.xdc │ │ │ ├── adrv9361z7035_constr_cmos.xdc │ │ │ ├── adrv9361z7035_constr_lvds.xdc │ │ │ ├── ccbob_bd.tcl │ │ │ ├── ccbob_constr.xdc │ │ │ ├── ccbox_bd.tcl │ │ │ ├── ccbox_constr.xdc │ │ │ ├── ccfmc_bd.tcl │ │ │ ├── ccfmc_constr.xdc │ │ │ ├── ccpci_bd.tcl │ │ │ ├── ccpci_constr.xdc │ │ │ ├── ccusb_bd.tcl │ │ │ ├── ccusb_constr.xdc │ │ │ ├── config_rx.tcl │ │ │ └── config_tx.tcl │ ├── adrv9364z7020 │ │ ├── ccbob_cmos │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rx.tcl │ │ │ ├── config_rx_tx.tcl │ │ │ ├── config_tx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ ├── system_project_tx.tcl │ │ │ └── system_top.v │ │ ├── ccbob_lvds │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rx.tcl │ │ │ ├── config_rx_tx.tcl │ │ │ ├── config_tx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ ├── system_project_tx.tcl │ │ │ └── system_top.v │ │ ├── ccbox_lvds │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rx.tcl │ │ │ ├── config_rx_tx.tcl │ │ │ ├── config_tx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_project_rx.tcl │ │ │ ├── system_project_rx_tx.tcl │ │ │ ├── system_project_tx.tcl │ │ │ └── system_top.v │ │ └── common │ │ │ ├── adrv9364z7020_bd.tcl │ │ │ ├── adrv9364z7020_constr.xdc │ │ │ ├── adrv9364z7020_constr_cmos.xdc │ │ │ ├── adrv9364z7020_constr_lvds.xdc │ │ │ ├── ccbob_bd.tcl │ │ │ ├── ccbob_constr.xdc │ │ │ ├── ccbox_bd.tcl │ │ │ ├── ccbox_constr.xdc │ │ │ ├── ccusb_bd.tcl │ │ │ ├── ccusb_constr.xdc │ │ │ ├── config_rx.tcl │ │ │ └── config_tx.tcl │ ├── adrv9371x │ │ ├── Makefile │ │ ├── common │ │ │ ├── adrv9371x_bd.tcl │ │ │ └── config_rxtx.tcl │ │ ├── zc706 │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project.tcl │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ │ └── zcu102 │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ ├── u-boot-zcu.elf │ │ │ ├── uEnv.txt │ │ │ └── zynqmp.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project.tcl │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ ├── common │ │ ├── boot │ │ │ ├── bl31.elf │ │ │ ├── zynq.bif │ │ │ └── zynqmp.bif │ │ ├── xilinx │ │ │ ├── adcfifo_bd.tcl │ │ │ └── dacfifo_bd.tcl │ │ ├── zc702 │ │ │ ├── zc702_system_bd.tcl │ │ │ └── zc702_system_constr.xdc │ │ ├── zc706 │ │ │ ├── zc706_plddr3_adcfifo_bd.tcl │ │ │ ├── zc706_plddr3_constr.xdc │ │ │ ├── zc706_plddr3_dacfifo_bd.tcl │ │ │ ├── zc706_plddr3_mig.mk │ │ │ ├── zc706_plddr3_mig.prj │ │ │ ├── zc706_system_bd.tcl │ │ │ └── zc706_system_constr.xdc │ │ ├── zcu102 │ │ │ ├── zcu102_system_bd.tcl │ │ │ └── zcu102_system_constr.xdc │ │ └── zed │ │ │ ├── zed_system_bd.tcl │ │ │ └── zed_system_constr.xdc │ ├── fmcomms2 │ │ ├── common │ │ │ ├── config_rxtx.tcl │ │ │ ├── fmcomms2_bd.tcl │ │ │ ├── prcfg.v │ │ │ ├── prcfg.xdc │ │ │ ├── prcfg_bb.v │ │ │ └── prcfg_bd.tcl │ │ ├── zc702 │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ │ ├── zc706 │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ │ └── zed │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ ├── u-boot.elf │ │ │ ├── uEnv.txt │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ ├── fmcomms5 │ │ ├── common │ │ │ ├── config_rxtx.tcl │ │ │ └── fmcomms5_bd.tcl │ │ ├── zc702 │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ │ ├── u-boot.elf │ │ │ │ ├── uEnv.txt │ │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ │ └── zc706 │ │ │ ├── Makefile │ │ │ ├── boot │ │ │ ├── u-boot.elf │ │ │ ├── uEnv.txt │ │ │ └── zynq.bif │ │ │ ├── config_prj.tcl │ │ │ ├── config_rxtx.tcl │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project_rxtx.tcl │ │ │ └── system_top.v │ ├── pluto │ │ ├── Makefile │ │ ├── config_prj.tcl │ │ ├── config_rxtx.tcl │ │ ├── config_rxtx_board.tcl │ │ ├── pluto_fpga.tcl │ │ ├── system_bd.tcl │ │ ├── system_constr.xdc │ │ ├── system_project.tcl │ │ ├── system_project_rxtx.tcl │ │ └── system_top.v │ └── scripts │ │ ├── adi_board.tcl │ │ ├── adi_prcfg_project.tcl │ │ ├── adi_tquest.tcl │ │ ├── fixmake.sh │ │ ├── fsbl_build.tcl │ │ ├── fsbl_build_zynq.tcl │ │ ├── fsbl_build_zynqmp.tcl │ │ └── pmufw_zynqmp.tcl └── scripts │ ├── Docker │ ├── Makefile │ ├── adi_build.tcl │ ├── adi_ip.tcl │ ├── adi_project.tcl │ ├── bsp.tmpl │ ├── bsp_noexamples.tmpl │ ├── build_bsp.m │ ├── build_bsp.sh │ ├── copy_all_packed_ips.tcl │ ├── dockermake │ ├── genTlbx.m │ ├── linter.m │ ├── pack_all_ips.tcl │ ├── setupDocker.sh │ ├── synth_designs.sh │ └── targeting_designs.sh ├── LICENSE ├── README.md ├── blocks └── ADIBlocks.slx ├── doc ├── Examples.html ├── Support.html ├── SupportedHardware.html ├── SystemObjects.html ├── adi_bsp.html ├── adi_logo.png └── helptoc.xml ├── hdl_wa_bsp ├── common │ ├── +hdlbsp │ │ ├── +util │ │ │ ├── +SDUpdater │ │ │ │ ├── DeviceTypes.m │ │ │ │ ├── FWModes.m │ │ │ │ └── SDUpdater.m │ │ │ ├── SDUpdater.m │ │ │ └── vendorInstall.m │ │ ├── install.m │ │ └── uninstall.m │ └── Contents.m └── vendor │ └── AnalogDevices │ ├── +AnalogDevices │ ├── +adrv9009 │ │ ├── +common │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ │ └── +zcu102 │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ ├── +adrv9361z7035 │ │ ├── +ccbob_cmos │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ ├── +ccbob_lvds │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ ├── +ccbox_lvds │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ ├── +ccfmc_lvds │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ └── +common │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ ├── +adrv9364z7020 │ │ ├── +ccbob_cmos │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ ├── +ccbob_lvds │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ ├── +ccbox_lvds │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ └── +common │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ ├── +adrv9371x │ │ ├── +common │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ │ ├── +zc706 │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ └── +zcu102 │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ ├── +fmcomms2 │ │ ├── +common │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ │ ├── +zc702 │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ ├── +zc706 │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ └── +zed │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ ├── +fmcomms5 │ │ ├── +common │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ │ ├── +zc702 │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ │ └── +zc706 │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ ├── plugin_rd_rx.m │ │ │ ├── plugin_rd_rxtx.m │ │ │ └── plugin_rd_tx.m │ ├── +pluto │ │ ├── add_io.m │ │ ├── hdlcoder_ref_design_customization.m │ │ ├── plugin_board.m │ │ ├── plugin_rd.m │ │ ├── plugin_rd_rx.m │ │ ├── plugin_rd_rxtx.m │ │ └── plugin_rd_tx.m │ ├── +util │ │ ├── ADIZynqSDRAttributeInfo.xml │ │ ├── ADIZynqSDRParameterInfo.xml │ │ ├── adizynqsdr.xml │ │ └── extmodeHooksADI.m │ ├── install.m │ └── uninstall.m │ ├── Contents.m │ └── hdlcoder_board_customization.m ├── hil_models ├── ad936x │ └── ad9361.m ├── ad9371 │ ├── ad9371.m │ ├── ad9371_mimo.m │ └── profile_TxBW100_ORxBW100_RxBW100.txt ├── adrv9009 │ ├── Tx_BW200_IR245p76_Rx_BW200_OR245p76_ORx_BW200_OR245p76_ADRV9009.txt │ └── adrv9009.m ├── daq2 │ └── daq2.m └── legacy │ ├── ADSB_MATLAB │ ├── AltVelCalc.m │ ├── ConvertFracDeg.m │ ├── LICENSE │ ├── LatLongCalcSingleADI.m │ ├── ModeS_BitDecode4.m │ ├── ModeS_DataSearch4.m │ ├── ModeS_ReadMsg4.m │ ├── ModeS_Receiver.m │ ├── ad9361.cfg │ ├── ad9361_ModeS.m │ └── newModeS.mat │ ├── ADSB_Simulink │ ├── AltVelCalc.m │ ├── ConvertFracDeg.m │ ├── DecodeBits.m │ ├── LatLongCalcSingle.m │ ├── ModeS_FixPt_Pipelined_ADI.slx │ ├── ModeS_Simulink_Decode.mdl │ └── data_Yb.mat │ ├── ADSB_Simulink_libiio │ ├── AltVelCalc.m │ ├── ConvertFracDeg.m │ ├── DecodeBits.m │ ├── LatLongCalcSingle.m │ ├── ModeS_Simulink_libiio.slx │ ├── ad9361.cfg │ └── data_Yb.mat │ ├── ADSB_transmitter │ ├── adsbTxGen.m │ └── txData.mat │ ├── LTE_MATLAB │ ├── LTE10_MHz.ftr │ ├── LTE1p4_MHz.ftr │ ├── LTE3_MHz.ftr │ ├── LTE5_MHz.ftr │ ├── LTEReceiver.m │ ├── PDSCHEVM.m │ ├── ad9361.cfg │ ├── ad9361_LTE.m │ ├── ad9361_LTE_2ch.m │ └── demo.m │ ├── adrv9009 │ ├── adrv9009.cfg │ └── adrv9009_matlab.m │ ├── adrv9371 │ ├── ad9371.cfg │ └── ad9371_matlab.m │ ├── daq2_data_stream │ ├── daq2.cfg │ └── daq2_sim.slx │ ├── fmcomms2_3_data_stream │ ├── ad9361.cfg │ ├── ad9361_matlab.m │ └── ad9361_sim.slx │ ├── fmcomms4_data_stream │ ├── ad9364.cfg │ └── ad9364_sim.slx │ ├── fmcomms5_data_stream │ ├── ad9361-1.cfg │ ├── ad9361-2.cfg │ └── fmcomms5.slx │ ├── ieee80211_beacon_rx │ ├── ad9361.cfg │ ├── wlan80211BeaconRx.slx │ ├── wlan80211BeaconRxInit.m │ └── wlan80211BeaconRxModelParams.m │ └── qpsktxrx │ ├── ad9361.cfg │ ├── qpsktxrx.slx │ ├── sdrqpskrx.mat │ └── sdrqpsktx.mat ├── info.xml ├── targeting_models ├── ADSB │ ├── AltVelCalc_ADI.m │ ├── DecodeBitsTest.m │ ├── DecodeBits_ADI.m │ ├── DecodeBits_ADI.prj │ ├── LICENSE │ ├── LatLongCalcSingle_ADI.m │ ├── ModeS_ADI_Codegen.slx │ ├── data_Yb.mat │ ├── data_noise.mat │ └── linux_app │ │ ├── DecodeBits_ADI.c │ │ ├── DecodeBits_ADI.h │ │ ├── DecodeBits_ADI_initialize.c │ │ ├── DecodeBits_ADI_initialize.h │ │ ├── DecodeBits_ADI_terminate.c │ │ ├── DecodeBits_ADI_terminate.h │ │ ├── DecodeBits_ADI_types.h │ │ ├── LatLongCalcSingle_ADI.c │ │ ├── LatLongCalcSingle_ADI.h │ │ ├── Makefile │ │ ├── adsb_decode │ │ ├── adsb_decode.c │ │ ├── mrdivide.c │ │ ├── mrdivide.h │ │ └── rtwtypes.h ├── frequency-hopping │ ├── +AnalogDevicesDemo │ │ └── +adrv9361z7035 │ │ │ ├── +ccfmc_lvds_hop │ │ │ └── +rxtx │ │ │ │ ├── add_rx_tx_io.m │ │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ │ ├── plugin_board.m │ │ │ │ └── plugin_rd.m │ │ │ └── +common │ │ │ ├── add_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ ├── FrequencyHopper.m │ ├── adi_build.tcl │ ├── build_kernel.sh │ ├── ccfmc_lvds_hop │ │ ├── boot │ │ │ ├── u-boot.elf │ │ │ ├── uEnv.txt │ │ │ └── zynq.bif │ │ ├── config_prj.tcl │ │ ├── config_rx.tcl │ │ ├── config_rx_tx.tcl │ │ ├── config_tx.tcl │ │ ├── system_bd.tcl │ │ ├── system_project_rx.tcl │ │ ├── system_project_rx_tx.tcl │ │ ├── system_project_tx.tcl │ │ └── system_top.v │ ├── devicetree.dtb │ ├── fastlock.m │ ├── frequency_hopping.slx │ ├── hdlcoder_board_customization.m │ ├── hdlworkflow.m │ ├── hop_result.bmp │ └── hopper.patch ├── modem-qpsk │ ├── ADI_logo.svg │ ├── FixedPoint │ │ ├── PlutoCaptureQPSK.bb │ │ ├── Receiver.slx │ │ ├── RxTxFixedPointLibrary.slx │ │ ├── RxTxFixedPointLibrary_noscopes.slx │ │ ├── Transmitter.slx │ │ ├── demos │ │ │ ├── ADI_DMA_TT │ │ │ │ ├── BOOT.BIN │ │ │ │ ├── adi_build.tcl │ │ │ │ ├── combinedTxRx_ADIDMA.slx │ │ │ │ └── hdlworkflow.m │ │ │ ├── ADI_logo.svg │ │ │ ├── External_Mode │ │ │ │ ├── Interface_Model.slx │ │ │ │ ├── combinedTxRx_ExternalMode.slx │ │ │ │ ├── gm_combinedTxRx_ExternalMode_lib.slx │ │ │ │ └── hdlworkflow.m │ │ │ ├── FPGA_Capture │ │ │ │ ├── FPGADataCapture.m │ │ │ │ ├── FPGADataCapture_model.slx │ │ │ │ ├── Receiver_FPGACap.slx │ │ │ │ ├── Receiver_FPGACapture.slx │ │ │ │ ├── hdlworkflow.m │ │ │ │ ├── support │ │ │ │ │ ├── aximm_runtime.m │ │ │ │ │ ├── generateBadFrame.m │ │ │ │ │ └── sendToBoard.m │ │ │ │ └── testBitErrorCheck.m │ │ │ └── Standard_IQ │ │ │ │ ├── Interface_Model_Tx.slx │ │ │ │ ├── Interface_Rx.m │ │ │ │ ├── combinedTxRx_StandardIQ.slx │ │ │ │ └── hdlworkflow.m │ │ ├── modelSettings.m │ │ └── modem_20MHz.ftr │ ├── FloatingPoint │ │ ├── EndToEndTest.m │ │ ├── IQ_baseline.bb │ │ ├── IQ_freqOffset500Hz.bb │ │ ├── RadioReceiver.slx │ │ ├── RxFloatingPointLibrary.slx │ │ ├── modelSettingsFloat.m │ │ └── private │ │ │ ├── FindFrameStart.m │ │ │ ├── PacketDetector.m │ │ │ ├── QPSKDemoChannel.m │ │ │ ├── convertPhaseToFrequency.m │ │ │ └── dfe_frac.m │ ├── LICENSE │ ├── README.md │ ├── precommit.m │ ├── startup_adi_qpsk.m │ ├── test │ │ ├── PlutoCaptureQPSK.bb │ │ ├── ReceiverFloatingPoint.m │ │ ├── ReceiverModelTests.m │ │ ├── Receiver_UnderTest_Fixed.slx │ │ ├── Receiver_UnderTest_Float.slx │ │ ├── generateFrame.m │ │ ├── hdl │ │ │ ├── HDLModelTests.m │ │ │ └── checkTimingReport.m │ │ ├── hdl_design │ │ │ ├── combinedTxRx.slx │ │ │ ├── hdlworkflow_combinedTxRx.m │ │ │ └── hdlworkflow_hwi.m │ │ ├── hdl_tests.m │ │ ├── linux │ │ │ ├── Makefile │ │ │ ├── mac.c │ │ │ ├── mac.h │ │ │ ├── modem_filter.ftr │ │ │ ├── modemd.c │ │ │ ├── reg.c │ │ │ ├── reg.h │ │ │ └── test_dma.c │ │ ├── matlab_tests.m │ │ ├── simulink_tests.m │ │ ├── testRunner.m │ │ └── utilmodels │ │ │ ├── rx.slx │ │ │ └── tx.slx │ └── utils │ │ ├── disableDebugBlocks.m │ │ ├── getFigurePositions.m │ │ ├── setupHDL.m │ │ ├── ssh.m │ │ ├── tileScopes.m │ │ └── toggleDebugBlocks.m └── tuneAGC-ad9361 │ ├── +AnalogDevicesAGCDemo │ └── +adrv9361z7035 │ │ ├── +ccfmc_lvds_agc │ │ └── +rx │ │ │ ├── add_rx_io.m │ │ │ ├── hdlcoder_ref_design_customization.m │ │ │ ├── plugin_board.m │ │ │ └── plugin_rd.m │ │ └── +common │ │ ├── hdlcoder_ref_design_customization.m │ │ ├── plugin_board.m │ │ └── plugin_rd.m │ ├── AD9361TRx.m │ ├── ModeS_testbench.slx │ ├── ad9361_rx_wlan_testbench.slx │ ├── ad9361_rx_wlan_testbench_targeting.slx │ ├── adi_ad9361_models.slx │ ├── captures │ ├── IQData_m20.bb │ ├── IQData_m25.bb │ ├── IQData_m30.bb │ ├── IQData_m40.bb │ ├── IQData_m50.bb │ ├── IQData_m60.bb │ └── IQData_m70.bb │ ├── ccfmc_lvds_agc │ ├── boot │ │ ├── u-boot.elf │ │ ├── uEnv.txt │ │ └── zynq.bif │ ├── config_prj.tcl │ ├── config_rx.tcl │ ├── config_rx_tx.tcl │ ├── config_tx.tcl │ ├── system_bd.tcl │ ├── system_project_rx.tcl │ ├── system_project_rx_tx.tcl │ ├── system_project_tx.tcl │ └── system_top.v │ ├── demod80211aTestWaveform.m │ ├── gen80211aTestWaveform.m │ ├── hdlcoder_board_customization.m │ ├── hdlworkflow.m │ ├── reg │ ├── Makefile │ ├── agc_ctrl.sh │ ├── devicetree.dts │ ├── reg.c │ └── reg.h │ ├── run_testbench.m │ ├── support │ ├── CollectBeacons.m │ ├── genBeacon.m │ ├── lltf.mat │ ├── nonHTBeaconRxMPDUDecode.m │ └── offline.m │ ├── tuneAD9361AGC.m │ └── tuneAGCad9361Tests.m └── test ├── AD9361Tests.m ├── AD9363Tests.m ├── AD9364Tests.m ├── AD9371Tests.m ├── ADRV9009Tests.m ├── BSPInstallerTests.m ├── BSPTests.m ├── BSPTestsBase.m ├── DAQ2Tests.m ├── DemoTests.m ├── HardwareTests.m ├── ModemTests.m ├── SysObjsTests.m ├── Tx_BW100_IR122p88_Rx_BW100_OR122p88_ORx_BW100_OR122p88_DC122p88.txt ├── Tx_BW200_IR245p76_Rx_BW100_OR122p88_ORx_BW200_OR245p76_ADRV9009.txt ├── Tx_BW200_IR245p76_Rx_BW200_OR245p76_ORx_BW200_OR245p76_ADRV9009.txt ├── Tx_BW200_IR245p76_Rx_BW200_OR245p76_ORx_BW200_OR245p76_DC245p76.txt ├── Tx_BW400_IR491p52_Rx_BW200_OR245p76_ORx_BW400_OR491p52_DC245p76.txt ├── board_variants.m ├── build_design.m ├── customAD9361filter.ftr ├── graphicalInstaller.m ├── perf ├── HardwarePerformanceTests.m ├── LTETests.m └── hwTestRunner.m ├── profile_TxBW100_ORxBW100_RxBW100.txt ├── profile_TxBW50_ORxBW50_RxBW50.txt ├── runDemoTests.m ├── runHWTests.m ├── runInstallerTests.m ├── runSynthTests.m ├── runTests.m ├── setportmapping.m ├── testModel.slx ├── testModel_Rx16Tx32.slx └── testModel_Tx32.slx /+adi/+AD9363/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9361.Rx 2 | % adi.AD9363.Rx Receive data from the AD9363 transceiver 3 | % The adi.AD9363.Rx System object is a signal source that can receive 4 | % complex data from the AD9364. 5 | % 6 | % rx = adi.AD9363.Rx; 7 | % rx = adi.AD9363.Rx('uri','192.168.2.1'); 8 | % 9 | % AD9363 Datasheet 10 | % 11 | % See also adi.Pluto.Rx 12 | 13 | methods 14 | %% Constructor 15 | function obj = Rx(varargin) 16 | % Returns the matlabshared.libiio.base object 17 | coder.allowpcode('plain'); 18 | obj = obj@adi.AD9361.Rx(varargin{:}); 19 | end 20 | end 21 | 22 | end 23 | 24 | -------------------------------------------------------------------------------- /+adi/+AD9363/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9361.Tx 2 | % adi.AD9363.Tx Transmit data from the AD9364 transceiver 3 | % The adi.AD9363.Tx System object is a signal sink that can 4 | % transmit complex data from the AD9364. 5 | % 6 | % tx = adi.AD9363.Tx; 7 | % tx = adi.AD9363.Tx('uri','192.168.2.1'); 8 | % 9 | % AD9363 Datasheet 10 | % 11 | % See also adi.Pluto.Tx 12 | 13 | methods 14 | %% Constructor 15 | function obj = Tx(varargin) 16 | % Returns the matlabshared.libiio.base object 17 | coder.allowpcode('plain'); 18 | obj = obj@adi.AD9361.Tx(varargin{:}); 19 | end 20 | end 21 | 22 | end 23 | 24 | -------------------------------------------------------------------------------- /+adi/+AD9364/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9361.Rx 2 | % adi.AD9364.Rx Receive data from the AD9364 transceiver 3 | % The adi.AD9361.Rx System object is a signal source that can receive 4 | % complex data from the AD9364. 5 | % 6 | % rx = adi.AD9364.Rx; 7 | % rx = adi.AD9364.Rx('uri','192.168.2.1'); 8 | % 9 | % AD9364 Datasheet 10 | % 11 | % See also adi.FMComms4.Rx 12 | 13 | methods 14 | %% Constructor 15 | function obj = Rx(varargin) 16 | % Returns the matlabshared.libiio.base object 17 | coder.allowpcode('plain'); 18 | obj = obj@adi.AD9361.Rx(varargin{:}); 19 | end 20 | end 21 | 22 | end 23 | 24 | -------------------------------------------------------------------------------- /+adi/+AD9364/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9361.Tx 2 | % adi.AD9364.Tx Transmit data from the AD9364 transceiver 3 | % The adi.AD9361.Rx System object is a signal sink that can 4 | % transmit complex data from the AD9364. 5 | % 6 | % tx = adi.AD9364.Tx; 7 | % tx = adi.AD9364.Tx('uri','192.168.2.1'); 8 | % 9 | % AD9364 Datasheet 10 | % 11 | % See also adi.FMComms4.Tx 12 | 13 | methods 14 | %% Constructor 15 | function obj = Tx(varargin) 16 | % Returns the matlabshared.libiio.base object 17 | coder.allowpcode('plain'); 18 | obj = obj@adi.AD9361.Tx(varargin{:}); 19 | end 20 | end 21 | 22 | end 23 | 24 | -------------------------------------------------------------------------------- /+adi/+ADRV9361Z7035/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9361.Rx 2 | % adi.ADRV9361Z7035.Rx Receive data from the ADRV9361Z7035 SOM 3 | % The adi.ADRV9361Z7035.Rx System object is a signal source that can 4 | % receive complex data from the ADRV9361Z7035. 5 | % 6 | % rx = adi.ADRV9361Z7035.Rx; 7 | % rx = adi.ADRV9361Z7035.Rx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9361.Rx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9361.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+ADRV9361Z7035/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9361.Tx 2 | % adi.ADRV9361Z7035.Tx Transmit data from the ADRV9361Z7035 SOM 3 | % The adi.ADRV9361Z7035.Tx System object is a signal source that can 4 | % send complex data to the FMComms2. 5 | % 6 | % tx = adi.ADRV9361Z7035.Tx; 7 | % tx = adi.ADRV9361Z7035.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9361.Tx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9361.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+ADRV9364Z7020/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9364.Rx 2 | % adi.ADRV9364Z7020.Tx Transmit data from the ADRV9364Z7020 SOM 3 | % The adi.ADRV9364Z7020.Tx System object is a signal source that can 4 | % send complex data to the FMComms4. 5 | % 6 | % tx = adi.ADRV9364Z7020.Tx; 7 | % tx = adi.ADRV9364Z7020.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9364.Tx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9364.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+ADRV9364Z7020/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9364.Tx 2 | % adi.ADRV9364Z7020.Tx Transmit data from the ADRV9364Z7020 SOM 3 | % The adi.ADRV9364Z7020.Tx System object is a signal sink that can 4 | % transmit complex data from the FMComms4. 5 | % 6 | % tx = adi.ADRV9364Z7020.Tx; 7 | % tx = adi.ADRV9364Z7020.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9364.Tx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9364.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+ADRV9371/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9371.Rx 2 | % adi.ADRV9371.Rx Receive data from the ADRV9371 evaluation platform 3 | % The adi.ADRV9371.Rx System object is a signal source that can receive 4 | % complex data from the ADRV9371. 5 | % 6 | % rx = adi.AD9371.Rx; 7 | % rx = adi.AD9371.Rx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9371.Rx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9371.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+ADRV9371/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9371.Tx 2 | % adi.ADRV9371.Tx Transmit data to the ADRV9371 evaluation platform 3 | % The adi.ADRV9371.Tx System object is a signal sink that can send 4 | % complex data to the ADRV9371. 5 | % 6 | % tx = adi.AD9371.Tx; 7 | % tx = adi.AD9371.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9371.Tx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9371.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+DAQ2/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9680.Rx 2 | % adi.DAQ2.Rx Receive data from the DAQ2 evaluation platform 3 | % The adi.DAQ2.Rx System object is a signal source that can 4 | % receive complex data from the DAQ2. 5 | % 6 | % rx = adi.DAQ2.Rx; 7 | % rx = adi.DAQ2.Rx('uri','192.168.2.1'); 8 | % 9 | % User Guide 10 | % 11 | % See also adi.AD9680.Rx, adi.DAQ2.Tx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9680.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+DAQ2/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9144.Tx 2 | % adi.DAQ2.Tx Transmit data from the DAQ2 evaluation platform 3 | % The adi.DAQ2.Tx System object is a signal source that can 4 | % send complex data to the DAQ2. 5 | % 6 | % tx = adi.DAQ2.Tx; 7 | % tx = adi.DAQ2.Tx('uri','192.168.2.1'); 8 | % 9 | % User Guide 10 | % 11 | % See also adi.AD9144.Tx, adi.DAQ2.Rx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9144.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+FMComms2/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9361.Rx 2 | % adi.FMComms2.Rx Receive data from the FMComms2 evaluation platform 3 | % The adi.FMComms2.Rx System object is a signal source that can 4 | % receive complex data from the FMComms2. 5 | % 6 | % rx = adi.FMComms2.Rx; 7 | % rx = adi.FMComms2.Rx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9361.Rx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9361.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+FMComms2/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9361.Tx 2 | % adi.FMComms2.Tx Transmit data from the FMComms2 evaluation platform 3 | % The adi.FMComms2.Tx System object is a signal source that can 4 | % send complex data to the FMComms2. 5 | % 6 | % tx = adi.FMComms2.Tx; 7 | % tx = adi.FMComms2.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9361.Tx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9361.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+FMComms3/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9361.Rx 2 | % adi.FMComms3.Rx Receive data from the FMComms3 evaluation platform 3 | % The adi.FMComms3.Rx System object is a signal source that can 4 | % receive complex data from the FMComms2. 5 | % 6 | % rx = adi.FMComms3.Rx; 7 | % rx = adi.FMComms3.Rx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9361.Rx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9361.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+FMComms3/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9361.Tx 2 | % adi.FMComms3.Tx Transmit data from the FMComms3 evaluation platform 3 | % The adi.FMComms3.Tx System object is a signal source that can 4 | % send complex data to the FMComms2. 5 | % 6 | % tx = adi.FMComms3.Tx; 7 | % tx = adi.FMComms3.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9361.Tx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9361.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+FMComms4/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9364.Rx 2 | % adi.FMComms4.Tx Transmit data from the FMComms4 evaluation platform 3 | % The adi.FMComms4.Tx System object is a signal source that can 4 | % send complex data to the FMComms4. 5 | % 6 | % tx = adi.FMComms4.Tx; 7 | % tx = adi.FMComms4.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9364.Tx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9364.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+FMComms4/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9364.Tx 2 | % adi.FMComms4.Tx Transmit data from the FMComms4 evaluation board 3 | % The adi.FMComms4.Tx System object is a signal sink that can 4 | % transmit complex data from the FMComms4. 5 | % 6 | % tx = adi.FMComms4.Tx; 7 | % tx = adi.FMComms4.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9364.Tx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9364.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+PackRF/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9361.Rx 2 | 3 | methods 4 | %% Constructor 5 | function obj = Rx(varargin) 6 | % Returns the matlabshared.libiio.base object 7 | coder.allowpcode('plain'); 8 | obj = obj@adi.AD9361.Rx(varargin{:}); 9 | end 10 | end 11 | 12 | end 13 | 14 | -------------------------------------------------------------------------------- /+adi/+PackRF/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9361.Tx 2 | 3 | methods 4 | %% Constructor 5 | function obj = Tx(varargin) 6 | % Returns the matlabshared.libiio.base object 7 | coder.allowpcode('plain'); 8 | obj = obj@adi.AD9361.Tx(varargin{:}); 9 | end 10 | end 11 | 12 | end 13 | 14 | -------------------------------------------------------------------------------- /+adi/+Pluto/Rx.m: -------------------------------------------------------------------------------- 1 | classdef Rx < adi.AD9363.Rx 2 | % adi.Pluto.Tx Transmit data from the Pluto evaluation platform 3 | % The adi.Pluto.Tx System object is a signal source that can 4 | % send complex data to the Pluto. 5 | % 6 | % tx = adi.Pluto.Tx; 7 | % tx = adi.Pluto.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9363.Tx 12 | methods 13 | %% Constructor 14 | function obj = Rx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9363.Rx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+Pluto/Tx.m: -------------------------------------------------------------------------------- 1 | classdef Tx < adi.AD9363.Tx 2 | % adi.Pluto.Tx Transmit data from the Pluto evaluation board 3 | % The adi.Pluto.Tx System object is a signal sink that can 4 | % transmit complex data from the Pluto. 5 | % 6 | % tx = adi.Pluto.Tx; 7 | % tx = adi.Pluto.Tx('uri','192.168.2.1'); 8 | % 9 | % Product Page 10 | % 11 | % See also adi.AD9363.Tx 12 | methods 13 | %% Constructor 14 | function obj = Tx(varargin) 15 | % Returns the matlabshared.libiio.base object 16 | coder.allowpcode('plain'); 17 | obj = obj@adi.AD9363.Tx(varargin{:}); 18 | end 19 | end 20 | 21 | end 22 | 23 | -------------------------------------------------------------------------------- /+adi/+utils/Downloader.m: -------------------------------------------------------------------------------- 1 | classdef Downloader < adi.utils.libad9361 2 | 3 | properties (Constant) 4 | PossibleDependencies = {'libad9361'}; 5 | end 6 | 7 | methods 8 | 9 | function download(obj,dep) 10 | if nargin == 0 11 | fprintf('Specific dependency name on input. Options are:\n%s',obj.PossibleDependencies); 12 | end 13 | switch dep 14 | case 'libad9361' 15 | download_libad9361(obj); 16 | otherwise 17 | error('Unknown dependency %s',dep); 18 | end 19 | end 20 | 21 | end 22 | end 23 | 24 | -------------------------------------------------------------------------------- /+adi/Version.m: -------------------------------------------------------------------------------- 1 | classdef Version 2 | %Version 3 | % BSP Version information 4 | properties(Constant) 5 | HDL = 'hdl_2018_r1'; 6 | Vivado = '2017.4.1'; 7 | MATLAB = 'R2018b'; 8 | Release = '18.2'; 9 | end 10 | properties(Dependent) 11 | VivadoShort 12 | end 13 | 14 | methods 15 | function value = get.VivadoShort(obj) 16 | value = obj.Vivado(1:6); 17 | end 18 | end 19 | end 20 | 21 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.mlappinstall 2 | *.mexw64 3 | **/slprj/** 4 | AD9361_Filter_Wizard/*TestFiltWiz*.m 5 | AD9361_Filter_Wizard/.previous_ip_addr 6 | -------------------------------------------------------------------------------- /CI/doc/ADI_Logo_AWP_Large.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/doc/ADI_Logo_AWP_Large.png -------------------------------------------------------------------------------- /CI/doc/Examples.mlx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/doc/Examples.mlx -------------------------------------------------------------------------------- /CI/doc/Support.mlx: -------------------------------------------------------------------------------- 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#################################################################################### 5 | 6 | include ../scripts/project-toplevel.mk 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9009/zcu102/boot/u-boot-zcu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9009/zcu102/boot/u-boot-zcu.elf -------------------------------------------------------------------------------- /CI/projects/adrv9009/zcu102/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | 6 | -------------------------------------------------------------------------------- /CI/projects/adrv9009/zcu102/boot/zynqmp.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [fsbl_config] a53_x64 4 | [bootloader] ./fsbl.elf 5 | [pmufw_image] ./pmufw.elf 6 | [destination_device=pl] ./system_top.bit 7 | [destination_cpu=a53-0,exception_level=el-3,trustzone] ./bl31.elf 8 | [destination_cpu=a53-0,exception_level=el-2] ./u-boot-zcu.elf 9 | } 10 | -------------------------------------------------------------------------------- /CI/projects/adrv9009/zcu102/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {14}] [get_bd_cells axi_cpu_interconnect] 3 | #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] 4 | connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M13_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9009/zcu102/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9009/zcu102 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9009/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9009/zcu102/system_project.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../../scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | adi_project_xilinx adrv9009_zcu102 7 | adi_project_files adrv9009_zcu102 [list \ 8 | "system_top.v" \ 9 | "system_constr.xdc"\ 10 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 11 | "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] 12 | 13 | adi_project_run adrv9009_zcu102 14 | 15 | -------------------------------------------------------------------------------- /CI/projects/adrv9009/zcu102/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9009/zcu102 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx adrv9009_zcu102 $proj_dir config_rxtx.tcl 9 | adi_project_files adrv9009_zcu102 [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc"\ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 13 | "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] 14 | 15 | adi_project_run adrv9009_zcu102 16 | 17 | # Copy the boot file to the root directory 18 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9361z7035/ccbob_cmos/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_cmos 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_cmos 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_cmos 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../common/adrv9361z7035_bd.tcl 3 | source ../common/ccbob_bd.tcl 4 | 5 | ad_ip_parameter util_ad9361_divclk CONFIG.SEL_0_DIV 2 6 | ad_ip_parameter util_ad9361_divclk CONFIG.SEL_1_DIV 1 7 | 8 | cfg_ad9361_interface CMOS 9 | 10 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29 11 | 12 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/system_project_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_cmos 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z035ifbg676-2L" 9 | adi_project_xilinx adrv9361z7035_ccbob_cmos $proj_dir config_rx.tcl 10 | adi_project_files adrv9361z7035_ccbob_cmos [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ 13 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_cmos.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \ 15 | "system_top.v" ] 16 | 17 | adi_project_run adrv9361z7035_ccbob_cmos 18 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 21 | 22 | 23 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_cmos/system_project_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_cmos 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z035ifbg676-2L" 9 | adi_project_xilinx adrv9361z7035_ccbob_cmos $proj_dir config_tx.tcl 10 | adi_project_files adrv9361z7035_ccbob_cmos [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ 13 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_cmos.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \ 15 | "system_top.v" ] 16 | 17 | adi_project_run adrv9361z7035_ccbob_cmos 18 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 21 | 22 | 23 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9361z7035/ccbob_lvds/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../common/adrv9361z7035_bd.tcl 3 | source ../common/ccbob_bd.tcl 4 | 5 | cfg_ad9361_interface LVDS 6 | 7 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29 8 | 9 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/system_project_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_lvds 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z035ifbg676-2L" 9 | adi_project_xilinx adrv9361z7035_ccbob_lvds $proj_dir config_rx.tcl 10 | adi_project_files adrv9361z7035_ccbob_lvds [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ 13 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \ 15 | "system_top.v" ] 16 | 17 | adi_project_run adrv9361z7035_ccbob_lvds 18 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbob_lvds/system_project_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbob_lvds 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z035ifbg676-2L" 9 | adi_project_xilinx adrv9361z7035_ccbob_lvds $proj_dir config_tx.tcl 10 | adi_project_files adrv9361z7035_ccbob_lvds [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ 13 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \ 15 | "system_top.v" ] 16 | 17 | adi_project_run adrv9361z7035_ccbob_lvds 18 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9361z7035/ccbox_lvds/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {6}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M05_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbox_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbox_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbox_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../common/adrv9361z7035_bd.tcl 3 | source ../common/ccbox_bd.tcl 4 | 5 | cfg_ad9361_interface LVDS 6 | 7 | create_bd_port -dir O sys_cpu_clk_out 8 | ad_connect sys_cpu_clk sys_cpu_clk_out 9 | 10 | set_property CONFIG.ADC_INIT_DELAY 29 [get_bd_cells axi_ad9361] 11 | 12 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/devicetree.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/devicetree.dtb -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/uImage: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/uImage -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds_modem/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccbox_lvds_modem/system_project_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccbox_lvds_modem 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z035ifbg676-2L" 9 | adi_project_xilinx adrv9361z7035_ccbox_lvds_modem $proj_dir config_rx_tx.tcl 10 | adi_project_files adrv9361z7035_ccbox_lvds_modem [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/library/common/ad_adl5904_rst.v" \ 13 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc" \ 15 | "$ad_hdl_dir/projects/adrv9361z7035/common/ccbox_constr.xdc" \ 16 | "system_top.v" ] 17 | 18 | adi_project_run adrv9361z7035_ccbox_lvds_modem 19 | 20 | # Copy the boot file to the root directory 21 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9361z7035/ccfmc_lvds/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {12}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M11_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M11_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9361z7035/ccfmc_lvds/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../common/adrv9361z7035_bd.tcl 3 | source ../common/ccfmc_bd.tcl 4 | 5 | cfg_ad9361_interface LVDS 6 | 7 | create_bd_port -dir O sys_cpu_clk_out 8 | ad_connect sys_cpu_clk sys_cpu_clk_out 9 | 10 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29 11 | 12 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9364z7020/ccbob_cmos/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {6}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M05_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_cmos 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_cmos 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_cmos 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../common/adrv9364z7020_bd.tcl 3 | source ../common/ccbob_bd.tcl 4 | 5 | ad_ip_parameter util_ad9361_divclk CONFIG.SEL_0_DIV 2 6 | ad_ip_parameter util_ad9361_divclk CONFIG.SEL_1_DIV 1 7 | 8 | cfg_ad9361_interface CMOS 9 | 10 | set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361] 11 | 12 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_cmos/system_project_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_cmos 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z020clg400-1" 9 | adi_project_xilinx adrv9364z7020_ccbob_cmos $proj_dir config_tx.tcl 10 | adi_project_files adrv9364z7020_ccbob_cmos [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/projects/adrv9364z7020/common/adrv9364z7020_constr.xdc" \ 13 | "$ad_hdl_dir/projects/adrv9364z7020/common/adrv9364z7020_constr_cmos.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9364z7020/common/ccbob_constr.xdc" \ 15 | "system_top.v" ] 16 | 17 | adi_project_run adrv9364z7020_ccbob_cmos 18 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 21 | 22 | 23 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9364z7020/ccbob_lvds/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {6}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M05_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../common/adrv9364z7020_bd.tcl 3 | source ../common/ccbob_bd.tcl 4 | 5 | cfg_ad9361_interface LVDS 6 | 7 | set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361] 8 | 9 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/system_project_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z020clg400-1" 9 | adi_project_xilinx adrv9364z7020_ccbob_lvds $proj_dir config_rx.tcl 10 | adi_project_files adrv9364z7020_ccbob_lvds [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/projects/adrv9364z7020/common/adrv9364z7020_constr.xdc" \ 13 | "$ad_hdl_dir/projects/adrv9364z7020/common/adrv9364z7020_constr_lvds.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9364z7020/common/ccbob_constr.xdc" \ 15 | "system_top.v" ] 16 | 17 | adi_project_run adrv9364z7020_ccbob_lvds 18 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 21 | 22 | 23 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbob_lvds/system_project_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | set p_device "xc7z020clg400-1" 9 | adi_project_xilinx adrv9364z7020_ccbob_lvds $proj_dir config_tx.tcl 10 | adi_project_files adrv9364z7020_ccbob_lvds [list \ 11 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 12 | "$ad_hdl_dir/projects/adrv9364z7020/common/adrv9364z7020_constr.xdc" \ 13 | "$ad_hdl_dir/projects/adrv9364z7020/common/adrv9364z7020_constr_lvds.xdc" \ 14 | "$ad_hdl_dir/projects/adrv9364z7020/common/ccbob_constr.xdc" \ 15 | "system_top.v" ] 16 | 17 | adi_project_run adrv9364z7020_ccbob_lvds 18 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 21 | 22 | 23 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9364z7020/ccbox_lvds/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {6}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M05_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbox_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbox_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9364z7020/ccbox_lvds 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9364z7020/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/ccbox_lvds/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../common/adrv9364z7020_bd.tcl 3 | source ../common/ccbox_bd.tcl 4 | 5 | cfg_ad9361_interface LVDS 6 | 7 | create_bd_port -dir O sys_cpu_clk_out 8 | ad_connect sys_cpu_clk sys_cpu_clk_out 9 | 10 | set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361] 11 | 12 | -------------------------------------------------------------------------------- /CI/projects/adrv9364z7020/common/ccbob_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | # lbfmc 3 | 4 | ad_connect sys_ps7/ENET1_GMII_RX_CLK GND 5 | ad_connect sys_ps7/ENET1_GMII_TX_CLK GND 6 | 7 | # un-used io (regular) 8 | 9 | ad_ip_instance axi_gpreg axi_gpreg 10 | ad_ip_parameter axi_gpreg CONFIG.NUM_OF_CLK_MONS 0 11 | ad_ip_parameter axi_gpreg CONFIG.NUM_OF_IO 1 12 | 13 | create_bd_port -dir I -from 31 -to 0 gp_in_0 14 | create_bd_port -dir O -from 31 -to 0 gp_out_0 15 | 16 | ad_connect gp_in_0 axi_gpreg/up_gp_in_0 17 | ad_connect gp_out_0 axi_gpreg/up_gp_out_0 18 | ad_cpu_interconnect 0x41200000 axi_gpreg 19 | 20 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | include ../scripts/project-toplevel.mk 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9371x/zc706/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | 6 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader] ./fsbl.elf 4 | ./system_top.bit 5 | ./u-boot-zc70x.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {19}] [get_bd_cells axi_cpu_interconnect] 3 | #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] 4 | connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M18_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9371x/zc706 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9371x/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout 8 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | set dac_fifo_name axi_ad9371_dacfifo 3 | set dac_fifo_address_width 10 4 | set dac_data_width 128 5 | set dac_dma_data_width 128 6 | 7 | source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl 8 | source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl 9 | 10 | ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200 11 | 12 | source $ad_hdl_dir/projects/adrv9371x/common/adrv9371x_bd.tcl 13 | #source ../common/adrv9371x_bd.tcl 14 | 15 | ad_connect sys_dma_clk sys_ps7/FCLK_CLK2 16 | ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in 17 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/system_project.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | source ../../scripts/adi_env.tcl 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx adrv9371x_zc706 9 | adi_project_files adrv9371x_zc706 [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc"\ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 13 | "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \ 14 | "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] 15 | 16 | adi_project_run adrv9371x_zc706 17 | 18 | 19 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zc706/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9371x/zc706 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx adrv9371x_zc706 $proj_dir config_rxtx.tcl 9 | adi_project_files adrv9371x_zc706 [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc"\ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 13 | "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \ 14 | "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] 15 | 16 | adi_project_run adrv9371x_zc706 17 | 18 | # Copy the boot file to the root directory 19 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 20 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zcu102/boot/u-boot-zcu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/adrv9371x/zcu102/boot/u-boot-zcu.elf -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zcu102/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | 6 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zcu102/boot/zynqmp.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [fsbl_config] a53_x64 4 | [bootloader] ./fsbl.elf 5 | [pmufw_image] ./pmufw.elf 6 | [destination_device=pl] ./system_top.bit 7 | [destination_cpu=a53-0,exception_level=el-3,trustzone] ./bl31.elf 8 | [destination_cpu=a53-0,exception_level=el-2] ./u-boot-zcu.elf 9 | } 10 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zcu102/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {14}] [get_bd_cells axi_cpu_interconnect] 3 | #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] 4 | connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M13_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zcu102/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9371x/zcu102 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9371x/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout 8 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zcu102/system_project.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../../scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | adi_project_xilinx adrv9371x_zcu102 7 | adi_project_files adrv9371x_zcu102 [list \ 8 | "system_top.v" \ 9 | "system_constr.xdc"\ 10 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 11 | "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] 12 | 13 | adi_project_run adrv9371x_zcu102 14 | 15 | -------------------------------------------------------------------------------- /CI/projects/adrv9371x/zcu102/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/adrv9371x/zcu102 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx adrv9371x_zcu102 $proj_dir config_rxtx.tcl 9 | adi_project_files adrv9371x_zcu102 [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc"\ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 13 | "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] 14 | 15 | adi_project_run adrv9371x_zcu102 16 | 17 | # Copy the boot file to the root directory 18 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 19 | -------------------------------------------------------------------------------- /CI/projects/common/boot/bl31.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/common/boot/bl31.elf -------------------------------------------------------------------------------- /CI/projects/common/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./fsbl.elf 4 | ./system_top.bit 5 | ./u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/common/boot/zynqmp.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [fsbl_config] a53_x64 4 | [bootloader] ./fsbl.elf 5 | [pmufw_image] ./pmufw.elf 6 | [destination_device=pl] ./system_top.bit 7 | [destination_cpu=a53-0,exception_level=el-3,trustzone] ./bl31.elf 8 | [destination_cpu=a53-0,exception_level=el-2] ./u-boot-zcu.elf 9 | } 10 | -------------------------------------------------------------------------------- /CI/projects/common/xilinx/adcfifo_bd.tcl: -------------------------------------------------------------------------------- 1 | # sys bram (use only when dma is not capable of keeping up). 2 | # generic fifo interface - existence is oblivious to software. 3 | 4 | ad_ip_instance util_adcfifo $adc_fifo_name 5 | ad_ip_parameter $adc_fifo_name CONFIG.ADC_DATA_WIDTH $adc_data_width 6 | ad_ip_parameter $adc_fifo_name CONFIG.DMA_DATA_WIDTH $adc_dma_data_width 7 | ad_ip_parameter $adc_fifo_name CONFIG.DMA_READY_ENABLE 1 8 | ad_ip_parameter $adc_fifo_name CONFIG.DMA_ADDRESS_WIDTH $adc_fifo_address_width 9 | 10 | 11 | -------------------------------------------------------------------------------- /CI/projects/common/xilinx/dacfifo_bd.tcl: -------------------------------------------------------------------------------- 1 | # sys bram (use only when dma is not capable of keeping up). 2 | # generic fifo interface - existence is oblivious to software. 3 | 4 | if {$dac_data_width != $dac_dma_data_width} { 5 | return -code error [format "ERROR: util_dacfifo dac/dma widths must be the same!"] 6 | } 7 | 8 | ad_ip_instance util_dacfifo $dac_fifo_name 9 | ad_ip_parameter $dac_fifo_name CONFIG.DATA_WIDTH $dac_data_width 10 | ad_ip_parameter $dac_fifo_name CONFIG.ADDRESS_WIDTH $dac_fifo_address_width 11 | 12 | -------------------------------------------------------------------------------- /CI/projects/common/zc706/zc706_plddr3_constr.xdc: -------------------------------------------------------------------------------- 1 | 2 | # clocks 3 | 4 | set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVDS} [get_ports sys_clk_p] 5 | set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports sys_clk_n] 6 | 7 | set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS15} [get_ports sys_rst] 8 | 9 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/common/prcfg.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_pblock pb_prcfg 3 | 4 | add_cells_to_pblock [get_pblocks pb_prcfg] [get_cells -quiet [list i_prcfg]] 5 | 6 | resize_pblock [get_pblocks pb_prcfg] -add {SLICE_X90Y0:SLICE_X161Y149} 7 | resize_pblock [get_pblocks pb_prcfg] -add {SLICE_X90Y150:SLICE_X122Y199} 8 | resize_pblock [get_pblocks pb_prcfg] -add {RAMB18_X4Y0:RAMB18_X7Y59} 9 | resize_pblock [get_pblocks pb_prcfg] -add {RAMB18_X4Y60:RAMB18_X4Y79} 10 | resize_pblock [get_pblocks pb_prcfg] -add {RAMB36_X4Y0:RAMB36_X7Y29} 11 | resize_pblock [get_pblocks pb_prcfg] -add {DSP48_X4Y0:DSP48_X6Y59} 12 | resize_pblock [get_pblocks pb_prcfg] -add {DSP48_X4Y60:DSP48_X4Y79} 13 | 14 | set_property SNAPPING_MODE ON [get_pblocks pb_prcfg] 15 | set_property RESET_AFTER_RECONFIG 1 [get_pblocks pb_prcfg] 16 | 17 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := fmcomms2_zc702 7 | 8 | M_DEPS += ../common/fmcomms2_bd.tcl 9 | M_DEPS += ../../common/zc702/zc702_system_constr.xdc 10 | M_DEPS += ../../common/zc702/zc702_system_bd.tcl 11 | M_DEPS += ../../../library/xilinx/common/ad_iobuf.v 12 | M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl 13 | 14 | LIB_DEPS += axi_ad9361 15 | LIB_DEPS += axi_clkgen 16 | LIB_DEPS += axi_dmac 17 | LIB_DEPS += axi_hdmi_tx 18 | LIB_DEPS += axi_spdif_tx 19 | LIB_DEPS += util_clkdiv 20 | LIB_DEPS += util_cpack 21 | LIB_DEPS += util_rfifo 22 | LIB_DEPS += util_tdd_sync 23 | LIB_DEPS += util_upack 24 | LIB_DEPS += util_wfifo 25 | 26 | include ../../scripts/project-xilinx.mk 27 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/fmcomms2/zc702/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {9}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M08_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/fmcomms2/zc702 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/fmcomms2/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl 3 | source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl 4 | 5 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 23 6 | 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc702/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/fmcomms2/zc702 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx fmcomms2_zc702 $proj_dir config_rxtx.tcl 9 | 10 | adi_project_files fmcomms2_zc702 [list \ 11 | "system_top.v" \ 12 | "system_constr.xdc"\ 13 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 14 | "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ] 15 | 16 | adi_project_run fmcomms2_zc702 17 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 18 | 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := fmcomms2_zc706 7 | 8 | M_DEPS += ../common/fmcomms2_bd.tcl 9 | M_DEPS += ../../common/zc706/zc706_system_constr.xdc 10 | M_DEPS += ../../common/zc706/zc706_system_bd.tcl 11 | M_DEPS += ../../../library/xilinx/common/ad_iobuf.v 12 | M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl 13 | 14 | LIB_DEPS += axi_ad9361 15 | LIB_DEPS += axi_clkgen 16 | LIB_DEPS += axi_dmac 17 | LIB_DEPS += axi_hdmi_tx 18 | LIB_DEPS += axi_spdif_tx 19 | LIB_DEPS += util_clkdiv 20 | LIB_DEPS += util_cpack 21 | LIB_DEPS += util_rfifo 22 | LIB_DEPS += util_tdd_sync 23 | LIB_DEPS += util_upack 24 | LIB_DEPS += util_wfifo 25 | 26 | include ../../scripts/project-xilinx.mk 27 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/fmcomms2/zc706/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {9}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M08_ARESETN] -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/fmcomms2/zc706 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/fmcomms2/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl 3 | source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl 4 | 5 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 20 6 | 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zc706/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/fmcomms2/zc706 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx fmcomms2_zc706 $proj_dir config_rxtx.tcl 9 | 10 | adi_project_files fmcomms2_zc706 [list \ 11 | "system_top.v" \ 12 | "system_constr.xdc"\ 13 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 14 | "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] 15 | 16 | adi_project_run fmcomms2_zc706 17 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 18 | 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zed/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/fmcomms2/zed/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zed/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zed/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zed/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {11}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M10_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M10_ARESETN] 5 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zed/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/fmcomms2/zed 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/fmcomms2/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zed/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl 3 | source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl 4 | 5 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 23 6 | 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms2/zed/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/fmcomms2/zed 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx fmcomms2_zed $proj_dir config_rxtx.tcl 9 | 10 | adi_project_files fmcomms2_zed [list \ 11 | "system_top.v" \ 12 | "system_constr.xdc"\ 13 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 14 | "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] 15 | 16 | adi_project_run fmcomms2_zed 17 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 18 | 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot 21 | 22 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := fmcomms5_zc702 7 | 8 | M_DEPS += ../common/fmcomms5_bd.tcl 9 | M_DEPS += ../../common/zc702/zc702_system_constr.xdc 10 | M_DEPS += ../../common/zc702/zc702_system_bd.tcl 11 | M_DEPS += ../../../library/xilinx/common/ad_iobuf.v 12 | M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl 13 | 14 | LIB_DEPS += axi_ad9361 15 | LIB_DEPS += axi_clkgen 16 | LIB_DEPS += axi_dmac 17 | LIB_DEPS += axi_hdmi_tx 18 | LIB_DEPS += axi_spdif_tx 19 | LIB_DEPS += util_clkdiv 20 | LIB_DEPS += util_cpack 21 | LIB_DEPS += util_rfifo 22 | LIB_DEPS += util_upack 23 | LIB_DEPS += util_wfifo 24 | 25 | include ../../scripts/project-xilinx.mk 26 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/fmcomms5/zc702/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {10}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M09_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M09_ARESETN] 5 | 6 | 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/fmcomms5/zc706 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/fmcomms5/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl 3 | 4 | ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1 5 | ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 150.0 6 | ad_connect sys_dma_clk sys_ps7/FCLK_CLK2 7 | source $ad_hdl_dir/projects/fmcomms5/common/fmcomms5_bd.tcl 8 | 9 | ad_ip_parameter axi_ad9361_0 CONFIG.ADC_INIT_DELAY 24 10 | ad_ip_parameter axi_ad9361_1 CONFIG.ADC_INIT_DELAY 24 11 | ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 1 12 | ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 1 13 | 14 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc702/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/fmcomms5/zc702 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx fmcomms5_zc702 $proj_dir config_rxtx.tcl 9 | 10 | adi_project_files fmcomms5_zc702 [list \ 11 | "system_top.v" \ 12 | "system_constr.xdc"\ 13 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 14 | "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ] 15 | 16 | adi_project_run fmcomms5_zc702 17 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 18 | 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := fmcomms5_zc706 7 | 8 | M_DEPS += ../common/fmcomms5_bd.tcl 9 | M_DEPS += ../../common/zc706/zc706_system_constr.xdc 10 | M_DEPS += ../../common/zc706/zc706_system_bd.tcl 11 | M_DEPS += ../../../library/xilinx/common/ad_iobuf.v 12 | M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl 13 | 14 | LIB_DEPS += axi_ad9361 15 | LIB_DEPS += axi_clkgen 16 | LIB_DEPS += axi_dmac 17 | LIB_DEPS += axi_hdmi_tx 18 | LIB_DEPS += axi_spdif_tx 19 | LIB_DEPS += util_clkdiv 20 | LIB_DEPS += util_cpack 21 | LIB_DEPS += util_rfifo 22 | LIB_DEPS += util_upack 23 | LIB_DEPS += util_wfifo 24 | 25 | include ../../scripts/project-xilinx.mk 26 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/CI/projects/fmcomms5/zc706/boot/u-boot.elf -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {10}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M09_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M09_ARESETN] 5 | 6 | 7 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/fmcomms5/zc706 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/fmcomms5/common/config_rxtx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl 3 | 4 | ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1 5 | ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200.0 6 | ad_connect sys_dma_clk sys_ps7/FCLK_CLK2 7 | source $ad_hdl_dir/projects/fmcomms5/common/fmcomms5_bd.tcl 8 | 9 | ad_ip_parameter axi_ad9361_0 CONFIG.ADC_INIT_DELAY 16 10 | ad_ip_parameter axi_ad9361_1 CONFIG.ADC_INIT_DELAY 16 11 | 12 | -------------------------------------------------------------------------------- /CI/projects/fmcomms5/zc706/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/fmcomms5/zc706 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx fmcomms5_zc706 $proj_dir config_rxtx.tcl 9 | 10 | adi_project_files fmcomms5_zc706 [list \ 11 | "system_top.v" \ 12 | "system_constr.xdc"\ 13 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ 14 | "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] 15 | 16 | adi_project_run fmcomms5_zc706 17 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 18 | 19 | # Copy the boot file to the root directory 20 | file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/pluto/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := pluto 7 | 8 | M_DEPS += ../../library/xilinx/common/ad_iobuf.v 9 | M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl 10 | 11 | LIB_DEPS += axi_ad9361 12 | LIB_DEPS += axi_dmac 13 | LIB_DEPS += util_fir_dec 14 | LIB_DEPS += util_fir_int 15 | 16 | include ../scripts/project-xilinx.mk 17 | -------------------------------------------------------------------------------- /CI/projects/pluto/config_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/pluto 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/pluto/config_rxtx_board.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /CI/projects/pluto/pluto_fpga.tcl: -------------------------------------------------------------------------------- 1 | # Build the project 2 | update_compile_order -fileset sources_1 3 | reset_run impl_1 4 | reset_run synth_1 5 | launch_runs synth_1 6 | wait_on_run synth_1 7 | launch_runs impl_1 -to_step write_bitstream 8 | wait_on_run impl_1 9 | 10 | # Define local variables 11 | set cdir [pwd] 12 | set sdk_loc vivado_prj.sdk 13 | 14 | # Export the hdf 15 | file delete -force $sdk_loc 16 | file mkdir $sdk_loc 17 | file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hdf 18 | 19 | # Close the Vivado project 20 | close_project 21 | 22 | puts "------------------------------------" 23 | puts "Embedded system build completed." 24 | puts "You may close this shell." 25 | puts "------------------------------------" 26 | exit 27 | -------------------------------------------------------------------------------- /CI/projects/pluto/system_project.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | set p_device "xc7z010clg225-1" 7 | adi_project_xilinx pluto 8 | 9 | adi_project_files pluto [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc" \ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] 13 | 14 | set_property is_enabled false [get_files *system_sys_ps7_0.xdc] 15 | adi_project_run pluto 16 | source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl 17 | 18 | -------------------------------------------------------------------------------- /CI/projects/pluto/system_project_rxtx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set ad_phdl_dir [pwd] 3 | set proj_dir $ad_hdl_dir/projects/pluto 4 | 5 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 6 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 7 | 8 | adi_project_xilinx pluto $proj_dir config_rxtx.tcl 9 | 10 | adi_project_files pluto [list \ 11 | "system_top.v" \ 12 | "system_constr.xdc"\ 13 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ] 14 | 15 | adi_project_run pluto 16 | #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl 17 | 18 | # Copy the boot file to the root directory 19 | #file copy -force $proj_dir/boot $ad_hdl_dir/boot -------------------------------------------------------------------------------- /CI/projects/scripts/adi_tquest.tcl: -------------------------------------------------------------------------------- 1 | 2 | report_timing -detail full_path -npaths 20 -file timing_impl.log 3 | 4 | set worst_path [get_timing_paths -npaths 1 -setup] 5 | foreach_in_collection path $worst_path { 6 | set slack [get_path_info $path -slack] 7 | } 8 | 9 | if {$slack > 0} { 10 | set worst_path [get_timing_paths -npaths 1 -hold] 11 | foreach_in_collection path $worst_path { 12 | set slack [get_path_info $path -slack] 13 | } 14 | } 15 | 16 | if {$slack < 0} { 17 | set sof_files [glob *.sof] 18 | foreach sof_file $sof_files { 19 | set root_sof_file [file rootname $sof_file] 20 | set new_sof_file [append root_sof_file "_timing.sof"] 21 | file rename -force $sof_file $new_sof_file 22 | } 23 | return -code error [format "ERROR: Timing Constraints NOT met!"] 24 | } 25 | -------------------------------------------------------------------------------- /CI/projects/scripts/fixmake.sh: -------------------------------------------------------------------------------- 1 | grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile 2 | cd pmufw 3 | make -------------------------------------------------------------------------------- /CI/projects/scripts/pmufw_zynqmp.tcl: -------------------------------------------------------------------------------- 1 | 2 | set cdir [pwd] 3 | set sdk_loc $cdir/vivado_prj.sdk 4 | 5 | ### Create create_pmufw_project.tcl 6 | set hwdsgn [open_hw_design $sdk_loc/system_top.hdf] 7 | generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw 8 | quit 9 | -------------------------------------------------------------------------------- /CI/scripts/Docker: -------------------------------------------------------------------------------- 1 | FROM ubuntu:16.04 2 | 3 | MAINTAINER Travis Collins 4 | RUN DEBIAN_FRONTEND=noninteractive apt update 5 | RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg 6 | RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb 7 | RUN DEBIAN_FRONTEND=noninteractive apt-get install -y fakeroot libncurses5-dev libssl-dev ccache dfu-util u-boot-tools device-tree-compiler 8 | RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libssl-dev mtools bc python cpio zip unzip rsync file wget 9 | RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386 10 | RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6 11 | -------------------------------------------------------------------------------- /CI/scripts/dockermake: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | docker build . -t matlabci -f CI/scripts/Docker 3 | docker run --rm -e "INCLUDE_EXAMPLES=$INCLUDE_EXAMPLES" -e "BOARD=$BOARD" -e "LM_LICENSE_FILE=$LM_LICENSE_FILE" -e "XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE" -e "MLRELEASE=$MLRELEASE" -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work" -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB -v /root/.matlab:/root/.matlabro:ro -v /root/.Xilinx:/root/.Xilinxro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'" 4 | -------------------------------------------------------------------------------- /CI/scripts/linter.m: -------------------------------------------------------------------------------- 1 | clc; 2 | ignoreFolders = {'CI','doc','test'}; 3 | cd ../.. 4 | d = pwd; 5 | cd .. 6 | addpath(genpath(d)); 7 | cd(d); 8 | 9 | files = dir('**/*.m'); 10 | for file = 1:length(files) 11 | if contains(files(file).folder,ignoreFolders) 12 | continue; 13 | end 14 | mfile = fullfile(files(file).folder,files(file).name); 15 | rpt = mlint(mfile); 16 | if ~isempty(rpt) 17 | disp(mfile); 18 | for l = 1:length(rpt) 19 | disp([num2str(rpt(l).line) ': ' rpt(l).message]); 20 | end 21 | end 22 | end 23 | 24 | -------------------------------------------------------------------------------- /CI/scripts/setupDocker.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # This file is run inside of the docker container 3 | echo "Copying HSP files" 4 | cp -r /mlhspro /mlhsp 5 | echo "Copying .matlab" 6 | cp -r /root/.matlabro /root/.matlab 7 | echo "Copying .Xilinx" 8 | cp -r /root/.Xilinxro /root/.Xilinx 9 | -------------------------------------------------------------------------------- /CI/scripts/synth_designs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | MLFLAGS="-nodisplay -nodesktop -nosplash" 4 | 5 | if [ -z "$MLRELEASE" ] 6 | then 7 | MLRELEASE=R2018b 8 | fi 9 | 10 | MLPATH=/usr/local/MATLAB 11 | 12 | cd ../.. 13 | cp hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m 14 | sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m 15 | source /opt/Xilinx/Vivado/2017.4/settings64.sh 16 | Xvfb :77 & 17 | export DISPLAY=:77 18 | export SWT_GTK3=0 19 | source /opt/Xilinx/Vivado/2017.4/settings64.sh 20 | $MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "cd('test');runSynthTests;" 21 | kill -9 `pidof Xvfb` 22 | -------------------------------------------------------------------------------- /CI/scripts/targeting_designs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | MLFLAGS="-nodisplay -nodesktop -nosplash" 4 | 5 | if [ -z "$MLRELEASE" ] 6 | then 7 | MLRELEASE=R2018b 8 | fi 9 | 10 | MLPATH=/usr/local/MATLAB 11 | 12 | cd ../.. 13 | source /opt/Xilinx/Vivado/2017.4/settings64.sh 14 | Xvfb :77 & 15 | export DISPLAY=:77 16 | export SWT_GTK3=0 17 | source /opt/Xilinx/Vivado/2017.4/settings64.sh 18 | $MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "addpath(genpath('test'));addpath(genpath('deps'));runDemoTests;" 19 | kill -9 `pidof Xvfb` 20 | -------------------------------------------------------------------------------- /blocks/ADIBlocks.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/blocks/ADIBlocks.slx -------------------------------------------------------------------------------- /doc/adi_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/doc/adi_logo.png -------------------------------------------------------------------------------- /doc/helptoc.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | Analog Devices Inc Board Support Packages 4 | 5 | System Objects 6 | Supported Hardware 7 | Examples 8 | Support 9 | 10 | -------------------------------------------------------------------------------- /hdl_wa_bsp/common/+hdlbsp/+util/+SDUpdater/DeviceTypes.m: -------------------------------------------------------------------------------- 1 | classdef DeviceTypes 2 | enumeration 3 | ZYNQ, ALTERA_SOC 4 | end 5 | end 6 | 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/common/+hdlbsp/+util/+SDUpdater/FWModes.m: -------------------------------------------------------------------------------- 1 | classdef FWModes 2 | enumeration 3 | FAT32_ZIP, DISK_IMAGE 4 | end 5 | end 6 | 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/common/+hdlbsp/+util/SDUpdater.m: -------------------------------------------------------------------------------- 1 | function SDUpdater(fhndl) 2 | 3 | persistent app cleanup; 4 | 5 | if ~isempty(cleanup) 6 | cleanup = []; 7 | end 8 | 9 | if ~ispc 10 | error('The SD Updater is only supported on Windows platforms'); 11 | end 12 | 13 | app = feval(fhndl); 14 | cleanup = onCleanup(@()delete(app)); 15 | 16 | -------------------------------------------------------------------------------- /hdl_wa_bsp/common/+hdlbsp/install.m: -------------------------------------------------------------------------------- 1 | function install(mode) 2 | % hdlbsp.install adds/removes common BSP utilities 3 | 4 | % Copyright 2016 MathWorks, Inc. All Rights Reserved. 5 | 6 | if nargin == 0 7 | mode = 0; 8 | end 9 | 10 | %% Initialization 11 | % Determine where we're operating out of 12 | hdlbspRootDir = fileparts(strtok(mfilename('fullpath'), '+')); 13 | olddir = cd(hdlbspRootDir); % Make sure we can access the tools 14 | cleanup = onCleanup(@()cd(olddir)); 15 | 16 | % Update the path 17 | paths = {... 18 | fullfile(hdlbspRootDir),... 19 | }; 20 | 21 | hdlbsp.util.vendorInstall(mode,paths); 22 | end -------------------------------------------------------------------------------- /hdl_wa_bsp/common/+hdlbsp/uninstall.m: -------------------------------------------------------------------------------- 1 | function uninstall 2 | % hdlbsp.uninstall removes common HDL BSP utilities 3 | 4 | % Copyright 2016 MathWorks, Inc. All Rights Reserved. 5 | 6 | hdlbsp.install(1); 7 | end 8 | -------------------------------------------------------------------------------- /hdl_wa_bsp/common/Contents.m: -------------------------------------------------------------------------------- 1 | % HDL Coder BSP Tools 2 | % Version 1.07 (R2017b) 01-May-2018 3 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+zcu102/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.adrv9009.common.plugin_board('ZCU102'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+zcu102/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9009.common.plugin_rd('ZCU102', 'Rx'); 6 | AnalogDevices.adrv9009.zcu102.add_io(hRD, 'Rx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+zcu102/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.adrv9009.common.plugin_rd('ZCU102', 'Rx & Tx'); 8 | AnalogDevices.adrv9009.zcu102.add_io(hRD, 'Rx & Tx'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+zcu102/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.adrv9009.common.plugin_rd('ZCU102', 'Tx'); 8 | AnalogDevices.adrv9009.zcu102.add_io(hRD, 'Tx'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbob_cmos/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbob_cmos','Rx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx', 'ccbob_cmos'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbob_cmos/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbob_cmos','Rx & Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx & Tx', 'ccbob_cmos'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbob_cmos/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbob_cmos','Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Tx', 'ccbob_cmos'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbob_lvds/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbob_lvds','Rx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx', 'ccbob_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbob_lvds/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbob_lvds','Rx & Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx & Tx', 'ccbob_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbob_lvds/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbob_lvds','Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Tx', 'ccbob_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbox_lvds/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbox_lvds','Rx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx', 'ccbox_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbox_lvds/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbox_lvds','Rx & Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx & Tx', 'ccbox_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccbox_lvds/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccbox_lvds','Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Tx', 'ccbox_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccfmc_lvds/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccfmc_lvds','Rx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx','ccfmc_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccfmc_lvds/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccfmc_lvds','Rx & Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Rx & Tx', 'ccfmc_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+ccfmc_lvds/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9361z7035.common.plugin_rd('ccfmc_lvds','Tx'); 6 | AnalogDevices.adrv9361z7035.common.add_io(hRD, 'Tx', 'ccfmc_lvds'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+common/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hB = plugin_board() 2 | % Use Plugin API to create board plugin object 3 | 4 | % Copyright 2015 The MathWorks, Inc. 5 | 6 | hB = hdlcoder.Board; 7 | 8 | % Target Board Information 9 | hB.BoardName = sprintf('AnalogDevices ADRV9361-Z7035'); 10 | 11 | % FPGA Device 12 | hB.FPGAVendor = 'Xilinx'; 13 | hB.FPGAFamily = 'Zynq'; 14 | 15 | % Determine the device based on the board 16 | hB.FPGADevice = sprintf('xc7%s', 'z035i'); 17 | hB.FPGAPackage = 'fbg676'; 18 | hB.FPGASpeed = '-2L'; 19 | 20 | 21 | % Tool Info 22 | hB.SupportedTool = {'Xilinx Vivado'}; 23 | 24 | % FPGA JTAG chain position 25 | hB.JTAGChainPosition = 2; 26 | 27 | %% Add interfaces 28 | % Standard "External Port" interface 29 | 30 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbob_cmos/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbob_cmos','Rx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Rx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbob_cmos/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbob_cmos','Rx & Tx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Rx & Tx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbob_cmos/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbob_cmos','Tx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Tx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbob_lvds/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbob_lvds','Rx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Rx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbob_lvds/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbob_lvds','Rx & Tx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Rx & Tx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbob_lvds/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbob_lvds','Tx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Tx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbox_lvds/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbox_lvds','Rx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Rx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbox_lvds/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbox_lvds','Rx & Tx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Rx & Tx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+ccbox_lvds/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9364z7020.common.plugin_rd('ccbox_lvds','Tx'); 6 | AnalogDevices.adrv9364z7020.common.add_io(hRD, 'Tx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+common/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hB = plugin_board() 2 | % Use Plugin API to create board plugin object 3 | 4 | % Copyright 2015 The MathWorks, Inc. 5 | 6 | hB = hdlcoder.Board; 7 | 8 | % Target Board Information 9 | hB.BoardName = sprintf('AnalogDevices ADRV9364-Z7020'); 10 | 11 | % FPGA Device 12 | hB.FPGAVendor = 'Xilinx'; 13 | hB.FPGAFamily = 'Zynq'; 14 | 15 | % Determine the device based on the board 16 | hB.FPGADevice = sprintf('xc7%s', 'z020'); 17 | hB.FPGAPackage = 'clg400'; 18 | hB.FPGASpeed = '-1'; 19 | 20 | % Tool Info 21 | hB.SupportedTool = {'Xilinx Vivado'}; 22 | 23 | % FPGA JTAG chain position 24 | hB.JTAGChainPosition = 2; 25 | 26 | %% Add interfaces 27 | % Standard "External Port" interface 28 | 29 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.adrv9371x.common.plugin_board('ZC706'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZC706', 'Rx'); 6 | AnalogDevices.adrv9371x.zc706.add_io(hRD, 'Rx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZC706', 'Rx & Tx'); 8 | AnalogDevices.adrv9371x.zc706.add_io(hRD, 'Rx & Tx'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZC706', 'Tx'); 8 | AnalogDevices.adrv9371x.zc706.add_io(hRD, 'Tx'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zcu102/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.adrv9371x.common.plugin_board('ZCU102'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zcu102/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Call the common reference design definition function 5 | hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZCU102', 'Rx'); 6 | AnalogDevices.adrv9371x.zcu102.add_io(hRD, 'Rx'); 7 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zcu102/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZCU102', 'Rx & Tx'); 8 | AnalogDevices.adrv9371x.zcu102.add_io(hRD, 'Rx & Tx'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zcu102/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZCU102', 'Tx'); 8 | AnalogDevices.adrv9371x.zcu102.add_io(hRD, 'Tx'); 9 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc702/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.fmcomms2.common.plugin_board('ZC702'); 9 | 10 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc702/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZC702', 'Rx'); 8 | AnalogDevices.fmcomms2.zc702.add_io(hRD,'Rx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc702/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZC702', 'Rx & Tx'); 8 | AnalogDevices.fmcomms2.zc702.add_io(hRD,'Rx & Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc702/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZC702', 'Tx'); 8 | AnalogDevices.fmcomms2.zc702.add_io(hRD,'Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc706/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.fmcomms2.common.plugin_board('ZC706'); 9 | 10 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc706/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZC706', 'Rx'); 8 | AnalogDevices.fmcomms2.zc706.add_io(hRD,'Rx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc706/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZC706', 'Rx & Tx'); 8 | AnalogDevices.fmcomms2.zc706.add_io(hRD,'Rx & Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zc706/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZC706', 'Tx'); 8 | AnalogDevices.fmcomms2.zc706.add_io(hRD,'Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zed/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.fmcomms2.common.plugin_board('ZED'); 9 | 10 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zed/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZED', 'Rx'); 8 | AnalogDevices.fmcomms2.zed.add_io(hRD,'Rx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zed/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZED', 'Rx & Tx'); 8 | AnalogDevices.fmcomms2.zed.add_io(hRD,'Rx & Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+zed/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms2.common.plugin_rd('ZED', 'Tx'); 8 | AnalogDevices.fmcomms2.zed.add_io(hRD,'Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc702/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.fmcomms5.common.plugin_board('ZC702'); 9 | 10 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc702/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms5.common.plugin_rd('ZC702', 'Rx'); 8 | AnalogDevices.fmcomms5.zc702.add_io(hRD,'Rx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc702/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms5.common.plugin_rd('ZC702', 'Rx & Tx'); 8 | AnalogDevices.fmcomms5.zc702.add_io(hRD,'Rx & Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc702/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms5.common.plugin_rd('ZC702', 'Tx'); 8 | AnalogDevices.fmcomms5.zc702.add_io(hRD,'Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc706/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.fmcomms5.common.plugin_board('ZC706'); 9 | 10 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc706/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms5.common.plugin_rd('ZC706', 'Rx'); 8 | AnalogDevices.fmcomms5.zc706.add_io(hRD,'Rx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc706/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms5.common.plugin_rd('ZC706', 'Rx & Tx'); 8 | AnalogDevices.fmcomms5.zc706.add_io(hRD,'Rx & Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+zc706/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.fmcomms5.common.plugin_rd('ZC706', 'Tx'); 8 | AnalogDevices.fmcomms5.zc706.add_io(hRD,'Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hB = plugin_board() 2 | % Use Plugin API to create board plugin object 3 | 4 | % Copyright 2015 The MathWorks, Inc. 5 | 6 | hB = hdlcoder.Board; 7 | 8 | % Target Board Information 9 | hB.BoardName = 'AnalogDevices ADALM-PLUTO'; 10 | 11 | % FPGA Device 12 | hB.FPGAVendor = 'Xilinx'; 13 | hB.FPGAFamily = 'Zynq'; 14 | 15 | % Determine the device based on the board 16 | hB.FPGADevice = sprintf('xc7%s', 'z010'); 17 | hB.FPGAPackage = 'clg225'; 18 | hB.FPGASpeed = '-1'; 19 | 20 | % Tool Info 21 | hB.SupportedTool = {'Xilinx Vivado'}; 22 | 23 | % FPGA JTAG chain position 24 | hB.JTAGChainPosition = 2; 25 | 26 | %% Add interfaces 27 | % Standard "External Port" interface 28 | 29 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.pluto.plugin_rd('Rx'); 8 | AnalogDevices.pluto.add_io(hRD,'Rx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rxtx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_rxtx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.pluto.plugin_rd('Rx & Tx'); 8 | AnalogDevices.pluto.add_io(hRD,'Rx & Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_tx.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd_tx 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevices.pluto.plugin_rd('Tx'); 8 | AnalogDevices.pluto.add_io(hRD,'Tx'); -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+util/extmodeHooksADI.m: -------------------------------------------------------------------------------- 1 | function extmodeHooksADI(hObj,hookpoint) 2 | 3 | % Copyright 2014-2015 The MathWorks, Inc. 4 | 5 | modelName = get(getModel(hObj),'Name'); 6 | modelName = sprintf('%s.elf', modelName); 7 | data = codertarget.data.getData(hObj); 8 | h__z = zynq(data.RTOS); 9 | h__z.IPAddress = getenv('ADI_ZYNQ_SDR_IPADDRESS'); 10 | h__z.Username = 'root'; 11 | h__z.Password = 'analog'; 12 | 13 | switch (lower(hookpoint)) 14 | case 'preconnectfcn', 15 | waitForAppToStart(h__z, modelName, 60); 16 | case 'setupfcn' 17 | checkConnection(h__z); 18 | otherwise 19 | end 20 | 21 | end 22 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/uninstall.m: -------------------------------------------------------------------------------- 1 | function uninstall 2 | % AnalogDevices.uninstall removes AnalogDevices HDL BSPs 3 | 4 | % Copyright 2015 MathWorks, Inc. All Rights Reserved. 5 | 6 | AnalogDevices.install(1); 7 | end 8 | -------------------------------------------------------------------------------- /hdl_wa_bsp/vendor/AnalogDevices/Contents.m: -------------------------------------------------------------------------------- 1 | % HDL Coder BSP: Analog Devices Inc 2 | % Version 19.1 (R2019a) 8-July-2019 3 | -------------------------------------------------------------------------------- /hil_models/daq2/daq2.m: -------------------------------------------------------------------------------- 1 | % Test Tx DDS output 2 | uri = 'ip:192.168.2.1'; 3 | 4 | %% Tx set up 5 | tx = adi.DAQ2.Tx('uri',uri); 6 | tx.DataSource = 'DDS'; 7 | toneFreq = 45e6; 8 | tx.DDSFrequencies = repmat(toneFreq,2,4); 9 | tx(); 10 | 11 | %% Rx set up 12 | rx = adi.DAQ2.Rx('uri',uri); 13 | 14 | %% Run 15 | for k=1:10 16 | valid = false; 17 | while ~valid 18 | [out, valid] = rx(); 19 | end 20 | end 21 | rx.release(); 22 | tx.release(); 23 | 24 | %% Plot 25 | nSamp = length(out); 26 | fs = tx.SamplingRate; 27 | FFTRxData = fftshift(10*log10(abs(fft(out)))); 28 | df = fs/nSamp; freqRangeRx = (-fs/2:df:fs/2-df).'/1000; 29 | plot(freqRangeRx, FFTRxData); 30 | xlabel('Frequency (kHz)');ylabel('Amplitude (dB)');grid on; 31 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_MATLAB/ConvertFracDeg.m: -------------------------------------------------------------------------------- 1 | function [dd,mm,ss] = ConvertFracDeg(degIn) 2 | 3 | % Copyright 2010, The MathWorks, Inc. 4 | 5 | if degIn>0 6 | dd=floor(degIn); 7 | else 8 | dd=ceil(degIn); 9 | end 10 | fracd = abs(degIn-dd); 11 | if dd==0 12 | if degIn>0 13 | mm=floor(fracd*60); 14 | fracm = fracd-(mm/60); 15 | else 16 | mm=-floor(fracd*60); 17 | fracm = fracd+(mm/60); 18 | end 19 | else 20 | mm=floor(fracd*60); 21 | fracm = fracd-(mm/60); 22 | end 23 | if (dd==0 && mm==0) 24 | if degIn>0 25 | ss=(fracm*3600); 26 | else 27 | ss=-(fracm*3600); 28 | end 29 | else 30 | ss=(fracm*3600); 31 | end 32 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_MATLAB/ad9361.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-lpc 2 | data_out_device = cf-ad9361-lpc 3 | ctrl_device = ad9361-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 6 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 7 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 8 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 9 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 10 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 11 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 12 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 13 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 14 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 15 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 16 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_MATLAB/newModeS.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/ADSB_MATLAB/newModeS.mat -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink/ConvertFracDeg.m: -------------------------------------------------------------------------------- 1 | function [dd,mm,ss] = ConvertFracDeg(degIn) 2 | 3 | % Copyright 2010, The MathWorks, Inc. 4 | 5 | if degIn>0 6 | dd=floor(degIn); 7 | else 8 | dd=ceil(degIn); 9 | end 10 | fracd = abs(degIn-dd); 11 | if dd==0 12 | if degIn>0 13 | mm=floor(fracd*60); 14 | fracm = fracd-(mm/60); 15 | else 16 | mm=-floor(fracd*60); 17 | fracm = fracd+(mm/60); 18 | end 19 | else 20 | mm=floor(fracd*60); 21 | fracm = fracd-(mm/60); 22 | end 23 | if (dd==0 && mm==0) 24 | if degIn>0 25 | ss=(fracm*3600); 26 | else 27 | ss=-(fracm*3600); 28 | end 29 | else 30 | ss=(fracm*3600); 31 | end 32 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink/DecodeBits.m: -------------------------------------------------------------------------------- 1 | function DecodeBits(bits) 2 | 3 | % Copyright 2010, The MathWorks, Inc. 4 | 5 | c = reshape(bits(1:112),4,28); 6 | d = bin2dec(num2str(c')); 7 | rxBytes = dec2hex(d)'; 8 | s1 = sprintf('Aircraft ID %s Long Message CRC: %s', rxBytes(3:8), rxBytes); 9 | disp(s1) 10 | if rxBytes(9) == '9' && rxBytes(10) == '9' 11 | [nV, eV, aV] = AltVelCalc(rxBytes); 12 | elseif rxBytes(9) == '5' || rxBytes(9) == '6' 13 | [alt, lat, long] = LatLongCalcSingle(rxBytes); 14 | elseif rxBytes(9) == '9' && rxBytes(10) =='0' 15 | [alt, lat, long] = LatLongCalcSingle(rxBytes); 16 | end 17 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink/ModeS_FixPt_Pipelined_ADI.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/ADSB_Simulink/ModeS_FixPt_Pipelined_ADI.slx -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink/data_Yb.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/ADSB_Simulink/data_Yb.mat -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink_libiio/ConvertFracDeg.m: -------------------------------------------------------------------------------- 1 | function [dd,mm,ss] = ConvertFracDeg(degIn) 2 | 3 | % Copyright 2010, The MathWorks, Inc. 4 | 5 | if degIn>0 6 | dd=floor(degIn); 7 | else 8 | dd=ceil(degIn); 9 | end 10 | fracd = abs(degIn-dd); 11 | if dd==0 12 | if degIn>0 13 | mm=floor(fracd*60); 14 | fracm = fracd-(mm/60); 15 | else 16 | mm=-floor(fracd*60); 17 | fracm = fracd+(mm/60); 18 | end 19 | else 20 | mm=floor(fracd*60); 21 | fracm = fracd-(mm/60); 22 | end 23 | if (dd==0 && mm==0) 24 | if degIn>0 25 | ss=(fracm*3600); 26 | else 27 | ss=-(fracm*3600); 28 | end 29 | else 30 | ss=(fracm*3600); 31 | end 32 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink_libiio/DecodeBits.m: -------------------------------------------------------------------------------- 1 | function DecodeBits(bits) 2 | 3 | % Copyright 2010, The MathWorks, Inc. 4 | 5 | c = reshape(bits(1:112),4,28); 6 | d = bin2dec(num2str(c')); 7 | rxBytes = dec2hex(d)'; 8 | s1 = sprintf('Aircraft ID %s Long Message CRC: %s', rxBytes(3:8), rxBytes); 9 | disp(s1) 10 | if rxBytes(9) == '9' && rxBytes(10) == '9' 11 | [nV, eV, aV] = AltVelCalc(rxBytes); 12 | elseif rxBytes(9) == '5' || rxBytes(9) == '6' 13 | [alt, lat, long] = LatLongCalcSingle(rxBytes); 14 | elseif rxBytes(9) == '9' && rxBytes(10) =='0' 15 | [alt, lat, long] = LatLongCalcSingle(rxBytes); 16 | end 17 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink_libiio/ModeS_Simulink_libiio.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/ADSB_Simulink_libiio/ModeS_Simulink_libiio.slx -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink_libiio/ad9361.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-lpc 2 | data_out_device = cf-ad9361-lpc 3 | ctrl_device = ad9361-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 6 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 7 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 8 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 9 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 10 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 11 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 12 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 13 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 14 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 15 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 16 | -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_Simulink_libiio/data_Yb.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/ADSB_Simulink_libiio/data_Yb.mat -------------------------------------------------------------------------------- /hil_models/legacy/ADSB_transmitter/txData.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/ADSB_transmitter/txData.mat -------------------------------------------------------------------------------- /hil_models/legacy/LTE_MATLAB/ad9361.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-lpc 2 | data_out_device = cf-ad9361-lpc 3 | ctrl_device = ad9361-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 6 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 7 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 8 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 9 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 10 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 11 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 12 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 13 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 14 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 15 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 16 | -------------------------------------------------------------------------------- /hil_models/legacy/LTE_MATLAB/demo.m: -------------------------------------------------------------------------------- 1 | function demo(IP) 2 | %while(1) 3 | [plots,~,~]=ad9361_LTE(IP,'LTE1.4'); 4 | close all; 5 | 6 | delete(plots{1});delete(plots{2});delete(plots{3});delete(plots{4}); 7 | clear functions; 8 | [plots,~,~]=ad9361_LTE(IP,'LTE3'); 9 | close all; 10 | 11 | delete(plots{1});delete(plots{2});delete(plots{3});delete(plots{4}); 12 | clear functions; 13 | [plots,~,~]=ad9361_LTE(IP,'LTE5'); 14 | close all; 15 | 16 | delete(plots{1});delete(plots{2});delete(plots{3});delete(plots{4}); 17 | clear functions; 18 | [plots,~,~]=ad9361_LTE(IP,'LTE10'); 19 | close all; 20 | 21 | delete(plots{1});delete(plots{2});delete(plots{3});delete(plots{4}); 22 | clear functions; 23 | %end -------------------------------------------------------------------------------- /hil_models/legacy/adrv9009/adrv9009.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = axi-adrv9009-tx-hpc 2 | data_out_device = axi-adrv9009-rx-hpc 3 | ctrl_device = adrv9009-phy 4 | channel = TRX_LO_FREQ,IN,out_altvoltage0_TRX_LO_frequency, 5 | channel = RX1_RF_BANDWIDTH,IN,in_voltage0_rf_bandwidth, 6 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 7 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 8 | channel = RX2_RF_BANDWIDTH,IN,in_voltage1_rf_bandwidth, 9 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 10 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 11 | channel = TX_RF_BANDWIDTH,IN,out_voltage0_rf_bandwidth, 12 | channel = TX_GAIN,IN,out_voltage0_hardwaregain, 13 | -------------------------------------------------------------------------------- /hil_models/legacy/adrv9371/ad9371.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = axi-ad9371-tx-hpc 2 | data_out_device = axi-ad9371-rx-hpc 3 | ctrl_device = ad9371-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX1_RF_BANDWIDTH,IN,in_voltage0_rf_bandwidth, 6 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 7 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 8 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 9 | channel = RX2_RF_BANDWIDTH,IN,in_voltage1_rf_bandwidth, 10 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 11 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 12 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 13 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 14 | channel = TX_RF_BANDWIDTH,IN,out_voltage0_rf_bandwidth, 15 | channel = TX_GAIN,IN,out_voltage0_hardwaregain, 16 | -------------------------------------------------------------------------------- /hil_models/legacy/daq2_data_stream/daq2.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = axi-ad9144-hpc 2 | data_out_device = axi-ad9680-hpc 3 | ctrl_device = ad9523-1 -------------------------------------------------------------------------------- /hil_models/legacy/daq2_data_stream/daq2_sim.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/daq2_data_stream/daq2_sim.slx -------------------------------------------------------------------------------- /hil_models/legacy/fmcomms2_3_data_stream/ad9361.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-lpc 2 | data_out_device = cf-ad9361-lpc 3 | ctrl_device = ad9361-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 6 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 7 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 8 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 9 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 10 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 11 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 12 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 13 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 14 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 15 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 16 | -------------------------------------------------------------------------------- /hil_models/legacy/fmcomms2_3_data_stream/ad9361_sim.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/fmcomms2_3_data_stream/ad9361_sim.slx -------------------------------------------------------------------------------- /hil_models/legacy/fmcomms4_data_stream/ad9364.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-lpc 2 | data_out_device = cf-ad9361-lpc 3 | ctrl_device = ad9361-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 6 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 7 | channel = RX_GAIN_MODE,IN,in_voltage0_gain_control_mode, 8 | channel = RX_GAIN,IN,in_voltage0_hardwaregain, 9 | channel = RX_RSSI,OUT,in_voltage0_rssi, 10 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 11 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 12 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 13 | -------------------------------------------------------------------------------- /hil_models/legacy/fmcomms4_data_stream/ad9364_sim.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/fmcomms4_data_stream/ad9364_sim.slx -------------------------------------------------------------------------------- /hil_models/legacy/fmcomms5_data_stream/ad9361-1.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-lpc 2 | data_out_device = cf-ad9361-A 3 | ctrl_device = ad9361-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 6 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 7 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 8 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 9 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 10 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 11 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 12 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 13 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 14 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 15 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 16 | -------------------------------------------------------------------------------- /hil_models/legacy/fmcomms5_data_stream/ad9361-2.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-B 2 | ctrl_device = ad9361-phy-B 3 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 4 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 5 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 6 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 7 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 8 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 9 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 10 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 11 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 12 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 13 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 14 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 15 | -------------------------------------------------------------------------------- /hil_models/legacy/fmcomms5_data_stream/fmcomms5.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/fmcomms5_data_stream/fmcomms5.slx -------------------------------------------------------------------------------- /hil_models/legacy/ieee80211_beacon_rx/ad9361.cfg: -------------------------------------------------------------------------------- 1 | data_out_device = cf-ad9361-lpc 2 | ctrl_device = ad9361-phy 3 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 4 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 5 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 6 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 7 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 8 | channel = RX1_RSSI,OUT,in_voltage0_rssi, -------------------------------------------------------------------------------- /hil_models/legacy/ieee80211_beacon_rx/wlan80211BeaconRx.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/ieee80211_beacon_rx/wlan80211BeaconRx.slx -------------------------------------------------------------------------------- /hil_models/legacy/ieee80211_beacon_rx/wlan80211BeaconRxInit.m: -------------------------------------------------------------------------------- 1 | function p80211 = wlan80211BeaconRxInit(agcStepSize, agcMaxGain, ... 2 | corrThreshold, sampsPerChip, chanNum) 3 | % wlan80211BeaconRxInit 802.11 Beacon Frame receiver parameters 4 | % p80211 = wlan80211BeaconRxInit(SZ,MG,TH,SPC,CHNUM) returns the 5 | % parameters required by the 802.11 Beacon Frame receiver 6 | % example, where SZ is AGC step size, MG is AGC maximum gain, TH is 7 | % synchronization threshold, SPC is samples per chip, and CHNUM is channel 8 | % number. 9 | % 10 | 11 | p80211 = commwlan80211BeaconRxInit(agcStepSize, agcMaxGain, ... 12 | corrThreshold, sampsPerChip); 13 | 14 | p80211.DecimationFactor = 4; 15 | p80211.ChannelNumber = chanNum; -------------------------------------------------------------------------------- /hil_models/legacy/qpsktxrx/ad9361.cfg: -------------------------------------------------------------------------------- 1 | data_in_device = cf-ad9361-dds-core-lpc 2 | data_out_device = cf-ad9361-lpc 3 | ctrl_device = ad9361-phy 4 | channel = RX_LO_FREQ,IN,out_altvoltage0_RX_LO_frequency, 5 | channel = RX_SAMPLING_FREQ,IN,in_voltage_sampling_frequency, 6 | channel = RX_RF_BANDWIDTH,IN,in_voltage_rf_bandwidth, 7 | channel = RX1_GAIN_MODE,IN,in_voltage0_gain_control_mode, 8 | channel = RX1_GAIN,IN,in_voltage0_hardwaregain, 9 | channel = RX1_RSSI,OUT,in_voltage0_rssi, 10 | channel = RX2_GAIN_MODE,IN,in_voltage1_gain_control_mode, 11 | channel = RX2_GAIN,IN,in_voltage1_hardwaregain, 12 | channel = RX2_RSSI,OUT,in_voltage1_rssi, 13 | channel = TX_LO_FREQ,IN,out_altvoltage1_TX_LO_frequency, 14 | channel = TX_SAMPLING_FREQ,IN,out_voltage_sampling_frequency, 15 | channel = TX_RF_BANDWIDTH,IN,out_voltage_rf_bandwidth, 16 | -------------------------------------------------------------------------------- /hil_models/legacy/qpsktxrx/qpsktxrx.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/qpsktxrx/qpsktxrx.slx -------------------------------------------------------------------------------- /hil_models/legacy/qpsktxrx/sdrqpskrx.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/qpsktxrx/sdrqpskrx.mat -------------------------------------------------------------------------------- /hil_models/legacy/qpsktxrx/sdrqpsktx.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/hil_models/legacy/qpsktxrx/sdrqpsktx.mat -------------------------------------------------------------------------------- /targeting_models/ADSB/AltVelCalc_ADI.m: -------------------------------------------------------------------------------- 1 | function [nv,ev,uv] = AltVelCalc_ADI(msg) 2 | % Calculate velocity data from message bits 3 | % Copyright 2010-2011, The MathWorks, Inc. 4 | 5 | % Calculate East-West velocity 6 | ewDir = msg(46); 7 | if ewDir == 0 8 | ed = 1; 9 | else 10 | ed = -1; 11 | end 12 | velBits = msg(47:56)'; 13 | ewVel = velBits*[512;256;128;64;32;16;8;4;2;1]-1; 14 | 15 | % Calculate North-South velocity 16 | nsDir = msg(57); 17 | if nsDir == 0 18 | nd = 1; 19 | else 20 | nd = -1; 21 | end 22 | velBits = msg(58:67)'; 23 | nsVel = velBits*[512;256;128;64;32;16;8;4;2;1]-1; 24 | 25 | % Calculate rate of climb/descent 26 | udDir = msg(69); 27 | if udDir == 0 28 | ud = 1; 29 | else 30 | ud = -1; 31 | end 32 | velBits = msg(70:78)'; 33 | udVel = (velBits*[256;128;64;32;16;8;4;2;1]-1)*64; 34 | 35 | nv = nd*nsVel; 36 | ev = ed*ewVel; 37 | uv = ud*udVel; 38 | 39 | 40 | -------------------------------------------------------------------------------- /targeting_models/ADSB/ModeS_ADI_Codegen.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/ADSB/ModeS_ADI_Codegen.slx -------------------------------------------------------------------------------- /targeting_models/ADSB/data_Yb.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/ADSB/data_Yb.mat -------------------------------------------------------------------------------- /targeting_models/ADSB/data_noise.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/ADSB/data_noise.mat -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/DecodeBits_ADI.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: DecodeBits_ADI.h 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | #ifndef __DECODEBITS_ADI_H__ 9 | #define __DECODEBITS_ADI_H__ 10 | 11 | /* Include Files */ 12 | #include 13 | #include 14 | #include 15 | #include "rtwtypes.h" 16 | #include "DecodeBits_ADI_types.h" 17 | 18 | /* Function Declarations */ 19 | extern void DecodeBits_ADI(const boolean_T bits[112], double currentLat, double 20 | currentLong, double *nV, double *eV, double *aV, double *alt, double *lat, 21 | double *b_long, char *type, double id[6]); 22 | 23 | #endif 24 | 25 | /* 26 | * File trailer for DecodeBits_ADI.h 27 | * 28 | * [EOF] 29 | */ 30 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/DecodeBits_ADI_initialize.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: DecodeBits_ADI_initialize.c 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | /* Include Files */ 9 | #include "DecodeBits_ADI.h" 10 | #include "DecodeBits_ADI_initialize.h" 11 | #include "LatLongCalcSingle_ADI.h" 12 | 13 | /* Function Definitions */ 14 | 15 | /* 16 | * Arguments : void 17 | * Return Type : void 18 | */ 19 | void DecodeBits_ADI_initialize(void) 20 | { 21 | NL_not_empty_init(); 22 | LatLongCalcSingle_ADI_init(); 23 | } 24 | 25 | /* 26 | * File trailer for DecodeBits_ADI_initialize.c 27 | * 28 | * [EOF] 29 | */ 30 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/DecodeBits_ADI_initialize.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: DecodeBits_ADI_initialize.h 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | #ifndef __DECODEBITS_ADI_INITIALIZE_H__ 9 | #define __DECODEBITS_ADI_INITIALIZE_H__ 10 | 11 | /* Include Files */ 12 | #include 13 | #include 14 | #include 15 | #include "rtwtypes.h" 16 | #include "DecodeBits_ADI_types.h" 17 | 18 | /* Function Declarations */ 19 | extern void DecodeBits_ADI_initialize(void); 20 | 21 | #endif 22 | 23 | /* 24 | * File trailer for DecodeBits_ADI_initialize.h 25 | * 26 | * [EOF] 27 | */ 28 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/DecodeBits_ADI_terminate.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: DecodeBits_ADI_terminate.c 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | /* Include Files */ 9 | #include "DecodeBits_ADI.h" 10 | #include "DecodeBits_ADI_terminate.h" 11 | 12 | /* Function Definitions */ 13 | 14 | /* 15 | * Arguments : void 16 | * Return Type : void 17 | */ 18 | void DecodeBits_ADI_terminate(void) 19 | { 20 | /* (no terminate code required) */ 21 | } 22 | 23 | /* 24 | * File trailer for DecodeBits_ADI_terminate.c 25 | * 26 | * [EOF] 27 | */ 28 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/DecodeBits_ADI_terminate.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: DecodeBits_ADI_terminate.h 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | #ifndef __DECODEBITS_ADI_TERMINATE_H__ 9 | #define __DECODEBITS_ADI_TERMINATE_H__ 10 | 11 | /* Include Files */ 12 | #include 13 | #include 14 | #include 15 | #include "rtwtypes.h" 16 | #include "DecodeBits_ADI_types.h" 17 | 18 | /* Function Declarations */ 19 | extern void DecodeBits_ADI_terminate(void); 20 | 21 | #endif 22 | 23 | /* 24 | * File trailer for DecodeBits_ADI_terminate.h 25 | * 26 | * [EOF] 27 | */ 28 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/DecodeBits_ADI_types.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: DecodeBits_ADI_types.h 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | #ifndef __DECODEBITS_ADI_TYPES_H__ 9 | #define __DECODEBITS_ADI_TYPES_H__ 10 | 11 | /* Include Files */ 12 | #include "rtwtypes.h" 13 | #endif 14 | 15 | /* 16 | * File trailer for DecodeBits_ADI_types.h 17 | * 18 | * [EOF] 19 | */ 20 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/LatLongCalcSingle_ADI.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: LatLongCalcSingle_ADI.h 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | #ifndef __LATLONGCALCSINGLE_ADI_H__ 9 | #define __LATLONGCALCSINGLE_ADI_H__ 10 | 11 | /* Include Files */ 12 | #include 13 | #include 14 | #include 15 | #include "rtwtypes.h" 16 | #include "DecodeBits_ADI_types.h" 17 | 18 | /* Function Declarations */ 19 | extern void LatLongCalcSingle_ADI(const boolean_T msg[112], double inputLat, 20 | double inputLong, double *Rlat, double *Rlon, double *alt); 21 | extern void LatLongCalcSingle_ADI_init(void); 22 | extern void NL_not_empty_init(void); 23 | 24 | #endif 25 | 26 | /* 27 | * File trailer for LatLongCalcSingle_ADI.h 28 | * 29 | * [EOF] 30 | */ 31 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/adsb_decode: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/ADSB/linux_app/adsb_decode -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/mrdivide.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: mrdivide.c 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | /* Include Files */ 9 | #include "DecodeBits_ADI.h" 10 | #include "mrdivide.h" 11 | 12 | /* Function Definitions */ 13 | 14 | /* 15 | * Arguments : const double B_data[] 16 | * Return Type : double 17 | */ 18 | double mrdivide(const double B_data[]) 19 | { 20 | return 1.0 / B_data[0] * 360.0; 21 | } 22 | 23 | /* 24 | * File trailer for mrdivide.c 25 | * 26 | * [EOF] 27 | */ 28 | -------------------------------------------------------------------------------- /targeting_models/ADSB/linux_app/mrdivide.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: mrdivide.h 3 | * 4 | * MATLAB Coder version : 2.8 5 | * C/C++ source code generated on : 10-Aug-2015 17:40:17 6 | */ 7 | 8 | #ifndef __MRDIVIDE_H__ 9 | #define __MRDIVIDE_H__ 10 | 11 | /* Include Files */ 12 | #include 13 | #include 14 | #include 15 | #include "rtwtypes.h" 16 | #include "DecodeBits_ADI_types.h" 17 | 18 | /* Function Declarations */ 19 | extern double mrdivide(const double B_data[]); 20 | 21 | #endif 22 | 23 | /* 24 | * File trailer for mrdivide.h 25 | * 26 | * [EOF] 27 | */ 28 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m: -------------------------------------------------------------------------------- 1 | function [rd, boardName] = hdlcoder_ref_design_customization 2 | % Reference design plugin registration file 3 | % 1. The registration file with this name inside of a board plugin folder 4 | % will be picked up 5 | % 2. Any registration file with this name on MATLAB path will also be picked up 6 | % 3. The registration file returns a cell array pointing to the location of 7 | % the reference design plugins 8 | % 4. The registration file also returns its associated board name 9 | % 5. Reference design plugin must be a package folder accessible from 10 | % MATLAB path, and contains a reference design definition file 11 | 12 | % Copyright 2013-2014 The MathWorks, Inc. 13 | 14 | rd = {'AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.plugin_rd', ... 15 | }; 16 | 17 | boardName = 'AnalogDevicesDemo adrv9361z7035 fmc lvds hop (Rx & Tx)'; 18 | 19 | end 20 | 21 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevices.adrv9361z7035.common.plugin_board('fmc lvds hop', 'Rx & Tx'); 9 | 10 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_rd.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevicesDemo.adrv9361z7035.common.plugin_rd('ccfmc_lvds_hop', 'Rx & Tx'); 8 | AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.add_rx_tx_io(hRD); -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/hdlcoder_ref_design_customization.m: -------------------------------------------------------------------------------- 1 | function [rd,boardName] = hdlcoder_ref_design_customization 2 | % Reference design plugin registration file 3 | % 1. The registration file with this name inside of a board plugin folder 4 | % will be picked up 5 | % 2. Any registration file with this name on MATLAB path will also be picked up 6 | % 3. The registration file returns a cell array pointing to the location of 7 | % the reference design plugins 8 | % 4. The registration file also returns its associated board name 9 | % 5. Reference design plugin must be a package folder accessible from 10 | % MATLAB path, and contains a reference design definition file 11 | 12 | % Copyright 2013-2014 The MathWorks, Inc. 13 | 14 | rd = {... 15 | 'AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.plugin_rd', ... 16 | }; 17 | 18 | boardName = 'AnalogDevices ADRV9361-Z7035 Frequency Hopping'; 19 | 20 | end 21 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hB = plugin_board() 2 | % Use Plugin API to create board plugin object 3 | 4 | % Copyright 2015 The MathWorks, Inc. 5 | 6 | hB = hdlcoder.Board; 7 | 8 | % Target Board Information 9 | hB.BoardName = sprintf('AnalogDevices ADRV9361-Z7035 Frequency Hopping'); 10 | 11 | % FPGA Device 12 | hB.FPGAVendor = 'Xilinx'; 13 | hB.FPGAFamily = 'Zynq'; 14 | 15 | % Determine the device based on the board 16 | hB.FPGADevice = sprintf('xc7%s', 'z035i'); 17 | hB.FPGAPackage = 'fbg676'; 18 | hB.FPGASpeed = '-2L'; 19 | 20 | 21 | % Tool Info 22 | hB.SupportedTool = {'Xilinx Vivado'}; 23 | 24 | % FPGA JTAG chain position 25 | hB.JTAGChainPosition = 2; 26 | 27 | %% Add interfaces 28 | % Standard "External Port" interface 29 | 30 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/adi_build.tcl: -------------------------------------------------------------------------------- 1 | # Build the project 2 | update_compile_order -fileset sources_1 3 | reset_run impl_1 4 | reset_run synth_1 5 | launch_runs synth_1 6 | wait_on_run synth_1 7 | launch_runs impl_1 -to_step write_bitstream 8 | wait_on_run impl_1 9 | 10 | # Define local variables 11 | set cdir [pwd] 12 | set sdk_loc vivado_prj.sdk 13 | 14 | # Export the hdf 15 | file delete -force $sdk_loc 16 | file mkdir $sdk_loc 17 | file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hdf 18 | 19 | # Close the Vivado project 20 | close_project 21 | 22 | # Create the BOOT.bin 23 | exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -wait 24 | 25 | puts "------------------------------------" 26 | puts "Embedded system build completed." 27 | puts "You may close this shell." 28 | puts "------------------------------------" 29 | exit 30 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/build_kernel.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Build kernel 4 | git clone https://github.com/analogdevicesinc/linux.git 5 | cd linux 6 | git checkout 2018_R2 7 | export ARCH=arm 8 | export CROSS_COMPILE=arm-linux-gnueabihf- 9 | source /opt/Xilinx/Vivado/2018.2/settings64.sh 10 | cp ../hopper.patch . 11 | git apply hopper.patch 12 | make zynq_xcomm_adv7511_defconfig 13 | make -j4 UIMAGE_LOADADDR=0x8000 uImage 14 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/u-boot.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/u-boot.elf -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {12}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M11_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M11_ARESETN] 5 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_hop 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/ccfmc_lvds_hop/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source $ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl 3 | source $ad_hdl_dir/projects/adrv9361z7035/common/ccfmc_bd.tcl 4 | 5 | cfg_ad9361_interface LVDS 6 | 7 | create_bd_port -dir O sys_cpu_clk_out 8 | ad_connect sys_cpu_clk sys_cpu_clk_out 9 | 10 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29 11 | 12 | # Add external pin for EN_AGC 13 | create_bd_port -dir O gpio_en_agc 14 | 15 | # Add external pins for CTRL_IN 16 | create_bd_port -from 0 -to 7 -dir I gpio_status 17 | 18 | # Add external pins for CTRL_OUT 19 | create_bd_port -from 0 -to 3 -dir O gpio_ctl -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/devicetree.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/frequency-hopping/devicetree.dtb -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/frequency_hopping.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/frequency-hopping/frequency_hopping.slx -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/hdlcoder_board_customization.m: -------------------------------------------------------------------------------- 1 | function r = hdlcoder_board_customization 2 | % Board plugin registration file 3 | % 1. Any registration file with this name on MATLAB path will be picked up 4 | % 2. Registration file returns a cell array pointing to the location of 5 | % the board plugins 6 | % 3. Board plugin must be a package folder accessible from MATLAB path, 7 | % and contains a board definition file 8 | 9 | % Copyright 2012-2013 The MathWorks, Inc. 10 | 11 | r = { ... 12 | 'AnalogDevicesDemo.adrv9361z7035.common.plugin_board', ... 13 | }; 14 | end 15 | % LocalWords: Zynq ZC 16 | -------------------------------------------------------------------------------- /targeting_models/frequency-hopping/hop_result.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/frequency-hopping/hop_result.bmp -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/FixedPoint/PlutoCaptureQPSK.bb: -------------------------------------------------------------------------------- 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Vivado project 20 | close_project 21 | 22 | # Create the BOOT.bin 23 | exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -wait 24 | 25 | puts "------------------------------------" 26 | puts "Embedded system build completed." 27 | puts "You may close this shell." 28 | puts "------------------------------------" 29 | exit 30 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/FixedPoint/demos/ADI_DMA_TT/combinedTxRx_ADIDMA.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/modem-qpsk/FixedPoint/demos/ADI_DMA_TT/combinedTxRx_ADIDMA.slx -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/FixedPoint/demos/External_Mode/Interface_Model.slx: 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Mean power 8 | cor = abs(filter(xPreamble(end:-1:1).',1,signal)); 9 | cor(1:preambleLength) = 0;% Remove invalid positions 10 | ind = find(cor./eng >= threshold, 1, 'first'); 11 | %stem(cor./eng); 12 | 13 | % The max should be at least X times the mean 14 | if sum(ind)>0 15 | % Correct to edge of preamble 16 | ind = ind(1) - preambleLength; 17 | frame = signal(ind+1:end); % Includes preamble 18 | % Get orientation 19 | phaseEst = round(angle(mean(conj(xPreamble) .* frame(1:preambleLength)))*2/pi)/2*pi; 20 | % Compensating for the phase offset 21 | frame = frame .* exp(-1i*phaseEst); 22 | else 23 | frame = []; 24 | end 25 | 26 | end 27 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/FloatingPoint/private/PacketDetector.m: -------------------------------------------------------------------------------- 1 | function [found, out] = PacketDetector(in, preamble) 2 | 3 | taps = preamble(end:-1:1); 4 | 5 | pLen = length(preamble); 6 | inDelayed = zeros(pLen,1); 7 | inBufferSQ = zeros(pLen,1); 8 | inBuffer = zeros(pLen,1); 9 | onesRow = ones(1,pLen); 10 | out = zeros(length(in),1); 11 | 12 | found = false; 13 | 14 | for i=1:length(in) 15 | 16 | inBuffer = [in(i); inBuffer(1:end-1)]; 17 | inBufferSQ = [abs(in(i))^2; inBufferSQ(1:end-1)]; 18 | if i>pLen 19 | inDelayed = [in(i-pLen); inDelayed(1:end-1)]; 20 | end 21 | squared = inBuffer.*inDelayed; 22 | 23 | sig = onesRow*squared; 24 | energy = onesRow*inBufferSQ; 25 | 26 | out(i) = abs(sig/energy); 27 | 28 | if out(i)>0.65 % Numerically found 29 | found = true; 30 | fprintf('Packet found\n'); 31 | return 32 | end 33 | 34 | end 35 | fprintf('Packet not found\n'); 36 | stem(out); 37 | 38 | end -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/FloatingPoint/private/QPSKDemoChannel.m: -------------------------------------------------------------------------------- 1 | function out = QPSKDemoChannel(in) 2 | 3 | DelayType = 'Triangle'; 4 | FilterSpan = 32; 5 | PhaseOffset = 45; 6 | FrameSize = 1000; 7 | UpSample = 4; 8 | EbNo = 13; 9 | BitsPerSymbol = 2; 10 | FrequencyOffset = 1000; 11 | Fs = 1e6; 12 | 13 | % Create and configure the AWGN channel System object 14 | qpskChan = QPSKChannel('DelayType', DelayType, ... 15 | 'RaisedCosineFilterSpan', FilterSpan, ... 16 | 'PhaseOffset', PhaseOffset, ... 17 | 'SignalPower', 1/UpSample, ... 18 | 'FrameSize', FrameSize, ... 19 | 'UpsamplingFactor', UpSample, ... 20 | 'EbNo', EbNo, ... 21 | 'BitsPerSymbol', BitsPerSymbol, ... 22 | 'FrequencyOffset', FrequencyOffset, ... 23 | 'SampleRate', Fs); 24 | 25 | frameCount = 10; 26 | out = qpskChan(in,frameCount); 27 | 28 | 29 | end -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/FloatingPoint/private/convertPhaseToFrequency.m: -------------------------------------------------------------------------------- 1 | function frequency = convertPhaseToFrequency(phase,fs,sps) 2 | factor = (fs/sps)/(2*pi); 3 | frequency = filter(ones(200,1)/200, 1, ... % Moving average 4 | diff(unwrap(phase(:)))*factor); 5 | end -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/README.md: -------------------------------------------------------------------------------- 1 | # modem-phy 2 | MATLAB/Simulink Physical layer design for QPSK wireless modem 3 | 4 | ### Run tests (Simulation only) 5 | `startup; cd('test'); testRunner;` 6 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/startup_adi_qpsk.m: -------------------------------------------------------------------------------- 1 | addpath('FixedPoint'); 2 | addpath('FloatingPoint'); 3 | addpath('utils'); 4 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/test/PlutoCaptureQPSK.bb: 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under: ',full,' or ',full1]); 21 | end 22 | end 23 | 24 | fid = fopen(full); 25 | str = textscan(fid, '%s'); 26 | str = strcat(str{1}{:}); 27 | %% 28 | if ~contains(str,'(VIOLATED)') 29 | disp('Passed Timing'); 30 | r = true; 31 | else 32 | disp('Failed Timing'); 33 | r = false; 34 | end 35 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/test/hdl_design/combinedTxRx.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/modem-qpsk/test/hdl_design/combinedTxRx.slx -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/test/linux/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CFLAGS=-std=c99 -pedantic -Wall -D_POSIX_SOURCE 3 | DEPS = mac.h reg.h 4 | OBJ = modemd.o mac.o test_dma.o reg.o 5 | prefix=/usr/local 6 | 7 | %.o: %.c $(DEPS) 8 | $(CC) $(CFLAGS) -c -o $@ $< 9 | 10 | modemd: $(OBJ) 11 | $(CC) $(CFLAGS) -pthread -o $@ mac.o modemd.o -lm 12 | 13 | test_dma: $(OBJ) 14 | $(CC) $(CFLAGS) -pthread -o $@ mac.o reg.o test_dma.o -lm 15 | 16 | install: 17 | install -m 0755 modemd $(prefix)/bin 18 | install -m 0777 restart_modem_gui.sh $(prefix)/bin 19 | install -m 0444 modem_filter.ftr $(prefix)/share/rfsom-box-gui 20 | clean: 21 | rm -rf test_dma modemd *.o 22 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/test/linux/mac.h: -------------------------------------------------------------------------------- 1 | #ifndef __MAC_H__ 2 | #define __MAC_H__ 3 | 4 | int32_t modem_reset(void); 5 | int32_t modem_setup(void); 6 | int32_t modem_start(void); 7 | int32_t modem_stop(void); 8 | int32_t modem_close(void); 9 | int32_t modem_running(void); 10 | int32_t modem_write(uint64_t* buf, uint32_t size, uint32_t cyclic); 11 | int32_t modem_read(uint64_t* buf, uint32_t size); 12 | 13 | #endif /*__MAC_H__ */ 14 | 15 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/test/linux/reg.h: -------------------------------------------------------------------------------- 1 | #ifndef __REG_H__ 2 | #define __REG_H__ 3 | 4 | int32_t reg_write(uint32_t reg_addr, uint32_t data); 5 | void defaults(int source, int loopbackmode); 6 | 7 | #endif /*__REG_H__ */ 8 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/test/utilmodels/rx.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/modem-qpsk/test/utilmodels/rx.slx -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/test/utilmodels/tx.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/modem-qpsk/test/utilmodels/tx.slx -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/utils/disableDebugBlocks.m: -------------------------------------------------------------------------------- 1 | function toggleDebugBlocks(modelname,turnOn) 2 | 3 | blocktypes = {'DEBUG'}; 4 | %blocktypes = {'Scope','Spectrum'}; 5 | 6 | allscopes = {}; 7 | % Get all scopes 8 | for block = blocktypes 9 | scopes = find_system(modelname,'CaseSensitive','off',... 10 | 'regexp','on','LookUnderMasks','all',... 11 | 'Name',block{:}); 12 | allscopes = {allscopes{:},scopes{:}}; 13 | end 14 | 15 | disp(allscopes); -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/utils/setupHDL.m: -------------------------------------------------------------------------------- 1 | 2 | v=ver('matlab'); Release = v.Release; 3 | switch Release 4 | case '(R2017a)' 5 | vivado = '2016.2'; 6 | case '(R2017b)' 7 | vivado = '2017.4'; 8 | case '(R2018b)' 9 | vivado = '2017.4'; 10 | end 11 | 12 | if ispc 13 | hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ... 14 | 'ToolPath', ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat']); 15 | elseif isunix 16 | hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ... 17 | 'ToolPath', ['/opt/Xilinx/Vivado/',vivado,'/bin/vivado']); 18 | end 19 | -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/utils/tileScopes.m: -------------------------------------------------------------------------------- 1 | 2 | function tileScopes(modelname) 3 | 4 | % tileScopes(bdroot) 5 | 6 | blocktypes = {'Constellation','Scope','Spectrum'}; 7 | %blocktypes = {'Scope','Spectrum'}; 8 | 9 | allscopes = {}; 10 | % Get all scopes 11 | for block = blocktypes 12 | scopes = find_system(modelname,'CaseSensitive','off',... 13 | 'regexp','on','LookUnderMasks','all',... 14 | 'blocktype',block{:}); 15 | allscopes = {allscopes{:},scopes{:}}; 16 | end 17 | num = numel(allscopes);screenBorder = 0.1; 18 | positions = getFigurePositions([ceil(sqrt(num)),ceil(sqrt(num))], screenBorder); 19 | 20 | for s = 1:num 21 | open_system(allscopes{s}); 22 | myConfiguration = get_param(allscopes{s},'ScopeConfiguration'); 23 | myConfiguration.Position = positions(s,:); 24 | 25 | end 26 | 27 | 28 | 29 | end -------------------------------------------------------------------------------- /targeting_models/modem-qpsk/utils/toggleDebugBlocks.m: -------------------------------------------------------------------------------- 1 | function toggleDebugBlocks(modelname,turnOn) 2 | 3 | % val=true (uncomment), val=false (comment) 4 | % toggleDebugBlocks(bdroot,val) 5 | 6 | keywords = {'DEBUG'}; % not case sensitive 7 | 8 | for block = keywords 9 | scopes = find_system(modelname,'CaseSensitive','off',... 10 | 'regexp','on','LookUnderMasks','all',... 11 | 'IncludeCommented','on','Name',block{:}); 12 | for scope = 1:length(scopes) 13 | if ~turnOn 14 | set_param(scopes{scope},'Commented','on') 15 | else 16 | set_param(scopes{scope},'Commented','off') 17 | end 18 | end 19 | end 20 | 21 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/+AnalogDevicesAGCDemo/+adrv9361z7035/+ccfmc_lvds_agc/+rx/hdlcoder_ref_design_customization.m: -------------------------------------------------------------------------------- 1 | function [rd, boardName] = hdlcoder_ref_design_customization 2 | % Reference design plugin registration file 3 | % 1. The registration file with this name inside of a board plugin folder 4 | % will be picked up 5 | % 2. Any registration file with this name on MATLAB path will also be picked up 6 | % 3. The registration file returns a cell array pointing to the location of 7 | % the reference design plugins 8 | % 4. The registration file also returns its associated board name 9 | % 5. Reference design plugin must be a package folder accessible from 10 | % MATLAB path, and contains a reference design definition file 11 | 12 | % Copyright 2013-2014 The MathWorks, Inc. 13 | 14 | rd = {'AnalogDevicesAGCDemo.adrv9361z7035.ccfmc_lvds_agc.rx.plugin_rd', ... 15 | }; 16 | 17 | boardName = 'AnalogDevices adrv9361z7035 fmc lvds agc (Rx)'; 18 | 19 | end -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/+AnalogDevicesAGCDemo/+adrv9361z7035/+ccfmc_lvds_agc/+rx/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hP = plugin_board() 2 | % Zynq Platform PCore 3 | % Use Plugin API to create board plugin object 4 | 5 | % Copyright 2015 The MathWorks, Inc. 6 | 7 | % Call the common board definition function 8 | hP = AnalogDevicesAGCDemo.adrv9361z7035.common.plugin_board('fmc lvds agc', 'Rx'); 9 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/+AnalogDevicesAGCDemo/+adrv9361z7035/+ccfmc_lvds_agc/+rx/plugin_rd.m: -------------------------------------------------------------------------------- 1 | function hRD = plugin_rd 2 | % Reference design definition 3 | 4 | % Copyright 2014-2015 The MathWorks, Inc. 5 | 6 | % Call the common reference design definition function 7 | hRD = AnalogDevicesAGCDemo.adrv9361z7035.common.plugin_rd('fmc lvds agc', 'Rx'); 8 | AnalogDevicesAGCDemo.adrv9361z7035.ccfmc_lvds_agc.rx.add_rx_io(hRD); -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/+AnalogDevicesAGCDemo/+adrv9361z7035/+common/hdlcoder_ref_design_customization.m: -------------------------------------------------------------------------------- 1 | function [rd,boardName] = hdlcoder_ref_design_customization 2 | % Reference design plugin registration file 3 | % 1. The registration file with this name inside of a board plugin folder 4 | % will be picked up 5 | % 2. Any registration file with this name on MATLAB path will also be picked up 6 | % 3. The registration file returns a cell array pointing to the location of 7 | % the reference design plugins 8 | % 4. The registration file also returns its associated board name 9 | % 5. Reference design plugin must be a package folder accessible from 10 | % MATLAB path, and contains a reference design definition file 11 | 12 | % Copyright 2013-2014 The MathWorks, Inc. 13 | 14 | rd = {... 15 | 'AnalogDevicesAGCDemo.adrv9361z7035.ccfmc_lvds_agc.rx.plugin_rd', ... 16 | }; 17 | 18 | boardName = 'AnalogDevices ADRV9361-Z7035 AGC'; 19 | 20 | end -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/+AnalogDevicesAGCDemo/+adrv9361z7035/+common/plugin_board.m: -------------------------------------------------------------------------------- 1 | function hB = plugin_board() 2 | % Use Plugin API to create board plugin object 3 | 4 | % Copyright 2015 The MathWorks, Inc. 5 | 6 | hB = hdlcoder.Board; 7 | 8 | % Target Board Information 9 | hB.BoardName = sprintf('AnalogDevices ADRV9361-Z7035 AGC'); 10 | 11 | % FPGA Device 12 | hB.FPGAVendor = 'Xilinx'; 13 | hB.FPGAFamily = 'Zynq'; 14 | 15 | % Determine the device based on the board 16 | hB.FPGADevice = sprintf('xc7%s', 'z035i'); 17 | hB.FPGAPackage = 'fbg676'; 18 | hB.FPGASpeed = '-2L'; 19 | 20 | 21 | % Tool Info 22 | hB.SupportedTool = {'Xilinx Vivado'}; 23 | 24 | % FPGA JTAG chain position 25 | hB.JTAGChainPosition = 2; 26 | 27 | %% Add interfaces 28 | % Standard "External Port" interface 29 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ModeS_testbench.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/tuneAGC-ad9361/ModeS_testbench.slx -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ad9361_rx_wlan_testbench.slx: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/boot/u-boot.elf -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/boot/uEnv.txt: -------------------------------------------------------------------------------- 1 | uenvcmd=run adi_sdboot 2 | adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi 3 | bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait 4 | 5 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/boot/zynq.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf 4 | ./vivado_prj.sdk/hw_0/system_top.bit 5 | ./boot/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/config_prj.tcl: -------------------------------------------------------------------------------- 1 | # Add 1 extra AXI master ports to the interconnect 2 | set_property -dict [list CONFIG.NUM_MI {12}] [get_bd_cells axi_cpu_interconnect] 3 | connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M11_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] 4 | connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M11_ARESETN] 5 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/config_rx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | 7 | # Configure DMA 8 | set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma] 9 | connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins util_ad9361_divclk/clk_out] 10 | connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data] 11 | connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] [get_bd_pins util_ad9361_adc_pack/adc_valid] 12 | 13 | regenerate_bd_layout -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/config_rx_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl 6 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 7 | 8 | regenerate_bd_layout -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/config_tx.tcl: -------------------------------------------------------------------------------- 1 | set ad_hdl_dir [pwd] 2 | set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc 3 | 4 | source $proj_dir/config_prj.tcl 5 | source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl 6 | 7 | regenerate_bd_layout -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/ccfmc_lvds_agc/system_bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | source $ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl 3 | source $ad_hdl_dir/projects/adrv9361z7035/common/ccfmc_bd.tcl 4 | 5 | cfg_ad9361_interface LVDS 6 | 7 | create_bd_port -dir O sys_cpu_clk_out 8 | ad_connect sys_cpu_clk sys_cpu_clk_out 9 | 10 | ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29 11 | 12 | # Add external pin for EN_AGC 13 | create_bd_port -dir O gpio_en_agc 14 | 15 | 16 | # Add external pin for EN_AGC 17 | create_bd_port -from 0 -to 7 -dir I gpio_status 18 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/hdlcoder_board_customization.m: -------------------------------------------------------------------------------- 1 | function r = hdlcoder_board_customization 2 | % Board plugin registration file 3 | % 1. Any registration file with this name on MATLAB path will be picked up 4 | % 2. Registration file returns a cell array pointing to the location of 5 | % the board plugins 6 | % 3. Board plugin must be a package folder accessible from MATLAB path, 7 | % and contains a board definition file 8 | 9 | % Copyright 2012-2013 The MathWorks, Inc. 10 | 11 | r = { ... 12 | 'AnalogDevicesAGCDemo.adrv9361z7035.common.plugin_board', ... 13 | }; 14 | end 15 | % LocalWords: Zynq ZC -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/reg/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CFLAGS=-std=c99 -pedantic -Wall -D_POSIX_SOURCE 3 | DEPS = reg.h 4 | OBJ = reg.o 5 | prefix=/usr/local 6 | 7 | %.o: %.c $(DEPS) 8 | $(CC) $(CFLAGS) -c -o $@ $< 9 | 10 | reg: $(OBJ) 11 | $(CC) $(CFLAGS) -pthread -o $@ reg.o -lm 12 | 13 | 14 | install: 15 | install -m 0755 modemd $(prefix)/bin 16 | install -m 0777 restart_modem_gui.sh $(prefix)/bin 17 | install -m 0444 modem_filter.ftr $(prefix)/share/rfsom-box-gui 18 | clean: 19 | rm -rf reg *.o 20 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/reg/reg.h: -------------------------------------------------------------------------------- 1 | #ifndef __REG_H__ 2 | #define __REG_H__ 3 | 4 | int32_t reg_write(uint32_t reg_addr, uint32_t data); 5 | 6 | #endif /*__REG_H__ */ 7 | -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/support/lltf.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/targeting_models/tuneAGC-ad9361/support/lltf.mat -------------------------------------------------------------------------------- /targeting_models/tuneAGC-ad9361/support/offline.m: -------------------------------------------------------------------------------- 1 | function [numDataSym] = offline(cfgNonHT) 2 | 3 | mcsTable = wlan.internal.getRateTable(cfgNonHT); 4 | Ntail = 6; Nservice = 16; 5 | numDataSym = ceil((8*cfgNonHT.PSDULength + Nservice + Ntail)/mcsTable.NDBPS); 6 | -------------------------------------------------------------------------------- /test/BSPTests.m: -------------------------------------------------------------------------------- 1 | classdef BSPTests < BSPTestsBase 2 | 3 | methods(TestClassSetup) 4 | function removeinstalledbsp(~) 5 | str = 'Analog Devices Board Support Packages'; 6 | ts = matlab.addons.toolbox.installedToolboxes; 7 | for t = ts 8 | if contains(t.Name,str) 9 | disp('Removing installed BSP'); 10 | matlab.addons.toolbox.uninstallToolbox(t); 11 | end 12 | end 13 | end 14 | % Add the necessary files to path 15 | function addbspfiles(~) 16 | addpath(genpath('../hdl_wa_bsp')); 17 | end 18 | end 19 | 20 | end 21 | -------------------------------------------------------------------------------- /test/SysObjsTests.m: -------------------------------------------------------------------------------- 1 | classdef SysObjsTests < AD9361Tests & AD9363Tests & AD9364Tests 2 | 3 | 4 | end 5 | 6 | -------------------------------------------------------------------------------- /test/graphicalInstaller.m: -------------------------------------------------------------------------------- 1 | workflow = adi.ADIWorkFlow; 2 | workflow.launch -------------------------------------------------------------------------------- /test/perf/hwTestRunner.m: -------------------------------------------------------------------------------- 1 | import matlab.unittest.plugins.DiagnosticsRecordingPlugin 2 | import matlab.unittest.plugins.TestReportPlugin 3 | 4 | runner = matlab.unittest.TestRunner.withNoPlugins; 5 | runner.addPlugin(DiagnosticsRecordingPlugin); 6 | runner.addPlugin(TestReportPlugin.producingPDF('Report.pdf',... 7 | 'IncludingPassingDiagnostics',true,'IncludingCommandWindowText',true)); 8 | runner.ArtifactsRootFolder = pwd; 9 | 10 | suite = testsuite('HardwarePerformanceTests'); 11 | 12 | if ~exist('logs', 'dir') 13 | mkdir('logs') 14 | end 15 | 16 | results = runner.run(suite); 17 | t = table(results); 18 | disp(t); 19 | 20 | exit(any([results.Failed])); 21 | -------------------------------------------------------------------------------- /test/runHWTests.m: -------------------------------------------------------------------------------- 1 | import matlab.unittest.TestRunner; 2 | import matlab.unittest.TestSuite; 3 | import matlab.unittest.plugins.TestReportPlugin; 4 | import matlab.unittest.plugins.XMLPlugin 5 | 6 | try 7 | suite = testsuite({'AD9361Tests','AD9363Tests','AD9364Tests'... 8 | 'AD9371Tests','ADRV9009Tests','DAQ2Tests'}); 9 | runner = TestRunner.withNoPlugins; 10 | xmlFile = 'HWTestResults.xml'; 11 | plugin = XMLPlugin.producingJUnitFormat(xmlFile); 12 | 13 | runner.addPlugin(plugin); 14 | results = runner.run(suite); 15 | 16 | t = table(results); 17 | disp(t); 18 | disp(repmat('#',1,80)); 19 | for test = results 20 | if test.Failed 21 | disp(test.Name); 22 | end 23 | end 24 | catch e 25 | disp(getReport(e,'extended')); 26 | bdclose('all'); 27 | exit(1); 28 | end 29 | save(['BSPTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t'); 30 | bdclose('all'); 31 | exit(any([results.Failed])); 32 | -------------------------------------------------------------------------------- /test/testModel.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/test/testModel.slx -------------------------------------------------------------------------------- /test/testModel_Rx16Tx32.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/test/testModel_Rx16Tx32.slx -------------------------------------------------------------------------------- /test/testModel_Tx32.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/MathWorks_tools/5f8df06d4fc2f4832ed9ec8b722fb750b2261f20/test/testModel_Tx32.slx --------------------------------------------------------------------------------