├── .gitattributes ├── .gitignore ├── LICENSE ├── LICENSE_ADIBSD ├── LICENSE_GPL2 ├── LICENSE_LGPL ├── README.md ├── cf_ad9361_ml605 ├── SDK │ └── SDK_Export │ │ └── hw │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── system.mhs └── system.xmp ├── cf_ad9361_zc702 ├── SDK │ └── SDK_Export │ │ └── hw │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ └── system.ucf ├── docs │ └── cf_ad9361_zc702_bd.jpg ├── license.txt ├── system.mhs └── system.xmp ├── cf_ad9361_zc706 ├── SDK │ └── SDK_Export │ │ └── hw │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ ├── system.ucf │ └── system.xdc ├── docs │ └── cf_ad9361_zc706_bd.jpg ├── license.txt ├── system.mhs └── system.xmp ├── cf_ad9361_zed ├── SDK │ └── SDK_Export │ │ └── hw │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ └── system.ucf ├── docs │ └── cf_ad9361_zed_bd.jpg ├── license.txt ├── system.mhs └── system.xmp ├── cf_adv7511_ac701 ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_adv7511_kc705 ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_adv7511_vc707 ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_adv7511_zc702 ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_adv7511_zc706 ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ ├── system.ucf │ └── system.xdc ├── license.txt ├── system.mhs └── system.xmp ├── cf_adv7511_zed ├── .gitignore ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_imageon_zed ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_lib └── edk │ └── pcores │ ├── adi_common_v1_00_a │ ├── data │ │ ├── adi_common_v2_1_0.pao │ │ └── generate_ngc_and_v.tcl │ ├── docs │ │ ├── adi_regmap.html │ │ ├── adi_regmap_adc.h │ │ ├── adi_regmap_adc.txt │ │ ├── adi_regmap_axis.h │ │ ├── adi_regmap_axis.txt │ │ ├── adi_regmap_clkgen.h │ │ ├── adi_regmap_clkgen.txt │ │ ├── adi_regmap_common.h │ │ ├── adi_regmap_common.txt │ │ ├── adi_regmap_dac.h │ │ ├── adi_regmap_dac.txt │ │ ├── adi_regmap_ddr_cntrl.h │ │ ├── adi_regmap_ddr_cntrl.txt │ │ ├── adi_regmap_fft.h │ │ ├── adi_regmap_fft.txt │ │ ├── adi_regmap_hdmi.h │ │ ├── adi_regmap_hdmi.txt │ │ ├── adi_regmap_jesd.h │ │ ├── adi_regmap_jesd.txt │ │ └── adi_regmap_wiki.txt │ ├── hdl │ │ ├── verilog │ │ │ ├── ad_axis_dma_rx.v │ │ │ ├── ad_axis_dma_tx.v │ │ │ ├── ad_axis_inf_rx.v │ │ │ ├── ad_csc_1.v │ │ │ ├── ad_csc_1_add.v │ │ │ ├── ad_csc_1_mul.v │ │ │ ├── ad_csc_CrYCb2RGB.v │ │ │ ├── ad_csc_RGB2CrYCb.v │ │ │ ├── ad_datafmt.v │ │ │ ├── ad_dcfilter.v │ │ │ ├── ad_gt_channel_1.v │ │ │ ├── ad_gt_common_1.v │ │ │ ├── ad_gt_es.v │ │ │ ├── ad_gtv6_channel_1.v │ │ │ ├── ad_intp2_16.v │ │ │ ├── ad_intp2_2.v │ │ │ ├── ad_intp2_4.v │ │ │ ├── ad_intp2_8.v │ │ │ ├── ad_iqcor.v │ │ │ ├── ad_jesd_align.v │ │ │ ├── ad_jesd_cntrl.v │ │ │ ├── ad_mac_1.v │ │ │ ├── ad_mem.v │ │ │ ├── ad_mmcm_drp.v │ │ │ ├── ad_mul_u16.v │ │ │ ├── ad_serdes_clk.v │ │ │ ├── ad_serdes_out.v │ │ │ ├── ad_sine.v │ │ │ ├── ad_ss_422to444.v │ │ │ ├── ad_ss_444to422.v │ │ │ ├── axis_inf.v │ │ │ ├── cf_adc_dma.v │ │ │ ├── cf_adc_dma_256.v │ │ │ ├── cf_adc_regmap.v │ │ │ ├── cf_csc_1.v │ │ │ ├── cf_csc_1_add.v │ │ │ ├── cf_csc_1_mul.v │ │ │ ├── cf_csc_CrYCb2RGB.v │ │ │ ├── cf_csc_RGB2CrYCb.v │ │ │ ├── cf_gtx_es_if.v │ │ │ ├── cf_gtx_es_wr.v │ │ │ ├── cf_iqcor.v │ │ │ ├── cf_iqcor_1.v │ │ │ ├── cf_jesd_align_1.v │ │ │ ├── cf_jesd_align_2.v │ │ │ ├── cf_jesd_mon.v │ │ │ ├── cf_jesd_regmap.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_mul_u16.v │ │ │ ├── cf_ss_422to444.v │ │ │ ├── cf_ss_444to422.v │ │ │ ├── dma_core.v │ │ │ ├── mem.v │ │ │ ├── mul_u16.v │ │ │ ├── sync_bits.v │ │ │ ├── sync_flag.v │ │ │ ├── sync_gray.v │ │ │ ├── up_adc_channel.v │ │ │ ├── up_adc_common.v │ │ │ ├── up_axi.v │ │ │ ├── up_axis_dma_rx.v │ │ │ ├── up_axis_dma_tx.v │ │ │ ├── up_busif.v │ │ │ ├── up_clkgen.v │ │ │ ├── up_dac_channel.v │ │ │ ├── up_dac_common.v │ │ │ ├── up_ddr_cntrl.v │ │ │ ├── up_fft.v │ │ │ ├── up_hdmi_tx.v │ │ │ ├── up_jesd.v │ │ │ └── vdma_core.v │ │ └── vhdl │ │ │ ├── axi_ctrlif.vhd │ │ │ ├── axi_streaming_dma_rx_fifo.vhd │ │ │ ├── axi_streaming_dma_tx_fifo.vhd │ │ │ ├── axi_upif.vhd │ │ │ ├── dma_fifo.vhd │ │ │ └── pl330_dma_fifo.vhd │ └── netlist │ │ ├── ad_dcfilter_1.xco │ │ ├── ad_dds_1.xco │ │ └── ad_mul_dsp48_1.xco │ ├── axi_ad7091_v1_00_a │ ├── data │ │ ├── axi_ad7091_v2_1_0.mpd │ │ └── axi_ad7091_v2_1_0.pao │ ├── hdl │ │ └── verilog │ │ │ ├── axi_ad7091.v │ │ │ └── axi_ad7091_dev_if.v │ └── regmap.txt │ ├── axi_ad7091r_v1_00_a │ ├── data │ │ ├── axi_ad7091r_v2_1_0.bbd │ │ ├── axi_ad7091r_v2_1_0.mpd │ │ ├── axi_ad7091r_v2_1_0.pao │ │ └── axi_ad7091r_v2_1_0.tcl │ ├── hdl │ │ └── verilog │ │ │ ├── axi_ad7091r.v │ │ │ └── axi_ad7091r_dev_if.v │ └── regmap.txt │ ├── axi_ad7980_v1_00_a │ ├── data │ │ ├── axi_ad7980_v2_1_0.bbd │ │ ├── axi_ad7980_v2_1_0.mpd │ │ ├── axi_ad7980_v2_1_0.pao │ │ └── axi_ad7980_v2_1_0.tcl │ ├── hdl │ │ └── verilog │ │ │ ├── axi_ad7980.v │ │ │ └── axi_ad7980_dev_if.v │ └── regmap.txt │ ├── axi_ad9122_v6_00_a │ ├── data │ │ ├── axi_ad9122_v2_1_0.bbd │ │ ├── axi_ad9122_v2_1_0.mpd │ │ ├── axi_ad9122_v2_1_0.pao │ │ └── axi_ad9122_v2_1_0.tcl │ └── hdl │ │ └── verilog │ │ ├── axi_ad9122.v │ │ ├── axi_ad9122_channel.v │ │ ├── axi_ad9122_core.v │ │ ├── axi_ad9122_dds.v │ │ └── axi_ad9122_if.v │ ├── axi_ad9361_v1_00_a │ ├── axi_ad9361.cdc │ ├── axi_ad9361_adc.cdc │ ├── data │ │ ├── axi_ad9361_v2_1_0.bbd │ │ ├── axi_ad9361_v2_1_0.mpd │ │ ├── axi_ad9361_v2_1_0.pao │ │ └── axi_ad9361_v2_1_0.tcl │ ├── hdl │ │ └── verilog │ │ │ ├── axi_ad9361.v │ │ │ ├── axi_ad9361_dev_if.v │ │ │ ├── axi_ad9361_pnlb.v │ │ │ ├── axi_ad9361_rx.v │ │ │ ├── axi_ad9361_rx_channel.v │ │ │ ├── axi_ad9361_rx_pnmon.v │ │ │ ├── axi_ad9361_tx.v │ │ │ ├── axi_ad9361_tx_channel.v │ │ │ └── axi_ad9361_tx_dds.v │ └── regmap.txt │ ├── axi_ad9434_v1_00_a │ ├── data │ │ ├── axi_ad9434_v2_1_0.mpd │ │ └── axi_ad9434_v2_1_0.pao │ └── hdl │ │ └── verilog │ │ ├── axi_ad9434.v │ │ ├── axi_ad9434_channel.v │ │ ├── axi_ad9434_if.v │ │ └── axi_ad9434_pnmon.v │ ├── axi_ad9643_v6_00_a │ ├── data │ │ ├── axi_ad9643_v2_1_0.bbd │ │ ├── axi_ad9643_v2_1_0.mpd │ │ ├── axi_ad9643_v2_1_0.pao │ │ └── axi_ad9643_v2_1_0.tcl │ └── hdl │ │ └── verilog │ │ ├── axi_ad9643.v │ │ ├── axi_ad9643_channel.v │ │ ├── axi_ad9643_if.v │ │ └── axi_ad9643_pnmon.v │ ├── axi_ad9649_v1_00_a │ ├── data │ │ ├── axi_ad9649_v2_1_0.mpd │ │ └── axi_ad9649_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_ad9649.v │ │ │ ├── cf_adc_if.v │ │ │ ├── cf_adc_wr.v │ │ │ ├── cf_dma_wr.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_pnmon.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_ad9649.vhd │ └── regmap.txt │ ├── axi_adc_1c_v1_00_a │ ├── data │ │ ├── _axi_adc_1c_xst.prj │ │ ├── axi_adc_1c_v2_1_0.mpd │ │ └── axi_adc_1c_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_adc_1c.v │ │ │ ├── cf_adc_if.v │ │ │ ├── cf_adc_wr.v │ │ │ ├── cf_dma_wr.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_pnmon.v │ │ │ ├── cf_spi.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_adc_1c.vhd │ └── regmap.txt │ ├── axi_adc_2c_v1_00_a │ ├── data │ │ ├── _axi_adc_2c_xst.prj │ │ ├── axi_adc_2c_v2_1_0.bbd │ │ ├── axi_adc_2c_v2_1_0.mpd │ │ └── axi_adc_2c_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_adc_2c.v │ │ │ ├── cf_adc_if.v │ │ │ ├── cf_adc_wr.v │ │ │ ├── cf_dcfilter.v │ │ │ ├── cf_dma_wr.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_muladd.v │ │ │ ├── cf_pnmon.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_adc_2c.vhd │ ├── netlist │ │ └── cf_dcfilter_1.xco │ └── regmap.txt │ ├── axi_adc_8c_v1_00_a │ ├── data │ │ ├── _axi_adc_8c_xst.prj │ │ ├── axi_adc_8c_v2_1_0.mpd │ │ └── axi_adc_8c_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_adc_8c.v │ │ │ ├── cf_adc_if.v │ │ │ ├── cf_adc_if_1.v │ │ │ ├── cf_dma_wr.v │ │ │ ├── cf_mem.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_adc_8c.vhd │ └── regmap.txt │ ├── axi_axis_xx_v1_00_a │ ├── data │ │ ├── axi_axis_xx_v2_1_0.mpd │ │ └── axi_axis_xx_v2_1_0.pao │ └── hdl │ │ └── verilog │ │ ├── axi_axis_rx_core.v │ │ ├── axi_axis_tx_core.v │ │ └── axi_axis_xx.v │ ├── axi_clkgen_v1_00_a │ ├── data │ │ ├── _axi_clkgen_xst.prj │ │ ├── axi_clkgen_v2_1_0.mpd │ │ └── axi_clkgen_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_clkgen.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_clkgen.vhd │ └── regmap.txt │ ├── axi_clkgen_v2_00_a │ ├── data │ │ ├── axi_clkgen_v2_1_0.mpd │ │ └── axi_clkgen_v2_1_0.pao │ └── hdl │ │ └── verilog │ │ └── axi_clkgen.v │ ├── axi_dac_1c_2p_f_v1_00_a │ ├── data │ │ ├── _axi_dac_1c_2p_f_xst.prj │ │ ├── axi_dac_1c_2p_f_v2_1_0.bbd │ │ ├── axi_dac_1c_2p_f_v2_1_0.mpd │ │ └── axi_dac_1c_2p_f_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_dac_1c_2p_f.v │ │ │ ├── cf_dac_if.v │ │ │ ├── cf_dds_top.v │ │ │ ├── cf_ddsv.v │ │ │ ├── cf_ddsx.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_spi.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_dac_1c_2p_f.vhd │ └── regmap.txt │ ├── axi_dac_1c_2p_v1_00_a │ ├── data │ │ ├── _axi_dac_1c_2p_xst.prj │ │ ├── axi_dac_1c_2p_v2_1_0.bbd │ │ ├── axi_dac_1c_2p_v2_1_0.mpd │ │ ├── axi_dac_1c_2p_v2_1_0.pao │ │ └── axi_dac_1c_2p_v2_1_0.tcl │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_dac_1c_2p.v │ │ │ ├── cf_dac_if.v │ │ │ ├── cf_dds_top.v │ │ │ ├── cf_ddsv.v │ │ │ ├── cf_ddsv_intp.v │ │ │ ├── cf_ddsv_intp_1.v │ │ │ ├── cf_ddsv_vdma.v │ │ │ ├── cf_ddsx.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_muls.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_dac_1c_2p.vhd │ ├── netlist │ │ └── cf_ddsx_1.xco │ └── regmap.txt │ ├── axi_dac_4d_2c_v1_00_a │ ├── data │ │ ├── _axi_dac_4d_2c_xst.prj │ │ ├── axi_dac_4d_2c_v2_1_0.bbd │ │ ├── axi_dac_4d_2c_v2_1_0.mpd │ │ ├── axi_dac_4d_2c_v2_1_0.pao │ │ └── axi_dac_4d_2c_v2_1_0.tcl │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_dac_4d_2c.v │ │ │ ├── cf_dac_if.v │ │ │ ├── cf_dds_top.v │ │ │ ├── cf_ddsv.v │ │ │ ├── cf_ddsv_intp.v │ │ │ ├── cf_ddsv_intp_1.v │ │ │ ├── cf_ddsv_vdma.v │ │ │ ├── cf_ddsx.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_muls.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_dac_4d_2c.vhd │ ├── netlist │ │ ├── cf_ddsv_intp4x_1.xco │ │ └── cf_ddsx_1.xco │ └── regmap.txt │ ├── axi_dmac_v1_00_a │ ├── data │ │ ├── axi_dmac_v2_1_0.mpd │ │ └── axi_dmac_v2_1_0.pao │ └── hdl │ │ └── verilog │ │ ├── 2d_transfer.v │ │ ├── address_generator.v │ │ ├── axi_dmac.v │ │ ├── axi_register_slice.v │ │ ├── axi_repack.v │ │ ├── data_mover.v │ │ ├── dest_axi_mm.v │ │ ├── dest_axi_stream.v │ │ ├── dest_fifo_inf.v │ │ ├── inc_id.v │ │ ├── request_arb.v │ │ ├── request_generator.v │ │ ├── resp.h │ │ ├── resp.v │ │ ├── response_generator.v │ │ ├── response_handler.v │ │ ├── splitter.v │ │ ├── src_axi_mm.v │ │ ├── src_axi_stream.v │ │ └── src_fifo_inf.v │ ├── axi_fft_v1_00_a │ ├── data │ │ ├── axi_fft_v2_1_0.bbd │ │ ├── axi_fft_v2_1_0.mpd │ │ ├── axi_fft_v2_1_0.pao │ │ └── axi_fft_v2_1_0.tcl │ ├── hdl │ │ └── verilog │ │ │ ├── axi_fft.v │ │ │ ├── axi_fft_core.v │ │ │ ├── axi_fft_mon.v │ │ │ └── axi_fft_win.v │ ├── netlist │ │ ├── axi_fft_fix2floatx_1.xco │ │ ├── axi_fft_float2fixx_1.xco │ │ ├── axi_fft_float4k_fftx_1.xco │ │ ├── axi_fft_float64k_fftx_1.xco │ │ ├── axi_fft_floataddx_1.xco │ │ ├── axi_fft_floatmulx_1.xco │ │ └── axi_fft_floatsqrtx_1.xco │ └── regmap.txt │ ├── axi_fifo_v1_00_a │ ├── data │ │ ├── axi_fifo_v2_1_0.mpd │ │ └── axi_fifo_v2_1_0.pao │ └── hdl │ │ └── verilog │ │ ├── address_gray.v │ │ ├── address_gray_pipelined.v │ │ ├── address_sync.v │ │ └── axi_fifo.v │ ├── axi_hdmi_16b_es_v1_00_a │ ├── data │ │ ├── _axi_hdmi_16b_es_xst.prj │ │ ├── axi_hdmi_16b_es_v2_1_0.mpd │ │ └── axi_hdmi_16b_es_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_h2v.v │ │ │ ├── cf_h2v_hdmi.v │ │ │ ├── cf_h2v_vdma.v │ │ │ ├── cf_hdmi_16b_es.v │ │ │ ├── cf_v2h.v │ │ │ ├── cf_v2h_hdmi.v │ │ │ ├── cf_v2h_vdma.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_hdmi_16b_es.vhd │ └── regmap.txt │ ├── axi_hdmi_rx_v1_00_a │ ├── data │ │ ├── axi_hdmi_rx_v2_1_0.mpd │ │ └── axi_hdmi_rx_v2_1_0.pao │ └── hdl │ │ └── verilog │ │ ├── axi_hdmi_rx.v │ │ ├── axi_hdmi_rx_core.v │ │ └── embedded_sync_decoder.v │ ├── axi_hdmi_tx_16b_v1_00_a │ ├── data │ │ ├── _axi_hdmi_tx_16b_xst.prj │ │ ├── axi_hdmi_tx_16b_v2_1_0.mpd │ │ └── axi_hdmi_tx_16b_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_add.v │ │ │ ├── cf_csc_1.v │ │ │ ├── cf_csc_RGB2CrYCb.v │ │ │ ├── cf_hdmi.v │ │ │ ├── cf_hdmi_tx_16b.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_mul.v │ │ │ ├── cf_ss_444to422.v │ │ │ ├── cf_vdma.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_hdmi_tx_16b.vhd │ └── regmap.txt │ ├── axi_hdmi_tx_36b_v1_00_a │ ├── data │ │ ├── _axi_hdmi_tx_36b_xst.prj │ │ ├── axi_hdmi_tx_36b_v2_1_0.mpd │ │ └── axi_hdmi_tx_36b_v2_1_0.pao │ ├── hdl │ │ ├── verilog │ │ │ ├── cf_hdmi.v │ │ │ ├── cf_hdmi_tx_36b.v │ │ │ ├── cf_mem.v │ │ │ ├── cf_vdma.v │ │ │ └── user_logic.v │ │ └── vhdl │ │ │ └── axi_hdmi_tx_36b.vhd │ └── regmap.txt │ ├── axi_hdmi_tx_v1_00_a │ ├── data │ │ ├── axi_hdmi_tx_v2_1_0.mpd │ │ └── axi_hdmi_tx_v2_1_0.pao │ └── hdl │ │ └── verilog │ │ ├── axi_hdmi_tx.v │ │ ├── axi_hdmi_tx_core.v │ │ └── axi_hdmi_tx_vdma.v │ ├── axi_i2s_adi_v1_00_a │ ├── data │ │ ├── _axi_i2s_adi_xst.prj │ │ ├── axi_i2s_adi_v2_1_0.mpd │ │ └── axi_i2s_adi_v2_1_0.pao │ └── hdl │ │ └── vhdl │ │ ├── axi_i2s_adi.vhd │ │ ├── fifo_synchronizer.vhd │ │ ├── i2s_clkgen.vhd │ │ ├── i2s_controller.vhd │ │ ├── i2s_rx.vhd │ │ └── i2s_tx.vhd │ ├── axi_spdif_rx_v1_00_a │ ├── data │ │ ├── axi_spdif_rx_v2_1_0.mpd │ │ └── axi_spdif_rx_v2_1_0.pao │ └── hdl │ │ └── vhdl │ │ ├── axi_spdif_rx.vhd │ │ ├── gen_control_reg.vhd │ │ ├── gen_event_reg.vhd │ │ ├── rx_cap_reg.vhd │ │ ├── rx_decode.vhd │ │ ├── rx_package.vhd │ │ ├── rx_phase_det.vhd │ │ ├── rx_spdif.vhd │ │ ├── rx_status_reg.vhd │ │ ├── rx_ver_reg.vhd │ │ ├── rx_wb_decoder.vhd │ │ └── user_logic.vhd │ ├── axi_spdif_tx_v1_00_a │ ├── data │ │ ├── axi_spdif_tx_v2_1_0.mpd │ │ └── axi_spdif_tx_v2_1_0.pao │ └── hdl │ │ └── vhdl │ │ ├── axi_spdif_tx.vhd │ │ ├── tx_encoder.vhd │ │ └── tx_package.vhd │ ├── util_hdmi_tx_24b_v1_00_a │ ├── data │ │ ├── util_hdmi_tx_24b_v2_1_0.mpd │ │ └── util_hdmi_tx_24b_v2_1_0.pao │ └── hdl │ │ └── vhdl │ │ └── util_hdmi_tx_24b.vhd │ ├── util_i2c_mixer_v1_00_a │ ├── data │ │ ├── util_i2c_mixer_v2_1_0.mpd │ │ └── util_i2c_mixer_v2_1_0.pao │ └── hdl │ │ └── vhdl │ │ └── util_i2c_mixer.vhd │ ├── util_outclk_lvds_v1_00_a │ ├── data │ │ ├── util_outclk_lvds_v2_1_0.mpd │ │ └── util_outclk_lvds_v2_1_0.pao │ └── hdl │ │ └── vhdl │ │ └── util_outclk_lvds.vhd │ └── util_spi_3w_v1_00_a │ ├── data │ ├── util_spi_3w_v2_1_0.mpd │ └── util_spi_3w_v2_1_0.pao │ └── hdl │ └── vhdl │ └── util_spi_3w.vhd ├── cf_sdp_adc └── cf_ad7091_ac701 │ ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld │ ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ ├── DDR3_pinout.ucf │ └── system.ucf │ ├── license.txt │ ├── system.mhs │ └── system.xmp ├── cf_sdp_kc705 ├── .gitattributes ├── .gitignore ├── SDK │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_xcomm ├── .gitignore ├── SDK │ ├── SDK_Export │ │ └── hw │ │ │ ├── system.bit │ │ │ ├── system.xml │ │ │ └── system_bd.bmm │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_xcomm_kc705 ├── .gitignore ├── SDK │ ├── SDK_Export │ │ └── hw │ │ │ ├── system.xml │ │ │ └── system_bd.bmm │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── docs │ ├── cf_xcomm_kc705_bd.jpg │ └── cf_xcomm_kc705_bd.vsd ├── license.txt ├── system.mhs └── system.xmp ├── cf_xcomm_vc707 ├── .gitignore ├── SDK │ ├── SDK_Export │ │ └── hw │ │ │ ├── system.xml │ │ │ └── system_bd.bmm │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── system.bit │ │ ├── system.xml │ │ └── system_bd.bmm │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── DDR3_SDRAM_mig_saved.prj │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_xcomm_zc702 ├── .gitignore ├── SDK │ ├── SDK_Export │ │ └── hw │ │ │ ├── ps7_init.c │ │ │ ├── ps7_init.h │ │ │ ├── ps7_init.tcl │ │ │ ├── system.bit │ │ │ └── system.xml │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp ├── cf_xcomm_zc706 ├── .gitignore ├── SDK │ ├── SDK_Export │ │ └── hw │ │ │ ├── ps7_init.c │ │ │ ├── ps7_init.h │ │ │ ├── ps7_init.tcl │ │ │ ├── system.bit │ │ │ └── system.xml │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ ├── system.ucf │ └── system.xdc ├── license.txt ├── system.mhs └── system.xmp ├── cf_xcomm_zed ├── .gitignore ├── SDK │ ├── SDK_Export │ │ └── hw │ │ │ ├── ps7_init.c │ │ │ ├── ps7_init.h │ │ │ ├── ps7_init.tcl │ │ │ ├── system.bit │ │ │ └── system.xml │ └── SDK_Workspace │ │ ├── bsp │ │ ├── .cproject │ │ ├── .project │ │ ├── .sdkproject │ │ ├── Makefile │ │ ├── libgen.options │ │ └── system.mss │ │ ├── hw │ │ ├── .project │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ ├── system.bit │ │ └── system.xml │ │ └── sw │ │ ├── .cproject │ │ ├── .project │ │ └── src │ │ └── lscript.ld ├── data │ ├── ps7_constraints.ucf │ ├── ps7_constraints.xdc │ ├── ps7_system_prj.xml │ └── system.ucf ├── license.txt ├── system.mhs └── system.xmp └── motor_control └── adi_zed_ise_rev2 ├── ADI_ZED_ISE.gise ├── ADI_ZED_ISE.xise ├── Chipscope └── motor_control_ref.cpj ├── ad7401_c2.v ├── debouncer.v ├── dec256sinc24b.v ├── freq_divider.v ├── impact.ipf ├── ipcore_dir ├── _xmsgs │ ├── cg.xmsgs │ └── xst.xmsgs ├── chipscope_icon.asy ├── chipscope_icon.constraints │ ├── chipscope_icon.ucf │ └── chipscope_icon.xdc ├── chipscope_icon.gise ├── chipscope_icon.ncf ├── chipscope_icon.ngc ├── chipscope_icon.sym ├── chipscope_icon.ucf ├── chipscope_icon.vhd ├── chipscope_icon.vho ├── chipscope_icon.xco ├── chipscope_icon.xdc ├── chipscope_icon.xise ├── chipscope_icon_flist.txt ├── chipscope_icon_xmdf.tcl ├── chipscope_ila.asy ├── chipscope_ila.cdc ├── chipscope_ila.constraints │ ├── chipscope_ila.ucf │ └── chipscope_ila.xdc ├── chipscope_ila.gise ├── chipscope_ila.ncf ├── chipscope_ila.ngc ├── chipscope_ila.sym ├── chipscope_ila.ucf ├── chipscope_ila.vhd ├── chipscope_ila.vho ├── chipscope_ila.xco ├── chipscope_ila.xdc ├── chipscope_ila.xise ├── chipscope_ila2.asy ├── chipscope_ila2.cdc ├── chipscope_ila2.constraints │ ├── chipscope_ila2.ucf │ └── chipscope_ila2.xdc ├── chipscope_ila2.gise ├── chipscope_ila2.ncf ├── chipscope_ila2.ngc ├── chipscope_ila2.sym ├── chipscope_ila2.ucf ├── chipscope_ila2.vhd ├── chipscope_ila2.vho ├── chipscope_ila2.xco ├── chipscope_ila2.xdc ├── chipscope_ila2.xise ├── chipscope_ila2_flist.txt ├── chipscope_ila2_xmdf.tcl ├── chipscope_ila_flist.txt ├── chipscope_ila_xmdf.tcl ├── chipscope_vio.asy ├── chipscope_vio.cdc ├── chipscope_vio.constraints │ ├── chipscope_vio.ucf │ └── chipscope_vio.xdc ├── chipscope_vio.gise ├── chipscope_vio.ncf ├── chipscope_vio.ngc ├── chipscope_vio.sym ├── chipscope_vio.ucf ├── chipscope_vio.vhd ├── chipscope_vio.vho ├── chipscope_vio.xco ├── chipscope_vio.xdc ├── chipscope_vio.xise ├── chipscope_vio_flist.txt ├── chipscope_vio_xmdf.tcl ├── chipsope_ila2.asy ├── chipsope_ila2.cdc ├── chipsope_ila2.constraints │ ├── chipsope_ila2.ucf │ └── chipsope_ila2.xdc ├── chipsope_ila2.gise ├── chipsope_ila2.ncf ├── chipsope_ila2.ngc ├── chipsope_ila2.sym ├── chipsope_ila2.ucf ├── chipsope_ila2.vhd ├── chipsope_ila2.vho ├── chipsope_ila2.xco ├── chipsope_ila2.xdc ├── chipsope_ila2.xise ├── chipsope_ila2_flist.txt ├── chipsope_ila2_readme.txt ├── chipsope_ila2_xmdf.tcl ├── clock_gen.asy ├── clock_gen.gise ├── clock_gen.sym ├── clock_gen.ucf ├── clock_gen.v ├── clock_gen.veo ├── clock_gen.vhd ├── clock_gen.vho ├── clock_gen.xci ├── clock_gen.xco ├── clock_gen.xdc ├── clock_gen.xise ├── clock_gen.xml ├── clock_gen │ ├── clk_wiz_v3_6_readme.txt │ ├── doc │ │ ├── clk_wiz_v3_6_readme.txt │ │ ├── clk_wiz_v3_6_vinfo.html │ │ └── pg065_clk_wiz.pdf │ ├── example_design │ │ ├── clock_gen_exdes.ucf │ │ ├── clock_gen_exdes.v │ │ ├── clock_gen_exdes.vhd │ │ └── clock_gen_exdes.xdc │ ├── implement │ │ ├── implement.bat │ │ ├── implement.sh │ │ ├── planAhead_ise.bat │ │ ├── planAhead_ise.sh │ │ ├── planAhead_ise.tcl │ │ ├── planAhead_rdn.bat │ │ ├── planAhead_rdn.sh │ │ ├── planAhead_rdn.tcl │ │ ├── xst.prj │ │ └── xst.scr │ └── simulation │ │ ├── clock_gen_tb.v │ │ ├── clock_gen_tb.vhd │ │ ├── functional │ │ ├── simcmds.tcl │ │ ├── simulate_isim.bat │ │ ├── simulate_isim.sh │ │ ├── simulate_mti.bat │ │ ├── simulate_mti.do │ │ ├── simulate_mti.sh │ │ ├── simulate_ncsim.sh │ │ ├── simulate_vcs.sh │ │ ├── ucli_commands.key │ │ ├── vcs_session.tcl │ │ ├── wave.do │ │ └── wave.sv │ │ └── timing │ │ ├── clock_gen_tb.v │ │ ├── clock_gen_tb.vhd │ │ ├── sdf_cmd_file │ │ ├── simcmds.tcl │ │ ├── simulate_isim.sh │ │ ├── simulate_mti.bat │ │ ├── simulate_mti.do │ │ ├── simulate_mti.sh │ │ ├── simulate_ncsim.sh │ │ ├── simulate_vcs.sh │ │ ├── ucli_commands.key │ │ ├── vcs_session.tcl │ │ └── wave.do ├── clock_gen_exdes.ncf ├── clock_gen_flist.txt ├── clock_gen_xmdf.tcl ├── coregen.cgp ├── create_chipscope_icon.tcl ├── create_chipscope_ila.tcl ├── create_chipscope_ila2.tcl ├── create_chipscope_vio.tcl ├── create_chipsope_ila2.tcl ├── create_clock_gen.tcl ├── edit_chipscope_icon.tcl ├── edit_chipscope_ila.tcl ├── edit_chipscope_ila2.tcl ├── edit_chipscope_vio.tcl ├── edit_chipsope_ila2.tcl ├── edit_clock_gen.tcl ├── gen_chipscope_ila.tcl ├── gen_clock_gen.tcl └── tmp │ ├── _xmsgs │ └── pn_parser.xmsgs │ ├── customization_gui.0.120093951989.out │ ├── customization_gui.0.380243128343.out │ ├── customization_gui.0.505241257839.out │ └── customization_gui.0.881266026237.out ├── iseconfig ├── ADI_ZED_ISE.projectmgr ├── current_sensor.xreport └── top.xreport ├── motor_driver.v ├── speed_detector.v ├── system.ucf ├── top.bit └── top.vhd /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/analogdevicesinc/fpgahdl_xilinx/HEAD/.gitattributes -------------------------------------------------------------------------------- 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