├── .gitignore ├── LICENSE ├── TODO.txt ├── firmware ├── cortex-m3 │ ├── qmake.conf │ ├── qplatformdefs.h │ └── stm32f103c8.ld ├── cortex-m4 │ ├── qmake.conf │ ├── qplatformdefs.h │ └── stm32f429xx.ld ├── fw_cpu │ ├── Makefile │ ├── fw_cpu.pro │ ├── fw_cpu.pro.user │ ├── inc │ │ ├── plc_bus.h │ │ ├── plc_conf.h │ │ ├── plc_control.h │ │ ├── plc_data_interface.h │ │ ├── plc_data_types.h │ │ ├── plc_fw.h │ │ ├── plc_hw.h │ │ ├── plc_io.h │ │ ├── plc_mod.h │ │ ├── plc_platform.h │ │ ├── plc_state.h │ │ └── stl_commands.h │ ├── platforms │ │ └── stm32 │ │ │ ├── diskio.h │ │ │ ├── diskiodriver.h │ │ │ ├── fatfs.cpp │ │ │ ├── fatfs.h │ │ │ ├── ffconf.h │ │ │ ├── init.cpp │ │ │ ├── init.h │ │ │ ├── memmanager.cpp │ │ │ ├── memmanager.h │ │ │ ├── sddriver.cpp │ │ │ ├── sddriver.h │ │ │ ├── stm32_conf.h │ │ │ ├── stm32_flash.cpp │ │ │ ├── stm32_flash.h │ │ │ ├── stm32_gpio.cpp │ │ │ ├── stm32_gpio.h │ │ │ ├── stm32_inc.h │ │ │ ├── stm32_nvic.cpp │ │ │ ├── stm32_nvic.h │ │ │ ├── stm32_pwr.cpp │ │ │ ├── stm32_pwr.h │ │ │ ├── stm32_rcc.cpp │ │ │ ├── stm32_rcc.h │ │ │ ├── stm32_rtc.cpp │ │ │ ├── stm32_rtc.h │ │ │ ├── stm32_sd.cpp │ │ │ ├── stm32_sd.h │ │ │ ├── stm32_sdram.cpp │ │ │ ├── stm32_sdram.h │ │ │ ├── stm32_spi.cpp │ │ │ ├── stm32_spi.h │ │ │ ├── stm32_systick.cpp │ │ │ ├── stm32_systick.h │ │ │ ├── stm32_uart.cpp │ │ │ ├── stm32_uart.h │ │ │ ├── xprintf.cpp │ │ │ └── xprintf.h │ └── src │ │ ├── main.cpp │ │ ├── plc_bus.cpp │ │ ├── plc_control.cpp │ │ ├── plc_data_types.cpp │ │ ├── plc_fw.cpp │ │ ├── plc_hw.cpp │ │ ├── plc_io.cpp │ │ ├── plc_mod.cpp │ │ ├── plc_platform.cpp │ │ ├── plc_state.cpp │ │ └── stl_commands.cpp ├── fw_di16 │ ├── fw_di16.ioc │ ├── fw_di16.pro │ ├── inc │ │ ├── main.h │ │ ├── plc_conf.h │ │ ├── plc_mod_info.h │ │ ├── stm32f1xx_hal_conf.h │ │ └── stm32f1xx_it.h │ ├── init.cpp │ ├── main.cpp │ ├── src │ │ ├── main.cpp │ │ ├── stm32f1xx_hal_msp.c │ │ └── stm32f1xx_it.c │ ├── stm32_conf.h │ └── system_stm32f10x.h └── shared │ ├── CMSIS │ ├── ISRstm32f429xx.cpp │ ├── ISRstm32f429xx.h │ ├── arm_common_tables.h │ ├── arm_const_structs.h │ ├── arm_math.h │ ├── cmsis_armcc.h │ ├── cmsis_armcc_V6.h │ ├── cmsis_gcc.h │ ├── core_cm0.h │ ├── core_cm0plus.h │ ├── core_cm3.h │ ├── core_cm4.h │ ├── core_cm7.h │ ├── core_cmFunc.h │ ├── core_cmInstr.h │ ├── core_cmSimd.h │ ├── core_sc000.h │ ├── core_sc300.h │ ├── startup_stm32f103xb.s │ ├── stm32f100xb.h │ ├── stm32f103xb.h │ ├── stm32f1xx.h │ ├── stm32f429xx.h │ ├── stm32f4xx.h │ ├── system_stm32f1xx.c │ ├── system_stm32f1xx.h │ └── system_stm32f4xx.h │ ├── HAL │ ├── inc │ │ ├── Legacy │ │ │ └── stm32_hal_legacy.h │ │ ├── stm32f1xx_hal.h │ │ ├── stm32f1xx_hal_cortex.h │ │ ├── stm32f1xx_hal_def.h │ │ ├── stm32f1xx_hal_dma.h │ │ ├── stm32f1xx_hal_dma_ex.h │ │ ├── stm32f1xx_hal_flash.h │ │ ├── stm32f1xx_hal_flash_ex.h │ │ ├── stm32f1xx_hal_gpio.h │ │ ├── stm32f1xx_hal_gpio_ex.h │ │ ├── stm32f1xx_hal_iwdg.h │ │ ├── stm32f1xx_hal_pwr.h │ │ ├── stm32f1xx_hal_rcc.h │ │ ├── stm32f1xx_hal_rcc_ex.h │ │ ├── stm32f1xx_hal_spi.h │ │ ├── stm32f1xx_hal_tim.h │ │ └── stm32f1xx_hal_tim_ex.h │ └── src │ │ ├── stm32f1xx_hal.c │ │ ├── stm32f1xx_hal_cortex.c │ │ ├── stm32f1xx_hal_dma.c │ │ ├── stm32f1xx_hal_flash.c │ │ ├── stm32f1xx_hal_flash_ex.c │ │ ├── stm32f1xx_hal_gpio.c │ │ ├── stm32f1xx_hal_gpio_ex.c │ │ ├── stm32f1xx_hal_iwdg.c │ │ ├── stm32f1xx_hal_pwr.c │ │ ├── stm32f1xx_hal_rcc.c │ │ ├── stm32f1xx_hal_rcc_ex.c │ │ ├── stm32f1xx_hal_spi.c │ │ ├── stm32f1xx_hal_spi_ex.c │ │ ├── stm32f1xx_hal_tim.c │ │ └── stm32f1xx_hal_tim_ex.c │ ├── Third_Party │ └── FatFs │ │ └── src │ │ ├── ff.c │ │ ├── ff.h │ │ ├── integer.h │ │ └── option │ │ ├── ccsbcs.c │ │ ├── syscall.c │ │ └── unicode.c │ ├── inc │ ├── ISRstm32f10x_md.h │ ├── bitbanding.h │ ├── my_func.h │ └── plc_mod.h │ └── src │ ├── ISRstm32f10x_md.cpp │ ├── my_func.cpp │ └── plc_mod.cpp ├── hardware ├── hw_cpu │ ├── hw_cpu-cache.lib │ ├── hw_cpu-rescue.lib │ ├── hw_cpu.cmp │ ├── hw_cpu.kicad_pcb │ ├── hw_cpu.net │ ├── hw_cpu.pro │ └── hw_cpu.sch ├── hw_cross │ ├── cross-cache.lib │ ├── cross.kicad_pcb │ ├── cross.net │ ├── cross.pro │ └── cross.sch ├── hw_di16 │ ├── module_di-cache.lib │ ├── module_di-rescue.lib │ ├── module_di.cmp │ ├── module_di.kicad_pcb │ ├── module_di.net │ ├── module_di.pro │ └── module_di.sch ├── hw_do16 │ ├── module_do-cache.lib │ ├── module_do-rescue.lib │ ├── module_do.cmp │ ├── module_do.kicad_pcb │ ├── module_do.net │ ├── module_do.pro │ └── module_do.sch └── hw_mod_cross │ ├── mod_cross-cache.lib │ ├── mod_cross.kicad_pcb │ ├── mod_cross.net │ ├── mod_cross.pro │ └── mod_cross.sch ├── runtime ├── datainterface.h ├── firmware_sample │ ├── firmware.cpp │ ├── firmware.h │ ├── fwdb.cpp │ └── fwdb.h ├── include │ ├── alt_vip_vfr_vga.h │ ├── hps.h │ ├── hps_0.h │ ├── hps_0_arm_a9_0.h │ ├── hps_0_arm_a9_1.h │ ├── hps_0_bridges.h │ ├── master_non_sec.h │ └── master_secure.h ├── main.cpp ├── plcbus.cpp ├── plcbus.h ├── plcdata.cpp ├── plcdata.h ├── plcstate.cpp ├── plcstate.h ├── runtime.cpp ├── runtime.h ├── runtime.pro └── settings.h └── stlc ├── CmdlineParser.cpp ├── CmdlineParser.h ├── Stream.cpp ├── Stream.h ├── example ├── prog.stl └── test.stl ├── main.cpp ├── stlc.cpp ├── stlc.h └── stlc.pro /.gitignore: -------------------------------------------------------------------------------- 1 | 1/* 2 | 3 | #Qt-Creator files 4 | build-* 5 | *.user* 6 | 7 | #Gerber files 8 | *.gbr 9 | *.drl 10 | 11 | *.*bak 12 | *.zip 13 | 14 | -------------------------------------------------------------------------------- /TODO.txt: -------------------------------------------------------------------------------- 1 | Hardware: 2 | 1) Исправить разводку светодиодов RUN/STOP; 3 | 2) Подключить сигнал CARD_DETECT к МК; 4 | 3) Исправить посадочное место переключателя RUN/STOP; 5 | 4) 6 | 7 | Software: 8 | 1) Перевести шину на аппаратный режим NSS; 9 | 2) Переход в STOP: 10 | * Выставить флаг перехода в STOP; 11 | * Подождать завершения текущего цикла; 12 | * Подождать оконцания записи в NAND и SD; 13 | * Выставить флаг состояния STOP; 14 | * Ждать снятия сигнала STOP. 15 | 3) 16 | -------------------------------------------------------------------------------- /firmware/cortex-m3/qmake.conf: -------------------------------------------------------------------------------- 1 | # 2 | # qmake configuration for Cortex-M3 SoC 3 | # 4 | # Written for MinGW / gcc 4.6 or higher 5 | 6 | load(device_config) 7 | 8 | MAKEFILE_GENERATOR = UNIX 9 | QMAKE_PLATFORM = linux win32 mingw 10 | CONFIG += debug_and_release debug_and_release_target precompile_header 11 | 12 | QMAKE_EXT_OBJ = .o 13 | QMAKE_EXT_RES = _res.o 14 | 15 | QMAKE_COMPILER = gcc 16 | 17 | QMAKE_CC = arm-none-eabi-gcc 18 | QMAKE_LEX = flex 19 | QMAKE_LEXFLAGS = 20 | QMAKE_YACC = bison -y 21 | QMAKE_YACCFLAGS = -d 22 | QMAKE_CFLAGS = -mcpu=cortex-m3 -mthumb -Os -fdata-sections -ffunction-sections 23 | QMAKE_CFLAGS_DEPS = -M 24 | QMAKE_CFLAGS_WARN_ON = -Wall -Wextra 25 | QMAKE_CFLAGS_WARN_OFF = -w 26 | QMAKE_CFLAGS_RELEASE = -O2 27 | QMAKE_CFLAGS_RELEASE_WITH_DEBUGINFO = -Os -g 28 | QMAKE_CFLAGS_DEBUG = -g 29 | QMAKE_CFLAGS_YACC = -Wno-unused -Wno-parentheses 30 | QMAKE_CFLAGS_SPLIT_SECTIONS = -ffunction-sections 31 | 32 | QMAKE_CXX = arm-none-eabi-g++ 33 | QMAKE_CXXFLAGS = $$QMAKE_CFLAGS -fno-unwind-tables -fno-exceptions 34 | QMAKE_CXXFLAGS_DEPS = $$QMAKE_CFLAGS_DEPS 35 | QMAKE_CXXFLAGS_WARN_ON = $$QMAKE_CFLAGS_WARN_ON 36 | QMAKE_CXXFLAGS_WARN_OFF = $$QMAKE_CFLAGS_WARN_OFF 37 | QMAKE_CXXFLAGS_RELEASE = $$QMAKE_CFLAGS_RELEASE 38 | QMAKE_CXXFLAGS_DEBUG = $$QMAKE_CFLAGS_DEBUG 39 | QMAKE_CXXFLAGS_YACC = $$QMAKE_CFLAGS_YACC 40 | QMAKE_CXXFLAGS_THREAD = $$QMAKE_CFLAGS_THREAD 41 | QMAKE_CXXFLAGS_CXX11 = -std=c++0x 42 | QMAKE_CXXFLAGS_CXX14 = -std=c++1y 43 | QMAKE_CXXFLAGS_CXX1Z = -std=c++1z 44 | QMAKE_CXXFLAGS_GNUCXX11 = -std=gnu++0x 45 | QMAKE_CXXFLAGS_GNUCXX14 = -std=gnu++1y 46 | QMAKE_CXXFLAGS_GNUCXX1Z = -std=gnu++1z 47 | QMAKE_CXXFLAGS_SPLIT_SECTIONS = $$QMAKE_CFLAGS_SPLIT_SECTIONS 48 | 49 | QMAKE_INCDIR = 50 | 51 | QMAKE_RUN_CC = $(CC) -c $(CFLAGS) $(INCPATH) -o $obj $src 52 | QMAKE_RUN_CC_IMP = $(CC) -c $(CFLAGS) $(INCPATH) -o $@ $< 53 | QMAKE_RUN_CXX = $(CXX) -c $(CXXFLAGS) $(INCPATH) -o $obj $src 54 | QMAKE_RUN_CXX_IMP = $(CXX) -c $(CXXFLAGS) $(INCPATH) -o $@ $< 55 | 56 | QMAKE_LINK = arm-none-eabi-ld 57 | QMAKE_LINK_C = arm-none-eabi-ld 58 | QMAKE_LFLAGS = 59 | QMAKE_LFLAGS_RELEASE = $$QMAKE_LFLAGS -s 60 | QMAKE_LFLAGS_DEBUG = $$QMAKE_LFLAGS 61 | QMAKE_LFLAGS_CXX11 = 62 | QMAKE_LFLAGS_CXX14 = 63 | QMAKE_LFLAGS_CXX1Z = 64 | QMAKE_LFLAGS_GCSECTIONS = -Wl,--gc-sections 65 | QMAKE_LINK_OBJECT_MAX = 10 66 | QMAKE_LINK_OBJECT_SCRIPT = object_script 67 | 68 | QMAKE_LIBS = -lgcc 69 | 70 | QMAKE_IDL = midl 71 | QMAKE_LIB = arm-none-eabi-ar -rc 72 | 73 | QMAKE_STRIP = arm-none-eabi-strip 74 | QMAKE_STRIPFLAGS_LIB += --strip-unneeded 75 | QMAKE_OBJCOPY = arm-none-eabi-objcopy 76 | QMAKE_NM = arm-none-eabi-nm -P 77 | load(qt_config) 78 | -------------------------------------------------------------------------------- /firmware/cortex-m3/qplatformdefs.h: -------------------------------------------------------------------------------- 1 | #ifndef QPLATFORMDEFS_H 2 | #define QPLATFORMDEFS_H 3 | 4 | 5 | #endif // QPLATFORMDEFS_H 6 | -------------------------------------------------------------------------------- /firmware/cortex-m4/qmake.conf: -------------------------------------------------------------------------------- 1 | # 2 | # qmake configuration for Cortex-M4 SoC 3 | # 4 | # Written for MinGW / gcc 4.6 or higher 5 | 6 | load(device_config) 7 | 8 | MAKEFILE_GENERATOR = UNIX 9 | QMAKE_PLATFORM = linux win32 mingw 10 | CONFIG += debug_and_release debug_and_release_target precompile_header 11 | 12 | QMAKE_EXT_OBJ = .o 13 | QMAKE_EXT_RES = _res.o 14 | 15 | QMAKE_COMPILER = gcc 16 | 17 | QMAKE_CC = arm-none-eabi-gcc 18 | QMAKE_LEX = flex 19 | QMAKE_LEXFLAGS = 20 | QMAKE_YACC = bison -y 21 | QMAKE_YACCFLAGS = -d 22 | QMAKE_CFLAGS = -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -fdata-sections -ffunction-sections 23 | QMAKE_CFLAGS_DEPS = -M 24 | QMAKE_CFLAGS_WARN_ON = -Wall -Wextra 25 | QMAKE_CFLAGS_WARN_OFF = -w 26 | QMAKE_CFLAGS_RELEASE = -Os 27 | QMAKE_CFLAGS_RELEASE_WITH_DEBUGINFO = -Os -g 28 | QMAKE_CFLAGS_DEBUG = -g 29 | QMAKE_CFLAGS_YACC = -Wno-unused -Wno-parentheses 30 | QMAKE_CFLAGS_SPLIT_SECTIONS = -ffunction-sections 31 | 32 | QMAKE_CXX = arm-none-eabi-g++ 33 | QMAKE_CXXFLAGS = $$QMAKE_CFLAGS -fno-unwind-tables -fno-exceptions 34 | QMAKE_CXXFLAGS_DEPS = $$QMAKE_CFLAGS_DEPS 35 | QMAKE_CXXFLAGS_WARN_ON = $$QMAKE_CFLAGS_WARN_ON 36 | QMAKE_CXXFLAGS_WARN_OFF = $$QMAKE_CFLAGS_WARN_OFF 37 | QMAKE_CXXFLAGS_RELEASE = $$QMAKE_CFLAGS_RELEASE 38 | QMAKE_CXXFLAGS_DEBUG = $$QMAKE_CFLAGS_DEBUG 39 | QMAKE_CXXFLAGS_YACC = $$QMAKE_CFLAGS_YACC 40 | QMAKE_CXXFLAGS_THREAD = $$QMAKE_CFLAGS_THREAD 41 | QMAKE_CXXFLAGS_CXX11 = -std=c++0x 42 | QMAKE_CXXFLAGS_CXX14 = -std=c++1y 43 | QMAKE_CXXFLAGS_CXX1Z = -std=c++1z 44 | QMAKE_CXXFLAGS_GNUCXX11 = -std=gnu++0x 45 | QMAKE_CXXFLAGS_GNUCXX14 = -std=gnu++1y 46 | QMAKE_CXXFLAGS_GNUCXX1Z = -std=gnu++1z 47 | QMAKE_CXXFLAGS_SPLIT_SECTIONS = $$QMAKE_CFLAGS_SPLIT_SECTIONS 48 | 49 | QMAKE_INCDIR = 50 | 51 | QMAKE_RUN_CC = $(CC) -c $(CFLAGS) $(INCPATH) -o $obj $src 52 | QMAKE_RUN_CC_IMP = $(CC) -c $(CFLAGS) $(INCPATH) -o $@ $< 53 | QMAKE_RUN_CXX = $(CXX) -c $(CXXFLAGS) $(INCPATH) -o $obj $src 54 | QMAKE_RUN_CXX_IMP = $(CXX) -c $(CXXFLAGS) $(INCPATH) -o $@ $< 55 | 56 | QMAKE_LINK = arm-none-eabi-ld 57 | QMAKE_LINK_C = arm-none-eabi-ld 58 | QMAKE_LFLAGS = --gc-sections 59 | QMAKE_LFLAGS_RELEASE = $$QMAKE_LFLAGS -s 60 | QMAKE_LFLAGS_DEBUG = $$QMAKE_LFLAGS 61 | QMAKE_LFLAGS_CXX11 = 62 | QMAKE_LFLAGS_CXX14 = 63 | QMAKE_LFLAGS_CXX1Z = 64 | QMAKE_LFLAGS_GCSECTIONS = -Wl,--gc-sections 65 | QMAKE_LINK_OBJECT_MAX = 10 66 | QMAKE_LINK_OBJECT_SCRIPT = object_script 67 | 68 | QMAKE_LIBS = /usr/arm-none-eabi/lib/fpu/libc.a /usr/lib/gcc/arm-none-eabi/7.1.0/fpu/libgcc.a 69 | #QMAKE_LIBS = `$(CC) -print-libgcc-file-name | sed 's/libgcc/fpu\/libstdc++/'` /usr/arm-none-eabi/lib/fpu/libc.a -lgcc 70 | 71 | QMAKE_IDL = midl 72 | QMAKE_LIB = arm-none-eabi-ar -rc 73 | 74 | QMAKE_STRIP = arm-none-eabi-strip 75 | QMAKE_STRIPFLAGS_LIB += --strip-unneeded 76 | QMAKE_OBJCOPY = arm-none-eabi-objcopy 77 | QMAKE_NM = arm-none-eabi-nm -P 78 | load(qt_config) 79 | -------------------------------------------------------------------------------- /firmware/cortex-m4/qplatformdefs.h: -------------------------------------------------------------------------------- 1 | #ifndef QPLATFORMDEFS_H 2 | #define QPLATFORMDEFS_H 3 | 4 | 5 | #endif // QPLATFORMDEFS_H 6 | -------------------------------------------------------------------------------- /firmware/fw_cpu/Makefile: -------------------------------------------------------------------------------- 1 | CPP=${CROSS_COMPILE}g++ 2 | GCC=${CROSS_COMPILE}gcc 3 | 4 | CPPFLAGS=-std=c++11 -Wall -fexceptions -std=gnu++11 -O2 -DNDEBUG -DUNICODE 5 | CFLAGS=-Wall -fexceptions -O2 6 | LDFLAGS= 7 | 8 | INCLUDES=\ 9 | ./inc 10 | 11 | INCLUDE=$(addprefix -I,$(INCLUDES)) 12 | 13 | LIBS=pthread 14 | 15 | LINKFLAGS=$(addprefix -l,$(LIBS)) 16 | 17 | SOURCE=main.cpp plc_control.cpp plc_io.cpp plc_state.cpp plc_mod.cpp \ 18 | plc_platform.cpp plc_bus.cpp plc_fw.cpp plc_data_types.cpp \ 19 | plc_hw.cpp stl_commands.cpp 20 | 21 | OBJ_DIR=./out 22 | SRC_DIR=./src 23 | 24 | OBJECTS=$(patsubst %,$(OBJ_DIR)/%,$(SOURCE:%.cpp=%.o)) 25 | 26 | all: fw_cpu 27 | 28 | fw_cpu: $(OBJ_DIR) $(OBJECTS) 29 | ${CPP} -o $(OBJ_DIR)/fw_cpu $(LDFLAGS) $(OBJECTS) $(LINKFLAGS) 30 | 31 | $(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp 32 | ${CPP} ${CPPFLAGS} ${INCLUDE} -c $< -o $@ 33 | 34 | $(OBJ_DIR): 35 | mkdir -p $(OBJ_DIR) 36 | 37 | clean: 38 | rm -f $(OBJECTS) $(OBJ_DIR)/fw_cpu 39 | -------------------------------------------------------------------------------- /firmware/fw_cpu/fw_cpu.pro: -------------------------------------------------------------------------------- 1 | QT -= core gui opengl 2 | 3 | APP = fw_cpu 4 | TARGET = fw_cpu 5 | 6 | CONFIG += c++11 7 | 8 | QMAKE_LFLAGS += -T$$PWD/../cortex-m4/stm32f429xx.ld 9 | 10 | DEFINES += STM32F429xx DATA_IN_ExtSDRAM 11 | 12 | DESTDIR = ./ 13 | #win32:EXT = .exe 14 | 15 | #QMAKE_CXXFLAGS += -O0 16 | win32:QMAKE_LFLAGS += -L/mingw32/lib/gcc/arm-none-eabi/5.4.1/ 17 | linux:QMAKE_LFLAGS += -L/usr/lib/gcc/arm-none-eabi/7.2.0/ 18 | 19 | createlist.target = all 20 | createlist.commands += arm-none-eabi-objdump -S $${OUT_PWD}/$${APP}$${EXT} > $$join(APP,,,".lst") 21 | createlist.commands += && arm-none-eabi-objcopy -Obinary $${OUT_PWD}/$${APP}$${EXT} $${OUT_PWD}/$${APP}.bin 22 | !win32:createlist.commands += && arm-none-eabi-nm -nalS --size-sort $${OUT_PWD}/$${APP}$${EXT} | grep " T " | tail 23 | createlist.commands += && arm-none-eabi-size $${OUT_PWD}/$${APP}$${EXT} 24 | QMAKE_EXTRA_TARGETS += createlist 25 | 26 | INCLUDEPATH += ../shared/CMSIS/ ./inc/ ../shared/inc/ platforms/stm32/ 27 | INCLUDEPATH += ../shared/Third_Party/FatFs/src/ ../shared/Third_Party/FatFs/src/option/ 28 | 29 | HEADERS += \ 30 | ../shared/CMSIS/core_cm4.h \ 31 | ../shared/CMSIS/core_cmFunc.h \ 32 | ../shared/CMSIS/core_cmInstr.h \ 33 | ../shared/CMSIS/stm32f429xx.h \ 34 | ../shared/CMSIS/stm32f4xx.h \ 35 | ../shared/CMSIS/ISRstm32f429xx.h \ 36 | inc/init.h \ 37 | platforms/stm32/stm32_uart.h \ 38 | platforms/stm32/stm32_rcc.h \ 39 | platforms/stm32/stm32_gpio.h \ 40 | ../shared/inc/my_func.h \ 41 | inc/bitbanding.h \ 42 | inc/plc_io.h \ 43 | platforms/stm32/stm32_pwr.h \ 44 | platforms/stm32/stm32_flash.h \ 45 | platforms/stm32/stm32_systick.h \ 46 | platforms/stm32/stm32_conf.h \ 47 | platforms/stm32/xprintf.h \ 48 | platforms/stm32/stm32_sdram.h \ 49 | inc/plc_control.h \ 50 | platforms/stm32/stm32_nvic.h \ 51 | platforms/stm32/stm32_inc.h \ 52 | ../shared/Third_Party/FatFs/src/ff.h \ 53 | ../shared/Third_Party/FatFs/src/integer.h \ 54 | platforms/stm32/ffconf.h \ 55 | platforms/stm32/stm32_sd.h \ 56 | platforms/stm32/fatfs.h \ 57 | platforms/stm32/diskiodriver.h \ 58 | platforms/stm32/sddriver.h \ 59 | platforms/stm32/diskio.h \ 60 | inc/memmanager.h \ 61 | platforms/stm32/stm32_spi.h \ 62 | ../shared/inc/plc_mod.h \ 63 | platforms/stm32/stm32_rtc.h \ 64 | inc/plc_state.h 65 | 66 | SOURCES += \ 67 | ../shared/CMSIS/ISRstm32f429xx.cpp \ 68 | src/main.cpp \ 69 | src/init.cpp \ 70 | platforms/stm32/stm32_uart.cpp \ 71 | platforms/stm32/stm32_rcc.cpp \ 72 | platforms/stm32/stm32_gpio.cpp \ 73 | ../shared/src/my_func.cpp \ 74 | src/plc_io.cpp \ 75 | platforms/stm32/stm32_pwr.cpp \ 76 | platforms/stm32/stm32_flash.cpp \ 77 | platforms/stm32/stm32_systick.cpp \ 78 | platforms/stm32/stm32_sdram.cpp \ 79 | src/plc_control.cpp \ 80 | platforms/stm32/stm32_nvic.cpp \ 81 | ../shared/Third_Party/FatFs/src/ff.c \ 82 | ../shared/Third_Party/FatFs/src/option/syscall.c \ 83 | ../shared/Third_Party/FatFs/src/option/ccsbcs.c \ 84 | platforms/stm32/fatfs.cpp \ 85 | platforms/stm32/sddriver.cpp \ 86 | platforms/stm32/stm32_sd.cpp \ 87 | src/memmanager.cpp \ 88 | platforms/stm32/stm32_spi.cpp \ 89 | ../shared/src/plc_mod.cpp \ 90 | platforms/stm32/xprintf.cpp \ 91 | platforms/stm32/stm32_rtc.cpp \ 92 | src/plc_state.cpp 93 | 94 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_bus.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_BUS_H 2 | #define PLC_BUS_H 3 | 4 | #include 5 | 6 | #ifdef PLATFORM_STM32 7 | class STM32_SPI; 8 | #endif 9 | 10 | class PLCBus 11 | { 12 | public: 13 | void init(bool is_com); 14 | 15 | void unselect(); 16 | void select(); 17 | 18 | uint32_t transmit(uint8_t* tx_data, uint32_t tx_size, uint32_t timeout); 19 | uint32_t transmit_recieve(uint8_t* tx_data, uint8_t* rx_data, uint32_t tx_size, uint32_t timeout); 20 | private: 21 | bool m_bus_com; 22 | #ifdef PLATFORM_STM32 23 | STM32_SPI *m_spi; 24 | #endif 25 | void init_CS(); 26 | }; 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_conf.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_CONF_H 2 | #define PLC_CONF_H 3 | 4 | #define PLC_MOD_EXT_SEL_GPIO gpiof 5 | #define PLC_MOD_EXT_SEL_PIN GPIO_PIN_6 6 | #define PLC_MOD_COM_SEL_GPIO gpiog 7 | #define PLC_MOD_COM_SEL_PIN GPIO_PIN_11 8 | 9 | #define PLC_RESULT_OK 0 10 | 11 | #define PLC_CPU 12 | 13 | #define PLC_FW_MAX_SIZE (10*1024*1024) 14 | 15 | #define PLC_SYSTEM_OB_COUNT 45 16 | #define PLC_FB_OFFSET PLC_SYSTEM_OB_COUNT 17 | 18 | #define PLC_NETWORKS_IN_BLOCK_MAX (10 * 1024) 19 | #define PLC_BLOCKS (PLC_SYSTEM_OB_COUNT + 10) 20 | #define PLC_NETWORKS 20 21 | #define PLC_DB_COUNT 10 22 | 23 | #define PLC_TITLE_SIZE 64 24 | #define PLC_COMMENT_SIZE 128 25 | 26 | #define PLC_IO_SIZE (60 * 1024) 27 | #define PLC_MEM_SIZE (1 * 1024 * 1024) 28 | #define PLC_DB_MEM_SIZE (1 * 1024 * 1024) 29 | #define PLC_LOCAL_SIZE (1024) 30 | #define PLC_OB_DB_SIZE (1024) 31 | 32 | #define PLC_NESTED_DEPTH 7 33 | 34 | #define PLC_EDGE_AREA_MEM_OFFSET 0 35 | #define PLC_EDGE_AREA_INPUT_OFFSET PLC_MEM_SIZE 36 | #define PLC_EDGE_AREA_OUTPUT_OFFSET (PLC_EDGE_AREA_INPUT_OFFSET + PLC_IO_SIZE) 37 | #define PLC_EGDE_AREA_SIZE (PLC_MEM_SIZE + PLC_IO_SIZE * 2) 38 | 39 | #define PLC_NETWORK_END (-1) 40 | 41 | #ifndef UNUSED 42 | #define UNUSED(x) (void)(x) 43 | #endif 44 | 45 | #endif // PLC_CONF_H 46 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_control.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_CONTROL_H 2 | #define PLC_CONTROL_H 3 | 4 | #include 5 | 6 | #define PLC_TEXT_BUF_SIZE 1024 7 | 8 | class PLC_CONTROL 9 | { 10 | public: 11 | static void init(); 12 | static void init_hw(); 13 | static void print_message(const char* fmt, ...); 14 | 15 | static void init_seq(); 16 | static void main(); 17 | 18 | static void fault_state_on(); 19 | 20 | static inline uint8_t in_run() { return m_state_run; } 21 | static inline uint8_t in_stop() { return m_state_stop; } 22 | static inline uint8_t in_rs_blink() { return m_state_rs_blink; } 23 | static inline uint8_t in_error() { return m_state_error; } 24 | static inline uint8_t in_fault() { return m_state_fault; } 25 | static inline uint8_t is_initialized() { return m_state_initialized; } 26 | private: 27 | static uint8_t m_state_run; 28 | static uint8_t m_state_stop; 29 | static uint8_t m_state_rs_blink; 30 | static uint8_t m_state_error; 31 | static uint8_t m_state_fault; 32 | static uint8_t m_state_com_fault; 33 | static uint8_t m_state_initialized; 34 | static char m_text_buf[PLC_TEXT_BUF_SIZE]; 35 | 36 | static inline void set_run(uint8_t val) { m_state_run = val; } 37 | static inline void set_stop(uint8_t val) { m_state_stop = val; } 38 | static inline void set_rs_blink(uint8_t val) { m_state_rs_blink = val; } 39 | static inline void set_error(uint8_t val) { m_state_error = val; } 40 | static inline void set_fault(uint8_t val) { m_state_fault = val; } 41 | static inline void set_com_fault(uint8_t val) { m_state_com_fault = val; } 42 | static inline void set_initialized(uint8_t val) { m_state_initialized = val; } 43 | 44 | static void scheck_RTC(); 45 | static void init_fs(); 46 | 47 | static void test_RAM(bool print_debug); 48 | static void test_RAM_speed(); 49 | }; 50 | 51 | void Error_Handler(); 52 | 53 | #endif // PLC_CONTROL_H 54 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_data_interface.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_DATA_INTERFACE_H 2 | #define PLC_DATA_INTERFACE_H 3 | 4 | #include 5 | #include "plc_conf.h" 6 | 7 | typedef struct 8 | { 9 | uint8_t b0 : 1; 10 | uint8_t b1 : 1; 11 | uint8_t b2 : 1; 12 | uint8_t b3 : 1; 13 | uint8_t b4 : 1; 14 | uint8_t b5 : 1; 15 | uint8_t b6 : 1; 16 | uint8_t b7 : 1; 17 | } mem_byte_t; 18 | 19 | #ifdef PLC_BE 20 | static __inline uint16_t __bswap16(uint16_t _x) 21 | { 22 | 23 | return ((uint16_t)((_x >> 8) | ((_x << 8) & 0xff00))); 24 | } 25 | 26 | static __inline uint32_t __bswap32(uint32_t _x) 27 | { 28 | 29 | return ((uint32_t)((_x >> 24) | ((_x >> 8) & 0xff00) | 30 | ((_x << 8) & 0xff0000) | ((_x << 24) & 0xff000000))); 31 | } 32 | 33 | #define BO_WORD(x) __builtin_bswap16(x) 34 | #define BO_DWORD(x) __builtin_bswap32(x) 35 | #else 36 | #define BO_WORD(x) x 37 | #define BO_DWORD(x) x 38 | #endif 39 | 40 | class PLCDataInterface 41 | { 42 | public: 43 | PLCDataInterface(uint8_t *mem) { m_data = mem; } 44 | 45 | bool read_bit(int addr, int bit) { return ( (m_data[addr] >> bit) & 1 ); } 46 | void set_bit(int addr, int bit) { m_data[addr] |= 1 << bit; } 47 | void set_bit(int addr, int bit, bool val) { m_data[addr] ^= (-val ^ m_data[addr]) & (1 << bit); } 48 | void clr_bit(int addr, int bit) { m_data[addr] &= ~(1 << bit); } 49 | 50 | uint8_t read_byte(int addr) { return m_data[addr]; } 51 | void write_byte(int addr, uint8_t val) { m_data[addr] = val; } 52 | 53 | int16_t read_word(int addr) { return BO_WORD(*((int16_t*)&m_data[addr])); } 54 | void write_word(int addr, int16_t val) { *((int16_t*)&m_data[addr]) = BO_WORD(val); } 55 | 56 | int32_t read_dword(int addr) { return BO_DWORD(*((int32_t*)&m_data[addr])); } 57 | void write_dword(int addr, int32_t val) { *((int32_t*)&m_data[addr]) = BO_DWORD(val); } 58 | 59 | float read_real(int addr) { return (float)BO_DWORD(*((int32_t*)&m_data[addr])); } 60 | void write_real(int addr, float val) { *((int32_t*)&m_data[addr]) = BO_DWORD((int32_t)val); } 61 | private: 62 | uint8_t *m_data; 63 | int32_t m_top_addr; 64 | int32_t m_top_bit; 65 | }; 66 | 67 | #endif // PLC_DATA_INTERFACE_H 68 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_data_types.h: -------------------------------------------------------------------------------- 1 | #ifndef DATA_TYPES_H 2 | #define DATA_TYPES_H 3 | 4 | #ifndef STLC 5 | #include "plc_conf.h" 6 | #endif 7 | #include 8 | #include 9 | 10 | enum class EBlockType 11 | { 12 | NONE, 13 | OB, 14 | FB, 15 | FC, 16 | SFB, 17 | SFC, 18 | }; 19 | 20 | typedef struct 21 | { 22 | int32_t idx; 23 | int32_t no; 24 | char title[PLC_COMMENT_SIZE]; 25 | } OB_descr_t; 26 | 27 | enum class EParameterLocation : uint8_t 28 | { 29 | NONE, 30 | LINK, //link to parameters area (if size > 2) 31 | INPUT, 32 | OUTPUT, 33 | MEMORY, 34 | LOCAL, 35 | IDX, 36 | DB, 37 | TIMER, 38 | COUNTER, 39 | CONSTANT, 40 | BLOCK_INPUT, 41 | BLOCK_OUTPUT, 42 | BLOCK_TEMP, 43 | FB, 44 | FC, 45 | SFB, 46 | SFC, 47 | STATUS_WORLD, 48 | AR1_OFFSET, 49 | AR2_OFFSET, 50 | }; 51 | 52 | enum class EDataType : uint8_t 53 | { 54 | NONE, 55 | BOOL, 56 | BYTE, 57 | CHAR, 58 | WORD, 59 | DWORD, 60 | INT, 61 | DINT, 62 | REAL, //float 63 | S5TIME, //16bit, word 64 | TIME, //32bit 65 | DATE, //16bit 66 | TIME_OF_DAY, //32 bit 67 | // complex types 68 | DATE_AND_TIME, 69 | STRING, 70 | ARRAY, 71 | ADDR, // for jump instructions 72 | }; 73 | 74 | enum class EDataSize 75 | { 76 | BIT, 77 | BYTE, 78 | WORD, 79 | DWORD, 80 | }; 81 | 82 | #define S5T_TB_10_MS 0x00 83 | #define S5T_TB_100_MS 0x01 84 | #define S5T_TB_1_S 0x10 85 | #define S5T_TB_10_S 0x11 86 | 87 | typedef struct 88 | { 89 | uint8_t BCD_0: 4; 90 | uint8_t BCD_1: 4; 91 | uint8_t BCD_2: 4; 92 | uint8_t time_base: 2; 93 | } S5TIME_t; 94 | 95 | union plc_data_t 96 | { 97 | uint16_t counter_idx; 98 | uint16_t timer_idx; 99 | 100 | struct 101 | { 102 | uint8_t bit; 103 | uint16_t addr; 104 | } BOOL; 105 | bool bool_val; 106 | struct 107 | { 108 | uint8_t bit; 109 | uint16_t addr; 110 | uint16_t db_idx; 111 | } ADDR_DB; 112 | uint16_t addr; 113 | uint8_t BYTE; 114 | char CHAR; 115 | int16_t WORD; 116 | int32_t DWORD; 117 | int16_t INT; 118 | int32_t DINT; 119 | float REAL; 120 | S5TIME_t S5TIME; 121 | uint32_t TIME; //TODO 122 | uint16_t DATE; //TODO 123 | uint32_t TIME_OF_DAY; 124 | 125 | uint32_t ADDR; // for jump instructions 126 | }; 127 | 128 | #ifndef STLC 129 | typedef struct parameter_t 130 | { 131 | EParameterLocation location; 132 | EDataType type; 133 | plc_data_t data; 134 | 135 | bool read_bool(); 136 | void write_bool(bool val); 137 | 138 | int8_t read_byte(); 139 | void write_byte(int8_t val); 140 | 141 | int16_t read_word(); 142 | void write_word(int16_t val); 143 | 144 | int32_t read_dword(); 145 | void write_dword(int32_t val); 146 | 147 | EDataSize get_size(); 148 | } parameter_t; 149 | #endif 150 | 151 | typedef struct 152 | { 153 | int32_t start; 154 | int32_t length; 155 | } symbol_t; 156 | 157 | typedef struct 158 | { 159 | EBlockType type; 160 | int32_t idx; 161 | symbol_t name; 162 | symbol_t title; 163 | symbol_t comment; 164 | int32_t nw_used; 165 | int32_t network_first; 166 | //TODO: local variables 167 | } program_block_t; 168 | 169 | typedef struct 170 | { 171 | symbol_t title; 172 | symbol_t comment; 173 | int32_t start_addr; 174 | int32_t network_next; 175 | } program_network_t; 176 | 177 | typedef struct 178 | { 179 | int16_t idx; 180 | int16_t no; 181 | int16_t size_bytes; 182 | int32_t offset; 183 | symbol_t title; 184 | } program_db_descr_t; 185 | 186 | typedef struct 187 | { 188 | char sign[4]; 189 | int32_t version; 190 | int32_t block_count; 191 | int32_t network_count; 192 | int32_t program_size; 193 | int32_t db_count; 194 | int32_t symbols_size; 195 | } program_header_t; 196 | 197 | union reg_union_t 198 | { 199 | struct 200 | { 201 | uint8_t b1; 202 | uint8_t b2; 203 | uint8_t b3; 204 | uint8_t b4; 205 | }; 206 | struct 207 | { 208 | uint16_t s1; 209 | uint16_t s2; 210 | }; 211 | uint32_t u32; 212 | float fl; 213 | }; 214 | 215 | #ifndef STLC 216 | typedef struct 217 | { 218 | int8_t get_lolo(); 219 | void set_lolo(int8_t val); 220 | int16_t get_lo(); 221 | void set_lo(int16_t val); 222 | int16_t get_hi(); 223 | void set_hi(int16_t val); 224 | 225 | int32_t get(); 226 | void set(int32_t val); 227 | 228 | float get_real(); 229 | void set_real(float val); 230 | 231 | void load_from_param(parameter_t* from); 232 | void load_to_param(parameter_t* to); 233 | private: 234 | reg_union_t m_reg; 235 | //uint32_t data; 236 | } PLCRegister; 237 | #endif 238 | 239 | #endif // DATA_TYPES_H 240 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_fw.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_FW_H 2 | #define PLC_FW_H 3 | 4 | #include 5 | #include "plc_conf.h" 6 | #include "stl_commands.h" 7 | #include "plc_data_types.h" 8 | 9 | class PLCFW 10 | { 11 | public: 12 | void init(); 13 | bool load(); 14 | 15 | void read_inputs(); 16 | void execute_OB1(); 17 | void write_outputs(); 18 | 19 | int32_t set_current_db(int32_t db_no); 20 | int32_t get_db_offset(int32_t db_no); 21 | 22 | int32_t get_current_db_offset() { return (m_cur_db == -1) ? 0 : m_db[m_cur_db].offset; } 23 | program_db_descr_t* get_cur_db_info() { return (m_cur_db == -1) ? nullptr : &m_db[m_cur_db]; } 24 | 25 | void exec_block(int32_t block_idx, int local_db = -1); 26 | 27 | bool is_ok() { return m_fw_ok; } 28 | private: 29 | uint8_t *m_fw; 30 | uint32_t m_fw_size; 31 | bool m_fw_ok; 32 | 33 | program_header_t *m_header; 34 | program_block_t *m_blocks; 35 | program_network_t *m_networks; 36 | STL_CMD_TYPE *m_prog_data; 37 | program_db_descr_t *m_db; 38 | char m_symbols; 39 | 40 | int32_t m_cur_db; 41 | }; 42 | 43 | extern PLCFW plc_fw; 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_hw.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_HW_H 2 | #define PLC_HW_H 3 | 4 | #include "plc_data_types.h" 5 | #include "plc_conf.h" 6 | #include "plc_data_interface.h" 7 | #include "stl_commands.h" 8 | 9 | #define PLC_STATUS_NOT_FC_BIT 0 10 | #define PLC_STATUS_RLO_BIT 1 11 | #define PLC_STATUS_STA_BIT 2 12 | #define PLC_STATUS_OR_BIT 3 13 | #define PLC_STATUS_OS_BIT 4 14 | #define PLC_STATUS_OV_BIT 5 15 | #define PLC_STATUS_CC0_BIT 6 16 | #define PLC_STATUS_CC1_BIT 7 17 | #define PLC_STATUS_BR_BIT 8 18 | 19 | #define PLC_STATUS_NOT_FC_MASK (1 << PLC_STATUS_NOT_FC_BIT) 20 | #define PLC_STATUS_RLO_MASK (1 << PLC_STATUS_RLO_BIT) 21 | #define PLC_STATUS_STA_MASK (1 << PLC_STATUS_STA_BIT) 22 | #define PLC_STATUS_OR_MASK (1 << PLC_STATUS_OR_BIT) 23 | #define PLC_STATUS_OS_MASK (1 << PLC_STATUS_OS_BIT) 24 | #define PLC_STATUS_OV_MASK (1 << PLC_STATUS_OV_BIT) 25 | #define PLC_STATUS_CC0_MASK (1 << PLC_STATUS_CC0_BIT) 26 | #define PLC_STATUS_CC1_MASK (1 << PLC_STATUS_CC1_BIT) 27 | #define PLC_STATUS_BR_MASK (1 << PLC_STATUS_BR_BIT) 28 | 29 | typedef struct 30 | { 31 | ESTLCommand cmd; 32 | uint32_t status; 33 | } nested_t; 34 | 35 | class PLCHW 36 | { 37 | public: 38 | PLCHW(); 39 | 40 | PLCDataInterface* get_mem_obj() { return m_memory; } 41 | PLCDataInterface* get_local_obj() { return m_local; } 42 | PLCDataInterface* get_dbs_obj() { return m_dbs; } 43 | PLCDataInterface* get_inputs_obj() { return m_inputs; } 44 | PLCDataInterface* get_outputs_obj() { return m_outputs; } 45 | 46 | void push_ACCU(int32_t val); 47 | void push_ACCU(parameter_t* param); 48 | int32_t pop_ACCU(); 49 | void pop_ACCU(parameter_t* param); 50 | 51 | PLCRegister* get_ACCU1() { return &m_ACCU1; } 52 | PLCRegister* get_ACCU2() { return &m_ACCU2; } 53 | 54 | PLCRegister* get_AR1() { return &m_AR1; } 55 | PLCRegister* get_AR2() { return &m_AR2; } 56 | 57 | int32_t get_status_bit(uint32_t bit_mask); 58 | void set_status_bits(uint32_t bit_mask); 59 | void set_reset_status_bits(uint32_t bit_mask, uint32_t values); 60 | void clear_status_bits(uint32_t bit_mask); 61 | 62 | uint32_t get_status_word() { return m_status_word; } 63 | void reset_status_word(); 64 | 65 | uint32_t get_local_top() { return m_local_top; } 66 | void set_local_top(uint32_t val) { m_local_top = val; } 67 | 68 | void nested_push(ESTLCommand cmd); 69 | nested_t nested_pop(); 70 | 71 | bool get_MCR() { return m_MCR; } 72 | private: 73 | PLCDataInterface *m_memory; 74 | PLCDataInterface *m_local; 75 | PLCDataInterface *m_dbs; 76 | PLCDataInterface *m_inputs; 77 | PLCDataInterface *m_outputs; 78 | uint8_t* m_memory_area; 79 | uint8_t* m_local_area; 80 | uint8_t* m_dbs_area; 81 | uint8_t* m_inputs_area; 82 | uint8_t* m_outputs_area; 83 | uint32_t m_status_word; 84 | uint32_t m_local_top; 85 | bool m_MCR; 86 | PLCRegister m_ACCU1; 87 | PLCRegister m_ACCU2; 88 | PLCRegister m_ACCU3; 89 | PLCRegister m_ACCU4; 90 | PLCRegister m_AR1; 91 | PLCRegister m_AR2; 92 | 93 | uint32_t m_nested_size; 94 | nested_t m_nested_buf[PLC_NESTED_DEPTH]; 95 | }; 96 | 97 | extern PLCHW plc_hw; 98 | 99 | #endif // PLC_HW_H 100 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_io.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_IO_H 2 | #define PLC_IO_H 3 | 4 | #ifdef PLATFORM_STM32 5 | #include "stm32_gpio.h" 6 | 7 | #define PIN_PWR GPIO_PIN_12 8 | #define PIN_RUN GPIO_PIN_11 9 | #define PIN_STP GPIO_PIN_9 10 | #define PIN_RSB GPIO_PIN_13 11 | #define PIN_ERR GPIO_PIN_14 12 | #define PIN_FLT GPIO_PIN_15 13 | #define PIN_CFL GPIO_PIN_13 14 | #endif 15 | 16 | class PLC_IO 17 | { 18 | public: 19 | static void init(); 20 | 21 | static void pin_on_POWER(); 22 | static void pin_off_POWER(); 23 | 24 | static void pin_on_RUN(); 25 | static void pin_off_RUN(); 26 | 27 | static void pin_on_STOP(); 28 | static void pin_off_STOP(); 29 | 30 | static void pin_on_RS_BLINK(); 31 | static void pin_off_RS_BLINK(); 32 | 33 | static void pin_on_ERROR(); 34 | static void pin_off_ERROR(); 35 | 36 | static void pin_on_FAULT(); 37 | static void pin_off_FAULT(); 38 | 39 | static void pin_on_COM_FAULT(); 40 | static void pin_off_COM_FAULT(); 41 | 42 | static void timer_proc(); 43 | private: 44 | }; 45 | 46 | #endif // PLC_IO_H 47 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_mod.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_MOD_H 2 | #define PLC_MOD_H 3 | 4 | #include 5 | #include "plc_conf.h" 6 | #include "plc_bus.h" 7 | 8 | #define PLC_MOD_TYPE_CPU (0x01 << 0x01) 9 | #define PLC_MOD_TYPE_PN (0x01 << 0x02) 10 | #define PLC_MOD_TYPE_PB (0x01 << 0x03) 11 | #define PLC_MOD_TYPE_DI (0x01 << 0x04) 12 | #define PLC_MOD_TYPE_DO (0x01 << 0x05) 13 | #define PLC_MOD_TYPE_AI (0x01 << 0x06) 14 | #define PLC_MOD_TYPE_AO (0x01 << 0x07) 15 | 16 | #define PLC_MOD_ADDR_MAX_DISCRET 16 17 | #define PLC_MOD_ADDR_MAX_ANALOG 8 18 | #define PLC_MOD_ADDR_MAX_COM 200 19 | 20 | #define PLC_MOD_TARGET_ALL 0xffff 21 | 22 | #define PLC_MOD_MAX_MODULES 32 23 | 24 | typedef struct 25 | { 26 | uint32_t type; 27 | uint32_t hw_version; 28 | uint32_t fw_version; 29 | uint32_t inputs; 30 | uint32_t outputs; 31 | } plc_mod_info_t; 32 | 33 | enum class EModRequest : uint32_t 34 | { 35 | NONE = 0, 36 | GET_INFO = 1, 37 | }; 38 | 39 | typedef struct 40 | { 41 | uint32_t target_id; 42 | uint32_t data_size; 43 | EModRequest request; 44 | union 45 | { 46 | uint8_t discret[PLC_MOD_ADDR_MAX_DISCRET]; 47 | uint16_t analog[PLC_MOD_ADDR_MAX_ANALOG]; 48 | uint8_t com[PLC_MOD_ADDR_MAX_COM]; 49 | plc_mod_info_t info; 50 | }; 51 | } plc_mod_pkt_t; 52 | 53 | class PLC_MOD 54 | { 55 | public: 56 | void init(bool is_com); 57 | void find_modules(); 58 | private: 59 | PLCBus m_bus; 60 | plc_mod_pkt_t m_pkt_send; 61 | plc_mod_pkt_t m_pkt_recv; 62 | 63 | bool m_bus_com; 64 | uint32_t m_mod_count; 65 | 66 | plc_mod_info_t m_modules[PLC_MOD_MAX_MODULES]; 67 | 68 | void CS_on(); 69 | void CS_off(); 70 | 71 | void print_module_info(plc_mod_info_t *mod); 72 | }; 73 | 74 | extern PLC_MOD plc_mod_com; 75 | extern PLC_MOD plc_mod_ext; 76 | 77 | #endif // PLC_MOD_H 78 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_platform.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_PLATFORM_H 2 | #define PLC_PLATFORM_H 3 | 4 | #include 5 | 6 | int32_t load_file(char* fn, uint8_t* buf); 7 | 8 | #ifdef PLATFORM_STM32 9 | 10 | #define PLATFORM_DELAY_MS(delay) STM32_SYSTICK::delay(delay) 11 | 12 | #else 13 | 14 | #include 15 | 16 | #define PLATFORM_DELAY_MS(delay) rt_delay_ms(delay) 17 | 18 | #define RT_INIT_THREAD() \ 19 | struct sched_param param; \ 20 | pthread_attr_t attr; \ 21 | pthread_t thread; \ 22 | int ret; \ 23 | \ 24 | /* Lock memory */ \ 25 | if(mlockall(MCL_CURRENT|MCL_FUTURE) == -1) \ 26 | { \ 27 | printf("mlockall failed: %m\n"); \ 28 | return; \ 29 | } \ 30 | \ 31 | /* Initialize pthread attributes (default values) */ \ 32 | ret = pthread_attr_init(&attr); \ 33 | if (ret) { \ 34 | printf("init pthread attributes failed\n"); \ 35 | return; \ 36 | } \ 37 | \ 38 | /* Set a specific stack size */ \ 39 | ret = pthread_attr_setstacksize(&attr, PTHREAD_STACK_MIN); \ 40 | if (ret) \ 41 | { \ 42 | printf("pthread setstacksize failed\n"); \ 43 | return; \ 44 | } \ 45 | \ 46 | /* Set scheduler policy and priority of pthread */ \ 47 | ret = pthread_attr_setschedpolicy(&attr, SCHED_FIFO); \ 48 | if (ret) \ 49 | { \ 50 | printf("pthread setschedpolicy failed\n"); \ 51 | return; \ 52 | } \ 53 | param.sched_priority = 80; \ 54 | ret = pthread_attr_setschedparam(&attr, ¶m); \ 55 | if (ret) \ 56 | { \ 57 | printf("pthread setschedparam failed\n"); \ 58 | return; \ 59 | } \ 60 | /* Use scheduling parameters of attr */ \ 61 | ret = pthread_attr_setinheritsched(&attr, PTHREAD_EXPLICIT_SCHED); \ 62 | if (ret) \ 63 | { \ 64 | printf("pthread setinheritsched failed\n"); \ 65 | return; \ 66 | } \ 67 | /* Create a pthread with specified attributes */ \ 68 | ret = pthread_create(&thread, &attr, thread_func, NULL); \ 69 | if (ret) \ 70 | { \ 71 | printf("create pthread failed\n"); \ 72 | return; \ 73 | } \ 74 | \ 75 | /* Join the thread and wait until it is done */ \ 76 | ret = pthread_join(thread, NULL); \ 77 | if (ret) \ 78 | printf("join pthread failed: %m\n"); 79 | 80 | void rt_delay_ms(uint32_t ms); 81 | 82 | #endif 83 | 84 | #endif 85 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/plc_state.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_STATE_H 2 | #define PLC_STATE_H 3 | 4 | #ifdef PLATFORM_STM32 5 | #include "stm32_rtc.h" 6 | #else 7 | #include 8 | #endif 9 | 10 | typedef struct 11 | { 12 | uint8_t year; 13 | uint8_t month; 14 | uint8_t day; 15 | uint8_t hour; 16 | uint8_t min; 17 | uint8_t sec; 18 | uint16_t msec; 19 | } plc_datetime_t; 20 | 21 | #define PLC_CYCLE_TIME_COUNT 100 22 | 23 | typedef struct 24 | { 25 | plc_datetime_t start_dt; 26 | plc_datetime_t current_dt; 27 | uint16_t last_cycle_time; 28 | } plc_state_t; 29 | 30 | class PLC_STATE 31 | { 32 | public: 33 | static void init(); 34 | 35 | static void update_ct(); 36 | 37 | static inline plc_datetime_t* get_start_dt() { return &m_start_dt; } 38 | static inline plc_datetime_t* get_current_dt() { return &m_current_dt; } 39 | static inline uint32_t get_last_cycle_time() { return m_last_cycle_time_avg; } 40 | 41 | private: 42 | static uint32_t m_last_cycle_time[PLC_CYCLE_TIME_COUNT]; 43 | static uint32_t m_last_cycle_time_avg; 44 | static uint32_t m_last_cycle_time_idx; 45 | 46 | static plc_datetime_t m_start_dt; 47 | static plc_datetime_t m_current_dt; 48 | 49 | static void get_dt(plc_datetime_t* dt); 50 | }; 51 | 52 | #endif // PLC_STATE_H 53 | -------------------------------------------------------------------------------- /firmware/fw_cpu/inc/stl_commands.h: -------------------------------------------------------------------------------- 1 | #ifndef STL_COMMANDS_H 2 | #define STL_COMMANDS_H 3 | 4 | #include 5 | 6 | #define STL_CMD_TYPE uint8_t 7 | 8 | enum class ESTLCommand 9 | { 10 | Nesting_closed, 11 | 12 | Assign, 13 | CLR, // untested 14 | FN, 15 | FP, 16 | NOT, 17 | O, 18 | O_net, 19 | ON, // untested 20 | ON_net, // untested 21 | R, 22 | S, 23 | SAVE, // untested 24 | SET, // untested 25 | A, 26 | A_net, 27 | AN, 28 | AN_net, // untested 29 | X, // untested 30 | X_net, // untested 31 | XN, // untested 32 | XN_net, // untested 33 | 34 | AD, 35 | AW, 36 | OD, 37 | OW, 38 | XOD, 39 | XOW, 40 | 41 | AR1_Add, 42 | AR2_Add, 43 | DEC, 44 | ENT, 45 | INC, 46 | LEAVE, 47 | NOP, 48 | POP, 49 | PUSH, 50 | TAK, 51 | 52 | Add, 53 | AR12_D_Add, 54 | AR12_D_Sub, 55 | AR12_D_Mul, 56 | AR12_D_Div, 57 | AR12_I_Add, 58 | AR12_I_Sub, 59 | AR12_I_Mul, 60 | AR12_I_Div, 61 | MOD, 62 | 63 | AR12_R_Add, 64 | AR12_R_Sub, 65 | AR12_R_Mul, 66 | AR12_R_Div, 67 | ABS, 68 | ACOS, 69 | ASIN, 70 | ATAN, 71 | COS, 72 | EXP, 73 | LN, 74 | SIN, 75 | SQR, 76 | SQRT, 77 | TAN, 78 | 79 | AR12_D_Eq, 80 | AR12_D_Ne, 81 | AR12_D_Gt, 82 | AR12_D_Lt, 83 | AR12_D_Ge, 84 | AR12_D_Le, 85 | AR12_I_Eq, 86 | AR12_I_Ne, 87 | AR12_I_Gt, 88 | AR12_I_Lt, 89 | AR12_I_Ge, 90 | AR12_I_Le, 91 | AR12_R_Eq, 92 | AR12_R_Ne, 93 | AR12_R_Gt, 94 | AR12_R_Lt, 95 | AR12_R_Ge, 96 | AR12_R_Le, 97 | 98 | BTD, 99 | BTI, 100 | DTB, 101 | DTR, 102 | INVD, 103 | INVI, 104 | ITB, 105 | ITD, 106 | NEGD, 107 | NEGI, 108 | NEGR, 109 | RND, 110 | RND_Add, 111 | RND_Sub, 112 | CAD, 113 | CAW, 114 | CDB, 115 | TRUNC, 116 | 117 | FR, 118 | LC_C, 119 | R_C, 120 | S_C, 121 | CD, 122 | CU, 123 | 124 | L, 125 | L_T, 126 | L_C, 127 | L_DBLG, 128 | L_DBNO, 129 | L_DILG, 130 | L_DINO, 131 | L_STW, 132 | LAR1, 133 | LAR1_AR2, 134 | LAR2, 135 | T, 136 | T_STW, 137 | CAR, 138 | TAR1, 139 | TAR1_AR2, 140 | TAR2, 141 | 142 | BE, 143 | BEU, 144 | BEC, 145 | BLD, 146 | CALL, 147 | CC, 148 | MCR_st, 149 | MCR_en, 150 | MCRA, 151 | MCRD, 152 | UC, 153 | 154 | RLD, 155 | RLDA, 156 | RRD, 157 | RRDA, 158 | SLD, 159 | SLW, 160 | SRD, 161 | SRW, 162 | SSD, 163 | SSI, 164 | 165 | LC_T, 166 | R_T, 167 | SF, 168 | SD, 169 | SP, 170 | SS, 171 | SE, 172 | 173 | LOOP, 174 | JU, 175 | JC, 176 | JCB, 177 | JBI, 178 | JNBI, 179 | JCN, 180 | JNB, 181 | JL, 182 | JM, 183 | JMZ, 184 | JN, 185 | JO, 186 | JP, 187 | JPZ, 188 | JOS, 189 | JUO, 190 | JZ, 191 | 192 | OPN, 193 | 194 | ARG_START, 195 | ARG_END, 196 | NETWORK_END, 197 | 198 | RET, 199 | }; 200 | 201 | enum class ESTLCategory 202 | { 203 | Integer_Match, 204 | Bit_Logic, 205 | Accumulator, 206 | Compare, 207 | Floating_point, 208 | DB_Call, 209 | Program_Control, 210 | Convert, 211 | Timers, 212 | Load_Transfer, 213 | Counters, 214 | Jumps, 215 | World_Logic, 216 | Shift_Rotate, 217 | }; 218 | 219 | typedef struct 220 | { 221 | ESTLCommand command; 222 | const char* mnemonic; 223 | ESTLCategory category; 224 | } STL_CMD_t; 225 | 226 | 227 | #define STL_CMD_COUNT 173 228 | 229 | extern STL_CMD_t STL_CMDs[STL_CMD_COUNT]; 230 | 231 | class STLCommands 232 | { 233 | public: 234 | STLCommands(); 235 | 236 | static int32_t exec_command(STL_CMD_TYPE *prog_data); 237 | private: 238 | static void proceed_real_op(float res); 239 | static void proceed_int32_op(int64_t res); 240 | static void proceed_int16_op(int32_t res); 241 | }; 242 | 243 | #endif // STL_COMMANDS_H 244 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/diskio.h: -------------------------------------------------------------------------------- 1 | #ifndef DISKIO_H 2 | #define DISKIO_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" 6 | { 7 | #endif 8 | 9 | #include "fatfs.h" 10 | 11 | DSTATUS disk_status(BYTE pdrv); 12 | DSTATUS disk_initialize(BYTE pdrv); 13 | DSTATUS disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count); 14 | #if _USE_WRITE == 1 15 | DSTATUS disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count); 16 | #endif 17 | #if _USE_IOCTL == 1 18 | DSTATUS disk_ioctl(BYTE pdrv, BYTE cmd, void *buff); 19 | #endif 20 | 21 | #ifdef __cplusplus 22 | } 23 | #endif 24 | 25 | #endif // DISKIO_H 26 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/diskiodriver.h: -------------------------------------------------------------------------------- 1 | #ifndef DISKIODRIVER_H 2 | #define DISKIODRIVER_H 3 | 4 | #include "fatfs.h" 5 | #include 6 | 7 | class DiskIODriver 8 | { 9 | public: 10 | void init_gpio(); 11 | uint8_t init(uint8_t); 12 | uint8_t status(uint8_t); 13 | uint8_t read(uint8_t lun, uint8_t*buf, uint32_t sector, uint32_t count); 14 | #if _USE_WRITE == 1 15 | uint8_t write(uint8_t lun, uint8_t*buf, uint32_t sector, uint32_t count); 16 | #endif 17 | #if _USE_IOCTL == 1 18 | uint8_t ioctl(uint8_t, uint8_t, void*); 19 | #endif 20 | }; 21 | 22 | #endif // DISKIODRIVER_H 23 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/fatfs.cpp: -------------------------------------------------------------------------------- 1 | #include "fatfs.h" 2 | #include "stm32_conf.h" 3 | #include STM32_FATFS_DRIVER_INC 4 | 5 | DiskDrv FAT_FS::m_disk; 6 | 7 | extern STM32_FATFS_DRIVER sd_driver; 8 | char SD_path[4]; 9 | 10 | void FAT_FS::init() 11 | { 12 | m_disk.nbr = 0; 13 | link_driver((DiskIODriver*)&sd_driver, SD_path, 0); 14 | } 15 | 16 | DSTATUS FAT_FS::disk_status(BYTE pdrv) 17 | { 18 | return ((STM32_FATFS_DRIVER*)m_disk.drv[pdrv])->status(m_disk.lun[pdrv]); 19 | } 20 | 21 | DSTATUS FAT_FS::disk_initialize(BYTE pdrv) 22 | { 23 | if (m_disk.is_initialized[pdrv] == 0) 24 | { 25 | if (((STM32_FATFS_DRIVER*)m_disk.drv[pdrv])->init(m_disk.lun[pdrv]) == RES_OK) 26 | { 27 | m_disk.is_initialized[pdrv] = 1; 28 | return RES_OK; 29 | } 30 | } 31 | return RES_ERROR; 32 | } 33 | 34 | DSTATUS FAT_FS::disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count) 35 | { 36 | return ((STM32_FATFS_DRIVER*)m_disk.drv[pdrv])->read(m_disk.lun[pdrv], buff, sector, count); 37 | } 38 | 39 | #if _USE_WRITE == 1 40 | DSTATUS FAT_FS::disk_write(BYTE pdrv, BYTE *buff, DWORD sector, UINT count) 41 | { 42 | return ((STM32_FATFS_DRIVER*)m_disk.drv[pdrv])->write(m_disk.lun[pdrv], buff, sector, count); 43 | } 44 | #endif 45 | #if _USE_IOCTL == 1 46 | DSTATUS FAT_FS::disk_ioctl(BYTE pdrv, BYTE cmd, void *buff) 47 | { 48 | return((STM32_FATFS_DRIVER*)m_disk.drv[pdrv])->ioctl(m_disk.lun[pdrv], cmd, buff); 49 | } 50 | #endif 51 | 52 | void FAT_FS::link_driver(DiskIODriver *drv, char *path, uint8_t lun) 53 | { 54 | if (m_disk.nbr <= _VOLUMES) 55 | { 56 | m_disk.is_initialized[m_disk.nbr] = 0; 57 | m_disk.drv[m_disk.nbr] = drv; 58 | m_disk.lun[m_disk.nbr] = lun; 59 | uint8_t num = m_disk.nbr++; 60 | path[0] = num + '0'; 61 | path[1] = ':'; 62 | path[2] = '/'; 63 | path[3] = 0; 64 | } 65 | } 66 | 67 | extern "C" 68 | { 69 | 70 | DSTATUS disk_status(BYTE pdrv) 71 | { 72 | return FAT_FS::disk_status(pdrv); 73 | } 74 | 75 | DSTATUS disk_initialize(BYTE pdrv) 76 | { 77 | return FAT_FS::disk_initialize(pdrv); 78 | } 79 | 80 | DSTATUS disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count) 81 | { 82 | return FAT_FS::disk_read(pdrv, buff, sector, count); 83 | } 84 | 85 | #if _USE_WRITE == 1 86 | DSTATUS disk_write(BYTE pdrv, BYTE *buff, DWORD sector, UINT count) 87 | { 88 | return FAT_FS::disk_write(pdrv, buff, sector, count); 89 | } 90 | 91 | #endif 92 | #if _USE_IOCTL == 1 93 | DSTATUS disk_ioctl(BYTE pdrv, BYTE cmd, void *buff) 94 | { 95 | return FAT_FS::disk_ioctl(pdrv, cmd, buff); 96 | } 97 | #endif 98 | 99 | } 100 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/fatfs.h: -------------------------------------------------------------------------------- 1 | #ifndef FATFS_H 2 | #define FATFS_H 3 | 4 | #include "ffconf.h" 5 | #include "integer.h" 6 | 7 | #define _USE_WRITE 1 /* 1: Enable disk_write function */ 8 | #define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */ 9 | 10 | typedef BYTE DSTATUS; 11 | 12 | /* Results of Disk Functions */ 13 | typedef enum { 14 | RES_OK = 0, /* 0: Successful */ 15 | RES_ERROR, /* 1: R/W Error */ 16 | RES_WRPRT, /* 2: Write Protected */ 17 | RES_NOTRDY, /* 3: Not Ready */ 18 | RES_PARERR /* 4: Invalid Parameter */ 19 | } DRESULT; 20 | 21 | /* Disk Status Bits (DSTATUS) */ 22 | 23 | #define STA_NOINIT 0x01 /* Drive not initialized */ 24 | #define STA_NODISK 0x02 /* No medium in the drive */ 25 | #define STA_PROTECT 0x04 /* Write protected */ 26 | 27 | /* Command code for disk_ioctrl fucntion */ 28 | 29 | /* Generic command (Used by FatFs) */ 30 | #define CTRL_SYNC 0 /* Complete pending write process (needed at _FS_READONLY == 0) */ 31 | #define GET_SECTOR_COUNT 1 /* Get media size (needed at _USE_MKFS == 1) */ 32 | #define GET_SECTOR_SIZE 2 /* Get sector size (needed at _MAX_SS != _MIN_SS) */ 33 | #define GET_BLOCK_SIZE 3 /* Get erase block size (needed at _USE_MKFS == 1) */ 34 | #define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */ 35 | 36 | /* Generic command (Not used by FatFs) */ 37 | #define CTRL_POWER 5 /* Get/Set power status */ 38 | #define CTRL_LOCK 6 /* Lock/Unlock media removal */ 39 | #define CTRL_EJECT 7 /* Eject media */ 40 | #define CTRL_FORMAT 8 /* Create physical format on the media */ 41 | 42 | /* MMC/SDC specific ioctl command */ 43 | #define MMC_GET_TYPE 10 /* Get card type */ 44 | #define MMC_GET_CSD 11 /* Get CSD */ 45 | #define MMC_GET_CID 12 /* Get CID */ 46 | #define MMC_GET_OCR 13 /* Get OCR */ 47 | #define MMC_GET_SDSTAT 14 /* Get SD status */ 48 | 49 | /* ATA/CF specific ioctl command */ 50 | #define ATA_GET_REV 20 /* Get F/W revision */ 51 | #define ATA_GET_MODEL 21 /* Get model name */ 52 | #define ATA_GET_SN 22 /* Get serial number */ 53 | 54 | #ifdef __cplusplus 55 | 56 | class DiskIODriver; 57 | 58 | typedef struct 59 | { 60 | uint32_t is_initialized[_VOLUMES]; 61 | DiskIODriver* drv[_VOLUMES]; 62 | uint8_t lun[_VOLUMES]; 63 | uint8_t nbr; 64 | } DiskDrv; 65 | 66 | class FAT_FS 67 | { 68 | public: 69 | static void init(); 70 | static DSTATUS disk_status(BYTE pdrv); 71 | static DSTATUS disk_initialize(BYTE pdrv); 72 | static DSTATUS disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count); 73 | #if _USE_WRITE == 1 74 | static DSTATUS disk_write(BYTE pdrv, BYTE *buff, DWORD sector, UINT count); 75 | #endif 76 | #if _USE_IOCTL == 1 77 | static DSTATUS disk_ioctl(BYTE pdrv, BYTE cmd, void *buff); 78 | #endif 79 | private: 80 | static DiskDrv m_disk; 81 | 82 | static void link_driver(DiskIODriver *drv, char *path, uint8_t lun); 83 | }; 84 | 85 | #endif 86 | 87 | #endif // FATFS_H 88 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/init.cpp: -------------------------------------------------------------------------------- 1 | #include "stm32_inc.h" 2 | #include "init.h" 3 | #include "my_func.h" 4 | #include "plc_control.h" 5 | #include "plc_io.h" 6 | #ifdef STM32_FATFS_USE 7 | #include "sddriver.h" 8 | #endif 9 | 10 | int main(); 11 | 12 | /* #define VECT_TAB_SRAM */ 13 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. 14 | This value must be a multiple of 0x200. */ 15 | 16 | // base initialization 17 | void base_init() 18 | { 19 | /* FPU settings ------------------------------------------------------------*/ 20 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 21 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 22 | #endif 23 | 24 | extern uint32_t _RAM_Start; 25 | memset((uint8_t*)&_RAM_Start, 0, 1024*50); 26 | 27 | STM32_RCC::deinit(); 28 | STM32_GPIO::init_all(); 29 | STM32_SYSTICK::init(); 30 | 31 | #if defined (DATA_IN_ExtSDRAM) 32 | if (STM32_SDRAM::init() != STM32_RESULT_OK) 33 | Error_Handler(); 34 | #endif 35 | 36 | /* Configure the Vector Table location add offset address ------------------*/ 37 | #ifdef VECT_TAB_SRAM 38 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 39 | #else 40 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 41 | #endif 42 | 43 | PLC_CONTROL::init(); 44 | 45 | #ifdef INSTRUCTION_CACHE_ENABLE 46 | STM32_FLASH::enable_instruction_cache(); 47 | #endif 48 | #ifdef DATA_CACHE_ENABLE 49 | STM32_FLASH::enable_data_cache(); 50 | #endif 51 | #ifdef PREFETCH_ENABLE 52 | STM32_FLASH::enable_prefetch_buffer(); 53 | #endif 54 | 55 | STM32_NVIC::init(); 56 | } 57 | 58 | void SystemInit() 59 | { 60 | base_init(); 61 | 62 | /* GPIO initializations */ 63 | PLC_IO::init(); 64 | 65 | // system initialization 66 | //__enable_fault_irq(); 67 | //__enable_irq(); 68 | STM32_RCC::init(); 69 | STM32_SYSTICK::init(); 70 | 71 | /* Other IO and peripheral initializations */ 72 | STM32_UART::init_all(); 73 | STM32_SPI::init_all(); 74 | STM32_RTC::init(); 75 | #ifdef STM32_FATFS_USE 76 | sd_driver.init_gpio(); 77 | #endif 78 | 79 | /* Initialize interrupt vectors for a peripheral */ 80 | STM32_NVIC::init_vectors(); 81 | 82 | uart3.init(STM32_BRATE_UART3); 83 | spi5.init(); 84 | spi6.init(); 85 | } 86 | 87 | #define INIT_SP() \ 88 | { \ 89 | __ASM volatile("mov r3, 0x08000000\n\r" \ 90 | "ldr sp, [r3, #0]\n\r" : : ); \ 91 | } \ 92 | 93 | void ISR::Reset() 94 | { 95 | INIT_SP(); 96 | SystemInit(); 97 | main(); 98 | } 99 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/init.h: -------------------------------------------------------------------------------- 1 | #ifndef __INIT__ 2 | #define __INIT__ 3 | 4 | #define TimerTick F_CPU/1000-1 5 | 6 | void RCCInit(void); 7 | void SystemInit(void); 8 | void SystemInit_ExtMemCtl(void); 9 | 10 | #endif // __INIT__ 11 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/memmanager.cpp: -------------------------------------------------------------------------------- 1 | #include "memmanager.h" 2 | #include "stm32_sdram.h" 3 | #include "my_func.h" 4 | 5 | uint8_t* MemManager::m_data; 6 | uint32_t MemManager::m_bitmap[BITMAP_SIZE]; 7 | 8 | #define IS_MAP_BIT_SET(pos) (m_bitmap[(pos) / INT_SIZE] & (1 << ((pos) % INT_SIZE))) 9 | #define MEM_BANK_ADDR SDRAM_BASE_BANK1 10 | 11 | void MemManager::init() 12 | { 13 | m_data = (uint8_t*)MEM_BANK_ADDR; 14 | memset((uint8_t*)m_bitmap, 0, sizeof(uint32_t) * BITMAP_SIZE); 15 | } 16 | 17 | void* MemManager::mem_allocate(int32_t size) 18 | { 19 | //caclulate blocks count need to allocate 20 | uint32_t need_chains = (size / RAM_SECTOR_SIZE) + ((size % RAM_SECTOR_SIZE) > 0 ? 1 : 0); 21 | //find free blocks chain 22 | for (uint32_t i=0 ; i (MEM_BANK_ADDR + STM32_SDRAM_SIZE_MB))) 76 | return; 77 | 78 | //calculate block index 79 | int block_idx = ((uint32_t)object - MEM_BANK_ADDR) / RAM_SECTOR_SIZE; 80 | while (IS_MAP_BIT_SET(block_idx)) 81 | { 82 | map_set_bit(block_idx, 0); 83 | ++block_idx; 84 | } 85 | } 86 | 87 | uint32_t MemManager::NumberOfSetBits(uint32_t i) 88 | { 89 | i = i - ((i >> 1) & 0x55555555); 90 | i = (i & 0x33333333) + ((i >> 2) & 0x33333333); 91 | return (((i + (i >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; 92 | } 93 | 94 | uint32_t MemManager::get_used_size() 95 | { 96 | uint32_t used = 0; 97 | for (uint32_t i=0 ; iACR |= FLASH_ACR_ICRST; 6 | FLASH->ACR &= ~FLASH_ACR_ICRST; 7 | } 8 | 9 | void STM32_FLASH::data_cache_reset() 10 | { 11 | FLASH->ACR |= FLASH_ACR_DCRST; 12 | FLASH->ACR &= ~FLASH_ACR_DCRST; 13 | } 14 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_flash.h: -------------------------------------------------------------------------------- 1 | #ifndef STM32_FLASH_H 2 | #define STM32_FLASH_H 3 | 4 | #include "stm32_conf.h" 5 | 6 | class STM32_FLASH 7 | { 8 | public: 9 | static inline void set_latency(uint8_t latency) { *((__IO uint8_t *)(FLASH_R_BASE + 0)) = latency; } 10 | static inline uint8_t get_latency() { return FLASH->ACR & FLASH_ACR_LATENCY; } 11 | 12 | ENDIS_REG_FLAG(prefetch_buffer, FLASH->ACR, FLASH_ACR_PRFTEN) 13 | ENDIS_REG_FLAG(instruction_cache, FLASH->ACR, FLASH_ACR_ICEN) 14 | ENDIS_REG_FLAG(data_cache, FLASH->ACR, FLASH_ACR_DCEN) 15 | 16 | static void instruction_cache_reset(); 17 | static void data_cache_reset(); 18 | }; 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_inc.h: -------------------------------------------------------------------------------- 1 | #ifndef STM32_INC_H 2 | #define STM32_INC_H 3 | 4 | #include "ISRstm32f429xx.h" 5 | #include "stm32_conf.h" 6 | #include "stm32_flash.h" 7 | #include "stm32_gpio.h" 8 | #include "stm32_nvic.h" 9 | #include "stm32_pwr.h" 10 | #include "stm32_rcc.h" 11 | #include "stm32_sdram.h" 12 | #include "stm32_systick.h" 13 | #include "stm32_uart.h" 14 | #include "stm32_sd.h" 15 | #include "stm32_spi.h" 16 | #include "stm32_rtc.h" 17 | #include "bitbanding.h" 18 | 19 | #define UNUSED(x) (void)(x) 20 | 21 | #endif // STM32_INC_H 22 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_nvic.cpp: -------------------------------------------------------------------------------- 1 | #include "stm32_inc.h" 2 | #include "plc_io.h" 3 | 4 | /* from core_cm4.h */ 5 | 6 | FORCE_INLINE uint32_t _NVIC_GetPriorityGrouping(void) 7 | { 8 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 9 | } 10 | 11 | FORCE_INLINE uint32_t _NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 12 | { 13 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 14 | uint32_t PreemptPriorityBits; 15 | uint32_t SubPriorityBits; 16 | 17 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? 18 | (uint32_t)(__NVIC_PRIO_BITS) : 19 | (uint32_t)(7UL - PriorityGroupTmp); 20 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? 21 | (uint32_t)0UL : 22 | (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 23 | 24 | return ( 25 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 26 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 27 | ); 28 | } 29 | 30 | void STM32_NVIC::init() 31 | { 32 | set_priority_grouping(NVIC_PRIORITYGROUP_4); 33 | set_priority(MemoryManagement_IRQn, 0, 0); 34 | set_priority(BusFault_IRQn, 0, 0); 35 | set_priority(UsageFault_IRQn, 0, 0); 36 | set_priority(SVCall_IRQn, 0, 0); 37 | set_priority(DebugMonitor_IRQn, 0, 0); 38 | set_priority(PendSV_IRQn, 0, 0); 39 | set_priority(SysTick_IRQn, 0, 0); 40 | set_priority(FLASH_IRQn, 0, 0); 41 | enable_IRQ(FLASH_IRQn); 42 | } 43 | 44 | void STM32_NVIC::init_vectors() 45 | { 46 | #ifdef STM32_USE_UART1 47 | enable_and_set_prior_IRQ(USART1_IRQn, 0, 0); 48 | #endif 49 | #ifdef STM32_USE_UART2 50 | enable_and_set_prior_IRQ(USART2_IRQn, 0, 0); 51 | #endif 52 | #ifdef STM32_USE_UART3 53 | enable_and_set_prior_IRQ(USART3_IRQn, 0, 0); 54 | #endif 55 | #ifdef STM32_USE_UART4 56 | enable_and_set_prior_IRQ(USART4_IRQn, 0, 0); 57 | #endif 58 | #ifdef STM32_USE_UART5 59 | enable_and_set_prior_IRQ(USART5_IRQn, 0, 0); 60 | #endif 61 | #ifdef STM32_USE_UART6 62 | enable_and_set_prior_IRQ(USART6_IRQn, 0, 0); 63 | #endif 64 | #ifdef STM32_USE_UART7 65 | enable_and_set_prior_IRQ(USART7_IRQn, 0, 0); 66 | #endif 67 | #ifdef STM32_USE_UART8 68 | enable_and_set_prior_IRQ(USART8_IRQn, 0, 0); 69 | #endif 70 | } 71 | 72 | void ISR::NMI() 73 | { 74 | //TODO 75 | } 76 | 77 | void ISR::MemManage() 78 | { 79 | Error_Handler(); 80 | } 81 | 82 | void ISR::BusFault() 83 | { 84 | Error_Handler(); 85 | } 86 | 87 | void ISR::UsageFault() 88 | { 89 | Error_Handler(); 90 | } 91 | 92 | void ISR::HardFault() 93 | { 94 | Error_Handler(); 95 | } 96 | 97 | void ISR::FLASH_IRQ() 98 | { 99 | //PLC_IO::pin_on_FAULT(); 100 | } 101 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_nvic.h: -------------------------------------------------------------------------------- 1 | #ifndef STM32_NVIC_H 2 | #define STM32_NVIC_H 3 | 4 | #include "stm32_conf.h" 5 | 6 | #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x07)/*!< 0 bits for pre-emption priority 7 | 4 bits for subpriority */ 8 | #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x06)/*!< 1 bits for pre-emption priority 9 | 3 bits for subpriority */ 10 | #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x05)/*!< 2 bits for pre-emption priority 11 | 2 bits for subpriority */ 12 | #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x04)/*!< 3 bits for pre-emption priority 13 | 1 bits for subpriority */ 14 | #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x03)/*!< 4 bits for pre-emption priority 15 | 0 bits for subpriority */ 16 | 17 | uint32_t _NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); 18 | uint32_t _NVIC_GetPriorityGrouping(void); 19 | 20 | class STM32_NVIC 21 | { 22 | public: 23 | static void init(); 24 | static void init_vectors(); 25 | 26 | static FORCE_INLINE void set_priority_grouping(uint32_t val) { NVIC_SetPriorityGrouping(val); } 27 | static FORCE_INLINE uint32_t get_priority_grouping() { return _NVIC_GetPriorityGrouping(); } 28 | 29 | static FORCE_INLINE uint32_t encode_priority(uint32_t group, uint32_t pre_prior, uint32_t sub_prior) 30 | { return NVIC_EncodePriority(group, pre_prior, sub_prior); } 31 | 32 | static FORCE_INLINE void set_priority(IRQn_Type irqn, uint32_t val) { NVIC_SetPriority(irqn, val); } 33 | static FORCE_INLINE void set_priority(IRQn_Type irqn, uint32_t prior, uint32_t subprior) 34 | { NVIC_SetPriority(irqn, 35 | _NVIC_EncodePriority(get_priority_grouping(), 36 | prior, subprior)); } 37 | static inline void enable_IRQ(IRQn_Type irqn) { NVIC_EnableIRQ(irqn); } 38 | static inline void disable_IRQ(IRQn_Type irqn) { NVIC_DisableIRQ(irqn); } 39 | static inline void enable_and_set_prior_IRQ(IRQn_Type irqn, uint32_t prior, uint32_t subprior) 40 | { set_priority(irqn, prior, subprior); 41 | enable_IRQ(irqn); } 42 | }; 43 | 44 | #endif // STM32_NVIC_H 45 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_sdram.h: -------------------------------------------------------------------------------- 1 | #ifndef STM32_SDRAM_H 2 | #define STM32_SDRAM_H 3 | 4 | #include "stm32_conf.h" 5 | 6 | #define SDRAM_BASE_BANK1 0xC0000000 7 | #define SDRAM_BASE_BANK2 0xD0000000 8 | 9 | #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U) 10 | #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U) 11 | #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U) 12 | #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U) 13 | 14 | #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U) 15 | #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U) 16 | #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U) 17 | 18 | #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 19 | #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) 20 | #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) 21 | 22 | #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U) 23 | #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U) 24 | 25 | #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U) 26 | #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U) 27 | #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U) 28 | 29 | #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U) 30 | #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U) 31 | 32 | #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U) 33 | #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U) 34 | #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U) 35 | 36 | #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U) 37 | #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U) 38 | 39 | #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U) 40 | #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U) 41 | #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U) 42 | 43 | #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U) 44 | #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U) 45 | #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U) 46 | #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U) 47 | #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U) 48 | #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U) 49 | #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U) 50 | 51 | #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 52 | #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 53 | #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U) 54 | 55 | #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U) 56 | #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 57 | #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 58 | 59 | class STM32_SDRAM 60 | { 61 | public: 62 | static void init_base(); 63 | static uint32_t init(); 64 | static uint32_t run_tests(uint32_t start_addr, uint32_t size, bool print_debug = true); 65 | private: 66 | static void init_gpio(); 67 | static void init_bank1(); 68 | static void init_bank2(); 69 | static void set_timing_bank1(); 70 | static void set_timing_bank2(); 71 | static uint32_t run_init_sequence(); 72 | static uint32_t send_comand(uint32_t mode, uint32_t target, uint32_t refresh, uint32_t mode_reg_def, uint32_t timeout); 73 | 74 | static inline void program_refresh_rate(uint32_t rate) { FMC_Bank5_6->SDRTR |= (rate << FMC_SDRTR_COUNT_Pos); } 75 | static inline void disable_write_protection(int bank) { MODIFY_REG(FMC_Bank5_6->SDCR[bank], FMC_SDCR1_WP, 0); } 76 | }; 77 | 78 | #endif // STM32_SDRAM_H 79 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_spi.h: -------------------------------------------------------------------------------- 1 | #ifndef STM32_SPI_H 2 | #define STM32_SPI_H 3 | 4 | #include "stm32_inc.h" 5 | 6 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ 7 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ 8 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ 9 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ 10 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ 11 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ 12 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ 13 | 14 | class STM32_SPI; 15 | 16 | typedef void(STM32_SPI::*callback_t)(); 17 | 18 | class STM32_SPI 19 | { 20 | public: 21 | static void init_all(); 22 | 23 | void init(); 24 | void irq(); 25 | 26 | uint32_t wait_busy(uint32_t timeout); 27 | 28 | uint32_t transmit(uint8_t* data, uint32_t size, TXRX_MODE mode, uint32_t timeout); 29 | uint32_t recieve(uint8_t* data, uint32_t size, TXRX_MODE mode, uint32_t timeout); 30 | uint32_t transmit_recieve(uint8_t* tx_buf, uint8_t* rx_buf, uint32_t size, TXRX_MODE mode, uint32_t timeout); 31 | 32 | ENDIS_REG_FLAG_(m_spi->CR1, SPI_CR1_SPE) 33 | inline uint32_t is_enabled() { return (m_spi->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE; } 34 | 35 | ENDIS_REG_FLAG_NAME(CRC, m_spi->CR1, SPI_CR1_CRCNEXT) 36 | 37 | inline void enable_IT(uint32_t mask) { m_spi->CR2 |= mask; } 38 | inline void disable_IT(uint32_t mask) { m_spi->CR2 &= ~mask; } 39 | 40 | inline bool get_flag(uint32_t flag_msk) { return ((m_spi->SR & flag_msk) == flag_msk); } 41 | inline void clear_ovrflag() { uint32_t tmp; tmp = m_spi->DR; tmp = m_spi->SR ; (void)(tmp); } 42 | inline void clear_CRCerror() { m_spi->SR &= ~SPI_FLAG_CRCERR; } 43 | 44 | inline void tx_1line() { m_spi->CR1 |= SPI_CR1_BIDIOE; } 45 | inline void rx_1line() { m_spi->CR1 &= ~SPI_CR1_BIDIOE; } 46 | 47 | inline uint32_t get_TXE() { return m_spi->SR & SPI_FLAG_TXE; } 48 | 49 | inline void crc_on() { m_spi->CR1 |= SPI_CR1_CRCEN; } 50 | inline void crc_off() { m_spi->CR1 &= ~SPI_CR1_CRCEN; } 51 | inline void crc_reset() { crc_off(); crc_on(); } 52 | private: 53 | SPI_TypeDef* m_spi; 54 | uint32_t m_busy; 55 | 56 | uint32_t m_mode; 57 | uint32_t m_direction; 58 | uint32_t m_data_size; 59 | uint32_t m_crc_calc; 60 | 61 | uint32_t m_tx_count; 62 | uint32_t m_tx_size; 63 | uint8_t *m_tx_buf; 64 | callback_t m_tx_call; 65 | 66 | uint32_t m_rx_count; 67 | uint32_t m_rx_size; 68 | uint8_t *m_rx_buf; 69 | callback_t m_rx_call; 70 | 71 | uint32_t transmit_blocked(uint8_t* data, uint32_t size, uint32_t timeout); 72 | uint32_t transmit_IT(uint8_t* data, uint32_t size); 73 | 74 | uint32_t recieve_blocked(uint8_t* data, uint32_t size, uint32_t timeout); 75 | uint32_t recieve_IT(uint8_t* data, uint32_t size); 76 | 77 | void callback_tx_8bit(); 78 | void callback_tx_16bit(); 79 | 80 | uint32_t close_tx_ISR(); 81 | }; 82 | 83 | extern STM32_SPI spi1; 84 | extern STM32_SPI spi2; 85 | extern STM32_SPI spi3; 86 | extern STM32_SPI spi4; 87 | extern STM32_SPI spi5; 88 | extern STM32_SPI spi6; 89 | 90 | #endif // STM32_SPI_H 91 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_systick.cpp: -------------------------------------------------------------------------------- 1 | #include "stm32_inc.h" 2 | #include "plc_io.h" 3 | 4 | volatile uint32_t STM32_SYSTICK::m_tick; 5 | 6 | void STM32_SYSTICK::init() 7 | { 8 | update_freq(); 9 | set_clock_source(SYSTICK_CLKSOURCE_HCLK); 10 | STM32_NVIC::set_priority(SysTick_IRQn, STM32_PRIORITY_SYSCLK, 0); 11 | m_tick = 0; 12 | } 13 | 14 | void STM32_SYSTICK::update_freq() 15 | { 16 | SysTick_Config(STM32_RCC::get_HCLK_freq() / 1000 - 1); 17 | set_clock_source(SYSTICK_CLKSOURCE_HCLK); 18 | } 19 | 20 | void STM32_SYSTICK::set_clock_source(uint32_t src) 21 | { 22 | if (src == SYSTICK_CLKSOURCE_HCLK) 23 | SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 24 | else 25 | SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 26 | } 27 | 28 | void STM32_SYSTICK::on_tick() 29 | { 30 | ++m_tick; 31 | PLC_IO::timer_proc(); 32 | } 33 | 34 | void STM32_SYSTICK::delay(__IO uint32_t delay_ms) 35 | { 36 | if (m_tick == 0) 37 | return; 38 | uint32_t tick_end = m_tick + delay_ms; 39 | while(m_tick < tick_end) {} 40 | } 41 | 42 | void ISR::SysTickTimer() 43 | { 44 | STM32_SYSTICK::on_tick(); 45 | } 46 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_systick.h: -------------------------------------------------------------------------------- 1 | #ifndef STM32_SYSTICK_H 2 | #define STM32_SYSTICK_H 3 | 4 | #include "stm32_conf.h" 5 | 6 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) 7 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) 8 | 9 | class STM32_SYSTICK 10 | { 11 | public: 12 | static void init(); 13 | static void update_freq(); 14 | static void set_clock_source(uint32_t src); 15 | 16 | static inline uint32_t get_tick() { return m_tick; } 17 | 18 | static void on_tick(); 19 | static void delay(__IO uint32_t delay_ms); 20 | 21 | static inline void suspend() { BIT_BAND_PER(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) = DISABLE; } 22 | static inline void resume() { BIT_BAND_PER(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) = ENABLE; } 23 | 24 | ENDIS_REG_FLAG(DBG_sleep_mode, DBGMCU->CR, DBGMCU_CR_DBG_SLEEP) 25 | ENDIS_REG_FLAG(DBG_stop_mode, DBGMCU->CR, DBGMCU_CR_DBG_SLEEP) 26 | ENDIS_REG_FLAG(DBG_standby_mode, DBGMCU->CR, DBGMCU_CR_DBG_SLEEP) 27 | ENDIS_REG_FLAG(compensation_cell, SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD) 28 | ENDIS_REG_FLAG(memory_swapping_bank, SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE) 29 | private: 30 | static volatile uint32_t m_tick; 31 | }; 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/stm32_uart.h: -------------------------------------------------------------------------------- 1 | #ifndef __STM32_UART__ 2 | #define __STM32_UART__ 3 | 4 | #include "stm32_inc.h" 5 | 6 | #define UART_BUF_SIZE 1024 7 | 8 | enum class UART_MODE 9 | { 10 | DIRECT, 11 | INTERRUPT, 12 | DMA, 13 | }; 14 | 15 | class STM32_UART 16 | { 17 | public: 18 | static void init_all(); 19 | void init_base(USART_TypeDef* uart); 20 | void init(uint32_t brate); 21 | 22 | void send_char(char ch); 23 | void send_str(const char *str, TXRX_MODE mode); 24 | void send_buf(const char *buf, int size, TXRX_MODE mode); 25 | 26 | void irq_proc(); 27 | private: 28 | USART_TypeDef* m_uart; 29 | uint32_t m_brate; 30 | volatile bool m_busy; 31 | 32 | void set_baud_rate(uint32_t brate); 33 | void set_config(); 34 | 35 | void recv_data(); 36 | void send_data(); 37 | 38 | char m_rx_buf[UART_BUF_SIZE]; 39 | int m_rx_size; 40 | int m_rx_pos; 41 | 42 | char m_tx_buf[UART_BUF_SIZE]; 43 | int m_tx_size; 44 | int m_tx_pos; 45 | }; 46 | 47 | extern STM32_UART uart1; 48 | extern STM32_UART uart2; 49 | extern STM32_UART uart3; 50 | extern STM32_UART uart4; 51 | extern STM32_UART uart5; 52 | extern STM32_UART uart6; 53 | extern STM32_UART uart7; 54 | extern STM32_UART uart8; 55 | 56 | #endif // __UART__ 57 | -------------------------------------------------------------------------------- /firmware/fw_cpu/platforms/stm32/xprintf.h: -------------------------------------------------------------------------------- 1 | /*------------------------------------------------------------------------*/ 2 | /* Universal string handler for user console interface (C)ChaN, 2011 */ 3 | /*------------------------------------------------------------------------*/ 4 | 5 | #ifndef _STRFUNC 6 | #define _STRFUNC 7 | 8 | #define _USE_XFUNC_OUT 1 /* 1: Use output functions */ 9 | #define _CR_CRLF 1 /* 1: Convert \n ==> \r\n in the output char */ 10 | 11 | #define _USE_XFUNC_IN 1 /* 1: Use input function */ 12 | #define _LINE_ECHO 1 /* 1: Echo back input chars in xgets function */ 13 | 14 | 15 | #if _USE_XFUNC_OUT 16 | void xputc (char c); 17 | void xputs (const char* str); 18 | void xprintf (const char* fmt, ...); 19 | void xsprintf (char* buff, const char* fmt, ...); 20 | void put_dump (const char *buff, unsigned long addr, int len, int width); 21 | #define DW_CHAR sizeof(char) 22 | #define DW_SHORT sizeof(short) 23 | #define DW_LONG sizeof(long) 24 | #endif 25 | 26 | #if _USE_XFUNC_IN 27 | #define xdev_in(func) xfunc_in = (unsigned char(*)(void))(func) 28 | extern unsigned char (*xfunc_in)(void); 29 | int xgets (char* buff, int len); 30 | int xfgets (unsigned char (*func)(void), char* buff, int len); 31 | int xatoi (char** str, long* res); 32 | #endif 33 | 34 | #endif 35 | -------------------------------------------------------------------------------- /firmware/fw_cpu/src/main.cpp: -------------------------------------------------------------------------------- 1 | #include "plc_control.h" 2 | #ifdef PLATFORM_STM32 3 | #include "stm32_inc.h" 4 | #include "my_func.h" 5 | #endif 6 | 7 | #ifdef PLATFORM_STM32 8 | //#define MEM_SPEED_TEST 9 | 10 | #ifdef MEM_SPEED_TEST 11 | #define TEST_CYCLES (1000 * 100) 12 | #define TEST_SIZE (1024) 13 | 14 | void test_mem_speed(uint8_t *mem, const char *title) 15 | { 16 | uint32_t ticks = STM32_SYSTICK::get_tick(); 17 | for (int i=0 ; itransmit(tx_data, tx_size, TXRX_MODE::DIRECT, timeout); 59 | #else 60 | #warning SPI transmit 61 | return 0; 62 | #endif 63 | } 64 | 65 | uint32_t PLCBus::transmit_recieve(uint8_t* tx_data, uint8_t* rx_data, uint32_t tx_size, uint32_t timeout) 66 | { 67 | #ifdef PLATFORM_STM32 68 | return m_spi->transmit_recieve(tx_data, rx_data, tx_size, TXRX_MODE::DIRECT, timeout); 69 | #else 70 | #warning SPI transmit+recieve 71 | return 0; 72 | #endif 73 | } 74 | -------------------------------------------------------------------------------- /firmware/fw_cpu/src/plc_hw.cpp: -------------------------------------------------------------------------------- 1 | #include "plc_hw.h" 2 | 3 | PLCHW plc_hw; 4 | 5 | PLCHW::PLCHW() 6 | : m_status_word (0) 7 | , m_local_top (0) 8 | , m_MCR (true) 9 | , m_nested_size (0) 10 | { 11 | m_MCR = true; 12 | m_local_top = 0; 13 | reset_status_word(); 14 | 15 | m_memory_area = new uint8_t[PLC_MEM_SIZE]; 16 | m_local_area = new uint8_t[PLC_LOCAL_SIZE]; 17 | m_dbs_area = new uint8_t[PLC_DB_MEM_SIZE]; 18 | m_inputs_area = new uint8_t[PLC_IO_SIZE]; 19 | m_outputs_area = new uint8_t[PLC_IO_SIZE]; 20 | 21 | m_memory = new PLCDataInterface(m_memory_area); 22 | m_local = new PLCDataInterface(m_local_area); 23 | m_dbs = new PLCDataInterface(m_dbs_area); 24 | m_inputs = new PLCDataInterface(m_inputs_area); 25 | m_outputs = new PLCDataInterface(m_outputs_area);; 26 | } 27 | 28 | void PLCHW::push_ACCU(int32_t val) 29 | { 30 | m_ACCU4.set(m_ACCU3.get()); 31 | m_ACCU3.set(m_ACCU2.get()); 32 | m_ACCU2.set(m_ACCU1.get()); 33 | m_ACCU1.set(val); 34 | } 35 | 36 | void PLCHW::push_ACCU(parameter_t* param) 37 | { 38 | m_ACCU4.set(m_ACCU3.get()); 39 | m_ACCU3.set(m_ACCU2.get()); 40 | m_ACCU2.set(m_ACCU1.get()); 41 | m_ACCU1.set(0); 42 | switch (param->get_size()) 43 | { 44 | case EDataSize::BIT: 45 | // unsupported 46 | break; 47 | case EDataSize::BYTE: 48 | m_ACCU1.set_lolo(param->read_byte()); 49 | break; 50 | case EDataSize::WORD: 51 | m_ACCU1.set_lo(param->read_word()); 52 | break; 53 | case EDataSize::DWORD: 54 | m_ACCU1.set(param->read_dword()); 55 | break; 56 | } 57 | } 58 | 59 | int32_t PLCHW::pop_ACCU() 60 | { 61 | int32_t val = m_ACCU1.get(); 62 | m_ACCU1.set(m_ACCU2.get()); 63 | m_ACCU2.set(m_ACCU3.get()); 64 | m_ACCU3.set(m_ACCU4.get()); 65 | return val; 66 | } 67 | 68 | void PLCHW::pop_ACCU(parameter_t* param) 69 | { 70 | switch (param->get_size()) 71 | { 72 | case EDataSize::BIT: 73 | // unsupported 74 | break; 75 | case EDataSize::BYTE: 76 | param->write_byte(m_ACCU1.get_lolo()); 77 | break; 78 | case EDataSize::WORD: 79 | param->write_word(m_ACCU1.get_lo()); 80 | break; 81 | case EDataSize::DWORD: 82 | param->write_dword(m_ACCU1.get()); 83 | break; 84 | } 85 | m_ACCU1.set(m_ACCU2.get()); 86 | m_ACCU2.set(m_ACCU3.get()); 87 | m_ACCU3.set(m_ACCU4.get()); 88 | } 89 | 90 | int32_t PLCHW::get_status_bit(uint32_t bit_mask) 91 | { 92 | return (m_status_word & bit_mask); 93 | } 94 | 95 | void PLCHW::set_status_bits(uint32_t bit_mask) 96 | { 97 | m_status_word |= bit_mask; 98 | } 99 | 100 | void PLCHW::set_reset_status_bits(uint32_t bit_mask, uint32_t values) 101 | { 102 | m_status_word = (m_status_word & (~(bit_mask & (~values)))) | (bit_mask & values); 103 | } 104 | 105 | void PLCHW::clear_status_bits(uint32_t bit_mask) 106 | { 107 | m_status_word &= ~bit_mask; 108 | } 109 | 110 | void PLCHW::reset_status_word() 111 | { 112 | m_status_word = 0; 113 | } 114 | 115 | void PLCHW::nested_push(ESTLCommand cmd) 116 | { 117 | if ((m_nested_size + 1) >= PLC_NESTED_DEPTH) 118 | { 119 | //TODO: exception 120 | return; 121 | } 122 | if (!PLCHW::get_status_bit(PLC_STATUS_NOT_FC_MASK)) 123 | m_nested_buf[m_nested_size++] = {cmd, 124 | PLC_STATUS_RLO_MASK | (m_status_word & PLC_STATUS_OR_MASK)}; 125 | else 126 | m_nested_buf[m_nested_size++] = {cmd, 127 | m_status_word & (PLC_STATUS_RLO_MASK | PLC_STATUS_OR_MASK)}; 128 | } 129 | 130 | nested_t PLCHW::nested_pop() 131 | { 132 | if (m_nested_size == 0) 133 | { 134 | //TODO: exception 135 | return {ESTLCommand::NOP_0, 0}; 136 | } 137 | return m_nested_buf[--m_nested_size]; 138 | } 139 | -------------------------------------------------------------------------------- /firmware/fw_cpu/src/plc_io.cpp: -------------------------------------------------------------------------------- 1 | #include "plc_io.h" 2 | #ifdef PLATFORM_STM32 3 | #include "ISRstm32f429xx.h" 4 | #include "stm32_rcc.h" 5 | #include "stm32_systick.h" 6 | #else 7 | #include 8 | #endif 9 | #include "plc_control.h" 10 | 11 | void PLC_IO::init() 12 | { 13 | #ifdef PLATFORM_STM32 14 | STM32_RCC::enable_clk_GPIOA(); 15 | gpioa.set_config(PIN_RUN | PIN_STP, 16 | GPIO_MODE_OUTPUT_PP, 0, GPIO_SPEED_FREQ_LOW, 17 | GPIO_NOPULL); 18 | STM32_RCC::enable_clk_GPIOB(); 19 | gpiob.set_config(PIN_PWR | PIN_ERR | PIN_FLT | PIN_CFL, 20 | GPIO_MODE_OUTPUT_PP, 0, GPIO_SPEED_FREQ_LOW, 21 | GPIO_NOPULL); 22 | STM32_RCC::enable_clk_GPIOD(); 23 | gpiod.set_config(PIN_RSB, 24 | GPIO_MODE_OUTPUT_PP, 0, GPIO_SPEED_FREQ_LOW, 25 | GPIO_NOPULL); 26 | #else 27 | #warning Init GPIO 28 | #endif 29 | pin_off_POWER(); 30 | pin_off_RUN(); 31 | pin_off_STOP(); 32 | pin_off_RS_BLINK(); 33 | pin_off_ERROR(); 34 | pin_off_FAULT(); 35 | pin_off_COM_FAULT(); 36 | } 37 | 38 | #ifdef PLATFORM_STM32 39 | void PLC_IO::pin_on_POWER() { gpiob.pin_ON(PIN_PWR); } 40 | void PLC_IO::pin_off_POWER() { gpiob.pin_OFF(PIN_PWR); } 41 | void PLC_IO::pin_on_RUN() { gpioa.pin_OFF(PIN_RUN); } 42 | void PLC_IO::pin_off_RUN() { gpioa.pin_ON(PIN_RUN); } 43 | void PLC_IO::pin_on_STOP() { gpioa.pin_OFF(PIN_STP); } 44 | void PLC_IO::pin_off_STOP() { gpioa.pin_ON(PIN_STP); } 45 | void PLC_IO::pin_on_RS_BLINK() { gpiob.pin_ON(PIN_RSB); } 46 | void PLC_IO::pin_off_RS_BLINK() { gpiob.pin_OFF(PIN_RSB); } 47 | void PLC_IO::pin_on_ERROR() { gpiob.pin_ON(PIN_ERR); } 48 | void PLC_IO::pin_off_ERROR() { gpiob.pin_OFF(PIN_ERR); } 49 | void PLC_IO::pin_on_FAULT() { gpiob.pin_ON(PIN_FLT); } 50 | void PLC_IO::pin_off_FAULT() { gpiob.pin_OFF(PIN_FLT); } 51 | void PLC_IO::pin_on_COM_FAULT() { gpiod.pin_ON(PIN_CFL); } 52 | void PLC_IO::pin_off_COM_FAULT() { gpiod.pin_OFF(PIN_CFL); } 53 | #else 54 | #warning GPIO proc 55 | void PLC_IO::pin_on_POWER() { } 56 | void PLC_IO::pin_off_POWER() { } 57 | void PLC_IO::pin_on_RUN() { } 58 | void PLC_IO::pin_off_RUN() { } 59 | void PLC_IO::pin_on_STOP() { } 60 | void PLC_IO::pin_off_STOP() { } 61 | void PLC_IO::pin_on_RS_BLINK() { } 62 | void PLC_IO::pin_off_RS_BLINK() { } 63 | void PLC_IO::pin_on_ERROR() { } 64 | void PLC_IO::pin_off_ERROR() { } 65 | void PLC_IO::pin_on_FAULT() { } 66 | void PLC_IO::pin_off_FAULT() { } 67 | void PLC_IO::pin_on_COM_FAULT() { } 68 | void PLC_IO::pin_off_COM_FAULT() { } 69 | #endif 70 | 71 | void PLC_IO::timer_proc() 72 | { 73 | pin_on_POWER(); 74 | 75 | #ifdef PLATFORM_STM32 76 | uint32_t ticks = STM32_SYSTICK::get_tick(); 77 | #else 78 | struct timespec ticks_str; 79 | clock_gettime(CLOCK_MONOTONIC, &ticks_str); 80 | uint32_t ticks = ticks_str.tv_sec * 1000 + ticks_str.tv_nsec / 1000000; 81 | #endif 82 | if (PLC_CONTROL::in_rs_blink()) 83 | { 84 | switch (ticks % 1000) 85 | { 86 | case 0: 87 | pin_on_RS_BLINK(); 88 | break; 89 | case 500: 90 | pin_off_RS_BLINK(); 91 | break; 92 | } 93 | } 94 | else 95 | pin_on_RS_BLINK(); 96 | 97 | if (!PLC_CONTROL::is_initialized()) 98 | { 99 | pin_on_STOP(); 100 | pin_on_FAULT(); 101 | return; 102 | } 103 | 104 | if (PLC_CONTROL::in_run()) 105 | pin_on_RUN(); 106 | else 107 | pin_off_RUN(); 108 | 109 | if (PLC_CONTROL::in_stop()) 110 | pin_on_STOP(); 111 | else 112 | pin_off_STOP(); 113 | 114 | switch (ticks % 1000) 115 | { 116 | case 0: 117 | if (PLC_CONTROL::in_fault()) 118 | pin_on_FAULT(); 119 | break; 120 | case 500: 121 | pin_off_FAULT(); 122 | break; 123 | } 124 | } 125 | -------------------------------------------------------------------------------- /firmware/fw_cpu/src/plc_mod.cpp: -------------------------------------------------------------------------------- 1 | #include "plc_mod.h" 2 | #ifdef PLATFORM_STM32 3 | #include "my_func.h" 4 | #include "stm32_spi.h" 5 | #else 6 | #include "plc_conf.h" 7 | #include 8 | #endif 9 | #include "plc_control.h" 10 | #include "plc_platform.h" 11 | 12 | PLC_MOD plc_mod_com; 13 | PLC_MOD plc_mod_ext; 14 | 15 | #define PLC_MOD_RESET_TIMEOUT 100 16 | #define PLC_MOD_DATA_TIMEOUT 500 17 | #define PLC_MOD_PKT_PAUSE 50 18 | 19 | void PLC_MOD::init(bool is_com) 20 | { 21 | m_bus_com = is_com; 22 | 23 | m_bus.init(m_bus_com); 24 | } 25 | 26 | void PLC_MOD::find_modules() 27 | { 28 | m_mod_count = 0; 29 | 30 | 31 | memset((uint8_t*)&m_pkt_send, 0, sizeof(plc_mod_pkt_t)); 32 | m_pkt_send.data_size = 0; 33 | m_pkt_send.request = EModRequest::GET_INFO; 34 | 35 | PLC_CONTROL::print_message("Get modules info (%s bus):\n", (m_bus_com ? "COM" : "EXT")); 36 | 37 | while (1) 38 | { 39 | // set target ID 40 | m_pkt_send.target_id = m_mod_count; 41 | m_pkt_recv.request = EModRequest::NONE; 42 | 43 | m_bus.unselect(); 44 | PLATFORM_DELAY_MS(PLC_MOD_RESET_TIMEOUT); 45 | m_bus.select(); 46 | m_bus.transmit((uint8_t*)&m_pkt_send, sizeof(plc_mod_pkt_t), 47 | PLC_MOD_DATA_TIMEOUT); 48 | PLATFORM_DELAY_MS(PLC_MOD_PKT_PAUSE); 49 | if ((m_bus.transmit_recieve((uint8_t*)&m_pkt_send, (uint8_t*)&m_pkt_recv, sizeof(plc_mod_pkt_t), 50 | PLC_MOD_DATA_TIMEOUT) != PLC_RESULT_OK) || 51 | (m_pkt_recv.request != EModRequest::GET_INFO)) 52 | break; 53 | 54 | print_module_info(&m_pkt_recv.info); 55 | // fill module info 56 | memcpy((uint8_t*)&m_modules[m_mod_count], (uint8_t*)&m_pkt_recv.info, 57 | sizeof(plc_mod_info_t)); 58 | 59 | ++m_mod_count; 60 | } 61 | #ifdef PLATFORM_STM32 62 | PLC_CONTROL::print_message("\tFinded %U modules\n", m_mod_count); 63 | #else 64 | PLC_CONTROL::print_message("\tFinded %i modules\n", m_mod_count); 65 | #endif 66 | } 67 | 68 | void PLC_MOD::print_module_info(plc_mod_info_t *mod) 69 | { 70 | 71 | PLC_CONTROL::print_message("\tModule: STM32-%08X-%02X:%02X-%02X:%02X\n", mod->type, 72 | mod->hw_version, mod->hw_version, 73 | mod->inputs, mod->outputs); 74 | } 75 | -------------------------------------------------------------------------------- /firmware/fw_cpu/src/plc_platform.cpp: -------------------------------------------------------------------------------- 1 | #include "plc_platform.h" 2 | 3 | #ifdef PLATFORM_STM32 4 | #else 5 | 6 | #include 7 | #include 8 | 9 | struct period_info 10 | { 11 | struct timespec next_period; 12 | long period_ns; 13 | }; 14 | 15 | static void inc_period(struct period_info *pinfo) 16 | { 17 | pinfo->next_period.tv_nsec += pinfo->period_ns; 18 | 19 | while (pinfo->next_period.tv_nsec >= 1000000000) 20 | { 21 | /* timespec nsec overflow */ 22 | pinfo->next_period.tv_sec++; 23 | pinfo->next_period.tv_nsec -= 1000000000; 24 | } 25 | } 26 | 27 | void rt_delay_ms(uint32_t ms) 28 | { 29 | struct period_info info; 30 | 31 | clock_gettime(CLOCK_MONOTONIC, &(info.next_period)); 32 | info.period_ns = ms * 1000000; 33 | inc_period(&info); 34 | /* for simplicity, ignoring possibilities of signal wakes */ 35 | clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &info.next_period, NULL); 36 | } 37 | 38 | int32_t load_file(char* fn, uint8_t* buf) 39 | { 40 | std::ifstream ifs(fn); 41 | if (ifs) 42 | { 43 | ifs.seekg (0, ifs.end); 44 | int32_t size = ifs.tellg(); 45 | ifs.seekg (0, ifs.beg); 46 | 47 | ifs.read((char*)buf, size); 48 | ifs.close(); 49 | 50 | return size; 51 | } 52 | else 53 | return -1; 54 | } 55 | 56 | #endif 57 | -------------------------------------------------------------------------------- /firmware/fw_cpu/src/plc_state.cpp: -------------------------------------------------------------------------------- 1 | #include "plc_state.h" 2 | #ifdef PLATFORM_STM32 3 | #include "stm32f4xx.h" 4 | #include "my_func.h" 5 | #else 6 | #include 7 | #include 8 | #endif 9 | 10 | uint32_t PLC_STATE::m_last_cycle_time[PLC_CYCLE_TIME_COUNT]; 11 | uint32_t PLC_STATE::m_last_cycle_time_idx; 12 | uint32_t PLC_STATE::m_last_cycle_time_avg; 13 | plc_datetime_t PLC_STATE::m_start_dt; 14 | plc_datetime_t PLC_STATE::m_current_dt; 15 | 16 | void PLC_STATE::init() 17 | { 18 | get_dt(&m_start_dt); 19 | m_current_dt = m_start_dt; 20 | memset((uint8_t*)m_last_cycle_time, 0, sizeof(uint32_t) * PLC_CYCLE_TIME_COUNT); 21 | m_last_cycle_time_idx = 0; 22 | m_last_cycle_time_avg = 0; 23 | } 24 | 25 | #define MSEC_MINUTE (1000*60) 26 | 27 | void PLC_STATE::update_ct() 28 | { 29 | uint32_t last_msec = ((((m_current_dt.hour * 60) + m_current_dt.min) * 60) + m_current_dt.sec) * 1000 + m_current_dt.msec; 30 | get_dt(&m_current_dt); 31 | uint32_t new_msec = ((((m_current_dt.hour * 60) + m_current_dt.min) * 60) + m_current_dt.sec) * 1000 + m_current_dt.msec; 32 | 33 | int32_t ct = new_msec - last_msec; 34 | if (ct >= 0) 35 | { 36 | if ((++m_last_cycle_time_idx) >= PLC_CYCLE_TIME_COUNT) 37 | m_last_cycle_time_idx = 0; 38 | m_last_cycle_time[m_last_cycle_time_idx] = ct; 39 | 40 | m_last_cycle_time_avg = 0; 41 | for (int i=0 ; iSSR; 51 | uint32_t tmpreg_tr = RTC->TR; 52 | uint32_t tmpreg_dr = RTC->DR; 53 | 54 | tmpreg_tr &= RTC_TR_RESERVED_MASK; 55 | dt->hour = RTC_Bcd2ToByte((tmpreg_tr & (RTC_TR_HT | RTC_TR_HU)) >> 16U); 56 | dt->min = RTC_Bcd2ToByte((tmpreg_tr & (RTC_TR_MNT | RTC_TR_MNU)) >>8U); 57 | dt->sec = RTC_Bcd2ToByte(tmpreg_tr & (RTC_TR_ST | RTC_TR_SU)); 58 | dt->msec = (1000 * (STM32_RTC_SYNC_PREDIV - ssr)) / (STM32_RTC_SYNC_PREDIV + 1); 59 | 60 | tmpreg_dr &= RTC_DR_RESERVED_MASK; 61 | dt->year = RTC_Bcd2ToByte((tmpreg_dr & (RTC_DR_YT | RTC_DR_YU)) >> 16U); 62 | dt->month = RTC_Bcd2ToByte((tmpreg_dr & (RTC_DR_MT | RTC_DR_MU)) >> 8U); 63 | dt->day = RTC_Bcd2ToByte(tmpreg_dr & (RTC_DR_DT | RTC_DR_DU)); 64 | #else 65 | std::time_t timev; 66 | time(&timev); 67 | std::tm* tm = localtime(&timev); 68 | 69 | struct timespec info; 70 | clock_gettime(CLOCK_MONOTONIC, &info); 71 | dt->msec = info.tv_nsec / 1000000; 72 | 73 | dt->hour = tm->tm_hour; 74 | dt->min = tm->tm_min; 75 | dt->sec = tm->tm_sec; 76 | 77 | dt->year = (1900 + tm->tm_year) % 100; 78 | dt->month = tm->tm_mon + 1; // start from 0 79 | dt->day = tm->tm_mday; 80 | #endif 81 | } 82 | -------------------------------------------------------------------------------- /firmware/fw_di16/fw_di16.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | File.Version=6 3 | KeepUserPlacement=false 4 | Mcu.Family=STM32F1 5 | Mcu.IP0=NVIC 6 | Mcu.IP1=RCC 7 | Mcu.IP2=SPI1 8 | Mcu.IP3=SYS 9 | Mcu.IPNb=4 10 | Mcu.Name=STM32F103C(8-B)Tx 11 | Mcu.Package=LQFP48 12 | Mcu.Pin0=PD0-OSC_IN 13 | Mcu.Pin1=PD1-OSC_OUT 14 | Mcu.Pin2=PA5 15 | Mcu.Pin3=PA6 16 | Mcu.Pin4=PA7 17 | Mcu.Pin5=PA13 18 | Mcu.Pin6=PA14 19 | Mcu.Pin7=VP_SYS_VS_Systick 20 | Mcu.PinsNb=8 21 | Mcu.UserConstants= 22 | Mcu.UserName=STM32F103C8Tx 23 | MxCube.Version=4.22.0 24 | MxDb.Version=DB.4.0.220 25 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true 26 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true 27 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true 28 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true 29 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true 30 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true 31 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 32 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true 33 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true 34 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true 35 | PA13.Mode=Serial_Wire 36 | PA13.Signal=SYS_JTMS-SWDIO 37 | PA14.Mode=Serial_Wire 38 | PA14.Signal=SYS_JTCK-SWCLK 39 | PA5.Mode=Full_Duplex_Slave 40 | PA5.Signal=SPI1_SCK 41 | PA6.Mode=Full_Duplex_Slave 42 | PA6.Signal=SPI1_MISO 43 | PA7.Mode=Full_Duplex_Slave 44 | PA7.Signal=SPI1_MOSI 45 | PCC.Checker=false 46 | PCC.Line=STM32F103 47 | PCC.MCU=STM32F103C(8-B)Tx 48 | PCC.PartNumber=STM32F103C8Tx 49 | PCC.Seq0=0 50 | PCC.Series=STM32F1 51 | PCC.Temperature=25 52 | PCC.Vdd=3.3 53 | PD0-OSC_IN.Locked=true 54 | PD0-OSC_IN.Signal=GPIO_Input 55 | PD1-OSC_OUT.Locked=true 56 | PD1-OSC_OUT.Signal=GPIO_Output 57 | PinOutPanel.RotationAngle=0 58 | ProjectManager.AskForMigrate=true 59 | ProjectManager.BackupPrevious=false 60 | ProjectManager.CompilerOptimize=2 61 | ProjectManager.ComputerToolchain=false 62 | ProjectManager.CoupleFile=false 63 | ProjectManager.CustomerFirmwarePackage=C\:/Users/User/STM32Cube/Repository/STM32Cube_FW_F1_V1.6.0 64 | ProjectManager.DefaultFWLocation=true 65 | ProjectManager.DeletePrevious=true 66 | ProjectManager.DeviceId=STM32F103C8Tx 67 | ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.6.0 68 | ProjectManager.FreePins=true 69 | ProjectManager.HalAssertFull=true 70 | ProjectManager.HeapSize=0x200 71 | ProjectManager.KeepUserCode=true 72 | ProjectManager.LastFirmware=true 73 | ProjectManager.LibraryCopy=1 74 | ProjectManager.PreviousToolchain= 75 | ProjectManager.ProjectBuild=false 76 | ProjectManager.ProjectFileName=fw_di16.ioc 77 | ProjectManager.ProjectName=fw_di16 78 | ProjectManager.StackSize=0x400 79 | ProjectManager.TargetToolchain=MDK-ARM V5 80 | ProjectManager.ToolChainLocation= 81 | ProjectManager.UnderRoot=false 82 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL,2-SystemClock_Config-RCC-false-HAL,3-MX_SPI1_Init-SPI1-false-HAL 83 | RCC.ADCFreqValue=32000000 84 | RCC.AHBFreq_Value=64000000 85 | RCC.APB1CLKDivider=RCC_HCLK_DIV2 86 | RCC.APB1Freq_Value=32000000 87 | RCC.APB1TimFreq_Value=64000000 88 | RCC.APB2Freq_Value=64000000 89 | RCC.APB2TimFreq_Value=64000000 90 | RCC.FCLKCortexFreq_Value=64000000 91 | RCC.FamilyName=M 92 | RCC.HCLKFreq_Value=64000000 93 | RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value 94 | RCC.MCOFreq_Value=64000000 95 | RCC.PLLCLKFreq_Value=64000000 96 | RCC.PLLMCOFreq_Value=32000000 97 | RCC.PLLMUL=RCC_PLL_MUL16 98 | RCC.SYSCLKFreq_VALUE=64000000 99 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 100 | RCC.TimSysFreq_Value=64000000 101 | RCC.USBFreq_Value=64000000 102 | SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 103 | SPI1.CalculateBaudRate=4.0 MBits/s 104 | SPI1.Direction=SPI_DIRECTION_2LINES 105 | SPI1.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate 106 | SPI1.Mode=SPI_MODE_SLAVE 107 | SPI1.VirtualType=VM_SLAVE 108 | VP_SYS_VS_Systick.Mode=SysTick 109 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 110 | board=fw_di16 111 | -------------------------------------------------------------------------------- /firmware/fw_di16/fw_di16.pro: -------------------------------------------------------------------------------- 1 | QT -= core gui opengl 2 | 3 | APP = fw_di16 4 | TARGET = fw_di16 5 | 6 | CONFIG += c++11 7 | 8 | QMAKE_LFLAGS = -T$$PWD/../cortex-m3/stm32f103c8.ld 9 | 10 | DEFINES += STM32F10X_MD STM32F103xB 11 | 12 | DESTDIR = ./ 13 | #unix:EXT = elf 14 | #win32:EXT = elf.exe 15 | 16 | win32:QMAKE_LFLAGS += -LC:/msys64/mingw32/lib/gcc/arm-none-eabi/5.4.1 17 | !win32:QMAKE_LFLAGS += -L/usr/lib/gcc/arm-none-eabi/7.1.0/ 18 | 19 | createlist.target = all 20 | createlist.commands += arm-none-eabi-objdump -S $${OUT_PWD}/$${APP}$${EXT} > $$join(APP,,,".lst") 21 | createlist.commands += && arm-none-eabi-objcopy -Obinary $${OUT_PWD}/$${APP}$${EXT} $${OUT_PWD}/$${APP}.bin 22 | !win32:createlist.commands += && arm-none-eabi-nm -nalS --size-sort $${OUT_PWD}/$${APP}$${EXT} | tail 23 | createlist.commands += && arm-none-eabi-size $${OUT_PWD}/$${APP}$${EXT} 24 | QMAKE_EXTRA_TARGETS += createlist 25 | 26 | INCLUDEPATH += ../shared/CMSIS/ ../shared/HAL/inc/ ../shared/inc/ ./inc/ 27 | 28 | HEADERS += \ 29 | ../shared/CMSIS/arm_common_tables.h \ 30 | ../shared/CMSIS/arm_const_structs.h \ 31 | ../shared/CMSIS/arm_math.h \ 32 | ../shared/CMSIS/cmsis_armcc.h \ 33 | ../shared/CMSIS/cmsis_armcc_V6.h \ 34 | ../shared/CMSIS/cmsis_gcc.h \ 35 | ../shared/CMSIS/core_cm0.h \ 36 | ../shared/CMSIS/core_cm0plus.h \ 37 | ../shared/CMSIS/core_cm3.h \ 38 | ../shared/CMSIS/core_cm4.h \ 39 | ../shared/CMSIS/core_cm7.h \ 40 | ../shared/CMSIS/core_cmFunc.h \ 41 | ../shared/CMSIS/core_cmInstr.h \ 42 | ../shared/CMSIS/core_cmSimd.h \ 43 | ../shared/CMSIS/core_sc000.h \ 44 | ../shared/CMSIS/core_sc300.h \ 45 | ../shared/CMSIS/stm32f1xx.h \ 46 | ../shared/CMSIS/stm32f103xb.h \ 47 | ../shared/CMSIS/system_stm32f1xx.h \ 48 | ../shared/HAL/inc/stm32f1xx_hal.h \ 49 | ../shared/HAL/inc/stm32f1xx_hal_cortex.h \ 50 | ../shared/HAL/inc/stm32f1xx_hal_def.h \ 51 | ../shared/HAL/inc/stm32f1xx_hal_dma.h \ 52 | ../shared/HAL/inc/stm32f1xx_hal_dma_ex.h \ 53 | ../shared/HAL/inc/stm32f1xx_hal_flash.h \ 54 | ../shared/HAL/inc/stm32f1xx_hal_flash_ex.h \ 55 | ../shared/HAL/inc/stm32f1xx_hal_gpio.h \ 56 | ../shared/HAL/inc/stm32f1xx_hal_gpio_ex.h \ 57 | ../shared/HAL/inc/stm32f1xx_hal_iwdg.h \ 58 | ../shared/HAL/inc/stm32f1xx_hal_pwr.h \ 59 | ../shared/HAL/inc/stm32f1xx_hal_rcc.h \ 60 | ../shared/HAL/inc/stm32f1xx_hal_rcc_ex.h \ 61 | ../shared/HAL/inc/stm32f1xx_hal_spi.h \ 62 | ../shared/HAL/inc/stm32f1xx_hal_tim.h \ 63 | ../shared/HAL/inc/stm32f1xx_hal_tim_ex.h \ 64 | ../shared/HAL/inc/Legacy/stm32_hal_legacy.h \ 65 | inc/main.h \ 66 | inc/stm32f1xx_hal_conf.h \ 67 | inc/stm32f1xx_it.h \ 68 | ../shared/inc/plc_mod.h \ 69 | inc/plc_conf.h \ 70 | inc/plc_mod_info.h \ 71 | ../shared/inc/my_func.h 72 | 73 | SOURCES += \ 74 | ../shared/HAL/src/stm32f1xx_hal.c \ 75 | ../shared/HAL/src/stm32f1xx_hal_cortex.c \ 76 | ../shared/HAL/src/stm32f1xx_hal_dma.c \ 77 | ../shared/HAL/src/stm32f1xx_hal_flash.c \ 78 | ../shared/HAL/src/stm32f1xx_hal_flash_ex.c \ 79 | ../shared/HAL/src/stm32f1xx_hal_gpio.c \ 80 | ../shared/HAL/src/stm32f1xx_hal_gpio_ex.c \ 81 | ../shared/HAL/src/stm32f1xx_hal_iwdg.c \ 82 | ../shared/HAL/src/stm32f1xx_hal_pwr.c \ 83 | ../shared/HAL/src/stm32f1xx_hal_rcc.c \ 84 | ../shared/HAL/src/stm32f1xx_hal_rcc_ex.c \ 85 | ../shared/HAL/src/stm32f1xx_hal_spi.c \ 86 | ../shared/HAL/src/stm32f1xx_hal_spi_ex.c \ 87 | ../shared/HAL/src/stm32f1xx_hal_tim.c \ 88 | ../shared/HAL/src/stm32f1xx_hal_tim_ex.c \ 89 | src/stm32f1xx_hal_msp.c \ 90 | src/stm32f1xx_it.c \ 91 | ../shared/CMSIS/system_stm32f1xx.c \ 92 | ../shared/CMSIS/startup_stm32f103xb.s \ 93 | ../shared/src/plc_mod.cpp \ 94 | src/main.cpp \ 95 | ../shared/src/my_func.cpp 96 | 97 | DISTFILES += 98 | -------------------------------------------------------------------------------- /firmware/fw_di16/inc/main.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * File Name : main.h 4 | * Description : This file contains the common defines of the application 5 | ****************************************************************************** 6 | ** This notice applies to any and all portions of this file 7 | * that are not between comment pairs USER CODE BEGIN and 8 | * USER CODE END. Other portions of this file, whether 9 | * inserted by the user or by software development tools 10 | * are owned by their respective copyright owners. 11 | * 12 | * COPYRIGHT(c) 2017 STMicroelectronics 13 | * 14 | * Redistribution and use in source and binary forms, with or without modification, 15 | * are permitted provided that the following conditions are met: 16 | * 1. Redistributions of source code must retain the above copyright notice, 17 | * this list of conditions and the following disclaimer. 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, 19 | * this list of conditions and the following disclaimer in the documentation 20 | * and/or other materials provided with the distribution. 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 22 | * may be used to endorse or promote products derived from this software 23 | * without specific prior written permission. 24 | * 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 | * 36 | ****************************************************************************** 37 | */ 38 | /* Define to prevent recursive inclusion -------------------------------------*/ 39 | #ifndef __MAIN_H 40 | #define __MAIN_H 41 | /* Includes ------------------------------------------------------------------*/ 42 | 43 | /* USER CODE BEGIN Includes */ 44 | 45 | /* USER CODE END Includes */ 46 | 47 | /* Private define ------------------------------------------------------------*/ 48 | 49 | #define DI0_Pin GPIO_PIN_13 50 | #define DI0_GPIO_Port GPIOC 51 | #define DI1_Pin GPIO_PIN_14 52 | #define DI1_GPIO_Port GPIOC 53 | #define DI2_Pin GPIO_PIN_15 54 | #define DI2_GPIO_Port GPIOC 55 | #define SEL_IN_Pin GPIO_PIN_0 56 | #define SEL_IN_GPIO_Port GPIOD 57 | #define SEL_OUT_Pin GPIO_PIN_1 58 | #define SEL_OUT_GPIO_Port GPIOD 59 | #define DI3_Pin GPIO_PIN_0 60 | #define DI3_GPIO_Port GPIOA 61 | #define DI4_Pin GPIO_PIN_1 62 | #define DI4_GPIO_Port GPIOA 63 | #define DI5_Pin GPIO_PIN_2 64 | #define DI5_GPIO_Port GPIOA 65 | #define DI6_Pin GPIO_PIN_3 66 | #define DI6_GPIO_Port GPIOA 67 | #define DI7_Pin GPIO_PIN_4 68 | #define DI7_GPIO_Port GPIOA 69 | #define DI8_Pin GPIO_PIN_12 70 | #define DI8_GPIO_Port GPIOB 71 | #define DI9_Pin GPIO_PIN_13 72 | #define DI9_GPIO_Port GPIOB 73 | #define DI10_Pin GPIO_PIN_14 74 | #define DI10_GPIO_Port GPIOB 75 | #define DI11_Pin GPIO_PIN_15 76 | #define DI11_GPIO_Port GPIOB 77 | #define DI12_Pin GPIO_PIN_8 78 | #define DI12_GPIO_Port GPIOA 79 | #define DI13_Pin GPIO_PIN_9 80 | #define DI13_GPIO_Port GPIOA 81 | #define DI14_Pin GPIO_PIN_10 82 | #define DI14_GPIO_Port GPIOA 83 | #define DI15_Pin GPIO_PIN_11 84 | #define DI15_GPIO_Port GPIOA 85 | 86 | /* USER CODE BEGIN Private defines */ 87 | 88 | /* USER CODE END Private defines */ 89 | 90 | void Error_Handler(); 91 | 92 | //#define Error_Handler() _Error_Handler(__FILE__, __LINE__) 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | #endif /* __MAIN_H */ 103 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 104 | -------------------------------------------------------------------------------- /firmware/fw_di16/inc/plc_conf.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_CONF_H 2 | #define PLC_CONF_H 3 | 4 | #define PLC_MODULE 5 | 6 | #include "stm32f1xx_hal.h" 7 | 8 | #endif // PLC_CONF_H 9 | -------------------------------------------------------------------------------- /firmware/fw_di16/inc/plc_mod_info.h: -------------------------------------------------------------------------------- 1 | const plc_mod_info_t mod_info = {type: PLC_MOD_TYPE_DI, 2 | hw_version: 1, 3 | fw_version: 1, 4 | inputs: 16, 5 | outputs: 0}; 6 | -------------------------------------------------------------------------------- /firmware/fw_di16/inc/stm32f1xx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_it.h 4 | * @brief This file contains the headers of the interrupt handlers. 5 | ****************************************************************************** 6 | * 7 | * COPYRIGHT(c) 2017 STMicroelectronics 8 | * 9 | * Redistribution and use in source and binary forms, with or without modification, 10 | * are permitted provided that the following conditions are met: 11 | * 1. Redistributions of source code must retain the above copyright notice, 12 | * this list of conditions and the following disclaimer. 13 | * 2. Redistributions in binary form must reproduce the above copyright notice, 14 | * this list of conditions and the following disclaimer in the documentation 15 | * and/or other materials provided with the distribution. 16 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 17 | * may be used to endorse or promote products derived from this software 18 | * without specific prior written permission. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | ****************************************************************************** 32 | */ 33 | 34 | /* Define to prevent recursive inclusion -------------------------------------*/ 35 | #ifndef __STM32F1xx_IT_H 36 | #define __STM32F1xx_IT_H 37 | 38 | #ifdef __cplusplus 39 | extern "C" { 40 | #endif 41 | 42 | /* Includes ------------------------------------------------------------------*/ 43 | /* Exported types ------------------------------------------------------------*/ 44 | /* Exported constants --------------------------------------------------------*/ 45 | /* Exported macro ------------------------------------------------------------*/ 46 | /* Exported functions ------------------------------------------------------- */ 47 | 48 | void NMI_Handler(void); 49 | void HardFault_Handler(void); 50 | void MemManage_Handler(void); 51 | void BusFault_Handler(void); 52 | void UsageFault_Handler(void); 53 | void SVC_Handler(void); 54 | void DebugMon_Handler(void); 55 | void PendSV_Handler(void); 56 | void SysTick_Handler(void); 57 | void DMA1_Channel2_IRQHandler(void); 58 | void DMA1_Channel3_IRQHandler(void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* __STM32F1xx_IT_H */ 65 | 66 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 67 | -------------------------------------------------------------------------------- /firmware/fw_di16/init.cpp: -------------------------------------------------------------------------------- 1 | #include "stm32_inc.h" 2 | #include "my_func.h" 3 | 4 | int main(); 5 | 6 | /* #define VECT_TAB_SRAM */ 7 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. 8 | This value must be a multiple of 0x200. */ 9 | 10 | // base initialization 11 | void base_init() 12 | { 13 | const uint32_t _RAM_Start = 0x20000000; 14 | memset((uint8_t*)&_RAM_Start, 0, 1024*16); 15 | 16 | STM32_RCC::deinit(); 17 | STM32_GPIO::init_all(); 18 | STM32_SYSTICK::init(); 19 | 20 | /* Configure the Vector Table location add offset address ------------------*/ 21 | #ifdef VECT_TAB_SRAM 22 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 23 | #else 24 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 25 | #endif 26 | 27 | #ifdef STM32F429xx 28 | #ifdef INSTRUCTION_CACHE_ENABLE 29 | STM32_FLASH::enable_instruction_cache(); 30 | #endif 31 | #endif 32 | 33 | STM32_NVIC::init(); 34 | } 35 | 36 | void SystemInit() 37 | { 38 | base_init(); 39 | 40 | /* GPIO initializations */ 41 | 42 | // system initialization 43 | //__enable_fault_irq(); 44 | //__enable_irq(); 45 | STM32_RCC::init(); 46 | STM32_SYSTICK::init(); 47 | 48 | /* Other IO and peripheral initializations */ 49 | 50 | /* Initialize interrupt vectors for a peripheral */ 51 | STM32_NVIC::init_vectors(); 52 | } 53 | 54 | #define INIT_SP() \ 55 | { \ 56 | __ASM volatile("mov r3, 0x08000000\n\r" \ 57 | "ldr sp, [r3, #0]\n\r" : : ); \ 58 | } \ 59 | 60 | void ISR::Reset() 61 | { 62 | INIT_SP(); 63 | SystemInit(); 64 | main(); 65 | } 66 | -------------------------------------------------------------------------------- /firmware/fw_di16/main.cpp: -------------------------------------------------------------------------------- 1 | #include "stm32_gpio.h" 2 | 3 | int main() 4 | { 5 | gpioa.set_config(GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | 6 | GPIO_PIN_4 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | 7 | GPIO_PIN_11, GPIO_MODE_INPUT, 0, GPIO_SPEED_FREQ_MEDIUM, 8 | GPIO_PULLUP); 9 | gpiob.set_config(GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15, 10 | GPIO_MODE_INPUT, 0, GPIO_SPEED_FREQ_MEDIUM, GPIO_PULLUP); 11 | gpioc.set_config(GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15, 12 | GPIO_MODE_INPUT, 0, GPIO_SPEED_FREQ_MEDIUM, GPIO_PULLUP); 13 | 14 | //UART::send_str("Hello world!~\n\r"); 15 | while (1) 16 | {} 17 | } 18 | 19 | void Error_Handler() 20 | { 21 | while (1) {} 22 | } 23 | -------------------------------------------------------------------------------- /firmware/fw_di16/system_stm32f10x.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /** @addtogroup CMSIS 23 | * @{ 24 | */ 25 | 26 | /** @addtogroup stm32f10x_system 27 | * @{ 28 | */ 29 | 30 | /** 31 | * @brief Define to prevent recursive inclusion 32 | */ 33 | #ifndef __SYSTEM_STM32F10X_H 34 | #define __SYSTEM_STM32F10X_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /** @addtogroup STM32F10x_System_Includes 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | 49 | /** @addtogroup STM32F10x_System_Exported_types 50 | * @{ 51 | */ 52 | 53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /firmware/shared/CMSIS/arm_const_structs.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 19. March 2015 5 | * $Revision: V.1.4.5 6 | * 7 | * Project: CMSIS DSP Library 8 | * Title: arm_const_structs.h 9 | * 10 | * Description: This file has constant structs that are initialized for 11 | * user convenience. For example, some can be given as 12 | * arguments to the arm_cfft_f32() function. 13 | * 14 | * Target Processor: Cortex-M4/Cortex-M3 15 | * 16 | * Redistribution and use in source and binary forms, with or without 17 | * modification, are permitted provided that the following conditions 18 | * are met: 19 | * - Redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer. 21 | * - Redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in 23 | * the documentation and/or other materials provided with the 24 | * distribution. 25 | * - Neither the name of ARM LIMITED nor the names of its contributors 26 | * may be used to endorse or promote products derived from this 27 | * software without specific prior written permission. 28 | * 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 33 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 35 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 39 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 | * POSSIBILITY OF SUCH DAMAGE. 41 | * -------------------------------------------------------------------- */ 42 | 43 | #ifndef _ARM_CONST_STRUCTS_H 44 | #define _ARM_CONST_STRUCTS_H 45 | 46 | #include "arm_math.h" 47 | #include "arm_common_tables.h" 48 | 49 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; 50 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; 51 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; 52 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; 53 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; 54 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; 55 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; 56 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; 57 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; 58 | 59 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; 60 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; 61 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; 62 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; 63 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; 64 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; 65 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; 66 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; 67 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; 68 | 69 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; 70 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; 71 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; 72 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; 73 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; 74 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; 75 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; 76 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; 77 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; 78 | 79 | #endif 80 | -------------------------------------------------------------------------------- /firmware/shared/CMSIS/core_cmFunc.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cmFunc.h 3 | * @brief CMSIS Cortex-M Core Function Access Header File 4 | * @version V4.30 5 | * @date 20. October 2015 6 | ******************************************************************************/ 7 | /* Copyright (c) 2009 - 2015 ARM LIMITED 8 | 9 | All rights reserved. 10 | Redistribution and use in source and binary forms, with or without 11 | modification, are permitted provided that the following conditions are met: 12 | - Redistributions of source code must retain the above copyright 13 | notice, this list of conditions and the following disclaimer. 14 | - Redistributions in binary form must reproduce the above copyright 15 | notice, this list of conditions and the following disclaimer in the 16 | documentation and/or other materials provided with the distribution. 17 | - Neither the name of ARM nor the names of its contributors may be used 18 | to endorse or promote products derived from this software without 19 | specific prior written permission. 20 | * 21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 | POSSIBILITY OF SUCH DAMAGE. 32 | ---------------------------------------------------------------------------*/ 33 | 34 | 35 | #if defined ( __ICCARM__ ) 36 | #pragma system_include /* treat file as system include file for MISRA check */ 37 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 38 | #pragma clang system_header /* treat file as system include file */ 39 | #endif 40 | 41 | #ifndef __CORE_CMFUNC_H 42 | #define __CORE_CMFUNC_H 43 | 44 | 45 | /* ########################### Core Function Access ########################### */ 46 | /** \ingroup CMSIS_Core_FunctionInterface 47 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 48 | @{ 49 | */ 50 | 51 | /*------------------ RealView Compiler -----------------*/ 52 | #if defined ( __CC_ARM ) 53 | #include "cmsis_armcc.h" 54 | 55 | /*------------------ ARM Compiler V6 -------------------*/ 56 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 57 | #include "cmsis_armcc_V6.h" 58 | 59 | /*------------------ GNU Compiler ----------------------*/ 60 | #elif defined ( __GNUC__ ) 61 | #include "cmsis_gcc.h" 62 | 63 | /*------------------ ICC Compiler ----------------------*/ 64 | #elif defined ( __ICCARM__ ) 65 | #include 66 | 67 | /*------------------ TI CCS Compiler -------------------*/ 68 | #elif defined ( __TMS470__ ) 69 | #include 70 | 71 | /*------------------ TASKING Compiler ------------------*/ 72 | #elif defined ( __TASKING__ ) 73 | /* 74 | * The CMSIS functions have been implemented as intrinsics in the compiler. 75 | * Please use "carm -?i" to get an up to date list of all intrinsics, 76 | * Including the CMSIS ones. 77 | */ 78 | 79 | /*------------------ COSMIC Compiler -------------------*/ 80 | #elif defined ( __CSMC__ ) 81 | #include 82 | 83 | #endif 84 | 85 | /*@} end of CMSIS_Core_RegAccFunctions */ 86 | 87 | #endif /* __CORE_CMFUNC_H */ 88 | -------------------------------------------------------------------------------- /firmware/shared/CMSIS/core_cmInstr.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cmInstr.h 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File 4 | * @version V4.30 5 | * @date 20. October 2015 6 | ******************************************************************************/ 7 | /* Copyright (c) 2009 - 2015 ARM LIMITED 8 | 9 | All rights reserved. 10 | Redistribution and use in source and binary forms, with or without 11 | modification, are permitted provided that the following conditions are met: 12 | - Redistributions of source code must retain the above copyright 13 | notice, this list of conditions and the following disclaimer. 14 | - Redistributions in binary form must reproduce the above copyright 15 | notice, this list of conditions and the following disclaimer in the 16 | documentation and/or other materials provided with the distribution. 17 | - Neither the name of ARM nor the names of its contributors may be used 18 | to endorse or promote products derived from this software without 19 | specific prior written permission. 20 | * 21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 | POSSIBILITY OF SUCH DAMAGE. 32 | ---------------------------------------------------------------------------*/ 33 | 34 | 35 | #if defined ( __ICCARM__ ) 36 | #pragma system_include /* treat file as system include file for MISRA check */ 37 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 38 | #pragma clang system_header /* treat file as system include file */ 39 | #endif 40 | 41 | #ifndef __CORE_CMINSTR_H 42 | #define __CORE_CMINSTR_H 43 | 44 | 45 | /* ########################## Core Instruction Access ######################### */ 46 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 47 | Access to dedicated instructions 48 | @{ 49 | */ 50 | 51 | /*------------------ RealView Compiler -----------------*/ 52 | #if defined ( __CC_ARM ) 53 | #include "cmsis_armcc.h" 54 | 55 | /*------------------ ARM Compiler V6 -------------------*/ 56 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 57 | #include "cmsis_armcc_V6.h" 58 | 59 | /*------------------ GNU Compiler ----------------------*/ 60 | #elif defined ( __GNUC__ ) 61 | #include "cmsis_gcc.h" 62 | 63 | /*------------------ ICC Compiler ----------------------*/ 64 | #elif defined ( __ICCARM__ ) 65 | #include 66 | 67 | /*------------------ TI CCS Compiler -------------------*/ 68 | #elif defined ( __TMS470__ ) 69 | #include 70 | 71 | /*------------------ TASKING Compiler ------------------*/ 72 | #elif defined ( __TASKING__ ) 73 | /* 74 | * The CMSIS functions have been implemented as intrinsics in the compiler. 75 | * Please use "carm -?i" to get an up to date list of all intrinsics, 76 | * Including the CMSIS ones. 77 | */ 78 | 79 | /*------------------ COSMIC Compiler -------------------*/ 80 | #elif defined ( __CSMC__ ) 81 | #include 82 | 83 | #endif 84 | 85 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 86 | 87 | #endif /* __CORE_CMINSTR_H */ 88 | -------------------------------------------------------------------------------- /firmware/shared/CMSIS/core_cmSimd.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cmSimd.h 3 | * @brief CMSIS Cortex-M SIMD Header File 4 | * @version V4.30 5 | * @date 20. October 2015 6 | ******************************************************************************/ 7 | /* Copyright (c) 2009 - 2015 ARM LIMITED 8 | 9 | All rights reserved. 10 | Redistribution and use in source and binary forms, with or without 11 | modification, are permitted provided that the following conditions are met: 12 | - Redistributions of source code must retain the above copyright 13 | notice, this list of conditions and the following disclaimer. 14 | - Redistributions in binary form must reproduce the above copyright 15 | notice, this list of conditions and the following disclaimer in the 16 | documentation and/or other materials provided with the distribution. 17 | - Neither the name of ARM nor the names of its contributors may be used 18 | to endorse or promote products derived from this software without 19 | specific prior written permission. 20 | * 21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 | POSSIBILITY OF SUCH DAMAGE. 32 | ---------------------------------------------------------------------------*/ 33 | 34 | 35 | #if defined ( __ICCARM__ ) 36 | #pragma system_include /* treat file as system include file for MISRA check */ 37 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 38 | #pragma clang system_header /* treat file as system include file */ 39 | #endif 40 | 41 | #ifndef __CORE_CMSIMD_H 42 | #define __CORE_CMSIMD_H 43 | 44 | #ifdef __cplusplus 45 | extern "C" { 46 | #endif 47 | 48 | 49 | /* ################### Compiler specific Intrinsics ########################### */ 50 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 51 | Access to dedicated SIMD instructions 52 | @{ 53 | */ 54 | 55 | /*------------------ RealView Compiler -----------------*/ 56 | #if defined ( __CC_ARM ) 57 | #include "cmsis_armcc.h" 58 | 59 | /*------------------ ARM Compiler V6 -------------------*/ 60 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 61 | #include "cmsis_armcc_V6.h" 62 | 63 | /*------------------ GNU Compiler ----------------------*/ 64 | #elif defined ( __GNUC__ ) 65 | #include "cmsis_gcc.h" 66 | 67 | /*------------------ ICC Compiler ----------------------*/ 68 | #elif defined ( __ICCARM__ ) 69 | #include 70 | 71 | /*------------------ TI CCS Compiler -------------------*/ 72 | #elif defined ( __TMS470__ ) 73 | #include 74 | 75 | /*------------------ TASKING Compiler ------------------*/ 76 | #elif defined ( __TASKING__ ) 77 | /* 78 | * The CMSIS functions have been implemented as intrinsics in the compiler. 79 | * Please use "carm -?i" to get an up to date list of all intrinsics, 80 | * Including the CMSIS ones. 81 | */ 82 | 83 | /*------------------ COSMIC Compiler -------------------*/ 84 | #elif defined ( __CSMC__ ) 85 | #include 86 | 87 | #endif 88 | 89 | /*@} end of group CMSIS_SIMD_intrinsics */ 90 | 91 | 92 | #ifdef __cplusplus 93 | } 94 | #endif 95 | 96 | #endif /* __CORE_CMSIMD_H */ 97 | -------------------------------------------------------------------------------- /firmware/shared/CMSIS/stm32f100xb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/andreili/STM32-PLC/b3e8cc85b282cb704f58ced873d7859212706f31/firmware/shared/CMSIS/stm32f100xb.h -------------------------------------------------------------------------------- /firmware/shared/CMSIS/stm32f103xb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/andreili/STM32-PLC/b3e8cc85b282cb704f58ced873d7859212706f31/firmware/shared/CMSIS/stm32f103xb.h -------------------------------------------------------------------------------- /firmware/shared/CMSIS/stm32f1xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/andreili/STM32-PLC/b3e8cc85b282cb704f58ced873d7859212706f31/firmware/shared/CMSIS/stm32f1xx.h -------------------------------------------------------------------------------- /firmware/shared/CMSIS/stm32f4xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/andreili/STM32-PLC/b3e8cc85b282cb704f58ced873d7859212706f31/firmware/shared/CMSIS/stm32f4xx.h -------------------------------------------------------------------------------- /firmware/shared/CMSIS/system_stm32f1xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V4.2.0 6 | * @date 31-March-2017 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT(c) 2017 STMicroelectronics

12 | * 13 | * Redistribution and use in source and binary forms, with or without modification, 14 | * are permitted provided that the following conditions are met: 15 | * 1. Redistributions of source code must retain the above copyright notice, 16 | * this list of conditions and the following disclaimer. 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, 18 | * this list of conditions and the following disclaimer in the documentation 19 | * and/or other materials provided with the distribution. 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 | * may be used to endorse or promote products derived from this software 22 | * without specific prior written permission. 23 | * 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 | * 35 | ****************************************************************************** 36 | */ 37 | 38 | /** @addtogroup CMSIS 39 | * @{ 40 | */ 41 | 42 | /** @addtogroup stm32f10x_system 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief Define to prevent recursive inclusion 48 | */ 49 | #ifndef __SYSTEM_STM32F10X_H 50 | #define __SYSTEM_STM32F10X_H 51 | 52 | #ifdef __cplusplus 53 | extern "C" { 54 | #endif 55 | 56 | /** @addtogroup STM32F10x_System_Includes 57 | * @{ 58 | */ 59 | 60 | /** 61 | * @} 62 | */ 63 | 64 | 65 | /** @addtogroup STM32F10x_System_Exported_types 66 | * @{ 67 | */ 68 | 69 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 70 | extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ 71 | extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @addtogroup STM32F10x_System_Exported_Constants 78 | * @{ 79 | */ 80 | 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @addtogroup STM32F10x_System_Exported_Macros 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @addtogroup STM32F10x_System_Exported_Functions 94 | * @{ 95 | */ 96 | 97 | extern void SystemInit(void); 98 | extern void SystemCoreClockUpdate(void); 99 | /** 100 | * @} 101 | */ 102 | 103 | #ifdef __cplusplus 104 | } 105 | #endif 106 | 107 | #endif /*__SYSTEM_STM32F10X_H */ 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 117 | -------------------------------------------------------------------------------- /firmware/shared/CMSIS/system_stm32f4xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.h 4 | * @author MCD Application Team 5 | * @version V2.6.0 6 | * @date 04-November-2016 7 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT(c) 2016 STMicroelectronics

12 | * 13 | * Redistribution and use in source and binary forms, with or without modification, 14 | * are permitted provided that the following conditions are met: 15 | * 1. Redistributions of source code must retain the above copyright notice, 16 | * this list of conditions and the following disclaimer. 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, 18 | * this list of conditions and the following disclaimer in the documentation 19 | * and/or other materials provided with the distribution. 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 | * may be used to endorse or promote products derived from this software 22 | * without specific prior written permission. 23 | * 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 | * 35 | ****************************************************************************** 36 | */ 37 | 38 | /** @addtogroup CMSIS 39 | * @{ 40 | */ 41 | 42 | /** @addtogroup stm32f4xx_system 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief Define to prevent recursive inclusion 48 | */ 49 | #ifndef __SYSTEM_STM32F4XX_H 50 | #define __SYSTEM_STM32F4XX_H 51 | 52 | #ifdef __cplusplus 53 | extern "C" { 54 | #endif 55 | 56 | /** @addtogroup STM32F4xx_System_Includes 57 | * @{ 58 | */ 59 | 60 | /** 61 | * @} 62 | */ 63 | 64 | 65 | /** @addtogroup STM32F4xx_System_Exported_types 66 | * @{ 67 | */ 68 | /* This variable is updated in three ways: 69 | 1) by calling CMSIS function SystemCoreClockUpdate() 70 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 71 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 72 | Note: If you use this function to configure the system clock; then there 73 | is no need to call the 2 first functions listed above, since SystemCoreClock 74 | variable is updated automatically. 75 | */ 76 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 77 | 78 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 79 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 80 | 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @addtogroup STM32F4xx_System_Exported_Constants 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @addtogroup STM32F4xx_System_Exported_Macros 94 | * @{ 95 | */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** @addtogroup STM32F4xx_System_Exported_Functions 102 | * @{ 103 | */ 104 | 105 | extern void SystemInit(void); 106 | extern void SystemCoreClockUpdate(void); 107 | /** 108 | * @} 109 | */ 110 | 111 | #ifdef __cplusplus 112 | } 113 | #endif 114 | 115 | #endif /*__SYSTEM_STM32F4XX_H */ 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 125 | -------------------------------------------------------------------------------- /firmware/shared/Third_Party/FatFs/src/integer.h: -------------------------------------------------------------------------------- 1 | /*-------------------------------------------*/ 2 | /* Integer type definitions for FatFs module */ 3 | /*-------------------------------------------*/ 4 | 5 | #ifndef _FF_INTEGER 6 | #define _FF_INTEGER 7 | 8 | #ifdef _WIN32 /* FatFs development platform */ 9 | 10 | #include 11 | #include 12 | 13 | #else /* Embedded platform */ 14 | 15 | /* This type MUST be 8 bit */ 16 | typedef unsigned char BYTE; 17 | 18 | /* These types MUST be 16 bit */ 19 | typedef short SHORT; 20 | typedef unsigned short WORD; 21 | typedef unsigned short WCHAR; 22 | 23 | /* These types MUST be 16 bit or 32 bit */ 24 | typedef int INT; 25 | typedef unsigned int UINT; 26 | 27 | /* These types MUST be 32 bit */ 28 | typedef long LONG; 29 | typedef unsigned long DWORD; 30 | 31 | #endif 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /firmware/shared/Third_Party/FatFs/src/option/syscall.c: -------------------------------------------------------------------------------- 1 | /*------------------------------------------------------------------------*/ 2 | /* Sample code of OS dependent controls for FatFs */ 3 | /* (C)ChaN, 2014 */ 4 | /*------------------------------------------------------------------------*/ 5 | 6 | #include /* ANSI memory controls */ 7 | #include "../ff.h" 8 | 9 | #if _FS_REENTRANT 10 | /*----------------------------------------------------------------------- 11 | Create a Synchronization Object 12 | ------------------------------------------------------------------------ 13 | This function is called in f_mount function to create a new 14 | synchronization object, such as semaphore and mutex. When a zero is 15 | returned, the f_mount function fails with FR_INT_ERR. 16 | */ 17 | 18 | int ff_cre_syncobj ( /* TRUE:Function succeeded, FALSE:Could not create due to any error */ 19 | BYTE vol, /* Corresponding logical drive being processed */ 20 | _SYNC_t *sobj /* Pointer to return the created sync object */ 21 | ) 22 | { 23 | int ret; 24 | 25 | osSemaphoreDef(SEM); 26 | *sobj = osSemaphoreCreate(osSemaphore(SEM), 1); 27 | ret = (*sobj != NULL); 28 | 29 | return ret; 30 | } 31 | 32 | 33 | 34 | /*------------------------------------------------------------------------*/ 35 | /* Delete a Synchronization Object */ 36 | /*------------------------------------------------------------------------*/ 37 | /* This function is called in f_mount function to delete a synchronization 38 | / object that created with ff_cre_syncobj function. When a zero is 39 | / returned, the f_mount function fails with FR_INT_ERR. 40 | */ 41 | 42 | int ff_del_syncobj ( /* TRUE:Function succeeded, FALSE:Could not delete due to any error */ 43 | _SYNC_t sobj /* Sync object tied to the logical drive to be deleted */ 44 | ) 45 | { 46 | osSemaphoreDelete (sobj); 47 | return 1; 48 | } 49 | 50 | 51 | 52 | /*------------------------------------------------------------------------*/ 53 | /* Request Grant to Access the Volume */ 54 | /*------------------------------------------------------------------------*/ 55 | /* This function is called on entering file functions to lock the volume. 56 | / When a zero is returned, the file function fails with FR_TIMEOUT. 57 | */ 58 | 59 | int ff_req_grant ( /* TRUE:Got a grant to access the volume, FALSE:Could not get a grant */ 60 | _SYNC_t sobj /* Sync object to wait */ 61 | ) 62 | { 63 | int ret = 0; 64 | 65 | if(osSemaphoreWait(sobj, _FS_TIMEOUT) == osOK) 66 | { 67 | ret = 1; 68 | } 69 | 70 | return ret; 71 | } 72 | 73 | 74 | 75 | /*------------------------------------------------------------------------*/ 76 | /* Release Grant to Access the Volume */ 77 | /*------------------------------------------------------------------------*/ 78 | /* This function is called on leaving file functions to unlock the volume. 79 | */ 80 | 81 | void ff_rel_grant ( 82 | _SYNC_t sobj /* Sync object to be signaled */ 83 | ) 84 | { 85 | osSemaphoreRelease(sobj); 86 | } 87 | 88 | #endif 89 | 90 | 91 | 92 | 93 | #if _USE_LFN == 3 /* LFN with a working buffer on the heap */ 94 | /*------------------------------------------------------------------------*/ 95 | /* Allocate a memory block */ 96 | /*------------------------------------------------------------------------*/ 97 | /* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE. 98 | */ 99 | 100 | void* ff_memalloc ( /* Returns pointer to the allocated memory block */ 101 | UINT msize /* Number of bytes to allocate */ 102 | ) 103 | { 104 | return malloc(msize); /* Allocate a new memory block with POSIX API */ 105 | } 106 | 107 | 108 | /*------------------------------------------------------------------------*/ 109 | /* Free a memory block */ 110 | /*------------------------------------------------------------------------*/ 111 | 112 | void ff_memfree ( 113 | void* mblock /* Pointer to the memory block to free */ 114 | ) 115 | { 116 | free(mblock); /* Discard the memory block with POSIX API */ 117 | } 118 | 119 | #endif 120 | -------------------------------------------------------------------------------- /firmware/shared/Third_Party/FatFs/src/option/unicode.c: -------------------------------------------------------------------------------- 1 | #include "../ff.h" 2 | 3 | #if _USE_LFN != 0 4 | 5 | #if _CODE_PAGE == 932 /* Japanese Shift_JIS */ 6 | #include "cc932.c" 7 | #elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ 8 | #include "cc936.c" 9 | #elif _CODE_PAGE == 949 /* Korean */ 10 | #include "cc949.c" 11 | #elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ 12 | #include "cc950.c" 13 | #else /* Single Byte Character-Set */ 14 | #include "ccsbcs.c" 15 | #endif 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /firmware/shared/inc/bitbanding.h: -------------------------------------------------------------------------------- 1 | #ifndef BITBANDING_H 2 | #define BITBANDING_H 3 | 4 | #define MASK_TO_BIT31(A) (A==0x80000000)? 31 : 0 5 | #define MASK_TO_BIT30(A) (A==0x40000000)? 30 : MASK_TO_BIT31(A) 6 | #define MASK_TO_BIT29(A) (A==0x20000000)? 29 : MASK_TO_BIT30(A) 7 | #define MASK_TO_BIT28(A) (A==0x10000000)? 28 : MASK_TO_BIT29(A) 8 | #define MASK_TO_BIT27(A) (A==0x08000000)? 27 : MASK_TO_BIT28(A) 9 | #define MASK_TO_BIT26(A) (A==0x04000000)? 26 : MASK_TO_BIT27(A) 10 | #define MASK_TO_BIT25(A) (A==0x02000000)? 25 : MASK_TO_BIT26(A) 11 | #define MASK_TO_BIT24(A) (A==0x01000000)? 24 : MASK_TO_BIT25(A) 12 | #define MASK_TO_BIT23(A) (A==0x00800000)? 23 : MASK_TO_BIT24(A) 13 | #define MASK_TO_BIT22(A) (A==0x00400000)? 22 : MASK_TO_BIT23(A) 14 | #define MASK_TO_BIT21(A) (A==0x00200000)? 21 : MASK_TO_BIT22(A) 15 | #define MASK_TO_BIT20(A) (A==0x00100000)? 20 : MASK_TO_BIT21(A) 16 | #define MASK_TO_BIT19(A) (A==0x00080000)? 19 : MASK_TO_BIT20(A) 17 | #define MASK_TO_BIT18(A) (A==0x00040000)? 18 : MASK_TO_BIT19(A) 18 | #define MASK_TO_BIT17(A) (A==0x00020000)? 17 : MASK_TO_BIT18(A) 19 | #define MASK_TO_BIT16(A) (A==0x00010000)? 16 : MASK_TO_BIT17(A) 20 | #define MASK_TO_BIT15(A) (A==0x00008000)? 15 : MASK_TO_BIT16(A) 21 | #define MASK_TO_BIT14(A) (A==0x00004000)? 14 : MASK_TO_BIT15(A) 22 | #define MASK_TO_BIT13(A) (A==0x00002000)? 13 : MASK_TO_BIT14(A) 23 | #define MASK_TO_BIT12(A) (A==0x00001000)? 12 : MASK_TO_BIT13(A) 24 | #define MASK_TO_BIT11(A) (A==0x00000800)? 11 : MASK_TO_BIT12(A) 25 | #define MASK_TO_BIT10(A) (A==0x00000400)? 10 : MASK_TO_BIT11(A) 26 | #define MASK_TO_BIT09(A) (A==0x00000200)? 9 : MASK_TO_BIT10(A) 27 | #define MASK_TO_BIT08(A) (A==0x00000100)? 8 : MASK_TO_BIT09(A) 28 | #define MASK_TO_BIT07(A) (A==0x00000080)? 7 : MASK_TO_BIT08(A) 29 | #define MASK_TO_BIT06(A) (A==0x00000040)? 6 : MASK_TO_BIT07(A) 30 | #define MASK_TO_BIT05(A) (A==0x00000020)? 5 : MASK_TO_BIT06(A) 31 | #define MASK_TO_BIT04(A) (A==0x00000010)? 4 : MASK_TO_BIT05(A) 32 | #define MASK_TO_BIT03(A) (A==0x00000008)? 3 : MASK_TO_BIT04(A) 33 | #define MASK_TO_BIT02(A) (A==0x00000004)? 2 : MASK_TO_BIT03(A) 34 | #define MASK_TO_BIT01(A) (A==0x00000002)? 1 : MASK_TO_BIT02(A) 35 | #define MASK_TO_BIT(A) (A==0x00000001)? 0 : MASK_TO_BIT01(A) 36 | 37 | #ifndef SET 38 | #define SET 1 39 | #define RESET 0 40 | #endif 41 | 42 | #define BIT_BAND_PER(REG,BIT_MASK) (*(volatile uint32_t*)(PERIPH_BB_BASE+32*((uint32_t)(&(REG))-PERIPH_BASE)+4*((uint32_t)(MASK_TO_BIT(BIT_MASK))))) 43 | 44 | #define BIT_BAND_SRAM(RAM,BIT) (*(volatile uint32_t*)(SRAM_BB_BASE+32*((uint32_t)((void*)(RAM))-SRAM_BASE)+4*((uint32_t)(BIT)))) 45 | 46 | //Example: BIT_BAND_PER(TIM1->SR, TIM_SR_UIF) = 0; //сбросить бит TIM_SR_UIF в TIM1->SR 47 | //Example2: BIT_BAND_SRAM(&a, 13) = 1; //установить 13-й бит в переменной "a" 48 | //Example3: BIT_BAND_SRAM(&a, 13) ^= 1; //инвертировать 13-й бит в "a", не задевая другие биты переменной (псевдо-атомарность) 49 | #endif 50 | -------------------------------------------------------------------------------- /firmware/shared/inc/my_func.h: -------------------------------------------------------------------------------- 1 | #ifndef __MY_FUNC__ 2 | #define __MY_FUNC__ 3 | 4 | #include 5 | 6 | int strlen(const char* str); 7 | void memcpy(uint8_t* dst, const uint8_t* src, uint32_t len); 8 | void memset(uint8_t* dst,char val, uint32_t len); 9 | int memcmp(const uint8_t *s1, const uint8_t *s2, uint32_t len); 10 | 11 | #endif //__MY_FUNC__ 12 | -------------------------------------------------------------------------------- /firmware/shared/inc/plc_mod.h: -------------------------------------------------------------------------------- 1 | #ifndef PLC_MOD_H 2 | #define PLC_MOD_H 3 | 4 | #include 5 | #include "plc_conf.h" 6 | 7 | #define PLC_MOD_TYPE_CPU (0x01 << 0x01) 8 | #define PLC_MOD_TYPE_PN (0x01 << 0x02) 9 | #define PLC_MOD_TYPE_PB (0x01 << 0x03) 10 | #define PLC_MOD_TYPE_DI (0x01 << 0x04) 11 | #define PLC_MOD_TYPE_DO (0x01 << 0x05) 12 | #define PLC_MOD_TYPE_AI (0x01 << 0x06) 13 | #define PLC_MOD_TYPE_AO (0x01 << 0x07) 14 | 15 | #define PLC_MOD_ADDR_MAX_DISCRET 16 16 | #define PLC_MOD_ADDR_MAX_ANALOG 8 17 | #define PLC_MOD_ADDR_MAX_COM 200 18 | 19 | #define PLC_MOD_TARGET_ALL 0xffff 20 | 21 | #define PLC_MOD_MAX_MODULES 32 22 | 23 | typedef struct 24 | { 25 | uint32_t type; 26 | uint32_t hw_version; 27 | uint32_t fw_version; 28 | uint32_t inputs; 29 | uint32_t outputs; 30 | } plc_mod_info_t; 31 | 32 | enum class EModRequest : uint32_t 33 | { 34 | NONE = 0, 35 | GET_INFO = 1, 36 | }; 37 | 38 | typedef struct 39 | { 40 | uint32_t target_id; 41 | uint32_t data_size; 42 | EModRequest request; 43 | union 44 | { 45 | uint8_t discret[PLC_MOD_ADDR_MAX_DISCRET]; 46 | uint16_t analog[PLC_MOD_ADDR_MAX_ANALOG]; 47 | uint8_t com[PLC_MOD_ADDR_MAX_COM]; 48 | plc_mod_info_t info; 49 | }; 50 | } plc_mod_pkt_t; 51 | 52 | #ifdef PLC_CPU 53 | class STM32_SPI; 54 | #endif 55 | 56 | class PLC_MOD 57 | { 58 | public: 59 | #ifdef PLC_CPU 60 | void init(STM32_SPI *spi, bool is_com); 61 | void find_modules(); 62 | #else 63 | void init(SPI_HandleTypeDef *spi); 64 | void init_seq(); 65 | #endif 66 | private: 67 | #ifdef PLC_CPU 68 | STM32_SPI *m_spi; 69 | #else 70 | SPI_HandleTypeDef *m_spi; 71 | #endif 72 | plc_mod_pkt_t m_pkt_send; 73 | plc_mod_pkt_t m_pkt_recv; 74 | 75 | #ifdef PLC_CPU 76 | bool m_bus_com; 77 | uint32_t m_mod_count; 78 | 79 | plc_mod_info_t m_modules[PLC_MOD_MAX_MODULES]; 80 | 81 | void CS_on(); 82 | void CS_off(); 83 | 84 | void print_module_info(plc_mod_info_t *mod); 85 | 86 | #else 87 | 88 | bool init_seq_get_req(); 89 | void init_seq_send_info(); 90 | 91 | //inline bool is_CSin_on() { return ((SEL_IN_GPIO_Port->IDR & SEL_IN_Pin) != SEL_IN_Pin); } 92 | void CSout_on(); 93 | void CSout_off(); 94 | 95 | #endif 96 | }; 97 | 98 | #ifdef PLC_CPU 99 | extern PLC_MOD plc_mod_com; 100 | extern PLC_MOD plc_mod_ext; 101 | #else 102 | extern PLC_MOD plc_mod; 103 | #endif 104 | 105 | #endif // PLC_MOD_H 106 | -------------------------------------------------------------------------------- /firmware/shared/src/ISRstm32f10x_md.cpp: -------------------------------------------------------------------------------- 1 | 2 | /********************************************************* 3 | * ISRstm32f10x_md.cpp 4 | * Automatic generated source file for MCU stm32f10x_md 5 | * 6 | * 7 | **/ 8 | #include "ISRstm32f10x_md.h" 9 | __attribute__((naked, noreturn)) void ISR::DefaultHandler() 10 | { 11 | for(;;); 12 | } 13 | 14 | extern uint32_t _estack; 15 | 16 | 17 | #ifdef USE_MEMORY_ISR 18 | __attribute__((section(".isr_vector"))) const volatile ISR::ShortVectors interruptsVectorTable = 19 | #else 20 | __attribute__((section(".isr_vector"))) const volatile ISR::Vectors interruptsVectorTable = 21 | #endif 22 | { 23 | #ifdef USE_MEMORY_ISR 24 | (uint32_t)&_estack, 25 | ISR::Reset 26 | }; 27 | 28 | __attribute__((section(".isr_vector2"))) ISR::Vectors MeminterruptsVectorTable = 29 | { 30 | #endif 31 | (uint32_t)&_estack, 32 | ISR::Reset, 33 | ISR::NMI, 34 | ISR::HardFault, 35 | ISR::MemManage, 36 | ISR::BusFault, 37 | ISR::UsageFault, 38 | {0, 0, 0, 0}, 39 | ISR::SVC, 40 | ISR::DebugMon, 41 | {0}, 42 | ISR::PendSV, 43 | ISR::SysTickTimer, 44 | ISR::WWDG_IRQ, 45 | ISR::PVD_IRQ, 46 | ISR::TAMPER_IRQ, 47 | ISR::RTC_IRQ, 48 | ISR::FLASH_IRQ, 49 | ISR::RCC_IRQ, 50 | ISR::EXTI0_IRQ, 51 | ISR::EXTI1_IRQ, 52 | ISR::EXTI2_IRQ, 53 | ISR::EXTI3_IRQ, 54 | ISR::EXTI4_IRQ, 55 | ISR::DMA1_Channel1_IRQ, 56 | ISR::DMA1_Channel2_IRQ, 57 | ISR::DMA1_Channel3_IRQ, 58 | ISR::DMA1_Channel4_IRQ, 59 | ISR::DMA1_Channel5_IRQ, 60 | ISR::DMA1_Channel6_IRQ, 61 | ISR::DMA1_Channel7_IRQ, 62 | ISR::ADC1_2_IRQ, 63 | ISR::USB_HP_CAN1_TX_IRQ, 64 | ISR::USB_LP_CAN1_RX0_IRQ, 65 | ISR::CAN1_RX1_IRQ, 66 | ISR::CAN1_SCE_IRQ, 67 | ISR::EXTI9_5_IRQ, 68 | ISR::TIM1_BRK_IRQ, 69 | ISR::TIM1_UP_IRQ, 70 | ISR::TIM1_TRG_COM_IRQ, 71 | ISR::TIM1_CC_IRQ, 72 | ISR::TIM2_IRQ, 73 | ISR::TIM3_IRQ, 74 | ISR::TIM4_IRQ, 75 | ISR::I2C1_EV_IRQ, 76 | ISR::I2C1_ER_IRQ, 77 | ISR::I2C2_EV_IRQ, 78 | ISR::I2C2_ER_IRQ, 79 | ISR::SPI1_IRQ, 80 | ISR::SPI2_IRQ, 81 | ISR::USART1_IRQ, 82 | ISR::USART2_IRQ, 83 | ISR::USART3_IRQ, 84 | ISR::EXTI15_10_IRQ, 85 | ISR::RTCAlarm_IRQ, 86 | ISR::USBWakeUp_IRQ, 87 | {0, 0, 0, 0, 0, 0, 0}, 88 | ISR::BootRAM, 89 | 90 | }; 91 | #pragma weak Reset = DefaultHandler 92 | #pragma weak NMI = DefaultHandler 93 | #pragma weak HardFault = DefaultHandler 94 | #pragma weak MemManage = DefaultHandler 95 | #pragma weak BusFault = DefaultHandler 96 | #pragma weak UsageFault = DefaultHandler 97 | #pragma weak SVC = DefaultHandler 98 | #pragma weak DebugMon = DefaultHandler 99 | #pragma weak PendSV = DefaultHandler 100 | #pragma weak SysTickTimer = DefaultHandler 101 | #pragma weak WWDG_IRQ = DefaultHandler 102 | #pragma weak PVD_IRQ = DefaultHandler 103 | #pragma weak TAMPER_IRQ = DefaultHandler 104 | #pragma weak RTC_IRQ = DefaultHandler 105 | #pragma weak FLASH_IRQ = DefaultHandler 106 | #pragma weak RCC_IRQ = DefaultHandler 107 | #pragma weak EXTI0_IRQ = DefaultHandler 108 | #pragma weak EXTI1_IRQ = DefaultHandler 109 | #pragma weak EXTI2_IRQ = DefaultHandler 110 | #pragma weak EXTI3_IRQ = DefaultHandler 111 | #pragma weak EXTI4_IRQ = DefaultHandler 112 | #pragma weak DMA1_Channel1_IRQ = DefaultHandler 113 | #pragma weak DMA1_Channel2_IRQ = DefaultHandler 114 | #pragma weak DMA1_Channel3_IRQ = DefaultHandler 115 | #pragma weak DMA1_Channel4_IRQ = DefaultHandler 116 | #pragma weak DMA1_Channel5_IRQ = DefaultHandler 117 | #pragma weak DMA1_Channel6_IRQ = DefaultHandler 118 | #pragma weak DMA1_Channel7_IRQ = DefaultHandler 119 | #pragma weak ADC1_2_IRQ = DefaultHandler 120 | #pragma weak USB_HP_CAN1_TX_IRQ = DefaultHandler 121 | #pragma weak USB_LP_CAN1_RX0_IRQ = DefaultHandler 122 | #pragma weak CAN1_RX1_IRQ = DefaultHandler 123 | #pragma weak CAN1_SCE_IRQ = DefaultHandler 124 | #pragma weak EXTI9_5_IRQ = DefaultHandler 125 | #pragma weak TIM1_BRK_IRQ = DefaultHandler 126 | #pragma weak TIM1_UP_IRQ = DefaultHandler 127 | #pragma weak TIM1_TRG_COM_IRQ = DefaultHandler 128 | #pragma weak TIM1_CC_IRQ = DefaultHandler 129 | #pragma weak TIM2_IRQ = DefaultHandler 130 | #pragma weak TIM3_IRQ = DefaultHandler 131 | #pragma weak TIM4_IRQ = DefaultHandler 132 | #pragma weak I2C1_EV_IRQ = DefaultHandler 133 | #pragma weak I2C1_ER_IRQ = DefaultHandler 134 | #pragma weak I2C2_EV_IRQ = DefaultHandler 135 | #pragma weak I2C2_ER_IRQ = DefaultHandler 136 | #pragma weak SPI1_IRQ = DefaultHandler 137 | #pragma weak SPI2_IRQ = DefaultHandler 138 | #pragma weak USART1_IRQ = DefaultHandler 139 | #pragma weak USART2_IRQ = DefaultHandler 140 | #pragma weak USART3_IRQ = DefaultHandler 141 | #pragma weak EXTI15_10_IRQ = DefaultHandler 142 | #pragma weak RTCAlarm_IRQ = DefaultHandler 143 | #pragma weak USBWakeUp_IRQ = DefaultHandler 144 | #pragma weak BootRAM = DefaultHandler 145 | 146 | -------------------------------------------------------------------------------- /firmware/shared/src/my_func.cpp: -------------------------------------------------------------------------------- 1 | #include "my_func.h" 2 | 3 | #define BIG_BLOCK_SIZE (sizeof(uint32_t) << 2) 4 | #define LITTLE_BLOCK_SIZE (sizeof(uint32_t)) 5 | #define TOO_SMALL1(LEN) ((LEN) < LITTLE_BLOCK_SIZE) 6 | #define TOO_SMALL4(LEN) ((LEN) < BIG_BLOCK_SIZE) 7 | 8 | #define UNALLIGNED1(X) ((uint32_t)X & (LITTLE_BLOCK_SIZE - 1)) 9 | #define UNALLIGNED2(X, Y) \ 10 | (((uint32_t)X & (sizeof(uint32_t) - 1)) | ((uint32_t)Y & (sizeof(uint32_t) - 1))) 11 | 12 | int strlen(const char* str) 13 | { 14 | int len = 0; 15 | while (*str++) 16 | ++len; 17 | return len; 18 | } 19 | 20 | 21 | 22 | 23 | void memcpy(uint8_t* dst, const uint8_t* src, uint32_t len) 24 | { 25 | if (TOO_SMALL4(len) && (!UNALLIGNED2(src, dst))) 26 | { 27 | uint32_t *al_dst = (uint32_t*)dst; 28 | uint32_t *al_src = (uint32_t*)src; 29 | while (len >= BIG_BLOCK_SIZE) 30 | { 31 | *al_dst++ = *al_src++; 32 | *al_dst++ = *al_src++; 33 | *al_dst++ = *al_src++; 34 | *al_dst++ = *al_src++; 35 | len -= BIG_BLOCK_SIZE; 36 | } 37 | while (len >= LITTLE_BLOCK_SIZE) 38 | { 39 | *al_dst++ = *al_src++; 40 | len -= LITTLE_BLOCK_SIZE; 41 | } 42 | dst = (uint8_t*)al_dst; 43 | src = (uint8_t*)al_src; 44 | } 45 | while (len--) 46 | *dst++ = *src++; 47 | } 48 | 49 | void memset(uint8_t* dst,char val, uint32_t len) 50 | { 51 | while (UNALLIGNED1(val)) 52 | { 53 | if (len--) 54 | *dst++ = val; 55 | else 56 | return; 57 | } 58 | 59 | if (!TOO_SMALL1(len)) 60 | { 61 | uint32_t *al_dst = (uint32_t*)dst; 62 | uint32_t buf = (val << 8) | val; 63 | buf |= (buf << 16); 64 | for (uint32_t i=32 ; i< LITTLE_BLOCK_SIZE*8 ; i<<=1) 65 | buf = (buf << i) | buf; 66 | while (len >= BIG_BLOCK_SIZE) 67 | { 68 | *al_dst++ = buf; 69 | *al_dst++ = buf; 70 | *al_dst++ = buf; 71 | *al_dst++ = buf; 72 | len -= BIG_BLOCK_SIZE; 73 | } 74 | while (len >= LITTLE_BLOCK_SIZE) 75 | { 76 | *al_dst++ = buf; 77 | len -= LITTLE_BLOCK_SIZE; 78 | } 79 | dst = (uint8_t*)al_dst; 80 | } 81 | 82 | while (len--) 83 | *dst++ = val; 84 | } 85 | 86 | int memcmp(const uint8_t *s1, const uint8_t *s2, uint32_t len) 87 | { 88 | int d = 0; 89 | 90 | while (len--) 91 | { 92 | d = (int)*s1++ - (int)*s2++; 93 | if (d) 94 | break; 95 | } 96 | 97 | return d; 98 | } 99 | -------------------------------------------------------------------------------- /hardware/hw_cpu/hw_cpu-rescue.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # Battery-RESCUE-main 5 | # 6 | DEF Battery-RESCUE-main BT 0 0 N Y 1 F N 7 | F0 "BT" 100 50 50 H V L CNN 8 | F1 "Battery-RESCUE-main" 100 -50 50 H V L CNN 9 | F2 "" 0 40 50 V V C CNN 10 | F3 "" 0 40 50 V V C CNN 11 | DRAW 12 | S -90 -7 90 -17 0 1 0 F 13 | S -90 50 90 40 0 1 0 F 14 | S -62 -30 58 -50 0 1 0 F 15 | S -62 27 58 7 0 1 0 F 16 | P 2 0 1 10 20 95 60 95 N 17 | P 2 0 1 10 40 115 40 75 N 18 | X ~ 1 0 150 100 D 50 50 1 1 P 19 | X ~ 2 0 -150 100 U 50 50 1 1 P 20 | ENDDRAW 21 | ENDDEF 22 | # 23 | # LED-RESCUE-main 24 | # 25 | DEF LED-RESCUE-main D 0 40 Y N 1 F N 26 | F0 "D" 0 100 50 H V C CNN 27 | F1 "LED-RESCUE-main" 0 -100 50 H V C CNN 28 | F2 "" 0 0 50 H V C CNN 29 | F3 "" 0 0 50 H V C CNN 30 | $FPLIST 31 | LED-* 32 | LED_* 33 | $ENDFPLIST 34 | DRAW 35 | P 2 0 1 0 -50 50 -50 -50 N 36 | P 3 0 1 0 -80 -25 -125 -65 -120 -40 N 37 | P 3 0 1 0 -65 -40 -110 -80 -105 -55 N 38 | P 3 0 1 0 50 50 -50 0 50 -50 F 39 | X K 1 -200 0 150 R 40 40 1 1 P 40 | X A 2 200 0 150 L 40 40 1 1 P 41 | ENDDRAW 42 | ENDDEF 43 | # 44 | #End Library 45 | -------------------------------------------------------------------------------- /hardware/hw_cpu/hw_cpu.pro: -------------------------------------------------------------------------------- 1 | update=Ср 27 дек 2017 08:30:16 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | [cvpcb] 7 | version=1 8 | NetIExt=net 9 | [cvpcb/libraries] 10 | EquName1=devcms 11 | [pcbnew] 12 | version=1 13 | LastNetListRead=hw_cpu.net 14 | UseCmpFile=1 15 | PadDrill=" 0,000000" 16 | PadDrillOvalY=" 0,000000" 17 | PadSizeH=" 4,000000" 18 | PadSizeV=" 4,000000" 19 | PcbTextSizeV=" 1,000000" 20 | PcbTextSizeH=" 1,000000" 21 | PcbTextThickness=" 0,300000" 22 | ModuleTextSizeV=" 1,000000" 23 | ModuleTextSizeH=" 1,000000" 24 | ModuleTextSizeThickness=" 0,150000" 25 | SolderMaskClearance=" 0,200000" 26 | SolderMaskMinWidth=" 0,000000" 27 | DrawSegmentWidth=" 0,200000" 28 | BoardOutlineThickness=" 0,150000" 29 | ModuleOutlineThickness=" 0,150000" 30 | [pcbnew/libraries] 31 | LibDir= 32 | LibName1=sockets 33 | LibName2=connect 34 | LibName3=discret 35 | LibName4=pin_array 36 | LibName5=divers 37 | LibName6=smd_capacitors 38 | LibName7=smd_resistors 39 | LibName8=smd_crystal&oscillator 40 | LibName9=smd_dil 41 | LibName10=smd_transistors 42 | LibName11=libcms 43 | LibName12=display 44 | LibName13=led 45 | LibName14=dip_sockets 46 | LibName15=pga_sockets 47 | LibName16=valves 48 | LibName17=lqfp 49 | LibName18=smd_soic_packages 50 | LibName19=smd_ssop_packages 51 | LibName20=switch-misc 52 | LibName21=w_battery_holders 53 | LibName22=w_conn_pc 54 | LibName23=w_pin_strip 55 | LibName24=Crystals_RevB_25Apr2012 56 | LibName25=inductors 57 | LibName26=open-project 58 | LibName27=inductances 59 | LibName28=w_smd_qfn 60 | LibName29=xtal 61 | [schematic_editor] 62 | version=1 63 | PageLayoutDescrFile= 64 | PlotDirectoryName=../_rel_/ 65 | SubpartIdSeparator=0 66 | SubpartFirstId=65 67 | NetFmtName= 68 | SpiceAjustPassiveValues=0 69 | LabSize=60 70 | ERC_TestSimilarLabels=1 71 | [eeschema] 72 | version=1 73 | LibDir=../../../SH/Devices/main 74 | [eeschema/libraries] 75 | LibName1=hw_cpu-rescue 76 | LibName2=power 77 | LibName3=device 78 | LibName4=transistors 79 | LibName5=conn 80 | LibName6=linear 81 | LibName7=regul 82 | LibName8=74xx 83 | LibName9=cmos4000 84 | LibName10=adc-dac 85 | LibName11=memory 86 | LibName12=xilinx 87 | LibName13=microcontrollers 88 | LibName14=dsp 89 | LibName15=microchip 90 | LibName16=analog_switches 91 | LibName17=motorola 92 | LibName18=texas 93 | LibName19=intel 94 | LibName20=audio 95 | LibName21=interface 96 | LibName22=digital-audio 97 | LibName23=philips 98 | LibName24=display 99 | LibName25=cypress 100 | LibName26=siliconi 101 | LibName27=opto 102 | LibName28=atmel 103 | LibName29=contrib 104 | LibName30=valves 105 | LibName31=stm32 106 | LibName32=stm8 107 | LibName33=powerint 108 | LibName34=/media/Dev/KiCad/conn_an 109 | LibName35=switches 110 | LibName36=dc-dc 111 | -------------------------------------------------------------------------------- /hardware/hw_cross/cross-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # 74LS125 5 | # 6 | DEF 74LS125 U 0 30 Y Y 4 F N 7 | F0 "U" 0 100 50 H V L BNN 8 | F1 "74LS125" 50 -150 50 H V L TNN 9 | F2 "" 0 0 50 H I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | ALIAS 74LVC125 12 | DRAW 13 | X GND 7 -150 -150 0 U 50 30 0 0 W N 14 | X VCC 14 -150 150 0 D 50 30 0 0 W N 15 | X E 1 0 -300 220 U 50 30 1 0 I I 16 | X E 4 0 -300 220 U 50 30 2 0 I I 17 | X E 10 0 -300 220 U 50 30 3 0 I I 18 | X E 13 0 -300 220 U 50 30 4 0 I I 19 | P 4 0 1 0 -150 150 -150 -150 150 0 -150 150 N 20 | X D 2 -450 0 300 R 50 30 1 1 I 21 | X O 3 450 0 300 L 50 30 1 1 T 22 | X D 5 -450 0 300 R 50 30 2 1 I 23 | X O 6 450 0 300 L 50 30 2 1 T 24 | X O 8 450 0 300 L 50 30 3 1 T 25 | X D 9 -450 0 300 R 50 30 3 1 I 26 | X O 11 450 0 300 L 50 30 4 1 T 27 | X D 12 -450 0 300 R 50 30 4 1 I 28 | ENDDRAW 29 | ENDDEF 30 | # 31 | # CONN_01X14 32 | # 33 | DEF CONN_01X14 J 0 40 Y N 1 F N 34 | F0 "J" 0 750 50 H V C CNN 35 | F1 "CONN_01X14" 100 0 50 V V C CNN 36 | F2 "" 0 0 50 H I C CNN 37 | F3 "" 0 0 50 H I C CNN 38 | $FPLIST 39 | Pin_Header_Straight_1X* 40 | Pin_Header_Angled_1X* 41 | Socket_Strip_Straight_1X* 42 | Socket_Strip_Angled_1X* 43 | $ENDFPLIST 44 | DRAW 45 | S -50 -645 10 -655 0 1 0 N 46 | S -50 -545 10 -555 0 1 0 N 47 | S -50 -445 10 -455 0 1 0 N 48 | S -50 -345 10 -355 0 1 0 N 49 | S -50 -245 10 -255 0 1 0 N 50 | S -50 -145 10 -155 0 1 0 N 51 | S -50 -45 10 -55 0 1 0 N 52 | S -50 55 10 45 0 1 0 N 53 | S -50 155 10 145 0 1 0 N 54 | S -50 255 10 245 0 1 0 N 55 | S -50 355 10 345 0 1 0 N 56 | S -50 455 10 445 0 1 0 N 57 | S -50 555 10 545 0 1 0 N 58 | S -50 655 10 645 0 1 0 N 59 | S -50 700 50 -700 0 1 0 N 60 | X P1 1 -200 650 150 R 50 50 1 1 P 61 | X P2 2 -200 550 150 R 50 50 1 1 P 62 | X P3 3 -200 450 150 R 50 50 1 1 P 63 | X P4 4 -200 350 150 R 50 50 1 1 P 64 | X P5 5 -200 250 150 R 50 50 1 1 P 65 | X P6 6 -200 150 150 R 50 50 1 1 P 66 | X P7 7 -200 50 150 R 50 50 1 1 P 67 | X P8 8 -200 -50 150 R 50 50 1 1 P 68 | X P9 9 -200 -150 150 R 50 50 1 1 P 69 | X P10 10 -200 -250 150 R 50 50 1 1 P 70 | X P11 11 -200 -350 150 R 50 50 1 1 P 71 | X P12 12 -200 -450 150 R 50 50 1 1 P 72 | X P13 13 -200 -550 150 R 50 50 1 1 P 73 | X P14 14 -200 -650 150 R 50 50 1 1 P 74 | ENDDRAW 75 | ENDDEF 76 | # 77 | # GND 78 | # 79 | DEF GND #PWR 0 0 Y Y 1 F P 80 | F0 "#PWR" 0 -250 50 H I C CNN 81 | F1 "GND" 0 -150 50 H V C CNN 82 | F2 "" 0 0 50 H I C CNN 83 | F3 "" 0 0 50 H I C CNN 84 | DRAW 85 | P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N 86 | X GND 1 0 0 0 D 50 50 1 1 W N 87 | ENDDRAW 88 | ENDDEF 89 | # 90 | # VCC 91 | # 92 | DEF VCC #PWR 0 0 Y Y 1 F P 93 | F0 "#PWR" 0 -150 50 H I C CNN 94 | F1 "VCC" 0 150 50 H V C CNN 95 | F2 "" 0 0 50 H I C CNN 96 | F3 "" 0 0 50 H I C CNN 97 | DRAW 98 | C 0 75 25 0 1 0 N 99 | P 2 0 1 0 0 0 0 50 N 100 | X VCC 1 0 0 0 U 50 50 1 1 W N 101 | ENDDRAW 102 | ENDDEF 103 | # 104 | # VDD 105 | # 106 | DEF VDD #PWR 0 0 Y Y 1 F P 107 | F0 "#PWR" 0 -150 50 H I C CNN 108 | F1 "VDD" 0 150 50 H V C CNN 109 | F2 "" 0 0 50 H I C CNN 110 | F3 "" 0 0 50 H I C CNN 111 | DRAW 112 | C 0 75 25 0 1 0 N 113 | P 2 0 1 0 0 0 0 50 N 114 | X VDD 1 0 0 0 U 50 50 1 1 W N 115 | ENDDRAW 116 | ENDDEF 117 | # 118 | # VSS 119 | # 120 | DEF VSS #PWR 0 0 Y Y 1 F P 121 | F0 "#PWR" 0 -150 50 H I C CNN 122 | F1 "VSS" 0 150 50 H V C CNN 123 | F2 "" 0 0 50 H I C CNN 124 | F3 "" 0 0 50 H I C CNN 125 | DRAW 126 | C 0 75 25 0 1 0 N 127 | P 2 0 1 0 0 0 0 50 N 128 | X VSS 1 0 0 0 U 50 50 1 1 W N 129 | ENDDRAW 130 | ENDDEF 131 | # 132 | #End Library 133 | -------------------------------------------------------------------------------- /hardware/hw_cross/cross.pro: -------------------------------------------------------------------------------- 1 | update=Ср 16 авг 2017 08:24:03 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [eeschema] 27 | version=1 28 | LibDir= 29 | [eeschema/libraries] 30 | LibName1=power 31 | LibName2=device 32 | LibName3=transistors 33 | LibName4=conn 34 | LibName5=linear 35 | LibName6=regul 36 | LibName7=74xx 37 | LibName8=cmos4000 38 | LibName9=adc-dac 39 | LibName10=memory 40 | LibName11=xilinx 41 | LibName12=microcontrollers 42 | LibName13=dsp 43 | LibName14=microchip 44 | LibName15=analog_switches 45 | LibName16=motorola 46 | LibName17=texas 47 | LibName18=intel 48 | LibName19=audio 49 | LibName20=interface 50 | LibName21=digital-audio 51 | LibName22=philips 52 | LibName23=display 53 | LibName24=cypress 54 | LibName25=siliconi 55 | LibName26=opto 56 | LibName27=atmel 57 | LibName28=contrib 58 | LibName29=valves 59 | [general] 60 | version=1 61 | -------------------------------------------------------------------------------- /hardware/hw_di16/module_di-rescue.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # LED-RESCUE-main_io 5 | # 6 | DEF LED-RESCUE-main_io D 0 40 Y N 1 F N 7 | F0 "D" 0 100 50 H V C CNN 8 | F1 "LED-RESCUE-main_io" 0 -100 50 H V C CNN 9 | F2 "" 0 0 50 H V C CNN 10 | F3 "" 0 0 50 H V C CNN 11 | $FPLIST 12 | LED-* 13 | LED_* 14 | $ENDFPLIST 15 | DRAW 16 | P 2 0 1 0 -50 50 -50 -50 N 17 | P 3 0 1 0 -80 -25 -125 -65 -120 -40 N 18 | P 3 0 1 0 -65 -40 -110 -80 -105 -55 N 19 | P 3 0 1 0 50 50 -50 0 50 -50 F 20 | X K 1 -200 0 150 R 40 40 1 1 P 21 | X A 2 200 0 150 L 40 40 1 1 P 22 | ENDDRAW 23 | ENDDEF 24 | # 25 | #End Library 26 | -------------------------------------------------------------------------------- /hardware/hw_di16/module_di.pro: -------------------------------------------------------------------------------- 1 | update=23.06.2017 21:30:37 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | [cvpcb] 7 | version=1 8 | NetIExt=net 9 | [cvpcb/libraries] 10 | EquName1=devcms 11 | [pcbnew] 12 | version=1 13 | LastNetListRead=module_di.net 14 | UseCmpFile=1 15 | PadDrill=" 0,000000" 16 | PadDrillOvalY=" 0,000000" 17 | PadSizeH=" 4,000000" 18 | PadSizeV=" 4,000000" 19 | PcbTextSizeV=" 1,000000" 20 | PcbTextSizeH=" 1,000000" 21 | PcbTextThickness=" 0,300000" 22 | ModuleTextSizeV=" 1,000000" 23 | ModuleTextSizeH=" 1,000000" 24 | ModuleTextSizeThickness=" 0,150000" 25 | SolderMaskClearance=" 0,200000" 26 | SolderMaskMinWidth=" 0,000000" 27 | DrawSegmentWidth=" 0,200000" 28 | BoardOutlineThickness=" 0,150000" 29 | ModuleOutlineThickness=" 0,150000" 30 | [pcbnew/libraries] 31 | LibDir= 32 | LibName1=sockets 33 | LibName2=connect 34 | LibName3=discret 35 | LibName4=pin_array 36 | LibName5=divers 37 | LibName6=smd_capacitors 38 | LibName7=smd_resistors 39 | LibName8=smd_crystal&oscillator 40 | LibName9=smd_dil 41 | LibName10=smd_transistors 42 | LibName11=libcms 43 | LibName12=display 44 | LibName13=led 45 | LibName14=dip_sockets 46 | LibName15=pga_sockets 47 | LibName16=valves 48 | LibName17=lqfp 49 | LibName18=smd_soic_packages 50 | LibName19=smd_ssop_packages 51 | LibName20=switch-misc 52 | LibName21=w_battery_holders 53 | LibName22=w_conn_pc 54 | LibName23=w_pin_strip 55 | LibName24=Crystals_RevB_25Apr2012 56 | LibName25=inductors 57 | LibName26=open-project 58 | LibName27=inductances 59 | LibName28=w_smd_qfn 60 | LibName29=xtal 61 | [eeschema] 62 | version=1 63 | LibDir= 64 | [eeschema/libraries] 65 | LibName1=module_di-rescue 66 | LibName2=power 67 | LibName3=device 68 | LibName4=transistors 69 | LibName5=conn 70 | LibName6=linear 71 | LibName7=regul 72 | LibName8=74xx 73 | LibName9=cmos4000 74 | LibName10=adc-dac 75 | LibName11=memory 76 | LibName12=xilinx 77 | LibName13=microcontrollers 78 | LibName14=dsp 79 | LibName15=microchip 80 | LibName16=analog_switches 81 | LibName17=motorola 82 | LibName18=texas 83 | LibName19=intel 84 | LibName20=audio 85 | LibName21=interface 86 | LibName22=digital-audio 87 | LibName23=philips 88 | LibName24=display 89 | LibName25=cypress 90 | LibName26=siliconi 91 | LibName27=opto 92 | LibName28=atmel 93 | LibName29=contrib 94 | LibName30=valves 95 | LibName31=stm32 96 | LibName32=stm8 97 | LibName33=powerint 98 | [schematic_editor] 99 | version=1 100 | PageLayoutDescrFile= 101 | PlotDirectoryName=../_rel_/ 102 | SubpartIdSeparator=0 103 | SubpartFirstId=65 104 | NetFmtName= 105 | SpiceAjustPassiveValues=0 106 | LabSize=60 107 | ERC_TestSimilarLabels=1 108 | -------------------------------------------------------------------------------- /hardware/hw_do16/module_do-rescue.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # LED-RESCUE-main_io 5 | # 6 | DEF LED-RESCUE-main_io D 0 40 Y N 1 F N 7 | F0 "D" 0 100 50 H V C CNN 8 | F1 "LED-RESCUE-main_io" 0 -100 50 H V C CNN 9 | F2 "" 0 0 50 H V C CNN 10 | F3 "" 0 0 50 H V C CNN 11 | $FPLIST 12 | LED-* 13 | LED_* 14 | $ENDFPLIST 15 | DRAW 16 | P 2 0 1 0 -50 50 -50 -50 N 17 | P 3 0 1 0 -80 -25 -125 -65 -120 -40 N 18 | P 3 0 1 0 -65 -40 -110 -80 -105 -55 N 19 | P 3 0 1 0 50 50 -50 0 50 -50 F 20 | X K 1 -200 0 150 R 40 40 1 1 P 21 | X A 2 200 0 150 L 40 40 1 1 P 22 | ENDDRAW 23 | ENDDEF 24 | # 25 | #End Library 26 | -------------------------------------------------------------------------------- /hardware/hw_do16/module_do.pro: -------------------------------------------------------------------------------- 1 | update=23.06.2017 21:31:14 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | [cvpcb] 7 | version=1 8 | NetIExt=net 9 | [cvpcb/libraries] 10 | EquName1=devcms 11 | [pcbnew] 12 | version=1 13 | LastNetListRead=module_do.net 14 | UseCmpFile=1 15 | PadDrill=" 0,000000" 16 | PadDrillOvalY=" 0,000000" 17 | PadSizeH=" 4,000000" 18 | PadSizeV=" 4,000000" 19 | PcbTextSizeV=" 1,000000" 20 | PcbTextSizeH=" 1,000000" 21 | PcbTextThickness=" 0,300000" 22 | ModuleTextSizeV=" 1,000000" 23 | ModuleTextSizeH=" 1,000000" 24 | ModuleTextSizeThickness=" 0,150000" 25 | SolderMaskClearance=" 0,200000" 26 | SolderMaskMinWidth=" 0,000000" 27 | DrawSegmentWidth=" 0,200000" 28 | BoardOutlineThickness=" 0,150000" 29 | ModuleOutlineThickness=" 0,150000" 30 | [pcbnew/libraries] 31 | LibDir= 32 | LibName1=sockets 33 | LibName2=connect 34 | LibName3=discret 35 | LibName4=pin_array 36 | LibName5=divers 37 | LibName6=smd_capacitors 38 | LibName7=smd_resistors 39 | LibName8=smd_crystal&oscillator 40 | LibName9=smd_dil 41 | LibName10=smd_transistors 42 | LibName11=libcms 43 | LibName12=display 44 | LibName13=led 45 | LibName14=dip_sockets 46 | LibName15=pga_sockets 47 | LibName16=valves 48 | LibName17=lqfp 49 | LibName18=smd_soic_packages 50 | LibName19=smd_ssop_packages 51 | LibName20=switch-misc 52 | LibName21=w_battery_holders 53 | LibName22=w_conn_pc 54 | LibName23=w_pin_strip 55 | LibName24=Crystals_RevB_25Apr2012 56 | LibName25=inductors 57 | LibName26=open-project 58 | LibName27=inductances 59 | LibName28=w_smd_qfn 60 | LibName29=xtal 61 | [eeschema] 62 | version=1 63 | LibDir= 64 | [eeschema/libraries] 65 | LibName1=module_do-rescue 66 | LibName2=main-rescue 67 | LibName3=power 68 | LibName4=device 69 | LibName5=transistors 70 | LibName6=conn 71 | LibName7=linear 72 | LibName8=regul 73 | LibName9=74xx 74 | LibName10=cmos4000 75 | LibName11=adc-dac 76 | LibName12=memory 77 | LibName13=xilinx 78 | LibName14=microcontrollers 79 | LibName15=dsp 80 | LibName16=microchip 81 | LibName17=analog_switches 82 | LibName18=motorola 83 | LibName19=texas 84 | LibName20=intel 85 | LibName21=audio 86 | LibName22=interface 87 | LibName23=digital-audio 88 | LibName24=philips 89 | LibName25=display 90 | LibName26=cypress 91 | LibName27=siliconi 92 | LibName28=opto 93 | LibName29=atmel 94 | LibName30=contrib 95 | LibName31=valves 96 | LibName32=stm32 97 | LibName33=stm8 98 | LibName34=powerint 99 | LibName35=/media/Dev/SH/Devices/main/memory 100 | LibName36=/media/Dev/SH/Devices/main/microchip 101 | LibName37=/home/andreil/ao6801e 102 | LibName38=/home/andreil/zener 103 | [schematic_editor] 104 | version=1 105 | PageLayoutDescrFile= 106 | PlotDirectoryName=../_rel_/ 107 | SubpartIdSeparator=0 108 | SubpartFirstId=65 109 | NetFmtName= 110 | SpiceAjustPassiveValues=0 111 | LabSize=60 112 | ERC_TestSimilarLabels=1 113 | -------------------------------------------------------------------------------- /hardware/hw_mod_cross/mod_cross-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # CONN_01X14 5 | # 6 | DEF CONN_01X14 J 0 40 Y N 1 F N 7 | F0 "J" 0 750 50 H V C CNN 8 | F1 "CONN_01X14" 100 0 50 V V C CNN 9 | F2 "" 0 0 50 H I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | $FPLIST 12 | Pin_Header_Straight_1X* 13 | Pin_Header_Angled_1X* 14 | Socket_Strip_Straight_1X* 15 | Socket_Strip_Angled_1X* 16 | $ENDFPLIST 17 | DRAW 18 | S -50 -645 10 -655 0 1 0 N 19 | S -50 -545 10 -555 0 1 0 N 20 | S -50 -445 10 -455 0 1 0 N 21 | S -50 -345 10 -355 0 1 0 N 22 | S -50 -245 10 -255 0 1 0 N 23 | S -50 -145 10 -155 0 1 0 N 24 | S -50 -45 10 -55 0 1 0 N 25 | S -50 55 10 45 0 1 0 N 26 | S -50 155 10 145 0 1 0 N 27 | S -50 255 10 245 0 1 0 N 28 | S -50 355 10 345 0 1 0 N 29 | S -50 455 10 445 0 1 0 N 30 | S -50 555 10 545 0 1 0 N 31 | S -50 655 10 645 0 1 0 N 32 | S -50 700 50 -700 0 1 0 N 33 | X P1 1 -200 650 150 R 50 50 1 1 P 34 | X P2 2 -200 550 150 R 50 50 1 1 P 35 | X P3 3 -200 450 150 R 50 50 1 1 P 36 | X P4 4 -200 350 150 R 50 50 1 1 P 37 | X P5 5 -200 250 150 R 50 50 1 1 P 38 | X P6 6 -200 150 150 R 50 50 1 1 P 39 | X P7 7 -200 50 150 R 50 50 1 1 P 40 | X P8 8 -200 -50 150 R 50 50 1 1 P 41 | X P9 9 -200 -150 150 R 50 50 1 1 P 42 | X P10 10 -200 -250 150 R 50 50 1 1 P 43 | X P11 11 -200 -350 150 R 50 50 1 1 P 44 | X P12 12 -200 -450 150 R 50 50 1 1 P 45 | X P13 13 -200 -550 150 R 50 50 1 1 P 46 | X P14 14 -200 -650 150 R 50 50 1 1 P 47 | ENDDRAW 48 | ENDDEF 49 | # 50 | # CONN_02X14 51 | # 52 | DEF CONN_02X14 J 0 1 Y N 1 F N 53 | F0 "J" 0 750 50 H V C CNN 54 | F1 "CONN_02X14" 0 0 50 V V C CNN 55 | F2 "" 0 -1150 50 H I C CNN 56 | F3 "" 0 -1150 50 H I C CNN 57 | $FPLIST 58 | Pin_Header_Straight_2X* 59 | Pin_Header_Angled_2X* 60 | Socket_Strip_Straight_2X* 61 | Socket_Strip_Angled_2X* 62 | $ENDFPLIST 63 | DRAW 64 | S -100 -645 -50 -655 0 1 0 N 65 | S -100 -545 -50 -555 0 1 0 N 66 | S -100 -445 -50 -455 0 1 0 N 67 | S -100 -345 -50 -355 0 1 0 N 68 | S -100 -245 -50 -255 0 1 0 N 69 | S -100 -145 -50 -155 0 1 0 N 70 | S -100 -45 -50 -55 0 1 0 N 71 | S -100 55 -50 45 0 1 0 N 72 | S -100 155 -50 145 0 1 0 N 73 | S -100 255 -50 245 0 1 0 N 74 | S -100 355 -50 345 0 1 0 N 75 | S -100 455 -50 445 0 1 0 N 76 | S -100 555 -50 545 0 1 0 N 77 | S -100 655 -50 645 0 1 0 N 78 | S -100 700 100 -700 0 1 0 N 79 | S 50 -645 100 -655 0 1 0 N 80 | S 50 -545 100 -555 0 1 0 N 81 | S 50 -445 100 -455 0 1 0 N 82 | S 50 -345 100 -355 0 1 0 N 83 | S 50 -245 100 -255 0 1 0 N 84 | S 50 -145 100 -155 0 1 0 N 85 | S 50 -45 100 -55 0 1 0 N 86 | S 50 55 100 45 0 1 0 N 87 | S 50 155 100 145 0 1 0 N 88 | S 50 255 100 245 0 1 0 N 89 | S 50 355 100 345 0 1 0 N 90 | S 50 455 100 445 0 1 0 N 91 | S 50 555 100 545 0 1 0 N 92 | S 50 655 100 645 0 1 0 N 93 | X P1 1 -250 650 150 R 50 50 1 1 P 94 | X P2 2 250 650 150 L 50 50 1 1 P 95 | X P3 3 -250 550 150 R 50 50 1 1 P 96 | X P4 4 250 550 150 L 50 50 1 1 P 97 | X P5 5 -250 450 150 R 50 50 1 1 P 98 | X P6 6 250 450 150 L 50 50 1 1 P 99 | X P7 7 -250 350 150 R 50 50 1 1 P 100 | X P8 8 250 350 150 L 50 50 1 1 P 101 | X P9 9 -250 250 150 R 50 50 1 1 P 102 | X P10 10 250 250 150 L 50 50 1 1 P 103 | X P20 20 250 -250 150 L 50 50 1 1 P 104 | X P11 11 -250 150 150 R 50 50 1 1 P 105 | X P21 21 -250 -350 150 R 50 50 1 1 P 106 | X P12 12 250 150 150 L 50 50 1 1 P 107 | X P22 22 250 -350 150 L 50 50 1 1 P 108 | X P13 13 -250 50 150 R 50 50 1 1 P 109 | X P23 23 -250 -450 150 R 50 50 1 1 P 110 | X P14 14 250 50 150 L 50 50 1 1 P 111 | X P24 24 250 -450 150 L 50 50 1 1 P 112 | X P15 15 -250 -50 150 R 50 50 1 1 P 113 | X P25 25 -250 -550 150 R 50 50 1 1 P 114 | X P16 16 250 -50 150 L 50 50 1 1 P 115 | X P26 26 250 -550 150 L 50 50 1 1 P 116 | X P17 17 -250 -150 150 R 50 50 1 1 P 117 | X P27 27 -250 -650 150 R 50 50 1 1 P 118 | X P18 18 250 -150 150 L 50 50 1 1 P 119 | X P28 28 250 -650 150 L 50 50 1 1 P 120 | X P19 19 -250 -250 150 R 50 50 1 1 P 121 | ENDDRAW 122 | ENDDEF 123 | # 124 | # VDD 125 | # 126 | DEF VDD #PWR 0 0 Y Y 1 F P 127 | F0 "#PWR" 0 -150 50 H I C CNN 128 | F1 "VDD" 0 150 50 H V C CNN 129 | F2 "" 0 0 50 H I C CNN 130 | F3 "" 0 0 50 H I C CNN 131 | DRAW 132 | C 0 75 25 0 1 0 N 133 | P 2 0 1 0 0 0 0 50 N 134 | X VDD 1 0 0 0 U 50 50 1 1 W N 135 | ENDDRAW 136 | ENDDEF 137 | # 138 | # VSS 139 | # 140 | DEF VSS #PWR 0 0 Y Y 1 F P 141 | F0 "#PWR" 0 -150 50 H I C CNN 142 | F1 "VSS" 0 150 50 H V C CNN 143 | F2 "" 0 0 50 H I C CNN 144 | F3 "" 0 0 50 H I C CNN 145 | DRAW 146 | C 0 75 25 0 1 0 N 147 | P 2 0 1 0 0 0 0 50 N 148 | X VSS 1 0 0 0 U 50 50 1 1 W N 149 | ENDDRAW 150 | ENDDEF 151 | # 152 | #End Library 153 | -------------------------------------------------------------------------------- /hardware/hw_mod_cross/mod_cross.pro: -------------------------------------------------------------------------------- 1 | update=Ср 16 авг 2017 09:00:04 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [eeschema] 27 | version=1 28 | LibDir= 29 | [eeschema/libraries] 30 | LibName1=power 31 | LibName2=device 32 | LibName3=transistors 33 | LibName4=conn 34 | LibName5=linear 35 | LibName6=regul 36 | LibName7=74xx 37 | LibName8=cmos4000 38 | LibName9=adc-dac 39 | LibName10=memory 40 | LibName11=xilinx 41 | LibName12=microcontrollers 42 | LibName13=dsp 43 | LibName14=microchip 44 | LibName15=analog_switches 45 | LibName16=motorola 46 | LibName17=texas 47 | LibName18=intel 48 | LibName19=audio 49 | LibName20=interface 50 | LibName21=digital-audio 51 | LibName22=philips 52 | LibName23=display 53 | LibName24=cypress 54 | LibName25=siliconi 55 | LibName26=opto 56 | LibName27=atmel 57 | LibName28=contrib 58 | LibName29=valves 59 | [general] 60 | version=1 61 | -------------------------------------------------------------------------------- /runtime/datainterface.h: -------------------------------------------------------------------------------- 1 | #ifndef DATAINTERFACE_H 2 | #define DATAINTERFACE_H 3 | 4 | #include 5 | 6 | template 7 | class DataInterface 8 | { 9 | public: 10 | bool read_bit(int offset, int bit_idx) 11 | { return (m_data[offset] & (1 << bit_idx)); } 12 | void write_bit(int offset, int bit_idx, bool val) 13 | { 14 | if (val) 15 | m_data[offset] |= (1 << bit_idx); 16 | else 17 | m_data[offset] &= ~(1 << bit_idx); 18 | } 19 | 20 | uint8_t read_ubyte(int offset) 21 | { return m_data[offset]; } 22 | void write_ubyte(int offset, uint8_t val) 23 | { m_data[offset] = val; } 24 | 25 | int8_t read_byte(int offset) 26 | { return m_data[offset]; } 27 | void write_byte(int offset, int8_t val) 28 | { m_data[offset] = val; } 29 | 30 | uint16_t read_word(int offset) 31 | { return *((uint16_t*)&m_data[offset]); } 32 | void write_word(int offset, uint16_t val) 33 | { *((uint16_t*)&m_data[offset]) = val; } 34 | 35 | int16_t read_int(int offset) 36 | { return *((int16_t*)&m_data[offset]); } 37 | void write_int(int offset, int16_t val) 38 | { *((int16_t*)&m_data[offset]) = val; } 39 | 40 | uint32_t read_dword(int offset) 41 | { return *((uint32_t*)&m_data[offset]); } 42 | void write_dword(int offset, uint32_t val) 43 | { *((uint32_t*)&m_data[offset]) = val; } 44 | 45 | float read_real(int offset) 46 | { return *((float*)&m_data[offset]); } 47 | void write_real(int offset, float val) 48 | { *((float*)&m_data[offset]) = val; } 49 | 50 | 51 | void update_inputs(uint8_t* PIP) 52 | { std::memcpy(this->m_data, PIP, IO_AREA_SIZE); } 53 | void update_outputs(uint8_t* POP) 54 | { std::memcpy(POP, this->m_data, IO_AREA_SIZE); } 55 | protected: 56 | char m_data[data_size]; 57 | }; 58 | 59 | #endif // DATAINTERFACE_H 60 | -------------------------------------------------------------------------------- /runtime/firmware_sample/firmware.h: -------------------------------------------------------------------------------- 1 | #ifndef FIRMWARE_H 2 | #define FIRMWARE_H 3 | 4 | enum class EOB 5 | { 6 | OB_CYCLE_EXEC = 1, 7 | OB_TIME_OF_DAY_INT_0 = 10, 8 | OB_TIME_OF_DAY_INT_1 = 11, 9 | OB_TIME_OF_DAY_INT_2 = 12, 10 | OB_TIME_OF_DAY_INT_3 = 13, 11 | OB_TIME_OF_DAY_INT_4 = 14, 12 | OB_TIME_OF_DAY_INT_5 = 15, 13 | OB_TIME_OF_DAY_INT_6 = 16, 14 | OB_TIME_OF_DAY_INT_7 = 17, 15 | OB_TIME_DELAY_INT_0 = 20, 16 | OB_TIME_DELAY_INT_1 = 21, 17 | OB_TIME_DELAY_INT_2 = 22, 18 | OB_TIME_DELAY_INT_3 = 23, 19 | OB_CYCLIC_INT_0 = 30, 20 | OB_CYCLIC_INT_1 = 31, 21 | OB_CYCLIC_INT_2 = 32, 22 | OB_CYCLIC_INT_3 = 33, 23 | OB_CYCLIC_INT_4 = 34, 24 | OB_CYCLIC_INT_5 = 35, 25 | OB_CYCLIC_INT_6 = 36, 26 | OB_CYCLIC_INT_7 = 37, 27 | OB_CYCLIC_INT_8 = 38, 28 | OB_HW_INT_0 = 40, 29 | OB_HW_INT_1 = 41, 30 | OB_HW_INT_2 = 42, 31 | OB_HW_INT_3 = 43, 32 | OB_HW_INT_4 = 44, 33 | OB_HW_INT_5 = 45, 34 | OB_HW_INT_6 = 46, 35 | OB_HW_INT_7 = 47, 36 | OB_HW_INT_8 = 48, 37 | OB_MULTICOMP_INT = 60, 38 | OB_CYCLE_TIME_FAULT = 80, 39 | OB_POWER_SUP_FAULT = 81, 40 | OB_IO_POINT_FAULT_1 = 82, 41 | OB_IO_POINT_FAULT_2 = 83, 42 | OB_CPU_FAULT = 84, 43 | OB_OB_NOT_LOADED_FAULT = 85, 44 | OB_LOSS_OF_RACK_FAULT = 86, 45 | OB_COMM_FAULT = 87, 46 | OB_BACKGROUND_CYCLE = 90, 47 | OB_COMPLETE_RESTART = 100, 48 | OB_RESTART = 101, 49 | OB_COLD_RESTART = 102, 50 | OB_PROGRAMMING_ERROR = 121, 51 | OB_MOD_ACCESS_ERROR = 122, 52 | }; 53 | 54 | class Firmware 55 | { 56 | public: 57 | Firmware(); 58 | 59 | bool init(); 60 | bool run_OB(EOB ob); 61 | private: 62 | bool run_OB1(); 63 | bool run_OB84(); 64 | }; 65 | 66 | #endif // FIRMWARE_H 67 | -------------------------------------------------------------------------------- /runtime/firmware_sample/fwdb.cpp: -------------------------------------------------------------------------------- 1 | #include "fwdb.h" 2 | 3 | DB1 FWDB::db1; 4 | DBHeader FWDB::m_header; 5 | 6 | void FWDB::init() 7 | { 8 | db1.bit0 = false; 9 | db1.bit1 = false; 10 | db1.bit2 = false; 11 | db1.bit3 = false; 12 | db1.bit4 = false; 13 | db1.bit5 = false; 14 | db1.bit6 = false; 15 | db1.bit7 = false; 16 | db1.byte1 = false; 17 | db1.bit8 = false; 18 | } 19 | 20 | void FWDB::read() 21 | { 22 | //TODO: read from flash 23 | 24 | if (!m_header.initialized) 25 | { 26 | init(); 27 | save(); 28 | } 29 | } 30 | 31 | void FWDB::save() 32 | { 33 | //TODO: save to flash 34 | } 35 | -------------------------------------------------------------------------------- /runtime/firmware_sample/fwdb.h: -------------------------------------------------------------------------------- 1 | #ifndef FWDB_H 2 | #define FWDB_H 3 | 4 | #include 5 | 6 | #pragma pack(push, 1) 7 | struct DB1 8 | { 9 | bool bit0: 1; 10 | bool bit1: 1; 11 | bool bit2: 1; 12 | bool bit3: 1; 13 | bool bit4: 1; 14 | bool bit5: 1; 15 | bool bit6: 1; 16 | bool bit7: 1; 17 | uint8_t byte1; 18 | bool bit8: 1; 19 | }; 20 | 21 | struct DBHeader 22 | { 23 | bool initialized; 24 | uint32_t last_update; 25 | }; 26 | #pragma pack(pop) 27 | 28 | class FWDB 29 | { 30 | public: 31 | static void init(); 32 | static void read(); 33 | static void save(); 34 | 35 | static DB1 db1; 36 | private: 37 | static DBHeader m_header; 38 | }; 39 | 40 | #endif // FWDB_H 41 | -------------------------------------------------------------------------------- /runtime/include/master_non_sec.h: -------------------------------------------------------------------------------- 1 | #ifndef _ALTERA_MASTER_NON_SEC_H_ 2 | #define _ALTERA_MASTER_NON_SEC_H_ 3 | 4 | /* 5 | * This file was automatically generated by the swinfo2header utility. 6 | * 7 | * Created from SOPC Builder system 'hps' in 8 | * file '../../../FPGA/DE1_PLC/de1_sys/hps.sopcinfo'. 9 | */ 10 | 11 | /* 12 | * This file contains macros for module 'master_non_sec' and devices 13 | * connected to the following master: 14 | * master 15 | * 16 | * Do not include this header file and another header file created for a 17 | * different module or master group at the same time. 18 | * Doing so may result in duplicate macro names. 19 | * Instead, use the system header file which has macros with unique names. 20 | */ 21 | 22 | /* 23 | * Macros for device 'buttons', class 'altera_avalon_pio' 24 | * The macros are prefixed with 'BUTTONS_'. 25 | * The prefix is the slave descriptor. 26 | */ 27 | #define BUTTONS_COMPONENT_TYPE altera_avalon_pio 28 | #define BUTTONS_COMPONENT_NAME buttons 29 | #define BUTTONS_BASE 0x0 30 | #define BUTTONS_SPAN 16 31 | #define BUTTONS_END 0xf 32 | #define BUTTONS_BIT_CLEARING_EDGE_REGISTER 0 33 | #define BUTTONS_BIT_MODIFYING_OUTPUT_REGISTER 0 34 | #define BUTTONS_CAPTURE 0 35 | #define BUTTONS_DATA_WIDTH 4 36 | #define BUTTONS_DO_TEST_BENCH_WIRING 0 37 | #define BUTTONS_DRIVEN_SIM_VALUE 0 38 | #define BUTTONS_EDGE_TYPE NONE 39 | #define BUTTONS_FREQ 50000000 40 | #define BUTTONS_HAS_IN 1 41 | #define BUTTONS_HAS_OUT 0 42 | #define BUTTONS_HAS_TRI 0 43 | #define BUTTONS_IRQ_TYPE LEVEL 44 | #define BUTTONS_RESET_VALUE 0 45 | 46 | /* 47 | * Macros for device 'switches', class 'altera_avalon_pio' 48 | * The macros are prefixed with 'SWITCHES_'. 49 | * The prefix is the slave descriptor. 50 | */ 51 | #define SWITCHES_COMPONENT_TYPE altera_avalon_pio 52 | #define SWITCHES_COMPONENT_NAME switches 53 | #define SWITCHES_BASE 0x10 54 | #define SWITCHES_SPAN 16 55 | #define SWITCHES_END 0x1f 56 | #define SWITCHES_BIT_CLEARING_EDGE_REGISTER 0 57 | #define SWITCHES_BIT_MODIFYING_OUTPUT_REGISTER 0 58 | #define SWITCHES_CAPTURE 0 59 | #define SWITCHES_DATA_WIDTH 10 60 | #define SWITCHES_DO_TEST_BENCH_WIRING 0 61 | #define SWITCHES_DRIVEN_SIM_VALUE 0 62 | #define SWITCHES_EDGE_TYPE NONE 63 | #define SWITCHES_FREQ 50000000 64 | #define SWITCHES_HAS_IN 1 65 | #define SWITCHES_HAS_OUT 0 66 | #define SWITCHES_HAS_TRI 0 67 | #define SWITCHES_IRQ_TYPE LEVEL 68 | #define SWITCHES_RESET_VALUE 0 69 | 70 | /* 71 | * Macros for device 'leds', class 'altera_avalon_pio' 72 | * The macros are prefixed with 'LEDS_'. 73 | * The prefix is the slave descriptor. 74 | */ 75 | #define LEDS_COMPONENT_TYPE altera_avalon_pio 76 | #define LEDS_COMPONENT_NAME leds 77 | #define LEDS_BASE 0x20 78 | #define LEDS_SPAN 16 79 | #define LEDS_END 0x2f 80 | #define LEDS_BIT_CLEARING_EDGE_REGISTER 0 81 | #define LEDS_BIT_MODIFYING_OUTPUT_REGISTER 0 82 | #define LEDS_CAPTURE 0 83 | #define LEDS_DATA_WIDTH 10 84 | #define LEDS_DO_TEST_BENCH_WIRING 0 85 | #define LEDS_DRIVEN_SIM_VALUE 0 86 | #define LEDS_EDGE_TYPE NONE 87 | #define LEDS_FREQ 50000000 88 | #define LEDS_HAS_IN 0 89 | #define LEDS_HAS_OUT 1 90 | #define LEDS_HAS_TRI 0 91 | #define LEDS_IRQ_TYPE NONE 92 | #define LEDS_RESET_VALUE 0 93 | 94 | /* 95 | * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart' 96 | * The macros are prefixed with 'JTAG_UART_'. 97 | * The prefix is the slave descriptor. 98 | */ 99 | #define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart 100 | #define JTAG_UART_COMPONENT_NAME jtag_uart 101 | #define JTAG_UART_BASE 0x30 102 | #define JTAG_UART_SPAN 8 103 | #define JTAG_UART_END 0x37 104 | #define JTAG_UART_READ_DEPTH 64 105 | #define JTAG_UART_READ_THRESHOLD 8 106 | #define JTAG_UART_WRITE_DEPTH 64 107 | #define JTAG_UART_WRITE_THRESHOLD 8 108 | 109 | /* 110 | * Macros for device 'SYS_ID', class 'altera_avalon_sysid_qsys' 111 | * The macros are prefixed with 'SYS_ID_'. 112 | * The prefix is the slave descriptor. 113 | */ 114 | #define SYS_ID_COMPONENT_TYPE altera_avalon_sysid_qsys 115 | #define SYS_ID_COMPONENT_NAME SYS_ID 116 | #define SYS_ID_BASE 0x10000 117 | #define SYS_ID_SPAN 8 118 | #define SYS_ID_END 0x10007 119 | #define SYS_ID_ID 2899645186 120 | #define SYS_ID_TIMESTAMP 1514375775 121 | 122 | /* 123 | * Macros for device 'alt_vip_vfr_vga', class 'alt_vip_vfr' 124 | * The macros are prefixed with 'ALT_VIP_VFR_VGA_'. 125 | * The prefix is the slave descriptor. 126 | */ 127 | #define ALT_VIP_VFR_VGA_COMPONENT_TYPE alt_vip_vfr 128 | #define ALT_VIP_VFR_VGA_COMPONENT_NAME alt_vip_vfr_vga 129 | #define ALT_VIP_VFR_VGA_BASE 0x20000 130 | #define ALT_VIP_VFR_VGA_SPAN 128 131 | #define ALT_VIP_VFR_VGA_END 0x2007f 132 | 133 | 134 | #endif /* _ALTERA_MASTER_NON_SEC_H_ */ 135 | -------------------------------------------------------------------------------- /runtime/main.cpp: -------------------------------------------------------------------------------- 1 | #include "runtime.h" 2 | 3 | int main() 4 | { 5 | Runtime runtime; 6 | runtime.run(); 7 | return 0; 8 | } 9 | -------------------------------------------------------------------------------- /runtime/plcbus.h: -------------------------------------------------------------------------------- 1 | #ifndef PLCBUS_H 2 | #define PLCBUS_H 3 | 4 | #include "settings.h" 5 | #include "plcstate.h" 6 | #include 7 | #include 8 | 9 | #define MODULE_TYPE_DI 0x00000001 10 | #define MODULE_TYPE_DO 0x00000002 11 | #define MODULE_TYPE_AI 0x00000004 12 | #define MODULE_TYPE_AO 0x00000008 13 | #define MODULE_TYPE_PN 0x00000010 14 | #define MODULE_TYPE_PB 0x00000020 15 | #define MODULE_TYPE_CPU 0x00000040 16 | //#define MODULE_TYPE_ 0x00000000 17 | 18 | struct ModuleInfo 19 | { 20 | uint32_t type; 21 | uint32_t sub_type; 22 | 23 | uint32_t rack; 24 | uint32_t rack_idx; 25 | 26 | uint32_t input_start; 27 | uint32_t input_size; 28 | uint32_t output_start; 29 | uint32_t output_size; 30 | 31 | uint32_t PB_addr; 32 | uint32_t PN_addr; 33 | 34 | module_state_t state; 35 | // only on PLC 36 | bool finded; 37 | }; 38 | 39 | enum class EBusRequest 40 | { 41 | UNKNOWN = 0x00, 42 | FIND_DEVICE = 0x01, 43 | SET_RACK_IDX = 0x02, 44 | READ_INPUTS = 0x03, 45 | WRITE_OUTPUTS = 0x04, 46 | }; 47 | 48 | enum class EBusReply 49 | { 50 | UNKNOWN, 51 | OK, 52 | FAIL, 53 | }; 54 | 55 | struct BusMessage 56 | { 57 | uint32_t from; // index on rack 58 | uint32_t to; // index on rack 59 | union 60 | { 61 | uint32_t request_uint; 62 | EBusRequest request; 63 | }; 64 | union 65 | { 66 | uint32_t reply_uint; 67 | EBusReply reply; 68 | }; 69 | uint32_t data_size; 70 | union 71 | { 72 | uint8_t data[BUS_MSG_DATA_SIZE]; 73 | ModuleInfo module_info; 74 | uint32_t rack_idx; 75 | }; 76 | }; 77 | 78 | class PLCBus 79 | { 80 | public: 81 | bool init(); 82 | void copy_inputs(); 83 | void copy_outputs(); 84 | void bus_proc(); 85 | 86 | bool load_config(); 87 | private: 88 | int m_bus_dev; 89 | BusMessage m_send; 90 | BusMessage m_recv; 91 | uint8_t m_PIP[IO_AREA_SIZE]; 92 | uint8_t m_POP[IO_AREA_SIZE]; 93 | ModuleInfo m_modules_list[BUS_MAX_MODULES]; 94 | uint32_t m_count; 95 | 96 | bool init_UART(); 97 | bool search_modules(); 98 | 99 | bool load_module_info(ModuleInfo &module, Json::Value &info); 100 | }; 101 | 102 | #endif // PLCBUS_H 103 | -------------------------------------------------------------------------------- /runtime/plcdata.cpp: -------------------------------------------------------------------------------- 1 | #include "plcdata.h" 2 | 3 | DataInterface plc_inputs; 4 | DataInterface plc_outputs; 5 | DataInterface plc_memory; 6 | -------------------------------------------------------------------------------- /runtime/plcdata.h: -------------------------------------------------------------------------------- 1 | #ifndef PLCDATA_H 2 | #define PLCDATA_H 3 | 4 | #include "settings.h" 5 | #include "datainterface.h" 6 | 7 | extern DataInterface plc_inputs; 8 | extern DataInterface plc_outputs; 9 | extern DataInterface plc_memory; 10 | 11 | #endif // PLCDATA_H 12 | -------------------------------------------------------------------------------- /runtime/plcstate.cpp: -------------------------------------------------------------------------------- 1 | #include "plcstate.h" 2 | #include "settings.h" 3 | 4 | plc_state_t PLCState::m_state; 5 | EPLCState PLCState::m_state_en; 6 | bool PLCState::m_blink_on; 7 | 8 | void PLCState::init() 9 | { 10 | m_blink_on = false; 11 | 12 | m_state.pwr_on = true; 13 | m_state.pwr_ok = true; // TODO: check ADC 14 | 15 | m_state.stop_load = false; 16 | m_state.stop_fault = false; 17 | m_state.stop_stop = true; 18 | 19 | m_state.run_load = false; 20 | m_state.run_run = false; 21 | 22 | m_state.fault = false; 23 | m_state_en = EPLCState::INIT; 24 | } 25 | 26 | void PLCState::to_stop() 27 | { 28 | m_state.stop_stop = true; 29 | m_state.run_run = false; 30 | m_state_en = EPLCState::STOP; 31 | } 32 | 33 | void PLCState::to_full_stop() 34 | { 35 | m_state.stop_load = false; 36 | m_state.stop_fault = false; 37 | m_state.stop_stop = true; 38 | 39 | m_state.run_load = false; 40 | m_state.run_run = false; 41 | 42 | m_state.fault = false; 43 | } 44 | 45 | void PLCState::to_load_fw_in_plc() 46 | { 47 | m_state.stop_load = true; 48 | m_state_en = EPLCState::LOAD_FW; 49 | } 50 | 51 | void PLCState::to_wait_fw_in_plc() 52 | { 53 | m_state.stop_load = true; 54 | m_state_en = EPLCState::WAIT_FW; 55 | } 56 | 57 | void PLCState::to_bus_init() 58 | { 59 | m_state_en = EPLCState::BUS_INIT; 60 | } 61 | 62 | void PLCState::to_fw_load() 63 | { 64 | m_state.run_run = true; 65 | m_state.run_load = true; 66 | m_state_en = EPLCState::RUN; 67 | } 68 | 69 | void PLCState::to_run() 70 | { 71 | m_state.stop_stop = false; 72 | m_state.run_run = true; 73 | m_state.run_load = false; 74 | m_state_en = EPLCState::RUN; 75 | } 76 | 77 | void PLCState::to_error() 78 | { 79 | m_state.fault = true; 80 | } 81 | 82 | void PLCState::to_fault() 83 | { 84 | m_state.stop_stop = true; 85 | m_state.run_run = false; 86 | m_state.fault = true; 87 | m_state_en = EPLCState::FAULT; 88 | } 89 | 90 | #define LED_PWR_OFFSET 3 91 | #define LED_STP_OFFSET 4 92 | #define LED_RUN_OFFSET 5 93 | #define LED_FLT_OFFSET 6 94 | #define LED_FLTRL_OFFSET 7 95 | 96 | #ifdef FPGA_ALLOW 97 | #include "hps_0_arm_a9_0.h" 98 | #endif 99 | 100 | void PLCState::signal_1Hz() 101 | { 102 | m_blink_on = !m_blink_on; 103 | 104 | #ifdef FPGA_ALLOW 105 | char led_byte = 0; 106 | 107 | if (m_state.pwr_on) 108 | { 109 | if (m_state.pwr_ok || m_blink_on) 110 | led_byte |= (1 << LED_PWR_OFFSET); 111 | } 112 | 113 | if (m_state.stop_stop) 114 | { 115 | if ((m_state.stop_fault || m_state.stop_load) && m_blink_on) 116 | led_byte |= (1 << LED_STP_OFFSET); 117 | } 118 | 119 | if (m_state.run_run) 120 | { 121 | if (m_state.run_load && m_blink_on) 122 | led_byte |= (1 << LED_RUN_OFFSET); 123 | } 124 | 125 | if (m_state.fault) 126 | led_byte |= (1 << LED_FLT_OFFSET); 127 | 128 | //TODO: digital output! 129 | if (m_state.fault_relay) 130 | led_byte |= (1 << LED_FLTRL_OFFSET); 131 | 132 | *((char*)LEDS_BASE) = led_byte; 133 | #endif 134 | } 135 | -------------------------------------------------------------------------------- /runtime/plcstate.h: -------------------------------------------------------------------------------- 1 | #ifndef PLCSTATE_H 2 | #define PLCSTATE_H 3 | 4 | typedef struct 5 | { 6 | /* 7 | * 1) power on & voltage>=12V -> PWR_LED ON 8 | * 2) power on & voltage< 12V -> PWR_LED flashing 9 | * 3) power off | voltage< 05V -> PWR_LED OFF 10 | */ 11 | bool pwr_on: 1; 12 | bool pwr_ok: 1; 13 | 14 | /* 15 | * 1) PLC stoped -> STP_LED ON 16 | * 2) load FW to PLC -> STP_LED flashing 17 | * 3) fault/errors -> STP_LED flashing 18 | * 3) PLC run -> STP_LED OFF 19 | */ 20 | bool stop_load: 1; 21 | bool stop_fault: 1; 22 | bool stop_stop: 1; 23 | 24 | /* 25 | * 1) firmware not loaded fully -> RUN_LED flashing 26 | * 2) FW running -> RUN_LED ON 27 | * 3) stop/fault -> RUN_LED OFF 28 | */ 29 | bool run_load: 1; 30 | bool run_run: 1; 31 | 32 | bool fault: 1; 33 | 34 | bool fault_relay: 1; 35 | } plc_state_t; 36 | 37 | enum class EPLCState 38 | { 39 | INIT, 40 | LOAD_FW, 41 | WAIT_FW, 42 | BUS_INIT, 43 | RUN, 44 | STOP, 45 | FAULT, 46 | }; 47 | 48 | typedef struct 49 | { 50 | bool initialized: 1; 51 | bool overrun: 1; 52 | bool fault: 1; 53 | } module_state_t; 54 | 55 | class PLCState 56 | { 57 | public: 58 | static void init(); 59 | static void signal_1Hz(); 60 | 61 | static void to_stop(); 62 | static void to_full_stop(); 63 | static void to_load_fw_in_plc(); 64 | static void to_wait_fw_in_plc(); 65 | 66 | static void to_bus_init(); 67 | 68 | static void to_fw_load(); 69 | static void to_run(); 70 | 71 | static void to_error(); 72 | static void to_fault(); 73 | 74 | static inline void reset_fault_relay() { m_state.fault_relay = false; } 75 | static inline void fault_relay_ON() { m_state.fault_relay = true; } 76 | 77 | static inline EPLCState get_state() { return m_state_en; } 78 | private: 79 | static plc_state_t m_state; 80 | static EPLCState m_state_en; 81 | static bool m_blink_on; 82 | }; 83 | 84 | #endif // PLCSTATE_H 85 | -------------------------------------------------------------------------------- /runtime/runtime.cpp: -------------------------------------------------------------------------------- 1 | #include "runtime.h" 2 | #include "firmware_sample/firmware.h" 3 | #include 4 | #include "plcbus.h" 5 | #include 6 | #include 7 | #include 8 | 9 | Firmware Runtime::m_firmware; 10 | PLCBus Runtime::m_bus; 11 | 12 | std::mutex mtx_run_cycle; 13 | 14 | #define CYCLE_TIME_START \ 15 | auto cycle_start = std::chrono::high_resolution_clock::now(); 16 | 17 | #define CYCLE_TIME_END(time) \ 18 | auto cycle_finish = std::chrono::high_resolution_clock::now(); \ 19 | auto cycle_time = std::chrono::duration_cast(cycle_finish - cycle_start).count(); \ 20 | cycle_time = time - cycle_time; \ 21 | if (cycle_time > 0) \ 22 | std::this_thread::sleep_for(std::chrono::milliseconds(cycle_time)); 23 | 24 | Runtime::Runtime() 25 | {} 26 | 27 | void Runtime::run() 28 | { 29 | PLCState::init(); 30 | PLCState::reset_fault_relay(); 31 | PLCState::to_full_stop(); 32 | 33 | //TODO: start server (debug + monitoring) 34 | 35 | std::thread th_comm(&Runtime::comm_thread, this); 36 | std::thread th_main(&Runtime::main_thread, this); 37 | 38 | bool fw_loaded; 39 | // one cycle on 100ms 40 | while (1) 41 | { 42 | CYCLE_TIME_START; 43 | 44 | switch (PLCState::get_state()) 45 | { 46 | case EPLCState::INIT: 47 | printf("State: Initialization\n"); 48 | PLCState::to_load_fw_in_plc(); 49 | break; 50 | 51 | case EPLCState::LOAD_FW: 52 | printf("State: Firmware loading\n"); 53 | fw_loaded = m_bus.load_config(); 54 | if (fw_loaded) 55 | fw_loaded = load_firmware(); 56 | 57 | if (fw_loaded) 58 | PLCState::to_bus_init(); 59 | else 60 | PLCState::to_wait_fw_in_plc(); 61 | break; 62 | 63 | case EPLCState::WAIT_FW: 64 | printf("State: Waiting firmware\n"); 65 | printf("Unable to loading firmware, wait uploading from remote device\n"); 66 | //TODO: uploading wait 67 | std::this_thread::sleep_for(std::chrono::milliseconds(500)); 68 | break; 69 | 70 | case EPLCState::BUS_INIT: 71 | printf("State: BUS initialization\n"); 72 | if (!m_bus.init()) 73 | { 74 | printf("Failed initialize BUS\n"); 75 | //PLCState::to_fault(); 76 | PLCState::to_run(); //TODO: debug 77 | } 78 | else 79 | PLCState::to_run(); 80 | break; 81 | 82 | case EPLCState::RUN: 83 | mtx_run_cycle.lock(); 84 | 85 | //TODO: to STOP (switch, command) 86 | if (false) 87 | { 88 | PLCState::to_stop(); 89 | break; 90 | } 91 | 92 | //TODO: to STOP (download) 93 | if (false) 94 | { 95 | PLCState::to_stop(); 96 | PLCState::to_load_fw_in_plc(); 97 | break; 98 | } 99 | 100 | mtx_run_cycle.unlock(); 101 | break; 102 | 103 | case EPLCState::STOP: 104 | //TODO: to wait FW 105 | //TODO: to run 106 | break; 107 | 108 | case EPLCState::FAULT: 109 | //TODO: to initialize (stop switch changed to RUN) 110 | break; 111 | } 112 | 113 | CYCLE_TIME_END(CYCLE_TIME_MMAIN); 114 | } 115 | 116 | th_comm.join(); 117 | th_main.join(); 118 | } 119 | 120 | bool Runtime::load_firmware() 121 | { 122 | //TODO 123 | // added to runtime project. 124 | if (!m_firmware.init()) 125 | return false; 126 | return true; 127 | } 128 | 129 | void Runtime::comm_thread() 130 | { 131 | // one cycle on 100ms 132 | while (1) 133 | { 134 | CYCLE_TIME_START; 135 | if (PLCState::get_state() == EPLCState::RUN) 136 | { 137 | m_bus.bus_proc(); 138 | // TODO: CP modules 139 | } 140 | CYCLE_TIME_END(CYCLE_TIME_COMM); 141 | } 142 | } 143 | 144 | void Runtime::main_thread() 145 | { 146 | int cycle_counter = 0; 147 | while (1) 148 | { 149 | auto cycle_start = std::chrono::high_resolution_clock::now(); 150 | 151 | mtx_run_cycle.lock(); 152 | if (PLCState::get_state() == EPLCState::RUN) 153 | { 154 | m_bus.copy_inputs(); 155 | if (!m_firmware.run_OB(EOB::OB_CYCLE_EXEC)) 156 | { 157 | m_firmware.run_OB(EOB::OB_CPU_FAULT); 158 | } 159 | m_bus.copy_outputs(); 160 | } 161 | mtx_run_cycle.unlock(); 162 | 163 | if (PLCState::get_state() == EPLCState::RUN) 164 | { 165 | auto cycle_finish = std::chrono::high_resolution_clock::now(); 166 | auto cycle_time = std::chrono::duration_cast(cycle_finish - cycle_start).count(); 167 | if (++cycle_counter > 1000*10) 168 | { 169 | printf("\rCycle time: %lli ns.", cycle_time); 170 | cycle_counter = 0; 171 | } 172 | } 173 | } 174 | } 175 | -------------------------------------------------------------------------------- /runtime/runtime.h: -------------------------------------------------------------------------------- 1 | #ifndef RUNTIME_H 2 | #define RUNTIME_H 3 | 4 | #include "settings.h" 5 | 6 | class Firmware; 7 | class PLCBus; 8 | struct ModuleInfo; 9 | 10 | class Runtime 11 | { 12 | public: 13 | Runtime(); 14 | 15 | void run(); 16 | private: 17 | static Firmware m_firmware; 18 | static PLCBus m_bus; 19 | 20 | bool load_firmware(); 21 | 22 | void comm_thread(); 23 | void main_thread(); 24 | }; 25 | 26 | #endif // RUNTIME_H 27 | -------------------------------------------------------------------------------- /runtime/runtime.pro: -------------------------------------------------------------------------------- 1 | TEMPLATE = app 2 | CONFIG += c++11 console 3 | CONFIG -= app_bundle 4 | CONFIG -= qt 5 | 6 | INCLUDEPATH += /usr/include/jsoncpp ./include/ 7 | 8 | LIBS += -ljsoncpp -lpthread 9 | 10 | target.path = /_cross/tmp 11 | INSTALLS += target 12 | 13 | SOURCES += main.cpp \ 14 | runtime.cpp \ 15 | firmware_sample/firmware.cpp \ 16 | firmware_sample/fwdb.cpp \ 17 | plcbus.cpp \ 18 | plcstate.cpp \ 19 | plcdata.cpp 20 | 21 | HEADERS += \ 22 | runtime.h \ 23 | firmware_sample/firmware.h \ 24 | firmware_sample/fwdb.h \ 25 | plcbus.h \ 26 | settings.h \ 27 | include/hps_0_arm_a9_0.h \ 28 | include/hps_0_arm_a9_1.h \ 29 | include/hps_0_bridges.h \ 30 | include/hps_0.h \ 31 | include/hps.h \ 32 | plcstate.h \ 33 | datainterface.h \ 34 | plcdata.h 35 | -------------------------------------------------------------------------------- /runtime/settings.h: -------------------------------------------------------------------------------- 1 | #ifndef SETTINGS_H 2 | #define SETTINGS_H 3 | 4 | #include 5 | 6 | //#define FPGA_ALLOW 7 | 8 | //cycle time settings (in ms) 9 | #define CYCLE_TIME_COMM 100 10 | #define CYCLE_TIME_MMAIN 100 11 | 12 | #define BUS_MSG_DATA_SIZE 100 13 | #ifdef FPGA_ALLOW 14 | #define BUS_UART_DEVICE "/dev/ttyAL0" 15 | #else 16 | #define BUS_UART_DEVICE "/dev/ttyUSB0" 17 | #endif 18 | #define BUS_UART_BRATE B9600 19 | 20 | #define BUS_MAX_MODULES 1024 21 | #define BUS_MAX_MODULES_ON_RACK 32 22 | #define BUS_WAIT_TIME_MS 50 23 | 24 | #define MEM_AREA_SIZE 4096 25 | #define IO_AREA_SIZE 4096 26 | 27 | #define RT_ROOT_PATH "./" 28 | 29 | #endif // SETTINGS_H 30 | -------------------------------------------------------------------------------- /stlc/CmdlineParser.cpp: -------------------------------------------------------------------------------- 1 | #include "CmdlineParser.h" 2 | #include 3 | 4 | CmdlineParser* CmdlineParser::m_instance = nullptr; 5 | 6 | /** 7 | * @brief CmdlineParser::CmdlineParser 8 | * @param argc Количество параметров командной строки 9 | * @param argv Массив параметров командной строки 10 | */ 11 | CmdlineParser::CmdlineParser(int argc, char** argv) 12 | { 13 | m_instance = this; 14 | 15 | m_argc = argc; 16 | m_argv.resize(m_argc); 17 | for (int i=0 ; im_params.push_back({type: EParamType::STRING, 37 | name: name, 38 | desc: desc, 39 | val_str: val, 40 | val_bool: nullptr, 41 | val_int: nullptr}); 42 | } 43 | 44 | /** 45 | * @brief Добавление булевого параметра 46 | * @param name Имя параметра (его идентификатор) 47 | * @param val Указатель на значение параметра 48 | * @param val_def Значение по умолчанию 49 | * @param desc Описание параметра 50 | */ 51 | void CmdlineParser::add_bool_param(const std::string &name, bool* val, const bool &val_def, const std::string &desc) 52 | { 53 | *val = val_def; 54 | m_instance->m_params.push_back({type: EParamType::BOOLEAN, 55 | name: name, 56 | desc: desc, 57 | val_str: nullptr, 58 | val_bool: val, 59 | val_int: nullptr}); 60 | } 61 | 62 | /** 63 | * @brief Добавление целочисленного параметра 64 | * @param name Имя параметра (его идентификатор) 65 | * @param val Указатель на значение параметра 66 | * @param val_def Значение по умолчанию 67 | * @param desc Описание параметра 68 | */ 69 | void CmdlineParser::add_int_param(const std::string &name, int* val, const int &val_def, const std::string &desc) 70 | { 71 | *val = val_def; 72 | m_instance->m_params.push_back({type: EParamType::INT, 73 | name: name, 74 | desc: desc, 75 | val_str: nullptr, 76 | val_bool: nullptr, 77 | val_int: val}); 78 | } 79 | 80 | /** 81 | * @brief Вывести описание параметров 82 | */ 83 | void CmdlineParser::show_desc() 84 | { 85 | std::cout << "Usage:" << std::endl << "\t" <m_name; 86 | for (param_rec_t ¶m : m_instance->m_params) 87 | { 88 | switch (param.type) 89 | { 90 | case EParamType::STRING: 91 | std::cout << "--" << param.name << " [val str](" << *param.val_str << ") "; 92 | break; 93 | case EParamType::BOOLEAN: 94 | std::cout << "--" << param.name << " "; 95 | break; 96 | case EParamType::INT: 97 | std::cout << "--" << param.name << " [val int](" << *param.val_int << ") "; 98 | break; 99 | } 100 | } 101 | 102 | std::cout << "\n\nParameters description:" << std::endl; 103 | for (param_rec_t ¶m : m_instance->m_params) 104 | std::cout << "\t--" << param.name << " - " << param.desc << std::endl; 105 | } 106 | 107 | /** 108 | * @brief Разбор аргументов командной строки 109 | */ 110 | void CmdlineParser::parse() 111 | { 112 | for (param_rec_t ¶m : m_instance->m_params) 113 | { 114 | std::string s_name = "--" + param.name; 115 | for (int i=0 ; im_argc ; i++) 116 | if (s_name.compare(m_instance->m_argv[i]) == 0) 117 | switch (param.type) 118 | { 119 | case EParamType::STRING: 120 | *param.val_str = m_instance->m_argv[i + 1]; 121 | break; 122 | case EParamType::BOOLEAN: 123 | *param.val_bool = true; 124 | break; 125 | case EParamType::INT: 126 | *param.val_int = std::stoi(m_instance->m_argv[i + 1]); 127 | break; 128 | } 129 | } 130 | } 131 | -------------------------------------------------------------------------------- /stlc/CmdlineParser.h: -------------------------------------------------------------------------------- 1 | #ifndef CMDLINEPARSER_H 2 | #define CMDLINEPARSER_H 3 | 4 | #include 5 | #include 6 | 7 | /** 8 | * @brief Перечисление типов параметров командной строки 9 | */ 10 | enum class EParamType 11 | { 12 | STRING, 13 | BOOLEAN, 14 | INT, 15 | }; 16 | 17 | /** @brief Структура для хранения сведений о параметре коммандной строки */ 18 | typedef struct 19 | { 20 | /** @brief Тип параметра */ 21 | EParamType type; 22 | /** @brief Имя параметра */ 23 | std::string name; 24 | /** @brief Описание параметра */ 25 | std::string desc; 26 | /** @brief Ссылка на строковое значение параметра */ 27 | std::string* val_str; 28 | /** @brief Ссылка на булевое значение параметра */ 29 | bool* val_bool; 30 | /** @brief Ссылка на численное значение параметра */ 31 | int* val_int; 32 | } param_rec_t; 33 | 34 | /** 35 | * @brief Класс для работы с параметрами командной строки 36 | */ 37 | class CmdlineParser 38 | { 39 | public: 40 | CmdlineParser(int argc, char** argv); 41 | virtual ~CmdlineParser(); 42 | /** @brief Получение текущего экземпляра объекта */ 43 | static CmdlineParser* get_instance() { return m_instance; } 44 | 45 | static void add_string_param(const std::string &name, std::string* val, const std::string &val_def, const std::string &desc); 46 | static void add_bool_param(const std::string &name, bool* val, const bool &val_def, const std::string &desc); 47 | static void add_int_param(const std::string &name, int* val, const int &val_def, const std::string &desc); 48 | 49 | /** @brief Установка имени приложения (для вывода в справке) */ 50 | static void set_name(std::string name) { m_instance->m_name = name; } 51 | static void show_desc(); 52 | static void parse(); 53 | protected: 54 | private: 55 | static CmdlineParser* m_instance; 56 | int m_argc; 57 | std::string m_name; 58 | std::vector m_argv; 59 | std::vector m_params; 60 | }; 61 | 62 | #endif // CMDLINEPARSER_H 63 | -------------------------------------------------------------------------------- /stlc/example/test.stl: -------------------------------------------------------------------------------- 1 | DATA_BLOCK DB 2 2 | TITLE = 3 | VERSION : 0.1 4 | 5 | 6 | STRUCT 7 | DB_VAR : INT ; //Temporary placeholder variable 8 | F1 : BOOl; 9 | F2: BOOL; 10 | F3: REAL; 11 | END_STRUCT ; 12 | BEGIN 13 | DB_VAR := 1056; 14 | F1:=true; 15 | F2:=false; 16 | F3:=0.1; 17 | END_DATA_BLOCK 18 | 19 | ORGANIZATION_BLOCK OB 1 20 | TITLE = "Main Program Sweep (Cycle)" 21 | //fffffe 22 | VERSION : 0.1 23 | 24 | 25 | VAR_TEMP 26 | OB1_EV_CLASS : BYTE ; //Bits 0-3 = 1 (Coming event), Bits 4-7 = 1 (Event class 1) 27 | OB1_SCAN_1 : BYTE ; //1 (Cold restart scan 1 of OB 1), 3 (Scan 2-n of OB 1) 28 | OB1_PRIORITY : BYTE ; //Priority of OB Execution 29 | OB1_OB_NUMBR : BYTE ; //1 (Organization block 1, OB1) 30 | OB1_RESERVED_1 : BYTE ; //Reserved for system 31 | OB1_RESERVED_2 : BYTE ; //Reserved for system 32 | OB1_PREV_CYCLE : INT ; //Cycle time of previous OB1 scan (milliseconds) 33 | OB1_MIN_CYCLE : INT ; //Minimum cycle time of OB1 (milliseconds) 34 | OB1_MAX_CYCLE : INT ; //Maximum cycle time of OB1 (milliseconds) 35 | OB1_DATE_TIME : DATE_AND_TIME ; //Date and time OB1 started 36 | END_VAR 37 | BEGIN 38 | 39 | NETWORK 40 | TITLE =title1 41 | //comm1 42 | A( ; //Pressing either start switch turns the motor on. 43 | A I 1.1; 44 | AN I 1.3; 45 | O ; 46 | A I 1.3; 47 | AN I 1.1; 48 | O Q 4.0; 49 | ) ; 50 | AN I 1.2; 51 | AN I 1.4; 52 | A I 1.5; 53 | = M 0.0; 54 | 55 | END_ORGANIZATION_BLOCK 56 | 57 | 58 | -------------------------------------------------------------------------------- /stlc/main.cpp: -------------------------------------------------------------------------------- 1 | #include "CmdlineParser.h" 2 | #include "stlc.h" 3 | 4 | int main(int argc, char *argv[]) 5 | { 6 | bool mode_compile, mode_decompile, show_help, iec; 7 | std::string in_file, out_file; 8 | 9 | CmdlineParser* cmd = new CmdlineParser(argc, argv); 10 | cmd->set_name("ST(L) Compilator/Decompilator"); 11 | cmd->add_bool_param("iec", &iec, false, "Compatible with IEC61131 ST (otherwise - Siemens STL)"); 12 | cmd->add_bool_param("compile", &mode_compile, false, "Compile mode"); 13 | cmd->add_bool_param("decompile", &mode_decompile, false, "Decompile mode"); 14 | cmd->add_bool_param("help", &show_help, false, "Show help and exit"); 15 | cmd->add_string_param("in", &in_file, "", "Input file"); 16 | cmd->add_string_param("out", &out_file, "", "Output file"); 17 | cmd->parse(); 18 | 19 | if (show_help) 20 | { 21 | cmd->show_desc(); 22 | return 0; 23 | } 24 | 25 | STLC stlc; 26 | 27 | if (mode_compile && (in_file.length()) && (out_file.length())) 28 | { 29 | if (stlc.load_plain(in_file, iec) && stlc.compile(out_file)) 30 | printf("Compilation finished: OK.\n"); 31 | else 32 | printf("Compilation finished: FAILED!\n"); 33 | } 34 | else 35 | cmd->show_desc(); 36 | 37 | return 0; 38 | } 39 | -------------------------------------------------------------------------------- /stlc/stlc.h: -------------------------------------------------------------------------------- 1 | #ifndef PLCC_H 2 | #define PLCC_H 3 | 4 | #include 5 | #include 6 | #include "plc_data_types.h" 7 | #include "stl_commands.h" 8 | 9 | enum class EParseMainLocation 10 | { 11 | NONE, 12 | DATA_BLOCK, 13 | ORGANIZATION_BLOCK, 14 | FUNCTION, 15 | FUNCTION_BLOCK, 16 | }; 17 | 18 | enum class EParseSubLocation 19 | { 20 | NONE, 21 | HEADER, 22 | // DB only 23 | STRUCTURE, 24 | DATA_INIT, 25 | // code blocks only 26 | VAR_INPUT, 27 | VAR_OUTPUT, 28 | VAR_INOUT, 29 | VAR_TEMP, 30 | VAR_STATIC, 31 | NETWORK, 32 | CALL_PARAMETERS, 33 | }; 34 | 35 | enum class EParseHeaderType 36 | { 37 | NONE, 38 | LABEL, 39 | TITLE, 40 | COMMENT, 41 | }; 42 | 43 | typedef struct 44 | { 45 | std::string line_raw; 46 | std::string label; 47 | std::string title; 48 | std::string comment; 49 | EParseHeaderType header_type; 50 | 51 | int block_no; 52 | 53 | // DB 54 | EDataType var_type; 55 | std::string var_name; 56 | EBlockType inst_block; 57 | int inst_no; 58 | union 59 | { 60 | plc_data_t var_value; 61 | plc_data_t par_addr; 62 | }; 63 | 64 | // network 65 | STL_CMD_t *cmd; 66 | int nw_idx; 67 | EParameterLocation par_loc; 68 | 69 | // CALL parameters 70 | std::string par_name; 71 | // functions 72 | EDataType result_type; 73 | 74 | EParseMainLocation loc; 75 | EParseSubLocation loc_sub; 76 | } stl_plaint_line_t; 77 | 78 | enum class EParseResult 79 | { 80 | OK = 0, 81 | PERROR = 1, 82 | SKIP = 2, 83 | NOT_APP = 3, 84 | WARNING = 4, 85 | BLOCK_END = 10, 86 | }; 87 | 88 | class Stream; 89 | 90 | class STLC 91 | { 92 | public: 93 | STLC(); 94 | 95 | bool load_plain(std::string, bool iec); 96 | bool compile(std::string); 97 | private: 98 | static STLC* m_instance; 99 | std::deque m_plain; 100 | 101 | bool parse_stl_plain(Stream*); 102 | EParseMainLocation parse_stl_plain_location(std::string &line); 103 | EParseResult parse_stl_plain_DB(std::string &line, stl_plaint_line_t &plain); 104 | EParseResult parse_stl_plain_code_block(std::string &line, stl_plaint_line_t &plain, 105 | const char *block_header, const char *block_abbr, 106 | const char *end_marker); 107 | 108 | EDataType parse_data_type(std::string str); 109 | EParseResult parse_value(std::string str, EDataType type, plc_data_t &value); 110 | stl_plaint_line_t* find_var_def(std::string name, int block_no, EParseMainLocation loc); 111 | 112 | std::string parse_title(std::string &str); 113 | EParseResult parse_stl_plain_block_header(std::string &line, stl_plaint_line_t &plain, 114 | const char* header, const char* block_abbr); 115 | EParseResult parse_stl_plain_var_struct(std::string &line, stl_plaint_line_t &plain, 116 | const char* end_label, EParameterLocation par_loc); 117 | EParseResult parse_stl_plain_DB_data_init(std::string &line, stl_plaint_line_t &plain); 118 | bool parse_stl_plain_DB_check_sub(std::string &line, stl_plaint_line_t &plain); 119 | bool parse_stl_plain_OB_check_sub(std::string &line, stl_plaint_line_t &plain); 120 | EParseResult parse_stl_plain_network(std::string &line, stl_plaint_line_t &plain, const char* end_block_label); 121 | EParseResult parse_stl_plain_call_parameter(std::string &line, stl_plaint_line_t &plain); 122 | EParseResult parse_stl_parameter_location(std::string str, stl_plaint_line_t &plain); 123 | bool parse_stl_parameter_SW(std::string str, stl_plaint_line_t &plain); 124 | }; 125 | 126 | #endif // PLCC_H 127 | -------------------------------------------------------------------------------- /stlc/stlc.pro: -------------------------------------------------------------------------------- 1 | QT -= core gui 2 | 3 | CONFIG += c++11 4 | 5 | TARGET = stlc 6 | CONFIG += console 7 | CONFIG -= app_bundle 8 | 9 | TEMPLATE = app 10 | 11 | INCLUDEPATH += ../firmware/fw_cpu/inc/ 12 | 13 | DEFINES += STLC_DEF 14 | 15 | QMAKE_CXXFLAGS_RELEASE += -s 16 | win32:QMAKE_LFLAGS_RELEASE += -s -static -static-libgcc -static-libstdc++ 17 | 18 | SOURCES += main.cpp \ 19 | CmdlineParser.cpp \ 20 | Stream.cpp \ 21 | stlc.cpp \ 22 | ../firmware/fw_cpu/src/stl_commands.cpp 23 | 24 | # The following define makes your compiler emit warnings if you use 25 | # any feature of Qt which as been marked deprecated (the exact warnings 26 | # depend on your compiler). Please consult the documentation of the 27 | # deprecated API in order to know how to port your code away from it. 28 | DEFINES += QT_DEPRECATED_WARNINGS 29 | 30 | # You can also make your code fail to compile if you use deprecated APIs. 31 | # In order to do so, uncomment the following line. 32 | # You can also select to disable deprecated APIs only up to a certain version of Qt. 33 | #DEFINES += QT_DISABLE_DEPRECATED_BEFORE=0x060000 # disables all the APIs deprecated before Qt 6.0.0 34 | 35 | HEADERS += \ 36 | CmdlineParser.h \ 37 | Stream.h \ 38 | stlc.h \ 39 | ../firmware/fw_cpu/inc/plc_data_types.h \ 40 | ../firmware/fw_cpu/inc/stl_commands.h \ 41 | ../firmware/fw_cpu/inc/plc_hw.h 42 | --------------------------------------------------------------------------------