├── LICENSE
├── Makefile
├── Readme.md
├── tsc.c
└── tsc.h
/LICENSE:
--------------------------------------------------------------------------------
1 | GNU GENERAL PUBLIC LICENSE
2 | Version 2, June 1991
3 |
4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
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--------------------------------------------------------------------------------
/Makefile:
--------------------------------------------------------------------------------
1 | #
2 | # makefile
3 | PROJECT=tsc
4 | SRCS=tsc.c
5 | INCL=tsc.h
6 | CFLAGS=-g -Wall
7 | LIBS=-lrt -lm -lpthread
8 |
9 | all: $(PROJECT)
10 |
11 | $(PROJECT): $(SRCS) $(INCL)
12 | gcc $(CFLAGS) -DTEST_TSC -DTSC_VERBOSE -o $(PROJECT) $(SRCS) $(LIBS)
13 |
14 | clean:
15 | rm -f $(PROJECT) *~ *.o
16 |
--------------------------------------------------------------------------------
/Readme.md:
--------------------------------------------------------------------------------
1 | # Convert Intel TSC to nanoseconds
2 |
3 | This is a test/demonstration program that shows the use of the rdtscp instruction under linux,
4 | and how to convert from cycles to nanoseconds for a subset of intel architecture processors.
5 |
6 | There are lots of ways it could go wrong, most of which don't apply to server processors of
7 | the type I use. For more information see http://blog.tinola.com/
8 |
9 |
10 |
11 |
12 |
--------------------------------------------------------------------------------
/tsc.c:
--------------------------------------------------------------------------------
1 | #define _GNU_SOURCE
2 | #include
3 | #include
4 | #include
5 | #include
6 | #include
7 | #include
8 | #include
9 | #include
10 |
11 | #include "tsc.h"
12 |
13 | struct processor_type_s tsc_processor_types[] = {
14 | { "Too Old/Unknown", 100000u },
15 | { "Nehalem", 133330u },
16 | { "Westmere", 133330u },
17 | { "Sandybridge", 100000u },
18 | { "Ivybridge", 100000u },
19 | { "Haswell", 100000u },
20 | { "Broadwell", 100000u },
21 | { "Skylake", 100000u },
22 | { "Xeon Phi", 100000u }
23 | };
24 |
25 |
26 | // -------------------
27 | //
28 | // TSC functions.
29 | //
30 | // requires a processor that supports the RDTSCP instruction. Or, use LFENCE; RDTSC
31 | // We can extract the socket and cpu we actually ran on from %ECX.
32 | // Intel Instruction Set reference. Vol 2B - 4-304.
33 | //
34 | // returns cycles from the expected cpu.
35 | uint64_t rdtscp(uint32_t expected_cpu)
36 | {
37 | uint32_t lo, hi, cpuid;
38 | #ifdef PARANOID_TSC
39 | uint32_t core, socket;
40 | #endif
41 | __asm__ __volatile__ ("rdtscp" : "=a" (lo), "=d" (hi), "=c" (cpuid)::);
42 | #ifdef PARANOID_TSC
43 | socket = (cpuid & 0xfff000)>>12;
44 | core = cpuid & 0xfff;
45 | if (core != expected_cpu) return -1;
46 | #endif
47 | return (uint64_t)hi << 32 | lo;
48 | }
49 | //
50 | // return the family and model in a single 32 bit integer.
51 | // Family 06 = the ones we're interested in. Family 15 = netburst xeons.
52 | // See;
53 | // https://software.intel.com/en-us/articles/intel-architecture-and-processor-identification-with-cpuid-model-and-family-numbers
54 | // and intel architecture developers manual.
55 | //
56 | static __inline__ uint32_t get_intel_family_model()
57 | {
58 | uint32_t model_register, model, family;
59 | int eax = 1;
60 |
61 | __asm__ __volatile__ ("cpuid" : "=a" (model_register): "a" (eax): "%ebx", "%ecx", "%edx");
62 |
63 | model = ((model_register & 0xff) >> 4) | ((model_register & 0xf0000) >> 12);
64 | family = ((model_register & 0xf00) >> 8) | ((model_register & 0xff00000) >> 16);
65 | return (family << 16) | model;
66 | }
67 |
68 | // used to determine if we have a 133.33 mhz or 100.00 mhz bclk.
69 | int get_processor_type(uint32_t family_model)
70 | {
71 | switch (family_model) {
72 | // nehalem - Section 35.5 Vol 3c
73 | case 0x6001a:
74 | case 0x6001e:
75 | case 0x6001f:
76 | case 0x6002e:
77 | return NEHALEM;
78 | // westmere - section 35.6
79 | case 0x60025:
80 | case 0x6002c:
81 | case 0x6002f:
82 | return WESTMERE;
83 | // sandy bridge - section 35.8
84 | case 0x6002a:
85 | case 0x6002d:
86 | return SANDYBRIDGE;
87 | case 0x6003a:
88 | case 0x6003e:
89 | return IVYBRIDGE;
90 | case 0x6003c:
91 | case 0x6003f:
92 | case 0x60045:
93 | case 0x60046:
94 | return HASWELL;
95 | case 0x6003d:
96 | case 0x60047:
97 | case 0x6004f:
98 | case 0x60056:
99 | return BROADWELL;
100 | case 0x6004e:
101 | case 0x6005e:
102 | return SKYLAKE;
103 | case 0x60057:
104 | return PHI;
105 | default:
106 | return TOO_OLD;
107 | }
108 | return TOO_OLD;
109 | }
110 |
111 | // read msrs - stolen from cpupower helpers
112 | // http://lxr.free-electrons.com/source/tools/power/cpupower/utils/helpers/msr.c#L26
113 | //
114 | int read_msr(int cpu, unsigned int idx, uint64_t *val)
115 | {
116 | int fd;
117 | char msr_file_name[64];
118 |
119 | sprintf(msr_file_name, "/dev/cpu/%d/msr", cpu);
120 | fd = open(msr_file_name, O_RDONLY);
121 | if (fd < 0) return -1;
122 | if (lseek(fd, idx, SEEK_CUR) == -1) goto err;
123 | if (read(fd, val, sizeof *val) != sizeof *val) goto err;
124 | close(fd);
125 | return 0;
126 | err:
127 | close(fd);
128 | return -1;
129 | }
130 | // 0xce is the intel MSR_PLATFORM_INFO.
131 | // SandyBridge or later (IvyBridge, Haswell) is a 100mhz clock. Nehalem/Westmere is a 133.33Mhz baseclock
132 | // See section 35.
133 | //
134 | // There are some caveats. This is only supported on recent processor families.
135 | //
136 | // Also, if the motherboard manufacturer messes about with the BCLK then the base_clock will be wrong.
137 | //
138 | uint32_t get_tsc_freq_khz(cpu)
139 | {
140 | uint64_t platform_info, non_turbo_ratio;
141 | int processor_type;
142 |
143 | processor_type = get_processor_type(get_intel_family_model());
144 |
145 | #ifdef TSC_VERBOSE
146 | printf ("Detected processor with family/model of %x\n",get_intel_family_model());
147 | printf ("This is a %s processor with a base clock of %dkhz\n", tsc_processor_types[processor_type].name, tsc_processor_types[processor_type].base_clock_khz);
148 | #endif
149 | if (processor_type == TOO_OLD) {
150 | fprintf(stderr,"processor too new, too old, or not detected\n");
151 | return -1;
152 | }
153 |
154 | if (read_msr(cpu,0xce, &platform_info) == -1) {
155 | fprintf(stderr,"error reading MSR_PLATFORM_INFO - Are you running this as root?\n");
156 | return -1;
157 | }
158 | non_turbo_ratio = (platform_info & 0xff00) >> 8;
159 | return non_turbo_ratio * tsc_processor_types[processor_type].base_clock_khz;
160 | }
161 |
162 | // See comment for the math behind this in arch/x86/kernel/tsc.c
163 | // http://lxr.free-electrons.com/source/arch/x86/kernel/tsc.c?v=3.18#L157
164 | //
165 | uint32_t get_cycles_to_nsec_scale(unsigned int tsc_frequency_khz)
166 | {
167 | return (uint32_t)((1000000)<<10 )/(uint32_t)tsc_frequency_khz;
168 | }
169 |
170 | uint64_t cycles_to_nsec(uint64_t cycles, uint32_t scale_factor)
171 | {
172 | return (cycles * scale_factor) >> 10;
173 | }
174 | //
175 | // TSC Routines
176 | // -------
177 |
178 | #ifdef TEST_TSC
179 | pid_t gettid(void) { return syscall(SYS_gettid); } // not in libc apparently
180 |
181 |
182 | // This needs to run as root.
183 | int main (int argc, char *argv[])
184 | {
185 | cpu_set_t cpuset;
186 | uint32_t cycles_nsec_scale, tsc_freq_khz;
187 | uint64_t start_timestamp, end_timestamp, cycles;
188 | int cpu;
189 |
190 | if (argc < 2) {
191 | fprintf (stderr,"./tsc \ne.g ./tsc 47\nwill pin to cpu47 and then run a simple timing loop to test tsc and cpu family ident\n");
192 | exit (0);
193 | }
194 |
195 | cpu = atoi(argv[1]);
196 |
197 | CPU_ZERO(&cpuset);
198 | CPU_SET(cpu,&cpuset);
199 |
200 | // set our cpu affinity. Ideally onto an isolated cpu.
201 | if (sched_setaffinity(gettid(),sizeof(cpu_set_t), &cpuset) != 0) {
202 | fprintf(stderr,"Thread %d: failed to set affinity to cpu %d. Reason was %s\n",gettid(),cpu,strerror(errno));
203 | exit(0);
204 | }
205 |
206 | // Get the MSR's idea of the TSC tick rate in khz
207 | tsc_freq_khz = get_tsc_freq_khz(cpu);
208 |
209 | // convert this into a scale factor
210 | cycles_nsec_scale = get_cycles_to_nsec_scale(tsc_freq_khz);
211 | printf("Invariant TSC runs at %u kHz, scale factor %u\n",tsc_freq_khz, cycles_nsec_scale);
212 |
213 | // simple timing exercise to see if we're close to reality
214 | start_timestamp = rdtscp(cpu);
215 | usleep(500000);
216 | end_timestamp = rdtscp(cpu);
217 |
218 | // The difference in timestamp cycles, converted to nanoseconds via the scale factor.
219 | cycles = (end_timestamp-start_timestamp);
220 | printf ("Expected to sleep for %u nanos, actually slept for %Lu cycles, %Lu nanos\n", (500000*1000), (unsigned long long)cycles, (unsigned long long)cycles_to_nsec(cycles, cycles_nsec_scale));
221 |
222 | return 0;
223 | }
224 | #endif
225 |
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/tsc.h:
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1 | // tsc.h
2 | #include
3 | #include
4 |
5 | //
6 | // check cpu we executed on was the one expected. Turn off for speed.
7 | #define PARANOID_TSC 1
8 | //
9 | // Print out processor id information
10 | //#define TSC_VERBOSE 1
11 | //
12 | // Run as a stand alone program for testing
13 | //#define TEST_TSC 1
14 | //
15 | // Identification for setting the bclk rate
16 | //
17 | enum {
18 | TOO_OLD,
19 | NEHALEM,
20 | WESTMERE,
21 | SANDYBRIDGE,
22 | IVYBRIDGE,
23 | HASWELL,
24 | BROADWELL,
25 | SKYLAKE,
26 | PHI
27 | } processor_enum;
28 |
29 | struct processor_type_s {
30 | char *name;
31 | unsigned int base_clock_khz;
32 | };
33 |
34 | extern struct processor_type_s tsc_processor_types[];
35 |
36 | // prototypes
37 | /* tsc.c */
38 | uint64_t rdtscp(uint32_t expected_cpu);
39 | int get_processor_type(uint32_t family_model);
40 | int read_msr(int cpu, unsigned int idx, uint64_t *val);
41 | uint32_t get_tsc_freq_khz(int cpu);
42 | uint32_t get_cycles_to_nsec_scale(unsigned int tsc_frequency_khz);
43 | uint64_t cycles_to_nsec(uint64_t cycles, uint32_t scale_factor);
44 |
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