├── .clang-format ├── .github ├── ISSUE_TEMPLATE │ ├── bug-report.yml │ ├── config.yml │ ├── feature-request.yml │ └── question.yml ├── dependabot.yml └── workflows │ └── build.yml ├── .gitignore ├── .pre-commit-config.yaml ├── .pylintrc ├── .readthedocs.yml ├── CMakeLists.txt ├── LICENSE.txt ├── MANIFEST.in ├── README.md ├── docs ├── Makefile ├── api.rst ├── conf.py ├── guide.rst ├── index.rst ├── languages.rst └── make.bat ├── pypcode ├── __init__.py ├── __main__.py ├── __version__.py ├── docs │ └── ghidra │ │ ├── DISCLAIMER.md │ │ ├── LICENSE │ │ └── NOTICE ├── printing.py ├── processors │ ├── 6502 │ │ └── data │ │ │ ├── languages │ │ │ ├── 6502.cspec │ │ │ ├── 6502.ldefs │ │ │ ├── 6502.pspec │ │ │ ├── 6502.slaspec │ │ │ └── 65c02.slaspec │ │ │ └── manuals │ │ │ ├── 6502.idx │ │ │ └── 65c02.idx │ ├── 8048 │ │ └── data │ │ │ ├── languages │ │ │ ├── 8048.cspec │ │ │ ├── 8048.ldefs │ │ │ ├── 8048.pspec │ │ │ └── 8048.slaspec │ │ │ └── manuals │ │ │ └── 8048.idx │ ├── 8051 │ │ └── data │ │ │ ├── languages │ │ │ ├── 80251.cspec │ │ │ ├── 80251.pspec │ │ │ ├── 80251.sinc │ │ │ ├── 80251.slaspec │ │ │ ├── 80390.cspec │ │ │ ├── 80390.slaspec │ │ │ ├── 8051.cspec │ │ │ ├── 8051.ldefs │ │ │ ├── 8051.opinion │ │ │ ├── 8051.pspec │ │ │ ├── 8051.slaspec │ │ │ ├── 8051_archimedes.cspec │ │ │ ├── 8051_main.sinc │ │ │ ├── mx51.cspec │ │ │ ├── mx51.pspec │ │ │ ├── mx51.sinc │ │ │ ├── mx51.slaspec │ │ │ └── old │ │ │ │ ├── 8051v1.lang │ │ │ │ └── 8051v1.trans │ │ │ └── manuals │ │ │ └── 8051.idx │ ├── 8085 │ │ └── data │ │ │ └── languages │ │ │ ├── 8085.cspec │ │ │ ├── 8085.ldefs │ │ │ ├── 8085.pspec │ │ │ └── 8085.slaspec │ ├── 68000 │ │ └── data │ │ │ ├── languages │ │ │ ├── 68000.cspec │ │ │ ├── 68000.dwarf │ │ │ ├── 68000.ldefs │ │ │ ├── 68000.opinion │ │ │ ├── 68000.pspec │ │ │ ├── 68000.sinc │ │ │ ├── 68000_register.cspec │ │ │ ├── 68020.slaspec │ │ │ ├── 68030.slaspec │ │ │ ├── 68040.slaspec │ │ │ └── coldfire.slaspec │ │ │ ├── manuals │ │ │ └── 68000.idx │ │ │ └── patterns │ │ │ ├── 68000_patterns.xml │ │ │ └── patternconstraints.xml │ ├── AARCH64 │ │ └── data │ │ │ ├── aarch64-pltThunks.xml │ │ │ ├── languages │ │ │ ├── AARCH64.cspec │ │ │ ├── AARCH64.dwarf │ │ │ ├── AARCH64.ldefs │ │ │ ├── AARCH64.opinion │ │ │ ├── AARCH64.pspec │ │ │ ├── AARCH64.slaspec │ │ │ ├── AARCH64BE.slaspec │ │ │ ├── AARCH64_AMXext.sinc │ │ │ ├── AARCH64_AppleSilicon.slaspec │ │ │ ├── AARCH64_base_PACoptions.sinc │ │ │ ├── AARCH64_golang.cspec │ │ │ ├── AARCH64_golang.register.info │ │ │ ├── AARCH64_ilp32.cspec │ │ │ ├── AARCH64_swift.cspec │ │ │ ├── AARCH64_win.cspec │ │ │ ├── AARCH64base.sinc │ │ │ ├── AARCH64instructions.sinc │ │ │ ├── AARCH64ldst.sinc │ │ │ ├── AARCH64neon.sinc │ │ │ ├── AARCH64sve.sinc │ │ │ └── AppleSilicon.ldefs │ │ │ ├── manuals │ │ │ └── AARCH64.idx │ │ │ └── patterns │ │ │ ├── AARCH64_LE_patterns.xml │ │ │ ├── AARCH64_win_patterns.xml │ │ │ ├── patternconstraints.xml │ │ │ └── prepatternconstraints.xml │ ├── ARM │ │ └── data │ │ │ ├── languages │ │ │ ├── ARM.cspec │ │ │ ├── ARM.dwarf │ │ │ ├── ARM.gdis │ │ │ ├── ARM.ldefs │ │ │ ├── ARM.opinion │ │ │ ├── ARM.sinc │ │ │ ├── ARM4_be.slaspec │ │ │ ├── ARM4_le.slaspec │ │ │ ├── ARM4t_be.slaspec │ │ │ ├── ARM4t_le.slaspec │ │ │ ├── ARM5_be.slaspec │ │ │ ├── ARM5_le.slaspec │ │ │ ├── ARM5t_be.slaspec │ │ │ ├── ARM5t_le.slaspec │ │ │ ├── ARM6_be.slaspec │ │ │ ├── ARM6_le.slaspec │ │ │ ├── ARM7_be.slaspec │ │ │ ├── ARM7_le.slaspec │ │ │ ├── ARM8_be.slaspec │ │ │ ├── ARM8_le.slaspec │ │ │ ├── ARM8m_be.slaspec │ │ │ ├── ARM8m_le.slaspec │ │ │ ├── ARMCortex.pspec │ │ │ ├── ARMTHUMBinstructions.sinc │ │ │ ├── ARM_CDE.sinc │ │ │ ├── ARM_v45.cspec │ │ │ ├── ARM_v45.pspec │ │ │ ├── ARM_win.cspec │ │ │ ├── ARMinstructions.sinc │ │ │ ├── ARMneon.dwarf │ │ │ ├── ARMneon.sinc │ │ │ ├── ARMt.pspec │ │ │ ├── ARMtTHUMB.pspec │ │ │ ├── ARMt_v45.pspec │ │ │ ├── ARMt_v6.pspec │ │ │ ├── ARMv8.sinc │ │ │ └── old │ │ │ │ ├── ARMv5.lang │ │ │ │ ├── ARMv5.trans │ │ │ │ ├── THUMBv2.lang │ │ │ │ └── THUMBv2.trans │ │ │ ├── manuals │ │ │ └── ARM.idx │ │ │ └── patterns │ │ │ ├── ARM_BE_patterns.xml │ │ │ ├── ARM_LE_patterns.xml │ │ │ ├── ARM_switch_patterns.xml │ │ │ ├── patternconstraints.xml │ │ │ └── prepatternconstraints.xml │ ├── Atmel │ │ └── data │ │ │ ├── languages │ │ │ ├── atmega256.pspec │ │ │ ├── avr32.opinion │ │ │ ├── avr32a.cspec │ │ │ ├── avr32a.ldefs │ │ │ ├── avr32a.pspec │ │ │ ├── avr32a.slaspec │ │ │ ├── avr32a_arithmetic_operations.sinc │ │ │ ├── avr32a_autogen.sinc │ │ │ ├── avr32a_bit_operations.sinc │ │ │ ├── avr32a_coprocessor_interface.sinc │ │ │ ├── avr32a_data_transfer.sinc │ │ │ ├── avr32a_dsp_operations.sinc │ │ │ ├── avr32a_dsp_operations2.sinc │ │ │ ├── avr32a_instruction_flow.sinc │ │ │ ├── avr32a_logic_operations.sinc │ │ │ ├── avr32a_multiplication_operations.sinc │ │ │ ├── avr32a_shift_operations.sinc │ │ │ ├── avr32a_simd_operations.sinc │ │ │ ├── avr32a_system_control.sinc │ │ │ ├── avr8.ldefs │ │ │ ├── avr8.opinion │ │ │ ├── avr8.pspec │ │ │ ├── avr8.sinc │ │ │ ├── avr8.slaspec │ │ │ ├── avr8e.slaspec │ │ │ ├── avr8egcc.cspec │ │ │ ├── avr8eind.slaspec │ │ │ ├── avr8gcc.cspec │ │ │ ├── avr8iarV1.cspec │ │ │ ├── avr8imgCraftV8.cspec │ │ │ ├── avr8xmega.pspec │ │ │ └── avr8xmega.slaspec │ │ │ ├── manuals │ │ │ ├── AVR32.idx │ │ │ └── AVR8.idx │ │ │ └── patterns │ │ │ ├── AVR8_patterns.xml │ │ │ └── patternconstraints.xml │ ├── BPF │ │ └── data │ │ │ └── languages │ │ │ ├── BPF.cspec │ │ │ ├── BPF.ldefs │ │ │ ├── BPF.pspec │ │ │ ├── BPF.sinc │ │ │ └── BPF_le.slaspec │ ├── CP1600 │ │ └── data │ │ │ └── languages │ │ │ ├── CP1600.cspec │ │ │ ├── CP1600.ldefs │ │ │ ├── CP1600.opinion │ │ │ ├── CP1600.pspec │ │ │ └── CP1600.slaspec │ ├── CR16 │ │ └── data │ │ │ ├── languages │ │ │ ├── CR16.cspec │ │ │ ├── CR16.ldefs │ │ │ ├── CR16.opinion │ │ │ ├── CR16.pspec │ │ │ ├── CR16B.sinc │ │ │ ├── CR16B.slaspec │ │ │ ├── CR16C.sinc │ │ │ └── CR16C.slaspec │ │ │ └── manuals │ │ │ └── CR16.idx │ ├── DATA │ │ └── data │ │ │ └── languages │ │ │ ├── data-be-64.slaspec │ │ │ ├── data-le-64.slaspec │ │ │ ├── data-ptr16.cspec │ │ │ ├── data-ptr32.cspec │ │ │ ├── data-ptr64.cspec │ │ │ ├── data.ldefs │ │ │ ├── data.pspec │ │ │ └── data.sinc │ ├── Dalvik │ │ └── data │ │ │ └── languages │ │ │ ├── Dalvik.ldefs │ │ │ ├── Dalvik.opinion │ │ │ ├── Dalvik_Base.cspec │ │ │ ├── Dalvik_Base.pspec │ │ │ ├── Dalvik_Base.sinc │ │ │ ├── Dalvik_Base.slaspec │ │ │ ├── Dalvik_DEX_Android10.slaspec │ │ │ ├── Dalvik_DEX_Android11.slaspec │ │ │ ├── Dalvik_DEX_Android12.slaspec │ │ │ ├── Dalvik_DEX_KitKat.slaspec │ │ │ ├── Dalvik_DEX_Lollipop.slaspec │ │ │ ├── Dalvik_DEX_Marshmallow.slaspec │ │ │ ├── Dalvik_DEX_Nougat.slaspec │ │ │ ├── Dalvik_DEX_Oreo.slaspec │ │ │ ├── Dalvik_DEX_Pie.slaspec │ │ │ ├── Dalvik_ODEX_KitKat.slaspec │ │ │ ├── Dalvik_OpCode_3E_43_unused.sinc │ │ │ ├── Dalvik_OpCode_73_return_void_barrier.sinc │ │ │ ├── Dalvik_OpCode_73_return_void_no_barrier.sinc │ │ │ ├── Dalvik_OpCode_73_unused.sinc │ │ │ ├── Dalvik_OpCode_79_unused.sinc │ │ │ ├── Dalvik_OpCode_7A_unused.sinc │ │ │ ├── Dalvik_OpCode_E3_EA_dex.sinc │ │ │ ├── Dalvik_OpCode_E3_EA_unused.sinc │ │ │ ├── Dalvik_OpCode_EB_F2_iput_iget.sinc │ │ │ ├── Dalvik_OpCode_EB_F2_unused.sinc │ │ │ ├── Dalvik_OpCode_F3_unused.sinc │ │ │ ├── Dalvik_OpCode_F4_unused.sinc │ │ │ ├── Dalvik_OpCode_F5_unused.sinc │ │ │ ├── Dalvik_OpCode_F6_unused.sinc │ │ │ ├── Dalvik_OpCode_F7_unused.sinc │ │ │ ├── Dalvik_OpCode_F8_unused.sinc │ │ │ ├── Dalvik_OpCode_F9_unused.sinc │ │ │ ├── Dalvik_OpCode_FA_FD_dex.sinc │ │ │ ├── Dalvik_OpCode_FA_unused.sinc │ │ │ ├── Dalvik_OpCode_FB_unused.sinc │ │ │ ├── Dalvik_OpCode_FC_unused.sinc │ │ │ ├── Dalvik_OpCode_FD_unused.sinc │ │ │ ├── Dalvik_OpCode_FE_FF_dex.sinc │ │ │ ├── Dalvik_OpCode_FE_unused.sinc │ │ │ └── Dalvik_OpCode_FF_unused.sinc │ ├── HCS08 │ │ └── data │ │ │ ├── languages │ │ │ ├── HC05-M68HC05TB.pspec │ │ │ ├── HC05.cspec │ │ │ ├── HC05.ldefs │ │ │ ├── HC05.pspec │ │ │ ├── HC05.slaspec │ │ │ ├── HC08-MC68HC908QY4.pspec │ │ │ ├── HC08.ldefs │ │ │ ├── HC08.pspec │ │ │ ├── HC08.slaspec │ │ │ ├── HCS08-MC9S08GB60.pspec │ │ │ ├── HCS08.cspec │ │ │ ├── HCS08.ldefs │ │ │ ├── HCS08.opinion │ │ │ ├── HCS08.pspec │ │ │ ├── HCS08.slaspec │ │ │ └── HCS_HC.sinc │ │ │ ├── manuals │ │ │ ├── HC05.idx │ │ │ ├── HC08.idx │ │ │ └── HCS08.idx │ │ │ └── test-vectors │ │ │ ├── HC05_tv.s │ │ │ ├── HC08_tv.s │ │ │ └── HCS08_tv.s │ ├── HCS12 │ │ └── data │ │ │ ├── languages │ │ │ ├── HC12.cspec │ │ │ ├── HC12.pspec │ │ │ ├── HC12.slaspec │ │ │ ├── HCS12.cspec │ │ │ ├── HCS12.ldefs │ │ │ ├── HCS12.opinion │ │ │ ├── HCS12.pspec │ │ │ ├── HCS12.slaspec │ │ │ ├── HCS12X.cspec │ │ │ ├── HCS12X.pspec │ │ │ ├── HCS12X.slaspec │ │ │ ├── HCS_HC12.sinc │ │ │ └── XGATE.sinc │ │ │ └── manuals │ │ │ └── HCS12.idx │ ├── JVM │ │ └── data │ │ │ ├── languages │ │ │ ├── JVM.cspec │ │ │ ├── JVM.ldefs │ │ │ ├── JVM.opinion │ │ │ ├── JVM.pspec │ │ │ └── JVM.slaspec │ │ │ └── manuals │ │ │ └── JVM.idx │ ├── Loongarch │ │ └── data │ │ │ ├── languages │ │ │ ├── ilp32d.cspec │ │ │ ├── ilp32f.cspec │ │ │ ├── lasx.sinc │ │ │ ├── lbt.sinc │ │ │ ├── loongarch.ldefs │ │ │ ├── loongarch.opinion │ │ │ ├── loongarch32.pspec │ │ │ ├── loongarch32_f32.slaspec │ │ │ ├── loongarch32_f64.slaspec │ │ │ ├── loongarch32_instructions.sinc │ │ │ ├── loongarch64.pspec │ │ │ ├── loongarch64_f32.slaspec │ │ │ ├── loongarch64_f64.slaspec │ │ │ ├── loongarch64_instructions.sinc │ │ │ ├── loongarch_double.sinc │ │ │ ├── loongarch_float.sinc │ │ │ ├── loongarch_main.sinc │ │ │ ├── lp64d.cspec │ │ │ ├── lp64f.cspec │ │ │ ├── lsx.sinc │ │ │ └── lvz.sinc │ │ │ ├── manuals │ │ │ └── loongarch.idx │ │ │ └── patterns │ │ │ ├── loongarch_patterns.xml │ │ │ └── patternconstraints.xml │ ├── M16C │ │ └── data │ │ │ ├── languages │ │ │ ├── M16C_60.cspec │ │ │ ├── M16C_60.ldefs │ │ │ ├── M16C_60.pspec │ │ │ ├── M16C_60.slaspec │ │ │ ├── M16C_80.cspec │ │ │ ├── M16C_80.ldefs │ │ │ ├── M16C_80.pspec │ │ │ └── M16C_80.slaspec │ │ │ └── manuals │ │ │ ├── M16C_60.idx │ │ │ └── M16C_80.idx │ ├── M8C │ │ └── data │ │ │ └── languages │ │ │ ├── m8c.cspec │ │ │ ├── m8c.ldefs │ │ │ ├── m8c.opinion │ │ │ ├── m8c.pspec │ │ │ └── m8c.slaspec │ ├── MC6800 │ │ └── data │ │ │ ├── languages │ │ │ ├── 6800.ldefs │ │ │ ├── 6805.cspec │ │ │ ├── 6805.ldefs │ │ │ ├── 6805.pspec │ │ │ ├── 6805.slaspec │ │ │ ├── 6809.cspec │ │ │ ├── 6809.pspec │ │ │ ├── 6809.slaspec │ │ │ ├── 6x09.sinc │ │ │ ├── 6x09_exg_tfr.sinc │ │ │ ├── 6x09_pull.sinc │ │ │ ├── 6x09_push.sinc │ │ │ └── H6309.slaspec │ │ │ └── manuals │ │ │ └── 6809.idx │ ├── MCS96 │ │ └── data │ │ │ ├── languages │ │ │ ├── MCS96.cspec │ │ │ ├── MCS96.ldefs │ │ │ ├── MCS96.pspec │ │ │ ├── MCS96.sinc │ │ │ └── MCS96.slaspec │ │ │ └── manuals │ │ │ └── MCS96.idx │ ├── MIPS │ │ └── data │ │ │ ├── languages │ │ │ ├── MIPS.opinion │ │ │ ├── mips.dwarf │ │ │ ├── mips.ldefs │ │ │ ├── mips.sinc │ │ │ ├── mips16.sinc │ │ │ ├── mips32.pspec │ │ │ ├── mips32Instructions.sinc │ │ │ ├── mips32R6.pspec │ │ │ ├── mips32R6be.slaspec │ │ │ ├── mips32R6le.slaspec │ │ │ ├── mips32_fp64.cspec │ │ │ ├── mips32be.cspec │ │ │ ├── mips32be.slaspec │ │ │ ├── mips32be_eabi.cspec │ │ │ ├── mips32le.cspec │ │ │ ├── mips32le.slaspec │ │ │ ├── mips32le_eabi.cspec │ │ │ ├── mips32micro.pspec │ │ │ ├── mips64.cspec │ │ │ ├── mips64.pspec │ │ │ ├── mips64Instructions.sinc │ │ │ ├── mips64R6.pspec │ │ │ ├── mips64_32_n32.cspec │ │ │ ├── mips64_32_o32.cspec │ │ │ ├── mips64_32_o64.cspec │ │ │ ├── mips64be.slaspec │ │ │ ├── mips64le.slaspec │ │ │ ├── mips64micro.pspec │ │ │ ├── mips_dsp.sinc │ │ │ ├── mips_mt.sinc │ │ │ ├── mipsfloat.sinc │ │ │ └── mipsmicro.sinc │ │ │ ├── manuals │ │ │ ├── MIPS.idx │ │ │ ├── mipsM16.idx │ │ │ ├── mipsMic.idx │ │ │ └── r4000.idx │ │ │ └── patterns │ │ │ ├── MIPS_BE_patterns.xml │ │ │ ├── MIPS_LE_patterns.xml │ │ │ └── patternconstraints.xml │ ├── PA-RISC │ │ └── data │ │ │ ├── languages │ │ │ ├── pa-risc.ldefs │ │ │ ├── pa-risc.opinion │ │ │ ├── pa-risc.sinc │ │ │ ├── pa-risc32.cspec │ │ │ ├── pa-risc32.pspec │ │ │ ├── pa-risc32be.slaspec │ │ │ └── pa-riscInstructions.sinc │ │ │ ├── manuals │ │ │ └── pa11_acd.idx │ │ │ └── patterns │ │ │ ├── pa-risc_patterns.xml │ │ │ └── patternconstraints.xml │ ├── PIC │ │ └── data │ │ │ ├── languages │ │ │ ├── PIC24.cspec │ │ │ ├── PIC24.ldefs │ │ │ ├── PIC24.opinion │ │ │ ├── PIC24.pspec │ │ │ ├── PIC24.sinc │ │ │ ├── PIC24E.slaspec │ │ │ ├── PIC24F.slaspec │ │ │ ├── PIC24H.slaspec │ │ │ ├── PIC30.dwarf │ │ │ ├── PIC33.dwarf │ │ │ ├── dsPIC30F.slaspec │ │ │ ├── dsPIC33C.slaspec │ │ │ ├── dsPIC33E.slaspec │ │ │ ├── dsPIC33F.slaspec │ │ │ ├── pic12.sinc │ │ │ ├── pic12_instructions.sinc │ │ │ ├── pic12c5xx.cspec │ │ │ ├── pic12c5xx.ldefs │ │ │ ├── pic12c5xx.pspec │ │ │ ├── pic12c5xx.slaspec │ │ │ ├── pic16.cspec │ │ │ ├── pic16.ldefs │ │ │ ├── pic16.pspec │ │ │ ├── pic16.sinc │ │ │ ├── pic16.slaspec │ │ │ ├── pic16_instructions.sinc │ │ │ ├── pic16c5x.cspec │ │ │ ├── pic16c5x.ldefs │ │ │ ├── pic16c5x.pspec │ │ │ ├── pic16c5x.slaspec │ │ │ ├── pic16f.cspec │ │ │ ├── pic16f.pspec │ │ │ ├── pic16f.slaspec │ │ │ ├── pic17c7xx.cspec │ │ │ ├── pic17c7xx.ldefs │ │ │ ├── pic17c7xx.pspec │ │ │ ├── pic17c7xx.sinc │ │ │ ├── pic17c7xx.slaspec │ │ │ ├── pic17c7xx_instructions.sinc │ │ │ ├── pic18.cspec │ │ │ ├── pic18.ldefs │ │ │ ├── pic18.pspec │ │ │ ├── pic18.sinc │ │ │ ├── pic18.slaspec │ │ │ └── pic18_instructions.sinc │ │ │ └── manuals │ │ │ ├── PIC-12.idx │ │ │ ├── PIC-16.idx │ │ │ ├── PIC-16F.idx │ │ │ ├── PIC-17.idx │ │ │ ├── PIC-18.idx │ │ │ └── PIC24.idx │ ├── PowerPC │ │ └── data │ │ │ ├── languages │ │ │ ├── 4xx.sinc │ │ │ ├── FPRC.sinc │ │ │ ├── PowerPC.opinion │ │ │ ├── SPEF_SCR.sinc │ │ │ ├── SPE_APU.sinc │ │ │ ├── SPE_EFSD.sinc │ │ │ ├── SPE_EFV.sinc │ │ │ ├── SPE_FloatMulAdd.sinc │ │ │ ├── Scalar_SPFP.sinc │ │ │ ├── altivec.sinc │ │ │ ├── evx.sinc │ │ │ ├── g2.sinc │ │ │ ├── lmwInstructions.sinc │ │ │ ├── lswInstructions.sinc │ │ │ ├── mulhwInstructions.sinc │ │ │ ├── old │ │ │ │ ├── oldPPC.lang │ │ │ │ └── oldPPC.trans │ │ │ ├── ppc.dwarf │ │ │ ├── ppc.ldefs │ │ │ ├── ppc_32.pspec │ │ │ ├── ppc_32_4xx_be.slaspec │ │ │ ├── ppc_32_4xx_le.slaspec │ │ │ ├── ppc_32_be.cspec │ │ │ ├── ppc_32_be.slaspec │ │ │ ├── ppc_32_be_Mac.cspec │ │ │ ├── ppc_32_e200.cspec │ │ │ ├── ppc_32_e200.pspec │ │ │ ├── ppc_32_e200.slaspec │ │ │ ├── ppc_32_e500_be.cspec │ │ │ ├── ppc_32_e500_be.slaspec │ │ │ ├── ppc_32_e500_le.cspec │ │ │ ├── ppc_32_e500_le.slaspec │ │ │ ├── ppc_32_e500mc_be.cspec │ │ │ ├── ppc_32_e500mc_be.slaspec │ │ │ ├── ppc_32_e500mc_le.cspec │ │ │ ├── ppc_32_e500mc_le.slaspec │ │ │ ├── ppc_32_le.cspec │ │ │ ├── ppc_32_le.slaspec │ │ │ ├── ppc_32_mpc8270.pspec │ │ │ ├── ppc_32_quicciii_be.slaspec │ │ │ ├── ppc_32_quicciii_le.slaspec │ │ │ ├── ppc_64.cspec │ │ │ ├── ppc_64.pspec │ │ │ ├── ppc_64_32.cspec │ │ │ ├── ppc_64_be.slaspec │ │ │ ├── ppc_64_be_Mac.cspec │ │ │ ├── ppc_64_isa_altivec_be.slaspec │ │ │ ├── ppc_64_isa_altivec_le.slaspec │ │ │ ├── ppc_64_isa_altivec_vle_be.slaspec │ │ │ ├── ppc_64_isa_be.slaspec │ │ │ ├── ppc_64_isa_le.slaspec │ │ │ ├── ppc_64_isa_vle_be.slaspec │ │ │ ├── ppc_64_le.slaspec │ │ │ ├── ppc_a2.sinc │ │ │ ├── ppc_common.sinc │ │ │ ├── ppc_embedded.sinc │ │ │ ├── ppc_instructions.sinc │ │ │ ├── ppc_isa.sinc │ │ │ ├── ppc_vle.sinc │ │ │ ├── quicciii.sinc │ │ │ ├── stmwInstructions.sinc │ │ │ ├── stswiInstructions.sinc │ │ │ └── vsx.sinc │ │ │ ├── manuals │ │ │ ├── PowerISA.idx │ │ │ └── PowerPC.idx │ │ │ ├── patterns │ │ │ ├── PPC_BE_patterns.xml │ │ │ ├── PPC_LE_patterns.xml │ │ │ └── patternconstraints.xml │ │ │ └── ppc64-r2CallStubs.xml │ ├── RISCV │ │ ├── data │ │ │ ├── languages │ │ │ │ ├── RV32G.pspec │ │ │ │ ├── RV32GC.pspec │ │ │ │ ├── RV32I.pspec │ │ │ │ ├── RV32IC.pspec │ │ │ │ ├── RV32IMC.pspec │ │ │ │ ├── RV64G.pspec │ │ │ │ ├── RV64GC.pspec │ │ │ │ ├── RV64I.pspec │ │ │ │ ├── RV64IC.pspec │ │ │ │ ├── riscv.csr.sinc │ │ │ │ ├── riscv.custom.sinc │ │ │ │ ├── riscv.ilp32d.slaspec │ │ │ │ ├── riscv.instr.sinc │ │ │ │ ├── riscv.ldefs │ │ │ │ ├── riscv.lp64d.slaspec │ │ │ │ ├── riscv.opinion │ │ │ │ ├── riscv.priv.sinc │ │ │ │ ├── riscv.reg.sinc │ │ │ │ ├── riscv.rv32a.sinc │ │ │ │ ├── riscv.rv32b.sinc │ │ │ │ ├── riscv.rv32d.sinc │ │ │ │ ├── riscv.rv32f.sinc │ │ │ │ ├── riscv.rv32i.sinc │ │ │ │ ├── riscv.rv32k.sinc │ │ │ │ ├── riscv.rv32m.sinc │ │ │ │ ├── riscv.rv32p.sinc │ │ │ │ ├── riscv.rv32q.sinc │ │ │ │ ├── riscv.rv64a.sinc │ │ │ │ ├── riscv.rv64b.sinc │ │ │ │ ├── riscv.rv64d.sinc │ │ │ │ ├── riscv.rv64f.sinc │ │ │ │ ├── riscv.rv64i.sinc │ │ │ │ ├── riscv.rv64k.sinc │ │ │ │ ├── riscv.rv64m.sinc │ │ │ │ ├── riscv.rv64p.sinc │ │ │ │ ├── riscv.rv64q.sinc │ │ │ │ ├── riscv.rvc.sinc │ │ │ │ ├── riscv.rvv.sinc │ │ │ │ ├── riscv.table.sinc │ │ │ │ ├── riscv.zi.sinc │ │ │ │ ├── riscv32-fp.cspec │ │ │ │ ├── riscv32.cspec │ │ │ │ ├── riscv32.dwarf │ │ │ │ ├── riscv64-fp.cspec │ │ │ │ ├── riscv64.cspec │ │ │ │ └── riscv64.dwarf │ │ │ └── patterns │ │ │ │ ├── patternconstraints.xml │ │ │ │ └── riscv_gc_patterns.xml │ │ └── scripts │ │ │ └── binutil.py │ ├── Sparc │ │ └── data │ │ │ ├── languages │ │ │ ├── Sparc.dwarf │ │ │ ├── Sparc.opinion │ │ │ ├── SparcV9.ldefs │ │ │ ├── SparcV9.pspec │ │ │ ├── SparcV9.sinc │ │ │ ├── SparcV9_32.cspec │ │ │ ├── SparcV9_32.slaspec │ │ │ ├── SparcV9_64.cspec │ │ │ ├── SparcV9_64.slaspec │ │ │ └── SparcVIS.sinc │ │ │ ├── manuals │ │ │ └── Sparc.idx │ │ │ └── patterns │ │ │ ├── SPARC_patterns.xml │ │ │ └── patternconstraints.xml │ ├── SuperH │ │ └── data │ │ │ └── languages │ │ │ ├── sh-1.slaspec │ │ │ ├── sh-2.slaspec │ │ │ ├── sh-2a.slaspec │ │ │ ├── superh.cspec │ │ │ ├── superh.ldefs │ │ │ ├── superh.pspec │ │ │ ├── superh.sinc │ │ │ └── superh2a.cspec │ ├── SuperH4 │ │ └── data │ │ │ ├── languages │ │ │ ├── SuperH4.ldefs │ │ │ ├── SuperH4.opinion │ │ │ ├── SuperH4.pspec │ │ │ ├── SuperH4.sinc │ │ │ ├── SuperH4_be.cspec │ │ │ ├── SuperH4_be.slaspec │ │ │ ├── SuperH4_le.cspec │ │ │ ├── SuperH4_le.slaspec │ │ │ └── old │ │ │ │ ├── SuperH4-BE-16.lang │ │ │ │ ├── SuperH4-BE-16.trans │ │ │ │ ├── SuperH4-LE-16.lang │ │ │ │ └── SuperH4-LE-16.trans │ │ │ ├── manuals │ │ │ └── superh4.idx │ │ │ └── patterns │ │ │ ├── SuperH4_patterns.xml │ │ │ └── patternconstraints.xml │ ├── TI_MSP430 │ │ └── data │ │ │ ├── languages │ │ │ ├── TI430Common.sinc │ │ │ ├── TI430X.sinc │ │ │ ├── TI_MSP430.cspec │ │ │ ├── TI_MSP430.dwarf │ │ │ ├── TI_MSP430.ldefs │ │ │ ├── TI_MSP430.pspec │ │ │ ├── TI_MSP430.slaspec │ │ │ ├── TI_MSP430X.cspec │ │ │ ├── TI_MSP430X.dwarf │ │ │ ├── TI_MSP430X.slaspec │ │ │ └── ti_msp430.opinion │ │ │ └── manuals │ │ │ └── MSP430.idx │ ├── Toy │ │ └── data │ │ │ └── languages │ │ │ ├── old │ │ │ ├── ToyV00BE64.lang │ │ │ ├── ToyV0BE64.trans │ │ │ ├── ToyV0LE64.lang │ │ │ ├── ToyV0LE64.trans │ │ │ └── v01stuff │ │ │ │ ├── toy.cspec │ │ │ │ ├── toy.ldefs_v01 │ │ │ │ ├── toy.sinc │ │ │ │ ├── toy64.cspec │ │ │ │ ├── toyInstructions.sinc │ │ │ │ └── toyPosStack.cspec │ │ │ ├── toy.cspec │ │ │ ├── toy.ldefs │ │ │ ├── toy.pspec │ │ │ ├── toy.sinc │ │ │ ├── toy64-long8.cspec │ │ │ ├── toy64.cspec │ │ │ ├── toy64_be.slaspec │ │ │ ├── toy64_be_harvard.slaspec │ │ │ ├── toy64_le.slaspec │ │ │ ├── toyInstructions.sinc │ │ │ ├── toyPosStack.cspec │ │ │ ├── toy_be.slaspec │ │ │ ├── toy_be_posStack.slaspec │ │ │ ├── toy_builder.sinc │ │ │ ├── toy_builder_be.slaspec │ │ │ ├── toy_builder_be_align2.slaspec │ │ │ ├── toy_builder_le.slaspec │ │ │ ├── toy_builder_le_align2.slaspec │ │ │ ├── toy_harvard.pspec │ │ │ ├── toy_le.slaspec │ │ │ ├── toy_wsz_be.slaspec │ │ │ └── toy_wsz_le.slaspec │ ├── V850 │ │ └── data │ │ │ ├── languages │ │ │ ├── Helpers │ │ │ │ ├── Conditions.sinc │ │ │ │ ├── Extras.sinc │ │ │ │ ├── Macros.sinc │ │ │ │ ├── Register.sinc │ │ │ │ ├── Tokens.sinc │ │ │ │ └── Variables.sinc │ │ │ ├── Instructions │ │ │ │ ├── Arithmetic.sinc │ │ │ │ ├── Float.sinc │ │ │ │ ├── Load_Store.sinc │ │ │ │ ├── Logic.sinc │ │ │ │ └── Special.sinc │ │ │ ├── V850.cspec │ │ │ ├── V850.ldefs │ │ │ ├── V850.opinion │ │ │ ├── V850.pspec │ │ │ └── V850.slaspec │ │ │ ├── manuals │ │ │ └── v850.idx │ │ │ └── patterns │ │ │ ├── V850_patterns.xml │ │ │ └── patternconstraints.xml │ ├── Xtensa │ │ └── data │ │ │ ├── languages │ │ │ ├── cust.sinc │ │ │ ├── flix.sinc │ │ │ ├── xtensa.cspec │ │ │ ├── xtensa.dwarf │ │ │ ├── xtensa.ldefs │ │ │ ├── xtensa.opinion │ │ │ ├── xtensa.pspec │ │ │ ├── xtensaArch.sinc │ │ │ ├── xtensaInstructions.sinc │ │ │ ├── xtensaMain.sinc │ │ │ ├── xtensa_be.slaspec │ │ │ ├── xtensa_depbits.sinc │ │ │ └── xtensa_le.slaspec │ │ │ ├── manuals │ │ │ └── xtensa.idx │ │ │ └── patterns │ │ │ ├── patternconstraints.xml │ │ │ └── xtensa_patterns.xml │ ├── Z80 │ │ ├── data │ │ │ ├── languages │ │ │ │ ├── z180.pspec │ │ │ │ ├── z180.slaspec │ │ │ │ ├── z182.pspec │ │ │ │ ├── z80.cspec │ │ │ │ ├── z80.ldefs │ │ │ │ ├── z80.pspec │ │ │ │ ├── z80.slaspec │ │ │ │ └── z8401x.pspec │ │ │ └── manuals │ │ │ │ ├── Z180.idx │ │ │ │ └── Z80.idx │ │ └── temp │ │ │ └── z8401x.pspec │ ├── eBPF │ │ └── data │ │ │ └── languages │ │ │ ├── eBPF.cspec │ │ │ ├── eBPF.dwarf │ │ │ ├── eBPF.ldefs │ │ │ ├── eBPF.opinion │ │ │ ├── eBPF.pspec │ │ │ ├── eBPF.sinc │ │ │ └── eBPF_le.slaspec │ ├── tricore │ │ └── data │ │ │ ├── languages │ │ │ ├── tc172x.pspec │ │ │ ├── tc176x.pspec │ │ │ ├── tc29x.pspec │ │ │ ├── tricore.cspec │ │ │ ├── tricore.dwarf │ │ │ ├── tricore.ldefs │ │ │ ├── tricore.opinion │ │ │ ├── tricore.pcp.sinc │ │ │ ├── tricore.pspec │ │ │ ├── tricore.sinc │ │ │ └── tricore.slaspec │ │ │ ├── manuals │ │ │ ├── tricore.idx │ │ │ └── tricore2.idx │ │ │ └── patterns │ │ │ ├── patternconstraints.xml │ │ │ └── tricore_patterns.xml │ └── x86 │ │ └── data │ │ ├── extensions │ │ └── rust │ │ │ ├── unix │ │ │ ├── cc.xml │ │ │ ├── probe_fixup.xml │ │ │ └── try_fixup.xml │ │ │ └── windows │ │ │ ├── probe_fixup.xml │ │ │ └── try_fixup.xml │ │ ├── languages │ │ ├── adx.sinc │ │ ├── avx.sinc │ │ ├── avx2.sinc │ │ ├── avx2_manual.sinc │ │ ├── avx512.sinc │ │ ├── avx512_manual.sinc │ │ ├── avx_manual.sinc │ │ ├── bmi1.sinc │ │ ├── bmi2.sinc │ │ ├── cet.sinc │ │ ├── clwb.sinc │ │ ├── fma.sinc │ │ ├── ia.sinc │ │ ├── lockable.sinc │ │ ├── lzcnt.sinc │ │ ├── macros.sinc │ │ ├── mpx.sinc │ │ ├── old │ │ │ ├── x86RealV1.lang │ │ │ ├── x86RealV1.trans │ │ │ ├── x86RealV2.lang │ │ │ ├── x86RealV2.trans │ │ │ ├── x86RealV3.lang │ │ │ ├── x86RealV3.trans │ │ │ ├── x86V1.lang │ │ │ ├── x86V1.trans │ │ │ ├── x86V2.lang │ │ │ ├── x86V2.trans │ │ │ ├── x86V3.lang │ │ │ ├── x86V3.trans │ │ │ ├── x86_64bit_compat32_v2.lang │ │ │ ├── x86_64bit_compat32_v2.trans │ │ │ ├── x86_64bit_compat32_v3.lang │ │ │ ├── x86_64bit_compat32_v3.trans │ │ │ ├── x86_64bit_v1.lang │ │ │ ├── x86_64bit_v1.trans │ │ │ ├── x86_64bit_v2.lang │ │ │ ├── x86_64bit_v2.trans │ │ │ ├── x86_64bit_v3.lang │ │ │ ├── x86_64bit_v3.trans │ │ │ ├── x86_ProtV2.lang │ │ │ ├── x86_ProtV2.trans │ │ │ ├── x86_ProtV3.lang │ │ │ ├── x86_ProtV3.trans │ │ │ ├── x86smmV1.lang │ │ │ ├── x86smmV1.trans │ │ │ ├── x86smmV2.lang │ │ │ ├── x86smmV2.trans │ │ │ ├── x86smmV3.lang │ │ │ └── x86smmV3.trans │ │ ├── pclmulqdq.sinc │ │ ├── rdrand.sinc │ │ ├── sgx.sinc │ │ ├── sha.sinc │ │ ├── smx.sinc │ │ ├── x86-16-real.pspec │ │ ├── x86-16.cspec │ │ ├── x86-16.gdis │ │ ├── x86-16.pspec │ │ ├── x86-32-golang.cspec │ │ ├── x86-32-golang.register.info │ │ ├── x86-64-compat32.pspec │ │ ├── x86-64-gcc.cspec │ │ ├── x86-64-golang.cspec │ │ ├── x86-64-golang.register.info │ │ ├── x86-64-swift.cspec │ │ ├── x86-64-win.cspec │ │ ├── x86-64.dwarf │ │ ├── x86-64.pspec │ │ ├── x86-64.slaspec │ │ ├── x86.dwarf │ │ ├── x86.ldefs │ │ ├── x86.opinion │ │ ├── x86.pspec │ │ ├── x86.slaspec │ │ ├── x86borland.cspec │ │ ├── x86delphi.cspec │ │ ├── x86gcc.cspec │ │ └── x86win.cspec │ │ ├── manuals │ │ └── x86.idx │ │ └── patterns │ │ ├── patternconstraints.xml │ │ ├── prepatternconstraints.xml │ │ ├── x86-16_default_patterns.xml │ │ ├── x86-64gcc_patterns.xml │ │ ├── x86-64win_patterns.xml │ │ ├── x86delphi_patterns.xml │ │ ├── x86gcc_patterns.xml │ │ ├── x86win_patterns.xml │ │ └── x86win_prepatterns.xml ├── py.typed ├── pypcode_native.cpp ├── pypcode_native.pyi ├── sleigh │ ├── Makefile │ ├── address.cc │ ├── address.hh │ ├── compression.cc │ ├── compression.hh │ ├── context.cc │ ├── context.hh │ ├── emulate.cc │ ├── emulate.hh │ ├── error.hh │ ├── filemanage.cc │ ├── filemanage.hh │ ├── float.cc │ ├── float.hh │ ├── globalcontext.cc │ ├── globalcontext.hh │ ├── loadimage.cc │ ├── loadimage.hh │ ├── loadimage_bfd.cc │ ├── loadimage_bfd.hh │ ├── marshal.cc │ ├── marshal.hh │ ├── memstate.cc │ ├── memstate.hh │ ├── opbehavior.cc │ ├── opbehavior.hh │ ├── opcodes.cc │ ├── opcodes.hh │ ├── partmap.hh │ ├── pcodecompile.cc │ ├── pcodecompile.hh │ ├── pcodeparse.cc │ ├── pcodeparse.hh │ ├── pcodeparse.y │ ├── pcoderaw.cc │ ├── pcoderaw.hh │ ├── semantics.cc │ ├── semantics.hh │ ├── slaformat.cc │ ├── slaformat.hh │ ├── sleigh.cc │ ├── sleigh.hh │ ├── sleighbase.cc │ ├── sleighbase.hh │ ├── slgh_compile.cc │ ├── slgh_compile.hh │ ├── slghparse.cc │ ├── slghparse.hh │ ├── slghparse.y │ ├── slghpatexpress.cc │ ├── slghpatexpress.hh │ ├── slghpattern.cc │ ├── slghpattern.hh │ ├── slghscan.cc │ ├── slghscan.l │ ├── slghsymbol.cc │ ├── slghsymbol.hh │ ├── space.cc │ ├── space.hh │ ├── translate.cc │ ├── translate.hh │ ├── types.h │ ├── xml.cc │ ├── xml.hh │ └── xml.y └── zlib │ ├── README.txt │ ├── adler32.c │ ├── deflate.c │ ├── deflate.h │ ├── gzguts.h │ ├── inffast.c │ ├── inffast.h │ ├── inffixed.h │ ├── inflate.c │ ├── inflate.h │ ├── inftrees.c │ ├── inftrees.h │ ├── trees.c │ ├── trees.h │ ├── zconf.h │ ├── zlib.h │ ├── zutil.c │ └── zutil.h ├── pyproject.toml ├── scripts ├── benchmark.py └── sleigh_download.sh ├── setup.py └── tests ├── test.py └── test_cli.py /.github/ISSUE_TEMPLATE/config.yml: -------------------------------------------------------------------------------- 1 | blank_issues_enabled: false 2 | contact_links: 3 | - name: Join our Slack community 4 | url: https://angr.io/invite/ 5 | about: For questions and help with angr, you are invited to join the angr Slack community 6 | -------------------------------------------------------------------------------- /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | updates: 3 | - package-ecosystem: "github-actions" 4 | directory: "/" 5 | schedule: 6 | interval: "weekly" 7 | commit-message: 8 | prefix: "ci" 9 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.egg-info/ 2 | __pycache__/ 3 | build/ 4 | dist/ 5 | pypcode/bin/ 6 | docs/_build/ 7 | *.so 8 | *.sla 9 | *.manifest 10 | *.gradle 11 | *.java 12 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | # Read the Docs configuration file 2 | # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details 3 | 4 | version: 2 5 | build: 6 | os: ubuntu-22.04 7 | tools: 8 | python: "3.10" 9 | 10 | python: 11 | install: 12 | - method: pip 13 | path: . 14 | extra_requirements: 15 | - docs 16 | 17 | sphinx: 18 | configuration: docs/conf.py 19 | -------------------------------------------------------------------------------- /MANIFEST.in: -------------------------------------------------------------------------------- 1 | graft pypcode 2 | prune pypcode/bin 3 | include CMakeLists.txt 4 | include LICENSE.txt 5 | graft tests 6 | global-exclude *.so 7 | global-exclude *.gitignore 8 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | pypcode 2 | ======= 3 | [![pypi](https://img.shields.io/pypi/v/pypcode)](https://pypi.org/project/pypcode/) 4 | 5 | Machine code disassembly and IR translation library for Python using the 6 | excellent SLEIGH library from the [Ghidra](https://ghidra-sre.org/) framework. 7 | 8 | This library was created primarily for use with [angr](http://angr.io), which 9 | provides analyses and symbolic execution of p-code. 10 | 11 | Documentation covering how to install and use pypcode is 12 | [available here](https://api.angr.io/projects/pypcode/en/latest/). 13 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = . 9 | BUILDDIR = _build 10 | 11 | # Put it first so that "make" without argument is like "make help". 12 | help: 13 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 14 | 15 | .PHONY: help Makefile 16 | 17 | # Catch-all target: route all unknown targets to Sphinx using the new 18 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 19 | %: Makefile 20 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 21 | -------------------------------------------------------------------------------- /docs/api.rst: -------------------------------------------------------------------------------- 1 | :mod:`pypcode` 2 | ========================================= 3 | 4 | .. automodule:: pypcode 5 | -------------------------------------------------------------------------------- /docs/index.rst: -------------------------------------------------------------------------------- 1 | pypcode documentation 2 | ===================== 3 | pypcode is a machine code disassembly and IR translation library for Python using the 4 | excellent `SLEIGH `__ library from the `Ghidra `__ framework (version 11.3.2). 5 | 6 | This library was created primarily for use with `angr `__, which provides analyses and symbolic 7 | execution of p-code. 8 | 9 | Table of Contents 10 | ----------------- 11 | 12 | .. toctree:: 13 | :maxdepth: 2 14 | 15 | Guide 16 | Architecture Support 17 | API Reference 18 | 19 | Indices and Tables 20 | ------------------ 21 | 22 | * :ref:`genindex` 23 | * :ref:`modindex` 24 | * :ref:`search` 25 | -------------------------------------------------------------------------------- /docs/languages.rst: -------------------------------------------------------------------------------- 1 | Architecture Support 2 | ==================== 3 | 4 | .. ipython:: 5 | 6 | In [0]: for arch in pypcode.Arch.enumerate(): 7 | ...: for lang in arch.languages: 8 | ...: print(f'{lang.id:32} - {lang.description}') 9 | -------------------------------------------------------------------------------- /docs/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=. 11 | set BUILDDIR=_build 12 | 13 | %SPHINXBUILD% >NUL 2>NUL 14 | if errorlevel 9009 ( 15 | echo. 16 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 17 | echo.installed, then set the SPHINXBUILD environment variable to point 18 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 19 | echo.may add the Sphinx directory to PATH. 20 | echo. 21 | echo.If you don't have Sphinx installed, grab it from 22 | echo.https://www.sphinx-doc.org/ 23 | exit /b 1 24 | ) 25 | 26 | if "%1" == "" goto help 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /pypcode/__version__.py: -------------------------------------------------------------------------------- 1 | __version__ = "3.2.2.dev0" 2 | -------------------------------------------------------------------------------- /pypcode/processors/6502/data/languages/6502.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /pypcode/processors/6502/data/languages/6502.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 14 | 6502 Microcontroller Family 15 | 16 | 17 | 18 | 19 | 28 | 65C02 Microcontroller Family 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /pypcode/processors/6502/data/languages/6502.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/6502/data/manuals/6502.idx: -------------------------------------------------------------------------------- 1 | @mcs6500_family_programming_manual.pdf [MCS 6500 Microcomputer Family Programming Manual, January 1976] 2 | ADC, 205 3 | AND, 205 4 | ASL, 206 5 | BCC, 206 6 | BCS, 207 7 | BEQ, 207 8 | BIT, 208 9 | BMI, 208 10 | BNE, 209 11 | BPL, 209 12 | BRK, 210 13 | BVC, 210 14 | BVS, 211 15 | CLC, 211 16 | CLD, 212 17 | CLI, 212 18 | CLV, 213 19 | CMP, 213 20 | CPX, 214 21 | CPY, 214 22 | DEC, 215 23 | DEX, 215 24 | DEY, 216 25 | EOR, 216 26 | INC, 217 27 | INX, 217 28 | INY, 218 29 | JMP, 218 30 | JSR, 219 31 | LDA, 219 32 | LDX, 220 33 | LDY, 220 34 | LSR, 221 35 | NOP, 221 36 | ORA, 222 37 | PHA, 222 38 | PHP, 223 39 | PLA, 223 40 | PLP, 224 41 | ROL, 224 42 | ROR, 225 43 | RTI, 225 44 | RTS, 225 45 | SBC, 226 46 | SEC, 226 47 | SED, 227 48 | SEI, 227 49 | STA, 228 50 | STX, 228 51 | STY, 229 52 | TAX, 229 53 | TAY, 230 54 | TSX, 231 55 | TXA, 231 56 | TXS, 231 57 | TYA, 230 58 | -------------------------------------------------------------------------------- /pypcode/processors/6502/data/manuals/65c02.idx: -------------------------------------------------------------------------------- 1 | @wdc_65816_programming_manual.pdf [Programming the 65816 - Including the 6502, 65C02 and 65802, 2007] 2 | ADC, 327 3 | AND, 328 4 | ASL, 329 5 | BBR, 457 6 | BBS, 458 7 | BCC, 330 8 | BCS, 331 9 | BEQ, 332 10 | BIT, 333 11 | BMI, 334 12 | BNE, 335 13 | BPL, 336 14 | BRA, 337 15 | BRK, 338 16 | BVC, 341 17 | BVS, 342 18 | CLC, 343 19 | CLD, 344 20 | CLI, 345 21 | CLV, 346 22 | CMP, 347 23 | CPX, 350 24 | CPY, 351 25 | DEC, 352 26 | DEX, 353 27 | DEY, 354 28 | EOR, 355 29 | INC, 357 30 | INX, 358 31 | INY, 359 32 | JMP, 360 33 | JSR, 362 34 | LDA, 363 35 | LDX, 364 36 | LDY, 365 37 | LSR, 366 38 | NOP, 369 39 | ORA, 370 40 | PHA, 375 41 | PHP, 379 42 | PHX, 380 43 | PHY, 381 44 | PLA, 382 45 | PLP, 385 46 | PLX, 386 47 | PLY, 387 48 | RMB, 459 49 | ROL, 389 50 | ROR, 390 51 | RTI, 391 52 | RTS, 393 53 | SBC, 395 54 | SEC, 397 55 | SED, 398 56 | SEI, 399 57 | SMB, 460 58 | STA, 401 59 | STX, 403 60 | STY, 404 61 | STZ, 405 62 | TAX, 406 63 | TAY, 407 64 | TRB, 411 65 | TSB, 412 66 | TSX, 414 67 | TXA, 415 68 | TXS, 416 69 | TYA, 418 70 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/languages/68000.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/languages/68000.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/languages/68000.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/languages/68020.slaspec: -------------------------------------------------------------------------------- 1 | @include "68000.sinc" 2 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/languages/68030.slaspec: -------------------------------------------------------------------------------- 1 | @define MC68030 "" 2 | @include "68000.sinc" 3 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/languages/68040.slaspec: -------------------------------------------------------------------------------- 1 | @define MC68040 "" 2 | @include "68000.sinc" 3 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/languages/coldfire.slaspec: -------------------------------------------------------------------------------- 1 | # Motorola's Coldfire processor 2 | 3 | @define COLDFIRE "" 4 | @define MC68040 "" 5 | 6 | @include "68000.sinc" 7 | -------------------------------------------------------------------------------- /pypcode/processors/68000/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 68000_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/8048/data/languages/8048.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /pypcode/processors/8048/data/languages/8048.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 14 | 8048 Microcontroller Family 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /pypcode/processors/8048/data/manuals/8048.idx: -------------------------------------------------------------------------------- 1 | @8048.pdf [MCS-48 Microcomputer User's Manual, February 1978] 2 | ADD, 63 3 | ADDC, 63 4 | ANL, 64 5 | ANLD, 65 6 | CALL, 66 7 | CLR, 67 8 | CPL, 67 9 | DA, 68 10 | DEC, 68 11 | DIS, 69 12 | DJNZ, 69 13 | EN, 70 14 | ENT0, 70 15 | IN, 70 16 | INC, 71 17 | INS, 72 18 | JB, 72 19 | JC, 72 20 | JF0, 72 21 | JF1, 73 22 | JMP, 73 23 | JMPP, 73 24 | JNC, 73 25 | JNI, 74 26 | JNT0, 74 27 | JNT1, 74 28 | JNZ, 74 29 | JTF, 75 30 | JT0, 75 31 | JT1, 75 32 | JZ, 75 33 | MOV, 76 34 | MOVD, 79 35 | MOVP, 79 36 | MOVP3, 80 37 | MOVX, 80 38 | NOP, 81 39 | ORL, 81 40 | ORLD, 82 41 | OUTL, 82 42 | RET, 83 43 | RETR, 83 44 | RL, 83 45 | RLC, 84 46 | RR, 84 47 | RRC, 84 48 | SEL, 85 49 | STOP, 86 50 | STRT, 87 51 | SWAP, 87 52 | XCH, 88 53 | XCHD, 88 54 | XRL, 89 55 | -------------------------------------------------------------------------------- /pypcode/processors/8051/data/languages/80251.slaspec: -------------------------------------------------------------------------------- 1 | @define MCS251 "" 2 | 3 | @include "8051_main.sinc" 4 | 5 | @include "80251.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/8051/data/languages/80390.slaspec: -------------------------------------------------------------------------------- 1 | @define MCS80390 "" 2 | 3 | @include "8051_main.sinc" 4 | -------------------------------------------------------------------------------- /pypcode/processors/8051/data/languages/8051.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/8051/data/languages/8051.slaspec: -------------------------------------------------------------------------------- 1 | @define MCS51 "" 2 | 3 | @include "8051_main.sinc" 4 | -------------------------------------------------------------------------------- /pypcode/processors/8051/data/languages/mx51.slaspec: -------------------------------------------------------------------------------- 1 | @define MX51 "" 2 | @define OMIT_RETADDR 1 3 | @define DUAL_DPTR "" 4 | @define DPS_REG_NUM 0xa2 5 | 6 | @include "8051_main.sinc" 7 | @include "mx51.sinc" 8 | -------------------------------------------------------------------------------- /pypcode/processors/8051/data/languages/old/8051v1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | 8051:BE:16:default 4 | 8051:BE:16:default 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/8051/data/manuals/8051.idx: -------------------------------------------------------------------------------- 1 | @8xc251sx_um.pdf [8XC251SA, 8XC251SB,8XC251SP, 8XC251SQ Embedded Microcontroller User�s Manual, May 1996] 2 | ACALL, 278 3 | ADD, 279 4 | ADDC, 284 5 | AJMP, 286 6 | ANL, 286 7 | CJNE, 294 8 | CLR, 295 9 | CMP, 295 10 | CPL, 301 11 | DA, 303 12 | DEC, 304 13 | DIV, 307 14 | DJNZ, 309 15 | ECALL, 311 16 | EJMP, 312 17 | ERET, 313 18 | INC, 313 19 | JB, 317 20 | JBC, 318 21 | JC, 319 22 | JE, 320 23 | JG, 320 24 | JLE, 321 25 | JMP, 322 26 | JNB, 322 27 | JNC, 324 28 | JNE, 324 29 | JNZ, 325 30 | JSG, 326 31 | JSGE, 326 32 | JSL, 327 33 | JSLE, 328 34 | JZ, 328 35 | LCALL, 329 36 | LJMP, 330 37 | MOV, 331 38 | MOVC, 348 39 | MOVH, 349 40 | MOVS, 349 41 | MOVX, 350 42 | MOVZ, 352 43 | MUL, 353 44 | NOP, 355 45 | ORL, 355 46 | POP, 362 47 | PUSH, 364 48 | RET, 366 49 | RETI, 367 50 | RL, 368 51 | RLC, 368 52 | RR, 369 53 | RRC, 370 54 | SETB, 370 55 | SJMP, 371 56 | SLL, 372 57 | SRA, 373 58 | SRL, 374 59 | SUB, 374 60 | SUBB, 379 61 | SWAP, 381 62 | TRAP, 381 63 | XCH, 382 64 | XCHD, 383 65 | XRL, 384 66 | -------------------------------------------------------------------------------- /pypcode/processors/8085/data/languages/8085.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /pypcode/processors/8085/data/languages/8085.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | Intel 8085 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/aarch64-pltThunks.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | ...10000 0x.. 0x.. 1..10000 # adrp x16, PLTGOT + n * 8 10 | 0x11 ......10 01...... 0xf9 # ldr x17, [x16, PLTGOT + n * 8] 11 | 0x10 ......10 00...... 0x91 # add x16, x16, :lo12:PLTGOT + n * 8 12 | 0x20 0x02 0x1f 0xd6 # br x17 13 | 14 | 15 | 16 | 17 | ...10000 0x.. 0x.. 1..10000 # adrp x16, PLTGOT + n * 4 18 | 0x11 ......10 01...... 0xb9 # ldr x17, [x16, PLTGOT + n * 4] 19 | 0x10 ......10 00...... 0x11 # add x16, x16, :lo12:PLTGOT + n * 4 20 | 0x20 0x02 0x1f 0xd6 # br x17 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/languages/AARCH64.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/languages/AARCH64.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define DATA_ENDIAN "little" 3 | 4 | @include "AARCH64instructions.sinc" 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/languages/AARCH64BE.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define DATA_ENDIAN "big" 3 | 4 | @include "AARCH64instructions.sinc" 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define DATA_ENDIAN "little" 3 | 4 | @include "AARCH64instructions.sinc" 5 | @include "AARCH64_AMXext.sinc" 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/languages/AARCH64_golang.register.info: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/languages/AppleSilicon.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 12 | AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | AARCH64_LE_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/AARCH64/data/patterns/prepatternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | AARCH64_win_patterns.xml 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 18 | 19 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM4_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | 4 | @include "ARM.sinc" 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM4_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | 4 | @include "ARM.sinc" 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM4t_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | 5 | @include "ARM.sinc" 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM4t_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | 5 | @include "ARM.sinc" 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM5_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define VERSION_5 "" 4 | @define VERSION_5E "" 5 | 6 | @include "ARM.sinc" 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM5_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define VERSION_5 "" 4 | @define VERSION_5E "" 5 | 6 | @include "ARM.sinc" 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM5t_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | 7 | @include "ARM.sinc" 8 | 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM5t_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | 7 | @include "ARM.sinc" 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM6_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VFPv2 "" 10 | 11 | @include "ARM.sinc" 12 | 13 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM6_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VFPv2 "" 10 | 11 | @include "ARM.sinc" 12 | 13 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM7_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define SIMD "" 12 | @define VFPv3 "" 13 | @define VFPv4 "" 14 | 15 | @include "ARM.sinc" 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM7_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define SIMD "" 12 | @define VFPv3 "" 13 | @define VFPv4 "" 14 | 15 | @include "ARM.sinc" 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM8_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define VFPv3 "" 14 | @define VFPv4 "" 15 | 16 | @include "ARM.sinc" 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM8_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define VFPv3 "" 14 | @define VFPv4 "" 15 | 16 | @include "ARM.sinc" 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM8m_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define CDE "" 14 | @define CORTEX "" 15 | @define VFPv3 "" 16 | @define VFPv4 "" 17 | 18 | @include "ARM.sinc" 19 | @include "ARM_CDE.sinc" 20 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARM8m_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define CDE "" 14 | @define CORTEX "" 15 | @define VFPv3 "" 16 | @define VFPv4 "" 17 | 18 | @include "ARM.sinc" 19 | @include "ARM_CDE.sinc" 20 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/ARMneon.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/old/ARMv5.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Sleigh-ARMv5 4 | ARM:LE:32:v5 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/languages/old/THUMBv2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Sleigh-THUMBv2 4 | ARM:LE:32:v5t 5 | 6 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | ARM_LE_patterns.xml 4 | 5 | 6 | 7 | ARM_BE_patterns.xml 8 | 9 | 10 | 11 | ARM_LE_patterns.xml 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/ARM/data/patterns/prepatternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | ARM_switch_patterns.xml 4 | 5 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr32.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr32a.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Generic AVR32-A big-endian 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr32a.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr8.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr8.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 16-bit addressable code space 2 | 3 | @define PCBYTESIZE "2" 4 | @define HASEIND "0" 5 | 6 | @include "avr8.sinc" 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr8e.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 16-bit addressable code space and support for 2 | 3 | @define PCBYTESIZE "2" 4 | @define HASEIND "1" 5 | 6 | @include "avr8.sinc" 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr8eind.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 22-bit addressable code space 2 | 3 | @define PCBYTESIZE "3" 4 | @define HASEIND "1" 5 | 6 | @include "avr8.sinc" 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/languages/avr8xmega.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 22-bit addressable code space 2 | 3 | @define PCBYTESIZE "3" 4 | @define HASEIND "1" 5 | 6 | @define IO_START "0" 7 | @define REGISTER_SPACE "register" 8 | @define EIND "0x3c" 9 | 10 | @include "avr8.sinc" 11 | 12 | -------------------------------------------------------------------------------- /pypcode/processors/Atmel/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | AVR8_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/BPF/data/languages/BPF.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | BPF processor 32-bit little-endian 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/BPF/data/languages/BPF.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/BPF/data/languages/BPF_le.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @include "BPF.sinc" -------------------------------------------------------------------------------- /pypcode/processors/CP1600/data/languages/CP1600.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | General Instruments CP1600 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/CP1600/data/languages/CP1600.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /pypcode/processors/CP1600/data/languages/CP1600.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/CR16/data/languages/CR16.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 18 | 27 | National Semiconductor's CompactRISC CR16C little endian 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /pypcode/processors/CR16/data/languages/CR16.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/CR16/data/languages/CR16.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/CR16/data/languages/CR16B.slaspec: -------------------------------------------------------------------------------- 1 | 2 | define endian=little; 3 | 4 | @include "CR16B.sinc" 5 | -------------------------------------------------------------------------------- /pypcode/processors/CR16/data/languages/CR16C.slaspec: -------------------------------------------------------------------------------- 1 | 2 | define endian=little; 3 | 4 | @include "CR16C.sinc" 5 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data-be-64.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | 3 | @define RAMSIZE "8" 4 | 5 | @include "data.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data-le-64.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | 3 | @define RAMSIZE "8" 4 | 5 | @include "data.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data-ptr16.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data-ptr32.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data-ptr64.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 13 | Raw Data File (Little Endian) 14 | 15 | 16 | 17 | 18 | 19 | 27 | Raw Data File (Big Endian) 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/DATA/data/languages/data.sinc: -------------------------------------------------------------------------------- 1 | define endian = $(ENDIAN); 2 | 3 | define alignment = 1; 4 | 5 | define space ram type=ram_space size=8 default; 6 | 7 | define space register type=register_space size=4; 8 | 9 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 10 | # AT LEAST ONE REGISTER, AND STACK POINTER ARE REQUIRED 11 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 12 | 13 | define register offset=0x0 size=8 [ sp r0 ]; 14 | 15 | # Define context bits 16 | define register offset=0x100 size=4 contextreg; 17 | 18 | define context contextreg 19 | test=(0,0) 20 | ; 21 | 22 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 23 | # AT LEAST ONE INSTRUCTION IS REQUIRED 24 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 25 | 26 | :nop is test=1 unimpl 27 | 28 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 29 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_Base.slaspec: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # Sleigh specification file for DALVIK VM (base set of instructions) 3 | #------------------------------------------------------------------------------------ 4 | 5 | @include "Dalvik_Base.sinc" -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Android10.slaspec: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # Sleigh specification file for DALVIK VM 3 | #------------------------------------------------------------------------------------ 4 | 5 | # Source: 6 | # https://android.googlesource.com/platform/art/+/refs/heads/android10-release/libdexfile/dex/dex_instruction_list.h 7 | 8 | @include "Dalvik_Base.sinc" 9 | 10 | @include "Dalvik_OpCode_3E_43_unused.sinc" 11 | 12 | @include "Dalvik_OpCode_73_return_void_no_barrier.sinc" 13 | 14 | @include "Dalvik_OpCode_79_unused.sinc" 15 | @include "Dalvik_OpCode_7A_unused.sinc" 16 | 17 | @include "Dalvik_OpCode_E3_EA_dex.sinc" 18 | 19 | @include "Dalvik_OpCode_EB_F2_iput_iget.sinc" 20 | 21 | @include "Dalvik_OpCode_F3_unused.sinc" 22 | @include "Dalvik_OpCode_F4_unused.sinc" 23 | @include "Dalvik_OpCode_F5_unused.sinc" 24 | @include "Dalvik_OpCode_F6_unused.sinc" 25 | @include "Dalvik_OpCode_F7_unused.sinc" 26 | @include "Dalvik_OpCode_F8_unused.sinc" 27 | @include "Dalvik_OpCode_F9_unused.sinc" 28 | 29 | @include "Dalvik_OpCode_FA_FD_dex.sinc" 30 | @include "Dalvik_OpCode_FE_FF_dex.sinc" 31 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Android11.slaspec: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # Sleigh specification file for DALVIK VM 3 | #------------------------------------------------------------------------------------ 4 | 5 | # Source: 6 | # https://android.googlesource.com/platform/art/+/refs/heads/android11-release/libdexfile/dex/dex_instruction_list.h 7 | 8 | @include "Dalvik_Base.sinc" 9 | 10 | @include "Dalvik_OpCode_3E_43_unused.sinc" 11 | 12 | @include "Dalvik_OpCode_73_return_void_no_barrier.sinc" 13 | 14 | @include "Dalvik_OpCode_79_unused.sinc" 15 | @include "Dalvik_OpCode_7A_unused.sinc" 16 | 17 | @include "Dalvik_OpCode_E3_EA_dex.sinc" 18 | 19 | @include "Dalvik_OpCode_EB_F2_iput_iget.sinc" 20 | 21 | @include "Dalvik_OpCode_F3_unused.sinc" 22 | @include "Dalvik_OpCode_F4_unused.sinc" 23 | @include "Dalvik_OpCode_F5_unused.sinc" 24 | @include "Dalvik_OpCode_F6_unused.sinc" 25 | @include "Dalvik_OpCode_F7_unused.sinc" 26 | @include "Dalvik_OpCode_F8_unused.sinc" 27 | @include "Dalvik_OpCode_F9_unused.sinc" 28 | 29 | @include "Dalvik_OpCode_FA_FD_dex.sinc" 30 | @include "Dalvik_OpCode_FE_FF_dex.sinc" -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Android12.slaspec: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # Sleigh specification file for DALVIK VM 3 | #------------------------------------------------------------------------------------ 4 | 5 | # Source: 6 | # https://android.googlesource.com/platform/art/+/refs/heads/android12-release/libdexfile/dex/dex_instruction_list.h 7 | # https://android.googlesource.com/platform/art/+/refs/heads/android13-release/libdexfile/dex/dex_instruction_list.h 8 | 9 | @include "Dalvik_Base.sinc" 10 | 11 | @include "Dalvik_OpCode_3E_43_unused.sinc" 12 | 13 | @include "Dalvik_OpCode_73_unused.sinc" 14 | 15 | @include "Dalvik_OpCode_79_unused.sinc" 16 | @include "Dalvik_OpCode_7A_unused.sinc" 17 | 18 | @include "Dalvik_OpCode_E3_EA_unused.sinc" 19 | 20 | @include "Dalvik_OpCode_EB_F2_unused.sinc" 21 | 22 | @include "Dalvik_OpCode_F3_unused.sinc" 23 | @include "Dalvik_OpCode_F4_unused.sinc" 24 | @include "Dalvik_OpCode_F5_unused.sinc" 25 | @include "Dalvik_OpCode_F6_unused.sinc" 26 | @include "Dalvik_OpCode_F7_unused.sinc" 27 | @include "Dalvik_OpCode_F8_unused.sinc" 28 | @include "Dalvik_OpCode_F9_unused.sinc" 29 | 30 | @include "Dalvik_OpCode_FA_FD_dex.sinc" 31 | @include "Dalvik_OpCode_FE_FF_dex.sinc" -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Oreo.slaspec: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # Sleigh specification file for DALVIK VM 3 | #------------------------------------------------------------------------------------ 4 | 5 | # Source: 6 | # https://android.googlesource.com/platform/art/+/oreo-release/runtime/dex_instruction_list.h 7 | 8 | @include "Dalvik_Base.sinc" 9 | 10 | @include "Dalvik_OpCode_3E_43_unused.sinc" 11 | 12 | @include "Dalvik_OpCode_73_return_void_no_barrier.sinc" 13 | 14 | @include "Dalvik_OpCode_79_unused.sinc" 15 | @include "Dalvik_OpCode_7A_unused.sinc" 16 | 17 | @include "Dalvik_OpCode_E3_EA_dex.sinc" 18 | 19 | @include "Dalvik_OpCode_EB_F2_iput_iget.sinc" 20 | 21 | @include "Dalvik_OpCode_F3_unused.sinc" 22 | @include "Dalvik_OpCode_F4_unused.sinc" 23 | @include "Dalvik_OpCode_F5_unused.sinc" 24 | @include "Dalvik_OpCode_F6_unused.sinc" 25 | @include "Dalvik_OpCode_F7_unused.sinc" 26 | @include "Dalvik_OpCode_F8_unused.sinc" 27 | @include "Dalvik_OpCode_F9_unused.sinc" 28 | 29 | @include "Dalvik_OpCode_FA_FD_dex.sinc" 30 | 31 | @include "Dalvik_OpCode_FE_unused.sinc" 32 | @include "Dalvik_OpCode_FF_unused.sinc" 33 | 34 | 35 | 36 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_DEX_Pie.slaspec: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # Sleigh specification file for DALVIK VM 3 | #------------------------------------------------------------------------------------ 4 | 5 | # Source: 6 | # https://android.googlesource.com/platform/art/+/refs/heads/pie-release/libdexfile/dex/dex_instruction_list.h 7 | 8 | @include "Dalvik_Base.sinc" 9 | 10 | @include "Dalvik_OpCode_3E_43_unused.sinc" 11 | 12 | @include "Dalvik_OpCode_73_return_void_no_barrier.sinc" 13 | 14 | @include "Dalvik_OpCode_79_unused.sinc" 15 | @include "Dalvik_OpCode_7A_unused.sinc" 16 | 17 | @include "Dalvik_OpCode_E3_EA_dex.sinc" 18 | 19 | @include "Dalvik_OpCode_EB_F2_iput_iget.sinc" 20 | 21 | @include "Dalvik_OpCode_F3_unused.sinc" 22 | @include "Dalvik_OpCode_F4_unused.sinc" 23 | @include "Dalvik_OpCode_F5_unused.sinc" 24 | @include "Dalvik_OpCode_F6_unused.sinc" 25 | @include "Dalvik_OpCode_F7_unused.sinc" 26 | @include "Dalvik_OpCode_F8_unused.sinc" 27 | @include "Dalvik_OpCode_F9_unused.sinc" 28 | 29 | @include "Dalvik_OpCode_FA_FD_dex.sinc" 30 | @include "Dalvik_OpCode_FE_FF_dex.sinc" 31 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_barrier.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # V(0x73, RETURN_VOID_BARRIER, "return-void-barrier", k10x, false, kNone, kReturn, kVerifyNone) \ 3 | 4 | :return_void_barrier is inst1=0x73 & inst1_padding 5 | { 6 | return [sp]; 7 | } 8 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_no_barrier.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # V(0x73, RETURN_VOID_NO_BARRIER, "return-void-no-barrier", k10x, false, kNone, kReturn, kVerifyNone) \ 3 | 4 | :return_void_no_barrier is inst1=0x73 & inst1_padding 5 | { 6 | return [sp]; 7 | } 8 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_73_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | 4 | :unused_73 is inst0=0x73 5 | { 6 | #no pCode 7 | } 8 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_79_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0x79, UNUSED_79, "unused-79", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_79 is inst0=0x79 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_7A_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0x7A, UNUSED_7A, "unused-7a", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_7a is inst0=0x7a 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F3_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF3, UNUSED_F3, "unused-f3", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f3 is inst0=0xf3 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F4_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF4, UNUSED_F4, "unused-f4", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f4 is inst0=0xf4 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F5_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF5, UNUSED_F5, "unused-f5", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f5 is inst0=0xf5 6 | { 7 | #no pCode 8 | } 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F6_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF6, UNUSED_F6, "unused-f6", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f6 is inst0=0xf6 6 | { 7 | #no pCode 8 | } 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F7_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF7, UNUSED_F7, "unused-f7", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f7 is inst0=0xf7 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F8_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF8, UNUSED_F8, "unused-f8", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f8 is inst0=0xf8 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_F9_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF9, UNUSED_F9, "unused-f9", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f9 is inst0=0xf9 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FA_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFA, UNUSED_FA, "unused-fa", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fa is inst0=0xfa 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FB_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFB, UNUSED_FB, "unused-fb", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fb is inst0=0xfb 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FC_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFC, UNUSED_FC, "unused-fc", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fc is inst0=0xfc 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FD_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFD, UNUSED_FD, "unused-fd", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fd is inst0=0xfd 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FE_FF_dex.sinc: -------------------------------------------------------------------------------- 1 | 2 | #------------------------------------------------------------------------------------ 3 | #------------------------------------------------------------------------------------ 4 | # V(0xFE, CONST_METHOD_HANDLE, "const-method-handle", k21c, kIndexMethodHandleRef, kContinue | kThrow, 0, kVerifyRegA | kVerifyRegBMethodHandle) \ 5 | 6 | :const_method_handle registerA8,B_BITS_0_15 is inst0=0xfe ; registerA8 ; B_BITS_0_15 7 | { 8 | #TODO pCode 9 | } 10 | 11 | #------------------------------------------------------------------------------------ 12 | #------------------------------------------------------------------------------------ 13 | # V(0xFF, CONST_METHOD_TYPE, "const-method-type", k21c, kIndexProtoRef, kContinue | kThrow, 0, kVerifyRegA | kVerifyRegBPrototype) 14 | 15 | :const_method_type registerA8,B_BITS_0_15 is inst0=0xff ; registerA8 ; B_BITS_0_15 16 | { 17 | #TODO pCode 18 | } 19 | 20 | #------------------------------------------------------------------------------------ 21 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FE_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFE, UNUSED_FE, "unused-fe", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fe is inst0=0xfe 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/Dalvik/data/languages/Dalvik_OpCode_FF_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFF, UNUSED_FF, "unused-ff", k10x, false, kUnknown, 0, kVerifyError) 4 | 5 | :unused_ff is inst0=0xff 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HC05.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HC05.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | HC05 (6805) Microcontroller Family 14 | 15 | 16 | 25 | HC05 (6805) Microcontroller Family - M68HC05TB 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HC05.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HC05 (6805, 68HC05) 2 | 3 | @define HC05 "1" 4 | 5 | @include "HCS_HC.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HC08.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | HC08 Microcontroller Family 14 | 15 | 16 | 25 | HC08 Microcontroller Family - MC68HC908QY4 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HC08.pspec: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HC08.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HC08 (68HC08) 2 | 3 | @define HC08 "1" 4 | 5 | @include "HCS_HC.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HCS08.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HCS08.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | HCS08 Microcontroller Family 14 | 15 | 16 | 25 | HCS08 Microcontroller Family - MC9S08GB60 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HCS08.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/HCS08/data/languages/HCS08.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HCS08 (68HCS08) 2 | 3 | @define HCS08 "1" 4 | 5 | @include "HCS_HC.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/HCS12/data/languages/HC12.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HC12 (68HC12) 2 | 3 | @define HC12 "1" 4 | 5 | @define SIZE "2" 6 | 7 | @define MAXFLASHPage "0xFF" 8 | 9 | @include "HCS_HC12.sinc" -------------------------------------------------------------------------------- /pypcode/processors/HCS12/data/languages/HCS12.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/HCS12/data/languages/HCS12.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HCS12 (68HCS12) 2 | 3 | @define HCS12 "1" 4 | 5 | @define SIZE "3" 6 | 7 | @define MAXFLASHPage "0xFF" 8 | 9 | @include "HCS_HC12.sinc" -------------------------------------------------------------------------------- /pypcode/processors/HCS12/data/languages/HCS12X.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HCS12 (68HCS12) 2 | 3 | @define HCS12 "1" 4 | @define HCS12X "1" 5 | @define SIZE "3" 6 | 7 | @define MAXFLASHPage "0xFF" 8 | 9 | @include "HCS_HC12.sinc" 10 | @include "XGATE.sinc" -------------------------------------------------------------------------------- /pypcode/processors/JVM/data/languages/JVM.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Generic JVM 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/JVM/data/languages/JVM.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/languages/loongarch.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 6 | 7 | 9 | 10 | 12 | 13 | 15 | 16 | 18 | 19 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/languages/loongarch32.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 10 | 11 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/languages/loongarch32_f32.slaspec: -------------------------------------------------------------------------------- 1 | @define REGSIZE 4 2 | @define FREGSIZE 4 3 | @define ADDRSIZE 4 4 | @include "loongarch_main.sinc" 5 | @include "loongarch32_instructions.sinc" 6 | @include "loongarch_float.sinc" 7 | @include "loongarch_double.sinc" 8 | 9 | 10 | @include "lasx.sinc" 11 | @include "lbt.sinc" 12 | @include "lsx.sinc" 13 | @include "lvz.sinc" 14 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/languages/loongarch32_f64.slaspec: -------------------------------------------------------------------------------- 1 | @define REGSIZE 4 2 | @define FREGSIZE 8 3 | @define ADDRSIZE 4 4 | @include "loongarch_main.sinc" 5 | @include "loongarch32_instructions.sinc" 6 | @include "loongarch_float.sinc" 7 | @include "loongarch_double.sinc" 8 | 9 | #@include "lasx.sinc" 10 | #@include "lbt.sinc" 11 | #@include "lsx.sinc" 12 | #@include "lvz.sinc" 13 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/languages/loongarch64.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 10 | 11 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/languages/loongarch64_f32.slaspec: -------------------------------------------------------------------------------- 1 | @define LA64 "" 2 | 3 | @define REGSIZE 8 4 | @define FREGSIZE 4 5 | @define ADDRSIZE 8 6 | @include "loongarch_main.sinc" 7 | @include "loongarch32_instructions.sinc" 8 | @include "loongarch64_instructions.sinc" 9 | @include "loongarch_float.sinc" 10 | @include "loongarch_double.sinc" 11 | 12 | 13 | @include "lasx.sinc" 14 | @include "lbt.sinc" 15 | @include "lsx.sinc" 16 | @include "lvz.sinc" 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/languages/loongarch64_f64.slaspec: -------------------------------------------------------------------------------- 1 | @define LA64 "" 2 | 3 | @define REGSIZE 8 4 | @define FREGSIZE 8 5 | @define ADDRSIZE 8 6 | @include "loongarch_main.sinc" 7 | @include "loongarch32_instructions.sinc" 8 | @include "loongarch64_instructions.sinc" 9 | @include "loongarch_float.sinc" 10 | @include "loongarch_double.sinc" 11 | 12 | @include "lasx.sinc" 13 | @include "lbt.sinc" 14 | @include "lsx.sinc" 15 | @include "lvz.sinc" 16 | -------------------------------------------------------------------------------- /pypcode/processors/Loongarch/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | loongarch_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/M16C/data/languages/M16C_60.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 16 | Renesas M16C/60 16-Bit MicroComputer 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/M16C/data/languages/M16C_80.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /pypcode/processors/M16C/data/languages/M16C_80.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 16 | Renesas M16C/80 16-Bit MicroComputer 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/M8C/data/languages/m8c.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | Cypress M8C Microcontroller Family 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/M8C/data/languages/m8c.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/MC6800/data/languages/6805.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /pypcode/processors/MC6800/data/languages/6805.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | 6805 Microcontroller Family 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/MC6800/data/languages/6809.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /pypcode/processors/MC6800/data/languages/6809.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/MC6800/data/languages/6809.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Motorola 6809 2 | 3 | @define M6809 "" 4 | 5 | @include "6x09.sinc" 6 | @include "6x09_push.sinc" 7 | @include "6x09_pull.sinc" 8 | @include "6x09_exg_tfr.sinc" 9 | -------------------------------------------------------------------------------- /pypcode/processors/MC6800/data/languages/H6309.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Hitachi 6309 2 | # Compatible with MC6809 with some extended instructions 3 | # and addressing modes 4 | 5 | @define H6309 "" 6 | 7 | @include "6x09.sinc" 8 | @include "6x09_push.sinc" 9 | @include "6x09_pull.sinc" 10 | @include "6x09_exg_tfr.sinc" 11 | -------------------------------------------------------------------------------- /pypcode/processors/MCS96/data/languages/MCS96.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /pypcode/processors/MCS96/data/languages/MCS96.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Intel MCS-96 Microcontroller Family 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/MCS96/data/languages/MCS96.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /pypcode/processors/MCS96/data/languages/MCS96.slaspec: -------------------------------------------------------------------------------- 1 | @define C196KB "1" 2 | @define C196KC "1" 3 | 4 | @include "MCS96.sinc" 5 | -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/languages/mips.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/languages/mips32R6be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 big endian 2 | 3 | @define ENDIAN "big" 4 | @define FREGSIZE "8" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_dsp.sinc" 12 | -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/languages/mips32R6le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 little endian 2 | 3 | @define ENDIAN "little" 4 | @define FREGSIZE "8" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_dsp.sinc" -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/languages/mips32be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 big endian 2 | 3 | @define ENDIAN "big" 4 | @define FREGSIZE "4" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_mt.sinc" 12 | @include "mips_dsp.sinc" 13 | -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/languages/mips32le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 little endian 2 | 3 | @define ENDIAN "little" 4 | @define FREGSIZE "4" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_mt.sinc" 12 | @include "mips_dsp.sinc" 13 | -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/languages/mips64be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS r5000 big endian 2 | 3 | @define ENDIAN "big" 4 | @define MIPS64 "" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips64Instructions.sinc" 12 | @include "mips_dsp.sinc" 13 | -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/languages/mips64le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS r5000 little endian 2 | 3 | @define ENDIAN "little" 4 | @define MIPS64 "" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips64Instructions.sinc" 12 | @include "mips_dsp.sinc" 13 | 14 | -------------------------------------------------------------------------------- /pypcode/processors/MIPS/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | MIPS_BE_patterns.xml 4 | 5 | 6 | MIPS_LE_patterns.xml 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/PA-RISC/data/languages/pa-risc.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Generic PA-RISC 32-bit big endian 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /pypcode/processors/PA-RISC/data/languages/pa-risc.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/PA-RISC/data/languages/pa-risc32.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/PA-RISC/data/languages/pa-risc32be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PA-RISC 32 bit big endian 2 | 3 | @define ENDIAN "big" 4 | @define BITS "32" 5 | 6 | @include "pa-risc.sinc" 7 | @include "pa-riscInstructions.sinc" 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/PA-RISC/data/patterns/pa-risc_patterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 0xe840c002 7 | 0xe840c000 0x........ 8 | 9 | 10 | 11 | 0x6bc23fd9 12 | 0x6bc23fd9 0x08030241 0x081e0243 13 | 0x........ 0x08030241 14 | 0x........ 0x........ 0x08030241 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/PA-RISC/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | pa-risc_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/PIC24.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/PIC24.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/PIC24E.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define PIC24E "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/PIC24F.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define PIC24F "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/PIC24H.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define PIC24H "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/PIC30.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/PIC33.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/dsPIC30F.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define dsPIC30F "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/dsPIC33C.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | define endian=little; # little endian only 4 | 5 | @define dsPIC33C "1" 6 | 7 | @include "PIC24.sinc" 8 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/dsPIC33E.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define dsPIC33E "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/dsPIC33F.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define dsPIC33F "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic12c5xx.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-12C5xx 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic12c5xx.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic12c5xx.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_12C5XX" 2 | 3 | @include "pic12.sinc" 4 | 5 | # 6 | # NOTES - 7 | # 1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and 8 | # slightly modified to specify a the correct Register File Map. 9 | # 10 | 11 | # Bank-0 File Registers 12 | define DATA offset=0x00 size=1 [ 13 | INDF TMR0 PCL.0 STATUS.0 FSR.0 OSCCAL GPIO 14 | ]; 15 | 16 | @include "pic12_instructions.sinc" 17 | 18 | # IO Tristate Register 19 | define register offset=0x0020 size=1 [ TRIS ]; 20 | 21 | # TRIS register 22 | trisREG: "6" is f5=0x6 { export TRIS; } 23 | 24 | :TRIS trisREG is op6=0x00 & d=0 & trisREG { 25 | # ---- 0000 0000 0fff 26 | # 0000 0000 0000 0110 -> TRIS 6 27 | trisREG = W; 28 | } 29 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic16.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-16(C,CR)XXX 14 | 15 | 16 | 17 | 26 | PIC-16F(L)XXX 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic16.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_16" 2 | 3 | @include "pic16.sinc" 4 | 5 | @include "pic16_instructions.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic16c5x.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic16c5x.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-16C5x 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic16c5x.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic16c5x.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_12C5XX" 2 | 3 | @include "pic12.sinc" 4 | 5 | # 6 | # NOTES - 7 | # 1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and 8 | # slightly modified to specify a the correct Register File Map. 9 | # 10 | 11 | # Bank-0 File Registers 12 | define DATA offset=0x00 size=1 [ 13 | INDF TMR0 PCL.0 STATUS.0 FSR.0 PORTA PORTB PORTC 14 | ]; 15 | 16 | @include "pic12_instructions.sinc" 17 | 18 | # IO Tristate Registers 19 | define register offset=0x0020 size=1 [ TRISA TRISB TRISC ]; 20 | 21 | # TRIS register 22 | trisREG: "5" is f5=0x5 { export TRISA; } 23 | trisREG: "6" is f5=0x6 { export TRISB; } 24 | trisREG: "7" is f5=0x7 { export TRISC; } 25 | 26 | :TRIS trisREG is op6=0x00 & d=0 & trisREG { 27 | # ---- 0000 0000 0fff 28 | # 0000 0000 0000 0110 -> TRIS 6 29 | trisREG = W; 30 | } 31 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic16f.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_16F" 2 | 3 | @include "pic16.sinc" 4 | 5 | @include "pic16_instructions.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic17c7xx.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-17C7xx 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/languages/pic18.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-18 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/manuals/PIC-12.idx: -------------------------------------------------------------------------------- 1 | @PIC12_40139e.pdf [PIC12C5XX 8-Pin, 8-Bit CMOS Microcontrollers (DS40139E)] 2 | ADDWF , 49 3 | ANDLW , 49 4 | ANDWF , 49 5 | BCF , 49 6 | BSF , 50 7 | BTFSC , 50 8 | BTFSS , 50 9 | CALL , 51 10 | CLRF , 51 11 | CLRW , 51 12 | CLRWDT , 51 13 | COMF , 52 14 | DECF , 52 15 | DECFSZ , 52 16 | GOTO , 52 17 | INCF , 53 18 | INCFSZ , 53 19 | IORLW , 53 20 | IORWF , 53 21 | MOVLW , 54 22 | MOVF , 54 23 | MOVWF , 54 24 | NOP , 54 25 | OPTION , 55 26 | RETLW , 55 27 | RLF , 55 28 | RRF , 55 29 | SLEEP , 56 30 | SUBWF , 56 31 | SWAPF , 57 32 | TRIS , 57 33 | XORLW , 57 34 | XORWF , 57 35 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/manuals/PIC-16.idx: -------------------------------------------------------------------------------- 1 | @PIC16_33023a.pdf [PICmicro� Mid-Range MCU Family Reference Manual, December 1997 (DS33023A)] 2 | ADDLW , 530 3 | ADDWF , 531 4 | ANDLW , 532 5 | ANDWF , 533 6 | BCF , 534 7 | BSF , 535 8 | BTFSC , 536 9 | BTFSS , 537 10 | CALL , 538 11 | CLRF , 539 12 | CLRW , 540 13 | CLRWDT , 541 14 | COMF , 542 15 | DECF , 543 16 | DECFSZ , 544 17 | GOTO , 545 18 | INCF , 546 19 | INCFSZ , 547 20 | IORLW , 548 21 | IORWF , 549 22 | MOVLW , 550 23 | MOVF , 551 24 | MOVWF , 552 25 | NOP , 553 26 | OPTION , 554 27 | RETFIE , 555 28 | RETLW , 556 29 | RETURN , 557 30 | RLF , 558 31 | RRF , 559 32 | SLEEP , 560 33 | SUBLW , 561 34 | SUBWF , 562 35 | SWAPF , 563 36 | TRIS , 564 37 | XORLW , 565 38 | XORWF , 566 39 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/manuals/PIC-16F.idx: -------------------------------------------------------------------------------- 1 | @PIC16F_40001761E.pdf [Microchip PIC16LF1554/1559 (DS40001761E)] 2 | ADDFSR , 273 3 | ADDLW , 273 4 | ADDWF , 273 5 | ADDWFC , 273 6 | ANDLW , 273 7 | ANDWF , 273 8 | ASRF , 273 9 | BCF , 274 10 | BRA , 274 11 | BRW , 274 12 | BSF , 274 13 | BTFSC , 274 14 | BTFSS , 274 15 | CALL , 275 16 | CALLW , 275 17 | CLRF , 275 18 | CLRW , 275 19 | CLRWDT , 275 20 | COMF , 275 21 | DECF , 275 22 | DECFSZ , 276 23 | GOTO , 276 24 | INCF , 276 25 | INCFSZ , 276 26 | IORLW , 276 27 | IORWF , 276 28 | LSLF , 277 29 | LSRF , 277 30 | MOVF , 277 31 | MOVIW , 278 32 | MOVLB , 278 33 | MOVLP , 278 34 | MOVLW , 278 35 | MOVWF , 278 36 | MOVWI , 279 37 | NOP , 279 38 | OPTION , 279 39 | RESET , 279 40 | RETFIE , 280 41 | RETLW , 280 42 | RETURN , 280 43 | RLF , 280 44 | RRF , 281 45 | SLEEP , 281 46 | SUBLW , 281 47 | SUBWF , 281 48 | SUBWFB , 281 49 | SWAPF , 282 50 | TRIS , 282 51 | XORLW , 282 52 | XORWF , 282 53 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/manuals/PIC-17.idx: -------------------------------------------------------------------------------- 1 | @PIC17_30289b.pdf [High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D, 2000 (DS30289B)] 2 | ADDLW , 202 3 | ADDWF , 202 4 | ADDWFC , 203 5 | ANDLW , 203 6 | ANDWF , 204 7 | BCF , 204 8 | BSF , 205 9 | BTFSC , 205 10 | BTFSS , 206 11 | BTG , 206 12 | CALL , 207 13 | CLRF , 207 14 | CLRWDT , 208 15 | COMF , 208 16 | CPFSEQ , 209 17 | CPFSGT , 209 18 | CPFSLT , 210 19 | DAW , 210 20 | DECF , 211 21 | DECFSZ , 211 22 | DCFSNZ , 212 23 | GOTO , 212 24 | INCF , 213 25 | INCFSZ , 213 26 | INFSNZ , 214 27 | IORLW , 214 28 | IORWF , 215 29 | LCALL , 215 30 | MOVFP , 216 31 | MOVLB , 216 32 | MOVLR , 217 33 | MOVLW , 217 34 | MOVPF , 218 35 | MOVWF , 218 36 | MULLW , 219 37 | MULWF , 219 38 | NEGW , 220 39 | NOP , 220 40 | RETFIE , 221 41 | RETLW , 221 42 | RETURN , 222 43 | RLCF , 222 44 | RLNCF , 223 45 | RRCF , 223 46 | RRNCF , 224 47 | SETF , 224 48 | SLEEP , 225 49 | SUBLW , 225 50 | SUBWF , 226 51 | SUBWFB , 226 52 | SWAPF , 227 53 | TABLRD , 227 54 | TABLWT , 228 55 | TLRD , 229 56 | TLWT , 230 57 | TSTFSZ , 230 58 | XORLW , 231 59 | XORWF , 231 60 | -------------------------------------------------------------------------------- /pypcode/processors/PIC/data/manuals/PIC-18.idx: -------------------------------------------------------------------------------- 1 | @PIC18_14702.pdf [PIC18CXX2 High-Performance Microcontrollers with 10-Bit A/D, 7/99 (DS39026B)] 2 | ADDLW , 197 3 | ADDWF , 197 4 | ADDWFC , 198 5 | ANDLW , 198 6 | ANDWF , 199 7 | BC , 199 8 | BCF , 200 9 | BN , 200 10 | BNC , 201 11 | BNN , 201 12 | BNOV , 202 13 | BNZ , 202 14 | BRA , 203 15 | BSF , 203 16 | BTFSC , 204 17 | BTFSS , 204 18 | BTG , 205 19 | BOV , 205 20 | BZ , 206 21 | CALL , 206 22 | CLRF , 207 23 | CLRWDT , 207 24 | COMF , 208 25 | CPFSEQ , 208 26 | CPFSGT , 209 27 | CPFSLT , 209 28 | DAW , 210 29 | DECF , 210 30 | DECFSZ , 211 31 | DCFSNZ , 211 32 | GOTO , 212 33 | INCF , 212 34 | INCFSZ , 213 35 | INFSNZ , 213 36 | IORLW , 214 37 | IORWF , 214 38 | LFSR , 215 39 | MOVF , 215 40 | MOVFF , 216 41 | MOVLB , 216 42 | MOVLW , 217 43 | MOVWF , 217 44 | MULLW , 218 45 | MULWF , 218 46 | NEGF , 219 47 | NOP , 219 48 | POP , 220 49 | PUSH , 220 50 | RCALL , 221 51 | RESET , 221 52 | RETFIE , 222 53 | RETLW , 222 54 | RETURN , 223 55 | RLCF , 223 56 | RLNCF , 224 57 | RRCF , 224 58 | RRNCF , 225 59 | SETF , 225 60 | SLEEP , 226 61 | SUBWFB , 226 62 | SUBLW , 227 63 | SUBWF , 228 64 | SUBWFB , 229 65 | SWAPF , 230 66 | TBLRD , 231 67 | TBLWT , 232 68 | TSTFSZ , 233 69 | XORLW , 233 70 | XORWF , 234 71 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/g2.sinc: -------------------------------------------------------------------------------- 1 | 2 | define pcodeop tlbli; 3 | define pcodeop tlbld; 4 | 5 | :tlbld B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=978 & BIT_0=0 6 | { 7 | tlbld(B); 8 | } 9 | 10 | :tlbli B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=1010 & BIT_0=0 11 | { 12 | tlbli(B); 13 | } 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/old/oldPPC.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Sleigh-PowerPC 32-bit 4 | PowerPC:BE:32:default 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_4xx_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "4xx.sinc" 13 | 14 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_4xx_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "4xx.sinc" 13 | 14 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 32-bit big endian 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "altivec.sinc" 13 | @include "g2.sinc" 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_e200.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC e200 series core 2 | # Note: e200 series use VLE, with exception of e200z7 which supports both VLE and non-VLE 3 | 4 | @define E200 5 | @define ENDIAN "big" 6 | @define REGISTER_SIZE "4" 7 | @define EATRUNC "ea" 8 | @define CTR_OFFSET "32" 9 | @define NoLegacyIntegerMultiplyAccumulate 10 | 11 | @include "ppc_common.sinc" 12 | @include "ppc_vle.sinc" 13 | @include "evx.sinc" 14 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_e500_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC e500 series core 2 | 3 | # NOTE: This language variant includes some registers and instructions not supported 4 | # by the actual processor (e.g., floating pointer registers and associated instructions). 5 | # The actual processor only supports a subset of the registers and instructions implemented. 6 | 7 | @define E500 8 | 9 | @define ENDIAN "big" 10 | 11 | # Although a 32-bit architecture, 64-bit general purpose registers are supported. 12 | # Language has been modeled using a 64-bit implementation with a 32-bit truncated 13 | # memory space (see ldefs). 14 | 15 | @define REGISTER_SIZE "8" 16 | @define BIT_64 "64" 17 | 18 | @define EATRUNC "ea" 19 | 20 | @define CTR_OFFSET "32" 21 | 22 | @define NoLegacyIntegerMultiplyAccumulate 23 | 24 | @include "ppc_common.sinc" 25 | @include "quicciii.sinc" 26 | @include "evx.sinc" 27 | @include "SPEF_SCR.sinc" 28 | @include "SPE_EFSD.sinc" 29 | @include "SPE_EFV.sinc" 30 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_e500_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC e500 series core 2 | 3 | # NOTE: This language variant includes some registers and instructions not supported 4 | # by the actual processor (e.g., floating pointer registers and associated instructions). 5 | # The actual processor only supports a subset of the registers and instructions implemented. 6 | 7 | @define E500 8 | 9 | @define ENDIAN "little" 10 | 11 | # Although a 32-bit architecture, 64-bit general purpose registers are supported. 12 | # Language has been modeled using a 64-bit implementation with a 32-bit truncated 13 | # memory space (see ldefs). 14 | 15 | @define REGISTER_SIZE "8" 16 | @define BIT_64 "64" 17 | 18 | @define EATRUNC "ea" 19 | 20 | @define CTR_OFFSET "32" 21 | 22 | @define NoLegacyIntegerMultiplyAccumulate 23 | 24 | @include "ppc_common.sinc" 25 | @include "quicciii.sinc" 26 | @include "evx.sinc" 27 | @include "SPEF_SCR.sinc" 28 | @include "SPE_EFSD.sinc" 29 | @include "SPE_EFV.sinc" 30 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC e500 series core 2 | 3 | # NOTE: This language variant includes some registers and instructions not supported 4 | # by the actual processor (e.g., floating pointer registers and associated instructions). 5 | # The actual processor only supports a subset of the registers and instructions implemented. 6 | 7 | @define ENDIAN "big" 8 | 9 | @define REGISTER_SIZE "4" 10 | 11 | @define EATRUNC "ea" 12 | 13 | # e500mc has 32 bit registers 14 | # 15 | @define CTR_OFFSET "32" 16 | 17 | @define NoLegacyIntegerMultiplyAccumulate 18 | 19 | @include "ppc_common.sinc" 20 | @include "quicciii.sinc" 21 | @include "evx.sinc" 22 | @include "SPEF_SCR.sinc" 23 | 24 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC e500 series core 2 | 3 | #@define E500 4 | 5 | @define ENDIAN "little" 6 | 7 | @define REGISTER_SIZE "4" 8 | 9 | @define EATRUNC "ea" 10 | 11 | # e500mc has 32 bit registers 12 | # 13 | @define CTR_OFFSET "32" 14 | 15 | @define NoLegacyIntegerMultiplyAccumulate 16 | 17 | @include "ppc_common.sinc" 18 | @include "quicciii.sinc" 19 | @include "evx.sinc" 20 | @include "SPEF_SCR.sinc" 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 32-bit little endian 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @include "ppc_common.sinc" 10 | @include "altivec.sinc" 11 | @include "g2.sinc" 12 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_quicciii_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "quicciii.sinc" 13 | @include "evx.sinc" 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_32_quicciii_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "quicciii.sinc" 13 | @include "evx.sinc" 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 64-bit big endian 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "8" 6 | @define BIT_64 "64" 7 | @define EATRUNC "ea:4" 8 | 9 | @include "ppc_common.sinc" 10 | @include "altivec.sinc" 11 | @include "g2.sinc" 12 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_isa_altivec_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) 2 | # ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. 3 | 4 | @define ENDIAN "big" 5 | 6 | @define IS_ISA "1" 7 | @define NoLegacyIntegerMultiplyAccumulate "1" 8 | 9 | @define REGISTER_SIZE "8" 10 | @define BIT_64 "64" 11 | 12 | @define EATRUNC "ea" 13 | 14 | @define CTR_OFFSET "32" 15 | 16 | @include "ppc_common.sinc" 17 | @include "ppc_isa.sinc" 18 | 19 | @include "ppc_a2.sinc" 20 | @include "quicciii.sinc" 21 | @include "FPRC.sinc" 22 | 23 | # A given processor can be compliant with the PowerISA spec by including EITHER 24 | # the embedded vector instructions (EVX) OR the AltiVec instructions 25 | # However, these instruction sets overlap in their bit patterns, so Sleigh cannot support 26 | # both at the same time. We have two language variants for PowerISA 27 | # that specify which of these two vector specs is supported. 28 | #@include "evx.sinc" 29 | #@include "SPEF_SCR.sinc" 30 | #@include "SPE_EFSD.sinc" 31 | #@include "SPE_EFV.sinc" 32 | ## OR 33 | @include "altivec.sinc" 34 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_isa_altivec_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) 2 | # ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. 3 | 4 | @define ENDIAN "little" 5 | 6 | @define IS_ISA "1" 7 | @define NoLegacyIntegerMultiplyAccumulate "1" 8 | 9 | @define REGISTER_SIZE "8" 10 | @define BIT_64 "64" 11 | 12 | @define EATRUNC "ea" 13 | 14 | @define CTR_OFFSET "32" 15 | 16 | @include "ppc_common.sinc" 17 | @include "ppc_isa.sinc" 18 | 19 | @include "ppc_a2.sinc" 20 | @include "quicciii.sinc" 21 | @include "FPRC.sinc" 22 | 23 | # A given processor can be compliant with the PowerISA spec by including EITHER 24 | # the embedded vector instructions (EVX) OR the AltiVec instructions 25 | # However, these instruction sets overlap in their bit patterns, so Sleigh cannot support 26 | # both at the same time. We have two language variants for PowerISA 27 | # that specify which of these two vector specs is supported. 28 | #@include "evx.sinc" 29 | #@include "SPEF_SCR.sinc" 30 | #@include "SPE_EFSD.sinc" 31 | #@include "SPE_EFV.sinc" 32 | # OR 33 | @include "altivec.sinc" 34 | 35 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_isa_altivec_vle_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) 2 | # ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. 3 | 4 | @define ENDIAN "big" 5 | 6 | @define IS_ISA "1" 7 | @define NoLegacyIntegerMultiplyAccumulate "1" 8 | 9 | @define REGISTER_SIZE "8" 10 | @define BIT_64 "64" 11 | 12 | @define EATRUNC "ea" 13 | 14 | @define CTR_OFFSET "32" 15 | 16 | @include "ppc_common.sinc" 17 | @include "ppc_isa.sinc" 18 | 19 | @include "ppc_a2.sinc" 20 | @include "quicciii.sinc" 21 | @include "FPRC.sinc" 22 | 23 | @include "ppc_vle.sinc" 24 | 25 | # A given processor can be compliant with the PowerISA spec by including EITHER 26 | # the embedded vector instructions (EVX) OR the AltiVec instructions 27 | # However, these instruction sets overlap in their bit patterns, so Sleigh cannot support 28 | # both at the same time. We have two language variants for PowerISA 29 | # that specify which of these two vector specs is supported. 30 | #@include "evx.sinc" 31 | #@include "SPEF_SCR.sinc" 32 | #@include "SPE_EFSD.sinc" 33 | #@include "SPE_EFV.sinc" 34 | ## OR 35 | @include "altivec.sinc" 36 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_isa_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) 2 | # ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. 3 | 4 | @define ENDIAN "big" 5 | 6 | @define IS_ISA "1" 7 | @define NoLegacyIntegerMultiplyAccumulate "1" 8 | 9 | @define REGISTER_SIZE "8" 10 | @define BIT_64 "64" 11 | 12 | @define EATRUNC "ea" 13 | 14 | @define CTR_OFFSET "32" 15 | 16 | @include "ppc_common.sinc" 17 | @include "ppc_isa.sinc" 18 | 19 | @include "quicciii.sinc" 20 | @include "FPRC.sinc" 21 | 22 | # A given processor can be compliant with the PowerISA spec by including EITHER 23 | # the embedded vector instructions (EVX) OR the AltiVec instructions 24 | # However, these instruction sets overlap in their bit patterns, so Sleigh cannot support 25 | # both at the same time. We have two language variants for PowerISA 26 | # that specify which of these two vector specs is supported. 27 | @include "evx.sinc" 28 | @include "SPEF_SCR.sinc" 29 | @include "SPE_EFSD.sinc" 30 | @include "SPE_EFV.sinc" 31 | # OR 32 | #@include "altivec.sinc" 33 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_isa_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) 2 | # ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. 3 | 4 | @define ENDIAN "little" 5 | 6 | @define IS_ISA "1" 7 | @define NoLegacyIntegerMultiplyAccumulate "1" 8 | 9 | @define REGISTER_SIZE "8" 10 | @define BIT_64 "64" 11 | 12 | @define EATRUNC "ea" 13 | 14 | @define CTR_OFFSET "32" 15 | 16 | @include "ppc_common.sinc" 17 | @include "ppc_isa.sinc" 18 | 19 | @include "quicciii.sinc" 20 | @include "FPRC.sinc" 21 | 22 | # A given processor can be compliant with the PowerISA spec by including EITHER 23 | # the embedded vector instructions (EVX) OR the AltiVec instructions 24 | # However, these instruction sets overlap in their bit patterns, so Sleigh cannot support 25 | # both at the same time. We have two language variants for PowerISA 26 | # that specify which of these two vector specs is supported. 27 | @include "evx.sinc" 28 | @include "SPEF_SCR.sinc" 29 | @include "SPE_EFSD.sinc" 30 | @include "SPE_EFV.sinc" 31 | # OR 32 | #@include "altivec.sinc" 33 | 34 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) 2 | # ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. 3 | 4 | @define ENDIAN "big" 5 | 6 | @define IS_ISA "1" 7 | @define NoLegacyIntegerMultiplyAccumulate "1" 8 | 9 | @define REGISTER_SIZE "8" 10 | @define BIT_64 "64" 11 | 12 | @define EATRUNC "ea" 13 | 14 | @define CTR_OFFSET "32" 15 | 16 | @include "ppc_common.sinc" 17 | @include "ppc_isa.sinc" 18 | 19 | @include "quicciii.sinc" 20 | @include "FPRC.sinc" 21 | 22 | @include "ppc_vle.sinc" 23 | 24 | # A given processor can be compliant with the PowerISA spec by including EITHER 25 | # the embedded vector instructions (EVX) OR the AltiVec instructions 26 | # However, these instruction sets overlap in their bit patterns, so Sleigh cannot support 27 | # both at the same time. We have two language variants for PowerISA 28 | # that specify which of these two vector specs is supported. 29 | @include "evx.sinc" 30 | @include "SPEF_SCR.sinc" 31 | @include "SPE_EFSD.sinc" 32 | @include "SPE_EFV.sinc" 33 | @include "SPE_FloatMulAdd.sinc" 34 | # OR 35 | #@include "altivec.sinc" 36 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/languages/ppc_64_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 64-bit little endian 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "8" 6 | @define BIT_64 "64" 7 | @define EATRUNC "ea:4" 8 | 9 | @include "ppc_common.sinc" 10 | @include "altivec.sinc" 11 | @include "g2.sinc" 12 | -------------------------------------------------------------------------------- /pypcode/processors/PowerPC/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | PPC_BE_patterns.xml 4 | 5 | 6 | PPC_LE_patterns.xml 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV32G.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV32GC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV32I.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV32IC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV32IMC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV64G.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV64GC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV64I.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/RV64IC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/riscv.ilp32d.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @define XLEN 4 4 | @define XLEN2 8 5 | @define FLEN 8 6 | 7 | @define MXLEN_1 31 8 | @define MXLEN_2 30 9 | 10 | @define ADDRSIZE "32" 11 | @define FPSIZE "64" 12 | 13 | @include "riscv.reg.sinc" 14 | @include "riscv.table.sinc" 15 | @include "riscv.instr.sinc" 16 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/riscv.lp64d.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @define XLEN 8 4 | @define XLEN2 16 5 | @define FLEN 8 6 | 7 | @define MXLEN_1 63 8 | @define MXLEN_2 62 9 | 10 | @define ADDRSIZE "64" 11 | @define FPSIZE "64" 12 | 13 | @include "riscv.reg.sinc" 14 | @include "riscv.table.sinc" 15 | @include "riscv.instr.sinc" 16 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/riscv.rv64f.sinc: -------------------------------------------------------------------------------- 1 | # RV64F Standard Extension (in addition to RV32F) 2 | 3 | # fcvt.l.s d,S,m c0200053 fff0007f SIMPLE (64, 0) 4 | :fcvt.l.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2 5 | { 6 | rdL = trunc(frs1S); 7 | } 8 | 9 | 10 | # fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0) 11 | :fcvt.lu.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3 12 | { 13 | #TODO unsigned 14 | rdL = trunc(frs1S); 15 | } 16 | 17 | 18 | # fcvt.s.l D,s,m d0200053 fff0007f SIMPLE (64, 0) 19 | :fcvt.s.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2 20 | { 21 | local tmp:4 = int2float(rs1L); 22 | fassignS(frd, tmp); 23 | } 24 | 25 | 26 | # fcvt.s.lu D,s,m d0300053 fff0007f SIMPLE (64, 0) 27 | :fcvt.s.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3 28 | { 29 | #ATTN unsigned can be an issue here 30 | local u64:$(XLEN2) = zext(rs1L); 31 | local tmp:4 = int2float(u64); 32 | fassignS(frd, tmp); 33 | } 34 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/riscv.rv64q.sinc: -------------------------------------------------------------------------------- 1 | # RV64Q Standard Extension (in addition to RV32Q) 2 | 3 | # fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0) 4 | :fcvt.l.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2 5 | { 6 | rd = trunc(frs1); 7 | } 8 | 9 | 10 | # fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0) 11 | :fcvt.lu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3 12 | { 13 | rd = trunc(frs1); 14 | } 15 | 16 | 17 | # fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0) 18 | :fcvt.q.l frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2 19 | { 20 | frd = int2float(rs1); 21 | } 22 | 23 | 24 | # fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0) 25 | :fcvt.q.lu frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3 26 | { 27 | frd = int2float(rs1); 28 | } 29 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/riscv.zi.sinc: -------------------------------------------------------------------------------- 1 | # RV32/RV64 Zifencei Standard Extension 2 | 3 | # fence.i 0000100f ffffffff SIMPLE (0, 0) 4 | :fence.i is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x1 & fm=0x0 & op0711=0x0 & op1527=0x0 5 | { 6 | fence.i(); 7 | } 8 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/riscv32.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/languages/riscv64.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/RISCV/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | riscv_gc_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/Sparc/data/languages/Sparc.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /pypcode/processors/Sparc/data/languages/Sparc.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /pypcode/processors/Sparc/data/languages/SparcV9.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /pypcode/processors/Sparc/data/languages/SparcV9_32.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define SIZE "4" 3 | 4 | @include "SparcV9.sinc" 5 | -------------------------------------------------------------------------------- /pypcode/processors/Sparc/data/languages/SparcV9_64.slaspec: -------------------------------------------------------------------------------- 1 | @define SIZE "8" 2 | 3 | @include "SparcV9.sinc" 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/Sparc/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | SPARC_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH/data/languages/sh-1.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define SH_VERSION "1" 3 | 4 | @include "superh.sinc" 5 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH/data/languages/sh-2.slaspec: -------------------------------------------------------------------------------- 1 | @define SH_VERSION "2" 2 | 3 | @include "superh.sinc" 4 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH/data/languages/sh-2a.slaspec: -------------------------------------------------------------------------------- 1 | @define SH_VERSION "2A" 2 | @define FPU "1" 3 | 4 | @include "superh.sinc" 5 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH/data/languages/superh.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/languages/SuperH4.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/languages/SuperH4.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/languages/SuperH4_be.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines SuperH version 4a, but should work against versions 1,2, and 3. 2 | # DSP Extensions are not yet added 3 | 4 | # Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf) 5 | 6 | @define ENDIAN "big" 7 | 8 | @include "SuperH4.sinc" 9 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/languages/SuperH4_le.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines SuperH version 4, but should work against versions 1,2, and 3. 2 | # There is a SuperH version 4A (which has 4 byte instruction length) which has instructions incompatable 3 | # with this. 4 | 5 | # Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf) 6 | 7 | @define ENDIAN "little" 8 | 9 | @include "SuperH4.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/languages/old/SuperH4-BE-16.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | SuperH4:BE:16:default 4 | SuperH4:BE:32:default 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/languages/old/SuperH4-LE-16.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | SuperH4:LE:16:default 4 | SuperH4:LE:32:default 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/patterns/SuperH4_patterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 0x0b 0x00 0x09 0x00 5 | 0x0b 0x00 0xf6 0x6. 6 | 0x0b 0x00 0x09 0x00 0x00 0x00 7 | 0x0b 0x00 0x.. 0x7f 8 | 9 | 10 | 10011101 11100011 10111... ........ 11 | 0x22 0x4f 12 | 0x22 0x4f 1....... 0x7f 13 | 1....... 0x7f 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /pypcode/processors/SuperH4/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | SuperH4_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/TI_MSP430/data/languages/TI_MSP430.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/TI_MSP430/data/languages/TI_MSP430.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define REG_SIZE "2" 3 | 4 | @include "TI430Common.sinc" 5 | -------------------------------------------------------------------------------- /pypcode/processors/TI_MSP430/data/languages/TI_MSP430X.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/TI_MSP430/data/languages/TI_MSP430X.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define REG_SIZE "4" 3 | 4 | @include "TI430Common.sinc" 5 | @include "TI430X.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/TI_MSP430/data/languages/ti_msp430.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/old/ToyV0BE64.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Toy:BE:64:default 4 | Toy:BE:64:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/old/ToyV0LE64.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Toy:LE:64:default 4 | Toy:LE:64:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/old/v01stuff/toy.ldefs_v01: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | Toy (test) processor 64-bit big-endian 13 | 14 | 15 | 23 | Toy (test) processor 64-bit little-endian 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/old/v01stuff/toy.sinc: -------------------------------------------------------------------------------- 1 | # Main slaspec must define endianness and alignment 2 | 3 | @ifndef WORDSIZE 4 | @define WORDSIZE "1" 5 | @endif 6 | 7 | define space ROM type=ram_space size=$(SIZE) wordsize=$(WORDSIZE) default; 8 | 9 | define space register type=register_space size=2; 10 | 11 | define register offset=0x1000 size=$(SIZE) [ 12 | a0 a1 a2 a3 a4 a5 a6 a7 13 | a8 a9 a10 a11 a12 sp lr pc 14 | ]; 15 | 16 | # STATUS REGISTER MAP: (LOW) 17 | # C - CARRY 18 | # Z - ZERO 19 | # N - NEGATIVE 20 | # V - OVERFLOW 21 | 22 | define register offset=0x1100 size=1 [ 23 | C Z N V 24 | ]; 25 | 26 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy64_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "8" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy64_be_harvard.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "8" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "data" 6 | 7 | @include "toy.sinc" 8 | 9 | define space data type=ram_space size=$(SIZE) wordsize=$(WORDSIZE); 10 | 11 | @include "toyInstructions.sinc" 12 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy64_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define SIZE "8" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "4" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_be_posStack.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "4" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define POS_STACK "true" # enables switch in instructions for push/pop to work in positive direction 6 | @define DATA_SPACE "ram" 7 | 8 | @include "toy.sinc" 9 | @include "toyInstructions.sinc" 10 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_builder_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "4" 3 | @define DATA_SPACE "ram" 4 | 5 | @include "toy_builder.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_builder_be_align2.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define DATA_SPACE "ram" 5 | 6 | @include "toy_builder.sinc" 7 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_builder_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define SIZE "4" 3 | @define DATA_SPACE "ram" 4 | 5 | @include "toy_builder.sinc" 6 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_builder_le_align2.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define DATA_SPACE "ram" 5 | 6 | @include "toy_builder.sinc" 7 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_harvard.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define SIZE "4" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_wsz_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define WORDSIZE "2" 5 | 6 | @define INSTR_PHASE "" # not used by basic toy language 7 | @define DATA_SPACE "ram" 8 | 9 | @include "toy.sinc" 10 | @include "toyInstructions.sinc" 11 | -------------------------------------------------------------------------------- /pypcode/processors/Toy/data/languages/toy_wsz_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define WORDSIZE "2" 5 | 6 | @define INSTR_PHASE "" # not used by basic toy language 7 | @define DATA_SPACE "ram" 8 | 9 | @include "toy.sinc" 10 | @include "toyInstructions.sinc" 11 | -------------------------------------------------------------------------------- /pypcode/processors/V850/data/languages/V850.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Renesas V850 family 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/V850/data/languages/V850.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/V850/data/languages/V850.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /pypcode/processors/V850/data/languages/V850.slaspec: -------------------------------------------------------------------------------- 1 | ##################################################### 2 | ##### ##### 3 | ##### V850E2M SLEIGH specification ##### 4 | ##### ##### 5 | ##################################################### 6 | 7 | define endian = little; 8 | define alignment = 2; 9 | 10 | # Size & default are required 11 | define space ram type=ram_space size=4 default; 12 | define space register type=register_space size=4; 13 | 14 | 15 | 16 | ##################################################### 17 | ##### Helpers ##### 18 | ##################################################### 19 | 20 | @include "./Helpers/Register.sinc" 21 | @include "./Helpers/Tokens.sinc" 22 | @include "./Helpers/Variables.sinc" 23 | @include "./Helpers/Conditions.sinc" 24 | @include "./Helpers/Macros.sinc" 25 | @include "./Helpers/Extras.sinc" 26 | 27 | 28 | 29 | ##################################################### 30 | ##### Instructions ##### 31 | ##################################################### 32 | 33 | @include "./Instructions/Arithmetic.sinc" 34 | @include "./Instructions/Float.sinc" 35 | @include "./Instructions/Load_Store.sinc" 36 | @include "./Instructions/Logic.sinc" 37 | @include "./Instructions/Special.sinc" 38 | -------------------------------------------------------------------------------- /pypcode/processors/V850/data/manuals/v850.idx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/angr/pypcode/307a998fe30719df2b67494ad3985cd8176bb49c/pypcode/processors/V850/data/manuals/v850.idx -------------------------------------------------------------------------------- /pypcode/processors/V850/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | V850_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/cust.sinc: -------------------------------------------------------------------------------- 1 | # Per the manual: 2 | # CUST0 and CUST1 opcode encodings shown in Table 7–193 are permanently reserved 3 | # for designer-defined opcodes. In the future, customers who use these spaces 4 | # exclusively for their own designer-defined opcodes will be able to add new 5 | # Tensilica-defined options without changing their opcodes or binary executables. 6 | 7 | define pcodeop cust0; 8 | 9 | :cust0 "{op2="^op2^", r="^ar^", s="^as^", t="^at^"}" is op0=0x0 & op1=0x6 & op2 & ar & as & at { 10 | cust0(); 11 | } 12 | 13 | define pcodeop cust1; 14 | 15 | :cust1 "{op2="^op2^", r="^ar^", s="^as^", t="^at^"}" is op0=0x0 & op1=0x7 & op2 & ar & as & at { 16 | cust1(); 17 | } -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/flix.sinc: -------------------------------------------------------------------------------- 1 | 2 | # FLIX (Flexible Length Instruction eXtension) is a Xtensa processor extension 3 | # that allows for variable-length, multi-op instructions with support from 4 4 | # 16 bytes. Customizable, if found they should be flagged. 5 | 6 | define pcodeop flix; 7 | :FLIX u_4_23 is op0=0xe & u_4_23 { 8 | flix(); 9 | } -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/xtensa.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/xtensa.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/xtensa.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/xtensa_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @include "xtensaArch.sinc" 3 | @include "xtensaMain.sinc" 4 | 5 | with : phase=1 { 6 | 7 | @include "xtensaInstructions.sinc" 8 | #@include "xtensa_depbits.sinc" #uncomment this to use depbits instruction, collides with floating point 9 | @include "cust.sinc" 10 | @include "flix.sinc" 11 | 12 | } -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/xtensa_depbits.sinc: -------------------------------------------------------------------------------- 1 | # Xtensa Deposit Bits instruction 2 | # This is broken out because it collides with the floating point instructions. It is not included by default 3 | 4 | # DEPBITS - Add (RRR), pg. 394. 5 | shiftimm: simm is u4_20_23 & u1_16 [ simm = u1_16 << 4 + u4_20_23; ] { export *[const]:4 simm; } 6 | :depbits as, at, shiftimm, u4_12_15 is u3_17_19=0x5 & u4_12_15 & as & at & op0 = 0 & shiftimm { 7 | mask:4 = (1 << u4_12_15) - 1; 8 | bits:4 = (as & mask) << shiftimm; 9 | mask = mask << shiftimm; 10 | at = (~mask & at) | bits; 11 | } 12 | -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/languages/xtensa_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @include "xtensaArch.sinc" 3 | @include "xtensaMain.sinc" 4 | 5 | with : phase=1 { 6 | 7 | @include "xtensaInstructions.sinc" 8 | #@include "xtensa_depbits.sinc" #uncomment this to use depbits instruction, collides with floating point 9 | @include "cust.sinc" 10 | @include "flix.sinc" 11 | 12 | } 13 | -------------------------------------------------------------------------------- /pypcode/processors/Xtensa/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | xtensa_patterns.xml 5 | 6 | 7 | -------------------------------------------------------------------------------- /pypcode/processors/Z80/data/languages/z180.slaspec: -------------------------------------------------------------------------------- 1 | @define Z180 "" 2 | 3 | @include "z80.slaspec" 4 | -------------------------------------------------------------------------------- /pypcode/processors/Z80/data/manuals/Z180.idx: -------------------------------------------------------------------------------- 1 | @um0050.pdf [Z8018x Family MPU User Manual (UM005003-0703)] 2 | ADD, 227 3 | ADC, 227 4 | AND, 228 5 | CP, 228 6 | CPL, 228 7 | DEC, 229 8 | INC, 229 9 | MLT, 229 10 | NEG, 229 11 | OR, 230 12 | SUB, 230 13 | SBC, 231 14 | TST, 231 15 | XOR, 231 16 | RL, 232 17 | RLC, 232 18 | RLD, 233 19 | RRA, 233 20 | RR, 234 21 | RRCA, 233 22 | RRC, 233 23 | RRD, 234 24 | SLA, 234 25 | SRA, 234 26 | SRL, 234 27 | SET, 235 28 | RES, 235 29 | BIT, 236 30 | LDA, 238 31 | LD, 238 32 | CPD, 241 33 | CPDR, 241 34 | CPI, 242 35 | CPIR, 242 36 | LDD, 242 37 | LDDR, 242 38 | LDI, 242 39 | LDIR, 242 40 | PUSH, 243 41 | POP, 243 42 | EX, 244 43 | CALL, 245 44 | DJNZ, 245 45 | JP, 245 46 | JR, 245 47 | RET, 246 48 | RETI, 246 49 | RETN, 246 50 | RST, 246 51 | IN, 247 52 | IN0, 247 53 | IND, 247 54 | INDR, 247 55 | INI, 247 56 | INIR, 248 57 | OUT, 248 58 | OUT0, 248 59 | OTDM, 248 60 | OTDMR, 248 61 | OTDR, 249 62 | OUTI, 249 63 | OTIR, 249 64 | TSTIO, 249 65 | OTIM, 249 66 | OTIMR, 250 67 | OUTD, 250 68 | DAA, 251 69 | CCF, 251 70 | SCF, 251 71 | DI, 251 72 | EI, 251 73 | HALT, 251 74 | IM0, 251 75 | IM1, 251 76 | IM2, 251 77 | NOP, 251 78 | SLP, 251 79 | 80 | 81 | -------------------------------------------------------------------------------- /pypcode/processors/Z80/data/manuals/Z80.idx: -------------------------------------------------------------------------------- 1 | @UM0080.pdf [Z80 FamilyCPU User Manual, Aug 2016 (UM008011-0816)] 2 | LD, 85 3 | PUSH, 129 4 | POP, 133 5 | EX, 138 6 | EXX, 140 7 | LDI, 144 8 | LDIR, 146 9 | LDD, 148 10 | LDDR, 150 11 | CPI, 152 12 | CPIR, 153 13 | CPD, 155 14 | CPDR, 156 15 | ADD, 159 16 | ADC, 165 17 | SUB, 167 18 | SBC, 169 19 | AND, 171 20 | OR, 173 21 | XOR, 175 22 | CP, 177 23 | INC, 179 24 | DEC, 184 25 | DAA, 187 26 | CPL, 189 27 | NEG, 190 28 | CCF, 192 29 | SCF, 193 30 | NOP, 194 31 | HALT, 195 32 | DI, 196 33 | EI, 197 34 | IM, 198 35 | RLCA, 219 36 | RLA, 221 37 | RRCA, 223 38 | RRA, 225 39 | RLC, 227 40 | RL, 235 41 | RRC, 238 42 | RR, 241 43 | SLA, 244 44 | SRA, 247 45 | SRL, 250 46 | RLD, 252 47 | RRD, 254 48 | BIT, 257 49 | SET, 265 50 | RES, 273 51 | JP, 276 52 | JR, 279 53 | DJNZ, 292 54 | CALL, 295 55 | RET, 299 56 | RETI, 302 57 | RETN, 304 58 | RST, 306 59 | IN, 309 60 | INI, 312 61 | INIR, 314 62 | IND, 316 63 | INDR, 318 64 | OUT, 320 65 | OUTI, 323 66 | OTIR, 325 67 | OUTD, 327 68 | OTDR, 329 69 | -------------------------------------------------------------------------------- /pypcode/processors/eBPF/data/languages/eBPF.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /pypcode/processors/eBPF/data/languages/eBPF.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | eBPF processor 64-bit little-endian 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /pypcode/processors/eBPF/data/languages/eBPF.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/eBPF/data/languages/eBPF_le.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @include "eBPF.sinc" 4 | -------------------------------------------------------------------------------- /pypcode/processors/tricore/data/languages/tricore.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/tricore/data/languages/tricore.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /pypcode/processors/tricore/data/languages/tricore.slaspec: -------------------------------------------------------------------------------- 1 | @define Tricore "" 2 | 3 | @define TRICORE_GENERIC "" 4 | #@define TRICORE_RIDER_D "" 5 | #@define TRICORE_RIDER_B "" 6 | 7 | @define TRICORE_V2 "" 8 | 9 | #@define TRICORE_VERBOSE "" 10 | 11 | define endian=little; 12 | 13 | @include "tricore.sinc" 14 | -------------------------------------------------------------------------------- /pypcode/processors/tricore/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tricore_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/extensions/rust/unix/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/extensions/rust/unix/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/extensions/rust/windows/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/extensions/rust/windows/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/adx.sinc: -------------------------------------------------------------------------------- 1 | :ADCX Reg32, rm32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... { 2 | tmp:5 = zext(Reg32) + zext(rm32) + zext(CF); 3 | tmpCF:1 = tmp(4); # just the carry byte 4 | CF = tmpCF != 0; 5 | Reg32 = tmp:4; 6 | build check_Reg32_dest; 7 | } 8 | 9 | @ifdef IA64 10 | :ADCX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 { 11 | tmp:9 = zext(Reg64) + zext(rm64) + zext(CF); 12 | tmpCF:1 = tmp(8); # just the carry byte 13 | CF = tmpCF != 0; 14 | Reg64 = tmp:8; 15 | } 16 | @endif 17 | 18 | :ADOX Reg32, rm32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... { 19 | tmp:5 = zext(Reg32) + zext(rm32) + zext(OF); 20 | tmpOF:1 = tmp(4); # just the carry byte 21 | OF = tmpOF != 0; 22 | Reg32 = tmp:4; 23 | build check_Reg32_dest; 24 | } 25 | 26 | @ifdef IA64 27 | :ADOX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 { 28 | tmp:9 = zext(Reg64) + zext(rm64) + zext(OF); 29 | tmpOF:1 = tmp(8); # just the carry byte 30 | OF = tmpOF != 0; 31 | Reg64 = tmp:8; 32 | } 33 | @endif 34 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/clwb.sinc: -------------------------------------------------------------------------------- 1 | define pcodeop clwb; 2 | :CLWB m8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=6 ... { 3 | clwb(m8); 4 | } 5 | 6 | @ifdef IA64 7 | define pcodeop clflushopt; 8 | :CLFLUSHOPT m8 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=7 ... { 9 | clflushopt(m8); 10 | } 11 | @endif 12 | 13 | # Note: PCOMMIT was deprecated prior to it ever being implemented in production processors. 14 | # I never found the encoding for it. Therefore, no constructor. 15 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/lzcnt.sinc: -------------------------------------------------------------------------------- 1 | macro lzcntflags(input, output) { 2 | ZF = (output == 0); 3 | CF = (input == 0); 4 | # OF, SF, PF, AF are undefined 5 | } 6 | 7 | #### 8 | #### LZCNT instructions 9 | #### 10 | 11 | 12 | :LZCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg16 ... & rm16 { 13 | 14 | Reg16 = lzcount(rm16); 15 | lzcntflags(rm16, Reg16); 16 | } 17 | 18 | :LZCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg32 ... & check_Reg32_dest ... & rm32 { 19 | 20 | Reg32 = lzcount(rm32); 21 | lzcntflags(rm32, Reg32); 22 | build check_Reg32_dest; 23 | } 24 | 25 | @ifdef IA64 26 | :LZCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBD; Reg64 ... & rm64 { 27 | 28 | Reg64 = lzcount(rm64); 29 | lzcntflags(rm64, Reg64); 30 | } 31 | @endif 32 | 33 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/macros.sinc: -------------------------------------------------------------------------------- 1 | macro conditionalAssign(dest, cond, trueVal, falseVal) { 2 | dest = zext(cond) * trueVal | zext(!cond) * falseVal; 3 | } -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86RealV1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Real Mode 4 | x86:LE:16:Real Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86RealV2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Real Mode 4 | x86:LE:16:Real Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86RealV3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Real Mode 4 | x86:LE:16:Real Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86V1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:default 4 | x86:LE:32:default 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86V2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:default 4 | x86:LE:32:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86V3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:default 4 | x86:LE:32:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86_64bit_compat32_v2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:compat32 4 | x86:LE:64:compat32 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86_64bit_compat32_v3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:compat32 4 | x86:LE:64:compat32 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86_64bit_v1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x64:LE:64:default 4 | x86:LE:64:default 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86_64bit_v2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:default 4 | x86:LE:64:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86_64bit_v3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:default 4 | x86:LE:64:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86_ProtV2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Protected Mode 4 | x86:LE:16:Protected Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86_ProtV3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Protected Mode 4 | x86:LE:16:Protected Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86smmV1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:System Management Mode 4 | x86:LE:32:System Management Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86smmV2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:System Management Mode 4 | x86:LE:32:System Management Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/old/x86smmV3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:System Management Mode 4 | x86:LE:32:System Management Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/x86-16-real.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/x86-16.gdis: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/x86-16.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/x86-32-golang.register.info: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/x86-64-golang.register.info: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/x86-64.slaspec: -------------------------------------------------------------------------------- 1 | @define IA64 "IA64" 2 | @include "x86.slaspec" 3 | with : lockprefx=0 { 4 | @include "sgx.sinc" 5 | @include "fma.sinc" 6 | } 7 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/languages/x86.slaspec: -------------------------------------------------------------------------------- 1 | @include "ia.sinc" 2 | @include "lockable.sinc" 3 | with : lockprefx=0 { 4 | @include "avx.sinc" 5 | @include "avx_manual.sinc" 6 | @include "avx2.sinc" 7 | @include "avx2_manual.sinc" 8 | @include "avx512.sinc" 9 | @include "avx512_manual.sinc" 10 | @include "adx.sinc" 11 | @include "clwb.sinc" 12 | @include "pclmulqdq.sinc" 13 | @include "mpx.sinc" 14 | @include "lzcnt.sinc" 15 | @include "bmi1.sinc" 16 | @include "bmi2.sinc" 17 | @include "sha.sinc" 18 | @include "smx.sinc" 19 | @include "cet.sinc" 20 | @include "rdrand.sinc" 21 | } 22 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | x86win_patterns.xml 5 | 6 | 7 | x86win_patterns.xml 8 | 9 | 10 | x86delphi_patterns.xml 11 | 12 | 13 | x86gcc_patterns.xml 14 | 15 | 16 | 17 | 18 | 19 | x86-64win_patterns.xml 20 | 21 | 22 | x86-64gcc_patterns.xml 23 | 24 | 25 | 26 | 27 | 28 | x86-16_default_patterns.xml 29 | 30 | 31 | 32 | 33 | 34 | x86-16_default_patterns.xml 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/patterns/prepatternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | x86win_prepatterns.xml 6 | 7 | 8 | x86win_prepatterns.xml 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/patterns/x86-16_default_patterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 0xc9c3 5 | 0xc9cb 6 | 0x4dcb 7 | 0.011... 1100.011 8 | 1100.010 .0.....0 0x00 9 | 1100.010 .0.....0 0x00 0x90 10 | 0xc390 11 | 0xcb90 12 | 0xc3 13 | 14 | 15 | 0x558bec 16 | 0x5589e5 17 | 0xc8 000....0 0x0000 18 | 0x8cd89045 19 | 0x8cd055 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /pypcode/processors/x86/data/patterns/x86win_prepatterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 0x8bff 6 | 0x55 7 | 0x8bec 8 | 0x83ec20 9 | 0x8b4508 10 | 0x56 11 | 0x57 12 | 0x6a08 13 | 0x59 14 | 0xbe........ 15 | 0x8d7de0 16 | 0xf3a5 17 | 0x8945f8 18 | 0x8b450c 19 | 0x5f 20 | 0x8945fc 21 | 0x5e 22 | 0x85c0 23 | 0x740c 24 | 0xf60008 25 | 0x7407 26 | 0xc745f4........ 27 | 0x8d45f4 28 | 0x50 29 | 0xff75f0 30 | 0xff75e4 31 | 0xff75e0 32 | 0xff15........ 33 | 0xc9 34 | 0xc20800 35 | 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /pypcode/py.typed: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/angr/pypcode/307a998fe30719df2b67494ad3985cd8176bb49c/pypcode/py.typed -------------------------------------------------------------------------------- /pypcode/zlib/README.txt: -------------------------------------------------------------------------------- 1 | The source files in this directory are copied from the zlib compression library, version 1.3.1 2 | available from https://www.zlib.net/ . 3 | 4 | The source files here are only a subset of the complete zlib library. The files have not been 5 | changed except for the addition of a comment at the top of each file, noting its association 6 | with the zlib license and the version number. 7 | 8 | Within Ghidra, the zlib license is available (in both the source repository and distributions) 9 | in licenses/zlib_License.txt. Additionally the license appears at the top of zlib.h in this 10 | directory. 11 | -------------------------------------------------------------------------------- /pypcode/zlib/inffast.h: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: zlib License 3 | * NOTE: from zlib 1.3.1 4 | */ 5 | /* inffast.h -- header to use inffast.c 6 | * Copyright (C) 1995-2003, 2010 Mark Adler 7 | * For conditions of distribution and use, see copyright notice in zlib.h 8 | */ 9 | 10 | /* WARNING: this file should *not* be used by applications. It is 11 | part of the implementation of the compression library and is 12 | subject to change. Applications should only use zlib.h. 13 | */ 14 | 15 | void ZLIB_INTERNAL inflate_fast(z_streamp strm, unsigned start); 16 | -------------------------------------------------------------------------------- /scripts/sleigh_download.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | set -x 4 | 5 | git clone --depth=1 -b Ghidra_11.3.2_build https://github.com/NationalSecurityAgency/ghidra.git ghidra_src 6 | 7 | # We just need Makefile and $(LIBSLA_SOURCE) defined inside Makefile. Do it this 8 | # way to make sure we stay up to date with the list of required files. 9 | SLEIGH_SRC_DIR=sleigh 10 | pushd ghidra_src/Ghidra/Features/Decompiler/src/decompile/cpp/ 11 | echo -e "$SLEIGH_SRC_DIR:\n\tmkdir -p $SLEIGH_SRC_DIR\n\tcp \$(LIBSLA_SOURCE) Makefile $SLEIGH_SRC_DIR" >> Makefile 12 | make $SLEIGH_SRC_DIR 13 | SLEIGH_SRC_DIR=${PWD}/${SLEIGH_SRC_DIR} 14 | popd 15 | 16 | mv $SLEIGH_SRC_DIR . 17 | mv ghidra_src/Ghidra/Processors processors 18 | -------------------------------------------------------------------------------- /tests/test_cli.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # pylint:disable=no-self-use 3 | 4 | import unittest 5 | import base64 6 | import subprocess 7 | import tempfile 8 | import sys 9 | import os 10 | 11 | 12 | class TestCli(unittest.TestCase): 13 | """ 14 | Test the pypcode module command line interface 15 | """ 16 | 17 | def test_cli_list(self): 18 | subprocess.run([sys.executable, "-m", "pypcode", "-l"], check=True) 19 | 20 | def test_cli_trans(self): 21 | with tempfile.NamedTemporaryFile(delete=False) as tf: 22 | tf.write(base64.b64decode("McA5xnYRSInBg+EfigwKMAwHSP/A6+vD")) 23 | tf.close() 24 | path = tf.name 25 | 26 | try: 27 | subprocess.run( 28 | [sys.executable, "-m", "pypcode", "x86:LE:64:default", path], 29 | check=True, 30 | ) 31 | finally: 32 | os.unlink(path) 33 | 34 | 35 | if __name__ == "__main__": 36 | unittest.main() 37 | --------------------------------------------------------------------------------