├── .gitignore ├── LICENSE.md ├── README.md ├── alu.v ├── cq.jpg ├── cq.v ├── lib.v ├── reg_alu.v ├── tb_cq.v └── tests.txt /.gitignore: -------------------------------------------------------------------------------- 1 | **/pdf 2 | out 3 | *.vcd 4 | 5 | # OS stuff 6 | Desktop.ini 7 | ehthumbs.db 8 | Thumbs.db 9 | $RECYCLE.BIN/ 10 | ._* 11 | .DS_Store 12 | .Spotlight-V100 13 | .Trashes 14 | .vscode/ 15 | 16 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | Copyright 2018 Aniket Kaulavkar 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 4 | 5 | The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 6 | 7 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Circular Queue – FIFO implementation in hardware 2 | 3 | ## Problem Description 4 | 5 | Implement a circular queue (FIFO) buffer in hardware using Icarus Verilog. A FIFO(First in First Out) buffer is an elastic storage usually used between two subsystems. As the name indicates the memory that is first written into the FIFO is the first to be read or processed. A FIFO has two control signals i.e. write and read. When write is enabled data is written into the buffer and when read is enabled data is "removed" from the buffer to make room for more data. 6 | 7 | ## Implementation Details 8 | 9 | A FIFO Buffer is a read/write memory array that automatically keep track of the order in which data enters the module and reads the data out in the same order. In hardware FIFO buffer is used for synchronization purposes. It is often implemented as a circular queue, and has two pointers: 10 | 1. Read Pointer/Read Address Register 11 | 2. Write Pointer/Write Address Register 12 | 13 | Read and write addresses are initially both at the first memory location. When the read address and write address are equal then the FIFO queue is _Empty_. When the write address is _one_ value behind the read address of the FIFO buffer then the FIFO queue is _Full_. 14 | 15 | ![Circuit Diagram](https://i.imgur.com/F966plD.jpg) 16 | 17 | ### Modules used 18 | 19 | #### Modules from lib.v file 20 | 21 | 1. **fa:** Used to increment read and write addresses. 22 | 23 | 2. **dfrl:** Used to store addresses in a register. 24 | 25 | 3. **and2:** Used to handle edge cases where queue is empty or full. 26 | 27 | 4. **xnor2:** Used to compare two numbers in isEqual module. 28 | 29 | 5. **and3:** Used in the isEqual module. 30 | 31 | #### User defined modules 32 | 33 | 1. **reg_file:** Used to store data values. Register file includes eight 16-bit registers. 34 | 35 | 2. **ThreeBitRegister:** Used to store read and write pointers. 36 | 37 | 3. **isEqual:** Module outputs a Boolean stating whether the two inputs are equal or not. 38 | 39 | 4. **inc:** Increments input by value one. 40 | 41 | ## Running 42 | To compile and build, run the following command: 43 | ``` 44 | iverilog lib.v cq.v reg_alu.v alu.v tb_cq.v -o out && vvp out 45 | ``` 46 | To view the output using gtkwave: 47 | ``` 48 | gtkwave tb_cq.vcd 49 | ``` 50 | -------------------------------------------------------------------------------- /alu.v: -------------------------------------------------------------------------------- 1 | 2 | module alu_slice (input wire [1:0] op, input wire i0, i1, cin, output wire o, cout); 3 | wire t_sumdiff, t_and, t_or, t_andor; 4 | addsub _i0 (op[0], i0, i1, cin, t_sumdiff, cout); 5 | and2 _i1 (i0, i1, t_and); 6 | or2 _i2 (i0, i1, t_or); 7 | mux2 _i3 (t_and, t_or, op[0], t_andor); 8 | mux2 _i4 (t_sumdiff, t_andor, op[1], o); 9 | endmodule 10 | 11 | module alu (input wire [1:0] op, input wire [15:0] i0, i1, 12 | output wire [15:0] o, output wire cout); 13 | wire [14:0] c; 14 | alu_slice _i0 (op, i0[0], i1[0], op[0] , o[0], c[0]); 15 | alu_slice _i1 (op, i0[1], i1[1], c[0], o[1], c[1]); 16 | alu_slice _i2 (op, i0[2], i1[2], c[1], o[2], c[2]); 17 | alu_slice _i3 (op, i0[3], i1[3], c[2], o[3], c[3]); 18 | alu_slice _i4 (op, i0[4], i1[4], c[3], o[4], c[4]); 19 | alu_slice _i5 (op, i0[5], i1[5], c[4], o[5], c[5]); 20 | alu_slice _i6 (op, i0[6], i1[6], c[5], o[6], c[6]); 21 | alu_slice _i7 (op, i0[7], i1[7], c[6], o[7], c[7]); 22 | alu_slice _i8 (op, i0[8], i1[8], c[7], o[8], c[8]); 23 | alu_slice _i9 (op, i0[9], i1[9], c[8], o[9], c[9]); 24 | alu_slice _i10 (op, i0[10], i1[10], c[9] , o[10], c[10]); 25 | alu_slice _i11 (op, i0[11], i1[11], c[10], o[11], c[11]); 26 | alu_slice _i12 (op, i0[12], i1[12], c[11], o[12], c[12]); 27 | alu_slice _i13 (op, i0[13], i1[13], c[12], o[13], c[13]); 28 | alu_slice _i14 (op, i0[14], i1[14], c[13], o[14], c[14]); 29 | alu_slice _i15 (op, i0[15], i1[15], c[14], o[15], cout); 30 | endmodule 31 | -------------------------------------------------------------------------------- /cq.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aniketnk/circular-queue-verilog/87e4d1e42bb4dbb860e62a8310326fa110bf7277/cq.jpg -------------------------------------------------------------------------------- /cq.v: -------------------------------------------------------------------------------- 1 | module isEqual(input wire[2:0] din_a,din_b , output wire o); 2 | wire [2:0] t; 3 | xnor2 x[2:0] (din_a, din_b, t); 4 | and3 an1(t[2], t[1], t[0], o); 5 | endmodule 6 | 7 | module inc(input wire[2:0] din, output wire[2:0] dout); 8 | wire t1, t2, t3; 9 | fa f1(din[0], 1'b1, 1'b0, dout[0], t1); 10 | fa f2(din[1], 1'b0, t1, dout[1], t2); 11 | fa f3(din[2], 1'b0, t2, dout[2], t3); 12 | endmodule 13 | 14 | module ThreeBitReg(input wire clk, reset, load, input wire[2:0] inp, output wire [2:0] outp); 15 | dfrl dfrl_0(clk, reset, load, inp[0], outp[0]); 16 | dfrl dfrl_1(clk, reset, load, inp[1], outp[1]); 17 | dfrl dfrl_2(clk, reset, load, inp[2], outp[2]); 18 | endmodule 19 | 20 | module cq(input wire clk, reset, wr, rd, input wire[15:0] din, output wire empty, full, output wire[15:0] dout); 21 | // Local variables 22 | wire [2:0] rd_addr, wr_addr; 23 | wire [2:0] rd_inc, wr_inc; 24 | wire [15:0] fakeDout; 25 | wire wr_load, rd_load; 26 | 27 | inc i2(wr_addr, wr_inc); 28 | inc i1(rd_addr, rd_inc); 29 | isEqual empty0(rd_addr, wr_addr, empty); 30 | isEqual full0(rd_addr, wr_inc, full); 31 | 32 | and2 rl(rd, !empty, rd_load); 33 | and2 wl(wr, !full, wr_load); 34 | 35 | ThreeBitReg read_addr (clk, reset, rd_load, rd_inc, rd_addr); 36 | ThreeBitReg write_addr (clk, reset, wr_load, wr_inc, wr_addr); 37 | 38 | reg_file rf1 (clk, reset, wr_load, rd_addr[2:0], 3'b000, wr_addr[2:0], din[15:0], dout[15:0], fakeDout[15:0]); 39 | endmodule 40 | 41 | `default_nettype wire -------------------------------------------------------------------------------- /lib.v: -------------------------------------------------------------------------------- 1 | module invert (input wire i, output wire o); 2 | assign o = !i; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (t, o); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (t, o); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (t, o); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | module mux2 (input wire i0, i1, j, output wire o); 72 | assign o = (j==0)?i0:i1; 73 | endmodule 74 | 75 | module mux4 (input wire [0:3] i, input wire j1, j0, output wire o); 76 | wire t0, t1; 77 | mux2 mux2_0 (i[0], i[1], j1, t0); 78 | mux2 mux2_1 (i[2], i[3], j1, t1); 79 | mux2 mux2_2 (t0, t1, j0, o); 80 | endmodule 81 | 82 | module mux8 (input wire [0:7] i, input wire j2, j1, j0, output wire o); 83 | wire t0, t1; 84 | mux4 mux4_0 (i[0:3], j2, j1, t0); 85 | mux4 mux4_1 (i[4:7], j2, j1, t1); 86 | mux2 mux2_0 (t0, t1, j0, o); 87 | endmodule 88 | 89 | module demux2 (input wire i, j, output wire o0, o1); 90 | assign o0 = (j==0)?i:1'b0; 91 | assign o1 = (j==1)?i:1'b0; 92 | endmodule 93 | 94 | module demux4 (input wire i, j1, j0, output wire [0:3] o); 95 | wire t0, t1; 96 | demux2 demux2_0 (i, j1, t0, t1); 97 | demux2 demux2_1 (t0, j0, o[0], o[1]); 98 | demux2 demux2_2 (t1, j0, o[2], o[3]); 99 | endmodule 100 | 101 | module demux8 (input wire i, j2, j1, j0, output wire [0:7] o); 102 | wire t0, t1; 103 | demux2 demux2_0 (i, j2, t0, t1); 104 | demux4 demux4_0 (t0, j1, j0, o[0:3]); 105 | demux4 demux4_1 (t1, j1, j0, o[4:7]); 106 | endmodule 107 | 108 | module df (input wire clk, in, output wire out); 109 | reg df_out; 110 | always@(posedge clk) df_out <= in; 111 | assign out = df_out; 112 | endmodule 113 | 114 | module dfr (input wire clk, reset, in, output wire out); 115 | wire reset_, df_in; 116 | invert invert_0 (reset, reset_); 117 | and2 and2_0 (in, reset_, df_in); 118 | df df_0 (clk, df_in, out); 119 | endmodule 120 | 121 | module dfrl (input wire clk, reset, load, in, output wire out); 122 | wire _in; 123 | mux2 mux2_0(out, in, load, _in); 124 | dfr dfr_1(clk, reset, _in, out); 125 | endmodule 126 | 127 | module dfs (input wire clk, set, in, output wire out); 128 | wire dfr_in,dfr_out; 129 | invert invert_0(in, dfr_in); 130 | invert invert_1(dfr_out, out); 131 | dfr dfr_2(clk, set, dfr_in, dfr_out); 132 | endmodule 133 | 134 | module dfsl (input wire clk, set, load, in, output wire out); 135 | wire _in; 136 | mux2 mux2_0(out, in, load, _in); 137 | dfs dfs_1(clk, set, _in, out); 138 | endmodule 139 | 140 | module fa (input wire i0, i1, cin, output wire sum, cout); 141 | wire t0, t1, t2; 142 | xor3 _i0 (i0, i1, cin, sum); 143 | and2 _i1 (i0, i1, t0); 144 | and2 _i2 (i1, cin, t1); 145 | and2 _i3 (cin, i0, t2); 146 | or3 _i4 (t0, t1, t2, cout); 147 | endmodule 148 | 149 | module addsub (input wire addsub, i0, i1, cin, output wire sumdiff, cout); 150 | wire t; 151 | fa _i0 (i0, t, cin, sumdiff, cout); 152 | xor2 _i1 (i1, addsub, t); 153 | endmodule 154 | -------------------------------------------------------------------------------- /reg_alu.v: -------------------------------------------------------------------------------- 1 | // Write code for modules you need here 2 | 3 | 4 | module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b); 5 | 6 | // Declare wires here 7 | wire [15:0] t0, t1, t2, t3, t4, t5, t6, t7, reg_op0, reg_op1, reg_op2, reg_op3, reg_op4, reg_op5, reg_op6, reg_op7; 8 | wire [0:7] wrload; 9 | 10 | // Instantiate modules here 11 | 12 | STBitDemux8 writer(wr_addr, d_in, t0, t1, t2, t3, t4, t5, t6, t7); 13 | 14 | demux8 load_demux(wr, wr_addr[2], wr_addr[1], wr_addr[0], wrload); 15 | 16 | STBitReg reg_0(clk, reset, wrload[0], d_in, reg_op0); 17 | STBitReg reg_1(clk, reset, wrload[1], d_in, reg_op1); 18 | STBitReg reg_2(clk, reset, wrload[2], d_in, reg_op2); 19 | STBitReg reg_3(clk, reset, wrload[3], d_in, reg_op3); 20 | STBitReg reg_4(clk, reset, wrload[4], d_in, reg_op4); 21 | STBitReg reg_5(clk, reset, wrload[5], d_in, reg_op5); 22 | STBitReg reg_6(clk, reset, wrload[6], d_in, reg_op6); 23 | STBitReg reg_7(clk, reset, wrload[7], d_in, reg_op7); 24 | 25 | STBitMux8 read_a(rd_addr_a, reg_op0, reg_op1, reg_op2, reg_op3, reg_op4, reg_op5, reg_op6, reg_op7, d_out_a); 26 | STBitMux8 read_b(rd_addr_b, reg_op0, reg_op1, reg_op2, reg_op3, reg_op4, reg_op5, reg_op6, reg_op7, d_out_b); 27 | 28 | endmodule 29 | 30 | 31 | module reg_alu (input wire clk, reset, sel, wr, input wire [1:0] op, input wire [2:0] rd_addr_a, 32 | rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b, output wire cout); 33 | 34 | // Declare wires here 35 | wire [15:0] alu_outp, reg_din; 36 | wire alu_cout; 37 | 38 | // Instantiate modules here 39 | reg_file reg_m(clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, reg_din, d_out_a, d_out_b); 40 | STBitMux2 din_mux(d_in, alu_outp, sel, reg_din); 41 | alu alu_m(op, d_out_a, d_out_b, alu_outp, alu_cout); 42 | dfr cout_dfr(clk, reset, alu_cout, cout); 43 | 44 | endmodule 45 | 46 | module STBitReg(input wire clk, rst, load, input wire[15:0] inp, output wire [15:0] outp); 47 | 48 | dfrl dfrl_0( clk, rst, load, inp[0], outp[0] ); 49 | dfrl dfrl_1( clk, rst, load, inp[1], outp[1] ); 50 | dfrl dfrl_2( clk, rst, load, inp[2], outp[2] ); 51 | dfrl dfrl_3( clk, rst, load, inp[3], outp[3] ); 52 | dfrl dfrl_4( clk, rst, load, inp[4], outp[4] ); 53 | dfrl dfrl_5( clk, rst, load, inp[5], outp[5] ); 54 | dfrl dfrl_6( clk, rst, load, inp[6], outp[6] ); 55 | dfrl dfrl_7( clk, rst, load, inp[7], outp[7] ); 56 | dfrl dfrl_8( clk, rst, load, inp[8], outp[8] ); 57 | dfrl dfrl_9( clk, rst, load, inp[9], outp[9] ); 58 | dfrl dfrl_10( clk, rst, load, inp[10], outp[10] ); 59 | dfrl dfrl_11( clk, rst, load, inp[11], outp[11] ); 60 | dfrl dfrl_12( clk, rst, load, inp[12], outp[12] ); 61 | dfrl dfrl_13( clk, rst, load, inp[13], outp[13] ); 62 | dfrl dfrl_14( clk, rst, load, inp[14], outp[14] ); 63 | dfrl dfrl_15( clk, rst, load, inp[15], outp[15] ); 64 | 65 | endmodule 66 | 67 | module STBitDemux8(input wire [2:0] s, input wire [15:0] inp, output [15:0] o0, o1, o2, o3, o4, o5, o6, o7); 68 | 69 | demux8 b_0( inp[0], s[2], s[1], s[0], { o0[0], o1[0], o2[0], o3[0], o4[0], o5[0], o6[0], o7[0] } ); 70 | demux8 b_1( inp[1], s[2], s[1], s[0], { o0[1], o1[1], o2[1], o3[1], o4[1], o5[1], o6[1], o7[1] } ); 71 | demux8 b_2( inp[2], s[2], s[1], s[0], { o0[2], o1[2], o2[2], o3[2], o4[2], o5[2], o6[2], o7[2] } ); 72 | demux8 b_3( inp[3], s[2], s[1], s[0], { o0[3], o1[3], o2[3], o3[3], o4[3], o5[3], o6[3], o7[3] } ); 73 | demux8 b_4( inp[4], s[2], s[1], s[0], { o0[4], o1[4], o2[4], o3[4], o4[4], o5[4], o6[4], o7[4] } ); 74 | demux8 b_5( inp[5], s[2], s[1], s[0], { o0[5], o1[5], o2[5], o3[5], o4[5], o5[5], o6[5], o7[5] } ); 75 | demux8 b_6( inp[6], s[2], s[1], s[0], { o0[6], o1[6], o2[6], o3[6], o4[6], o5[6], o6[6], o7[6] } ); 76 | demux8 b_7( inp[7], s[2], s[1], s[0], { o0[7], o1[7], o2[7], o3[7], o4[7], o5[7], o6[7], o7[7] } ); 77 | demux8 b_8( inp[8], s[2], s[1], s[0], { o0[8], o1[8], o2[8], o3[8], o4[8], o5[8], o6[8], o7[8] } ); 78 | demux8 b_9( inp[9], s[2], s[1], s[0], { o0[9], o1[9], o2[9], o3[9], o4[9], o5[9], o6[9], o7[9] } ); 79 | demux8 b_10( inp[10], s[2], s[1], s[0], { o0[10], o1[10], o2[10], o3[10], o4[10], o5[10], o6[10], o7[10] } ); 80 | demux8 b_11( inp[11], s[2], s[1], s[0], { o0[11], o1[11], o2[11], o3[11], o4[11], o5[11], o6[11], o7[11] } ); 81 | demux8 b_12( inp[12], s[2], s[1], s[0], { o0[12], o1[12], o2[12], o3[12], o4[12], o5[12], o6[12], o7[12] } ); 82 | demux8 b_13( inp[13], s[2], s[1], s[0], { o0[13], o1[13], o2[13], o3[13], o4[13], o5[13], o6[13], o7[13] } ); 83 | demux8 b_14( inp[14], s[2], s[1], s[0], { o0[14], o1[14], o2[14], o3[14], o4[14], o5[14], o6[14], o7[14] } ); 84 | demux8 b_15( inp[15], s[2], s[1], s[0], { o0[15], o1[15], o2[15], o3[15], o4[15], o5[15], o6[15], o7[15] } ); 85 | 86 | endmodule 87 | 88 | module STBitMux8(input wire [2:0] s, input wire [15:0] i0, i1, i2, i3, i4, i5, i6, i7, output wire [15:0] out); 89 | 90 | mux8 b_0( { i0[0], i1[0], i2[0], i3[0], i4[0], i5[0], i6[0], i7[0] }, s[0], s[1], s[2], out[0] ); 91 | mux8 b_1( { i0[1], i1[1], i2[1], i3[1], i4[1], i5[1], i6[1], i7[1] }, s[0], s[1], s[2], out[1] ); 92 | mux8 b_2( { i0[2], i1[2], i2[2], i3[2], i4[2], i5[2], i6[2], i7[2] }, s[0], s[1], s[2], out[2] ); 93 | mux8 b_3( { i0[3], i1[3], i2[3], i3[3], i4[3], i5[3], i6[3], i7[3] }, s[0], s[1], s[2], out[3] ); 94 | mux8 b_4( { i0[4], i1[4], i2[4], i3[4], i4[4], i5[4], i6[4], i7[4] }, s[0], s[1], s[2], out[4] ); 95 | mux8 b_5( { i0[5], i1[5], i2[5], i3[5], i4[5], i5[5], i6[5], i7[5] }, s[0], s[1], s[2], out[5] ); 96 | mux8 b_6( { i0[6], i1[6], i2[6], i3[6], i4[6], i5[6], i6[6], i7[6] }, s[0], s[1], s[2], out[6] ); 97 | mux8 b_7( { i0[7], i1[7], i2[7], i3[7], i4[7], i5[7], i6[7], i7[7] }, s[0], s[1], s[2], out[7] ); 98 | mux8 b_8( { i0[8], i1[8], i2[8], i3[8], i4[8], i5[8], i6[8], i7[8] }, s[0], s[1], s[2], out[8] ); 99 | mux8 b_9( { i0[9], i1[9], i2[9], i3[9], i4[9], i5[9], i6[9], i7[9] }, s[0], s[1], s[2], out[9] ); 100 | mux8 b_10( { i0[10], i1[10], i2[10], i3[10], i4[10], i5[10], i6[10], i7[10] }, s[0], s[1], s[2], out[10] ); 101 | mux8 b_11( { i0[11], i1[11], i2[11], i3[11], i4[11], i5[11], i6[11], i7[11] }, s[0], s[1], s[2], out[11] ); 102 | mux8 b_12( { i0[12], i1[12], i2[12], i3[12], i4[12], i5[12], i6[12], i7[12] }, s[0], s[1], s[2], out[12] ); 103 | mux8 b_13( { i0[13], i1[13], i2[13], i3[13], i4[13], i5[13], i6[13], i7[13] }, s[0], s[1], s[2], out[13] ); 104 | mux8 b_14( { i0[14], i1[14], i2[14], i3[14], i4[14], i5[14], i6[14], i7[14] }, s[0], s[1], s[2], out[14] ); 105 | mux8 b_15( { i0[15], i1[15], i2[15], i3[15], i4[15], i5[15], i6[15], i7[15] }, s[0], s[1], s[2], out[15] ); 106 | 107 | endmodule 108 | 109 | module STBitMux2(input [15:0] i0, i1, input s, output [15:0] o); 110 | mux2 op_0( i0[0], i1[0], s, o[0] ); 111 | mux2 op_1( i0[1], i1[1], s, o[1] ); 112 | mux2 op_2( i0[2], i1[2], s, o[2] ); 113 | mux2 op_3( i0[3], i1[3], s, o[3] ); 114 | mux2 op_4( i0[4], i1[4], s, o[4] ); 115 | mux2 op_5( i0[5], i1[5], s, o[5] ); 116 | mux2 op_6( i0[6], i1[6], s, o[6] ); 117 | mux2 op_7( i0[7], i1[7], s, o[7] ); 118 | mux2 op_8( i0[8], i1[8], s, o[8] ); 119 | mux2 op_9( i0[9], i1[9], s, o[9] ); 120 | mux2 op_10( i0[10], i1[10], s, o[10] ); 121 | mux2 op_11( i0[11], i1[11], s, o[11] ); 122 | mux2 op_12( i0[12], i1[12], s, o[12] ); 123 | mux2 op_13( i0[13], i1[13], s, o[13] ); 124 | mux2 op_14( i0[14], i1[14], s, o[14] ); 125 | mux2 op_15( i0[15], i1[15], s, o[15] ); 126 | endmodule 127 | -------------------------------------------------------------------------------- /tb_cq.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 100 ps 2 | `define TESTVECS 20 3 | 4 | module tb; 5 | reg clk, reset, wr, rd; 6 | wire full, empty; 7 | reg [15:0] din; 8 | wire [15:0] dout; 9 | reg [17:0] test_vecs [0:(`TESTVECS-1)]; 10 | integer i; 11 | initial begin $dumpfile("tb_cq.vcd"); $dumpvars(0,tb); end 12 | initial begin reset = 1'b1; #12.5 reset = 1'b0; end 13 | initial clk = 1'b0; always #5 clk =~ clk; 14 | initial begin 15 | test_vecs[0][17] = 1'b1; test_vecs[0][16] = 1'b0; test_vecs[0][15:0] = 16'ha; 16 | test_vecs[1][17] = 1'b0; test_vecs[1][16] = 1'b1; test_vecs[1][15:0] = 16'hxx; 17 | test_vecs[2][17] = 1'b1; test_vecs[2][16] = 1'b0; test_vecs[2][15:0] = 16'h1; 18 | test_vecs[3][17] = 1'b0; test_vecs[3][16] = 1'b1; test_vecs[3][15:0] = 16'hxx; 19 | test_vecs[4][17] = 1'b1; test_vecs[4][16] = 1'b0; test_vecs[4][15:0] = 16'h2; 20 | test_vecs[5][17] = 1'b0; test_vecs[5][16] = 1'b1; test_vecs[5][15:0] = 16'hxx; 21 | test_vecs[6][17] = 1'b0; test_vecs[6][16] = 1'b1; test_vecs[6][15:0] = 16'hxx; 22 | test_vecs[7][17] = 1'b1; test_vecs[7][16] = 1'b0; test_vecs[7][15:0] = 16'h4; 23 | test_vecs[8][17] = 1'b0; test_vecs[8][16] = 1'b1; test_vecs[8][15:0] = 16'hxx; 24 | test_vecs[9][17] = 1'b1; test_vecs[9][16] = 1'b0; test_vecs[9][15:0] = 16'h9; 25 | test_vecs[10][17] = 1'b1; test_vecs[10][16] = 1'b0; test_vecs[10][15:0] = 16'h6; 26 | test_vecs[11][17] = 1'b0; test_vecs[11][16] = 1'b1; test_vecs[11][15:0] = 16'hxx; 27 | test_vecs[12][17] = 1'b1; test_vecs[12][16] = 1'b0; test_vecs[12][15:0] = 16'h5; 28 | test_vecs[13][17] = 1'b1; test_vecs[13][16] = 1'b0; test_vecs[13][15:0] = 16'h8; 29 | test_vecs[14][17] = 1'b0; test_vecs[14][16] = 1'b1; test_vecs[14][15:0] = 16'hxx; 30 | test_vecs[15][17] = 1'b0; test_vecs[15][16] = 1'b1; test_vecs[15][15:0] = 16'hxx; 31 | test_vecs[16][17] = 1'b1; test_vecs[16][16] = 1'b0; test_vecs[16][15:0] = 16'h7; 32 | test_vecs[17][17] = 1'b0; test_vecs[17][16] = 1'b1; test_vecs[17][15:0] = 16'hxx; 33 | test_vecs[18][17] = 1'b1; test_vecs[18][16] = 1'b0; test_vecs[18][15:0] = 16'h3; 34 | test_vecs[19][17] = 1'b0; test_vecs[19][16] = 1'b1; test_vecs[19][15:0] = 16'hxx; 35 | end 36 | initial {wr, rd, din} = 0; 37 | cq cq_0 (clk, reset, wr, rd, din[15:0], empty, full, dout[15:0]); 38 | initial begin 39 | #6 for(i=0;i<`TESTVECS;i=i+1) 40 | begin #10 {wr, rd, din}=test_vecs[i]; end 41 | #10 $finish; 42 | end 43 | endmodule -------------------------------------------------------------------------------- /tests.txt: -------------------------------------------------------------------------------- 1 | // TEST 2 2 | test_vecs[0][17] = 1'b1; test_vecs[0][16] = 1'b0; test_vecs[0][15:0] = 16'ha; 3 | test_vecs[1][17] = 1'b0; test_vecs[1][16] = 1'b1; test_vecs[1][15:0] = 16'hxx; 4 | test_vecs[2][17] = 1'b1; test_vecs[2][16] = 1'b0; test_vecs[2][15:0] = 16'h1; 5 | test_vecs[3][17] = 1'b0; test_vecs[3][16] = 1'b1; test_vecs[3][15:0] = 16'hxx; 6 | test_vecs[4][17] = 1'b1; test_vecs[4][16] = 1'b0; test_vecs[4][15:0] = 16'h2; 7 | test_vecs[5][17] = 1'b0; test_vecs[5][16] = 1'b1; test_vecs[5][15:0] = 16'hxx; 8 | test_vecs[6][17] = 1'b0; test_vecs[6][16] = 1'b1; test_vecs[6][15:0] = 16'hxx; 9 | test_vecs[7][17] = 1'b1; test_vecs[7][16] = 1'b0; test_vecs[7][15:0] = 16'h4; 10 | test_vecs[8][17] = 1'b0; test_vecs[8][16] = 1'b1; test_vecs[8][15:0] = 16'hxx; 11 | test_vecs[9][17] = 1'b1; test_vecs[9][16] = 1'b0; test_vecs[9][15:0] = 16'h9; 12 | test_vecs[10][17] = 1'b1; test_vecs[10][16] = 1'b0; test_vecs[10][15:0] = 16'h6; 13 | test_vecs[11][17] = 1'b0; test_vecs[11][16] = 1'b1; test_vecs[11][15:0] = 16'hxx; 14 | test_vecs[12][17] = 1'b1; test_vecs[12][16] = 1'b0; test_vecs[12][15:0] = 16'h5; 15 | test_vecs[13][17] = 1'b1; test_vecs[13][16] = 1'b0; test_vecs[13][15:0] = 16'h8; 16 | test_vecs[14][17] = 1'b0; test_vecs[14][16] = 1'b1; test_vecs[14][15:0] = 16'hxx; 17 | test_vecs[15][17] = 1'b0; test_vecs[15][16] = 1'b1; test_vecs[15][15:0] = 16'hxx; 18 | test_vecs[16][17] = 1'b1; test_vecs[16][16] = 1'b0; test_vecs[16][15:0] = 16'h7; 19 | test_vecs[17][17] = 1'b0; test_vecs[17][16] = 1'b1; test_vecs[17][15:0] = 16'hxx; 20 | test_vecs[18][17] = 1'b1; test_vecs[18][16] = 1'b0; test_vecs[18][15:0] = 16'h3; 21 | test_vecs[19][17] = 1'b0; test_vecs[19][16] = 1'b1; test_vecs[19][15:0] = 16'hxx; 22 | 23 | 24 | // TEST 1 25 | test_vecs[0][17] = 1'b1; test_vecs[0][16] = 1'b0; test_vecs[0][15:0] = 16'h1; 26 | test_vecs[1][17] = 1'b1; test_vecs[1][16] = 1'b0; test_vecs[1][15:0] = 16'h2; 27 | test_vecs[2][17] = 1'b1; test_vecs[2][16] = 1'b0; test_vecs[2][15:0] = 16'h3; 28 | test_vecs[3][17] = 1'b1; test_vecs[3][16] = 1'b0; test_vecs[3][15:0] = 16'h4; 29 | test_vecs[4][17] = 1'b1; test_vecs[4][16] = 1'b0; test_vecs[4][15:0] = 16'h5; 30 | test_vecs[5][17] = 1'b1; test_vecs[5][16] = 1'b0; test_vecs[5][15:0] = 16'h6; 31 | test_vecs[6][17] = 1'b1; test_vecs[6][16] = 1'b0; test_vecs[6][15:0] = 16'h7; 32 | test_vecs[7][17] = 1'b1; test_vecs[7][16] = 1'b0; test_vecs[7][15:0] = 16'h8; 33 | test_vecs[8][17] = 1'b1; test_vecs[8][16] = 1'b0; test_vecs[8][15:0] = 16'h9; 34 | test_vecs[9][17] = 1'b1; test_vecs[9][16] = 1'b0; test_vecs[9][15:0] = 16'ha; 35 | test_vecs[10][17] = 1'b0; test_vecs[10][16] = 1'b1; test_vecs[10][15:0] = 16'hxx; 36 | test_vecs[11][17] = 1'b0; test_vecs[11][16] = 1'b1; test_vecs[11][15:0] = 16'hxx; 37 | test_vecs[12][17] = 1'b0; test_vecs[12][16] = 1'b1; test_vecs[12][15:0] = 16'hxx; 38 | test_vecs[13][17] = 1'b0; test_vecs[13][16] = 1'b1; test_vecs[13][15:0] = 16'hxx; 39 | test_vecs[14][17] = 1'b0; test_vecs[14][16] = 1'b1; test_vecs[14][15:0] = 16'hxx; 40 | test_vecs[15][17] = 1'b0; test_vecs[15][16] = 1'b1; test_vecs[15][15:0] = 16'hxx; 41 | test_vecs[16][17] = 1'b0; test_vecs[16][16] = 1'b1; test_vecs[16][15:0] = 16'hxx; 42 | test_vecs[17][17] = 1'b0; test_vecs[17][16] = 1'b1; test_vecs[17][15:0] = 16'hxx; 43 | test_vecs[18][17] = 1'b0; test_vecs[18][16] = 1'b1; test_vecs[18][15:0] = 16'hxx; 44 | test_vecs[19][17] = 1'b0; test_vecs[19][16] = 1'b1; test_vecs[19][15:0] = 16'hxx; --------------------------------------------------------------------------------