├── Testbench Generation code ├── Testbench Files │ ├── _test_nlog,sqrt.log.swp │ ├── test_sin,arctan.py │ ├── test_sin,sinh.py │ └── test_nodiv,tan.py └── Testbench code │ ├── test1.py │ └── test.py ├── HCORDIC_Verilog ├── sum_z.v ├── IdleState.v ├── CheckOpcode.v ├── HCORDIC_pipeline_crude.v ├── IdleMult.v ├── Pack_z.v ├── PackAdder.v ├── MultiplyMult.v ├── Descale_pipeline.v ├── Add.v ├── MultiplyMultDescale.v ├── PackSum_y.v ├── PreProcessxy.v ├── Pack_z_descale.v ├── AllignAdder.v ├── PackSum.v ├── ExecutePipeline.v ├── NormaliseProdMult.v ├── MultiplyState_Y.v ├── AddState.v ├── MultiplyState.v ├── NormaliseProdMultDescale.v ├── Allign2.v ├── mult_k.v ├── PackAdderProcess.v ├── AddProcess.v ├── FSM.v ├── Adder_z.v ├── AllignAdderProcess.v ├── NormaliseProd.v ├── mult_descale_pipeline.v ├── HCORDIC_Pipeline.v ├── Fetch_Crude.v ├── Fetch.v ├── PreProcessY.v ├── PreProcessX.v ├── InputMux.v ├── SpecialMult.v ├── SpecialAdd.v ├── SpecialMultDescale.v ├── HCORDIC_Pipeline_FSL.v ├── NormaliseAdder.v ├── Fetch_FSL.v ├── SpecialAddProcess.v ├── Allign.v ├── NormaliseSum.v ├── NormaliseAdderProcess.v ├── SpecialCases.v ├── alu_y_pipelined.v ├── alu_x_pipelined.v └── FSM_1.v └── README.md /Testbench Generation code/Testbench Files/_test_nlog,sqrt.log.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ankitshah009/High-Radix-Adaptive-CORDIC/HEAD/Testbench Generation code/Testbench Files/_test_nlog,sqrt.log.swp -------------------------------------------------------------------------------- /HCORDIC_Verilog/sum_z.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:38:20 02/22/2015 7 | // Design Name: 8 | // Module Name: sum_z 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module sum_z( 22 | ); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/IdleState.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:05:12 02/22/2015 7 | // Design Name: 8 | // Module Name: IdleState 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module IdleState( 22 | ); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/CheckOpcode.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:43:17 03/13/2015 7 | // Design Name: 8 | // Module Name: CheckOpcode 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CheckOpcode( 22 | ); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/HCORDIC_pipeline_crude.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:47:36 03/13/2015 7 | // Design Name: 8 | // Module Name: HCORDIC_pipeline_crude 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module HCORDIC_pipeline_crude( 22 | ); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/IdleMult.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:06:54 02/22/2015 7 | // Design Name: 8 | // Module Name: IdleMult 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module IdleMult( 22 | input [31:0] FinalProduct, 23 | input clock, 24 | output reg [31:0] FinalProductout 25 | ); 26 | 27 | always @ (posedge clock) 28 | begin 29 | FinalProductout <= FinalProduct; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # High-Radix-Adaptive-CORDIC 2 | High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC 3 | 4 | Pipelined implementation of high radix adaptive CORDIC as a coprocessor 5 | 6 | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7411207 7 | 8 | Abstract: The Coordinate Rotational Digital Computer (CORDIC) algorithm allows computation of trigonometric, hyperbolic, natural log and square root functions. This iterative algorithm uses only shift and add operations to converge. Multiple fixed radix variants of the algorithm have been implemented on hardware. These have demonstrated faster convergence at the expense of reduced accuracy. High radix adaptive variants of CORDIC also exist in literature. These allow for faster convergence at the expense of hardware multipliers in the datapath without compromising on the accuracy of the results. This paper proposes a 12 stage deep pipeline architecture to implement a high radix adaptive CORDIC algorithm. It employs floating point multipliers in place of the conventional shift and add architecture of fixed radix CORDIC. This design has been synthesised on a FPGA board to act as a coprocessor. The paper also studies the power, latency and accuracy of this implementation. 9 | 10 | Citation : Cite the following paper. Official Citation available on IEEE page 11 | 12 | S. S. Oza, A. P. Shah, T. Thokala and S. David, "Pipelined implementation of high radix adaptive CORDIC as a coprocessor," 2015 International Conference on Computing and Network Communications (CoCoNet), Trivandrum, 2015, pp. 333-342. 13 | 14 | Paper inspired by the work of HCORDIC research group -http://www.ece.uvic.ca/~elec499/2011-summer/group01/ 15 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Pack_z.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:52:13 02/22/2015 7 | // Design Name: 8 | // Module Name: Pack_z 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Pack_z( 22 | input idle_NormaliseProd, 23 | input [32:0] zout_NormaliseProd, 24 | input [49:0] productout_NormaliseProd, 25 | input clock, 26 | output reg [31:0] FinalProduct 27 | ); 28 | 29 | parameter no_idle = 1'b0, 30 | put_idle = 1'b1; 31 | 32 | wire z_sign; 33 | wire [7:0] z_exponent; 34 | wire [26:0] z_mantissa; 35 | 36 | assign z_sign = zout_NormaliseProd[32]; 37 | assign z_exponent = zout_NormaliseProd[31:24]; 38 | assign z_mantissa = {zout_NormaliseProd[23:0]}; 39 | 40 | always @ (posedge clock) 41 | begin 42 | 43 | if (idle_NormaliseProd == no_idle) 44 | begin 45 | FinalProduct[22 : 0] <= z_mantissa[22:0]; 46 | FinalProduct[30 : 23] <= z_exponent[7:0] + 127; 47 | FinalProduct[31] <= z_sign; 48 | if ($signed(z_exponent) == -126 && z_mantissa[23] == 0) begin 49 | FinalProduct[30 : 23] <= 0; 50 | end 51 | //if overflow occurs, return inf 52 | if ($signed(z_exponent) > 127) begin 53 | FinalProduct[22 : 0] <= 0; 54 | FinalProduct[30 : 23] <= 255; 55 | FinalProduct[31] <= z_sign; 56 | end 57 | end 58 | 59 | else begin 60 | FinalProduct <= zout_NormaliseProd[32:1]; 61 | end 62 | end 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/PackAdder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:31:09 02/22/2015 7 | // Design Name: 8 | // Module Name: PackAdder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PackAdder( 22 | input idle_NormaliseSum, 23 | input [31:0] sout_NormaliseSum, 24 | input [27:0] sum_NormaliseSum, 25 | input clock, 26 | output reg [31:0] sout_PackSum 27 | ); 28 | 29 | parameter no_idle = 1'b0, 30 | put_idle = 1'b1; 31 | 32 | wire s_sign; 33 | wire [7:0] s_exponent; 34 | 35 | assign s_sign = sout_NormaliseSum[31]; 36 | assign s_exponent = sout_NormaliseSum[30:23]; 37 | 38 | always @ (posedge clock) 39 | begin 40 | 41 | if (idle_NormaliseSum != put_idle) begin 42 | sout_PackSum[22:0] <= sum_NormaliseSum[25:3]; 43 | sout_PackSum[30:23] <= s_exponent + 127; 44 | sout_PackSum[31] <= s_sign; 45 | if ($signed(s_exponent) == -126 && sum_NormaliseSum[22] == 0) begin 46 | sout_PackSum[30 : 23] <= 0; 47 | end 48 | 49 | if ($signed(s_exponent) <= -126) begin 50 | sout_PackSum[30 : 23] <= 0; 51 | sout_PackSum[22:0] <= 0; 52 | end 53 | 54 | //if overflow occurs, return inf 55 | if ($signed(s_exponent) > 127) begin 56 | sout_PackSum[22 : 0] <= 0; 57 | sout_PackSum[30 : 23] <= 255; 58 | sout_PackSum[31] <= s_sign; 59 | end 60 | end 61 | 62 | else begin 63 | sout_PackSum <= sout_NormaliseSum; 64 | end 65 | end 66 | 67 | endmodule 68 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/MultiplyMult.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:45:48 02/22/2015 7 | // Design Name: 8 | // Module Name: MultiplyMult 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module MultiplyMult( 22 | input [32:0] aout_Special, 23 | input [32:0] bout_Special, 24 | input [32:0] zout_Special, 25 | input idle_Special, 26 | input clock, 27 | output reg idle_Multiply, 28 | output reg [32:0] zout_Multiply, 29 | output reg [49:0] productout_Multiply 30 | ); 31 | 32 | parameter no_idle = 1'b0, 33 | put_idle = 1'b1; 34 | 35 | wire a_sign; 36 | wire [7:0] a_exponent; 37 | wire [23:0] a_mantissa; 38 | 39 | wire b_sign; 40 | wire [7:0] b_exponent; 41 | wire [23:0] b_mantissa; 42 | 43 | assign a_sign = aout_Special[32]; 44 | assign a_exponent = aout_Special[31:24] - 127; 45 | assign a_mantissa = {aout_Special[23:0]}; 46 | 47 | assign b_sign = bout_Special[32]; 48 | assign b_exponent = bout_Special[31:24] - 127; 49 | assign b_mantissa = {bout_Special[23:0]}; 50 | 51 | 52 | always @ (posedge clock) 53 | begin 54 | 55 | idle_Multiply <= idle_Special; 56 | 57 | if (idle_Special == no_idle) begin 58 | 59 | zout_Multiply[32] <= a_sign ^ b_sign; 60 | zout_Multiply[31:24] <= a_exponent + b_exponent + 1; 61 | zout_Multiply[23:0] <= 0; 62 | productout_Multiply <= a_mantissa * b_mantissa * 4; 63 | 64 | end 65 | 66 | else begin 67 | zout_Multiply <= zout_Special; 68 | end 69 | 70 | end 71 | endmodule 72 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Descale_pipeline.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:04:44 02/23/2015 7 | // Design Name: 8 | // Module Name: Descale_pipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Descale_pipeline( 22 | input [31:0] x_scale, 23 | input [31:0] y_scale, 24 | input [31:0] z_scale, 25 | input [31:0] k_in, 26 | input [7:0] InsTagScaleOut, 27 | input ScaleValid, 28 | input NatLogFlagScaleOut, 29 | input reset, 30 | input clock, 31 | output [31:0] x_out, 32 | output [31:0] y_out, 33 | output [31:0] z_out, 34 | output done, 35 | output [7:0] InsTagFinal 36 | ); 37 | 38 | wire doneSpare; 39 | wire [7:0] InsTagFinalSpare; 40 | wire [31:0] z_outSpare; 41 | 42 | mult_descale_pipeline DescalePipe_x ( 43 | .a_multiplicand(x_scale), 44 | .b_multiplier(k_in), 45 | .z_scale(z_scale), 46 | .InsTagScaleOut(InsTagScaleOut), 47 | .ScaleValid(ScaleValid), 48 | .NatLogFlagScaleOut(NatLogFlagScaleOut), 49 | .reset(reset), 50 | .clock(clock), 51 | .FinalProduct(x_out), 52 | .done(done), 53 | .InsTagDescale(InsTagFinal), 54 | .z_out(z_out) 55 | ); 56 | 57 | mult_descale_pipeline DescalePipe_y ( 58 | .a_multiplicand(y_scale), 59 | .b_multiplier(k_in), 60 | .z_scale(z_scale), 61 | .InsTagScaleOut(InsTagScaleOut), 62 | .ScaleValid(ScaleValid), 63 | .NatLogFlagScaleOut(NatLogFlagScaleOut), 64 | .reset(reset), 65 | .clock(clock), 66 | .FinalProduct(y_out), 67 | .done(doneSpare), 68 | .InsTagDescale(InsTagFinalSpare), 69 | .z_out(z_outSpare) 70 | ); 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Add.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:20:24 02/22/2015 7 | // Design Name: 8 | // Module Name: Add 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Add( 22 | input idle_Allign, 23 | input [35:0] cout_Allign, 24 | input [35:0] zout_Allign, 25 | input [31:0] sout_Allign, 26 | input clock, 27 | output reg idle_AddState, 28 | output reg [31:0] sout_AddState, 29 | output reg [27:0] sum_AddState 30 | ); 31 | parameter no_idle = 1'b0, 32 | put_idle = 1'b1; 33 | 34 | wire z_sign; 35 | wire [7:0] z_exponent; 36 | wire [26:0] z_mantissa; 37 | 38 | wire c_sign; 39 | wire [7:0] c_exponent; 40 | wire [26:0] c_mantissa; 41 | 42 | assign z_sign = zout_Allign[35]; 43 | assign z_exponent = zout_Allign[34:27] - 127; 44 | assign z_mantissa = {zout_Allign[26:0]}; 45 | 46 | assign c_sign = cout_Allign[35]; 47 | assign c_exponent = cout_Allign[34:27] - 127; 48 | assign c_mantissa = {cout_Allign[26:0]}; 49 | 50 | always @ (posedge clock) 51 | begin 52 | 53 | idle_AddState <= idle_Allign; 54 | 55 | if (idle_Allign != put_idle) begin 56 | sout_AddState[30:23] <= c_exponent; 57 | sout_AddState[22:0] <= 0; 58 | if (c_sign == z_sign) begin 59 | sum_AddState <= c_mantissa + z_mantissa; 60 | sout_AddState[31] <= c_sign; 61 | end else begin 62 | if (c_mantissa >= z_mantissa) begin 63 | sum_AddState <= c_mantissa - z_mantissa; 64 | sout_AddState[31] <= c_sign; 65 | end else begin 66 | sum_AddState <= z_mantissa - c_mantissa; 67 | sout_AddState[31] <= z_sign; 68 | end 69 | end 70 | end 71 | 72 | else begin 73 | sout_AddState <= sout_Allign; 74 | sum_AddState <= 0; 75 | end 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/MultiplyMultDescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:45:48 02/22/2015 7 | // Design Name: 8 | // Module Name: MultiplyMult 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module MultiplyMultDescale( 22 | input [32:0] aout_Special, 23 | input [32:0] bout_Special, 24 | input [32:0] zout_Special, 25 | input idle_Special, 26 | input [7:0] InsTagSpecial, 27 | input ScaleValidSpecial, 28 | input [31:0] z_Special, 29 | input clock, 30 | output reg idle_Multiply, 31 | output reg [32:0] zout_Multiply, 32 | output reg [49:0] productout_Multiply, 33 | output reg [7:0] InsTagMultiply, 34 | output reg ScaleValidMultiply, 35 | output reg [31:0] z_Multiply 36 | ); 37 | 38 | parameter no_idle = 1'b0, 39 | put_idle = 1'b1; 40 | 41 | wire a_sign; 42 | wire [7:0] a_exponent; 43 | wire [23:0] a_mantissa; 44 | 45 | wire b_sign; 46 | wire [7:0] b_exponent; 47 | wire [23:0] b_mantissa; 48 | 49 | assign a_sign = aout_Special[32]; 50 | assign a_exponent = aout_Special[31:24] - 127; 51 | assign a_mantissa = {aout_Special[23:0]}; 52 | 53 | assign b_sign = bout_Special[32]; 54 | assign b_exponent = bout_Special[31:24] - 127; 55 | assign b_mantissa = {bout_Special[23:0]}; 56 | 57 | 58 | always @ (posedge clock) 59 | begin 60 | 61 | z_Multiply <= z_Special; 62 | ScaleValidMultiply <= ScaleValidSpecial; 63 | InsTagMultiply <= InsTagSpecial; 64 | idle_Multiply <= idle_Special; 65 | 66 | if (idle_Special == no_idle) begin 67 | 68 | zout_Multiply[32] <= a_sign ^ b_sign; 69 | zout_Multiply[31:24] <= a_exponent + b_exponent + 1; 70 | zout_Multiply[23:0] <= 0; 71 | productout_Multiply <= a_mantissa * b_mantissa * 4; 72 | 73 | end 74 | 75 | else begin 76 | zout_Multiply <= zout_Special; 77 | end 78 | 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/PackSum_y.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:07:40 02/23/2015 7 | // Design Name: 8 | // Module Name: PackSum_y 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PackSum_y( 22 | input [1:0] idle_NormaliseSum, 23 | input [31:0] sout_NormaliseSum, 24 | input [1:0] modeout_NormaliseSum, 25 | input operationout_NormaliseSum, 26 | input [27:0] sum_NormaliseSum, 27 | input [7:0] InsTag_NormaliseSum, 28 | input clock, 29 | output reg [31:0] sout_PackSum, 30 | output reg done = 1'b0 31 | ); 32 | 33 | parameter mode_circular =2'b01, 34 | mode_linear =2'b00, 35 | mode_hyperbolic=2'b11; 36 | 37 | parameter no_idle = 2'b00, 38 | allign_idle = 2'b01, 39 | put_idle = 2'b10; 40 | 41 | wire s_sign; 42 | wire [7:0] s_exponent; 43 | 44 | assign s_sign = sout_NormaliseSum[31]; 45 | assign s_exponent = sout_NormaliseSum[30:23]; 46 | 47 | always @ (posedge clock) 48 | begin 49 | 50 | if (modeout_NormaliseSum == mode_circular) begin 51 | done <= 1'b1; 52 | end 53 | 54 | if (idle_NormaliseSum != put_idle) begin 55 | sout_PackSum[22:0] <= sum_NormaliseSum[25:3]; 56 | sout_PackSum[30:23] <= s_exponent + 127; 57 | sout_PackSum[31] <= s_sign; 58 | if ($signed(s_exponent) == -126 && sum_NormaliseSum[22] == 0) begin 59 | sout_PackSum[30 : 23] <= 0; 60 | end 61 | 62 | if ($signed(s_exponent) <= -126) begin 63 | sout_PackSum[30 : 23] <= 0; 64 | sout_PackSum[22:0] <= 0; 65 | end 66 | 67 | //if overflow occurs, return inf 68 | if ($signed(s_exponent) > 127) begin 69 | sout_PackSum[22 : 0] <= 0; 70 | sout_PackSum[30 : 23] <= 255; 71 | sout_PackSum[31] <= s_sign; 72 | end 73 | end 74 | 75 | else begin 76 | sout_PackSum <= sout_NormaliseSum; 77 | end 78 | end 79 | 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/PreProcessxy.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:34:44 03/13/2015 7 | // Design Name: 8 | // Module Name: PreProcessxy 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PreProcessxy( 22 | input [107:0] InstructionPacket, // Unprocessed square root is given an opcode that is not defined in fetch. 23 | input clock, 24 | output [107:0] InstructionPacketOut, 25 | output InputReady 26 | ); 27 | 28 | wire [3:0] Opcode; 29 | wire [31:0] x_processor; 30 | wire [31:0] y_processor; 31 | wire [31:0] z_processor; 32 | wire [7:0] InsTagIn; 33 | 34 | wire [31:0] x_new, y_new, z_newX, z_newY; 35 | wire [3:0] OpcodeX, OpcodeY; 36 | wire DoneX, DoneY; 37 | wire [7:0] InsX,InsY; 38 | 39 | assign InsTagIn = InstructionPacket[107:100]; 40 | assign Opcode = InstructionPacket[99:96]; 41 | assign x_processor = InstructionPacket[31:0]; 42 | assign y_processor = InstructionPacket[63:32]; 43 | assign z_processor = InstructionPacket[95:64]; 44 | 45 | assign InstructionPacketOut[31:0] = x_new; 46 | assign InstructionPacketOut[63:32] = y_new; 47 | 48 | assign InputReady = DoneX && DoneY; 49 | assign InstructionPacketOut[95:64] = z_newX; 50 | assign InstructionPacketOut[99:96] = OpcodeX; 51 | assign InstructionPacketOut[107:100] = InsX; 52 | 53 | PreProcessX X ( 54 | .z_preprocess(z_processor), 55 | .Opcode(Opcode), 56 | .b_adder(x_processor), 57 | .InsTagIn(InsTagIn), 58 | .clock(clock), 59 | .FinalSum(x_new), 60 | .Done(DoneX), 61 | .z_postprocess(z_newX), 62 | .Opcode_out(OpcodeX), 63 | .InsTagOut(InsX) 64 | ); 65 | 66 | PreProcessY Y ( 67 | .z_preprocess(z_processor), 68 | .Opcode(Opcode), 69 | .b_adder(y_processor), 70 | .InsTagIn(InsTagIn), 71 | .clock(clock), 72 | .FinalSum(y_new), 73 | .Done(DoneY), 74 | .z_postprocess(z_newY), 75 | .Opcode_out(OpcodeY), 76 | .InsTagOut(InsY) 77 | ); 78 | 79 | 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Pack_z_descale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:10:30 02/23/2015 7 | // Design Name: 8 | // Module Name: Pack_z_descale 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Pack_z_descale( 22 | input idle_NormaliseProd, 23 | input [32:0] zout_NormaliseProd, 24 | input [49:0] productout_NormaliseProd, 25 | input [7:0] InsTagNormaliseProd, 26 | input ScaleValidNormaliseProd, 27 | input [31:0] z_NormaliseProd, 28 | input reset, 29 | input clock, 30 | output reg done = 1'b0, 31 | output reg [31:0] FinalProduct, 32 | output reg [7:0] InsTagPack, 33 | output reg [31:0] z_Descale 34 | ); 35 | 36 | parameter no_idle = 1'b0, 37 | put_idle = 1'b1; 38 | 39 | wire z_sign; 40 | wire [7:0] z_exponent; 41 | wire [26:0] z_mantissa; 42 | 43 | assign z_sign = zout_NormaliseProd[32]; 44 | assign z_exponent = zout_NormaliseProd[31:24]; 45 | assign z_mantissa = {zout_NormaliseProd[23:0]}; 46 | 47 | always @ (posedge clock) 48 | begin 49 | 50 | if(reset == 1'b1) begin 51 | done <= 1'b0; 52 | end 53 | 54 | else begin 55 | z_Descale <= z_NormaliseProd; 56 | InsTagPack <= InsTagNormaliseProd; 57 | 58 | if(ScaleValidNormaliseProd == 1'b1) begin 59 | done <= 1'b1; 60 | end 61 | else begin 62 | done <= 1'b0; 63 | end 64 | 65 | if (idle_NormaliseProd == no_idle) 66 | begin 67 | FinalProduct[22 : 0] <= z_mantissa[22:0]; 68 | FinalProduct[30 : 23] <= z_exponent[7:0] + 127; 69 | FinalProduct[31] <= z_sign; 70 | if ($signed(z_exponent) == -126 && z_mantissa[23] == 0) begin 71 | FinalProduct[30 : 23] <= 0; 72 | end 73 | //if overflow occurs, return inf 74 | if ($signed(z_exponent) > 127) begin 75 | FinalProduct[22 : 0] <= 0; 76 | FinalProduct[30 : 23] <= 255; 77 | FinalProduct[31] <= z_sign; 78 | end 79 | end 80 | 81 | else begin 82 | FinalProduct <= zout_NormaliseProd[32:1]; 83 | end 84 | 85 | end 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/AllignAdder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:11:24 02/22/2015 7 | // Design Name: 8 | // Module Name: AllignAdder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module AllignAdder( 22 | input idle_Special, 23 | input [35:0] cout_Special, 24 | input [35:0] zout_Special, 25 | input [31:0] sout_Special, 26 | input [7:0] difference_Special, 27 | input clock, 28 | output reg idle_Allign, 29 | output reg [35:0] cout_Allign, 30 | output reg [35:0] zout_Allign, 31 | output reg [31:0] sout_Allign 32 | ); 33 | 34 | parameter no_idle = 1'b01, 35 | put_idle = 1'b1; 36 | 37 | wire z_sign; 38 | wire [7:0] z_exponent; 39 | wire [26:0] z_mantissa; 40 | 41 | wire c_sign; 42 | wire [7:0] c_exponent; 43 | wire [26:0] c_mantissa; 44 | 45 | assign z_sign = zout_Special[35]; 46 | assign z_exponent = zout_Special[34:27] - 127; 47 | assign z_mantissa = {zout_Special[26:0]}; 48 | 49 | assign c_sign = cout_Special[35]; 50 | assign c_exponent = cout_Special[34:27] - 127; 51 | assign c_mantissa = {cout_Special[26:0]}; 52 | 53 | always @ (posedge clock) 54 | begin 55 | 56 | idle_Allign <= idle_Special; 57 | sout_Allign <= sout_Special; 58 | 59 | if (idle_Special != put_idle) begin 60 | if ($signed(c_exponent) > $signed(z_exponent)) begin 61 | zout_Allign[35] <= zout_Special[35]; 62 | zout_Allign[34:27] <= z_exponent + difference_Special + 127; 63 | zout_Allign[26:0] <= z_mantissa >> difference_Special; 64 | zout_Allign[0] <= z_mantissa[0] | z_mantissa[1]; 65 | cout_Allign <= cout_Special; 66 | end else if ($signed(c_exponent) <= $signed(z_exponent)) begin 67 | cout_Allign[35] <= cout_Special[35]; 68 | cout_Allign[34:27] <= c_exponent + difference_Special + 127; 69 | cout_Allign[26:0] <= c_mantissa >> difference_Special; 70 | cout_Allign[0] <= c_mantissa[0] | c_mantissa[1]; 71 | zout_Allign <= zout_Special; 72 | end 73 | end 74 | 75 | else begin 76 | zout_Allign <= zout_Special; 77 | cout_Allign <= cout_Special; 78 | end 79 | end 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/PackSum.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:25:13 02/22/2015 7 | // Design Name: 8 | // Module Name: PackSum 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PackSum( 22 | input [1:0] idle_NormaliseSum, 23 | input [31:0] sout_NormaliseSum, 24 | input [1:0] modeout_NormaliseSum, 25 | input operationout_NormaliseSum, 26 | input NatLogFlagout_NormaliseSum, 27 | input [27:0] sum_NormaliseSum, 28 | input [7:0] InsTag_NormaliseSum, 29 | input clock, 30 | output reg [31:0] sout_PackSum, 31 | output reg [1:0] modeout_PackSum, 32 | output reg operationout_PackSum, 33 | output reg NatLogFlagout_PackSum, 34 | output reg [7:0] InsTag_PackSum 35 | ); 36 | 37 | parameter mode_circular =2'b01, 38 | mode_linear =2'b00, 39 | mode_hyperbolic=2'b11; 40 | 41 | parameter no_idle = 2'b00, 42 | allign_idle = 2'b01, 43 | put_idle = 2'b10; 44 | 45 | wire s_sign; 46 | wire [7:0] s_exponent; 47 | 48 | assign s_sign = sout_NormaliseSum[31]; 49 | assign s_exponent = sout_NormaliseSum[30:23]; 50 | 51 | always @ (posedge clock) 52 | begin 53 | 54 | InsTag_PackSum <= InsTag_NormaliseSum; 55 | modeout_PackSum <= modeout_NormaliseSum; 56 | operationout_PackSum <= operationout_NormaliseSum; 57 | NatLogFlagout_PackSum <= NatLogFlagout_NormaliseSum; 58 | 59 | if (idle_NormaliseSum != put_idle) begin 60 | sout_PackSum[22:0] <= sum_NormaliseSum[25:3]; 61 | sout_PackSum[30:23] <= s_exponent + 127; 62 | sout_PackSum[31] <= s_sign; 63 | if ($signed(s_exponent) == -126 && sum_NormaliseSum[22] == 0) begin 64 | sout_PackSum[30 : 23] <= 0; 65 | end 66 | 67 | if ($signed(s_exponent) <= -126) begin 68 | sout_PackSum[30 : 23] <= 0; 69 | sout_PackSum[22:0] <= 0; 70 | end 71 | 72 | //if overflow occurs, return inf 73 | if ($signed(s_exponent) > 127) begin 74 | sout_PackSum[22 : 0] <= 0; 75 | sout_PackSum[30 : 23] <= 255; 76 | sout_PackSum[31] <= s_sign; 77 | end 78 | end 79 | 80 | else begin 81 | sout_PackSum <= sout_NormaliseSum; 82 | end 83 | end 84 | 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/ExecutePipeline.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:32:54 02/22/2015 7 | // Design Name: 8 | // Module Name: ExecutePipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ExecutePipeline( 22 | input [31:0] X_in, 23 | input [31:0] Y_in, 24 | input [31:0] Z_in, 25 | input [31:0] K_in, 26 | input [31:0] kappa_in, 27 | input [31:0] theta_in, 28 | input [31:0] delta_in, 29 | input reset, 30 | input clock, 31 | input operation, 32 | input NatLogFlag_Execute, 33 | input [1:0] mode, 34 | input [7:0] InsTagFSMOut, 35 | output [31:0] X_next, 36 | output [31:0] Y_next, 37 | output [31:0] Z_next, 38 | output [31:0] K_next, 39 | output [1:0] mode_out, 40 | output operation_out, 41 | output NatLogFlag_iter, 42 | output ALU_done, 43 | output [7:0] InsTag_iter 44 | ); 45 | 46 | alu_x_pipelined alu_x ( 47 | .a_multiplicand(Y_in), 48 | .b_multiplier(delta_in), 49 | .c_addition(X_in), 50 | .mode(mode), 51 | .operation(operation), 52 | .NatLogFlag_Execute(NatLogFlag_Execute), 53 | .InsTagFSMOut(InsTagFSMOut), 54 | .reset(reset), 55 | .clock(clock), 56 | .accumulate(X_next), 57 | .mode_out(mode_out), 58 | .operation_out(operation_out), 59 | .NatLogFlag_iter(NatLogFlag_iter), 60 | .InsTagXOut(InsTag_iter) 61 | ); 62 | 63 | alu_y_pipelined alu_y ( 64 | .a_multiplicand(X_in), 65 | .b_multiplier(delta_in), 66 | .c_addition(Y_in), 67 | .mode(mode), 68 | .operation(operation), 69 | .NatLogFlag_Execute(NatLogFlag_Execute), 70 | .InsTagFSMOut(InsTagFSMOut), 71 | .reset(reset), 72 | .clock(clock), 73 | .accumulate(Y_next), 74 | .done(ALU_done) 75 | ); 76 | 77 | mult_k mul_k ( 78 | .a_multiplicand(K_in), 79 | .b_multiplier(kappa_in), 80 | .reset(reset), 81 | .clock(clock), 82 | .FinalProduct(K_next) 83 | ); 84 | 85 | Adder_z add_z ( 86 | .a_adder(Z_in), 87 | .b_adder(theta_in), 88 | .reset(reset), 89 | .clock(clock), 90 | .FinalSum(Z_next) 91 | ); 92 | endmodule 93 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/NormaliseProdMult.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:49:08 02/22/2015 7 | // Design Name: 8 | // Module Name: NormaliseProdMult 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NormaliseProdMult( 22 | input [32:0] zout_Multiply, 23 | input [49:0] productout_Multiply, 24 | input clock, 25 | input idle_Multiply, 26 | output reg idle_NormaliseProd, 27 | output reg [32:0] zout_NormaliseProd, 28 | output reg [49:0] productout_NormaliseProd 29 | ); 30 | 31 | parameter no_idle = 1'b0, 32 | put_idle = 1'b1; 33 | 34 | wire z_sign; 35 | wire [7:0] z_exponent; 36 | wire [26:0] z_mantissa; 37 | 38 | assign z_sign = zout_Multiply[32]; 39 | assign z_exponent = zout_Multiply[31:24]; 40 | assign z_mantissa = {zout_Multiply[23:0]}; 41 | 42 | always @ (posedge clock) begin 43 | 44 | idle_NormaliseProd <= idle_Multiply; 45 | 46 | if (idle_Multiply == no_idle) begin 47 | 48 | // This case will never arise. This is because for input with exponent less than -12 multiply isn't used. 49 | if ($signed(z_exponent) < -126) begin 50 | zout_NormaliseProd[32] <= z_sign; 51 | zout_NormaliseProd[31:24] <= z_exponent + 1; 52 | zout_NormaliseProd[23:0] <= z_mantissa; 53 | productout_NormaliseProd <= productout_Multiply >> 1; 54 | end 55 | 56 | // This could be problematic. Will have to test for average number of cycles 57 | // Current solution is to hard code for all cases like normalisation in addition. 58 | else if (productout_Multiply[49] == 0) begin 59 | zout_NormaliseProd[32] <= z_sign; 60 | zout_NormaliseProd[31:24] <= z_exponent - 1; 61 | zout_NormaliseProd[23:0] <= {productout_Multiply[48:25]}; 62 | productout_NormaliseProd <= productout_Multiply << 1; 63 | end 64 | 65 | else begin 66 | zout_NormaliseProd[32] <= z_sign; 67 | zout_NormaliseProd[31:24] <= z_exponent; 68 | zout_NormaliseProd[23:0] <= {productout_Multiply[49:26]}; 69 | productout_NormaliseProd <= productout_Multiply; 70 | end 71 | end 72 | 73 | else begin 74 | zout_NormaliseProd <= zout_Multiply; 75 | end 76 | 77 | end 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/MultiplyState_Y.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:27:13 02/22/2015 7 | // Design Name: 8 | // Module Name: MultiplyState_Y 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module MultiplyState_Y( 22 | input [32:0] aout_Special, 23 | input [32:0] bout_Special, 24 | input [35:0] cout_Special, 25 | input [35:0] zout_Special, 26 | input [31:0] sout_Special, 27 | input [1:0] modeout_Special, 28 | input operationout_Special, 29 | input NatLogFlagout_Special, 30 | input [7:0] InsTag_Special, 31 | input clock, 32 | input [1:0] idle_Special, 33 | output reg [1:0] idle_Multiply, 34 | output reg [35:0] cout_Multiply, 35 | output reg [35:0] zout_Multiply, 36 | output reg [31:0] sout_Multiply, 37 | output reg [1:0] modeout_Multiply, 38 | output reg operationout_Multiply, 39 | output reg NatLogFlagout_Multiply, 40 | output reg [49:0] productout_Multiply, 41 | output reg [7:0] InsTag_Multiply 42 | ); 43 | 44 | parameter mode_circular =2'b01, 45 | mode_linear =2'b00, 46 | mode_hyperbolic=2'b11; 47 | 48 | parameter no_idle = 2'b00, 49 | allign_idle = 2'b01, 50 | put_idle = 2'b10; 51 | 52 | wire a_sign; 53 | wire [7:0] a_exponent; 54 | wire [23:0] a_mantissa; 55 | 56 | wire b_sign; 57 | wire [7:0] b_exponent; 58 | wire [23:0] b_mantissa; 59 | 60 | assign a_sign = aout_Special[32]; 61 | assign a_exponent = aout_Special[31:24] - 127; 62 | assign a_mantissa = {aout_Special[23:0]}; 63 | 64 | assign b_sign = bout_Special[32]; 65 | assign b_exponent = bout_Special[31:24] - 127; 66 | assign b_mantissa = {bout_Special[23:0]}; 67 | 68 | 69 | always @ (posedge clock) 70 | begin 71 | 72 | InsTag_Multiply <= InsTag_Special; 73 | sout_Multiply <= sout_Special; 74 | cout_Multiply <= cout_Special; 75 | modeout_Multiply <= modeout_Special; 76 | operationout_Multiply <= operationout_Special; 77 | idle_Multiply <= idle_Special; 78 | NatLogFlagout_Multiply <= NatLogFlagout_Special; 79 | 80 | if (idle_Special == no_idle) begin 81 | 82 | zout_Multiply[35] <= ~(a_sign ^ b_sign); 83 | zout_Multiply[34:27] <= a_exponent + b_exponent + 1; 84 | zout_Multiply[26:0] <= 0; 85 | productout_Multiply <= a_mantissa * b_mantissa * 4; 86 | 87 | end 88 | 89 | else begin 90 | zout_Multiply <= zout_Special; 91 | end 92 | end 93 | endmodule 94 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/AddState.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:45:21 02/22/2015 7 | // Design Name: 8 | // Module Name: AddState 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module AddState( 22 | input [1:0] idle_Allign2, 23 | input [35:0] cout_Allign2, 24 | input [35:0] zout_Allign2, 25 | input [31:0] sout_Allign2, 26 | input [1:0] modeout_Allign2, 27 | input operationout_Allign2, 28 | input NatLogFlagout_Allign2, 29 | input [7:0] InsTag_Allign2, 30 | input clock, 31 | output reg [1:0] idle_AddState, 32 | output reg [31:0] sout_AddState, 33 | output reg [1:0] modeout_AddState, 34 | output reg operationout_AddState, 35 | output reg NatLogFlagout_AddState, 36 | output reg [27:0] sum_AddState, 37 | output reg [7:0] InsTag_AddState 38 | ); 39 | 40 | parameter mode_circular =2'b01, 41 | mode_linear =2'b00, 42 | mode_hyperbolic=2'b11; 43 | 44 | parameter no_idle = 2'b00, 45 | allign_idle = 2'b01, 46 | put_idle = 2'b10; 47 | 48 | wire z_sign; 49 | wire [7:0] z_exponent; 50 | wire [26:0] z_mantissa; 51 | 52 | wire c_sign; 53 | wire [7:0] c_exponent; 54 | wire [26:0] c_mantissa; 55 | 56 | assign z_sign = zout_Allign2[35]; 57 | assign z_exponent = zout_Allign2[34:27] - 127; 58 | assign z_mantissa = {zout_Allign2[26:0]}; 59 | 60 | assign c_sign = cout_Allign2[35]; 61 | assign c_exponent = cout_Allign2[34:27] - 127; 62 | assign c_mantissa = {cout_Allign2[26:0]}; 63 | 64 | always @ (posedge clock) 65 | begin 66 | 67 | InsTag_AddState <= InsTag_Allign2; 68 | idle_AddState <= idle_Allign2; 69 | modeout_AddState <= modeout_Allign2; 70 | operationout_AddState <= operationout_Allign2; 71 | NatLogFlagout_AddState <= NatLogFlagout_Allign2; 72 | 73 | if (idle_Allign2 != put_idle) begin 74 | sout_AddState[30:23] <= c_exponent; 75 | sout_AddState[22:0] <= 0; 76 | if (c_sign == z_sign) begin 77 | sum_AddState <= c_mantissa + z_mantissa; 78 | sout_AddState[31] <= c_sign; 79 | end else begin 80 | if (c_mantissa >= z_mantissa) begin 81 | sum_AddState <= c_mantissa - z_mantissa; 82 | sout_AddState[31] <= c_sign; 83 | end else begin 84 | sum_AddState <= z_mantissa - c_mantissa; 85 | sout_AddState[31] <= z_sign; 86 | end 87 | end 88 | end 89 | 90 | else begin 91 | sout_AddState <= sout_Allign2; 92 | sum_AddState <= 0; 93 | end 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/MultiplyState.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:01:44 02/21/2015 7 | // Design Name: 8 | // Module Name: MultiplyState 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module MultiplyState( 22 | input [32:0] aout_Special, 23 | input [32:0] bout_Special, 24 | input [35:0] cout_Special, 25 | input [35:0] zout_Special, 26 | input [31:0] sout_Special, 27 | input [1:0] modeout_Special, 28 | input operationout_Special, 29 | input NatLogFlagout_Special, 30 | input [7:0] InsTag_Special, 31 | input clock, 32 | input [1:0] idle_Special, 33 | output reg [1:0] idle_Multiply, 34 | output reg [35:0] cout_Multiply, 35 | output reg [35:0] zout_Multiply, 36 | output reg [31:0] sout_Multiply, 37 | output reg [1:0] modeout_Multiply, 38 | output reg operationout_Multiply, 39 | output reg NatLogFlagout_Multiply, 40 | output reg [49:0] productout_Multiply, 41 | output reg [7:0] InsTag_Multiply 42 | ); 43 | 44 | parameter mode_circular =2'b01, 45 | mode_linear =2'b00, 46 | mode_hyperbolic=2'b11; 47 | 48 | parameter no_idle = 2'b00, 49 | allign_idle = 2'b01, 50 | put_idle = 2'b10; 51 | 52 | wire a_sign; 53 | wire [7:0] a_exponent; 54 | wire [23:0] a_mantissa; 55 | 56 | wire b_sign; 57 | wire [7:0] b_exponent; 58 | wire [23:0] b_mantissa; 59 | 60 | assign a_sign = aout_Special[32]; 61 | assign a_exponent = aout_Special[31:24] - 127; 62 | assign a_mantissa = {aout_Special[23:0]}; 63 | 64 | assign b_sign = bout_Special[32]; 65 | assign b_exponent = bout_Special[31:24] - 127; 66 | assign b_mantissa = {bout_Special[23:0]}; 67 | 68 | 69 | always @ (posedge clock) 70 | begin 71 | 72 | InsTag_Multiply <= InsTag_Special; 73 | sout_Multiply <= sout_Special; 74 | cout_Multiply <= cout_Special; 75 | modeout_Multiply <= modeout_Special; 76 | operationout_Multiply <= operationout_Special; 77 | idle_Multiply <= idle_Special; 78 | NatLogFlagout_Multiply <= NatLogFlagout_Special; 79 | 80 | if (idle_Special == no_idle) begin 81 | 82 | if (modeout_Special == mode_circular) begin 83 | zout_Multiply[35] <= a_sign ^ b_sign; 84 | end 85 | else if (modeout_Special == mode_hyperbolic) begin 86 | zout_Multiply[35] <= ~(a_sign ^ b_sign); 87 | end 88 | zout_Multiply[34:27] <= a_exponent + b_exponent + 1; 89 | zout_Multiply[26:0] <= 0; 90 | productout_Multiply <= a_mantissa * b_mantissa * 4; 91 | 92 | end 93 | 94 | else begin 95 | zout_Multiply <= zout_Special; 96 | end 97 | end 98 | endmodule 99 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/NormaliseProdMultDescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:49:08 02/22/2015 7 | // Design Name: 8 | // Module Name: NormaliseProdMult 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NormaliseProdMultDescale( 22 | input [32:0] zout_Multiply, 23 | input [49:0] productout_Multiply, 24 | input [7:0] InsTagMultiply, 25 | input ScaleValidMultiply, 26 | input [31:0] z_Multiply, 27 | input clock, 28 | input idle_Multiply, 29 | output reg idle_NormaliseProd, 30 | output reg [32:0] zout_NormaliseProd, 31 | output reg [49:0] productout_NormaliseProd, 32 | output reg [7:0] InsTagNormaliseProd, 33 | output reg ScaleValidNormaliseProd, 34 | output reg [31:0] z_NormaliseProd 35 | ); 36 | 37 | parameter no_idle = 1'b0, 38 | put_idle = 1'b1; 39 | 40 | wire z_sign; 41 | wire [7:0] z_exponent; 42 | wire [26:0] z_mantissa; 43 | 44 | assign z_sign = zout_Multiply[32]; 45 | assign z_exponent = zout_Multiply[31:24]; 46 | assign z_mantissa = {zout_Multiply[23:0]}; 47 | 48 | always @ (posedge clock) begin 49 | 50 | z_NormaliseProd <= z_Multiply; 51 | ScaleValidNormaliseProd <= ScaleValidMultiply; 52 | InsTagNormaliseProd <= InsTagMultiply; 53 | idle_NormaliseProd <= idle_Multiply; 54 | 55 | if (idle_Multiply == no_idle) begin 56 | 57 | // This case will never arise. This is because for input with exponent less than -12 multiply isn't used. 58 | if ($signed(z_exponent) < -126) begin 59 | zout_NormaliseProd[32] <= z_sign; 60 | zout_NormaliseProd[31:24] <= z_exponent + 1; 61 | zout_NormaliseProd[23:0] <= z_mantissa; 62 | productout_NormaliseProd <= productout_Multiply >> 1; 63 | end 64 | 65 | // This could be problematic. Will have to test for average number of cycles 66 | // Current solution is to hard code for all cases like normalisation in addition. 67 | else if (productout_Multiply[49] == 0) begin 68 | zout_NormaliseProd[32] <= z_sign; 69 | zout_NormaliseProd[31:24] <= z_exponent - 1; 70 | zout_NormaliseProd[23:0] <= {productout_Multiply[48:25]}; 71 | productout_NormaliseProd <= productout_Multiply << 1; 72 | end 73 | 74 | else begin 75 | zout_NormaliseProd[32] <= z_sign; 76 | zout_NormaliseProd[31:24] <= z_exponent; 77 | zout_NormaliseProd[23:0] <= {productout_Multiply[49:26]}; 78 | productout_NormaliseProd <= productout_Multiply; 79 | end 80 | end 81 | 82 | else begin 83 | zout_NormaliseProd <= zout_Multiply; 84 | end 85 | 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Allign2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:21:30 02/22/2015 7 | // Design Name: 8 | // Module Name: Allign2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Allign2( 22 | input [1:0] idle_Allign, 23 | input [35:0] cout_Allign, 24 | input [35:0] zout_Allign, 25 | input [31:0] sout_Allign, 26 | input [1:0] modeout_Allign, 27 | input operationout_Allign, 28 | input NatLogFlagout_Allign, 29 | input [7:0] difference_Allign, 30 | input [7:0] InsTag_Allign, 31 | input clock, 32 | output reg [1:0] idle_Allign2, 33 | output reg [35:0] cout_Allign2, 34 | output reg [35:0] zout_Allign2, 35 | output reg [31:0] sout_Allign2, 36 | output reg [1:0] modeout_Allign2, 37 | output reg operationout_Allign2, 38 | output reg NatLogFlagout_Allign2, 39 | output reg [7:0] InsTag_Allign2 40 | ); 41 | 42 | parameter mode_circular =2'b01, 43 | mode_linear =2'b00, 44 | mode_hyperbolic=2'b11; 45 | 46 | parameter no_idle = 2'b00, 47 | allign_idle = 2'b01, 48 | put_idle = 2'b10; 49 | 50 | wire z_sign; 51 | wire [7:0] z_exponent; 52 | wire [26:0] z_mantissa; 53 | 54 | wire c_sign; 55 | wire [7:0] c_exponent; 56 | wire [26:0] c_mantissa; 57 | 58 | assign z_sign = zout_Allign[35]; 59 | assign z_exponent = zout_Allign[34:27] - 127; 60 | assign z_mantissa = {zout_Allign[26:0]}; 61 | 62 | assign c_sign = cout_Allign[35]; 63 | assign c_exponent = cout_Allign[34:27] - 127; 64 | assign c_mantissa = {cout_Allign[26:0]}; 65 | 66 | always @ (posedge clock) 67 | begin 68 | 69 | InsTag_Allign2 <= InsTag_Allign; 70 | idle_Allign2 <= idle_Allign; 71 | modeout_Allign2 <= modeout_Allign; 72 | operationout_Allign2 <= operationout_Allign; 73 | sout_Allign2 <= sout_Allign; 74 | 75 | if (idle_Allign != put_idle) begin 76 | if ($signed(c_exponent) > $signed(z_exponent)) begin 77 | zout_Allign2[35] <= zout_Allign[35]; 78 | zout_Allign2[34:27] <= z_exponent + difference_Allign + 127; 79 | zout_Allign2[26:0] <= z_mantissa >> difference_Allign; 80 | zout_Allign2[0] <= z_mantissa[0] | z_mantissa[1]; 81 | cout_Allign2 <= cout_Allign; 82 | end else if ($signed(c_exponent) <= $signed(z_exponent)) begin 83 | cout_Allign2[35] <= cout_Allign[35]; 84 | cout_Allign2[34:27] <= c_exponent + difference_Allign + 127; 85 | cout_Allign2[26:0] <= c_mantissa >> difference_Allign; 86 | cout_Allign2[0] <= c_mantissa[0] | c_mantissa[1]; 87 | zout_Allign2 <= zout_Allign; 88 | end 89 | end 90 | 91 | else begin 92 | zout_Allign2 <= zout_Allign; 93 | cout_Allign2 <= cout_Allign; 94 | end 95 | end 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/mult_k.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:33:10 02/22/2015 7 | // Design Name: 8 | // Module Name: mult_k 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mult_k( 22 | input [31:0] a_multiplicand, 23 | input [31:0] b_multiplier, 24 | input reset, 25 | input clock, 26 | output [31:0] FinalProduct 27 | ); 28 | 29 | wire idle_Special, idle_Multiply, idle_NormaliseProd; 30 | wire [32:0] aout_Special,bout_Special; 31 | wire [32:0] zout_Special,zout_Multiply,zout_NormaliseProd; 32 | wire [49:0] productout_Multiply, productout_NormaliseProd; 33 | wire [31:0] FinalProduct_Idle1,FinalProduct_Idle2,FinalProduct_Idle3,FinalProduct_Idle4; 34 | 35 | SpecialMult Mult1 ( 36 | .ain_Special(a_multiplicand), 37 | .bin_Special(b_multiplier), 38 | .reset(reset), 39 | .clock(clock), 40 | .idle_Special(idle_Special), 41 | .aout_Special(aout_Special), 42 | .bout_Special(bout_Special), 43 | .zout_Special(zout_Special) 44 | ); 45 | 46 | MultiplyMult Mult2 ( 47 | .aout_Special(aout_Special), 48 | .bout_Special(bout_Special), 49 | .zout_Special(zout_Special), 50 | .idle_Special(idle_Special), 51 | .clock(clock), 52 | .idle_Multiply(idle_Multiply), 53 | .zout_Multiply(zout_Multiply), 54 | .productout_Multiply(productout_Multiply) 55 | ); 56 | 57 | NormaliseProdMult Mult3 ( 58 | .zout_Multiply(zout_Multiply), 59 | .productout_Multiply(productout_Multiply), 60 | .clock(clock), 61 | .idle_Multiply(idle_Multiply), 62 | .idle_NormaliseProd(idle_NormaliseProd), 63 | .zout_NormaliseProd(zout_NormaliseProd), 64 | .productout_NormaliseProd(productout_NormaliseProd) 65 | ); 66 | 67 | Pack_z Mult4 ( 68 | .idle_NormaliseProd(idle_NormaliseProd), 69 | .zout_NormaliseProd(zout_NormaliseProd), 70 | .productout_NormaliseProd(productout_NormaliseProd), 71 | .clock(clock), 72 | .FinalProduct(FinalProduct_Idle1) 73 | ); 74 | 75 | IdleMult Mult5 ( 76 | .FinalProduct(FinalProduct_Idle1), 77 | .clock(clock), 78 | .FinalProductout(FinalProduct_Idle2) 79 | ); 80 | 81 | IdleMult Mult6 ( 82 | .FinalProduct(FinalProduct_Idle2), 83 | .clock(clock), 84 | .FinalProductout(FinalProduct_Idle3) 85 | ); 86 | 87 | IdleMult Mult7 ( 88 | .FinalProduct(FinalProduct_Idle3), 89 | .clock(clock), 90 | .FinalProductout(FinalProduct_Idle4) 91 | ); 92 | 93 | IdleMult Mult8 ( 94 | .FinalProduct(FinalProduct_Idle4), 95 | .clock(clock), 96 | .FinalProductout(FinalProduct) 97 | ); 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/PackAdderProcess.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:31:09 02/22/2015 7 | // Design Name: 8 | // Module Name: PackAdder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PackAdderProcess( 22 | input [31:0] z_postNormaliseSum, 23 | input [3:0] Opcode_NormaliseSum, 24 | input idle_NormaliseSum, 25 | input [31:0] sout_NormaliseSum, 26 | input [27:0] sum_NormaliseSum, 27 | input [7:0] InsTagNormaliseAdder, 28 | input clock, 29 | output reg [31:0] sout_PackSum, 30 | output reg Done = 1'b0, 31 | output reg [31:0] z_postPack, 32 | output reg [3:0] Opcode_Pack, 33 | output reg [7:0] InsTagPack 34 | ); 35 | 36 | parameter no_idle = 1'b0, 37 | put_idle = 1'b1; 38 | 39 | wire s_sign; 40 | wire [7:0] s_exponent; 41 | 42 | assign s_sign = sout_NormaliseSum[31]; 43 | assign s_exponent = sout_NormaliseSum[30:23]; 44 | 45 | parameter sin_cos = 4'd0, 46 | sinh_cosh = 4'd1, 47 | arctan = 4'd2, 48 | arctanh = 4'd3, 49 | exp = 4'd4, 50 | sqr_root = 4'd5, // Pre processed input is given 4'd11 51 | // This requires pre processing. x = (a+1)/2 and y = (a-1)/2 52 | division = 4'd6, 53 | tan = 4'd7, // This is iterative. sin_cos followed by division. 54 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 55 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 56 | hypotenuse = 4'd10, 57 | PreProcess = 4'd11; 58 | 59 | always @ (posedge clock) 60 | begin 61 | 62 | InsTagPack <= InsTagNormaliseAdder; 63 | Opcode_Pack <= Opcode_NormaliseSum; 64 | z_postPack <= z_postNormaliseSum; 65 | 66 | //if (Opcode_NormaliseSum == PreProcess) begin 67 | 68 | Done <= 1'b0; 69 | 70 | if (idle_NormaliseSum != put_idle) begin 71 | sout_PackSum[22:0] <= sum_NormaliseSum[25:3]; 72 | sout_PackSum[30:23] <= s_exponent + 127; 73 | sout_PackSum[31] <= s_sign; 74 | if ($signed(s_exponent) == -126 && sum_NormaliseSum[22] == 0) begin 75 | sout_PackSum[30 : 23] <= 0; 76 | end 77 | 78 | if ($signed(s_exponent) <= -126) begin 79 | sout_PackSum[30 : 23] <= 0; 80 | sout_PackSum[22:0] <= 0; 81 | end 82 | 83 | //if overflow occurs, return inf 84 | if ($signed(s_exponent) > 127) begin 85 | sout_PackSum[22 : 0] <= 0; 86 | sout_PackSum[30 : 23] <= 255; 87 | sout_PackSum[31] <= s_sign; 88 | end 89 | end 90 | 91 | else begin 92 | sout_PackSum <= sout_NormaliseSum; 93 | end 94 | 95 | //end 96 | 97 | if (Opcode_NormaliseSum == sqr_root || Opcode_NormaliseSum == nat_log) begin 98 | Done <= 1'b1; 99 | end 100 | end 101 | 102 | endmodule 103 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/AddProcess.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:20:24 02/22/2015 7 | // Design Name: 8 | // Module Name: Add 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module AddProcess( 22 | input [31:0] z_postAllign, 23 | input [3:0] Opcode_Allign, 24 | input idle_Allign, 25 | input [35:0] cout_Allign, 26 | input [35:0] zout_Allign, 27 | input [31:0] sout_Allign, 28 | input [7:0] InsTagAllign, 29 | input clock, 30 | output reg idle_AddState, 31 | output reg [31:0] sout_AddState, 32 | output reg [27:0] sum_AddState, 33 | output reg [3:0] Opcode_AddState, 34 | output reg [31:0] z_postAddState, 35 | output reg [7:0] InsTagAdder 36 | ); 37 | parameter no_idle = 1'b0, 38 | put_idle = 1'b1; 39 | 40 | wire z_sign; 41 | wire [7:0] z_exponent; 42 | wire [26:0] z_mantissa; 43 | 44 | wire c_sign; 45 | wire [7:0] c_exponent; 46 | wire [26:0] c_mantissa; 47 | 48 | assign z_sign = zout_Allign[35]; 49 | assign z_exponent = zout_Allign[34:27] - 127; 50 | assign z_mantissa = {zout_Allign[26:0]}; 51 | 52 | assign c_sign = cout_Allign[35]; 53 | assign c_exponent = cout_Allign[34:27] - 127; 54 | assign c_mantissa = {cout_Allign[26:0]}; 55 | 56 | parameter sin_cos = 4'd0, 57 | sinh_cosh = 4'd1, 58 | arctan = 4'd2, 59 | arctanh = 4'd3, 60 | exp = 4'd4, 61 | sqr_root = 4'd5, // Pre processed input is given 4'd11 62 | // This requires pre processing. x = (a+1)/2 and y = (a-1)/2 63 | division = 4'd6, 64 | tan = 4'd7, // This is iterative. sin_cos followed by division. 65 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 66 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 67 | hypotenuse = 4'd10, 68 | PreProcess = 4'd11; 69 | 70 | 71 | always @ (posedge clock) 72 | begin 73 | 74 | InsTagAdder <= InsTagAllign; 75 | z_postAddState <= z_postAllign; 76 | Opcode_AddState <= Opcode_Allign; 77 | 78 | //if(Opcode_Allign == PreProcess) begin 79 | 80 | idle_AddState <= idle_Allign; 81 | 82 | if (idle_Allign != put_idle) begin 83 | sout_AddState[30:23] <= c_exponent; 84 | sout_AddState[22:0] <= 0; 85 | if (c_sign == z_sign) begin 86 | sum_AddState <= c_mantissa + z_mantissa; 87 | sout_AddState[31] <= c_sign; 88 | end else begin 89 | if (c_mantissa >= z_mantissa) begin 90 | sum_AddState <= c_mantissa - z_mantissa; 91 | sout_AddState[31] <= c_sign; 92 | end else begin 93 | sum_AddState <= z_mantissa - c_mantissa; 94 | sout_AddState[31] <= z_sign; 95 | end 96 | end 97 | end 98 | 99 | else begin 100 | sout_AddState <= sout_Allign; 101 | sum_AddState <= 0; 102 | end 103 | 104 | //end 105 | end 106 | 107 | endmodule 108 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/FSM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:32:44 02/22/2015 7 | // Design Name: 8 | // Module Name: FSM 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module FSM( 22 | input [31:0] x_FSM, 23 | input [31:0] y_FSM, 24 | input [31:0] z_FSM, 25 | input [31:0] k_FSM, 26 | input reset, 27 | input clock, 28 | input [1:0] mode_FSM, 29 | input operation_FSM, 30 | input NatLogFlagout_Mux, 31 | input [7:0] InsTagMuxOut, 32 | output [1:0] modeout_FSM, 33 | output operationout_FSM, 34 | output NatLogFlagout_FSM, 35 | output [31:0] xout_FSM, 36 | output [31:0] yout_FSM, 37 | output [31:0] zout_FSM, 38 | output [31:0] kout_FSM, 39 | output [31:0] thetaout_FSM, 40 | output [31:0] deltaout_FSM, 41 | output [31:0] kappaout_FSM, 42 | output [7:0] InsTagFSMOut 43 | ); 44 | 45 | wire [7:0] InsTagFSM1Out; 46 | wire [1:0] enable_LUT; 47 | wire [7:0] address; 48 | wire [3:0] state_FSM2; 49 | wire [1:0] mode_FSM1; 50 | wire operation_FSM1; 51 | wire [31:0] x_FSM1,y_FSM1,z_FSM1,k_FSM1,theta_FSM1,kappa_FSM1,delta_FSM1; 52 | wire NatLogFlagout_FSM1; 53 | 54 | FSM_1 FSM1 ( 55 | .x(x_FSM), 56 | .y(y_FSM), 57 | .z(z_FSM), 58 | .k(k_FSM), 59 | .mode(mode_FSM), 60 | .operation(operation_FSM), 61 | .NatLogFlagout_Mux(NatLogFlagout_Mux), 62 | .reset(reset), 63 | .clock(clock), 64 | .InsTagMuxOut(InsTagMuxOut), 65 | .enable_LUT(enable_LUT), 66 | .address(address), 67 | .state_FSM2(state_FSM2), 68 | .x_FSM1(x_FSM1), 69 | .y_FSM1(y_FSM1), 70 | .z_FSM1(z_FSM1), 71 | .k_FSM1(k_FSM1), 72 | .theta_FSM1(theta_FSM1), 73 | .kappa_FSM1(kappa_FSM1), 74 | .delta_FSM1(delta_FSM1), 75 | .mode_FSM1(mode_FSM1), 76 | .operation_FSM1(operation_FSM1), 77 | .NatLogFlagout_FSM1(NatLogFlagout_FSM1), 78 | .InsTagFSM1Out(InsTagFSM1Out) 79 | ); 80 | 81 | FSM_2 FSM2 ( 82 | .x_FSM1(x_FSM1), 83 | .y_FSM1(y_FSM1), 84 | .z_FSM1(z_FSM1), 85 | .k_FSM1(k_FSM1), 86 | .theta_FSM1(theta_FSM1), 87 | .kappa_FSM1(kappa_FSM1), 88 | .delta_FSM1(delta_FSM1), 89 | .mode_FSM1(mode_FSM1), 90 | .operation_FSM1(operation_FSM1), 91 | .NatLogFlagout_FSM1(NatLogFlagout_FSM1), 92 | .reset(reset), 93 | .clock(clock), 94 | .enable_LUT(enable_LUT), 95 | .address(address), 96 | .state_FSM2(state_FSM2), 97 | .InsTagFSM1Out(InsTagFSM1Out), 98 | .x_FSM2(xout_FSM), 99 | .y_FSM2(yout_FSM), 100 | .z_FSM2(zout_FSM), 101 | .k_FSM2(kout_FSM), 102 | .theta_FSM2(thetaout_FSM), 103 | .kappa_FSM2(kappaout_FSM), 104 | .delta_FSM2(deltaout_FSM), 105 | .mode_FSM2(modeout_FSM), 106 | .operation_FSM2(operationout_FSM), 107 | .NatLogFlagout_FSM(NatLogFlagout_FSM), 108 | .InsTagFSMOut(InsTagFSMOut) 109 | ); 110 | 111 | endmodule 112 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Adder_z.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:44:11 02/22/2015 7 | // Design Name: 8 | // Module Name: Adder_z 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Adder_z( 22 | input [31:0] a_adder, 23 | input [31:0] b_adder, 24 | input reset, 25 | input clock, 26 | output [31:0] FinalSum 27 | ); 28 | 29 | wire idle_Special,idle_Allign,idle_AddState,idle_NormaliseSum; 30 | wire [31:0] sout_Special,sout_Allign,sout_AddState,sout_NormaliseSum; 31 | wire [35:0] cout_Special,cout_Allign; 32 | wire [35:0] zout_Special,zout_Allign; 33 | wire [7:0] difference_Special; 34 | wire [27:0] sum_AddState,sum_NormaliseSum; 35 | wire [31:0] FinalSum_Idle1,FinalSum_Idle2,FinalSum_Idle3; 36 | 37 | SpecialAdd Add1 ( 38 | .cin_Special(a_adder), 39 | .zin_Special(b_adder), 40 | .reset(reset), 41 | .clock(clock), 42 | .idle_Special(idle_Special), 43 | .difference_Special(difference_Special), 44 | .cout_Special(cout_Special), 45 | .zout_Special(zout_Special), 46 | .sout_Special(sout_Special) 47 | ); 48 | 49 | AllignAdder Add2 ( 50 | .idle_Special(idle_Special), 51 | .cout_Special(cout_Special), 52 | .zout_Special(zout_Special), 53 | .sout_Special(sout_Special), 54 | .difference_Special(difference_Special), 55 | .clock(clock), 56 | .idle_Allign(idle_Allign), 57 | .cout_Allign(cout_Allign), 58 | .zout_Allign(zout_Allign), 59 | .sout_Allign(sout_Allign) 60 | ); 61 | 62 | Add Add3 ( 63 | .idle_Allign(idle_Allign), 64 | .cout_Allign(cout_Allign), 65 | .zout_Allign(zout_Allign), 66 | .sout_Allign(sout_Allign), 67 | .clock(clock), 68 | .idle_AddState(idle_AddState), 69 | .sout_AddState(sout_AddState), 70 | .sum_AddState(sum_AddState) 71 | ); 72 | 73 | NormaliseAdder Add4 ( 74 | .idle_AddState(idle_AddState), 75 | .sout_AddState(sout_AddState), 76 | .sum_AddState(sum_AddState), 77 | .clock(clock), 78 | .idle_NormaliseSum(idle_NormaliseSum), 79 | .sout_NormaliseSum(sout_NormaliseSum), 80 | .sum_NormaliseSum(sum_NormaliseSum) 81 | ); 82 | 83 | PackAdder Add5 ( 84 | .idle_NormaliseSum(idle_NormaliseSum), 85 | .sout_NormaliseSum(sout_NormaliseSum), 86 | .sum_NormaliseSum(sum_NormaliseSum), 87 | .clock(clock), 88 | .sout_PackSum(FinalSum_Idle1) 89 | ); 90 | 91 | IdleMult Add6 ( 92 | .FinalProduct(FinalSum_Idle1), 93 | .clock(clock), 94 | .FinalProductout(FinalSum_Idle2) 95 | ); 96 | 97 | IdleMult Add7 ( 98 | .FinalProduct(FinalSum_Idle2), 99 | .clock(clock), 100 | .FinalProductout(FinalSum_Idle3) 101 | ); 102 | 103 | IdleMult Add8 ( 104 | .FinalProduct(FinalSum_Idle3), 105 | .clock(clock), 106 | .FinalProductout(FinalSum) 107 | ); 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /Testbench Generation code/Testbench code/test1.py: -------------------------------------------------------------------------------- 1 | import math,sys 2 | from math import pi 3 | def ieee754 (a): 4 | rep = 0 5 | #sign bit 6 | if (a<0): 7 | rep = 1<<31 8 | a = math.fabs(a) 9 | if (a >= 1): 10 | #exponent 11 | exp = int(math.log(a,2)) 12 | rep = rep|((exp+127)<<23) 13 | 14 | #mantissa 15 | temp = a / pow(2,exp) - 1 16 | i = 22 17 | while i>=0: 18 | temp = temp * 2 19 | if temp > 1: 20 | rep = rep | (1<=0: 37 | temp = temp * 2 38 | if temp > 1: 39 | rep = rep | (1<>23 48 | ex = ex - 127 49 | i = 1 50 | p = 22 51 | num = 1.0 52 | #print('%d \n' % (ex)) 53 | while (p != -1) : 54 | i = 1<

>p 56 | #print dig 57 | num += (dig * pow(2,p-23)) 58 | p -= 1 59 | num = num * pow(2,ex) 60 | i = 1<<31 61 | sign = a & i 62 | if (sign) : 63 | num = num * -1 64 | print num 65 | return num 66 | 67 | 68 | #def generate_testbench(value): 69 | 70 | 71 | if __name__ == "__main__": 72 | 73 | time =0; 74 | i = 0; 75 | j = 0; 76 | for time in range(0,100): 77 | i = i+1 78 | j = j+1 79 | if j == 255: 80 | j = 0; 81 | else: 82 | j = j; 83 | if i ==5: 84 | i = 0 85 | else: 86 | i=i 87 | InsTagIn = j 88 | InsTagIn = hex(InsTagIn) 89 | InsTagIn = InsTagIn.split('x') 90 | InsTagIn = InsTagIn[1] 91 | instagin = str("\tInsTagIn = ") 92 | InsTagIn = instagin + "8'h"+str(InsTagIn) + ";" 93 | Opcode = 0 94 | Opcode = hex(Opcode) 95 | Opcode = Opcode.split('x') 96 | Opcode = Opcode[1] 97 | opcode = str("\tOpcode = ") 98 | Opcode = opcode +"4'h"+ str(Opcode) +";" 99 | delay = 20 100 | delay = str(delay) 101 | delay = '#' + delay 102 | x = str(" x_processor= ") 103 | x = delay +x 104 | y = str("\ty_processor= ") 105 | 106 | z = str("\tz_processor= ") 107 | z = delay+z 108 | '''x_processor = 0.01*time 109 | x_processor = float(x_processor) 110 | x_processor = ieee754(x_processor) 111 | x_processor = hex(x_processor) 112 | x_processor = x_processor.split('x') 113 | x_processor = x_processor[1] 114 | x_processor = str(x_processor) 115 | y_processor = 0.5 + 0.01*time 116 | y_processor = float(y_processor) 117 | y_processor = ieee754(y_processor) 118 | y_processor = hex(y_processor) 119 | y_processor = y_processor.split('x') 120 | y_processor = y_processor[1] 121 | y_processor = str(y_processor)''' 122 | x_processor = str(00000000); 123 | y_processor = str(00000000); 124 | z_processor = time*pi/180 125 | z_processor = float(z_processor) 126 | z_processor = ieee754(z_processor) 127 | z_processor = hex(z_processor) 128 | z_processor = z_processor.split('x') 129 | z_processor = z_processor[1] 130 | z_processor = str(z_processor) 131 | x = x+"32'h"+x_processor +";" 132 | y = y+"32'h"+y_processor +";" 133 | z = z+"32'h"+z_processor +";" 134 | print x 135 | print y 136 | print z 137 | print Opcode 138 | print InsTagIn 139 | 140 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/AllignAdderProcess.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:11:24 02/22/2015 7 | // Design Name: 8 | // Module Name: AllignAdder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module AllignAdderProcess( 22 | input [31:0] z_postSpecial, 23 | input [3:0] Opcode_Special, 24 | input idle_Special, 25 | input [35:0] cout_Special, 26 | input [35:0] zout_Special, 27 | input [31:0] sout_Special, 28 | input [7:0] difference_Special, 29 | input [7:0] InsTagSpecial, 30 | input clock, 31 | output reg idle_Allign, 32 | output reg [35:0] cout_Allign, 33 | output reg [35:0] zout_Allign, 34 | output reg [31:0] sout_Allign, 35 | output reg [3:0] Opcode_Allign, 36 | output reg [31:0] z_postAllign, 37 | output reg [7:0] InsTagAllign 38 | ); 39 | 40 | parameter no_idle = 1'b0, 41 | put_idle = 1'b1; 42 | 43 | wire z_sign; 44 | wire [7:0] z_exponent; 45 | wire [26:0] z_mantissa; 46 | 47 | wire c_sign; 48 | wire [7:0] c_exponent; 49 | wire [26:0] c_mantissa; 50 | 51 | assign z_sign = zout_Special[35]; 52 | assign z_exponent = zout_Special[34:27] - 127; 53 | assign z_mantissa = {zout_Special[26:0]}; 54 | 55 | assign c_sign = cout_Special[35]; 56 | assign c_exponent = cout_Special[34:27] - 127; 57 | assign c_mantissa = {cout_Special[26:0]}; 58 | 59 | parameter sin_cos = 4'd0, 60 | sinh_cosh = 4'd1, 61 | arctan = 4'd2, 62 | arctanh = 4'd3, 63 | exp = 4'd4, 64 | sqr_root = 4'd5, // Pre processed input is given 4'd11 65 | // This requires pre processing. x = (a+1)/2 and y = (a-1)/2 66 | division = 4'd6, 67 | tan = 4'd7, // This is iterative. sin_cos followed by division. 68 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 69 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 70 | hypotenuse = 4'd10, 71 | PreProcess = 4'd11; 72 | 73 | 74 | always @ (posedge clock) 75 | begin 76 | 77 | InsTagAllign <= InsTagSpecial; 78 | Opcode_Allign <= Opcode_Special; 79 | z_postAllign <= z_postSpecial; 80 | 81 | //if(Opcode_Special == PreProcess) begin 82 | 83 | idle_Allign <= idle_Special; 84 | sout_Allign <= sout_Special; 85 | 86 | if (idle_Special != put_idle) begin 87 | if ($signed(c_exponent) > $signed(z_exponent)) begin 88 | zout_Allign[35] <= zout_Special[35]; 89 | zout_Allign[34:27] <= z_exponent + difference_Special + 127; 90 | zout_Allign[26:0] <= z_mantissa >> difference_Special; 91 | zout_Allign[0] <= z_mantissa[0] | z_mantissa[1]; 92 | cout_Allign <= cout_Special; 93 | end else if ($signed(c_exponent) <= $signed(z_exponent)) begin 94 | cout_Allign[35] <= cout_Special[35]; 95 | cout_Allign[34:27] <= c_exponent + difference_Special + 127; 96 | cout_Allign[26:0] <= c_mantissa >> difference_Special; 97 | cout_Allign[0] <= c_mantissa[0] | c_mantissa[1]; 98 | zout_Allign <= zout_Special; 99 | end 100 | end 101 | 102 | else begin 103 | zout_Allign <= zout_Special; 104 | cout_Allign <= cout_Special; 105 | end 106 | //end 107 | 108 | end 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/NormaliseProd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:52:15 02/21/2015 7 | // Design Name: 8 | // Module Name: NormaliseProd 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NormaliseProd( 22 | input [35:0] cout_Multiply, 23 | input [35:0] zout_Multiply, 24 | input [31:0] sout_Multiply, 25 | input [49:0] productout_Multiply, 26 | input [1:0] modeout_Multiply, 27 | input operationout_Multiply, 28 | input NatLogFlagout_Multiply, 29 | input [7:0] InsTag_Multiply, 30 | input clock, 31 | input [1:0] idle_Multiply, 32 | output reg [1:0] idle_NormaliseProd, 33 | output reg [35:0] cout_NormaliseProd, 34 | output reg [35:0] zout_NormaliseProd, 35 | output reg [31:0] sout_NormaliseProd, 36 | output reg [1:0] modeout_NormaliseProd, 37 | output reg operationout_NormaliseProd, 38 | output reg NatLogFlagout_NormaliseProd, 39 | output reg [49:0] productout_NormaliseProd, 40 | output reg [7:0] InsTag_NormaliseProd 41 | ); 42 | 43 | parameter mode_circular =2'b01, 44 | mode_linear =2'b00, 45 | mode_hyperbolic=2'b11; 46 | 47 | parameter no_idle = 2'b00, 48 | allign_idle = 2'b01, 49 | put_idle = 2'b10; 50 | 51 | wire z_sign; 52 | wire [7:0] z_exponent; 53 | wire [26:0] z_mantissa; 54 | 55 | assign z_sign = zout_Multiply[35]; 56 | assign z_exponent = zout_Multiply[34:27]; 57 | assign z_mantissa = {zout_Multiply[26:0]}; 58 | 59 | always @ (posedge clock) begin 60 | 61 | InsTag_NormaliseProd <= InsTag_Multiply; 62 | sout_NormaliseProd <= sout_Multiply; 63 | cout_NormaliseProd <= cout_Multiply; 64 | modeout_NormaliseProd <= modeout_Multiply; 65 | operationout_NormaliseProd <= operationout_Multiply; 66 | idle_NormaliseProd <= idle_Multiply; 67 | NatLogFlagout_NormaliseProd <= NatLogFlagout_Multiply; 68 | 69 | if (idle_Multiply == no_idle) begin 70 | 71 | // This case will never arise. This is because for input with exponent less than -12 multiply isn't used. 72 | if ($signed(z_exponent) < -126) begin 73 | zout_NormaliseProd[35] <= z_sign; 74 | zout_NormaliseProd[34:27] <= z_exponent + 1; 75 | zout_NormaliseProd[26:0] <= z_mantissa; 76 | productout_NormaliseProd <= productout_Multiply >> 1; 77 | end 78 | 79 | // This could be problematic. Will have to test for average number of cycles 80 | // Current solution is to hard code for all cases like normalisation in addition. 81 | else if (productout_Multiply[49] == 0) begin 82 | zout_NormaliseProd[35] <= z_sign; 83 | zout_NormaliseProd[34:27] <= z_exponent - 1; 84 | //zout_NormaliseProd[26:0] <= product[48:25]; 85 | zout_NormaliseProd[26:0] <= {productout_Multiply[48:25] , 3'd0}; 86 | productout_NormaliseProd <= productout_Multiply << 1; 87 | end 88 | 89 | else begin 90 | zout_NormaliseProd[35] <= z_sign; 91 | zout_NormaliseProd[34:27] <= z_exponent; 92 | //z_mantissa <= productout_Multiply[49:26]; 93 | zout_NormaliseProd[26:0] <= {productout_Multiply[49:26] , 3'd0}; 94 | productout_NormaliseProd <= productout_Multiply; 95 | end 96 | end 97 | 98 | else begin 99 | zout_NormaliseProd <= zout_Multiply; 100 | end 101 | 102 | end 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/mult_descale_pipeline.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:05:56 02/23/2015 7 | // Design Name: 8 | // Module Name: mult_descale_pipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mult_descale_pipeline( 22 | input [31:0] a_multiplicand, 23 | input [31:0] b_multiplier, 24 | input [31:0] z_scale, 25 | input [7:0] InsTagScaleOut, 26 | input ScaleValid, 27 | input NatLogFlagScaleOut, 28 | input reset, 29 | input clock, 30 | output [31:0] FinalProduct, 31 | output done, 32 | output [7:0] InsTagDescale, 33 | output [31:0] z_out 34 | ); 35 | 36 | wire idle_Special, idle_Multiply, idle_NormaliseProd; 37 | wire [32:0] aout_Special,bout_Special; 38 | wire [32:0] zout_Special,zout_Multiply,zout_NormaliseProd; 39 | wire [49:0] productout_Multiply, productout_NormaliseProd; 40 | wire [7:0] InsTagSpecial,InsTagMultiply,InsTagNormaliseProd; 41 | wire ScaleValidSpecial,ScaleValidMultiply,ScaleValidNormaliseProd; 42 | wire [31:0] z_Special,z_Multiply,z_NormaliseProd; 43 | 44 | SpecialMultDescale Mult1 ( 45 | .ain_Special(a_multiplicand), 46 | .bin_Special(b_multiplier), 47 | .InsTagScaleOut(InsTagScaleOut), 48 | .ScaleValid(ScaleValid), 49 | .NatLogFlagScaleOut(NatLogFlagScaleOut), 50 | .z_scale(z_scale), 51 | .reset(reset), 52 | .clock(clock), 53 | .idle_Special(idle_Special), 54 | .aout_Special(aout_Special), 55 | .bout_Special(bout_Special), 56 | .zout_Special(zout_Special), 57 | .InsTagSpecial(InsTagSpecial), 58 | .ScaleValidSpecial(ScaleValidSpecial), 59 | .z_Special(z_Special) 60 | ); 61 | 62 | MultiplyMultDescale Mult2 ( 63 | .aout_Special(aout_Special), 64 | .bout_Special(bout_Special), 65 | .zout_Special(zout_Special), 66 | .idle_Special(idle_Special), 67 | .InsTagSpecial(InsTagSpecial), 68 | .ScaleValidSpecial(ScaleValidSpecial), 69 | .z_Special(z_Special), 70 | .clock(clock), 71 | .idle_Multiply(idle_Multiply), 72 | .zout_Multiply(zout_Multiply), 73 | .productout_Multiply(productout_Multiply), 74 | .InsTagMultiply(InsTagMultiply), 75 | .ScaleValidMultiply(ScaleValidMultiply), 76 | .z_Multiply(z_Multiply) 77 | ); 78 | 79 | NormaliseProdMultDescale Mult3 ( 80 | .zout_Multiply(zout_Multiply), 81 | .productout_Multiply(productout_Multiply), 82 | .InsTagMultiply(InsTagMultiply), 83 | .ScaleValidMultiply(ScaleValidMultiply), 84 | .z_Multiply(z_Multiply), 85 | .clock(clock), 86 | .idle_Multiply(idle_Multiply), 87 | .idle_NormaliseProd(idle_NormaliseProd), 88 | .zout_NormaliseProd(zout_NormaliseProd), 89 | .productout_NormaliseProd(productout_NormaliseProd), 90 | .InsTagNormaliseProd(InsTagNormaliseProd), 91 | .ScaleValidNormaliseProd(ScaleValidNormaliseProd), 92 | .z_NormaliseProd(z_NormaliseProd) 93 | ); 94 | 95 | Pack_z_descale Mult4 ( 96 | .idle_NormaliseProd(idle_NormaliseProd), 97 | .zout_NormaliseProd(zout_NormaliseProd), 98 | .productout_NormaliseProd(productout_NormaliseProd), 99 | .InsTagNormaliseProd(InsTagNormaliseProd), 100 | .ScaleValidNormaliseProd(ScaleValidNormaliseProd), 101 | .z_NormaliseProd(z_NormaliseProd), 102 | .reset(reset), 103 | .clock(clock), 104 | .done(done), 105 | .FinalProduct(FinalProduct), 106 | .InsTagPack(InsTagDescale), 107 | .z_Descale(z_out) 108 | ); 109 | 110 | 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/HCORDIC_Pipeline.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:03:51 02/23/2015 7 | // Design Name: 8 | // Module Name: HCORDIC_Pipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module HCORDIC_Pipeline( 22 | input [15:0] InstructionPacket, 23 | input clock, 24 | output [31:0] x_out, 25 | output [31:0] y_out, 26 | output [31:0] z_out, 27 | output done 28 | ); 29 | 30 | wire stall,load,ALU_done,converge; 31 | wire operation_Fetch,operation_iter,operation_FSM,operation_Execute; 32 | wire [1:0] mode_Fetch,mode_iter,mode_FSM,mode_Execute; 33 | wire [31:0] x_input, x_iter, xout_Mux, x_scale, xout_FSM; 34 | wire [31:0] y_input, y_iter, yout_Mux, y_scale, yout_FSM; 35 | wire [31:0] z_input, z_iter, zout_Mux, z_scale, zout_FSM; 36 | wire [31:0] k_iter, kout_Mux, k_scale, kout_FSM; 37 | wire [31:0] thetaout_FSM; 38 | wire [31:0] deltaout_FSM; 39 | wire [31:0] kappaout_FSM; 40 | 41 | Fetch v0 ( 42 | .InstructionPacket(InstructionPacket), 43 | .clock(clock), 44 | .stall(stall), 45 | .x_input(x_input), 46 | .y_input(y_input), 47 | .z_input(z_input), 48 | .mode(mode_Fetch), 49 | .operation(operation_Fetch), 50 | .load(load) 51 | ); 52 | 53 | InputMux v1 ( 54 | .x_in(x_input), 55 | .y_in(y_input), 56 | .z_in(z_input), 57 | .x_iter(x_iter), 58 | .y_iter(y_iter), 59 | .z_iter(z_iter), 60 | .k_iter(k_iter), 61 | .load(load), 62 | .ALU_done(ALU_done), 63 | .clock(clock), 64 | .mode_in(mode_Fetch), 65 | .operation_in(operation_Fetch), 66 | .mode_iter(mode_iter), 67 | .operation_iter(operation_iter), 68 | .x_out(xout_Mux), 69 | .y_out(yout_Mux), 70 | .z_out(zout_Mux), 71 | .k_out(kout_Mux), 72 | .x_scale(x_scale), 73 | .y_scale(y_scale), 74 | .z_scale(z_scale), 75 | .k_scale(k_scale), 76 | .modeout_Mux(mode_FSM), 77 | .operationout_Mux(operation_FSM), 78 | .converge(converge), 79 | .stall(stall) 80 | ); 81 | 82 | FSM v3 ( 83 | .x_FSM(xout_Mux), 84 | .y_FSM(yout_Mux), 85 | .z_FSM(zout_Mux), 86 | .k_FSM(kout_Mux), 87 | .clock(clock), 88 | .mode_FSM(mode_FSM), 89 | .operation_FSM(operation_FSM), 90 | .modeout_FSM(mode_Execute), 91 | .operationout_FSM(operation_Execute), 92 | .xout_FSM(xout_FSM), 93 | .yout_FSM(yout_FSM), 94 | .zout_FSM(zout_FSM), 95 | .kout_FSM(kout_FSM), 96 | .thetaout_FSM(thetaout_FSM), 97 | .deltaout_FSM(deltaout_FSM), 98 | .kappaout_FSM(kappaout_FSM) 99 | ); 100 | 101 | ExecutePipeline v4 ( 102 | .X_in(xout_FSM), 103 | .Y_in(yout_FSM), 104 | .Z_in(zout_FSM), 105 | .K_in(kout_FSM), 106 | .kappa_in(kappaout_FSM), 107 | .theta_in(thetaout_FSM), 108 | .delta_in(deltaout_FSM), 109 | .clock(clock), 110 | .operation(operation_Execute), 111 | .mode(mode_Execute), 112 | .X_next(x_iter), 113 | .Y_next(y_iter), 114 | .Z_next(z_iter), 115 | .K_next(k_iter), 116 | .mode_out(mode_iter), 117 | .operation_out(operation_iter), 118 | .ALU_done(ALU_done) 119 | ); 120 | 121 | Descale_pipeline v5 ( 122 | .x_scale(x_scale), 123 | .y_scale(y_scale), 124 | .z_scale(z_scale), 125 | .k_in(k_scale), 126 | .clock(clock), 127 | .x_out(x_out), 128 | .y_out(y_out), 129 | .z_out(z_out), 130 | .done(done) 131 | ); 132 | 133 | endmodule 134 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Fetch_Crude.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:43:45 02/20/2015 7 | // Design Name: 8 | // Module Name: Fetch 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Fetch_Crude( 22 | input [98:0] InstructionPacket, 23 | input clock, 24 | input stall, 25 | output reg [31:0] x_input = 32'h00000000, 26 | output reg [31:0] y_input = 32'h00000000, 27 | output reg [31:0] z_input = 32'h00000000, 28 | output reg [1:0] mode, 29 | output reg operation, 30 | output reg load = 1'b0 31 | ); 32 | 33 | wire [3:0] Opcode; 34 | wire [31:0] x_processor; 35 | wire [31:0] y_processor; 36 | wire [31:0] z_processor; 37 | 38 | assign Opcode = InstructionPacket[98:96]; 39 | assign x_processor = InstructionPacket[31:0]; 40 | assign y_processor = InstructionPacket[63:32]; 41 | assign z_processor = InstructionPacket[95:64]; 42 | 43 | parameter sin_cos = 4'd0, 44 | sinh_cosh = 4'd1, 45 | arctan = 4'd2, 46 | arctanh = 4'd3, 47 | exp = 4'd4, 48 | sqr_root = 4'd5, // This requires pre processing. x = (a+1)/4 and y = (a-1)/4 49 | division = 4'd6, 50 | tan = 4'd7, // This is iterative. sin_cos followed by division. 51 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 52 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 53 | hypotenuse = 4'd10; 54 | 55 | parameter vectoring = 1'b0, 56 | rotation = 1'b1; 57 | 58 | parameter circular = 2'b01, 59 | linear = 2'b00, 60 | hyperbolic = 2'b11; 61 | 62 | always @ (posedge clock) 63 | begin 64 | 65 | if (stall == 1'b0) begin 66 | 67 | case(Opcode) 68 | 69 | sin_cos: 70 | begin 71 | mode <= circular; 72 | operation <= rotation; 73 | x_input <= 32'h3F800000; 74 | y_input <= 32'h00000000; 75 | z_input <= z_processor; 76 | load <= 1'b1; 77 | end 78 | 79 | sinh_cosh: 80 | begin 81 | mode <= hyperbolic; 82 | operation <= rotation; 83 | x_input <= 32'h3F800000; 84 | y_input <= 32'h00000000; 85 | z_input <= z_processor; 86 | load <= 1'b1; 87 | end 88 | 89 | arctan: 90 | begin 91 | mode <= circular; 92 | operation <= vectoring; 93 | x_input <= 32'h3F800000; 94 | y_input <= y_processor; 95 | z_input <= 32'h00000000; 96 | load <= 1'b1; 97 | end 98 | 99 | arctanh: 100 | begin 101 | mode <= hyperbolic; 102 | operation <= vectoring; 103 | x_input <= 32'h3F800000; 104 | y_input <= y_processor; 105 | z_input <= 32'h00000000; 106 | load <= 1'b1; 107 | end 108 | 109 | exp: 110 | begin 111 | mode <= hyperbolic; 112 | operation <= rotation; 113 | x_input <= 32'h3F800000; 114 | y_input <= 32'h3F800000; 115 | z_input <= z_processor; 116 | load <= 1'b1; 117 | end 118 | 119 | sqr_root: 120 | begin 121 | mode <= hyperbolic; 122 | operation <= vectoring; 123 | x_input <= Register_File[x_address]; 124 | y_input <= Register_File[y_address]; 125 | z_input <= 32'h00000000; 126 | load <= 1'b1; 127 | end 128 | 129 | division: 130 | begin 131 | mode <= linear; 132 | operation <= vectoring; 133 | x_input <= x_processor; 134 | y_input <= y_processor; 135 | z_input <= 32'h00000000; 136 | load <= 1'b1; 137 | end 138 | 139 | hypotenuse: 140 | begin 141 | mode <= circular; 142 | operation <= vectoring; 143 | x_input <= x_processor; 144 | y_input <= y_processor; 145 | z_input <= 32'h00000000; 146 | load <= 1'b1; 147 | end 148 | 149 | endcase 150 | 151 | end 152 | 153 | else begin 154 | load <= 1'b0; 155 | end 156 | 157 | 158 | end 159 | 160 | 161 | endmodule 162 | -------------------------------------------------------------------------------- /Testbench Generation code/Testbench Files/test_sin,arctan.py: -------------------------------------------------------------------------------- 1 | import math,sys 2 | from math import pi 3 | def ieee754 (a): 4 | rep = 0 5 | #sign bit 6 | if (a<0): 7 | rep = 1<<31 8 | a = math.fabs(a) 9 | if (a >= 1): 10 | #exponent 11 | exp = int(math.log(a,2)) 12 | rep = rep|((exp+127)<<23) 13 | 14 | #mantissa 15 | temp = a / pow(2,exp) - 1 16 | i = 22 17 | while i>=0: 18 | temp = temp * 2 19 | if temp > 1: 20 | rep = rep | (1<=0: 37 | temp = temp * 2 38 | if temp > 1: 39 | rep = rep | (1<>23 48 | ex = ex - 127 49 | i = 1 50 | p = 22 51 | num = 1.0 52 | #print('%d \n' % (ex)) 53 | while (p != -1) : 54 | i = 1<

>p 56 | #print dig 57 | num += (dig * pow(2,p-23)) 58 | p -= 1 59 | num = num * pow(2,ex) 60 | i = 1<<31 61 | sign = a & i 62 | if (sign) : 63 | num = num * -1 64 | print num 65 | return num 66 | 67 | 68 | #def generate_testbench(value): 69 | def convert2hex_of_xilinx(hex_number,num_of_bits): 70 | hex_number = hex_number.split('x') 71 | hex_number = hex_number[1] 72 | hex_number = str(hex_number) 73 | hex_number = str(num_of_bits)+"'h"+ hex_number +';' 74 | return hex_number 75 | 76 | if __name__ == "__main__": 77 | 78 | time =0; 79 | i = 0; 80 | j = 0; 81 | for time in range(0,100): 82 | i = i+1 83 | j = j+1 84 | if j == 255: 85 | j = 0; 86 | else: 87 | j = j; 88 | if i ==3: 89 | i = 0 90 | elif i==1: 91 | i=i+1 92 | else: 93 | i=i 94 | InsTagIn = j 95 | InsTagIn = hex(InsTagIn) 96 | InsTagIn = InsTagIn.split('x') 97 | InsTagIn = InsTagIn[1] 98 | instagin = str("\tInsTagIn = ") 99 | InsTagIn = instagin + "8'h"+str(InsTagIn) + ";" 100 | Opcode = i 101 | Opcode = hex(Opcode) 102 | Opcode = Opcode.split('x') 103 | Opcode = Opcode[1] 104 | opcode = str("\tOpcode = ") 105 | Opcode = opcode +"4'h"+ str(Opcode) +";" 106 | delay = 20 107 | delay = str(delay) 108 | delay = '#' + delay 109 | x = str(" x_processor= ") 110 | x = delay +x 111 | y = str("\ty_processor= ") 112 | 113 | z = str("\tz_processor= ") 114 | #z = delay+z 115 | '''x_processor = 0.01*time 116 | x_processor = float(x_processor) 117 | x_processor = ieee754(x_processor) 118 | x_processor = hex(x_processor) 119 | x_processor = x_processor.split('x') 120 | x_processor = x_processor[1] 121 | x_processor = str(x_processor)''' 122 | y_processor = 0.5 + 0.01*time 123 | y_float1 = float(y_processor) 124 | y_processor = ieee754(y_float1) 125 | y_processor = hex(y_processor) 126 | y_processor = y_processor.split('x') 127 | y_processor = y_processor[1] 128 | y_processor = str(y_processor) 129 | x_processor = str(00000000); 130 | #y_processor = str(00000000); 131 | z_processor = time*pi/180 132 | z_float1 = float(z_processor) 133 | z_processor = ieee754(z_float1) 134 | z_processor = hex(z_processor) 135 | z_processor = z_processor.split('x') 136 | z_processor = z_processor[1] 137 | z_processor = str(z_processor) 138 | x = x+"32'h"+x_processor +";" 139 | y = y+"32'h"+y_processor +";" 140 | z = z+"32'h"+z_processor +";" 141 | print x 142 | print y 143 | print z 144 | print Opcode 145 | print InsTagIn 146 | '''if i ==0: 147 | sine = math.sin(z_float1) 148 | sine = ieee754(sine) 149 | sine = hex(sine) 150 | sine = convert2hex_of_xilinx(sine,32) 151 | cosine = math.cos(z_float1) 152 | cosine = ieee754(cosine) 153 | cosine = hex(cosine) 154 | cosine = convert2hex_of_xilinx(cosine,32) 155 | print "\t" +"x_out ="+ str(cosine) 156 | print "\t" +"y_out ="+ str(sine) 157 | elif i==2: 158 | atangent = math.atan(y_float1) 159 | atangent = ieee754(atangent) 160 | atangent = hex(atangent) 161 | atangent = convert2hex_of_xilinx(atangent,32) 162 | print "\t" +"z_out = " + str(atangent)''' 163 | 164 | -------------------------------------------------------------------------------- /Testbench Generation code/Testbench Files/test_sin,sinh.py: -------------------------------------------------------------------------------- 1 | import math,sys 2 | from math import pi 3 | def ieee754 (a): 4 | rep = 0 5 | #sign bit 6 | if (a<0): 7 | rep = 1<<31 8 | a = math.fabs(a) 9 | if (a >= 1): 10 | #exponent 11 | exp = int(math.log(a,2)) 12 | rep = rep|((exp+127)<<23) 13 | 14 | #mantissa 15 | temp = a / pow(2,exp) - 1 16 | i = 22 17 | while i>=0: 18 | temp = temp * 2 19 | if temp > 1: 20 | rep = rep | (1<=0: 37 | temp = temp * 2 38 | if temp > 1: 39 | rep = rep | (1<>23 48 | ex = ex - 127 49 | i = 1 50 | p = 22 51 | num = 1.0 52 | #print('%d \n' % (ex)) 53 | while (p != -1) : 54 | i = 1<

>p 56 | #print dig 57 | num += (dig * pow(2,p-23)) 58 | p -= 1 59 | num = num * pow(2,ex) 60 | i = 1<<31 61 | sign = a & i 62 | if (sign) : 63 | num = num * -1 64 | print num 65 | return num 66 | 67 | 68 | #def generate_testbench(value): 69 | def convert2hex_of_xilinx(hex_number,num_of_bits): 70 | hex_number = hex_number.split('x') 71 | hex_number = hex_number[1] 72 | hex_number = str(hex_number) 73 | hex_number = str(num_of_bits)+"'h"+ hex_number +';' 74 | return hex_number 75 | 76 | if __name__ == "__main__": 77 | 78 | time =0; 79 | i = 0; 80 | j = 0; 81 | for time in range(0,100): 82 | i = i+1 83 | j = j+1 84 | if j == 255: 85 | j = 0; 86 | else: 87 | j = j; 88 | if i ==2: 89 | i = 0 90 | else: 91 | i=i 92 | InsTagIn = j 93 | InsTagIn = hex(InsTagIn) 94 | InsTagIn = InsTagIn.split('x') 95 | InsTagIn = InsTagIn[1] 96 | instagin = str("\tInsTagIn = ") 97 | InsTagIn = instagin + "8'h"+str(InsTagIn) + ";" 98 | Opcode = i 99 | Opcode = hex(Opcode) 100 | Opcode = Opcode.split('x') 101 | Opcode = Opcode[1] 102 | opcode = str("\tOpcode = ") 103 | Opcode = opcode +"4'h"+ str(Opcode) +";" 104 | delay = 20 105 | delay = str(delay) 106 | delay = '#' + delay 107 | x = str(" x_processor= ") 108 | x = delay +x 109 | y = str("\ty_processor= ") 110 | 111 | z = str("\tz_processor= ") 112 | #z = delay+z 113 | '''x_processor = 0.01*time 114 | x_processor = float(x_processor) 115 | x_processor = ieee754(x_processor) 116 | x_processor = hex(x_processor) 117 | x_processor = x_processor.split('x') 118 | x_processor = x_processor[1] 119 | x_processor = str(x_processor) 120 | y_processor = 0.5 + 0.01*time 121 | y_processor = float(y_processor) 122 | y_processor = ieee754(y_processor) 123 | y_processor = hex(y_processor) 124 | y_processor = y_processor.split('x') 125 | y_processor = y_processor[1] 126 | y_processor = str(y_processor)''' 127 | x_processor = str(00000000); 128 | y_processor = str(00000000); 129 | z_processor = time*pi/180 130 | z_float1 = float(z_processor) 131 | z_processor = ieee754(z_float1) 132 | z_processor = hex(z_processor) 133 | z_processor = z_processor.split('x') 134 | z_processor = z_processor[1] 135 | z_processor = str(z_processor) 136 | x = x+"32'h"+x_processor +";" 137 | y = y+"32'h"+y_processor +";" 138 | z = z+"32'h"+z_processor +";" 139 | print x 140 | print y 141 | print z 142 | print Opcode 143 | print InsTagIn 144 | '''if i ==0: 145 | sine = math.sin(z_float1) 146 | sine = ieee754(sine) 147 | sine = hex(sine) 148 | sine = convert2hex_of_xilinx(sine,32) 149 | cosine = math.cos(z_float1) 150 | cosine = ieee754(cosine) 151 | cosine = hex(cosine) 152 | cosine = convert2hex_of_xilinx(cosine,32) 153 | print "\t" +"x_out ="+ str(cosine) 154 | print "\t" +"y_out ="+ str(sine) 155 | elif i==1: 156 | sineh = math.sinh(z_float1) 157 | sineh = ieee754(sineh) 158 | sineh = hex(sineh) 159 | sineh = convert2hex_of_xilinx(sineh,32) 160 | cosineh = math.cosh(z_float1) 161 | cosineh = ieee754(cosineh) 162 | cosineh = hex(cosineh) 163 | cosineh = convert2hex_of_xilinx(cosineh,32) 164 | print "\t" +"x_out = "+ str(cosineh) 165 | print "\t" +"y_out = "+ str(sineh)''' 166 | 167 | 168 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Fetch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:43:45 02/20/2015 7 | // Design Name: 8 | // Module Name: Fetch 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Fetch( 22 | input [15:0] InstructionPacket, 23 | input clock, 24 | input stall, 25 | output reg [31:0] x_input = 32'h00000000, 26 | output reg [31:0] y_input = 32'h00000000, 27 | output reg [31:0] z_input = 32'h00000000, 28 | output reg [1:0] mode, 29 | output reg operation, 30 | output reg load = 1'b0 31 | ); 32 | 33 | wire [3:0] Opcode; 34 | wire [3:0] x_address; 35 | wire [3:0] y_address; 36 | wire [3:0] z_address; 37 | 38 | assign Opcode = InstructionPacket[15:12]; 39 | assign x_address = InstructionPacket[11:8]; 40 | assign y_address = InstructionPacket[7:4]; 41 | assign z_address = InstructionPacket[3:0]; 42 | 43 | reg [31:0] Register_File [0:15]; 44 | 45 | parameter sin_cos = 4'd0, 46 | sinh_cosh = 4'd1, 47 | arctan = 4'd2, 48 | arctanh = 4'd3, 49 | exp = 4'd4, 50 | sqr_root = 4'd5, // This requires pre processing. x = (a+1)/4 and y = (a-1)/4 51 | division = 4'd6, 52 | tan = 4'd7, // This is iterative. sin_cos followed by division. 53 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 54 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 55 | hypotenuse = 4'd10; 56 | 57 | parameter vectoring = 1'b0, 58 | rotation = 1'b1; 59 | 60 | 61 | parameter circular = 2'b01, 62 | linear = 2'b00, 63 | hyperbolic = 2'b11; 64 | 65 | initial 66 | begin 67 | $readmemh("test_reg.txt",Register_File,0,15); 68 | end 69 | 70 | 71 | always @ (posedge clock) 72 | begin 73 | 74 | if (stall == 1'b0) begin 75 | 76 | case(Opcode) 77 | 78 | sin_cos: 79 | begin 80 | mode <= circular; 81 | operation <= rotation; 82 | x_input <= 32'h3F800000; 83 | y_input <= 32'h00000000; 84 | z_input <= Register_File[z_address]; 85 | load <= 1'b1; 86 | end 87 | 88 | sinh_cosh: 89 | begin 90 | mode <= hyperbolic; 91 | operation <= rotation; 92 | x_input <= 32'h3F800000; 93 | y_input <= 32'h00000000; 94 | z_input <= Register_File[z_address]; 95 | load <= 1'b1; 96 | end 97 | 98 | arctan: 99 | begin 100 | mode <= circular; 101 | operation <= vectoring; 102 | x_input <= 32'h3F800000; 103 | y_input <= Register_File[y_address]; 104 | z_input <= 32'h00000000; 105 | load <= 1'b1; 106 | end 107 | 108 | arctanh: 109 | begin 110 | mode <= hyperbolic; 111 | operation <= vectoring; 112 | x_input <= 32'h3F800000; 113 | y_input <= Register_File[y_address]; 114 | z_input <= 32'h00000000; 115 | load <= 1'b1; 116 | end 117 | 118 | exp: 119 | begin 120 | mode <= hyperbolic; 121 | operation <= rotation; 122 | x_input <= 32'h3F800000; 123 | y_input <= 32'h3F800000; 124 | z_input <= Register_File[z_address]; 125 | load <= 1'b1; 126 | end 127 | 128 | sqr_root: 129 | begin 130 | mode <= hyperbolic; 131 | operation <= vectoring; 132 | x_input <= Register_File[x_address]; 133 | y_input <= Register_File[y_address]; 134 | z_input <= 32'h00000000; 135 | load <= 1'b1; 136 | end 137 | 138 | division: 139 | begin 140 | mode <= linear; 141 | operation <= vectoring; 142 | x_input <= Register_File[x_address]; 143 | y_input <= Register_File[y_address]; 144 | z_input <= 32'h00000000; 145 | load <= 1'b1; 146 | end 147 | 148 | hypotenuse: 149 | begin 150 | mode <= circular; 151 | operation <= vectoring; 152 | x_input <= Register_File[x_address]; 153 | y_input <= Register_File[y_address]; 154 | z_input <= 32'h00000000; 155 | load <= 1'b1; 156 | end 157 | 158 | endcase 159 | 160 | end 161 | 162 | else begin 163 | load <= 1'b0; 164 | end 165 | 166 | 167 | end 168 | 169 | 170 | endmodule 171 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/PreProcessY.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:04:15 03/13/2015 7 | // Design Name: 8 | // Module Name: PreProcessX 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PreProcessY( 22 | input [31:0] z_preprocess, 23 | input [3:0] Opcode, 24 | input [31:0] b_adder, 25 | input [7:0] InsTagIn, 26 | input clock, 27 | output [31:0] FinalSum, 28 | output Done, 29 | output [31:0] z_postprocess, 30 | output [3:0] Opcode_out, 31 | output [7:0] InsTagOut 32 | ); 33 | 34 | reg [31:0] a_adder_reg = 32'hbf800000; 35 | wire [31:0] a_adder; 36 | 37 | assign a_adder = a_adder_reg; 38 | 39 | wire idle_Special,idle_Allign,idle_AddState,idle_NormaliseSum; 40 | wire [3:0] Opcode_Special,Opcode_Allign,Opcode_AddState,Opcode_NormaliseSum; 41 | wire [31:0] z_postSpecial,z_postAllign,z_postAddState,z_postNormaliseSum; 42 | wire [31:0] sout_Special,sout_Allign,sout_AddState,sout_NormaliseSum; 43 | wire [35:0] cout_Special,cout_Allign; 44 | wire [35:0] zout_Special,zout_Allign; 45 | wire [7:0] difference_Special; 46 | wire [27:0] sum_AddState,sum_NormaliseSum; 47 | wire [31:0] FinalSum_Idle1,FinalSum_Idle2,FinalSum_Idle3; 48 | wire [7:0] InsTagSpecial,InsTagAllign,InsTagAdder,InsTagNormaliseAdder; 49 | 50 | SpecialAddProcess Add1 ( 51 | .z_preSpecial(z_preprocess), 52 | .Opcode(Opcode), 53 | .cin_Special(a_adder), 54 | .zin_Special(b_adder), 55 | .InsTagIn(InsTagIn), 56 | .clock(clock), 57 | .idle_Special(idle_Special), 58 | .difference_Special(difference_Special), 59 | .cout_Special(cout_Special), 60 | .zout_Special(zout_Special), 61 | .sout_Special(sout_Special), 62 | .Opcode_Special(Opcode_Special), 63 | .z_postSpecial(z_postSpecial), 64 | .InsTagSpecial(InsTagSpecial) 65 | ); 66 | 67 | AllignAdderProcess Add2 ( 68 | .z_postSpecial(z_postSpecial), 69 | .Opcode_Special(Opcode_Special), 70 | .idle_Special(idle_Special), 71 | .cout_Special(cout_Special), 72 | .zout_Special(zout_Special), 73 | .sout_Special(sout_Special), 74 | .difference_Special(difference_Special), 75 | .InsTagSpecial(InsTagSpecial), 76 | .clock(clock), 77 | .idle_Allign(idle_Allign), 78 | .cout_Allign(cout_Allign), 79 | .zout_Allign(zout_Allign), 80 | .sout_Allign(sout_Allign), 81 | .Opcode_Allign(Opcode_Allign), 82 | .z_postAllign(z_postAllign), 83 | .InsTagAllign(InsTagAllign) 84 | ); 85 | 86 | AddProcess Add3 ( 87 | .z_postAllign(z_postAllign), 88 | .Opcode_Allign(Opcode_Allign), 89 | .idle_Allign(idle_Allign), 90 | .cout_Allign(cout_Allign), 91 | .zout_Allign(zout_Allign), 92 | .sout_Allign(sout_Allign), 93 | .InsTagAllign(InsTagAllign), 94 | .clock(clock), 95 | .idle_AddState(idle_AddState), 96 | .sout_AddState(sout_AddState), 97 | .sum_AddState(sum_AddState), 98 | .Opcode_AddState(Opcode_AddState), 99 | .z_postAddState(z_postAddState), 100 | .InsTagAdder(InsTagAdder) 101 | ); 102 | 103 | NormaliseAdderProcess Add4 ( 104 | .z_postAddState(z_postAddState), 105 | .Opcode_AddState(Opcode_AddState), 106 | .idle_AddState(idle_AddState), 107 | .sout_AddState(sout_AddState), 108 | .sum_AddState(sum_AddState), 109 | .InsTagAdder(InsTagAdder), 110 | .clock(clock), 111 | .idle_NormaliseSum(idle_NormaliseSum), 112 | .sout_NormaliseSum(sout_NormaliseSum), 113 | .sum_NormaliseSum(sum_NormaliseSum), 114 | .Opcode_NormaliseSum(Opcode_NormaliseSum), 115 | .z_postNormaliseSum(z_postNormaliseSum), 116 | .InsTagNormaliseAdder(InsTagNormaliseAdder) 117 | ); 118 | 119 | PackAdderProcess Add5 ( 120 | .z_postNormaliseSum(z_postNormaliseSum), 121 | .Opcode_NormaliseSum(Opcode_NormaliseSum), 122 | .idle_NormaliseSum(idle_NormaliseSum), 123 | .sout_NormaliseSum(sout_NormaliseSum), 124 | .sum_NormaliseSum(sum_NormaliseSum), 125 | .InsTagNormaliseAdder(InsTagNormaliseAdder), 126 | .clock(clock), 127 | .sout_PackSum(FinalSum), 128 | .Done(Done), 129 | .z_postPack(z_postprocess), 130 | .Opcode_Pack(Opcode_out), 131 | .InsTagPack(InsTagOut) 132 | ); 133 | 134 | endmodule -------------------------------------------------------------------------------- /HCORDIC_Verilog/PreProcessX.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:04:15 03/13/2015 7 | // Design Name: 8 | // Module Name: PreProcessX 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PreProcessX( 22 | input [31:0] z_preprocess, 23 | input [3:0] Opcode, 24 | input [31:0] b_adder, 25 | input [7:0] InsTagIn, 26 | input clock, 27 | output [31:0] FinalSum, 28 | output Done, 29 | output [31:0] z_postprocess, 30 | output [3:0] Opcode_out, 31 | output [7:0] InsTagOut 32 | ); 33 | 34 | reg [31:0] a_adder_reg = 32'h3f800000; 35 | wire [31:0] a_adder; 36 | 37 | assign a_adder = a_adder_reg; 38 | 39 | wire idle_Special,idle_Allign,idle_AddState,idle_NormaliseSum; 40 | wire [3:0] Opcode_Special,Opcode_Allign,Opcode_AddState,Opcode_NormaliseSum; 41 | wire [31:0] z_postSpecial,z_postAllign,z_postAddState,z_postNormaliseSum; 42 | wire [31:0] sout_Special,sout_Allign,sout_AddState,sout_NormaliseSum; 43 | wire [35:0] cout_Special,cout_Allign; 44 | wire [35:0] zout_Special,zout_Allign; 45 | wire [7:0] difference_Special; 46 | wire [27:0] sum_AddState,sum_NormaliseSum; 47 | wire [31:0] FinalSum_Idle1,FinalSum_Idle2,FinalSum_Idle3; 48 | wire [7:0] InsTagSpecial,InsTagAllign,InsTagAdder,InsTagNormaliseAdder; 49 | 50 | SpecialAddProcess Add1 ( 51 | .z_preSpecial(z_preprocess), 52 | .Opcode(Opcode), 53 | .cin_Special(a_adder), 54 | .zin_Special(b_adder), 55 | .InsTagIn(InsTagIn), 56 | .clock(clock), 57 | .idle_Special(idle_Special), 58 | .difference_Special(difference_Special), 59 | .cout_Special(cout_Special), 60 | .zout_Special(zout_Special), 61 | .sout_Special(sout_Special), 62 | .Opcode_Special(Opcode_Special), 63 | .z_postSpecial(z_postSpecial), 64 | .InsTagSpecial(InsTagSpecial) 65 | ); 66 | 67 | AllignAdderProcess Add2 ( 68 | .z_postSpecial(z_postSpecial), 69 | .Opcode_Special(Opcode_Special), 70 | .idle_Special(idle_Special), 71 | .cout_Special(cout_Special), 72 | .zout_Special(zout_Special), 73 | .sout_Special(sout_Special), 74 | .difference_Special(difference_Special), 75 | .InsTagSpecial(InsTagSpecial), 76 | .clock(clock), 77 | .idle_Allign(idle_Allign), 78 | .cout_Allign(cout_Allign), 79 | .zout_Allign(zout_Allign), 80 | .sout_Allign(sout_Allign), 81 | .Opcode_Allign(Opcode_Allign), 82 | .z_postAllign(z_postAllign), 83 | .InsTagAllign(InsTagAllign) 84 | ); 85 | 86 | AddProcess Add3 ( 87 | .z_postAllign(z_postAllign), 88 | .Opcode_Allign(Opcode_Allign), 89 | .idle_Allign(idle_Allign), 90 | .cout_Allign(cout_Allign), 91 | .zout_Allign(zout_Allign), 92 | .sout_Allign(sout_Allign), 93 | .InsTagAllign(InsTagAllign), 94 | .clock(clock), 95 | .idle_AddState(idle_AddState), 96 | .sout_AddState(sout_AddState), 97 | .sum_AddState(sum_AddState), 98 | .Opcode_AddState(Opcode_AddState), 99 | .z_postAddState(z_postAddState), 100 | .InsTagAdder(InsTagAdder) 101 | ); 102 | 103 | NormaliseAdderProcess Add4 ( 104 | .z_postAddState(z_postAddState), 105 | .Opcode_AddState(Opcode_AddState), 106 | .idle_AddState(idle_AddState), 107 | .sout_AddState(sout_AddState), 108 | .sum_AddState(sum_AddState), 109 | .InsTagAdder(InsTagAdder), 110 | .clock(clock), 111 | .idle_NormaliseSum(idle_NormaliseSum), 112 | .sout_NormaliseSum(sout_NormaliseSum), 113 | .sum_NormaliseSum(sum_NormaliseSum), 114 | .Opcode_NormaliseSum(Opcode_NormaliseSum), 115 | .z_postNormaliseSum(z_postNormaliseSum), 116 | .InsTagNormaliseAdder(InsTagNormaliseAdder) 117 | ); 118 | 119 | PackAdderProcess Add5 ( 120 | .z_postNormaliseSum(z_postNormaliseSum), 121 | .Opcode_NormaliseSum(Opcode_NormaliseSum), 122 | .idle_NormaliseSum(idle_NormaliseSum), 123 | .sout_NormaliseSum(sout_NormaliseSum), 124 | .sum_NormaliseSum(sum_NormaliseSum), 125 | .InsTagNormaliseAdder(InsTagNormaliseAdder), 126 | .clock(clock), 127 | .sout_PackSum(FinalSum), 128 | .Done(Done), 129 | .z_postPack(z_postprocess), 130 | .Opcode_Pack(Opcode_out), 131 | .InsTagPack(InsTagOut) 132 | ); 133 | 134 | endmodule 135 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/InputMux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:40:25 11/02/2014 7 | // Design Name: 8 | // Module Name: InputMux 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module InputMux( 22 | input [31:0] x_in, 23 | input [31:0] y_in, 24 | input [31:0] z_in, 25 | input [31:0] x_iter, 26 | input [31:0] y_iter, 27 | input [31:0] z_iter, 28 | input [31:0] k_iter, 29 | input load, 30 | input ALU_done, 31 | input reset, 32 | input clock, 33 | input [1:0] mode_in, 34 | input operation_in, 35 | input NatLogFlag, 36 | input [1:0] mode_iter, 37 | input operation_iter, 38 | input NatLogFlag_iter, 39 | input [7:0] InsTagFetchOut, 40 | input [7:0] InsTag_iter, 41 | output reg [31:0] x_out, 42 | output reg [31:0] y_out, 43 | output reg [31:0] z_out, 44 | output reg [31:0] k_out, 45 | output reg [31:0] x_scale, 46 | output reg [31:0] y_scale, 47 | output reg [31:0] z_scale, 48 | output reg [31:0] k_scale, 49 | output reg [1:0] modeout_Mux, 50 | output reg operationout_Mux, 51 | output reg NatLogFlagout_Mux = 1'b0, 52 | output reg converge, 53 | output reg stall = 1'b0, 54 | output reg [7:0] InsTagMuxOut, 55 | output reg [7:0] InsTagScaleOut, 56 | output reg NatLogFlagScaleOut, 57 | output reg ScaleValid = 1'b0 58 | ); 59 | 60 | reg [7:0] exponent, exponentbar; 61 | 62 | parameter rotation = 1'b1, 63 | vectoring = 1'b0; 64 | 65 | parameter mode_circular = 2'b01, 66 | mode_linear = 2'b00, 67 | mode_hyperbolic = 2'b11; 68 | 69 | always @ (*) 70 | begin 71 | case (operation_iter) 72 | rotation : exponent <= 8'b01111111 - z_iter[30:23]; 73 | vectoring : exponent <= y_iter[30:23] - x_iter[30:23]; 74 | default : exponent <= y_iter[30:23] - x_iter[30:23]; 75 | endcase 76 | exponentbar <= ~exponent + 8'b00000001 ;//Change Ankit 77 | end 78 | 79 | always @ ( posedge clock) 80 | begin 81 | 82 | if (reset == 1'b1) begin 83 | stall <= 1'b0; 84 | ScaleValid <= 1'b0; 85 | NatLogFlagout_Mux <= 1'b0; 86 | end 87 | 88 | else begin 89 | if((ALU_done == 1'b1)) 90 | begin 91 | if (!((operation_iter==rotation && mode_iter !=mode_linear && z_iter[30:23] <= 8'b00000000)||(operation_iter==vectoring && ((exponentbar[7] == 1'b0 && exponentbar >= 8'b00001110 && ((mode_iter == 2'b11)|| (mode_iter==2'b01)))||(exponentbar[7] == 1'b0 && exponentbar >= 8'b00001111) || y_iter[30:23] == 8'b0)))) 92 | //if (!((operation_iter==rotation && mode_iter !=mode_linear && z_iter[30:23] <= 8'b00000000)||(operation_iter==vectoring && ((exponentbar[7] == 1'b0 && exponentbar >= 8'b00001111) || y_iter[30:23] == 8'b0)))) // Change Ankit - 31-March 93 | //if (!((operation_iter==rotation && mode_iter !=mode_linear && z_iter[30:23] <= 8'b00000000)||(operation_iter==vectoring && exponentbar[7] == 1'b0 && exponentbar >= 8'b00001111))) 94 | begin 95 | x_out <= x_iter; 96 | y_out <= y_iter; 97 | z_out <= z_iter; 98 | k_out <= k_iter; 99 | stall <= 1'b1; 100 | modeout_Mux <= mode_iter; 101 | operationout_Mux <= operation_iter; 102 | InsTagMuxOut <= InsTag_iter; 103 | ScaleValid <= 1'b0; 104 | NatLogFlagout_Mux <= NatLogFlag_iter; 105 | end 106 | else 107 | begin 108 | x_scale <= x_iter; 109 | y_scale <= y_iter; 110 | z_scale <= z_iter; 111 | k_scale <= k_iter; 112 | InsTagScaleOut <= InsTag_iter; 113 | ScaleValid <= 1'b1; 114 | converge <= 1'b1; 115 | stall <= 1'b0; 116 | NatLogFlagScaleOut <= NatLogFlag; 117 | 118 | x_out <= x_in; 119 | y_out <= y_in; 120 | z_out <= z_in; 121 | k_out <= 32'h3f800000; 122 | modeout_Mux <= mode_in; 123 | operationout_Mux <= operation_in; 124 | InsTagMuxOut <= InsTagFetchOut; 125 | NatLogFlagout_Mux <= NatLogFlag; 126 | end 127 | end 128 | 129 | else if ((load == 1'b1)) 130 | begin 131 | x_out <= x_in; 132 | y_out <= y_in; 133 | z_out <= z_in; 134 | k_out <= 32'h3f800000; 135 | modeout_Mux <= mode_in; 136 | operationout_Mux <= operation_in; 137 | InsTagMuxOut <= InsTagFetchOut; 138 | ScaleValid <= 1'b0; 139 | NatLogFlagout_Mux <= NatLogFlag; 140 | end 141 | 142 | end 143 | 144 | end 145 | 146 | endmodule 147 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/SpecialMult.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:36:52 02/22/2015 7 | // Design Name: 8 | // Module Name: SpecialMult 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SpecialMult( 22 | input [31:0] ain_Special, 23 | input [31:0] bin_Special, 24 | input reset, 25 | input clock, 26 | output reg idle_Special = 1'b0, 27 | output reg [32:0] aout_Special, 28 | output reg [32:0] bout_Special, 29 | output reg [32:0] zout_Special 30 | ); 31 | 32 | wire a_sign; 33 | wire [7:0] a_exponent; 34 | wire [23:0] a_mantissa; 35 | 36 | wire b_sign; 37 | wire [7:0] b_exponent; 38 | wire [23:0] b_mantissa; 39 | 40 | assign a_sign = ain_Special[31]; 41 | assign a_exponent = {ain_Special[30:23] - 127}; 42 | assign a_mantissa = {1'b0, ain_Special[22:0]}; 43 | 44 | assign b_sign = {bin_Special[31]}; 45 | assign b_exponent = {bin_Special[30:23] - 127}; 46 | assign b_mantissa = {1'b0, bin_Special[22:0]}; 47 | 48 | parameter no_idle = 1'b0, 49 | put_idle = 1'b1; 50 | 51 | always @ (posedge clock) 52 | begin 53 | 54 | if(reset == 1'b1) begin 55 | idle_Special <= 1'b0; 56 | end 57 | 58 | else begin 59 | //if a is NaN or b is NaN return NaN 60 | if ((a_exponent == 128 && a_mantissa != 0) || (b_exponent == 128 && b_mantissa != 0)) begin 61 | idle_Special <= put_idle; 62 | aout_Special <= {a_sign,a_exponent+127,a_mantissa}; 63 | bout_Special <= {b_sign,b_exponent+127,b_mantissa}; 64 | zout_Special <= {1'b1,8'd255,1'b1,23'd0}; 65 | //if a is inf return inf 66 | end else if (a_exponent == 128) begin 67 | idle_Special <= put_idle; 68 | //if b is zero return NaN 69 | if ($signed(b_exponent == -127) && (b_mantissa == 0)) begin 70 | idle_Special <= put_idle; 71 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 72 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 73 | zout_Special <= {1'b1,8'd255,1'b1,23'd0}; 74 | end 75 | else begin 76 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 77 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 78 | zout_Special <= {a_sign ^ b_sign,8'd255,24'd0}; 79 | end 80 | //if b is inf return inf 81 | end else if (b_exponent == 128) begin 82 | idle_Special <= put_idle; 83 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 84 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 85 | zout_Special <= {a_sign ^ b_sign,8'd255,24'd0}; 86 | //if a is zero return zero 87 | end else if (($signed(a_exponent) == -127) && (a_mantissa == 0)) begin 88 | idle_Special <= put_idle; 89 | aout_Special[32] <= a_sign; 90 | aout_Special[31:24] <= a_exponent+127; 91 | aout_Special[23] <= 1'b1; 92 | aout_Special[22:0] <= a_mantissa[22:0]; 93 | bout_Special[32] <= b_sign; 94 | bout_Special[31:24] <= b_exponent+127; 95 | bout_Special[23] <= 1'b1; 96 | bout_Special[22:0] <= b_mantissa[22:0]; 97 | zout_Special <= {1'b0,8'd0,24'd0}; 98 | //if b is zero return zero 99 | end else if (($signed(b_exponent) == -127) && (b_mantissa == 0)) begin 100 | aout_Special[32] <= a_sign; 101 | aout_Special[31:24] <= a_exponent+127; 102 | aout_Special[23] <= 1'b1; 103 | aout_Special[22:0] <= a_mantissa[22:0]; 104 | bout_Special[32] <= b_sign; 105 | bout_Special[31:24] <= b_exponent+127; 106 | bout_Special[23] <= 1'b1; 107 | bout_Special[22:0] <= b_mantissa[22:0]; 108 | zout_Special <= {1'b0,8'd0,24'd0}; 109 | idle_Special <= put_idle; 110 | end else begin 111 | //Denormalised Number 112 | zout_Special <= 0; 113 | idle_Special <= no_idle; 114 | if ($signed(a_exponent) == -127) begin 115 | aout_Special <= {a_sign,-126,a_mantissa}; 116 | end else begin 117 | aout_Special[32] <= a_sign; 118 | aout_Special[31:24] <= a_exponent+127; 119 | aout_Special[23] <= 1'b1; 120 | aout_Special[22:0] <= a_mantissa[22:0]; 121 | end 122 | //Denormalised Number 123 | if ($signed(b_exponent) == -127) begin 124 | bout_Special <= {b_sign,-126,b_mantissa}; 125 | end else begin 126 | bout_Special[32] <= b_sign; 127 | bout_Special[31:24] <= b_exponent+127; 128 | bout_Special[23] <= 1'b1; 129 | bout_Special[22:0] <= b_mantissa[22:0]; 130 | end 131 | end 132 | end 133 | end 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/SpecialAdd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:46:09 02/22/2015 7 | // Design Name: 8 | // Module Name: SpecialAdd 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SpecialAdd( 22 | input [31:0] cin_Special, 23 | input [31:0] zin_Special, 24 | input reset, 25 | input clock, 26 | output reg idle_Special = 1'b0, 27 | output reg [7:0] difference_Special, 28 | output reg [35:0] cout_Special, 29 | output reg [35:0] zout_Special, 30 | output reg [31:0] sout_Special 31 | ); 32 | 33 | wire z_sign; 34 | wire [7:0] z_exponent; 35 | wire [26:0] z_mantissa; 36 | 37 | wire c_sign; 38 | wire [7:0] c_exponent; 39 | wire [26:0] c_mantissa; 40 | 41 | assign c_sign = cin_Special[31]; 42 | assign c_exponent = {cin_Special[30:23] - 127}; 43 | assign c_mantissa = {cin_Special[22:0],3'd0}; 44 | 45 | assign z_sign = {zin_Special[31]}; 46 | assign z_exponent = {zin_Special[30:23] - 127}; 47 | assign z_mantissa = {zin_Special[22:0],3'd0}; 48 | 49 | parameter no_idle = 1'b0, 50 | put_idle = 1'b1; 51 | 52 | always @ (posedge clock) 53 | begin 54 | 55 | if (reset == 1'b1) begin 56 | idle_Special <= 1'b0; 57 | end 58 | 59 | else begin 60 | if ($signed(z_exponent) > $signed(c_exponent)) begin 61 | difference_Special <= z_exponent - c_exponent; 62 | end 63 | else if ($signed(z_exponent) <= $signed(c_exponent)) begin 64 | difference_Special <= c_exponent - z_exponent; 65 | end 66 | 67 | // Most of the special cases will never occur except the case where one input is zero. 68 | // The HCORDIC module will not receive NaN and inf at input stage. 69 | //if c is NaN or z is NaN return NaN 70 | if ((c_exponent == 128 && c_mantissa != 0) || (z_exponent == 128 && z_mantissa != 0)) begin 71 | sout_Special[31] <= 1; 72 | sout_Special[30:23] <= 255; 73 | sout_Special[22] <= 1; 74 | sout_Special[21:0] <= 0; 75 | zout_Special <= zin_Special; 76 | cout_Special <= cin_Special; 77 | idle_Special <= put_idle; 78 | //if c is inf return inf 79 | end else if (c_exponent == 128) begin 80 | sout_Special[31] <= c_sign; 81 | sout_Special[30:23] <= 255; 82 | sout_Special[22:0] <= 0; 83 | zout_Special <= zin_Special; 84 | cout_Special <= cin_Special; 85 | idle_Special <= put_idle; 86 | //if z is inf return inf 87 | end else if (z_exponent == 128) begin 88 | sout_Special[31] <= z_sign; 89 | sout_Special[30:23] <= 255; 90 | sout_Special[22:0] <= 0; 91 | zout_Special <= zin_Special; 92 | cout_Special <= cin_Special; 93 | idle_Special <= put_idle; 94 | //if c is zero return z 95 | end else if ((($signed(c_exponent) == -127) && (c_mantissa == 0)) && (($signed(z_exponent) == -127) && (z_mantissa == 0))) begin 96 | sout_Special[31] <= c_sign & z_sign; 97 | sout_Special[30:23] <= z_exponent[7:0] + 127; 98 | sout_Special[22:0] <= z_mantissa[26:3]; 99 | zout_Special <= zin_Special; 100 | cout_Special <= cin_Special; 101 | idle_Special <= put_idle; 102 | //if c is zero return z 103 | end else if (($signed(c_exponent) == -127) && (c_mantissa == 0)) begin 104 | sout_Special[31] <= z_sign; 105 | sout_Special[30:23] <= z_exponent[7:0] + 127; 106 | sout_Special[22:0] <= z_mantissa[26:3]; 107 | zout_Special <= zin_Special; 108 | cout_Special <= cin_Special; 109 | idle_Special <= put_idle; 110 | //if z is zero return c 111 | end else if (($signed(z_exponent) == -127) && (z_mantissa == 0)) begin 112 | sout_Special[31] <= c_sign; 113 | sout_Special[30:23] <= c_exponent[7:0] + 127; 114 | sout_Special[22:0] <= c_mantissa[26:3]; 115 | zout_Special <= zin_Special; 116 | cout_Special <= cin_Special; 117 | idle_Special <= put_idle; 118 | end else begin 119 | sout_Special <= 0; 120 | //Denormalised Number 121 | if ($signed(c_exponent) == -127) begin 122 | cout_Special[34:27] <= -126; 123 | cout_Special[35] <= c_sign; 124 | cout_Special[26:0] <= c_mantissa; 125 | end else begin 126 | cout_Special[34:27] <= c_exponent + 127; 127 | cout_Special[35] <= c_sign; 128 | cout_Special[26] <= 1; 129 | cout_Special[25:0] <= c_mantissa[25:0]; 130 | idle_Special <= no_idle; 131 | end 132 | //Denormalised Number 133 | if ($signed(z_exponent) == -127) begin 134 | zout_Special[35] <= z_sign; 135 | zout_Special[34:27] <= -126; 136 | zout_Special[26:0] <= z_mantissa; 137 | end else begin 138 | zout_Special[35] <= z_sign; 139 | zout_Special[34:27] <= z_exponent + 127; 140 | zout_Special[25:0] <= z_mantissa[25:0]; 141 | zout_Special[26] <= 1; 142 | idle_Special <= no_idle; 143 | end 144 | end 145 | end 146 | end 147 | 148 | endmodule 149 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/SpecialMultDescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:36:52 02/22/2015 7 | // Design Name: 8 | // Module Name: SpecialMult 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SpecialMultDescale( 22 | input [31:0] ain_Special, 23 | input [31:0] bin_Special, 24 | input [7:0] InsTagScaleOut, 25 | input ScaleValid, 26 | input NatLogFlagScaleOut, 27 | input [31:0] z_scale, 28 | input reset, 29 | input clock, 30 | output reg idle_Special = 1'b0, 31 | output reg [32:0] aout_Special, 32 | output reg [32:0] bout_Special, 33 | output reg [32:0] zout_Special, 34 | output reg [7:0] InsTagSpecial, 35 | output reg ScaleValidSpecial, 36 | output reg [31:0] z_Special 37 | ); 38 | 39 | wire a_sign; 40 | wire [7:0] a_exponent; 41 | wire [23:0] a_mantissa; 42 | 43 | wire b_sign; 44 | wire [7:0] b_exponent; 45 | wire [23:0] b_mantissa; 46 | 47 | assign a_sign = ain_Special[31]; 48 | assign a_exponent = {ain_Special[30:23] - 127}; 49 | assign a_mantissa = {1'b0, ain_Special[22:0]}; 50 | 51 | assign b_sign = {bin_Special[31]}; 52 | assign b_exponent = {bin_Special[30:23] - 127}; 53 | assign b_mantissa = {1'b0, bin_Special[22:0]}; 54 | 55 | parameter no_idle = 1'b0, 56 | put_idle = 1'b1; 57 | 58 | always @ (posedge clock) 59 | begin 60 | 61 | if (reset == 1'b1) begin 62 | idle_Special <= 1'b0; 63 | end 64 | 65 | else begin 66 | 67 | if (NatLogFlagScaleOut == 1'b1) begin 68 | z_Special[30:23] <= z_scale[30:23] + 8'h01; 69 | z_Special[31] <= z_scale[31]; 70 | z_Special[22:0] <= z_scale[22:0]; 71 | end 72 | else begin 73 | z_Special <= z_scale; 74 | end 75 | 76 | ScaleValidSpecial <= ScaleValid; 77 | InsTagSpecial <= InsTagScaleOut; 78 | 79 | //if a is NaN or b is NaN return NaN 80 | if ((a_exponent == 128 && a_mantissa != 0) || (b_exponent == 128 && b_mantissa != 0)) begin 81 | idle_Special <= put_idle; 82 | aout_Special <= {a_sign,a_exponent+127,a_mantissa}; 83 | bout_Special <= {b_sign,b_exponent+127,b_mantissa}; 84 | zout_Special <= {1'b1,8'd255,1'b1,23'd0}; 85 | //if a is inf return inf 86 | end else if (a_exponent == 128) begin 87 | idle_Special <= put_idle; 88 | //if b is zero return NaN 89 | if ($signed(b_exponent == -127) && (b_mantissa == 0)) begin 90 | idle_Special <= put_idle; 91 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 92 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 93 | zout_Special <= {1'b1,8'd255,1'b1,23'd0}; 94 | end 95 | else begin 96 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 97 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 98 | zout_Special <= {a_sign ^ b_sign,8'd255,24'd0}; 99 | end 100 | //if b is inf return inf 101 | end else if (b_exponent == 128) begin 102 | idle_Special <= put_idle; 103 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 104 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 105 | zout_Special <= {a_sign ^ b_sign,8'd255,24'd0}; 106 | //if a is zero return zero 107 | end else if (($signed(a_exponent) == -127) && (a_mantissa == 0)) begin 108 | idle_Special <= put_idle; 109 | aout_Special[32] <= a_sign; 110 | aout_Special[31:24] <= a_exponent+127; 111 | aout_Special[23] <= 1'b1; 112 | aout_Special[22:0] <= a_mantissa[22:0]; 113 | bout_Special[32] <= b_sign; 114 | bout_Special[31:24] <= b_exponent+127; 115 | bout_Special[23] <= 1'b1; 116 | bout_Special[22:0] <= b_mantissa[22:0]; 117 | zout_Special <= {1'b0,8'd0,24'd0}; 118 | //if b is zero return zero 119 | end else if (($signed(b_exponent) == -127) && (b_mantissa == 0)) begin 120 | aout_Special[32] <= a_sign; 121 | aout_Special[31:24] <= a_exponent+127; 122 | aout_Special[23] <= 1'b1; 123 | aout_Special[22:0] <= a_mantissa[22:0]; 124 | bout_Special[32] <= b_sign; 125 | bout_Special[31:24] <= b_exponent+127; 126 | bout_Special[23] <= 1'b1; 127 | bout_Special[22:0] <= b_mantissa[22:0]; 128 | zout_Special <= {1'b0,8'd0,24'd0}; 129 | idle_Special <= put_idle; 130 | end else begin 131 | //Denormalised Number 132 | zout_Special <= 0; 133 | idle_Special <= no_idle; 134 | if ($signed(a_exponent) == -127) begin 135 | aout_Special <= {a_sign,-126,a_mantissa}; 136 | end else begin 137 | aout_Special[32] <= a_sign; 138 | aout_Special[31:24] <= a_exponent+127; 139 | aout_Special[23] <= 1'b1; 140 | aout_Special[22:0] <= a_mantissa[22:0]; 141 | end 142 | //Denormalised Number 143 | if ($signed(b_exponent) == -127) begin 144 | bout_Special <= {b_sign,-126,b_mantissa}; 145 | end else begin 146 | bout_Special[32] <= b_sign; 147 | bout_Special[31:24] <= b_exponent+127; 148 | bout_Special[23] <= 1'b1; 149 | bout_Special[22:0] <= b_mantissa[22:0]; 150 | end 151 | end 152 | end 153 | 154 | end 155 | 156 | endmodule 157 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/HCORDIC_Pipeline_FSL.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:03:51 02/23/2015 7 | // Design Name: 8 | // Module Name: HCORDIC_Pipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module HCORDIC_Pipeline_FSL( 22 | input [107:0] InstructionPacket, 23 | input reset, 24 | input clock, 25 | output [103:0] InstructionPacketOut, 26 | output InstructionAck, 27 | output OutputReady 28 | ); 29 | 30 | wire stall,load,ALU_done,converge; 31 | wire operation_Fetch,operation_iter,operation_FSM,operation_Execute; 32 | wire [107:0] InstructionPacket_Processed; 33 | wire [7:0] InsTagFetchOut,InsTagMuxOut,InsTagFSMOut,InsTag_iter,InsTagScaleOut,InsTagFinal; 34 | wire [1:0] mode_Fetch,mode_iter,mode_FSM,mode_Execute; 35 | wire [31:0] x_input, x_iter, xout_Mux, x_scale, xout_FSM; 36 | wire [31:0] y_input, y_iter, yout_Mux, y_scale, yout_FSM; 37 | wire [31:0] z_input, z_iter, zout_Mux, z_scale, zout_FSM; 38 | wire [31:0] k_iter, kout_Mux, k_scale, kout_FSM; 39 | wire [31:0] thetaout_FSM; 40 | wire [31:0] deltaout_FSM; 41 | wire [31:0] kappaout_FSM; 42 | wire ScaleValid; 43 | wire ProcessInputReady; 44 | wire [31:0] x_out, y_out, z_out; 45 | wire NatLogFlag, NatLogFlag_iter, NatLogFlagout_Mux, NatLogFlagScaleOut, NatLogFlag_Execute; 46 | 47 | assign InstructionAck = stall; 48 | assign InstructionPacketOut[31:0] = x_out; 49 | assign InstructionPacketOut[63:32] = y_out; 50 | assign InstructionPacketOut[95:64] = z_out; 51 | assign InstructionPacketOut[103:96] = InsTagFinal; 52 | 53 | Fetch_FSL v0 ( 54 | .InstructionPacket(InstructionPacket), 55 | .InstructionPacket_Processed(InstructionPacket_Processed), 56 | .ProcessInputReady(ProcessInputReady), 57 | .reset(reset), 58 | .clock(clock), 59 | .stall(stall), 60 | .x_input(x_input), 61 | .y_input(y_input), 62 | .z_input(z_input), 63 | .mode(mode_Fetch), 64 | .operation(operation_Fetch), 65 | .InsTagFetchOut(InsTagFetchOut), 66 | .load(load), 67 | .NatLogFlag(NatLogFlag) 68 | ); 69 | 70 | PreProcessxy v6 ( 71 | .InstructionPacket(InstructionPacket), 72 | .clock(clock), 73 | .InstructionPacketOut(InstructionPacket_Processed), 74 | .InputReady(ProcessInputReady) 75 | ); 76 | 77 | InputMux v1 ( 78 | .x_in(x_input), 79 | .y_in(y_input), 80 | .z_in(z_input), 81 | .x_iter(x_iter), 82 | .y_iter(y_iter), 83 | .z_iter(z_iter), 84 | .k_iter(k_iter), 85 | .load(load), 86 | .ALU_done(ALU_done), 87 | .reset(reset), 88 | .clock(clock), 89 | .mode_in(mode_Fetch), 90 | .operation_in(operation_Fetch), 91 | .NatLogFlag(NatLogFlag), 92 | .mode_iter(mode_iter), 93 | .operation_iter(operation_iter), 94 | .NatLogFlag_iter(NatLogFlag_iter), 95 | .InsTagFetchOut(InsTagFetchOut), 96 | .InsTag_iter(InsTag_iter), 97 | .x_out(xout_Mux), 98 | .y_out(yout_Mux), 99 | .z_out(zout_Mux), 100 | .k_out(kout_Mux), 101 | .x_scale(x_scale), 102 | .y_scale(y_scale), 103 | .z_scale(z_scale), 104 | .k_scale(k_scale), 105 | .modeout_Mux(mode_FSM), 106 | .operationout_Mux(operation_FSM), 107 | .NatLogFlagout_Mux(NatLogFlagout_Mux), 108 | .converge(converge), 109 | .stall(stall), 110 | .InsTagMuxOut(InsTagMuxOut), 111 | .InsTagScaleOut(InsTagScaleOut), 112 | .NatLogFlagScaleOut(NatLogFlagScaleOut), 113 | .ScaleValid(ScaleValid) 114 | ); 115 | 116 | FSM v3 ( 117 | .x_FSM(xout_Mux), 118 | .y_FSM(yout_Mux), 119 | .z_FSM(zout_Mux), 120 | .k_FSM(kout_Mux), 121 | .reset(reset), 122 | .clock(clock), 123 | .mode_FSM(mode_FSM), 124 | .operation_FSM(operation_FSM), 125 | .NatLogFlagout_Mux(NatLogFlagout_Mux), 126 | .InsTagMuxOut(InsTagMuxOut), 127 | .modeout_FSM(mode_Execute), 128 | .operationout_FSM(operation_Execute), 129 | .NatLogFlagout_FSM(NatLogFlag_Execute), 130 | .xout_FSM(xout_FSM), 131 | .yout_FSM(yout_FSM), 132 | .zout_FSM(zout_FSM), 133 | .kout_FSM(kout_FSM), 134 | .thetaout_FSM(thetaout_FSM), 135 | .deltaout_FSM(deltaout_FSM), 136 | .kappaout_FSM(kappaout_FSM), 137 | .InsTagFSMOut(InsTagFSMOut) 138 | ); 139 | 140 | ExecutePipeline v4 ( 141 | .X_in(xout_FSM), 142 | .Y_in(yout_FSM), 143 | .Z_in(zout_FSM), 144 | .K_in(kout_FSM), 145 | .kappa_in(kappaout_FSM), 146 | .theta_in(thetaout_FSM), 147 | .delta_in(deltaout_FSM), 148 | .reset(reset), 149 | .clock(clock), 150 | .operation(operation_Execute), 151 | .NatLogFlag_Execute(NatLogFlag_Execute), 152 | .mode(mode_Execute), 153 | .InsTagFSMOut(InsTagFSMOut), 154 | .X_next(x_iter), 155 | .Y_next(y_iter), 156 | .Z_next(z_iter), 157 | .K_next(k_iter), 158 | .mode_out(mode_iter), 159 | .operation_out(operation_iter), 160 | .NatLogFlag_iter(NatLogFlag_iter), 161 | .ALU_done(ALU_done), 162 | .InsTag_iter(InsTag_iter) 163 | ); 164 | 165 | Descale_pipeline v5 ( 166 | .x_scale(x_scale), 167 | .y_scale(y_scale), 168 | .z_scale(z_scale), 169 | .k_in(k_scale), 170 | .InsTagScaleOut(InsTagScaleOut), 171 | .ScaleValid(ScaleValid), 172 | .NatLogFlagScaleOut(NatLogFlagScaleOut), 173 | .reset(reset), 174 | .clock(clock), 175 | .x_out(x_out), 176 | .y_out(y_out), 177 | .z_out(z_out), 178 | .done(OutputReady), 179 | .InsTagFinal(InsTagFinal) 180 | ); 181 | 182 | endmodule 183 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/NormaliseAdder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:27:45 02/22/2015 7 | // Design Name: 8 | // Module Name: NormaliseAdder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NormaliseAdder( 22 | input idle_AddState, 23 | input [31:0] sout_AddState, 24 | input [27:0] sum_AddState, 25 | input clock, 26 | output reg idle_NormaliseSum, 27 | output reg [31:0] sout_NormaliseSum, 28 | output reg [27:0] sum_NormaliseSum 29 | ); 30 | 31 | parameter no_idle = 1'b0, 32 | put_idle = 1'b1; 33 | 34 | wire [7:0] s_exponent; 35 | 36 | assign s_exponent = sout_AddState[30:23]; 37 | 38 | always @ (posedge clock) 39 | begin 40 | 41 | idle_NormaliseSum <= idle_AddState; 42 | 43 | if (idle_AddState != put_idle) begin 44 | 45 | sout_NormaliseSum[31] <= sout_AddState[31]; 46 | sout_NormaliseSum[22:0] <= sout_AddState[22:0]; 47 | 48 | if (sum_AddState[27] == 1'b1) begin 49 | sout_NormaliseSum[30:23] <= s_exponent + 1; 50 | sum_NormaliseSum <= sum_AddState >> 1; 51 | end 52 | 53 | else if(sum_AddState[26:3] == 24'h000000) begin 54 | sout_NormaliseSum[30:23] <= 10'h382; 55 | end 56 | 57 | else if (sum_AddState[26:4] == 23'h000000) begin 58 | sout_NormaliseSum[30:23] <= s_exponent - 23; 59 | sum_NormaliseSum <= sum_AddState << 23; 60 | end 61 | 62 | else if (sum_AddState[26:5] == 22'h000000) begin 63 | sout_NormaliseSum[30:23] <= s_exponent - 22; 64 | sum_NormaliseSum <= sum_AddState << 22; 65 | end 66 | 67 | else if (sum_AddState[26:6] == 21'h000000) begin 68 | sout_NormaliseSum[30:23] <= s_exponent - 21; 69 | sum_NormaliseSum <= sum_AddState << 21; 70 | end 71 | 72 | else if (sum_AddState[26:7] == 20'h00000) begin 73 | sout_NormaliseSum[30:23] <= s_exponent - 20; 74 | sum_NormaliseSum <= sum_AddState << 20; 75 | end 76 | 77 | else if (sum_AddState[26:8] == 19'h00000) begin 78 | sout_NormaliseSum[30:23] <= s_exponent - 19; 79 | sum_NormaliseSum <= sum_AddState << 19; 80 | end 81 | 82 | else if (sum_AddState[26:9] == 18'h00000) begin 83 | sout_NormaliseSum[30:23] <= s_exponent - 18; 84 | sum_NormaliseSum <= sum_AddState << 18; 85 | end 86 | 87 | else if (sum_AddState[26:10] == 17'h00000) begin 88 | sout_NormaliseSum[30:23] <= s_exponent - 17; 89 | sum_NormaliseSum <= sum_AddState << 17; 90 | end 91 | 92 | else if (sum_AddState[26:11] == 16'h0000) begin 93 | sout_NormaliseSum[30:23] <= s_exponent - 16; 94 | sum_NormaliseSum <= sum_AddState << 16; 95 | end 96 | 97 | else if (sum_AddState[26:12] == 15'h0000) begin 98 | sout_NormaliseSum[30:23] <= s_exponent - 15; 99 | sum_NormaliseSum <= sum_AddState << 15; 100 | end 101 | 102 | else if (sum_AddState[26:13] == 14'h0000) begin 103 | sout_NormaliseSum[30:23] <= s_exponent - 14; 104 | sum_NormaliseSum <= sum_AddState << 14; 105 | end 106 | 107 | else if (sum_AddState[26:14] == 13'h0000) begin 108 | sout_NormaliseSum[30:23] <= s_exponent - 13; 109 | sum_NormaliseSum <= sum_AddState << 13; 110 | end 111 | 112 | else if (sum_AddState[26:15] == 12'h000) begin 113 | sout_NormaliseSum[30:23] <= s_exponent - 12; 114 | sum_NormaliseSum <= sum_AddState << 12; 115 | end 116 | 117 | else if (sum_AddState[26:16] == 11'h000) begin 118 | sout_NormaliseSum[30:23] <= s_exponent - 11; 119 | sum_NormaliseSum <= sum_AddState << 11; 120 | end 121 | 122 | else if (sum_AddState[26:17] == 10'h000) begin 123 | sout_NormaliseSum[30:23] <= s_exponent - 10; 124 | sum_NormaliseSum <= sum_AddState << 10; 125 | end 126 | 127 | else if (sum_AddState[26:18] == 9'h0000) begin 128 | sout_NormaliseSum[30:23] <= s_exponent - 9; 129 | sum_NormaliseSum <= sum_AddState << 9; 130 | end 131 | 132 | else if (sum_AddState[26:19] == 8'h00) begin 133 | sout_NormaliseSum[30:23] <= s_exponent - 8; 134 | sum_NormaliseSum <= sum_AddState << 8; 135 | end 136 | 137 | else if (sum_AddState[26:20] == 7'h00) begin 138 | sout_NormaliseSum[30:23] <= s_exponent - 7; 139 | sum_NormaliseSum <= sum_AddState << 7; 140 | end 141 | 142 | else if (sum_AddState[26:21] == 6'h00) begin 143 | sout_NormaliseSum[30:23] <= s_exponent - 6; 144 | sum_NormaliseSum <= sum_AddState << 6; 145 | end 146 | 147 | else if (sum_AddState[26:22] == 5'h00) begin 148 | sout_NormaliseSum[30:23] <= s_exponent - 5; 149 | sum_NormaliseSum <= sum_AddState << 5; 150 | end 151 | 152 | else if (sum_AddState[26:23] == 4'h0) begin 153 | sout_NormaliseSum[30:23] <= s_exponent - 4; 154 | sum_NormaliseSum <= sum_AddState << 4; 155 | end 156 | 157 | else if (sum_AddState[26:24] == 3'h0) begin 158 | sout_NormaliseSum[30:23] <= s_exponent - 3; 159 | sum_NormaliseSum <= sum_AddState << 3; 160 | end 161 | 162 | else if (sum_AddState[26:25] == 2'h0) begin 163 | sout_NormaliseSum[30:23] <= s_exponent - 2; 164 | sum_NormaliseSum <= sum_AddState << 2; 165 | end 166 | 167 | else if (sum_AddState[26] == 1'h0) begin 168 | sout_NormaliseSum[30:23] <= s_exponent - 1; 169 | sum_NormaliseSum <= sum_AddState << 1; 170 | end 171 | 172 | else begin 173 | sout_NormaliseSum[30:23] <= s_exponent; 174 | sum_NormaliseSum <= sum_AddState; 175 | end 176 | end 177 | 178 | else begin 179 | sout_NormaliseSum <= sout_AddState; 180 | sum_NormaliseSum <= 0; 181 | end 182 | end 183 | 184 | endmodule 185 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Fetch_FSL.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:43:45 02/20/2015 7 | // Design Name: 8 | // Module Name: Fetch 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Fetch_FSL( 22 | input [107:0] InstructionPacket, 23 | input [107:0] InstructionPacket_Processed, 24 | input ProcessInputReady, 25 | input reset, 26 | input clock, 27 | input stall, 28 | output reg [31:0] x_input = 32'h00000000, 29 | output reg [31:0] y_input = 32'h00000000, 30 | output reg [31:0] z_input = 32'h00000000, 31 | output reg [1:0] mode, 32 | output reg operation, 33 | output reg [7:0] InsTagFetchOut, 34 | output reg load = 1'b0, 35 | output reg NatLogFlag = 1'b0 36 | ); 37 | 38 | wire [3:0] Opcode; 39 | wire [31:0] x_processor; 40 | wire [31:0] y_processor; 41 | wire [31:0] z_processor; 42 | wire [7:0] InstructionTag; 43 | 44 | wire [3:0] Opcode_processed; 45 | wire [31:0] x_processor_processed; 46 | wire [31:0] y_processor_processed; 47 | wire [31:0] z_processor_processed; 48 | wire [7:0] InstructionTag_processed; 49 | 50 | assign InstructionTag = InstructionPacket[107:100]; 51 | assign Opcode = InstructionPacket[99:96]; 52 | assign x_processor = InstructionPacket[31:0]; 53 | assign y_processor = InstructionPacket[63:32]; 54 | assign z_processor = InstructionPacket[95:64]; 55 | 56 | assign InstructionTag_processed = InstructionPacket_Processed[107:100]; 57 | assign Opcode_processed = InstructionPacket_Processed[99:96]; 58 | assign x_processor_processed = InstructionPacket_Processed[31:0]; 59 | assign y_processor_processed = InstructionPacket_Processed[63:32]; 60 | assign z_processor_processed = InstructionPacket_Processed[95:64]; 61 | 62 | parameter sin_cos = 4'd0, 63 | sinh_cosh = 4'd1, 64 | arctan = 4'd2, 65 | arctanh = 4'd3, 66 | exp = 4'd4, 67 | sqr_root = 4'd5, // Pre processed input is given 4'd11 68 | // This requires pre processing. x = (a+1)/2 and y = (a-1)/2 69 | division = 4'd6, 70 | tan = 4'd7, // This is iterative. sin_cos followed by division. 71 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 72 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 73 | hypotenuse = 4'd10; 74 | 75 | parameter vectoring = 1'b0, 76 | rotation = 1'b1; 77 | 78 | parameter circular = 2'b01, 79 | linear = 2'b00, 80 | hyperbolic = 2'b11; 81 | 82 | always @ (posedge clock) 83 | begin 84 | 85 | if (reset == 1'b1) begin 86 | x_input <= 32'h00000000; 87 | y_input <= 32'h00000000; 88 | z_input <= 32'h00000000; 89 | load <= 1'b0; 90 | NatLogFlag <= 1'b0; 91 | end 92 | 93 | else begin 94 | 95 | if (ProcessInputReady == 1'b0) begin 96 | 97 | InsTagFetchOut <= InstructionTag; 98 | 99 | case(Opcode) 100 | 101 | sin_cos: 102 | begin 103 | mode <= circular; 104 | operation <= rotation; 105 | x_input <= 32'h3F800000; 106 | y_input <= 32'h00000000; 107 | z_input <= z_processor; 108 | load <= 1'b1; 109 | end 110 | 111 | sinh_cosh: 112 | begin 113 | mode <= hyperbolic; 114 | operation <= rotation; 115 | x_input <= 32'h3F800000; 116 | y_input <= 32'h00000000; 117 | z_input <= z_processor; 118 | load <= 1'b1; 119 | end 120 | 121 | arctan: 122 | begin 123 | mode <= circular; 124 | operation <= vectoring; 125 | x_input <= 32'h3F800000; 126 | y_input <= y_processor; 127 | z_input <= 32'h00000000; 128 | load <= 1'b1; 129 | end 130 | 131 | arctanh: 132 | begin 133 | mode <= hyperbolic; 134 | operation <= vectoring; 135 | x_input <= 32'h3F800000; 136 | y_input <= y_processor; 137 | z_input <= 32'h00000000; 138 | load <= 1'b1; 139 | end 140 | 141 | exp: 142 | begin 143 | mode <= hyperbolic; 144 | operation <= rotation; 145 | x_input <= 32'h3F800000; 146 | y_input <= 32'h3F800000; 147 | z_input <= z_processor; 148 | load <= 1'b1; 149 | end 150 | 151 | division: 152 | begin 153 | mode <= linear; 154 | operation <= vectoring; 155 | x_input <= x_processor; 156 | y_input <= y_processor; 157 | z_input <= 32'h00000000; 158 | load <= 1'b1; 159 | end 160 | 161 | hypotenuse: 162 | begin 163 | mode <= circular; 164 | operation <= vectoring; 165 | x_input <= x_processor; 166 | y_input <= y_processor; 167 | z_input <= 32'h00000000; 168 | load <= 1'b1; 169 | end 170 | 171 | endcase 172 | 173 | end 174 | 175 | else begin 176 | 177 | InsTagFetchOut <= InstructionTag_processed; 178 | 179 | case(Opcode_processed) 180 | 181 | sqr_root: 182 | begin 183 | mode <= hyperbolic; 184 | operation <= vectoring; 185 | x_input[31] <= x_processor_processed[31]; 186 | x_input[30:23] <= x_processor_processed[30:23] - 8'h01; 187 | x_input[22:0] <= x_processor_processed[22:0]; 188 | y_input[31] <= 1'b0; 189 | y_input[30:23] <= y_processor_processed[30:23] - 8'h01; 190 | y_input[22:0] <= y_processor_processed[22:0]; 191 | z_input <= 32'h00000000; 192 | load <= 1'b1; 193 | end 194 | 195 | nat_log: 196 | begin 197 | mode <= hyperbolic; 198 | operation <= vectoring; 199 | x_input <= x_processor_processed; 200 | y_input[30:0] <= y_processor_processed[30:0]; 201 | y_input[31] <= 1'b0; 202 | z_input <= 32'h00000000; 203 | load <= 1'b1; 204 | NatLogFlag <= 1'b1; 205 | end 206 | 207 | endcase 208 | 209 | end 210 | 211 | if (stall == 1'b1) begin 212 | load <= 1'b0; 213 | end 214 | 215 | 216 | end 217 | end 218 | endmodule 219 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/SpecialAddProcess.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:46:09 02/22/2015 7 | // Design Name: 8 | // Module Name: SpecialAdd 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SpecialAddProcess( 22 | input [31:0] z_preSpecial, 23 | input [3:0] Opcode, 24 | input [31:0] cin_Special, 25 | input [31:0] zin_Special, 26 | input [7:0] InsTagIn, 27 | input clock, 28 | output reg idle_Special = 1'b0, 29 | output reg [7:0] difference_Special, 30 | output reg [35:0] cout_Special, 31 | output reg [35:0] zout_Special, 32 | output reg [31:0] sout_Special, 33 | output reg [3:0] Opcode_Special, 34 | output reg [31:0] z_postSpecial, 35 | output reg [7:0] InsTagSpecial 36 | ); 37 | 38 | wire z_sign; 39 | wire [7:0] z_exponent; 40 | wire [26:0] z_mantissa; 41 | 42 | wire c_sign; 43 | wire [7:0] c_exponent; 44 | wire [26:0] c_mantissa; 45 | 46 | assign c_sign = cin_Special[31]; 47 | assign c_exponent = {cin_Special[30:23] - 127}; 48 | assign c_mantissa = {cin_Special[22:0],3'd0}; 49 | 50 | assign z_sign = {zin_Special[31]}; 51 | assign z_exponent = {zin_Special[30:23] - 127}; 52 | assign z_mantissa = {zin_Special[22:0],3'd0}; 53 | 54 | parameter no_idle = 1'b0, 55 | put_idle = 1'b1; 56 | 57 | parameter sin_cos = 4'd0, 58 | sinh_cosh = 4'd1, 59 | arctan = 4'd2, 60 | arctanh = 4'd3, 61 | exp = 4'd4, 62 | sqr_root = 4'd5, // Pre processed input is given 4'd11 63 | // This requires pre processing. x = (a+1)/2 and y = (a-1)/2 64 | division = 4'd6, 65 | tan = 4'd7, // This is iterative. sin_cos followed by division. 66 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 67 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 68 | hypotenuse = 4'd10, 69 | PreProcess = 4'd11; 70 | 71 | always @ (posedge clock) 72 | begin 73 | 74 | InsTagSpecial <= InsTagIn; 75 | z_postSpecial <= z_preSpecial; 76 | Opcode_Special <= Opcode; 77 | 78 | if(Opcode == sqr_root || Opcode == nat_log) begin 79 | 80 | if ($signed(z_exponent) > $signed(c_exponent)) begin 81 | difference_Special <= z_exponent - c_exponent; 82 | end 83 | else if ($signed(z_exponent) <= $signed(c_exponent)) begin 84 | difference_Special <= c_exponent - z_exponent; 85 | end 86 | 87 | // Most of the special cases will never occur except the case where one input is zero. 88 | // The HCORDIC module will not receive NaN and inf at input stage. 89 | //if c is NaN or z is NaN return NaN 90 | if ((c_exponent == 128 && c_mantissa != 0) || (z_exponent == 128 && z_mantissa != 0)) begin 91 | sout_Special[31] <= 1; 92 | sout_Special[30:23] <= 255; 93 | sout_Special[22] <= 1; 94 | sout_Special[21:0] <= 0; 95 | zout_Special <= zin_Special; 96 | cout_Special <= cin_Special; 97 | idle_Special <= put_idle; 98 | //if c is inf return inf 99 | end else if (c_exponent == 128) begin 100 | sout_Special[31] <= c_sign; 101 | sout_Special[30:23] <= 255; 102 | sout_Special[22:0] <= 0; 103 | zout_Special <= zin_Special; 104 | cout_Special <= cin_Special; 105 | idle_Special <= put_idle; 106 | //if z is inf return inf 107 | end else if (z_exponent == 128) begin 108 | sout_Special[31] <= z_sign; 109 | sout_Special[30:23] <= 255; 110 | sout_Special[22:0] <= 0; 111 | zout_Special <= zin_Special; 112 | cout_Special <= cin_Special; 113 | idle_Special <= put_idle; 114 | //if c is zero return z 115 | end else if ((($signed(c_exponent) == -127) && (c_mantissa == 0)) && (($signed(z_exponent) == -127) && (z_mantissa == 0))) begin 116 | sout_Special[31] <= c_sign & z_sign; 117 | sout_Special[30:23] <= z_exponent[7:0] + 127; 118 | sout_Special[22:0] <= z_mantissa[26:3]; 119 | zout_Special <= zin_Special; 120 | cout_Special <= cin_Special; 121 | idle_Special <= put_idle; 122 | //if c is zero return z 123 | end else if (($signed(c_exponent) == -127) && (c_mantissa == 0)) begin 124 | sout_Special[31] <= z_sign; 125 | sout_Special[30:23] <= z_exponent[7:0] + 127; 126 | sout_Special[22:0] <= z_mantissa[26:3]; 127 | zout_Special <= zin_Special; 128 | cout_Special <= cin_Special; 129 | idle_Special <= put_idle; 130 | //if z is zero return c 131 | end else if (($signed(z_exponent) == -127) && (z_mantissa == 0)) begin 132 | sout_Special[31] <= c_sign; 133 | sout_Special[30:23] <= c_exponent[7:0] + 127; 134 | sout_Special[22:0] <= c_mantissa[26:3]; 135 | zout_Special <= zin_Special; 136 | cout_Special <= cin_Special; 137 | idle_Special <= put_idle; 138 | end else begin 139 | sout_Special <= 0; 140 | //Denormalised Number 141 | if ($signed(c_exponent) == -127) begin 142 | cout_Special[34:27] <= -126; 143 | cout_Special[35] <= c_sign; 144 | cout_Special[26:0] <= c_mantissa; 145 | end else begin 146 | cout_Special[34:27] <= c_exponent + 127; 147 | cout_Special[35] <= c_sign; 148 | cout_Special[26] <= 1; 149 | cout_Special[25:0] <= c_mantissa[25:0]; 150 | idle_Special <= no_idle; 151 | end 152 | //Denormalised Number 153 | if ($signed(z_exponent) == -127) begin 154 | zout_Special[35] <= z_sign; 155 | zout_Special[34:27] <= -126; 156 | zout_Special[26:0] <= z_mantissa; 157 | end else begin 158 | zout_Special[35] <= z_sign; 159 | zout_Special[34:27] <= z_exponent + 127; 160 | zout_Special[25:0] <= z_mantissa[25:0]; 161 | zout_Special[26] <= 1; 162 | idle_Special <= no_idle; 163 | end 164 | end 165 | 166 | end 167 | 168 | else begin 169 | sout_Special[31] <= z_sign; 170 | sout_Special[30:23] <= z_exponent[7:0] + 127; 171 | sout_Special[22:0] <= z_mantissa[26:3]; 172 | zout_Special <= zin_Special; 173 | cout_Special <= cin_Special; 174 | idle_Special <= put_idle; 175 | end 176 | 177 | end 178 | 179 | endmodule 180 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/Allign.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:45:59 02/22/2015 7 | // Design Name: 8 | // Module Name: Allign 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Allign( 22 | input [1:0] idle_NormaliseProd, 23 | input [35:0] cout_NormaliseProd, 24 | input [35:0] zout_NormaliseProd, 25 | input [31:0] sout_NormaliseProd, 26 | input [1:0] modeout_NormaliseProd, 27 | input operationout_NormaliseProd, 28 | input NatLogFlagout_NormaliseProd, 29 | input [49:0] productout_NormaliseProd, 30 | input [7:0] InsTag_NormaliseProd, 31 | input clock, 32 | output reg [1:0] idle_Allign, 33 | output reg [35:0] cout_Allign, 34 | output reg [35:0] zout_Allign, 35 | output reg [31:0] sout_Allign, 36 | output reg [1:0] modeout_Allign, 37 | output reg operationout_Allign, 38 | output reg NatLogFlagout_Allign, 39 | output reg [7:0] difference_Allign, 40 | output reg [7:0] InsTag_Allign 41 | ); 42 | 43 | parameter mode_circular =2'b01, 44 | mode_linear =2'b00, 45 | mode_hyperbolic=2'b11; 46 | 47 | parameter no_idle = 2'b00, 48 | allign_idle = 2'b01, 49 | put_idle = 2'b10; 50 | 51 | wire z_sign; 52 | wire [7:0] z_exponent; 53 | wire [26:0] z_mantissa; 54 | 55 | wire c_sign; 56 | wire [7:0] c_exponent; 57 | wire [26:0] c_mantissa; 58 | 59 | assign z_sign = zout_NormaliseProd[35]; 60 | assign z_exponent = zout_NormaliseProd[34:27]; 61 | assign z_mantissa = {zout_NormaliseProd[26:0]}; 62 | 63 | assign c_sign = cout_NormaliseProd[35]; 64 | assign c_exponent = cout_NormaliseProd[34:27] - 127; 65 | assign c_mantissa = {cout_NormaliseProd[26:0]}; 66 | 67 | always @ (posedge clock) 68 | begin 69 | 70 | InsTag_Allign <= InsTag_NormaliseProd; 71 | idle_Allign <= idle_NormaliseProd; 72 | modeout_Allign <= modeout_NormaliseProd; 73 | operationout_Allign <= operationout_NormaliseProd; 74 | NatLogFlagout_Allign <= NatLogFlagout_NormaliseProd; 75 | 76 | if (idle_NormaliseProd == no_idle || idle_NormaliseProd == allign_idle) begin 77 | if ($signed(z_exponent) > $signed(c_exponent)) begin 78 | difference_Allign <= z_exponent - c_exponent; 79 | end 80 | else if ($signed(z_exponent) <= $signed(c_exponent)) begin 81 | difference_Allign <= c_exponent - z_exponent; 82 | end 83 | 84 | 85 | // Most of the special cases will never occur except the case where one input is zero. 86 | // The HCORDIC module will not receive NaN and inf at input stage. 87 | //if c is NaN or z is NaN return NaN 88 | if ((c_exponent == 128 && c_mantissa != 0) || (z_exponent == 128 && z_mantissa != 0)) begin 89 | sout_Allign[31] <= 1; 90 | sout_Allign[30:23] <= 255; 91 | sout_Allign[22] <= 1; 92 | sout_Allign[21:0] <= 0; 93 | zout_Allign <= zout_NormaliseProd; 94 | cout_Allign <= cout_NormaliseProd; 95 | idle_Allign <= put_idle; 96 | //if c is inf return inf 97 | end else if (c_exponent == 128) begin 98 | sout_Allign[31] <= c_sign; 99 | sout_Allign[30:23] <= 255; 100 | sout_Allign[22:0] <= 0; 101 | zout_Allign <= zout_NormaliseProd; 102 | cout_Allign <= cout_NormaliseProd; 103 | idle_Allign <= put_idle; 104 | //if z is inf return inf 105 | end else if (z_exponent == 128) begin 106 | sout_Allign[31] <= z_sign; 107 | sout_Allign[30:23] <= 255; 108 | sout_Allign[22:0] <= 0; 109 | zout_Allign <= zout_NormaliseProd; 110 | cout_Allign <= cout_NormaliseProd; 111 | idle_Allign <= put_idle; 112 | //if c is zero return z 113 | end else if ((($signed(c_exponent) == -127) && (c_mantissa == 0)) && (($signed(z_exponent) == -127) && (z_mantissa == 0))) begin 114 | sout_Allign[31] <= c_sign & z_sign; 115 | sout_Allign[30:23] <= z_exponent[7:0] + 127; 116 | sout_Allign[22:0] <= z_mantissa[26:3]; 117 | zout_Allign <= zout_NormaliseProd; 118 | cout_Allign <= cout_NormaliseProd; 119 | idle_Allign <= put_idle; 120 | //if c is zero return z 121 | end else if (($signed(c_exponent) == -127) && (c_mantissa == 0)) begin 122 | sout_Allign[31] <= z_sign; 123 | sout_Allign[30:23] <= z_exponent[7:0] + 127; 124 | sout_Allign[22:0] <= z_mantissa[26:3]; 125 | zout_Allign <= zout_NormaliseProd; 126 | cout_Allign <= cout_NormaliseProd; 127 | idle_Allign <= put_idle; 128 | //if z is zero return c 129 | end else if (($signed(z_exponent) == -127) && (z_mantissa == 0)) begin 130 | sout_Allign[31] <= c_sign; 131 | sout_Allign[30:23] <= c_exponent[7:0] + 127; 132 | sout_Allign[22:0] <= c_mantissa[26:3]; 133 | zout_Allign <= zout_NormaliseProd; 134 | cout_Allign <= cout_NormaliseProd; 135 | idle_Allign <= put_idle; 136 | end else begin 137 | sout_Allign <= sout_NormaliseProd; 138 | //Denormalised Number 139 | if ($signed(c_exponent) == -127) begin 140 | cout_Allign[34:27] <= -126; 141 | cout_Allign[35] <= c_sign; 142 | cout_Allign[26:0] <= c_mantissa; 143 | end else begin 144 | cout_Allign[34:27] <= c_exponent + 127; 145 | cout_Allign[35] <= c_sign; 146 | cout_Allign[26] <= 1; 147 | cout_Allign[25:0] <= c_mantissa[25:0]; 148 | end 149 | //Denormalised Number 150 | if ($signed(z_exponent) == -127) begin 151 | zout_Allign[35] <= z_sign; 152 | zout_Allign[34:27] <= -126; 153 | zout_Allign[26:0] <= z_mantissa; 154 | end else begin 155 | zout_Allign[35] <= z_sign; 156 | zout_Allign[34:27] <= z_exponent + 127; 157 | zout_Allign[25:0] <= z_mantissa[25:0]; 158 | zout_Allign[26] <= 1; 159 | end 160 | end 161 | end 162 | 163 | else begin 164 | sout_Allign <= sout_NormaliseProd; 165 | zout_Allign <= zout_NormaliseProd; 166 | cout_Allign <= cout_NormaliseProd; 167 | end 168 | end 169 | 170 | 171 | endmodule 172 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/NormaliseSum.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:04:29 02/22/2015 7 | // Design Name: 8 | // Module Name: NormaliseSum 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NormaliseSum( 22 | input [1:0] idle_AddState, 23 | input [31:0] sout_AddState, 24 | input [1:0] modeout_AddState, 25 | input operationout_AddState, 26 | input NatLogFlagout_AddState, 27 | input [27:0] sum_AddState, 28 | input [7:0] InsTag_AddState, 29 | input clock, 30 | output reg [1:0] idle_NormaliseSum, 31 | output reg [31:0] sout_NormaliseSum, 32 | output reg [1:0] modeout_NormaliseSum, 33 | output reg operationout_NormaliseSum, 34 | output reg NatLogFlagout_NormaliseSum, 35 | output reg [27:0] sum_NormaliseSum, 36 | output reg [7:0] InsTag_NormaliseSum 37 | ); 38 | 39 | parameter mode_circular =2'b01, 40 | mode_linear =2'b00, 41 | mode_hyperbolic=2'b11; 42 | 43 | parameter no_idle = 2'b00, 44 | allign_idle = 2'b01, 45 | put_idle = 2'b10; 46 | 47 | wire [7:0] s_exponent; 48 | 49 | assign s_exponent = sout_AddState[30:23]; 50 | 51 | always @ (posedge clock) 52 | begin 53 | 54 | InsTag_NormaliseSum <= InsTag_AddState; 55 | idle_NormaliseSum <= idle_AddState; 56 | modeout_NormaliseSum <= modeout_AddState; 57 | operationout_NormaliseSum <= operationout_AddState; 58 | NatLogFlagout_NormaliseSum <= NatLogFlagout_AddState; 59 | 60 | if (idle_AddState != put_idle) begin 61 | 62 | sout_NormaliseSum[31] <= sout_AddState[31]; 63 | sout_NormaliseSum[22:0] <= sout_AddState[22:0]; 64 | 65 | if (sum_AddState[27] == 1'b1) begin 66 | sout_NormaliseSum[30:23] <= s_exponent + 1; 67 | sum_NormaliseSum <= sum_AddState >> 1; 68 | end 69 | 70 | else if(sum_AddState[26:3] == 24'h000000) begin 71 | sout_NormaliseSum[30:23] <= 10'h382; 72 | end 73 | 74 | else if (sum_AddState[26:4] == 23'h000000) begin 75 | sout_NormaliseSum[30:23] <= s_exponent - 23; 76 | sum_NormaliseSum <= sum_AddState << 23; 77 | end 78 | 79 | else if (sum_AddState[26:5] == 22'h000000) begin 80 | sout_NormaliseSum[30:23] <= s_exponent - 22; 81 | sum_NormaliseSum <= sum_AddState << 22; 82 | end 83 | 84 | else if (sum_AddState[26:6] == 21'h000000) begin 85 | sout_NormaliseSum[30:23] <= s_exponent - 21; 86 | sum_NormaliseSum <= sum_AddState << 21; 87 | end 88 | 89 | else if (sum_AddState[26:7] == 20'h00000) begin 90 | sout_NormaliseSum[30:23] <= s_exponent - 20; 91 | sum_NormaliseSum <= sum_AddState << 20; 92 | end 93 | 94 | else if (sum_AddState[26:8] == 19'h00000) begin 95 | sout_NormaliseSum[30:23] <= s_exponent - 19; 96 | sum_NormaliseSum <= sum_AddState << 19; 97 | end 98 | 99 | else if (sum_AddState[26:9] == 18'h00000) begin 100 | sout_NormaliseSum[30:23] <= s_exponent - 18; 101 | sum_NormaliseSum <= sum_AddState << 18; 102 | end 103 | 104 | else if (sum_AddState[26:10] == 17'h00000) begin 105 | sout_NormaliseSum[30:23] <= s_exponent - 17; 106 | sum_NormaliseSum <= sum_AddState << 17; 107 | end 108 | 109 | else if (sum_AddState[26:11] == 16'h0000) begin 110 | sout_NormaliseSum[30:23] <= s_exponent - 16; 111 | sum_NormaliseSum <= sum_AddState << 16; 112 | end 113 | 114 | else if (sum_AddState[26:12] == 15'h0000) begin 115 | sout_NormaliseSum[30:23] <= s_exponent - 15; 116 | sum_NormaliseSum <= sum_AddState << 15; 117 | end 118 | 119 | else if (sum_AddState[26:13] == 14'h0000) begin 120 | sout_NormaliseSum[30:23] <= s_exponent - 14; 121 | sum_NormaliseSum <= sum_AddState << 14; 122 | end 123 | 124 | else if (sum_AddState[26:14] == 13'h0000) begin 125 | sout_NormaliseSum[30:23] <= s_exponent - 13; 126 | sum_NormaliseSum <= sum_AddState << 13; 127 | end 128 | 129 | else if (sum_AddState[26:15] == 12'h000) begin 130 | sout_NormaliseSum[30:23] <= s_exponent - 12; 131 | sum_NormaliseSum <= sum_AddState << 12; 132 | end 133 | 134 | else if (sum_AddState[26:16] == 11'h000) begin 135 | sout_NormaliseSum[30:23] <= s_exponent - 11; 136 | sum_NormaliseSum <= sum_AddState << 11; 137 | end 138 | 139 | else if (sum_AddState[26:17] == 10'h000) begin 140 | sout_NormaliseSum[30:23] <= s_exponent - 10; 141 | sum_NormaliseSum <= sum_AddState << 10; 142 | end 143 | 144 | else if (sum_AddState[26:18] == 9'h0000) begin 145 | sout_NormaliseSum[30:23] <= s_exponent - 9; 146 | sum_NormaliseSum <= sum_AddState << 9; 147 | end 148 | 149 | else if (sum_AddState[26:19] == 8'h00) begin 150 | sout_NormaliseSum[30:23] <= s_exponent - 8; 151 | sum_NormaliseSum <= sum_AddState << 8; 152 | end 153 | 154 | else if (sum_AddState[26:20] == 7'h00) begin 155 | sout_NormaliseSum[30:23] <= s_exponent - 7; 156 | sum_NormaliseSum <= sum_AddState << 7; 157 | end 158 | 159 | else if (sum_AddState[26:21] == 6'h00) begin 160 | sout_NormaliseSum[30:23] <= s_exponent - 6; 161 | sum_NormaliseSum <= sum_AddState << 6; 162 | end 163 | 164 | else if (sum_AddState[26:22] == 5'h00) begin 165 | sout_NormaliseSum[30:23] <= s_exponent - 5; 166 | sum_NormaliseSum <= sum_AddState << 5; 167 | end 168 | 169 | else if (sum_AddState[26:23] == 4'h0) begin 170 | sout_NormaliseSum[30:23] <= s_exponent - 4; 171 | sum_NormaliseSum <= sum_AddState << 4; 172 | end 173 | 174 | else if (sum_AddState[26:24] == 3'h0) begin 175 | sout_NormaliseSum[30:23] <= s_exponent - 3; 176 | sum_NormaliseSum <= sum_AddState << 3; 177 | end 178 | 179 | else if (sum_AddState[26:25] == 2'h0) begin 180 | sout_NormaliseSum[30:23] <= s_exponent - 2; 181 | sum_NormaliseSum <= sum_AddState << 2; 182 | end 183 | 184 | else if (sum_AddState[26] == 1'h0) begin 185 | sout_NormaliseSum[30:23] <= s_exponent - 1; 186 | sum_NormaliseSum <= sum_AddState << 1; 187 | end 188 | 189 | else begin 190 | sout_NormaliseSum[30:23] <= s_exponent; 191 | sum_NormaliseSum <= sum_AddState; 192 | end 193 | end 194 | 195 | else begin 196 | sout_NormaliseSum <= sout_AddState; 197 | sum_NormaliseSum <= 0; 198 | end 199 | end 200 | 201 | endmodule 202 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/NormaliseAdderProcess.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:27:45 02/22/2015 7 | // Design Name: 8 | // Module Name: NormaliseAdder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NormaliseAdderProcess( 22 | input [31:0] z_postAddState, 23 | input [3:0] Opcode_AddState, 24 | input idle_AddState, 25 | input [31:0] sout_AddState, 26 | input [27:0] sum_AddState, 27 | input [7:0] InsTagAdder, 28 | input clock, 29 | output reg idle_NormaliseSum, 30 | output reg [31:0] sout_NormaliseSum, 31 | output reg [27:0] sum_NormaliseSum, 32 | output reg [3:0] Opcode_NormaliseSum, 33 | output reg [31:0] z_postNormaliseSum, 34 | output reg [7:0] InsTagNormaliseAdder 35 | ); 36 | 37 | parameter no_idle = 1'b0, 38 | put_idle = 1'b1; 39 | 40 | wire [7:0] s_exponent; 41 | 42 | assign s_exponent = sout_AddState[30:23]; 43 | 44 | parameter sin_cos = 4'd0, 45 | sinh_cosh = 4'd1, 46 | arctan = 4'd2, 47 | arctanh = 4'd3, 48 | exp = 4'd4, 49 | sqr_root = 4'd5, // Pre processed input is given 4'd11 50 | // This requires pre processing. x = (a+1)/2 and y = (a-1)/2 51 | division = 4'd6, 52 | tan = 4'd7, // This is iterative. sin_cos followed by division. 53 | tanh = 4'd8, // This is iterative. sinh_cosh followed by division. 54 | nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1) 55 | hypotenuse = 4'd10, 56 | PreProcess = 4'd11; 57 | 58 | always @ (posedge clock) 59 | begin 60 | 61 | InsTagNormaliseAdder <= InsTagAdder; 62 | z_postNormaliseSum <= z_postAddState; 63 | Opcode_NormaliseSum <= Opcode_AddState; 64 | 65 | //if(Opcode_AddState == PreProcess) begin 66 | 67 | idle_NormaliseSum <= idle_AddState; 68 | 69 | if (idle_AddState != put_idle) begin 70 | 71 | sout_NormaliseSum[31] <= sout_AddState[31]; 72 | sout_NormaliseSum[22:0] <= sout_AddState[22:0]; 73 | 74 | if (sum_AddState[27] == 1'b1) begin 75 | sout_NormaliseSum[30:23] <= s_exponent + 1; 76 | sum_NormaliseSum <= sum_AddState >> 1; 77 | end 78 | 79 | else if(sum_AddState[26:3] == 24'h000000) begin 80 | sout_NormaliseSum[30:23] <= 10'h382; 81 | end 82 | 83 | else if (sum_AddState[26:4] == 23'h000000) begin 84 | sout_NormaliseSum[30:23] <= s_exponent - 23; 85 | sum_NormaliseSum <= sum_AddState << 23; 86 | end 87 | 88 | else if (sum_AddState[26:5] == 22'h000000) begin 89 | sout_NormaliseSum[30:23] <= s_exponent - 22; 90 | sum_NormaliseSum <= sum_AddState << 22; 91 | end 92 | 93 | else if (sum_AddState[26:6] == 21'h000000) begin 94 | sout_NormaliseSum[30:23] <= s_exponent - 21; 95 | sum_NormaliseSum <= sum_AddState << 21; 96 | end 97 | 98 | else if (sum_AddState[26:7] == 20'h00000) begin 99 | sout_NormaliseSum[30:23] <= s_exponent - 20; 100 | sum_NormaliseSum <= sum_AddState << 20; 101 | end 102 | 103 | else if (sum_AddState[26:8] == 19'h00000) begin 104 | sout_NormaliseSum[30:23] <= s_exponent - 19; 105 | sum_NormaliseSum <= sum_AddState << 19; 106 | end 107 | 108 | else if (sum_AddState[26:9] == 18'h00000) begin 109 | sout_NormaliseSum[30:23] <= s_exponent - 18; 110 | sum_NormaliseSum <= sum_AddState << 18; 111 | end 112 | 113 | else if (sum_AddState[26:10] == 17'h00000) begin 114 | sout_NormaliseSum[30:23] <= s_exponent - 17; 115 | sum_NormaliseSum <= sum_AddState << 17; 116 | end 117 | 118 | else if (sum_AddState[26:11] == 16'h0000) begin 119 | sout_NormaliseSum[30:23] <= s_exponent - 16; 120 | sum_NormaliseSum <= sum_AddState << 16; 121 | end 122 | 123 | else if (sum_AddState[26:12] == 15'h0000) begin 124 | sout_NormaliseSum[30:23] <= s_exponent - 15; 125 | sum_NormaliseSum <= sum_AddState << 15; 126 | end 127 | 128 | else if (sum_AddState[26:13] == 14'h0000) begin 129 | sout_NormaliseSum[30:23] <= s_exponent - 14; 130 | sum_NormaliseSum <= sum_AddState << 14; 131 | end 132 | 133 | else if (sum_AddState[26:14] == 13'h0000) begin 134 | sout_NormaliseSum[30:23] <= s_exponent - 13; 135 | sum_NormaliseSum <= sum_AddState << 13; 136 | end 137 | 138 | else if (sum_AddState[26:15] == 12'h000) begin 139 | sout_NormaliseSum[30:23] <= s_exponent - 12; 140 | sum_NormaliseSum <= sum_AddState << 12; 141 | end 142 | 143 | else if (sum_AddState[26:16] == 11'h000) begin 144 | sout_NormaliseSum[30:23] <= s_exponent - 11; 145 | sum_NormaliseSum <= sum_AddState << 11; 146 | end 147 | 148 | else if (sum_AddState[26:17] == 10'h000) begin 149 | sout_NormaliseSum[30:23] <= s_exponent - 10; 150 | sum_NormaliseSum <= sum_AddState << 10; 151 | end 152 | 153 | else if (sum_AddState[26:18] == 9'h0000) begin 154 | sout_NormaliseSum[30:23] <= s_exponent - 9; 155 | sum_NormaliseSum <= sum_AddState << 9; 156 | end 157 | 158 | else if (sum_AddState[26:19] == 8'h00) begin 159 | sout_NormaliseSum[30:23] <= s_exponent - 8; 160 | sum_NormaliseSum <= sum_AddState << 8; 161 | end 162 | 163 | else if (sum_AddState[26:20] == 7'h00) begin 164 | sout_NormaliseSum[30:23] <= s_exponent - 7; 165 | sum_NormaliseSum <= sum_AddState << 7; 166 | end 167 | 168 | else if (sum_AddState[26:21] == 6'h00) begin 169 | sout_NormaliseSum[30:23] <= s_exponent - 6; 170 | sum_NormaliseSum <= sum_AddState << 6; 171 | end 172 | 173 | else if (sum_AddState[26:22] == 5'h00) begin 174 | sout_NormaliseSum[30:23] <= s_exponent - 5; 175 | sum_NormaliseSum <= sum_AddState << 5; 176 | end 177 | 178 | else if (sum_AddState[26:23] == 4'h0) begin 179 | sout_NormaliseSum[30:23] <= s_exponent - 4; 180 | sum_NormaliseSum <= sum_AddState << 4; 181 | end 182 | 183 | else if (sum_AddState[26:24] == 3'h0) begin 184 | sout_NormaliseSum[30:23] <= s_exponent - 3; 185 | sum_NormaliseSum <= sum_AddState << 3; 186 | end 187 | 188 | else if (sum_AddState[26:25] == 2'h0) begin 189 | sout_NormaliseSum[30:23] <= s_exponent - 2; 190 | sum_NormaliseSum <= sum_AddState << 2; 191 | end 192 | 193 | else if (sum_AddState[26] == 1'h0) begin 194 | sout_NormaliseSum[30:23] <= s_exponent - 1; 195 | sum_NormaliseSum <= sum_AddState << 1; 196 | end 197 | 198 | else begin 199 | sout_NormaliseSum[30:23] <= s_exponent; 200 | sum_NormaliseSum <= sum_AddState; 201 | end 202 | end 203 | 204 | else begin 205 | sout_NormaliseSum <= sout_AddState; 206 | sum_NormaliseSum <= 0; 207 | end 208 | 209 | //end 210 | end 211 | 212 | endmodule 213 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/SpecialCases.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:39:17 02/21/2015 7 | // Design Name: 8 | // Module Name: SpecialCases 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SpecialCases( 22 | input [31:0] ain_Special, 23 | input [31:0] bin_Special, 24 | input [31:0] cin_Special, 25 | input [1:0] mode_Special, 26 | input operation_Special, 27 | input NatLogFlag_Special, 28 | input [7:0] InsTagFSMOut, 29 | input reset, 30 | input clock, 31 | output reg [1:0] idle_Special = 1'b00, 32 | output reg [32:0] aout_Special, 33 | output reg [32:0] bout_Special, 34 | output reg [35:0] cout_Special, 35 | output reg [35:0] zout_Special, 36 | output reg [31:0] sout_Special, 37 | output reg [1:0] modeout_Special, 38 | output reg operationout_Special, 39 | output reg NatLogFlagout_Special, 40 | output reg [7:0] InsTag_Special 41 | ); 42 | 43 | wire a_sign; 44 | wire [7:0] a_exponent; 45 | wire [23:0] a_mantissa; 46 | 47 | wire b_sign; 48 | wire [7:0] b_exponent; 49 | wire [23:0] b_mantissa; 50 | 51 | wire c_sign; 52 | wire [7:0] c_exponent; 53 | wire [26:0] c_mantissa; 54 | 55 | assign a_sign = ain_Special[31]; 56 | assign a_exponent = {ain_Special[30:23] - 127}; 57 | assign a_mantissa = {1'b0, ain_Special[22:0]}; 58 | 59 | assign b_sign = {bin_Special[31]}; 60 | assign b_exponent = {bin_Special[30:23] - 127}; 61 | assign b_mantissa = {1'b0, bin_Special[22:0]}; 62 | 63 | assign c_sign = {cin_Special[31]}; 64 | assign c_exponent = {cin_Special[30:23] - 127}; 65 | assign c_mantissa = {cin_Special[22:0],3'd0}; 66 | 67 | parameter no_idle = 2'b00, 68 | allign_idle = 2'b01, 69 | put_idle = 2'b10; 70 | 71 | always @ (posedge clock) 72 | begin 73 | 74 | if(reset == 1'b1) begin 75 | idle_Special <= 1'b00; 76 | end 77 | 78 | else begin 79 | InsTag_Special <= InsTagFSMOut; 80 | modeout_Special <= mode_Special; 81 | operationout_Special <= operation_Special; 82 | NatLogFlagout_Special <= NatLogFlag_Special; 83 | 84 | //if a is NaN or b is NaN return NaN 85 | if ((a_exponent == 128 && a_mantissa != 0) || (b_exponent == 128 && b_mantissa != 0)) begin 86 | idle_Special <= allign_idle; 87 | aout_Special <= {a_sign,a_exponent+127,a_mantissa}; 88 | bout_Special <= {b_sign,b_exponent+127,b_mantissa}; 89 | cout_Special <= {c_sign,c_exponent+127,c_mantissa}; 90 | zout_Special <= {1'b1,8'd255,1'b1,26'd0}; 91 | sout_Special <= 0; 92 | //if a is inf return inf 93 | end else if (a_exponent == 128) begin 94 | idle_Special <= allign_idle; 95 | //if b is zero return NaN 96 | if ($signed(b_exponent == -127) && (b_mantissa == 0)) begin 97 | idle_Special <= allign_idle; 98 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 99 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 100 | cout_Special <= {c_sign,c_exponent,c_mantissa}; 101 | zout_Special <= {1'b1,8'd255,1'b1,26'd0}; 102 | sout_Special <= 0; 103 | end 104 | else begin 105 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 106 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 107 | cout_Special <= {c_sign,c_exponent,c_mantissa}; 108 | zout_Special <= {a_sign ^ b_sign,8'd255,27'd0}; 109 | sout_Special <= 0; 110 | end 111 | //if b is inf return inf 112 | end else if (b_exponent == 128) begin 113 | idle_Special <= allign_idle; 114 | aout_Special <= {a_sign,a_exponent,a_mantissa}; 115 | bout_Special <= {b_sign,b_exponent,b_mantissa}; 116 | cout_Special <= {c_sign,c_exponent,c_mantissa}; 117 | zout_Special <= {a_sign ^ b_sign,8'd255,27'd0}; 118 | sout_Special <= 0; 119 | //if a is zero return zero 120 | end else if (($signed(a_exponent) == -127) && (a_mantissa == 0)) begin 121 | idle_Special <= put_idle; 122 | aout_Special[32] <= a_sign; 123 | aout_Special[31:24] <= a_exponent+127; 124 | aout_Special[23] <= 1'b1; 125 | aout_Special[22:0] <= a_mantissa[22:0]; 126 | bout_Special[32] <= b_sign; 127 | bout_Special[31:24] <= b_exponent+127; 128 | bout_Special[23] <= 1'b1; 129 | bout_Special[22:0] <= b_mantissa[22:0]; 130 | cout_Special[35] <= c_sign; 131 | cout_Special[34:27] <= c_exponent+127; 132 | cout_Special[26:0] <= c_mantissa[26:0]; 133 | zout_Special <= {a_sign ^ b_sign,8'd0,27'd0}; 134 | sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]}; 135 | //if b is zero return zero 136 | end else if (($signed(b_exponent) == -127) && (b_mantissa == 0)) begin 137 | aout_Special[32] <= a_sign; 138 | aout_Special[31:24] <= a_exponent+127; 139 | aout_Special[23] <= 1'b1; 140 | aout_Special[22:0] <= a_mantissa[22:0]; 141 | bout_Special[32] <= b_sign; 142 | bout_Special[31:24] <= b_exponent+127; 143 | bout_Special[23] <= 1'b1; 144 | bout_Special[22:0] <= b_mantissa[22:0]; 145 | cout_Special[35] <= c_sign; 146 | cout_Special[35] <= c_sign; 147 | cout_Special[34:27] <= c_exponent+127; 148 | cout_Special[26:0] <= c_mantissa[26:0]; 149 | zout_Special <= {a_sign ^ b_sign,8'd0,27'd0}; 150 | sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]}; 151 | idle_Special <= put_idle; 152 | // If mode is linear, return 0 for product 153 | end else if (mode_Special == 2'b00) begin 154 | idle_Special <= put_idle; 155 | aout_Special[32] <= a_sign; 156 | aout_Special[31:24] <= a_exponent+127; 157 | aout_Special[23] <= 1'b1; 158 | aout_Special[22:0] <= a_mantissa[22:0]; 159 | bout_Special[32] <= b_sign; 160 | bout_Special[31:24] <= b_exponent+127; 161 | bout_Special[23] <= 1'b1; 162 | bout_Special[22:0] <= b_mantissa[22:0]; 163 | cout_Special[35] <= c_sign; 164 | cout_Special[34:27] <= c_exponent+127; 165 | cout_Special[26:0] <= c_mantissa[26:0]; 166 | zout_Special <= {a_sign ^ b_sign,8'd0,27'd0}; 167 | sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]}; 168 | end else begin 169 | //Denormalised Number 170 | cout_Special[35] <= c_sign; 171 | cout_Special[34:27] <= c_exponent+127; 172 | cout_Special[26:0] <= c_mantissa[26:0]; 173 | zout_Special <= 0; 174 | sout_Special <= 0; 175 | idle_Special <= no_idle; 176 | if ($signed(a_exponent) == -127) begin 177 | aout_Special <= {a_sign,-126,a_mantissa}; 178 | end else begin 179 | aout_Special[32] <= a_sign; 180 | aout_Special[31:24] <= a_exponent+127; 181 | aout_Special[23] <= 1'b1; 182 | aout_Special[22:0] <= a_mantissa[22:0]; 183 | end 184 | //Denormalised Number 185 | if ($signed(b_exponent) == -127) begin 186 | bout_Special <= {b_sign,-126,b_mantissa}; 187 | end else begin 188 | bout_Special[32] <= b_sign; 189 | bout_Special[31:24] <= b_exponent+127; 190 | bout_Special[23] <= 1'b1; 191 | bout_Special[22:0] <= b_mantissa[22:0]; 192 | end 193 | end 194 | end 195 | end 196 | 197 | endmodule 198 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/alu_y_pipelined.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:24:17 02/22/2015 7 | // Design Name: 8 | // Module Name: alu_y_pipelined 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module alu_y_pipelined( 22 | input [31:0] a_multiplicand, 23 | input [31:0] b_multiplier, 24 | input [31:0] c_addition, 25 | input [1:0] mode, 26 | input operation, 27 | input NatLogFlag_Execute, 28 | input [7:0] InsTagFSMOut, 29 | input reset, 30 | input clock, 31 | output [31:0] accumulate, 32 | output done 33 | ); 34 | 35 | wire [1:0] idle_Special,idle_Multiply,idle_NormaliseProd,idle_Allign,idle_Allign2,idle_AddState,idle_NormaliseSum; 36 | wire [32:0] aout_Special,bout_Special; 37 | wire [31:0] sout_Special,sout_Multiply,sout_NormaliseProd,sout_Allign,sout_Allign2,sout_AddState,sout_NormaliseSum; 38 | wire [35:0] cout_Special,cout_Multiply,cout_NormaliseProd,cout_Allign,cout_Allign2; 39 | wire [35:0] zout_Special,zout_Multiply,zout_NormaliseProd,zout_Allign,zout_Allign2; 40 | wire [1:0] modeout_Special,modeout_Multiply, modeout_NormaliseProd,modeout_Allign,modeout_Allign2,modeout_AddState,modeout_NormaliseSum,modeout_PackSum; 41 | wire operationout_Special,operationout_Multiply, operationout_NormaliseProd,operationout_Allign,operationout_Allign2,operationout_AddState,operationout_NormaliseSum,operationout_PackSum; 42 | wire [49:0] productout_Multiply, productout_NormaliseProd; 43 | wire [7:0] difference_Allign; 44 | wire [27:0] sum_AddState,sum_NormaliseSum; 45 | wire [7:0] InsTag_Special,InsTag_Multiply,InsTag_NormaliseProd,InsTag_Allign,InsTag_Allign2,InsTag_AddState,InsTag_NormaliseSum,InsTagYOut; 46 | wire NatLogFlag_Special,NatLogFlagout_Special,NatLogFlagout_Multiply,NatLogFlagout_NormaliseProd,NatLogFlagout_Allign,NatLogFlagout_Allign2,NatLogFlagout_AddState,NatLogFlagout_NormaliseSum; 47 | 48 | SpecialCases ALU_Y1 ( 49 | .ain_Special(a_multiplicand), 50 | .bin_Special(b_multiplier), 51 | .cin_Special(c_addition), 52 | .mode_Special(mode), 53 | .operation_Special(operation), 54 | .NatLogFlag_Special(NatLogFlag_Special), 55 | .InsTagFSMOut(InsTagFSMOut), 56 | .reset(reset), 57 | .clock(clock), 58 | .idle_Special(idle_Special), 59 | .aout_Special(aout_Special), 60 | .bout_Special(bout_Special), 61 | .cout_Special(cout_Special), 62 | .zout_Special(zout_Special), 63 | .sout_Special(sout_Special), 64 | .modeout_Special(modeout_Special), 65 | .operationout_Special(operationout_Special), 66 | .NatLogFlagout_Special(NatLogFlagout_Special), 67 | .InsTag_Special(InsTag_Special) 68 | ); 69 | 70 | MultiplyState_Y ALU_Y2 ( 71 | .aout_Special(aout_Special), 72 | .bout_Special(bout_Special), 73 | .cout_Special(cout_Special), 74 | .zout_Special(zout_Special), 75 | .sout_Special(sout_Special), 76 | .modeout_Special(modeout_Special), 77 | .operationout_Special(operationout_Special), 78 | .NatLogFlagout_Special(NatLogFlagout_Special), 79 | .InsTag_Special(InsTag_Special), 80 | .clock(clock), 81 | .idle_Special(idle_Special), 82 | .idle_Multiply(idle_Multiply), 83 | .cout_Multiply(cout_Multiply), 84 | .zout_Multiply(zout_Multiply), 85 | .sout_Multiply(sout_Multiply), 86 | .modeout_Multiply(modeout_Multiply), 87 | .operationout_Multiply(operationout_Multiply), 88 | .NatLogFlagout_Multiply(NatLogFlagout_Multiply), 89 | .productout_Multiply(productout_Multiply), 90 | .InsTag_Multiply(InsTag_Multiply) 91 | ); 92 | 93 | NormaliseProd ALU_Y3 ( 94 | .cout_Multiply(cout_Multiply), 95 | .zout_Multiply(zout_Multiply), 96 | .sout_Multiply(sout_Multiply), 97 | .productout_Multiply(productout_Multiply), 98 | .modeout_Multiply(modeout_Multiply), 99 | .operationout_Multiply(operationout_Multiply), 100 | .NatLogFlagout_Multiply(NatLogFlagout_Multiply), 101 | .InsTag_Multiply(InsTag_Multiply), 102 | .clock(clock), 103 | .idle_Multiply(idle_Multiply), 104 | .idle_NormaliseProd(idle_NormaliseProd), 105 | .cout_NormaliseProd(cout_NormaliseProd), 106 | .zout_NormaliseProd(zout_NormaliseProd), 107 | .sout_NormaliseProd(sout_NormaliseProd), 108 | .modeout_NormaliseProd(modeout_NormaliseProd), 109 | .operationout_NormaliseProd(operationout_NormaliseProd), 110 | .NatLogFlagout_NormaliseProd(NatLogFlagout_NormaliseProd), 111 | .productout_NormaliseProd(productout_NormaliseProd), 112 | .InsTag_NormaliseProd(InsTag_NormaliseProd) 113 | ); 114 | 115 | Allign ALU_Y4 ( 116 | .idle_NormaliseProd(idle_NormaliseProd), 117 | .cout_NormaliseProd(cout_NormaliseProd), 118 | .zout_NormaliseProd(zout_NormaliseProd), 119 | .sout_NormaliseProd(sout_NormaliseProd), 120 | .modeout_NormaliseProd(modeout_NormaliseProd), 121 | .operationout_NormaliseProd(operationout_NormaliseProd), 122 | .NatLogFlagout_NormaliseProd(NatLogFlagout_NormaliseProd), 123 | .productout_NormaliseProd(productout_NormaliseProd), 124 | .InsTag_NormaliseProd(InsTag_NormaliseProd), 125 | .clock(clock), 126 | .idle_Allign(idle_Allign), 127 | .cout_Allign(cout_Allign), 128 | .zout_Allign(zout_Allign), 129 | .sout_Allign(sout_Allign), 130 | .modeout_Allign(modeout_Allign), 131 | .operationout_Allign(operationout_Allign), 132 | .NatLogFlagout_Allign(NatLogFlagout_Allign), 133 | .difference_Allign(difference_Allign), 134 | .InsTag_Allign(InsTag_Allign) 135 | ); 136 | 137 | Allign2 ALU_Y5 ( 138 | .idle_Allign(idle_Allign), 139 | .cout_Allign(cout_Allign), 140 | .zout_Allign(zout_Allign), 141 | .sout_Allign(sout_Allign), 142 | .modeout_Allign(modeout_Allign), 143 | .operationout_Allign(operationout_Allign), 144 | .NatLogFlagout_Allign(NatLogFlagout_Allign), 145 | .difference_Allign(difference_Allign), 146 | .InsTag_Allign(InsTag_Allign), 147 | .clock(clock), 148 | .idle_Allign2(idle_Allign2), 149 | .cout_Allign2(cout_Allign2), 150 | .zout_Allign2(zout_Allign2), 151 | .sout_Allign2(sout_Allign2), 152 | .modeout_Allign2(modeout_Allign2), 153 | .operationout_Allign2(operationout_Allign2), 154 | .NatLogFlagout_Allign2(NatLogFlagout_Allign2), 155 | .InsTag_Allign2(InsTag_Allign2) 156 | ); 157 | 158 | AddState ALU_Y6 ( 159 | .idle_Allign2(idle_Allign2), 160 | .cout_Allign2(cout_Allign2), 161 | .zout_Allign2(zout_Allign2), 162 | .sout_Allign2(sout_Allign2), 163 | .modeout_Allign2(modeout_Allign2), 164 | .operationout_Allign2(operationout_Allign2), 165 | .NatLogFlagout_Allign2(NatLogFlagout_Allign2), 166 | .InsTag_Allign2(InsTag_Allign2), 167 | .clock(clock), 168 | .idle_AddState(idle_AddState), 169 | .sout_AddState(sout_AddState), 170 | .modeout_AddState(modeout_AddState), 171 | .operationout_AddState(operationout_AddState), 172 | .NatLogFlagout_AddState(NatLogFlagout_AddState), 173 | .sum_AddState(sum_AddState), 174 | .InsTag_AddState(InsTag_AddState) 175 | ); 176 | 177 | NormaliseSum ALU_Y7 ( 178 | .idle_AddState(idle_AddState), 179 | .sout_AddState(sout_AddState), 180 | .modeout_AddState(modeout_AddState), 181 | .operationout_AddState(operationout_AddState), 182 | .NatLogFlagout_AddState(NatLogFlagout_AddState), 183 | .sum_AddState(sum_AddState), 184 | .InsTag_AddState(InsTag_AddState), 185 | .clock(clock), 186 | .idle_NormaliseSum(idle_NormaliseSum), 187 | .sout_NormaliseSum(sout_NormaliseSum), 188 | .modeout_NormaliseSum(modeout_NormaliseSum), 189 | .operationout_NormaliseSum(operationout_NormaliseSum), 190 | .NatLogFlagout_NormaliseSum(NatLogFlagout_NormaliseSum), 191 | .sum_NormaliseSum(sum_NormaliseSum), 192 | .InsTag_NormaliseSum(InsTag_NormaliseSum) 193 | ); 194 | 195 | PackSum_y ALU_Y8 ( 196 | .idle_NormaliseSum(idle_NormaliseSum), 197 | .sout_NormaliseSum(sout_NormaliseSum), 198 | .modeout_NormaliseSum(modeout_NormaliseSum), 199 | .operationout_NormaliseSum(operationout_NormaliseSum), 200 | .sum_NormaliseSum(sum_NormaliseSum), 201 | .InsTag_NormaliseSum(InsTag_NormaliseSum), 202 | .clock(clock), 203 | .sout_PackSum(accumulate), 204 | .done(done) 205 | ); 206 | 207 | endmodule 208 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/alu_x_pipelined.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:02:23 02/21/2015 7 | // Design Name: 8 | // Module Name: alu_x_pipelined 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module alu_x_pipelined( 22 | input [31:0] a_multiplicand, 23 | input [31:0] b_multiplier, 24 | input [31:0] c_addition, 25 | input [1:0] mode, 26 | input operation, 27 | input NatLogFlag_Execute, 28 | input [7:0] InsTagFSMOut, 29 | input reset, 30 | input clock, 31 | output [31:0] accumulate, 32 | output [1:0] mode_out, 33 | output operation_out, 34 | output NatLogFlag_iter, 35 | output [7:0] InsTagXOut 36 | ); 37 | 38 | wire [1:0] idle_Special,idle_Multiply,idle_NormaliseProd,idle_Allign,idle_Allign2,idle_AddState,idle_NormaliseSum; 39 | wire [32:0] aout_Special,bout_Special; 40 | wire [31:0] sout_Special,sout_Multiply,sout_NormaliseProd,sout_Allign,sout_Allign2,sout_AddState,sout_NormaliseSum; 41 | wire [35:0] cout_Special,cout_Multiply,cout_NormaliseProd,cout_Allign,cout_Allign2; 42 | wire [35:0] zout_Special,zout_Multiply,zout_NormaliseProd,zout_Allign,zout_Allign2; 43 | wire [1:0] modeout_Special,modeout_Multiply, modeout_NormaliseProd,modeout_Allign,modeout_Allign2,modeout_AddState,modeout_NormaliseSum,modeout_PackSum; 44 | wire operationout_Special,operationout_Multiply, operationout_NormaliseProd,operationout_Allign,operationout_Allign2,operationout_AddState,operationout_NormaliseSum,operationout_PackSum; 45 | wire [49:0] productout_Multiply, productout_NormaliseProd; 46 | wire [7:0] difference_Allign; 47 | wire [27:0] sum_AddState,sum_NormaliseSum; 48 | wire [7:0] InsTag_Special,InsTag_Multiply,InsTag_NormaliseProd,InsTag_Allign,InsTag_Allign2,InsTag_AddState,InsTag_NormaliseSum; 49 | wire NatLogFlag_Special,NatLogFlagout_Special,NatLogFlagout_Multiply,NatLogFlagout_NormaliseProd,NatLogFlagout_Allign,NatLogFlagout_Allign2,NatLogFlagout_AddState,NatLogFlagout_NormaliseSum; 50 | 51 | SpecialCases ALU_X1 ( 52 | .ain_Special(a_multiplicand), 53 | .bin_Special(b_multiplier), 54 | .cin_Special(c_addition), 55 | .mode_Special(mode), 56 | .operation_Special(operation), 57 | .NatLogFlag_Special(NatLogFlag_Special), 58 | .InsTagFSMOut(InsTagFSMOut), 59 | .reset(reset), 60 | .clock(clock), 61 | .idle_Special(idle_Special), 62 | .aout_Special(aout_Special), 63 | .bout_Special(bout_Special), 64 | .cout_Special(cout_Special), 65 | .zout_Special(zout_Special), 66 | .sout_Special(sout_Special), 67 | .modeout_Special(modeout_Special), 68 | .operationout_Special(operationout_Special), 69 | .NatLogFlagout_Special(NatLogFlagout_Special), 70 | .InsTag_Special(InsTag_Special) 71 | ); 72 | 73 | MultiplyState ALU_X2 ( 74 | .aout_Special(aout_Special), 75 | .bout_Special(bout_Special), 76 | .cout_Special(cout_Special), 77 | .zout_Special(zout_Special), 78 | .sout_Special(sout_Special), 79 | .modeout_Special(modeout_Special), 80 | .operationout_Special(operationout_Special), 81 | .NatLogFlagout_Special(NatLogFlagout_Special), 82 | .InsTag_Special(InsTag_Special), 83 | .clock(clock), 84 | .idle_Special(idle_Special), 85 | .idle_Multiply(idle_Multiply), 86 | .cout_Multiply(cout_Multiply), 87 | .zout_Multiply(zout_Multiply), 88 | .sout_Multiply(sout_Multiply), 89 | .modeout_Multiply(modeout_Multiply), 90 | .operationout_Multiply(operationout_Multiply), 91 | .NatLogFlagout_Multiply(NatLogFlagout_Multiply), 92 | .productout_Multiply(productout_Multiply), 93 | .InsTag_Multiply(InsTag_Multiply) 94 | ); 95 | 96 | NormaliseProd ALU_X3 ( 97 | .cout_Multiply(cout_Multiply), 98 | .zout_Multiply(zout_Multiply), 99 | .sout_Multiply(sout_Multiply), 100 | .productout_Multiply(productout_Multiply), 101 | .modeout_Multiply(modeout_Multiply), 102 | .operationout_Multiply(operationout_Multiply), 103 | .NatLogFlagout_Multiply(NatLogFlagout_Multiply), 104 | .InsTag_Multiply(InsTag_Multiply), 105 | .clock(clock), 106 | .idle_Multiply(idle_Multiply), 107 | .idle_NormaliseProd(idle_NormaliseProd), 108 | .cout_NormaliseProd(cout_NormaliseProd), 109 | .zout_NormaliseProd(zout_NormaliseProd), 110 | .sout_NormaliseProd(sout_NormaliseProd), 111 | .modeout_NormaliseProd(modeout_NormaliseProd), 112 | .operationout_NormaliseProd(operationout_NormaliseProd), 113 | .NatLogFlagout_NormaliseProd(NatLogFlagout_NormaliseProd), 114 | .productout_NormaliseProd(productout_NormaliseProd), 115 | .InsTag_NormaliseProd(InsTag_NormaliseProd) 116 | ); 117 | 118 | Allign ALU_X4 ( 119 | .idle_NormaliseProd(idle_NormaliseProd), 120 | .cout_NormaliseProd(cout_NormaliseProd), 121 | .zout_NormaliseProd(zout_NormaliseProd), 122 | .sout_NormaliseProd(sout_NormaliseProd), 123 | .modeout_NormaliseProd(modeout_NormaliseProd), 124 | .operationout_NormaliseProd(operationout_NormaliseProd), 125 | .NatLogFlagout_NormaliseProd(NatLogFlagout_NormaliseProd), 126 | .productout_NormaliseProd(productout_NormaliseProd), 127 | .InsTag_NormaliseProd(InsTag_NormaliseProd), 128 | .clock(clock), 129 | .idle_Allign(idle_Allign), 130 | .cout_Allign(cout_Allign), 131 | .zout_Allign(zout_Allign), 132 | .sout_Allign(sout_Allign), 133 | .modeout_Allign(modeout_Allign), 134 | .operationout_Allign(operationout_Allign), 135 | .NatLogFlagout_Allign(NatLogFlagout_Allign), 136 | .difference_Allign(difference_Allign), 137 | .InsTag_Allign(InsTag_Allign) 138 | ); 139 | 140 | Allign2 ALU_X5 ( 141 | .idle_Allign(idle_Allign), 142 | .cout_Allign(cout_Allign), 143 | .zout_Allign(zout_Allign), 144 | .sout_Allign(sout_Allign), 145 | .modeout_Allign(modeout_Allign), 146 | .operationout_Allign(operationout_Allign), 147 | .NatLogFlagout_Allign(NatLogFlagout_Allign), 148 | .difference_Allign(difference_Allign), 149 | .InsTag_Allign(InsTag_Allign), 150 | .clock(clock), 151 | .idle_Allign2(idle_Allign2), 152 | .cout_Allign2(cout_Allign2), 153 | .zout_Allign2(zout_Allign2), 154 | .sout_Allign2(sout_Allign2), 155 | .modeout_Allign2(modeout_Allign2), 156 | .operationout_Allign2(operationout_Allign2), 157 | .NatLogFlagout_Allign2(NatLogFlagout_Allign2), 158 | .InsTag_Allign2(InsTag_Allign2) 159 | ); 160 | 161 | AddState ALU_X6 ( 162 | .idle_Allign2(idle_Allign2), 163 | .cout_Allign2(cout_Allign2), 164 | .zout_Allign2(zout_Allign2), 165 | .sout_Allign2(sout_Allign2), 166 | .modeout_Allign2(modeout_Allign2), 167 | .operationout_Allign2(operationout_Allign2), 168 | .NatLogFlagout_Allign2(NatLogFlagout_Allign2), 169 | .InsTag_Allign2(InsTag_Allign2), 170 | .clock(clock), 171 | .idle_AddState(idle_AddState), 172 | .sout_AddState(sout_AddState), 173 | .modeout_AddState(modeout_AddState), 174 | .operationout_AddState(operationout_AddState), 175 | .NatLogFlagout_AddState(NatLogFlagout_AddState), 176 | .sum_AddState(sum_AddState), 177 | .InsTag_AddState(InsTag_AddState) 178 | ); 179 | 180 | NormaliseSum ALU_X7 ( 181 | .idle_AddState(idle_AddState), 182 | .sout_AddState(sout_AddState), 183 | .modeout_AddState(modeout_AddState), 184 | .operationout_AddState(operationout_AddState), 185 | .NatLogFlagout_AddState(NatLogFlagout_AddState), 186 | .sum_AddState(sum_AddState), 187 | .InsTag_AddState(InsTag_AddState), 188 | .clock(clock), 189 | .idle_NormaliseSum(idle_NormaliseSum), 190 | .sout_NormaliseSum(sout_NormaliseSum), 191 | .modeout_NormaliseSum(modeout_NormaliseSum), 192 | .operationout_NormaliseSum(operationout_NormaliseSum), 193 | .NatLogFlagout_NormaliseSum(NatLogFlagout_NormaliseSum), 194 | .sum_NormaliseSum(sum_NormaliseSum), 195 | .InsTag_NormaliseSum(InsTag_NormaliseSum) 196 | ); 197 | 198 | PackSum ALU_X8 ( 199 | .idle_NormaliseSum(idle_NormaliseSum), 200 | .sout_NormaliseSum(sout_NormaliseSum), 201 | .modeout_NormaliseSum(modeout_NormaliseSum), 202 | .operationout_NormaliseSum(operationout_NormaliseSum), 203 | .NatLogFlagout_NormaliseSum(NatLogFlagout_NormaliseSum), 204 | .sum_NormaliseSum(sum_NormaliseSum), 205 | .InsTag_NormaliseSum(InsTag_NormaliseSum), 206 | .clock(clock), 207 | .sout_PackSum(accumulate), 208 | .modeout_PackSum(mode_out), 209 | .operationout_PackSum(operation_out), 210 | .NatLogFlagout_PackSum(NatLogFlag_iter), 211 | .InsTag_PackSum(InsTagXOut) 212 | ); 213 | endmodule 214 | -------------------------------------------------------------------------------- /HCORDIC_Verilog/FSM_1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:13:59 02/21/2015 7 | // Design Name: 8 | // Module Name: FSM_1 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module FSM_1( 22 | input [31:0] x, // x Input to FSM from Mux 23 | input [31:0] y, // y Input to FSM from Mux 24 | input [31:0] z, // z Input to FSM from Mux 25 | input [31:0] k, // k Input to FSM from Mux 26 | input [1:0] mode, // Linear: 00 Hyperbolic: 11 Circular: 01 27 | input operation, // operation = 1 is rotation. operation = 0 is vectoring 28 | input NatLogFlagout_Mux, 29 | input reset, 30 | input clock, 31 | input [7:0] InsTagMuxOut, 32 | output reg [1:0] enable_LUT = 2'b00, // Enable bit set by FSM to enable LUT 33 | output reg [7:0] address, // Address field to LUT 34 | output reg [3:0] state_FSM2, // next state of FSM 35 | output reg [31:0] x_FSM1, // x_FSM1 enters FSM2 36 | output reg [31:0] y_FSM1, // y_FSM1 enters FSM2 37 | output reg [31:0] z_FSM1, // z_FSM1 enters FSM2 38 | output reg [31:0] k_FSM1, // k_FSM1 enters FSM2 39 | output reg [31:0] theta_FSM1, // theta Output to ALU 40 | output reg [31:0] kappa_FSM1, // kappa Output to ALU 41 | output reg [31:0] delta_FSM1, // delta Output to ALU 42 | output reg [1:0] mode_FSM1, 43 | output reg operation_FSM1, 44 | output reg NatLogFlagout_FSM1, 45 | output reg [7:0] InsTagFSM1Out 46 | ); 47 | 48 | reg [7:0] exponent, exponentbar; 49 | 50 | parameter rotation =1'b1, 51 | vectoring =1'b0; 52 | 53 | parameter mode_circular =2'b01, 54 | mode_linear =2'b00, 55 | mode_hyperbolic=2'b11; 56 | 57 | parameter Linear_Rotation = 4'd0, 58 | Hyperbolic_Rotation_by_1 = 4'd1, 59 | Circular_Rotation_by_1 = 4'd2, 60 | Rotation_with_small_theta = 4'd3, 61 | Circular_Rotation_with_table = 4'd4, 62 | Hyperbolic_Rotation_with_table = 4'd5, 63 | Linear_Vectoring = 4'd6, 64 | Hyperbolic_Vectoring_by_1 = 4'd7, 65 | Circular_Vectoring_by_1 = 4'd8, 66 | Vectoring_by_small_fraction = 4'd9, 67 | Circular_Vectoring_with_table = 4'd10, 68 | Hyperbolic_Vectoring_with_table= 4'd11, 69 | Idle_state = 4'd12, 70 | ConvergeRotation = 4'd13, 71 | ConvergeVectoring = 4'd14; 72 | 73 | parameter LUT_Disable = 2'b00, 74 | LUT_Rotation = 2'b01, 75 | LUT_Vectoring = 2'b10, 76 | LUT_LinVec = 2'b11; 77 | 78 | reg [3:0] state_FSM1; 79 | 80 | always @ (*) 81 | begin 82 | 83 | case (operation) 84 | rotation : exponent <= 8'b01111111 - z[30:23]; 85 | vectoring : exponent <= y[30:23] - x[30:23]; 86 | default : exponent <= y[30:23] - x[30:23]; 87 | endcase 88 | 89 | exponentbar <= ~exponent + 8'b00000001; 90 | end 91 | 92 | always @ (posedge clock) 93 | begin 94 | //////////////////////////////////////////////////////////////////////////// 95 | 96 | if (reset == 1'b1) begin 97 | enable_LUT <= 2'b00; 98 | end 99 | 100 | else begin 101 | x_FSM1 <= x; 102 | y_FSM1 <= y; 103 | z_FSM1 <= z; 104 | k_FSM1 <= k; 105 | mode_FSM1 <= mode; 106 | operation_FSM1 <= operation; 107 | InsTagFSM1Out <= InsTagMuxOut; 108 | NatLogFlagout_FSM1 <= NatLogFlagout_Mux; 109 | 110 | if(operation==rotation && mode==mode_linear) begin 111 | state_FSM1 <= Linear_Rotation; 112 | theta_FSM1[30:0] <= z[30:0]; 113 | delta_FSM1[30:0] <= z[30:0]; 114 | theta_FSM1[31] <= ~z[31]; 115 | delta_FSM1[31] <= ~z[31]; 116 | kappa_FSM1 <= 32'h3F800000; 117 | enable_LUT <= LUT_Disable; 118 | state_FSM2 <= Idle_state; 119 | end 120 | 121 | else if (operation==rotation && mode==mode_hyperbolic && z[30:23] >= 8'b01111111) begin 122 | state_FSM1 <= Hyperbolic_Rotation_by_1; 123 | theta_FSM1 <= 32'hBF800000; 124 | delta_FSM1 <= 32'hBF42F7D6; 125 | kappa_FSM1 <= 32'h3FC583AB; 126 | enable_LUT <= LUT_Disable; 127 | state_FSM2 <= Idle_state; 128 | end 129 | 130 | else if (operation==rotation && mode==mode_circular && z[30:23] >=8'b01111111) begin 131 | state_FSM1 <= Circular_Rotation_by_1; 132 | theta_FSM1 <= 32'hBF800000; 133 | delta_FSM1 <= 32'hBFC75923; 134 | kappa_FSM1 <= 32'h3F0A5142; 135 | enable_LUT <= LUT_Disable; 136 | state_FSM2 <= Idle_state; 137 | end 138 | 139 | // Bring this back in pre decode in InputMux.v to avoid bringing it into FSM and passing a bubble through entire pipeline 140 | /*else if (operation==rotation && mode !=mode_linear && z[30:23] <= 8'b00000000) begin 141 | state_FSM1 <= ConvergeRotation; 142 | end*/ 143 | 144 | else if (operation==rotation && mode !=mode_linear && z[30:23] <= 8'b01110011) begin 145 | state_FSM1 <= Rotation_with_small_theta; 146 | theta_FSM1[30:0] <= z[30:0]; 147 | delta_FSM1[30:0] <= z[30:0]; 148 | theta_FSM1[31] <= ~z[31]; 149 | delta_FSM1[31] <= ~z[31]; 150 | kappa_FSM1 <= 32'h3F800000; 151 | enable_LUT <= LUT_Disable; 152 | state_FSM2 <= Idle_state; 153 | end 154 | 155 | else if (operation==rotation && mode==mode_circular && z[30:23]<8'b01111111 && z[30:23]>8'b01110011) begin 156 | state_FSM1 <= Circular_Rotation_with_table; 157 | address[7:4] <= exponent[3:0]; 158 | address[3:0] <= z[22:19]; 159 | enable_LUT <= LUT_Rotation; 160 | state_FSM2 <= Circular_Rotation_with_table; 161 | end 162 | 163 | else if (operation==rotation && mode==mode_hyperbolic && z[30:23]<8'b01111111 && z[30:23]>8'b01110011) begin 164 | state_FSM1 <= Hyperbolic_Rotation_with_table; 165 | address[7:4] <= exponent[3:0]; 166 | address[3:0] <= z[22:19]; 167 | enable_LUT <= LUT_Rotation; 168 | state_FSM2 <= Hyperbolic_Rotation_with_table; 169 | end 170 | 171 | else if (operation==vectoring && mode==mode_linear && (exponentbar[7] == 1'b1 || exponentbar < 8'b00010101)) begin 172 | state_FSM1 <= Linear_Vectoring; 173 | address[7:4] <= y[22:19]; 174 | address[3:0] <= x[22:19]; 175 | kappa_FSM1 <= 32'h3F800004; 176 | enable_LUT <= LUT_LinVec; 177 | state_FSM2 <= Linear_Vectoring; 178 | end 179 | 180 | else if (operation==vectoring && mode==mode_hyperbolic && exponent[7] != 1'b1 &&(exponent > 0 || (exponent == 0 && y[22:0]>=x[22:0]))) begin 181 | state_FSM1 <= Hyperbolic_Vectoring_by_1; 182 | theta_FSM1 <= 32'h3fea77cb; 183 | delta_FSM1 <= 32'h3F733333; 184 | kappa_FSM1 <= 32'h3e9fdf38; 185 | enable_LUT <= LUT_Disable; 186 | state_FSM2 <= Idle_state; 187 | end 188 | 189 | else if (operation==vectoring && mode==mode_circular && exponent[7] != 1'b1 && (exponent > 0 || (exponent == 0 && y[22:0]>=x[22:0]))) begin 190 | state_FSM1 <= Circular_Vectoring_by_1; 191 | theta_FSM1 <= 32'h3F490FDB; 192 | delta_FSM1 <= 32'h3F800000; 193 | kappa_FSM1 <= 32'h3F3504F2; 194 | enable_LUT <= LUT_Disable; 195 | state_FSM2 <= Idle_state; 196 | end 197 | 198 | /*else if (operation==vectoring && exponentbar[7] == 1'b0 && exponentbar >= 8'b00001111) begin 199 | state<= ConvergeVectoring; 200 | end*/ 201 | 202 | else if (operation==vectoring && mode!=mode_linear && exponentbar == 8'b00001110) begin 203 | state_FSM1 <= Vectoring_by_small_fraction; 204 | address[7:4] <= x[22:19]; 205 | address[3:0] <= y[22:19]; 206 | kappa_FSM1 <= 32'h3F800000; 207 | enable_LUT <= LUT_LinVec; 208 | state_FSM2 <= Vectoring_by_small_fraction; 209 | end 210 | 211 | else if (operation==vectoring && mode==mode_circular && exponentbar >= 8'b00000000 && exponentbar < 8'b00001110) begin 212 | state_FSM1 <= Circular_Vectoring_with_table; 213 | address[7:4] <= ~exponent[3:0] + 4'b0001; 214 | address[3:2] <= y[22:21]; 215 | address[1:0] <= x[22:21]; 216 | enable_LUT <= LUT_Vectoring; 217 | state_FSM2 <= Circular_Vectoring_with_table; 218 | end 219 | 220 | else if (operation==vectoring && mode==mode_hyperbolic && exponentbar >= 8'b00000000 && exponentbar < 8'b00001110) begin 221 | state_FSM1 <= Hyperbolic_Vectoring_with_table; 222 | address[7:4] <= ~exponent[3:0] + 4'b0001; 223 | address[3:2] <= y[22:21]; 224 | address[1:0] <= x[22:21]; 225 | enable_LUT <= LUT_Vectoring; 226 | state_FSM2 <= Hyperbolic_Vectoring_with_table; 227 | end 228 | 229 | else begin 230 | state_FSM1 <= Idle_state; 231 | enable_LUT <= LUT_Disable; 232 | state_FSM2 <= Idle_state; 233 | end 234 | end 235 | end 236 | 237 | endmodule 238 | -------------------------------------------------------------------------------- /Testbench Generation code/Testbench code/test.py: -------------------------------------------------------------------------------- 1 | import math,sys 2 | from math import pi 3 | import numpy 4 | from numpy import sin 5 | def ieee754 (a): 6 | rep = 0 7 | #sign bit 8 | if (a<0): 9 | rep = 1<<31 10 | a = math.fabs(a) 11 | if (a >= 1): 12 | #exponent 13 | exp = int(math.log(a,2)) 14 | rep = rep|((exp+127)<<23) 15 | 16 | #mantissa 17 | temp = a / pow(2,exp) - 1 18 | i = 22 19 | while i>=0: 20 | temp = temp * 2 21 | if temp > 1: 22 | rep = rep | (1<=0: 39 | temp = temp * 2 40 | if temp > 1: 41 | rep = rep | (1<>23 50 | ex = ex - 127 51 | i = 1 52 | p = 22 53 | num = 1.0 54 | #print('%d \n' % (ex)) 55 | while (p != -1) : 56 | i = 1<

>p 58 | #print dig 59 | num += (dig * pow(2,p-23)) 60 | p -= 1 61 | num = num * pow(2,ex) 62 | i = 1<<31 63 | sign = a & i 64 | if (sign) : 65 | num = num * -1 66 | print num 67 | return num 68 | 69 | def convert2hex_of_xilinx(hex_number,num_of_bits): 70 | hex_number = hex_number.split('x') 71 | hex_number = hex_number[1] 72 | hex_number = str(hex_number) 73 | hex_number = str(num_of_bits)+"'h"+ hex_number +';' 74 | return hex_number 75 | 76 | 77 | #def generate_testbench(value): 78 | 79 | 80 | if __name__ == "__main__": 81 | 82 | time =0; 83 | i = 0; 84 | j = 0; 85 | for time in range(0,100): 86 | i = i+1 87 | j = j+1 88 | if j == 255: 89 | j = 0; 90 | else: 91 | j = j; 92 | if i ==9: 93 | i = 0 94 | else: 95 | i=i 96 | InsTagIn = j 97 | InsTagIn = hex(InsTagIn) 98 | InsTagIn = InsTagIn.split('x') 99 | InsTagIn = InsTagIn[1] 100 | instagin = str("\tInsTagIn = ") 101 | InsTagIn = instagin + "8'h"+str(InsTagIn) + ";" 102 | Opcode = i 103 | Opcode = hex(Opcode) 104 | Opcode = Opcode.split('x') 105 | Opcode = Opcode[1] 106 | opcode = str("\tOpcode = ") 107 | Opcode = opcode +"4'h"+ str(Opcode) +";" 108 | delay = 20 109 | delay = str(delay) 110 | delay = '#' + delay 111 | x = str(" x_processor= ") 112 | x = delay +x 113 | y = str("\ty_processor= ") 114 | z = str("\tz_processor= ") 115 | x_processor = 0.01*time 116 | x_float1 = float(x_processor) 117 | x_processor = ieee754(x_float1) 118 | x_processor = hex(x_processor) 119 | x_processor = x_processor.split('x') 120 | x_processor = x_processor[1] 121 | x_processor = str(x_processor) 122 | y_processor = 0.1 + 0.005*time 123 | y_float1 = float(y_processor) 124 | y_processor = ieee754(y_float1) 125 | y_processor = hex(y_processor) 126 | y_processor = y_processor.split('x') 127 | y_processor = y_processor[1] 128 | y_processor = str(y_processor) 129 | z_float = time*pi/180 130 | z_float1 = float(z_float) 131 | z_processor = ieee754(z_float1) 132 | z_processor = hex(z_processor) 133 | z_processor = z_processor.split('x') 134 | z_processor = z_processor[1] 135 | z_processor = str(z_processor) 136 | x = x+"32'h"+x_processor +";" 137 | y = y+"32'h"+y_processor +";" 138 | z = z+"32'h"+z_processor +";" 139 | print x 140 | print y 141 | print z 142 | print Opcode 143 | print InsTagIn 144 | if i ==0: 145 | sine = math.sin(z_float1) 146 | sine = ieee754(sine) 147 | sine = hex(sine) 148 | sine = convert2hex_of_xilinx(sine,32) 149 | cosine = math.cos(z_float1) 150 | cosine = ieee754(cosine) 151 | cosine = hex(cosine) 152 | cosine = convert2hex_of_xilinx(cosine,32) 153 | print "\t" +"x_out ="+ str(cosine) 154 | print "\t" +"y_out ="+ str(sine) 155 | elif i==1: 156 | sineh = math.sinh(z_float1) 157 | sineh = ieee754(sineh) 158 | sineh = hex(sineh) 159 | sineh = convert2hex_of_xilinx(sineh,32) 160 | cosineh = math.cosh(z_float1) 161 | cosineh = ieee754(cosineh) 162 | cosineh = hex(cosineh) 163 | cosineh = convert2hex_of_xilinx(cosineh,32) 164 | print "\t" +"x_out = "+ str(cosineh) 165 | print "\t" +"y_out = "+ str(sineh) 166 | elif i==2: 167 | atangent = math.atan(y_float1) 168 | atangent = ieee754(atangent) 169 | atangent = hex(atangent) 170 | atangent = convert2hex_of_xilinx(atangent,32) 171 | print "\t" + str(atangent) 172 | elif i==3: 173 | atangenth = math.atanh(y_float1) 174 | atangenth = ieee754(atangenth) 175 | atangenth = hex(atangenth) 176 | atangenth = convert2hex_of_xilinx(atangenth,32) 177 | print "\t" + str(atangenth) 178 | elif i==4: 179 | exponent = math.exp(z_float1) 180 | exponent = ieee754(exponent) 181 | exponent = hex(exponent) 182 | exponent = convert2hex_of_xilinx(exponent,32) 183 | 184 | print "\t" + str(exponent) 185 | elif i==5: 186 | squareroot=math.sqrt(math.pow(x_float1,2)+math.pow(y_float1,2)) 187 | squareroot= ieee754(squareroot) 188 | squareroot= hex(squareroot) 189 | squareroot =convert2hex_of_xilinx(squareroot,32) 190 | print "\t" + str(squareroot) 191 | elif i==6: 192 | division = y_float1/x_float1 193 | division = ieee754(division) 194 | division = hex(division) 195 | division = convert2hex_of_xilinx(division,32) 196 | print "\t" + str(division) 197 | elif i==7: 198 | tangent = math.tan(z_float1) 199 | tangent = ieee754(tangent) 200 | tangent = hex(tangent) 201 | tangent = convert2hex_of_xilinx(tangent,32) 202 | print "\t" + str(tangent) 203 | elif i==8: 204 | tangenth = math.tanh(z_float1) 205 | tangenth = ieee754(tangenth) 206 | tangenth = hex(tangenth) 207 | tangenth = convert2hex_of_xilinx(tangenth,32) 208 | print "\t" + str(tangenth) 209 | 210 | 211 | 212 | 213 | 214 | 215 | '''tr = open('theta_rot.txt'w')dc = open('DeltaCir_rot.txt','w') 216 | dh = open('DeltaHyper_rot.txt','w') 217 | kcr = open('KappaCir_rot.txt','w') 218 | khr = open('KappaHyper_rot.txt','w') 219 | 220 | #dv = open('Delta_Vec_nonlin.txt','w') 221 | #dlv = open('DeltaLin_Vec.txt','w') 222 | #tcv = open('ThetaCir_Vec.txt','w') 223 | #thv = open('ThetaHyp_Vec.txt','w') 224 | #kcv = open('KappaCir_Vec.txt','w') 225 | #khv = open('KappaHyp_Vec.txt','w') 226 | address = 0 227 | 228 | while address <= 255 : 229 | #extracting relevant bits 230 | #For nonlinear Vectoring 231 | #den = (((address & 0x3)<<21) + 0x1FFFFF) + 0x3F800000 232 | #num = ((address & 0xC)<<19) + 0x3F800000 233 | #ex = ((address & 0xF0)>>4) 234 | 235 | #for linear vectoring 236 | #denl = (((address & 0xF)<<19) + 0x7FFFF) + 0x3F800000 237 | #numl = ((address & 0xF0)<<15) + 0x3F800000 238 | #print ('%08X \t %08X \t' % (denl,numl)) 239 | #for Rotation 240 | ze = (0x7F - ((address & 0xF0)>>4)) << 23 241 | zs = ((address & 0xF)<<19) + ze 242 | #print ("0x%08X \t 0x%08X" % (zs,ze)) 243 | 244 | #numf = ieee754tofloat(num) 245 | #print ("Numerator (in float): %f" % (numf)) 246 | #denf = ieee754tofloat(den) 247 | #print ("Denominator (in float): %f" % (denf)) 248 | #zsf = ieee754tofloat(zs) 249 | #print ("%f \t %f" % (denf,numf)) 250 | 251 | #deltav = (numf/denf) 252 | theta_r = zs 253 | #if deltav > +11: 254 | # deltav = 0.999999999 255 | #print hex(ieee754(deltav)) 256 | 257 | #print address 258 | #print('%08X \t' % (ieee754(deltav))) 259 | #dv.write ('%08X \n' % (ieee754(deltav))) 260 | #print ('%f \t %08X \n' % (deltav,ieee754(deltav))) 261 | #tcv.write('%08X \n' % (ieee754(math.atan(deltav)))) 262 | #print ('%f \t %08X \n' % (math.atan(deltav),ieee754(math.atan(deltav)))) 263 | #thv.write('%08X \n' % (ieee754(math.atanh(deltav)))) 264 | #print ('%f \t %08X \n' % (math.atanh(deltav),ieee754(math.atanh(deltav)))) 265 | #kcv.write('%08X \n' % (ieee754(math.cos(math.atan(deltav)) + pow(10,-7) ))) 266 | #print ('%f \t %08X \n' % (math.cos(math.atan(deltav)) + pow(10,-7),ieee754(math.cos(math.atan(deltav)) + pow(10,-7) ))) 267 | #khv.write('%08X \n' % (ieee754(math.cosh(math.atanh(deltav)) + pow(10,-7) ))) 268 | #print ('%f \t %08X \n' % (math.cosh(math.atanh(deltav)),ieee754(math.cosh(math.atanh(deltav))))) 269 | #dlv.write('%08X \n' % (ieee754(deltav))) 270 | 271 | #print ('%08X \t' % (theta_r)) 272 | #Writing calculated values into the LUT file for Rotation 273 | tr.write("%08X\n" % (theta_r)) 274 | #print ("%08X \t %f\n" % (theta_r,ieee754tofloat(theta_r))) 275 | dc.write("%08X\n" % ((ieee754(math.tan(ieee754tofloat(theta_r)))))) 276 | #print ("%08X \t %f\n" % ((ieee754(math.tan(ieee754tofloat(theta_r)))),math.tan(ieee754tofloat(theta_r)))) 277 | dh.write("%08X\n" % ((ieee754(math.tanh(ieee754tofloat(theta_r)))))) 278 | #print ("%08X \t %f\n" % ((ieee754(math.tanh(ieee754tofloat(theta_r)))),math.tanh(ieee754tofloat(theta_r)))) 279 | kcr.write("%08X\n" % ((ieee754(math.cos(ieee754tofloat(theta_r))) + pow(10,-7) ))) 280 | #print ("%08X \t %f\n" % ((ieee754(math.cos(ieee754tofloat(theta_r)))),math.cos(ieee754tofloat(theta_r)))) 281 | khr.write("%08X\n" % (ieee754(math.cosh(ieee754tofloat(theta_r)) + pow(10,-7) ))) 282 | #print ("%08X \t %f\n" % (ieee754(math.cosh(ieee754tofloat(theta_r))),math.cosh(ieee754tofloat(theta_r)))) 283 | 284 | #print("%08X\n" % (theta_r)) 285 | #print("%08X\n" % ((ieee754(math.tan(ieee754tofloat(theta_r)))))) 286 | #print("%08X\n" % ((ieee754(math.tanh(ieee754tofloat(theta_r)))))) 287 | #print("%08X\n" % ((ieee754(1/math.cos(ieee754tofloat(theta_r)))))) 288 | address += 1 289 | #print "done"''' 290 | -------------------------------------------------------------------------------- /Testbench Generation code/Testbench Files/test_nodiv,tan.py: -------------------------------------------------------------------------------- 1 | import math,sys 2 | from math import pi 3 | import numpy 4 | from numpy import sin 5 | def ieee754 (a): 6 | rep = 0 7 | #sign bit 8 | if (a<0): 9 | rep = 1<<31 10 | a = math.fabs(a) 11 | if (a >= 1): 12 | #exponent 13 | exp = int(math.log(a,2)) 14 | rep = rep|((exp+127)<<23) 15 | 16 | #mantissa 17 | temp = a / pow(2,exp) - 1 18 | i = 22 19 | while i>=0: 20 | temp = temp * 2 21 | if temp > 1: 22 | rep = rep | (1<=0: 39 | temp = temp * 2 40 | if temp > 1: 41 | rep = rep | (1<>23 50 | ex = ex - 127 51 | i = 1 52 | p = 22 53 | num = 1.0 54 | #print('%d \n' % (ex)) 55 | while (p != -1) : 56 | i = 1<

>p 58 | #print dig 59 | num += (dig * pow(2,p-23)) 60 | p -= 1 61 | num = num * pow(2,ex) 62 | i = 1<<31 63 | sign = a & i 64 | if (sign) : 65 | num = num * -1 66 | print num 67 | return num 68 | 69 | def convert2hex_of_xilinx(hex_number,num_of_bits): 70 | hex_number = hex_number.split('x') 71 | hex_number = hex_number[1] 72 | hex_number = str(hex_number) 73 | hex_number = str(num_of_bits)+"'h"+ hex_number +';' 74 | return hex_number 75 | 76 | 77 | #def generate_testbench(value): 78 | 79 | 80 | if __name__ == "__main__": 81 | 82 | time =0; 83 | i = 0; 84 | j = 0; 85 | for time in range(0,100): 86 | i = i+1 87 | j = j+1 88 | if j == 255: 89 | j = 0; 90 | else: 91 | j = j; 92 | if i ==10: 93 | i = 0 94 | elif i==6: 95 | i = i+3 96 | else: 97 | i=i 98 | InsTagIn = j 99 | InsTagIn = hex(InsTagIn) 100 | InsTagIn = InsTagIn.split('x') 101 | InsTagIn = InsTagIn[1] 102 | instagin = str("\tInsTagIn = ") 103 | InsTagIn = instagin + "8'h"+str(InsTagIn) + ";" 104 | Opcode = i 105 | Opcode = hex(Opcode) 106 | Opcode = Opcode.split('x') 107 | Opcode = Opcode[1] 108 | opcode = str("\tOpcode = ") 109 | Opcode = opcode +"4'h"+ str(Opcode) +";" 110 | delay = 20 111 | delay = str(delay) 112 | delay = '#' + delay 113 | x = str(" x_processor= ") 114 | x = delay +x 115 | y = str("\ty_processor= ") 116 | z = str("\tz_processor= ") 117 | x_processor = 0.01*time 118 | x_float1 = float(x_processor) 119 | x_processor = ieee754(x_float1) 120 | x_processor = hex(x_processor) 121 | x_processor = x_processor.split('x') 122 | x_processor = x_processor[1] 123 | x_processor = str(x_processor) 124 | y_processor = 0.1 + 0.005*time 125 | y_float1 = float(y_processor) 126 | y_processor = ieee754(y_float1) 127 | y_processor = hex(y_processor) 128 | y_processor = y_processor.split('x') 129 | y_processor = y_processor[1] 130 | y_processor = str(y_processor) 131 | z_float = time*pi/180 132 | z_float1 = float(z_float) 133 | z_processor = ieee754(z_float1) 134 | z_processor = hex(z_processor) 135 | z_processor = z_processor.split('x') 136 | z_processor = z_processor[1] 137 | z_processor = str(z_processor) 138 | x = x+"32'h"+x_processor +";" 139 | y = y+"32'h"+y_processor +";" 140 | z = z+"32'h"+z_processor +";" 141 | print x 142 | print y 143 | print z 144 | print Opcode 145 | print InsTagIn 146 | if i ==0: 147 | sine = math.sin(z_float1) 148 | sine = ieee754(sine) 149 | sine = hex(sine) 150 | sine = convert2hex_of_xilinx(sine,32) 151 | cosine = math.cos(z_float1) 152 | cosine = ieee754(cosine) 153 | cosine = hex(cosine) 154 | cosine = convert2hex_of_xilinx(cosine,32) 155 | print "\t" +"x_out ="+ str(cosine) 156 | print "\t" +"y_out ="+ str(sine) 157 | elif i==1: 158 | sineh = math.sinh(z_float1) 159 | sineh = ieee754(sineh) 160 | sineh = hex(sineh) 161 | sineh = convert2hex_of_xilinx(sineh,32) 162 | cosineh = math.cosh(z_float1) 163 | cosineh = ieee754(cosineh) 164 | cosineh = hex(cosineh) 165 | cosineh = convert2hex_of_xilinx(cosineh,32) 166 | print "\t" +"x_out = "+ str(cosineh) 167 | print "\t" +"y_out = "+ str(sineh) 168 | elif i==2: 169 | atangent = math.atan(y_float1) 170 | atangent = ieee754(atangent) 171 | atangent = hex(atangent) 172 | atangent = convert2hex_of_xilinx(atangent,32) 173 | print "\t" +"z_out = " + str(atangent) 174 | elif i==3: 175 | atangenth = math.atanh(y_float1) 176 | atangenth = ieee754(atangenth) 177 | atangenth = hex(atangenth) 178 | atangenth = convert2hex_of_xilinx(atangenth,32) 179 | print "\t" +"z_out = "+ str(atangenth) 180 | elif i==4: 181 | exponent = math.exp(z_float1) 182 | exponent = ieee754(exponent) 183 | exponent = hex(exponent) 184 | exponent = convert2hex_of_xilinx(exponent,32) 185 | 186 | print "\t" +"x_out = "+ str(exponent) 187 | print "\t" +"y_out = "+ str(exponent) 188 | 189 | elif i==5: 190 | squareroot=math.sqrt(math.pow(x_float1,2)+math.pow(y_float1,2)) 191 | squareroot= ieee754(squareroot) 192 | squareroot= hex(squareroot) 193 | squareroot =convert2hex_of_xilinx(squareroot,32) 194 | print "\t" +"x_out = "+ str(squareroot) 195 | elif i==6: 196 | division = y_float1/x_float1 197 | division = ieee754(division) 198 | division = hex(division) 199 | division = convert2hex_of_xilinx(division,32) 200 | print "\t" + str(division) 201 | elif i==7: 202 | tangent = math.tan(z_float1) 203 | tangent = ieee754(tangent) 204 | tangent = hex(tangent) 205 | tangent = convert2hex_of_xilinx(tangent,32) 206 | print "\t" + str(tangent) 207 | elif i==8: 208 | tangenth = math.tanh(z_float1) 209 | tangenth = ieee754(tangenth) 210 | tangenth = hex(tangenth) 211 | tangenth = convert2hex_of_xilinx(tangenth,32) 212 | print "\t" + str(tangenth) 213 | 214 | 215 | 216 | 217 | 218 | 219 | '''tr = open('theta_rot.txt'w')dc = open('DeltaCir_rot.txt','w') 220 | dh = open('DeltaHyper_rot.txt','w') 221 | kcr = open('KappaCir_rot.txt','w') 222 | khr = open('KappaHyper_rot.txt','w') 223 | 224 | #dv = open('Delta_Vec_nonlin.txt','w') 225 | #dlv = open('DeltaLin_Vec.txt','w') 226 | #tcv = open('ThetaCir_Vec.txt','w') 227 | #thv = open('ThetaHyp_Vec.txt','w') 228 | #kcv = open('KappaCir_Vec.txt','w') 229 | #khv = open('KappaHyp_Vec.txt','w') 230 | address = 0 231 | 232 | while address <= 255 : 233 | #extracting relevant bits 234 | #For nonlinear Vectoring 235 | #den = (((address & 0x3)<<21) + 0x1FFFFF) + 0x3F800000 236 | #num = ((address & 0xC)<<19) + 0x3F800000 237 | #ex = ((address & 0xF0)>>4) 238 | 239 | #for linear vectoring 240 | #denl = (((address & 0xF)<<19) + 0x7FFFF) + 0x3F800000 241 | #numl = ((address & 0xF0)<<15) + 0x3F800000 242 | #print ('%08X \t %08X \t' % (denl,numl)) 243 | #for Rotation 244 | ze = (0x7F - ((address & 0xF0)>>4)) << 23 245 | zs = ((address & 0xF)<<19) + ze 246 | #print ("0x%08X \t 0x%08X" % (zs,ze)) 247 | 248 | #numf = ieee754tofloat(num) 249 | #print ("Numerator (in float): %f" % (numf)) 250 | #denf = ieee754tofloat(den) 251 | #print ("Denominator (in float): %f" % (denf)) 252 | #zsf = ieee754tofloat(zs) 253 | #print ("%f \t %f" % (denf,numf)) 254 | 255 | #deltav = (numf/denf) 256 | theta_r = zs 257 | #if deltav > +11: 258 | # deltav = 0.999999999 259 | #print hex(ieee754(deltav)) 260 | 261 | #print address 262 | #print('%08X \t' % (ieee754(deltav))) 263 | #dv.write ('%08X \n' % (ieee754(deltav))) 264 | #print ('%f \t %08X \n' % (deltav,ieee754(deltav))) 265 | #tcv.write('%08X \n' % (ieee754(math.atan(deltav)))) 266 | #print ('%f \t %08X \n' % (math.atan(deltav),ieee754(math.atan(deltav)))) 267 | #thv.write('%08X \n' % (ieee754(math.atanh(deltav)))) 268 | #print ('%f \t %08X \n' % (math.atanh(deltav),ieee754(math.atanh(deltav)))) 269 | #kcv.write('%08X \n' % (ieee754(math.cos(math.atan(deltav)) + pow(10,-7) ))) 270 | #print ('%f \t %08X \n' % (math.cos(math.atan(deltav)) + pow(10,-7),ieee754(math.cos(math.atan(deltav)) + pow(10,-7) ))) 271 | #khv.write('%08X \n' % (ieee754(math.cosh(math.atanh(deltav)) + pow(10,-7) ))) 272 | #print ('%f \t %08X \n' % (math.cosh(math.atanh(deltav)),ieee754(math.cosh(math.atanh(deltav))))) 273 | #dlv.write('%08X \n' % (ieee754(deltav))) 274 | 275 | #print ('%08X \t' % (theta_r)) 276 | #Writing calculated values into the LUT file for Rotation 277 | tr.write("%08X\n" % (theta_r)) 278 | #print ("%08X \t %f\n" % (theta_r,ieee754tofloat(theta_r))) 279 | dc.write("%08X\n" % ((ieee754(math.tan(ieee754tofloat(theta_r)))))) 280 | #print ("%08X \t %f\n" % ((ieee754(math.tan(ieee754tofloat(theta_r)))),math.tan(ieee754tofloat(theta_r)))) 281 | dh.write("%08X\n" % ((ieee754(math.tanh(ieee754tofloat(theta_r)))))) 282 | #print ("%08X \t %f\n" % ((ieee754(math.tanh(ieee754tofloat(theta_r)))),math.tanh(ieee754tofloat(theta_r)))) 283 | kcr.write("%08X\n" % ((ieee754(math.cos(ieee754tofloat(theta_r))) + pow(10,-7) ))) 284 | #print ("%08X \t %f\n" % ((ieee754(math.cos(ieee754tofloat(theta_r)))),math.cos(ieee754tofloat(theta_r)))) 285 | khr.write("%08X\n" % (ieee754(math.cosh(ieee754tofloat(theta_r)) + pow(10,-7) ))) 286 | #print ("%08X \t %f\n" % (ieee754(math.cosh(ieee754tofloat(theta_r))),math.cosh(ieee754tofloat(theta_r)))) 287 | 288 | #print("%08X\n" % (theta_r)) 289 | #print("%08X\n" % ((ieee754(math.tan(ieee754tofloat(theta_r)))))) 290 | #print("%08X\n" % ((ieee754(math.tanh(ieee754tofloat(theta_r)))))) 291 | #print("%08X\n" % ((ieee754(1/math.cos(ieee754tofloat(theta_r)))))) 292 | address += 1 293 | #print "done"''' 294 | --------------------------------------------------------------------------------