├── .ci.yml ├── .github ├── scripts │ ├── ci.sh │ └── package_cores.py └── workflows │ ├── ghpages.yml │ ├── pipeline.yml │ └── release.yml ├── .gitignore ├── .pre-commit-config.yaml ├── CHANGELOG.md ├── LICENSE ├── README.md ├── docs ├── Makefile ├── puppeteer-config.json ├── requirements.txt └── source │ ├── _extensions │ └── kpm_plugin.py │ ├── advanced_options.md │ ├── conf.py │ ├── config.md │ ├── description_files.md │ ├── developers_guide │ ├── checks.md │ ├── config.md │ ├── fusesocbuilder.md │ ├── future_enhancements.md │ ├── generator.md │ ├── inline_kpm_howto.md │ ├── interconnect.md │ ├── interface.md │ ├── internal_representation.md │ ├── ipxact-design.md │ ├── ir-examples.md │ ├── repo.md │ ├── setup.md │ ├── style.md │ └── tests.md │ ├── examples.md │ ├── fusesoc.md │ ├── getting_started.md │ ├── img │ ├── external_port.png │ ├── getting_started_project.png │ ├── invalid_connection.png │ ├── kpm_button_fullscreen.png │ ├── kpm_buttons.png │ ├── logo.png │ ├── node_parameters.png │ ├── pwm.png │ ├── save_graph_kpm.png │ ├── side_bar_kpm.png │ ├── soc-diagram-anim.gif │ └── topwrap--github-readme.png │ ├── index.md │ ├── inference.md │ ├── installation.md │ ├── interconnect_gen.md │ ├── introduction.md │ └── user_repositories.md ├── examples ├── constant │ ├── Makefile │ ├── README.md │ ├── ipcores │ │ └── ibuf.yaml │ ├── project.yaml │ └── sources │ │ └── ibuf.v ├── getting_started_demo │ ├── Makefile │ ├── README.md │ ├── design.v │ ├── project.yaml │ └── verilogs │ │ ├── simple_core_1.v │ │ └── simple_core_2.v ├── hdmi │ ├── Makefile │ ├── README.md │ ├── constr │ │ ├── snickerdoodle.xdc │ │ └── zynq_video_board.xdc │ ├── core.yaml.j2 │ ├── ipcores │ │ ├── axi_dispctrl.core │ │ ├── axi_dispctrl.yaml │ │ ├── clock_crossing.yaml │ │ ├── dma_axi_in_axis_out.core │ │ ├── dma_axi_in_axis_out.yaml │ │ ├── hdmi_tx.core │ │ ├── hdmi_tx.yaml │ │ ├── litex_mmcm.core │ │ ├── litex_mmcm.yaml │ │ ├── proc_sys_reset.yaml │ │ ├── ps7.yaml │ │ └── verilog-axi.core │ ├── project.yaml │ ├── requirements.txt │ └── sources │ │ ├── clock_crossing.v │ │ ├── prebuild.sh │ │ └── ps7.v ├── hierarchy │ ├── Makefile │ ├── README.md │ ├── kpm_complex_subgraph_view.png │ ├── kpm_hierarchy_design.png │ ├── project.yaml │ └── repo │ │ └── cores │ │ ├── c_mod_1 │ │ ├── c_mod_1.yaml │ │ └── srcs │ │ │ └── c_mod_1.v │ │ ├── c_mod_2 │ │ ├── c_mod_2.yaml │ │ └── srcs │ │ │ └── c_mod_2.v │ │ ├── c_mod_3 │ │ ├── c_mod_3.yaml │ │ └── srcs │ │ │ └── c_mod_3.v │ │ ├── s1_mod_1 │ │ ├── s1_mod_1.yaml │ │ └── srcs │ │ │ └── s1_mod_1.v │ │ ├── s1_mod_2 │ │ ├── s1_mod_2.yaml │ │ └── srcs │ │ │ └── s1_mod_2.v │ │ ├── s1_mod_3 │ │ ├── s1_mod_3.yaml │ │ └── srcs │ │ │ └── s1_mod_3.v │ │ ├── s2_mod_1 │ │ ├── s2_mod_1.yaml │ │ └── srcs │ │ │ └── s2_mod_1.v │ │ └── s2_mod_2 │ │ ├── s2_mod_2.yaml │ │ └── srcs │ │ └── s2_mod_2.v ├── inout │ ├── Makefile │ ├── README.md │ ├── core.yaml.j2 │ ├── project.yaml │ ├── requirements.txt │ └── sources │ │ ├── ibuf.v │ │ ├── iobuf.v │ │ ├── obuf.v │ │ └── zynq.xdc ├── ir_examples │ ├── README.md │ ├── SoC_AXI │ │ ├── Makefile │ │ ├── ir │ │ │ ├── axi.py │ │ │ ├── design.py │ │ │ ├── simple_manager.py │ │ │ └── uart.py │ │ └── kpm_build.py │ ├── advanced │ │ ├── Makefile │ │ ├── ir │ │ │ ├── design.py │ │ │ ├── proc.py │ │ │ ├── seq_sci_bridge.py │ │ │ ├── sseq.py │ │ │ └── types.py │ │ └── kpm_build.py │ ├── hierarchical │ │ ├── Makefile │ │ ├── design.yaml │ │ ├── ips │ │ │ ├── adder.yaml │ │ │ ├── d_ff.yaml │ │ │ └── debouncer.yaml │ │ ├── ipxact │ │ │ └── antmicro.com │ │ │ │ └── hierarchical │ │ │ │ ├── adder │ │ │ │ └── 1.0 │ │ │ │ │ └── adder.1.0.xml │ │ │ │ ├── d_ff │ │ │ │ └── 1.0 │ │ │ │ │ └── d_ff.1.0.xml │ │ │ │ ├── debouncer │ │ │ │ └── 1.0 │ │ │ │ │ └── debouncer.1.0.xml │ │ │ │ ├── encoder │ │ │ │ └── 1.0 │ │ │ │ │ ├── encoder.1.0.xml │ │ │ │ │ ├── encoder.design.1.0.xml │ │ │ │ │ └── encoder.designcfg.1.0.xml │ │ │ │ ├── four_bit_counter │ │ │ │ └── 1.0 │ │ │ │ │ ├── four_bit_counter.1.0.xml │ │ │ │ │ ├── four_bit_counter.design.1.0.xml │ │ │ │ │ └── four_bit_counter.designcfg.1.0.xml │ │ │ │ ├── proc │ │ │ │ └── 1.0 │ │ │ │ │ ├── proc.1.0.xml │ │ │ │ │ ├── proc.design.1.0.xml │ │ │ │ │ └── proc.designcfg.1.0.xml │ │ │ │ └── top │ │ │ │ └── 1.0 │ │ │ │ ├── top.1.0.xml │ │ │ │ ├── top.design.1.0.xml │ │ │ │ └── top.designcfg.1.0.xml │ │ └── ir │ │ │ ├── adder.py │ │ │ ├── d_ff.py │ │ │ ├── debouncer.py │ │ │ └── design.py │ ├── interconnect │ │ ├── Makefile │ │ ├── design.yaml │ │ ├── ips │ │ │ ├── cpu.yaml │ │ │ ├── dsp.yaml │ │ │ ├── mem.yaml │ │ │ └── wb_passthrough.yaml │ │ ├── ipxact │ │ │ ├── antmicro.com │ │ │ │ └── interconnect │ │ │ │ │ ├── cpu │ │ │ │ │ └── 1.0 │ │ │ │ │ │ └── cpu.1.0.xml │ │ │ │ │ ├── dsp │ │ │ │ │ └── 1.0 │ │ │ │ │ │ └── dsp.1.0.xml │ │ │ │ │ ├── interconnect │ │ │ │ │ └── wishbone_interconnect1.xml │ │ │ │ │ ├── mem │ │ │ │ │ └── 1.0 │ │ │ │ │ │ └── mem.1.0.xml │ │ │ │ │ └── top │ │ │ │ │ └── 1.0 │ │ │ │ │ ├── top.1.0.xml │ │ │ │ │ ├── top.design.1.0.xml │ │ │ │ │ └── top.designcfg.1.0.xml │ │ │ └── opencores.org │ │ │ │ └── interface │ │ │ │ ├── wishbone_b4.xml │ │ │ │ └── wishbone_b4_def.xml │ │ └── ir │ │ │ ├── cpu.py │ │ │ ├── design.py │ │ │ ├── dsp.py │ │ │ ├── mem.py │ │ │ └── wishbone.py │ ├── interface │ │ ├── Makefile │ │ ├── design.yaml │ │ ├── ips │ │ │ ├── receiver.yaml │ │ │ └── streamer.yaml │ │ ├── ipxact │ │ │ └── antmicro.com │ │ │ │ └── interface │ │ │ │ ├── receiver │ │ │ │ └── 1.0 │ │ │ │ │ └── receiver.1.0.xml │ │ │ │ ├── streamer │ │ │ │ └── 1.0 │ │ │ │ │ └── streamer.1.0.xml │ │ │ │ └── top │ │ │ │ └── 1.0 │ │ │ │ ├── top.1.0.xml │ │ │ │ ├── top.design.1.0.xml │ │ │ │ └── top.designcfg.1.0.xml │ │ └── ir │ │ │ ├── axistream.py │ │ │ ├── design.py │ │ │ ├── receiver.py │ │ │ └── streamer.py │ ├── modules.py │ └── simple │ │ ├── Makefile │ │ ├── design.yaml │ │ ├── ips │ │ ├── 2mux.yaml │ │ └── lfsr_gen.yaml │ │ ├── ipxact │ │ └── antmicro.com │ │ │ └── simple │ │ │ ├── 2mux │ │ │ └── 1.0 │ │ │ │ ├── 2mux.1.0.xml │ │ │ │ └── two_mux.xml │ │ │ ├── lfsr_gen │ │ │ └── 1.2 │ │ │ │ └── lfsr_gen.1.2.xml │ │ │ └── top │ │ │ └── 1.0 │ │ │ ├── top.1.0.xml │ │ │ ├── top.design.1.0.xml │ │ │ └── top.designcfg.1.0.xml │ │ └── ir │ │ ├── design.py │ │ ├── lfsr_gen.py │ │ └── two_mux.py ├── pwm │ ├── Makefile │ ├── README.md │ ├── core.yaml.j2 │ ├── ipcores │ │ ├── litex_pwm.yaml │ │ ├── proc_sys_reset.yaml │ │ ├── ps7.yaml │ │ └── verilog-axi.core │ ├── project.yaml │ ├── requirements.txt │ └── sources │ │ ├── litex_pwm.v │ │ ├── pre_symbiflow.sh │ │ ├── pre_vivado.sh │ │ ├── ps7.v │ │ └── zynq.xdc ├── soc │ ├── Makefile │ ├── README.md │ ├── expected-waveform.svg │ ├── helloworld.asm │ ├── ir │ │ ├── crg.py │ │ ├── design.py │ │ ├── mem.py │ │ ├── uart.py │ │ ├── vex_riscv.py │ │ └── wishbone.py │ ├── project.yaml │ ├── sim.cpp │ ├── simple_soc.tcl │ ├── simple_soc.xdc │ ├── sources │ │ ├── VexRiscv.v │ │ ├── crg.v │ │ ├── mem.v │ │ └── wb_uart.v │ └── verilator.mk └── user_repository │ ├── Makefile │ ├── README.md │ ├── project.yaml │ ├── repo │ ├── cores │ │ ├── example_core1 │ │ │ ├── .core.yaml │ │ │ └── core1.yaml │ │ └── example_core2 │ │ │ ├── .core.yaml │ │ │ └── core2.yaml │ └── interfaces │ │ └── interface1.yaml │ └── topwrap.yaml ├── noxfile.py ├── pyproject.toml ├── tests ├── __init__.py ├── data │ ├── data_build │ │ ├── DMATop.yaml │ │ ├── axi_dispctrl_v1_0.yaml │ │ ├── clog2 │ │ │ ├── clog2_design.yaml │ │ │ ├── clog2_design2.yaml │ │ │ ├── clog2_tester.v │ │ │ ├── clog2_tester.yaml │ │ │ ├── clog2_tester2.v │ │ │ └── clog2_tester2.yaml │ │ ├── design.yaml │ │ ├── hierarchy │ │ │ ├── counter.yaml │ │ │ ├── design.yaml │ │ │ └── pwm.yaml │ │ └── interconnect │ │ │ ├── ipcores │ │ │ ├── VexRiscv.yaml │ │ │ ├── crg.yaml │ │ │ ├── litex_mem.yaml │ │ │ └── soc.yaml │ │ │ ├── project.yaml │ │ │ └── sources │ │ │ ├── crg.v │ │ │ ├── mem.v │ │ │ └── soc.v │ ├── data_ir │ │ ├── frontend │ │ │ └── kpm │ │ │ │ ├── complex_flow.json │ │ │ │ ├── front_spec.json │ │ │ │ ├── interconnect_graph.json │ │ │ │ ├── io_inference_flow.json │ │ │ │ ├── ir_hier_flow.json │ │ │ │ ├── ir_interconn_flow.json │ │ │ │ ├── ir_interface_flow.json │ │ │ │ └── ir_simple_flow.json │ │ └── inference │ │ │ ├── ahb_if.py │ │ │ ├── axi_if.py │ │ │ ├── axilite_if.py │ │ │ ├── bbox_if.py │ │ │ ├── guineveer_axi_to_ahb.py │ │ │ ├── guineveer_i3c.py │ │ │ ├── guineveer_intercon.py │ │ │ ├── guineveer_sram.py │ │ │ ├── guineveer_uart.py │ │ │ ├── guineveer_veer_el2.py │ │ │ ├── pulp_axi_cdc.py │ │ │ ├── pulp_axi_demux.py │ │ │ ├── pulp_types.py │ │ │ └── util.py │ ├── data_kpm │ │ ├── conversions │ │ │ └── complex │ │ │ │ ├── dataflow_complex.json │ │ │ │ ├── project_complex.yaml │ │ │ │ └── specification_complex.json │ │ ├── dataflow_tests │ │ │ ├── dataflow_conn_subgraph_metanode.json │ │ │ ├── dataflow_connected_unnamed_metanode.json │ │ │ ├── dataflow_duplicate_ext_input_ifaces.json │ │ │ ├── dataflow_duplicate_ips.json │ │ │ ├── dataflow_duplicate_metanode_names.json │ │ │ ├── dataflow_hierarchical_duplicate_names.json │ │ │ ├── dataflow_inouts_connections.json │ │ │ ├── dataflow_invalid_params.json │ │ │ ├── dataflow_meta_to_meta_conn.json │ │ │ ├── dataflow_multiple_invalid_designs.json │ │ │ ├── dataflow_port_to_multiple_external_metanodes.json │ │ │ ├── dataflow_subgraph_multiple_external_metanodes.json │ │ │ └── dataflow_unconn_hierarchy.json │ │ └── examples │ │ │ ├── hdmi │ │ │ ├── dataflow_hdmi.json │ │ │ └── specification_hdmi.json │ │ │ ├── hierarchy │ │ │ ├── dataflow_hierarchy.json │ │ │ └── specification_hierarchy.json │ │ │ └── pwm │ │ │ ├── dataflow_pwm.json │ │ │ └── specification_pwm.json │ └── data_parse │ │ ├── DMATop.v │ │ ├── axi_axil_adapter.v │ │ ├── axi_axil_adapter.yaml │ │ ├── axi_dispctrl_v1_0.vhd │ │ ├── ip_core_invalid.yaml │ │ ├── ip_core_valid.yaml │ │ ├── seg7_4d_ctrl.v │ │ └── test_relative_paths.yaml ├── test_cli │ ├── __init__.py │ └── test_commands.py ├── test_config.py ├── test_repo │ ├── __init__.py │ ├── test_files.py │ ├── test_repo.py │ └── test_user_repo.py ├── test_util.py ├── tests_build │ ├── __init__.py │ └── test_interconnect.py ├── tests_generator │ └── test_axi_generator.py ├── tests_ir │ ├── __init__.py │ ├── backend │ │ ├── test_interconnect_generation.py │ │ ├── test_kpm.py │ │ ├── test_kpm_examples.py │ │ └── test_sv.py │ ├── frontend │ │ ├── __init__.py │ │ ├── test_automatic.py │ │ ├── test_ir_examples.py │ │ ├── test_kpm.py │ │ ├── test_kpm_examples.py │ │ ├── test_sv.py │ │ └── test_yaml.py │ ├── inference │ │ ├── test_guineveer.py │ │ ├── test_inference.py │ │ ├── test_mapping.py │ │ └── test_port.py │ ├── test_ir.py │ └── test_kpm_non_destructive.py ├── tests_kpm │ ├── __init__.py │ ├── common.py │ ├── conftest.py │ ├── test_kpm_client.py │ └── test_kpm_validation.py ├── tests_parse │ ├── __init__.py │ ├── test_common_serdes.py │ ├── test_interface.py │ └── test_ip_desc.py └── update_test_data.py └── topwrap ├── __init__.py ├── __main__.py ├── backend ├── backend.py ├── generator.py ├── kpm │ ├── backend.py │ ├── common.py │ ├── dataflow.py │ └── specification.py └── sv │ ├── backend.py │ ├── common.py │ ├── design.py │ ├── generators.py │ ├── templates │ ├── design.j2 │ ├── interface.j2 │ └── package.j2 │ └── wishbone_interconnect.py ├── builtin ├── cores │ ├── axi_axil_adapter │ │ ├── .core.yaml │ │ └── core.yaml │ ├── axi_interconnect │ │ ├── .core.yaml │ │ └── core.yaml │ ├── axi_protocol_converter │ │ ├── .core.yaml │ │ └── core.yaml │ ├── axis_async_fifo │ │ ├── .core.yaml │ │ └── core.yaml │ └── axis_dwidth_converter │ │ ├── .core.yaml │ │ └── core.yaml ├── default_config.yaml └── interfaces │ ├── axi3.yaml │ ├── axi4.yaml │ ├── axilite.yaml │ ├── axistream.yaml │ └── wishbone.yaml ├── cli ├── __init__.py ├── main.py └── repo.py ├── common_serdes.py ├── config.py ├── frontend ├── automatic.py ├── frontend.py ├── kpm │ ├── common.py │ ├── dataflow.py │ ├── frontend.py │ └── specification.py ├── sv │ ├── frontend.py │ └── module.py └── yaml │ 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