├── README.md ├── power_spec ├── InstructionBuffer.upf ├── RamConfigurable.upf ├── PipeLineReg.upf ├── ExecutionPipe_SC.upf ├── RenameLane.upf ├── IssueLane.upf ├── Decode_PISA.upf ├── RamConfigurableAL.upf ├── IssuePartition.upf ├── FetchStage1.upf ├── PhyRegFile.upf ├── RenameDispatch.upf ├── Fetch2Decode.upf ├── IssueQRegRead.upf ├── Fetch1Fetch2.upf ├── FetchStage2.upf ├── InstBufRename.upf ├── Decode.upf ├── LSU.upf ├── ExecutionPipe_SC_Both.upf ├── Core_OOO_Hier.upf ├── Rename.upf └── ActiveList.upf ├── Copyright ├── lib ├── clk_gater_fg.sv ├── PGIsolationCell.sv ├── PipeLineReg.sv └── clk_gater_ul.sv ├── configs ├── RAM_Params.svh ├── Config1.v ├── Config2.v └── StaticConfig5.v ├── fetch ├── SelectInst.sv ├── Fetch1Fetch2.sv └── Fetch2Decode.sv ├── execute ├── AgenLsu.sv ├── Mux.sv ├── Demux.sv └── ForwardCheck.sv ├── testbenches ├── TbConfig5.svh ├── TbConfig6.svh ├── TbConfig2.svh ├── TbConfig1.svh ├── TbConfig4.svh ├── TbConfig3.svh └── l2_icache.sv ├── regRead ├── RegReadExecute.sv └── Bypass_1D.sv ├── issue ├── PriorityEncoder.sv ├── SelectBlock.sv ├── Encoder.sv ├── SelectBetweenBlocks.sv ├── IssueQRegRead.sv └── Select.sv ├── LICENSE ├── lsu ├── MMU.sv ├── CommitLoad.sv └── CommitStore.sv ├── rams ├── RAM_1R1W.sv ├── BP_RAM_GSHARE.sv ├── BP_RAM.sv ├── BTB_RAM.sv ├── RAM_1R2W.sv ├── RAM_4R1W.sv ├── LDQ_CAM.sv ├── RAS_RAM.sv ├── DEBUG_DATA_RAM.sv ├── STQ_CAM.sv ├── CTI_COMMIT_RAM.sv ├── RAM_8R4W.sv ├── LDVIO_VLD_RAM.sv ├── LDVIO_RAM.sv ├── CTI_COUNTER_RAM.sv └── DEBUG_INST_RAM.sv ├── decode ├── Decode.sv ├── ppa_decode.sv └── InstBufRename.sv ├── rams_configurable ├── RAM_PG_1R1W.sv ├── RAM_PG_2R1W.sv └── RAM_STATIC_CONFIG_NO_DECODE.sv ├── writeback ├── Writeback_SC.sv ├── Writeback_M.sv └── Writeback_Ctrl.sv ├── bist ├── MemBist.sv └── LogicBist.sv ├── rename └── RenameDispatch.sv └── core_top └── ResetControl.sv /README.md: -------------------------------------------------------------------------------- 1 | anycore 2 | ======= 3 | 4 | This contains the RTL for Anycore and associated simulation and synthesis framework for the latest RISCV based development of AnyCore 5 | 6 | -------------------------------------------------------------------------------- /power_spec/InstructionBuffer.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | #create_power_domain PD_IBUFF 3 | 4 | ## Change the scope to IBUFF_RAM ram instance 5 | set_scope instBuffer/ram_configurable 6 | load_upf RamConfigurable.upf 7 | set_scope ../.. 8 | 9 | ## SUPPLY NETWORK - PD_IBUFF 10 | #create_supply_port VDD 11 | #create_supply_port VSS 12 | # 13 | #create_supply_net VDD 14 | #create_supply_net VSS 15 | 16 | #create_supply_net VDD -domain PD_IBUFF 17 | #create_supply_net VSS -domain PD_IBUFF 18 | 19 | #set_domain_supply_net PD_IBUFF -primary_power_net VDD -primary_ground_net VSS 20 | 21 | set_scope 22 | connect_supply_net VDD -ports {instBuf/instBuffer/ram_configurable/VDD} 23 | 24 | connect_supply_net VSS -ports {instBuf/instBuffer/ram_configurable/VSS} 25 | 26 | -------------------------------------------------------------------------------- /power_spec/RamConfigurable.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain PD_RAM_CONFIG 3 | 4 | ## Change the scope to RAM_PARTITIONED instance 5 | set_scope PARTITIONED.ram_partitioned 6 | load_upf RamPartitioned.upf 7 | set_scope .. 8 | 9 | ## SUPPLY NETWORK - PD_RAM_CONFIG 10 | create_supply_port VDD -domain PD_RAM_CONFIG 11 | create_supply_port VSS -domain PD_RAM_CONFIG 12 | # 13 | #create_supply_net VDD 14 | #create_supply_net VSS 15 | 16 | create_supply_net VDD -domain PD_RAM_CONFIG 17 | create_supply_net VSS -domain PD_RAM_CONFIG 18 | 19 | set_domain_supply_net PD_RAM_CONFIG -primary_power_net VDD -primary_ground_net VSS 20 | 21 | connect_supply_net VDD -ports {VDD PARTITIONED.ram_partitioned/VDD} 22 | 23 | connect_supply_net VSS -ports {VSS PARTITIONED.ram_partitioned/VSS} 24 | 25 | -------------------------------------------------------------------------------- /Copyright: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # AnyCore Project 4 | # 5 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 6 | # 7 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 8 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 9 | # 10 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 11 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 12 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 13 | # and Salil Wadhavkar. 14 | # 15 | # AnyCore is distributed under the BSD license. 16 | ******************************************************************************/ 17 | 18 | -------------------------------------------------------------------------------- /power_spec/PipeLineReg.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain PD_PIPEREG 3 | 4 | 5 | ## SUPPLY NETWORK - PD_PIPEREG 6 | create_supply_net VDD -domain PD_PIPEREG 7 | create_supply_net VSS -domain PD_PIPEREG 8 | 9 | create_supply_port VDD -domain PD_PIPEREG 10 | create_supply_port VSS -domain PD_PIPEREG 11 | 12 | connect_supply_net VDD -ports {VDD} 13 | connect_supply_net VSS -ports {VSS} 14 | 15 | ## Power Switch 16 | 17 | create_supply_net SWITCHED_VDD -domain PD_PIPEREG 18 | 19 | create_power_switch PD_PIPEREG_SW -domain PD_PIPEREG -output_supply_port {vout SWITCHED_VDD} -input_supply_port {vin VDD} \ 20 | -control_port {ctrl pwrEn_i} -on_state {on_s vin {ctrl}} \ 21 | -off_state {off_s {!ctrl}} 22 | 23 | ## Set domain power and ground supplies 24 | set_domain_supply_net PD_PIPEREG -primary_power_net SWITCHED_VDD -primary_ground_net VSS 25 | 26 | -------------------------------------------------------------------------------- /power_spec/ExecutionPipe_SC.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain PD_EX_SC 3 | 4 | 5 | ## SUPPLY NETWORK - PD_EX_SC 6 | create_supply_net VDD -domain PD_EX_SC 7 | create_supply_net VSS -domain PD_EX_SC 8 | 9 | create_supply_port VDD -domain PD_EX_SC 10 | create_supply_port VSS -domain PD_EX_SC 11 | 12 | 13 | 14 | connect_supply_net VDD -ports {VDD} 15 | connect_supply_net VSS -ports {VSS} 16 | 17 | ## Power Switch 18 | create_supply_net SWITCHED_VDD -domain PD_EX_SC 19 | 20 | 21 | create_power_switch PD_EX_SC_SW -domain PD_EX_SC -output_supply_port {vout SWITCHED_VDD} -input_supply_port {vin VDD} \ 22 | -control_port {ctrl laneActive_i} -on_state {on_s vin {ctrl}} \ 23 | -off_state {off_s {!ctrl}} 24 | 25 | ## Set domain power and ground supplies 26 | set_domain_supply_net PD_EX_SC -primary_power_net SWITCHED_VDD -primary_ground_net VSS 27 | 28 | 29 | 30 | -------------------------------------------------------------------------------- /power_spec/RenameLane.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain PD_REN_LANE 3 | 4 | 5 | ## SUPPLY NETWORK - PD_REN_LANE 6 | create_supply_net VDD -domain PD_REN_LANE 7 | create_supply_net VSS -domain PD_REN_LANE 8 | 9 | create_supply_port VDD -domain PD_REN_LANE 10 | create_supply_port VSS -domain PD_REN_LANE 11 | 12 | 13 | 14 | connect_supply_net VDD -ports {VDD} 15 | connect_supply_net VSS -ports {VSS} 16 | 17 | ## Power Switch 18 | create_supply_net SWITCHED_VDD -domain PD_REN_LANE 19 | 20 | 21 | create_power_switch PD_REN_LANE_SW -domain PD_REN_LANE -output_supply_port {vout SWITCHED_VDD} -input_supply_port {vin VDD} \ 22 | -control_port {ctrl laneActive_i} -on_state {on_s vin {ctrl}} \ 23 | -off_state {off_s {!ctrl}} 24 | 25 | ## Set domain power and ground supplies 26 | set_domain_supply_net PD_REN_LANE -primary_power_net SWITCHED_VDD -primary_ground_net VSS 27 | 28 | 29 | -------------------------------------------------------------------------------- /power_spec/IssueLane.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain PD_ISSUE_LANE 3 | 4 | 5 | ## SUPPLY NETWORK - PD_ISSUE_LANE 6 | create_supply_net VDD -domain PD_ISSUE_LANE 7 | create_supply_net VSS -domain PD_ISSUE_LANE 8 | 9 | create_supply_port VDD -domain PD_ISSUE_LANE 10 | create_supply_port VSS -domain PD_ISSUE_LANE 11 | 12 | 13 | 14 | connect_supply_net VDD -ports {VDD} 15 | connect_supply_net VSS -ports {VSS} 16 | 17 | ## Power Switch 18 | create_supply_net SWITCHED_VDD -domain PD_ISSUE_LANE 19 | 20 | 21 | create_power_switch PD_ISSUE_LANE_SW -domain PD_ISSUE_LANE -output_supply_port {vout SWITCHED_VDD} -input_supply_port {vin VDD} \ 22 | -control_port {ctrl laneActive_i} -on_state {on_s vin {ctrl}} \ 23 | -off_state {off_s {!ctrl}} 24 | 25 | ## Set domain power and ground supplies 26 | set_domain_supply_net PD_ISSUE_LANE -primary_power_net SWITCHED_VDD -primary_ground_net VSS 27 | 28 | 29 | -------------------------------------------------------------------------------- /power_spec/Decode_PISA.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain PD_DECODE_PISA 3 | 4 | 5 | ## SUPPLY NETWORK - PD_DECODE_PISA 6 | create_supply_net VDD -domain PD_DECODE_PISA 7 | create_supply_net VSS -domain PD_DECODE_PISA 8 | 9 | create_supply_port VDD -domain PD_DECODE_PISA 10 | create_supply_port VSS -domain PD_DECODE_PISA 11 | 12 | 13 | 14 | connect_supply_net VDD -ports {VDD} 15 | connect_supply_net VSS -ports {VSS} 16 | 17 | ## Power Switch 18 | create_supply_net SWITCHED_VDD -domain PD_DECODE_PISA 19 | 20 | 21 | create_power_switch PD_DECODE_PISA_SW -domain PD_DECODE_PISA -output_supply_port {vout SWITCHED_VDD} -input_supply_port {vin VDD} \ 22 | -control_port {ctrl laneActive_i} -on_state {on_s vin {ctrl}} \ 23 | -off_state {off_s {!ctrl}} 24 | 25 | ## Set domain power and ground supplies 26 | set_domain_supply_net PD_DECODE_PISA -primary_power_net SWITCHED_VDD -primary_ground_net VSS 27 | 28 | 29 | -------------------------------------------------------------------------------- /power_spec/RamConfigurableAL.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain ${PD_RAM_CONFIG} 3 | 4 | ## Change the scope to RAM_PARTITIONED instance 5 | set PREVIOUS_SCOPE ${CURRENT_SCOPE} 6 | set CURRENT_SCOPE [set_scope PARTITIONED.ram_partitioned] 7 | load_upf RamPartitionedAL.upf 8 | set_scope ${CURRENT_SCOPE} 9 | 10 | ## SUPPLY NETWORK - PD_RAM_CONFIG 11 | create_supply_port VDD -domain ${PD_RAM_CONFIG} 12 | create_supply_port VSS -domain ${PD_RAM_CONFIG} 13 | # 14 | #create_supply_net VDD 15 | #create_supply_net VSS 16 | 17 | create_supply_net VDD -domain ${PD_RAM_CONFIG} 18 | create_supply_net VSS -domain ${PD_RAM_CONFIG} 19 | 20 | set_domain_supply_net ${PD_RAM_CONFIG} -primary_power_net VDD -primary_ground_net VSS 21 | 22 | connect_supply_net VDD -ports {VDD PARTITIONED.ram_partitioned/VDD} 23 | 24 | connect_supply_net VSS -ports {VSS PARTITIONED.ram_partitioned/VSS} 25 | 26 | ## Restore CURRENT_SCOPE to the same scope when entering this file 27 | set CURRENT_SCOPE ${PREVIOUS_SCOPE} 28 | 29 | -------------------------------------------------------------------------------- /power_spec/IssuePartition.upf: -------------------------------------------------------------------------------- 1 | ## CREATE POWER DOMAINS 2 | create_power_domain PD_ISSUE_PARTITION 3 | 4 | 5 | ## SUPPLY NETWORK - PD_ISSUE_PARTITION 6 | create_supply_net VDD -domain PD_ISSUE_PARTITION 7 | create_supply_net VSS -domain PD_ISSUE_PARTITION 8 | 9 | create_supply_port VDD -domain PD_ISSUE_PARTITION 10 | create_supply_port VSS -domain PD_ISSUE_PARTITION 11 | 12 | 13 | 14 | connect_supply_net VDD -ports {VDD} 15 | connect_supply_net VSS -ports {VSS} 16 | 17 | ## Power Switch 18 | create_supply_net SWITCHED_VDD -domain PD_ISSUE_PARTITION 19 | 20 | 21 | create_power_switch PD_ISSUE_PARTITION_SW -domain PD_ISSUE_PARTITION -output_supply_port {vout SWITCHED_VDD} -input_supply_port {vin VDD} \ 22 | -control_port {ctrl partitionActive_i} -on_state {on_s vin {ctrl}} \ 23 | -off_state {off_s {!ctrl}} 24 | 25 | ## Set domain power and ground supplies 26 | set_domain_supply_net PD_ISSUE_PARTITION -primary_power_net SWITCHED_VDD -primary_ground_net VSS 27 | 28 | 29 | -------------------------------------------------------------------------------- /lib/clk_gater_fg.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | `timescale 1ns/100ps 19 | 20 | module clk_gater_fg(clk_i,clkGated_o,clkEn_i); 21 | 22 | input clk_i; 23 | input clkEn_i; 24 | output clkGated_o; 25 | 26 | `CLK_GATE_CELL_FG latch ( .E(clkEn_i), .CK(clk_i), .ECK(clkGated_o) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /power_spec/FetchStage1.upf: -------------------------------------------------------------------------------- 1 | # This empty power domain seems to be necessary in order to create the power domains correctly 2 | # ** SOme bug maybe ** 3 | #create_power_domain FS1 4 | 5 | ## Change the scope to BTB module 6 | set CURRENT_SCOPE [set_scope btb] 7 | load_upf BTB.upf 8 | ## Change the scope back to FetchStage1 module 9 | set_scope ${CURRENT_SCOPE} 10 | 11 | ## Change the scope to BTB module 12 | set CURRENT_SCOPE [set_scope bp] 13 | load_upf BPU.upf 14 | ## Change the scope back to FetchStage1 module 15 | set_scope ${CURRENT_SCOPE} 16 | 17 | #create_supply_port VDD -domain PD_FS1 18 | #create_supply_port VSS -domain PD_FS1 19 | # 20 | #create_supply_net VDD -domain PD_FS1 21 | #create_supply_net VSS -domain PD_FS1 22 | # 23 | #set_domain_supply_net PD_FS1 -primary_power_net VDD -primary_ground_net VSS 24 | # 25 | #connect_supply_net VDD -ports {VDD btb/VDD} 26 | #connect_supply_net VSS -ports {VSS btb/VSS} 27 | 28 | 29 | set_scope 30 | #connect_supply_net VDD -ports {fs1/VDD} 31 | #connect_supply_net VSS -ports {fs1/VSS} 32 | connect_supply_net VDD -ports {fs1/btb/VDD fs1/bp/VDD} 33 | connect_supply_net VSS -ports {fs1/btb/VSS fs1/bp/VSS} 34 | 35 | -------------------------------------------------------------------------------- /lib/PGIsolationCell.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | `timescale 1ns/100ps 19 | 20 | module PGIsolationCell #(WIDTH = 1) 21 | (signalIn,signalOut,clampEn,clampValue); 22 | 23 | input [WIDTH-1:0] signalIn; 24 | output [WIDTH-1:0] signalOut; 25 | input clampEn; 26 | input [WIDTH-1:0] clampValue; 27 | 28 | assign signalOut = clampEn ? clampValue : signalIn; 29 | 30 | 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /configs/RAM_Params.svh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `define RAM_CONFIG_DEPTH 64 20 | `define RAM_CONFIG_INDEX 6 21 | `define RAM_CONFIG_WIDTH 32 22 | `define RAM_CONFIG_RP 12 23 | `define RAM_CONFIG_WP 6 24 | `define RAM_CONFIG_WP_LOG 3 25 | `define RAM_CONFIG_PARTS 4 26 | 27 | `define RAM_RESET_ZERO 0 28 | `define RAM_RESET_SEQ 1 29 | 30 | `define RAM_PARTS 4 31 | `define RAM_PARTS_LOG 2 32 | 33 | `define LATCH_BASED_RAM 0 34 | -------------------------------------------------------------------------------- /fetch/SelectInst.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | 20 | `timescale 1ns/100ps 21 | 22 | 23 | module SelectInst( 24 | input [`SIZE_PC-1:0] pc_i, 25 | output startBlock_o, // Select signal for inst read from Even/Odd banks 26 | output [1:0] firstInst_o // First instruction from the cache blocks read 27 | ); 28 | 29 | assign startBlock_o = pc_i[4]; 30 | assign firstInst_o = pc_i[3:2]; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /execute/AgenLsu.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `timescale 1ns/100ps 20 | 21 | 22 | module AgenLsu ( 23 | input clk, 24 | input reset, 25 | input flush_i, 26 | 27 | input memPkt memPacket_i, 28 | 29 | output memPkt memPacket_o 30 | ); 31 | 32 | 33 | always_ff @(posedge clk) 34 | begin 35 | if (reset | flush_i) 36 | begin 37 | memPacket_o <= 0; 38 | end 39 | 40 | else 41 | begin 42 | memPacket_o.valid <= memPacket_i.valid; 43 | 44 | if (memPacket_i.valid) 45 | begin 46 | memPacket_o <= memPacket_i; 47 | end 48 | 49 | `ifdef SIM 50 | else 51 | begin 52 | memPacket_o <= 0; 53 | end 54 | `endif 55 | 56 | end 57 | end 58 | 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /testbenches/TbConfig5.svh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `define FETCH_LANE_ACTIVE {`FETCH_WIDTH{1'b1}}; 20 | `define DISPATCH_LANE_ACTIVE {`DISPATCH_WIDTH{1'b1}}; 21 | `define ISSUE_LANE_ACTIVE {`ISSUE_WIDTH{1'b1}}; 22 | `define EXEC_LANE_ACTIVE {`EXEC_WIDTH{1'b1}}; 23 | `define SALU_LANE_ACTIVE {5'b11100}; 24 | `define CALU_LANE_ACTIVE {5'b00100}; 25 | `define COMMIT_LANE_ACTIVE {`COMMIT_WIDTH{1'b1}}; 26 | `define RF_PARTITION_ACTIVE {`NUM_PARTS_RF{1'b1}}; 27 | `define AL_PARTITION_ACTIVE {`NUM_PARTS_RF{1'b1}}; 28 | `define LSQ_PARTITION_ACTIVE {`STRUCT_PARTS_LSQ{1'b1}}; 29 | `define IQ_PARTITION_ACTIVE {`STRUCT_PARTS{1'b1}}; 30 | `define IBUFF_PARTITION_ACTIVE {`STRUCT_PARTS{1'b1}}; 31 | -------------------------------------------------------------------------------- /regRead/RegReadExecute.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `timescale 1ns/100ps 20 | 21 | 22 | module RegReadExecute ( 23 | input clk, 24 | input reset, 25 | 26 | input flush_i, 27 | 28 | input fuPkt exePacket_i, 29 | output fuPkt exePacket_o 30 | ); 31 | 32 | 33 | /* Pipeline registers between RegRead and Execute stage. */ 34 | always_ff @(posedge clk) 35 | begin 36 | if (reset | flush_i) 37 | begin 38 | exePacket_o <= {`FU_PKT_SIZE{1'b0}}; 39 | end 40 | 41 | else 42 | begin 43 | //TODO: Fix this 44 | if (exePacket_i.valid) 45 | begin 46 | exePacket_o <= exePacket_i; 47 | end 48 | 49 | exePacket_o.valid <= exePacket_i.valid; 50 | end 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /issue/PriorityEncoder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `timescale 1ns/100ps 20 | 21 | module PriorityEncoder #( 22 | parameter ENCODER_WIDTH = 32 23 | )( 24 | 25 | input [ENCODER_WIDTH-1:0] vector_i, 26 | output [ENCODER_WIDTH-1:0] vector_o 27 | ); 28 | 29 | /* Mask to reset all other bits except the first */ 30 | reg [ENCODER_WIDTH-1:0] mask; 31 | 32 | wire [ENCODER_WIDTH-1:0] vector; 33 | 34 | assign vector_o = vector; 35 | 36 | /* Mask the input vector so that only the first 1'b1 is seen */ 37 | assign vector = vector_i & mask; 38 | 39 | 40 | always_comb 41 | begin: ENCODER_CONSTRUCT 42 | int i; 43 | mask[0] = 1'b1; 44 | 45 | for (i = 1; i < ENCODER_WIDTH; i++) 46 | begin 47 | if (vector_i[i-1]) 48 | begin 49 | mask[i] = 0; 50 | end 51 | 52 | else 53 | begin 54 | mask[i] = mask[i-1]; 55 | end 56 | end 57 | end 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /testbenches/TbConfig6.svh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `define FETCH_LANE_ACTIVE {`FETCH_WIDTH{1'b1}}; 20 | `define DISPATCH_LANE_ACTIVE {`DISPATCH_WIDTH{1'b1}}; 21 | `define ISSUE_LANE_ACTIVE {`ISSUE_WIDTH{1'b1}}; 22 | `define EXEC_LANE_ACTIVE {`EXEC_WIDTH{1'b1}}; 23 | `define SALU_LANE_ACTIVE {5'b11100}; 24 | `define CALU_LANE_ACTIVE {5'b00100}; 25 | `define COMMIT_LANE_ACTIVE {`COMMIT_WIDTH{1'b1}}; 26 | `define RF_PARTITION_ACTIVE {{`NUM_PARTS_RF-3{1'b0}},3'b111}; 27 | `define AL_PARTITION_ACTIVE {{`NUM_PARTS_RF-3{1'b0}},3'b111}; 28 | `define LSQ_PARTITION_ACTIVE {{`STRUCT_PARTS_LSQ-1{1'b0}},1'b1}; 29 | `define IQ_PARTITION_ACTIVE {{`STRUCT_PARTS-3{1'b0}},3'b111}; 30 | `define IBUFF_PARTITION_ACTIVE {`STRUCT_PARTS{1'b1}}; 31 | -------------------------------------------------------------------------------- /testbenches/TbConfig2.svh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `define FETCH_LANE_ACTIVE {{`FETCH_WIDTH-1{1'b0}},1'b1}; 20 | `define DISPATCH_LANE_ACTIVE {{`DISPATCH_WIDTH-1{1'b0}},1'b1}; 21 | `define ISSUE_LANE_ACTIVE {{`ISSUE_WIDTH-3{1'b0}},3'b111}; 22 | `define EXEC_LANE_ACTIVE {{`EXEC_WIDTH-3{1'b0}},3'b111}; 23 | `define SALU_LANE_ACTIVE {{`EXEC_WIDTH-3{1'b0}},3'b100}; 24 | `define CALU_LANE_ACTIVE {{`EXEC_WIDTH-3{1'b0}},3'b100}; 25 | `define COMMIT_LANE_ACTIVE {{`COMMIT_WIDTH-2{1'b0}},2'b11}; 26 | `define RF_PARTITION_ACTIVE {{`NUM_PARTS_RF-2{1'b0}},2'b11}; 27 | `define AL_PARTITION_ACTIVE {{`NUM_PARTS_RF-2{1'b0}},2'b11}; 28 | `define LSQ_PARTITION_ACTIVE {{`STRUCT_PARTS_LSQ-1{1'b0}},1'b1}; 29 | `define IQ_PARTITION_ACTIVE {{`STRUCT_PARTS-1{1'b0}},1'b1}; 30 | `define IBUFF_PARTITION_ACTIVE {{`STRUCT_PARTS-2{2'b0}},2'b11}; 31 | -------------------------------------------------------------------------------- /testbenches/TbConfig1.svh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `define FETCH_LANE_ACTIVE {{`FETCH_WIDTH-1{1'b0}},1'b1}; 20 | `define DISPATCH_LANE_ACTIVE {{`DISPATCH_WIDTH-1{1'b0}},1'b1}; 21 | `define ISSUE_LANE_ACTIVE {{`ISSUE_WIDTH-3{1'b0}},3'b111}; 22 | `define EXEC_LANE_ACTIVE {{`EXEC_WIDTH-3{1'b0}},3'b111}; 23 | `define SALU_LANE_ACTIVE {{`EXEC_WIDTH-3{1'b0}},3'b100}; 24 | `define CALU_LANE_ACTIVE {{`EXEC_WIDTH-3{1'b0}},3'b100}; 25 | `define COMMIT_LANE_ACTIVE {{`COMMIT_WIDTH-2{1'b0}},2'b11}; 26 | `define RF_PARTITION_ACTIVE {{`NUM_PARTS_RF-3{1'b0}},3'b111}; 27 | `define AL_PARTITION_ACTIVE {{`NUM_PARTS_RF-3{1'b0}},3'b111}; 28 | `define LSQ_PARTITION_ACTIVE {{`STRUCT_PARTS_LSQ-1{1'b0}},1'b1}; 29 | `define IQ_PARTITION_ACTIVE {{`STRUCT_PARTS-2{1'b0}},2'b11}; 30 | `define IBUFF_PARTITION_ACTIVE {{`STRUCT_PARTS-2{1'b0}},2'b11}; 31 | -------------------------------------------------------------------------------- /testbenches/TbConfig4.svh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `define FETCH_LANE_ACTIVE {{`FETCH_WIDTH-2{1'b0}},2'b11}; 20 | `define DISPATCH_LANE_ACTIVE {{`DISPATCH_WIDTH-2{1'b0}},2'b11}; 21 | `define ISSUE_LANE_ACTIVE {{`ISSUE_WIDTH-4{1'b0}},4'b1111}; 22 | `define EXEC_LANE_ACTIVE {{`EXEC_WIDTH-4{1'b0}},4'b1111}; 23 | `define SALU_LANE_ACTIVE {{`EXEC_WIDTH-4{1'b0}},4'b1100}; 24 | `define CALU_LANE_ACTIVE {{`EXEC_WIDTH-4{1'b0}},4'b0100}; 25 | `define COMMIT_LANE_ACTIVE {{`COMMIT_WIDTH-3{1'b0}},3'b111}; 26 | `define RF_PARTITION_ACTIVE {{`NUM_PARTS_RF-2{1'b0}},2'b11}; 27 | `define AL_PARTITION_ACTIVE {{`NUM_PARTS_RF-2{1'b0}},2'b11}; 28 | `define LSQ_PARTITION_ACTIVE {{`STRUCT_PARTS_LSQ-1{1'b0}},1'b1}; 29 | `define IQ_PARTITION_ACTIVE {{`STRUCT_PARTS-2{1'b0}},2'b11}; 30 | `define IBUFF_PARTITION_ACTIVE {{`STRUCT_PARTS-3{1'b0}},3'b111}; 31 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2016, North Carolina State University (NCSU). 2 | 3 | 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without modification, 7 | are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, this 13 | list of conditions and the following disclaimer in the documentation and/or other 14 | materials provided with the distribution. 15 | 16 | 3. The names “North Carolina State University”, “NCSU” and any trade‐name, personal 17 | name, trademark, trade device, service mark, symbol, image, icon, or any abbreviation, 18 | contraction or simulation thereof owned by North Carolina State University must not 19 | be used to endorse or promote products derived from this software without prior 20 | written permission. 21 | 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 23 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 | OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 25 | SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 27 | TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 28 | BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 | ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 | DAMAGE. 32 | 33 | -------------------------------------------------------------------------------- /testbenches/TbConfig3.svh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `define FETCH_LANE_ACTIVE {{`FETCH_WIDTH-2{1'b0}},2'b11}; 20 | `define DISPATCH_LANE_ACTIVE {{`DISPATCH_WIDTH-2{1'b0}},2'b11}; 21 | `define ISSUE_LANE_ACTIVE {{`ISSUE_WIDTH-4{1'b0}},4'b1111}; 22 | `define EXEC_LANE_ACTIVE {{`EXEC_WIDTH-4{1'b0}},4'b1111}; 23 | `define SALU_LANE_ACTIVE {{`EXEC_WIDTH-4{1'b0}},4'b1100}; 24 | `define CALU_LANE_ACTIVE {{`EXEC_WIDTH-4{1'b0}},4'b0100}; 25 | `define COMMIT_LANE_ACTIVE {{`COMMIT_WIDTH-3{1'b0}},3'b111}; 26 | `define RF_PARTITION_ACTIVE {{`NUM_PARTS_RF-3{1'b0}},3'b111}; 27 | `define AL_PARTITION_ACTIVE {{`NUM_PARTS_RF-3{1'b0}},3'b111}; 28 | `define LSQ_PARTITION_ACTIVE {{`STRUCT_PARTS_LSQ-2{1'b0}},2'b11}; 29 | `define IQ_PARTITION_ACTIVE {{`STRUCT_PARTS-3{1'b0}},3'b111}; 30 | `define IBUFF_PARTITION_ACTIVE {{`STRUCT_PARTS-3{1'b0}},3'b111}; 31 | -------------------------------------------------------------------------------- /lsu/MMU.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | module MMU 20 | ( 21 | input clk, 22 | input [`SIZE_DATA-1:0] virtAddress_i, 23 | input [`SIZE_DATA_BYTE_OFFSET-1:0] numBytes_i, 24 | input ldAccess_i, 25 | input stAccess_i, 26 | input instAccess_i, 27 | output reg [7:0] exception_o 28 | ); 29 | 30 | // synopsys translate_off 31 | 32 | int memAccessBytes; 33 | int exception; 34 | logic [`SIZE_DATA-1:0] phyAddress; 35 | 36 | always @(*) 37 | begin 38 | memAccessBytes = numBytes_i; 39 | exception_o = exception; 40 | end 41 | 42 | always @(negedge clk) 43 | begin 44 | if(ldAccess_i | stAccess_i | instAccess_i) 45 | begin 46 | phyAddress <= virt_to_phys(virtAddress_i, numBytes_i, stAccess_i, instAccess_i, exception); 47 | end 48 | else 49 | exception <= 0; 50 | end 51 | 52 | // synopsys translate_on 53 | 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /lsu/CommitLoad.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `timescale 1ns/100ps 20 | 21 | module CommitLoad ( 22 | input [`COMMIT_WIDTH-1:0] commitLoad_i, 23 | 24 | input [`SIZE_LSQ_LOG-1:0] ldqHead_i, 25 | 26 | output [2:0] commitLdCount_o, 27 | 28 | output [`SIZE_LSQ_LOG-1:0] commitLdIndex_o [0:`COMMIT_WIDTH-1] 29 | ); 30 | 31 | 32 | reg [2:0] commitLdCount; 33 | reg [`SIZE_LSQ_LOG-1:0] commitLdIndex [0:`COMMIT_WIDTH-1]; 34 | 35 | 36 | assign commitLdCount_o = commitLdCount; 37 | assign commitLdIndex_o = commitLdIndex; 38 | 39 | 40 | /* Following combinational logic counts the number of LD commitructions in the 41 | * incoming retiring commitructions. */ 42 | always_comb 43 | begin 44 | commitLdCount = commitLoad_i[0] + commitLoad_i[1] + commitLoad_i[2] + commitLoad_i[3]; 45 | commitLdIndex[0] = ldqHead_i; 46 | commitLdIndex[1] = ldqHead_i+1; 47 | commitLdIndex[2] = ldqHead_i+2; 48 | commitLdIndex[3] = ldqHead_i+3; 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /rams/RAM_1R1W.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | 20 | `timescale 1ns/100ps 21 | 22 | module RAM_1R1W( addr0_i,addr0wr_i,we0_i,data0wr_i, 23 | clk,data0_o); 24 | 25 | 26 | parameter RPORT = 1; 27 | parameter WPORT = 1; 28 | parameter DEPTH = 64; 29 | parameter INDEX = 6; 30 | parameter WIDTH = 32; 31 | 32 | input [INDEX-1:0] addr0_i; 33 | input [INDEX-1:0] addr0wr_i; 34 | input we0_i; 35 | input clk; 36 | //input reset; 37 | input [WIDTH-1:0] data0wr_i; 38 | output [WIDTH-1:0] data0_o; 39 | 40 | `ifdef RAM_1R1W_COMPILED 41 | //synopsys translate_off 42 | `endif 43 | 44 | /* Defining register file for ram */ 45 | reg [WIDTH-1:0] ram [DEPTH-1:0]; 46 | 47 | integer i; 48 | 49 | assign data0_o = ram[addr0_i]; 50 | 51 | 52 | always @(posedge clk) 53 | begin 54 | // if(reset) 55 | // begin 56 | // for(i=0;i 8 conversion) * 57 | ******************************************/ 58 | 59 | genvar g; 60 | generate 61 | for (g = 0; g < NUM_SELECT_BLOCK; g = g + 1) 62 | begin : SelectBlock_gen 63 | 64 | /* Stage 0 */ 65 | SelectBlock #( 66 | .SIZE_SELECT_BLOCK (SIZE_SELECT_BLOCK) 67 | ) 68 | U0 ( 69 | 70 | .req_i (requestVector_i[(g * SIZE_SELECT_BLOCK) +: SIZE_SELECT_BLOCK]), 71 | 72 | .grant_i (grantIn_u0[g]), 73 | 74 | .grant_o (grantedVector[(g * SIZE_SELECT_BLOCK) +: SIZE_SELECT_BLOCK]), 75 | 76 | .req_o (reqOut_u0[g]) 77 | ); 78 | 79 | end 80 | endgenerate 81 | 82 | 83 | /****************************************** 84 | * Stage 1 (deals with 8 -> 1 conversion) * 85 | ******************************************/ 86 | 87 | /* Stage 1, select block 0 */ 88 | SelectBetweenBlocks #( 89 | .SIZE_SELECT_BLOCK (NUM_SELECT_BLOCK) 90 | ) 91 | U1 ( 92 | 93 | .clk (clk), 94 | 95 | .reset (reset), 96 | 97 | .req_i (reqOut_u0), 98 | 99 | .grant_i (1'h1), 100 | 101 | .grant_o (grantIn_u0), 102 | 103 | .req_o (reqOut_u1) 104 | ); 105 | 106 | /* Instantiate the encoder */ 107 | Encoder #( 108 | .ENCODER_WIDTH (`SIZE_ISSUEQ), 109 | .ENCODER_WIDTH_LOG (`SIZE_ISSUEQ_LOG) 110 | ) 111 | grantEncoder( 112 | 113 | .vector_i (grantedVector), 114 | .encoded_o (grantedEntry) 115 | ); 116 | 117 | endmodule 118 | 119 | -------------------------------------------------------------------------------- /power_spec/Rename.upf: -------------------------------------------------------------------------------- 1 | ## Change the scope to BTB module 2 | set_scope RMT 3 | 4 | ## CREATE POWER DOMAINS 5 | #create_power_domain PD_RMT 6 | 7 | ## Change the scope to Lane0 8 | set_scope LANEGEN[0].lane 9 | load_upf RenameLane.upf 10 | set_scope .. 11 | 12 | ## Change the scope to Lane1 13 | set_scope LANEGEN[1].lane 14 | load_upf RenameLane.upf 15 | set_scope .. 16 | 17 | ## Change the scope to Lane2 18 | set_scope LANEGEN[2].lane 19 | load_upf RenameLane.upf 20 | set_scope .. 21 | 22 | ## Change the scope to Lane3 23 | set_scope LANEGEN[3].lane 24 | load_upf RenameLane.upf 25 | set_scope .. 26 | 27 | ## Change the scope to Lane4 28 | set_scope LANEGEN[4].lane 29 | load_upf RenameLane.upf 30 | set_scope .. 31 | 32 | ## Change the scope to Lane5 33 | set_scope LANEGEN[5].lane 34 | load_upf RenameLane.upf 35 | set_scope .. 36 | 37 | ## SUPPLY NETWORK - TOP in scope RenameMapTable 38 | #create_supply_port VDD 39 | #create_supply_port VSS 40 | 41 | #create_supply_net VDD 42 | #create_supply_net VSS 43 | 44 | #create_supply_net VDD -domain PD_RMT 45 | #create_supply_net VSS -domain PD_RMT 46 | 47 | #set_domain_supply_net PD_RMT -primary_power_net VDD -primary_ground_net VSS 48 | 49 | ## VDD and VSS networks in scope RenameMapTable 50 | set_scope 51 | connect_supply_net VDD -ports {rename/RMT/LANEGEN[0].lane/VDD \ 52 | rename/RMT/LANEGEN[1].lane/VDD \ 53 | rename/RMT/LANEGEN[2].lane/VDD \ 54 | rename/RMT/LANEGEN[3].lane/VDD \ 55 | rename/RMT/LANEGEN[4].lane/VDD \ 56 | rename/RMT/LANEGEN[5].lane/VDD} 57 | 58 | connect_supply_net VSS -ports {rename/RMT/LANEGEN[0].lane/VSS \ 59 | rename/RMT/LANEGEN[1].lane/VSS \ 60 | rename/RMT/LANEGEN[2].lane/VSS \ 61 | rename/RMT/LANEGEN[3].lane/VSS \ 62 | rename/RMT/LANEGEN[4].lane/VSS \ 63 | rename/RMT/LANEGEN[5].lane/VSS} 64 | 65 | 66 | 67 | ## Change scope back to Rename from RenameMapTable 68 | set_scope .. 69 | 70 | ## Not using partitioned RAM for FreeListRAM right now 71 | ## This will be converted to partitioned RAM pretty soon 72 | ### Change scope to SpecFreeList 73 | #set_scope specfreelist/freeList/ram_configurable 74 | #load_upf RamConfigurable.upf 75 | ### Move back to scope Rename 76 | #set_scope .. 77 | #set_scope .. 78 | #set_scope .. 79 | 80 | ## SUPPLY NETWORK - TOP in scope Rename 81 | #create_supply_port VDD 82 | #create_supply_port VSS 83 | # 84 | #create_supply_net VDD 85 | #create_supply_net VSS 86 | 87 | #create_supply_net VDD -domain PD_RENAME 88 | #create_supply_net VSS -domain PD_RENAME 89 | 90 | #set_domain_supply_net PD_RENAME -primary_power_net VDD -primary_ground_net VSS 91 | 92 | ## VDD and VSS networks in scope Rename 93 | ## Connect VDD and VSS to the ports in the two main components 94 | ## of Rename, namely RMT and SpecFreeList 95 | #connect_supply_net VDD -ports {VDD RMT/VDD \ 96 | # specfreelist/freeList/ram_configurable/VDD} 97 | # 98 | #connect_supply_net VSS -ports {VSS RMT/VSS \ 99 | # specfreelist/freeList/ram_configurable/VSS} 100 | 101 | #set_scope 102 | #connect_supply_net VDD -ports {RMT/VDD} 103 | # 104 | #connect_supply_net VSS -ports {RMT/VSS} 105 | 106 | 107 | -------------------------------------------------------------------------------- /execute/ForwardCheck.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | `timescale 1ns/100ps 20 | 21 | 22 | module ForwardCheck ( 23 | input [`SIZE_PHYSICAL_LOG-1:0] srcReg_i, 24 | input [`SIZE_DATA-1:0] srcData_i, 25 | 26 | input bypassPkt bypassPacket_i [0:`ISSUE_WIDTH-1], 27 | 28 | output [`SIZE_DATA-1:0] dataOut_o 29 | ); 30 | 31 | reg [`SIZE_DATA-1:0] dataOut; 32 | 33 | 34 | assign dataOut_o = dataOut; 35 | 36 | always_comb 37 | begin:FORWARD_CHECK 38 | int i; 39 | reg [`ISSUE_WIDTH-1:0] match; 40 | 41 | for (i = 0; i < `ISSUE_WIDTH; i = i + 1) 42 | begin 43 | match[i] = bypassPacket_i[i].valid && (srcReg_i == bypassPacket_i[i].tag); 44 | end 45 | 46 | case (match) // synopsys full_case 47 | 8'b00000000: dataOut = srcData_i; 48 | 49 | 8'b00000001: 50 | begin 51 | /* dataOut = {bypassPacket_i[0].byte3, bypassPacket_i[0].byte2, bypassPacket_i[0].byte1, bypassPacket_i[0].byte0}; */ 52 | dataOut = bypassPacket_i[0].data; 53 | end 54 | 55 | 8'b00000010: 56 | begin 57 | /* dataOut = {bypassPacket_i[1].byte3, bypassPacket_i[1].byte2, bypassPacket_i[1].byte1, bypassPacket_i[1].byte0}; */ 58 | dataOut = bypassPacket_i[1].data; 59 | end 60 | 61 | 8'b00000100: 62 | begin 63 | /* dataOut = {bypassPacket_i[2].byte3, bypassPacket_i[2].byte2, bypassPacket_i[2].byte1, bypassPacket_i[2].byte0}; */ 64 | dataOut = bypassPacket_i[2].data; 65 | end 66 | 67 | `ifdef ISSUE_FOUR_WIDE 68 | 8'b00001000: 69 | begin 70 | /* dataOut = {bypassPacket_i[3].byte3, bypassPacket_i[3].byte2, bypassPacket_i[3].byte1, bypassPacket_i[3].byte0}; */ 71 | dataOut = bypassPacket_i[3].data; 72 | end 73 | `endif 74 | 75 | `ifdef ISSUE_FIVE_WIDE 76 | 8'b00010000: 77 | begin 78 | /* dataOut = {bypassPacket_i[4].byte3, bypassPacket_i[4].byte2, bypassPacket_i[4].byte1, bypassPacket_i[4].byte0}; */ 79 | dataOut = bypassPacket_i[4].data; 80 | end 81 | `endif 82 | 83 | `ifdef ISSUE_SIX_WIDE 84 | 8'b00100000: 85 | begin 86 | /* dataOut = {bypassPacket_i[5].byte3, bypassPacket_i[5].byte2, bypassPacket_i[5].byte1, bypassPacket_i[5].byte0}; */ 87 | dataOut = bypassPacket_i[5].data; 88 | end 89 | `endif 90 | 91 | `ifdef ISSUE_SEVEN_WIDE 92 | 8'b01000000: 93 | begin 94 | /* dataOut = {bypassPacket_i[6].byte3, bypassPacket_i[6].byte2, bypassPacket_i[6].byte1, bypassPacket_i[6].byte0}; */ 95 | dataOut = bypassPacket_i[6].data; 96 | end 97 | `endif 98 | 99 | `ifdef ISSUE_EIGHT_WIDE 100 | 8'b10000000: 101 | begin 102 | /* dataOut = {bypassPacket_i[7].byte3, bypassPacket_i[7].byte2, bypassPacket_i[7].byte1, bypassPacket_i[7].byte0}; */ 103 | dataOut = bypassPacket_i[7].data; 104 | end 105 | `endif 106 | endcase 107 | end 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /rams/RAM_8R4W.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | # NORTH CAROLINA STATE UNIVERSITY 3 | # 4 | # AnyCore Project 5 | # 6 | # AnyCore written by NCSU authors Rangeen Basu Roy Chowdhury and Eric Rotenberg. 7 | # 8 | # AnyCore is based on FabScalar which was written by NCSU authors Niket K. 9 | # Choudhary, Brandon H. Dwiel, and Eric Rotenberg. 10 | # 11 | # AnyCore also includes contributions by NCSU authors Elliott Forbes, Jayneel 12 | # Gandhi, Anil Kumar Kannepalli, Sungkwan Ku, Hiran Mayukh, Hashem Hashemi 13 | # Najaf-abadi, Sandeep Navada, Tanmay Shah, Ashlesha Shastri, Vinesh Srinivasan, 14 | # and Salil Wadhavkar. 15 | # 16 | # AnyCore is distributed under the BSD license. 17 | *******************************************************************************/ 18 | 19 | 20 | `timescale 1ns/100ps 21 | 22 | module RAM_8R4W( 23 | clk, 24 | reset, 25 | 26 | addr0_i, 27 | addr1_i, 28 | addr2_i, 29 | addr3_i, 30 | addr4_i, 31 | addr5_i, 32 | addr6_i, 33 | addr7_i, 34 | addr0wr_i, 35 | addr1wr_i, 36 | addr2wr_i, 37 | addr3wr_i, 38 | we0_i, 39 | we1_i, 40 | we2_i, 41 | we3_i, 42 | data0wr_i, 43 | data1wr_i, 44 | data2wr_i, 45 | data3wr_i, 46 | 47 | data0_o, 48 | data1_o, 49 | data2_o, 50 | data3_o, 51 | data4_o, 52 | data5_o, 53 | data6_o, 54 | data7_o 55 | ); 56 | 57 | /* Parameters */ 58 | parameter DEPTH = 16; 59 | parameter INDEX = 4; 60 | parameter WIDTH = 8; 61 | 62 | /* Input and output wires and regs */ 63 | input wire clk; 64 | input wire reset; 65 | 66 | input wire [INDEX-1:0] addr0_i; 67 | input wire [INDEX-1:0] addr1_i; 68 | input wire [INDEX-1:0] addr2_i; 69 | input wire [INDEX-1:0] addr3_i; 70 | input wire [INDEX-1:0] addr4_i; 71 | input wire [INDEX-1:0] addr5_i; 72 | input wire [INDEX-1:0] addr6_i; 73 | input wire [INDEX-1:0] addr7_i; 74 | input wire [INDEX-1:0] addr0wr_i; 75 | input wire [INDEX-1:0] addr1wr_i; 76 | input wire [INDEX-1:0] addr2wr_i; 77 | input wire [INDEX-1:0] addr3wr_i; 78 | input wire we0_i; 79 | input wire we1_i; 80 | input wire we2_i; 81 | input wire we3_i; 82 | input wire [WIDTH-1:0] data0wr_i; 83 | input wire [WIDTH-1:0] data1wr_i; 84 | input wire [WIDTH-1:0] data2wr_i; 85 | input wire [WIDTH-1:0] data3wr_i; 86 | 87 | output wire [WIDTH-1:0] data0_o; 88 | output wire [WIDTH-1:0] data1_o; 89 | output wire [WIDTH-1:0] data2_o; 90 | output wire [WIDTH-1:0] data3_o; 91 | output wire [WIDTH-1:0] data4_o; 92 | output wire [WIDTH-1:0] data5_o; 93 | output wire [WIDTH-1:0] data6_o; 94 | output wire [WIDTH-1:0] data7_o; 95 | 96 | /* The ram reg */ 97 | reg [WIDTH-1:0] ram [DEPTH-1:0]; 98 | 99 | integer i; 100 | 101 | /* Read operation */ 102 | assign data0_o = ram[addr0_i]; 103 | assign data1_o = ram[addr1_i]; 104 | assign data2_o = ram[addr2_i]; 105 | assign data3_o = ram[addr3_i]; 106 | assign data4_o = ram[addr4_i]; 107 | assign data5_o = ram[addr5_i]; 108 | assign data6_o = ram[addr6_i]; 109 | assign data7_o = ram[addr7_i]; 110 | 111 | /* Write operation */ 112 | always @(posedge clk) 113 | begin 114 | 115 | if(reset == 1'b1) 116 | begin 117 | for(i=0; i