├── repos └── README.md ├── .gitignore ├── clone.py ├── LICENSE └── README.md /repos/README.md: -------------------------------------------------------------------------------- 1 | Empty directory. Cloned repos go here. 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | #Temp Diro for clones 3 | repos 4 | 5 | #Editor files 6 | *~ 7 | *.log 8 | tmp* 9 | 10 | # Byte-compiled / optimized / DLL files 11 | __pycache__/ -------------------------------------------------------------------------------- /clone.py: -------------------------------------------------------------------------------- 1 | # Use at your own risk!!!! 2 | import os 3 | import re 4 | import sys 5 | import glob 6 | 7 | repos = [] 8 | # match repos 9 | os.chdir('repos') 10 | with open("../README.md") as f: 11 | for line in f: 12 | match = re.search(r'\((https://.*)\)', line) 13 | if match: 14 | repos.append(match.group(1)) 15 | 16 | # clone repos into 'repos' 17 | for name in repos: 18 | os.system(f"git clone {name}") 19 | 20 | # get sizes of all repos 21 | dirs = glob.glob("*") 22 | for name in dirs: 23 | os.system(f"du -sh {name}") 24 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2016 Andreas Olofsson 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # awesome-opensource-hardware 2 | 3 | A curated list of awesome open source hardware tools. 4 | 5 | * Categorized 6 | * Alphabetical (per category) 7 | * Requirements 8 | * link should be to source code repository 9 | * open source projects only 10 | * working projects only (not WIP/rusty) 11 | * One tag line sentence per project. 12 | 13 | ## Accelerators 14 | 15 | * [aes](https://github.com/secworks/aes) 16 | * Symmetric block cipher AES (Advanced Encryption Standard) 17 | * [ara](https://github.com/pulp-platform/ara) 18 | * Vector Unit, compatible with the RISC-V Vector Extension 19 | * [BISMO](https://github.com/EECS-NTNU/bismo/) 20 | * Chisel-based bit-serial matrix multiplication accelerator generator 21 | * [FINN](https://github.com/Xilinx/finn) 22 | * Quantized NN to FPGA dataflow accelerator generator 23 | * [FFTGenerator](https://github.com/ucb-bar/FFTGenerator) 24 | * MMIO-Based FFT Generator 25 | * [fpu](https://github.com/dawsonjon/fpu) 26 | * Synthesizable ieee 754 floating point library in verilog 27 | * [garnet](https://github.com/StanfordAHA/garnet) 28 | * CGRA generator 29 | * [gemmini](https://github.com/ucb-bar/gemmini) 30 | * Berkeley Spatial Array Generator 31 | * [gplgpu](https://github.com/asicguy/gplgpu) 32 | * GPL v3 2D/3D graphics engine in verilog 33 | * [core_jpeg](https://github.com/ultraembedded/core_jpeg) 34 | * High throughput JPEG decoder in Verilog for FPGA 35 | * [fftgenerator](https://github.com/ucb-bar/FFTGenerator) 36 | * Chisel based FFT generator 37 | * [h265-encoder-rtl](https://github.com/openasic-org/h265-encoder-rtl) 38 | * H.265 Video Encoder IP Core 39 | * [LogicNets](https://github.com/Xilinx/logicnets) 40 | * Train and generate LUT-based neural networks 41 | * [nvdla](https://github.com/nvdla/hw) 42 | * NVIDIA Deep Learning Accelerator (NVDLA) 43 | * [NyuziProcessor](https://github.com/jbush001/NyuziProcessor) 44 | * GPGPU microprocessor architecture 45 | * [openofdm](https://github.com/jhshi/openofdm) 46 | * 802.11 OFDM PHY decoder 47 | * [sha3](https://github.com/ucb-bar/sha3) 48 | * Berkeley SHAR3 ROCC Accelerator 49 | * [Serpens](https://github.com/linghaosong/Serpens) 50 | * HBM FPGA based SpMV Accelerator 51 | * [Sextans](https://github.com/linghaosong/Sextans) 52 | * FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM) 53 | * [spiral](https://github.com/spiral-software/spiral-software) 54 | * Spiral based FFT generator 55 | * [tvm-vta](https://github.com/apache/tvm-vta) 56 | * Opwn, modular, deep learning accelerator 57 | * [VeriGOOD-ML](https://github.com/VeriGOOD-ML/public) 58 | * Verilog Generator, Optimized for Designs for Machine Learning 59 | * [VeriGPU](https://github.com/hughperkins/VeriGPU) 60 | * OpenSource GPU, loosely based on RISC-V ISA 61 | * [verilog-lfsr](https://github.com/alexforencich/verilog-lfsr) 62 | * Parametrizable combinatorial parallel LFSR/CRC module 63 | * [vortex](https://github.com/vortexgpgpu/vortex) 64 | * Full-system RISCV-based GPGPU processor 65 | 66 | ## Analog 67 | 68 | * [AMS_KGD](https://github.com/USCPOSH/AMS_KGD) 69 | * Repository for Known Good Analog Designs (KGDs) 70 | * [open-pmic](https://github.com/westonb/open-pmic) 71 | * Current mode buck converter on the SKY130 PDK 72 | * [Analog Basic Blocks/LDO](https://github.com/mabrains/Analog_blocks) 73 | * Repo that has designs with the following: OTA, BandGap and LDO design on Skywaters 130nm. 74 | 75 | ## Boards 76 | 77 | * [parallella-hw](https://github.com/parallella/parallella-hw) 78 | * Parallella board design files 79 | 80 | ## Connectivity 81 | 82 | * [aib](https://github.com/chipsalliance/aib-phy-hardware) 83 | * Advanced Interface Bus (AIB) die to die hardware 84 | * [aib-protocols](https://github.com/chipsalliance/aib-protocols) 85 | * Advanced Interface Bus (AIB) Protocol IP 86 | * [axi](https://github.com/pulp-platform/axi) 87 | * AXI SystemVerilog synthesizable IP 88 | * [axi4_aib_bridge](https://github.com/lmco/axi4_aib_bridge) 89 | * AXI4/AIB Bridge RTL 90 | * [core_ddr3_controller](https://github.com/ultraembedded/core_ddr3_controller) 91 | * DDR3 memory controller in Verilog for various FPGAs 92 | * [hdmi](https://github.com/hdl-util/hdmi) 93 | * Send video/audio over HDMI on an FPGA 94 | * [i2c](https://github.com/hdl-util/i2c) 95 | * Fully featured implementation of Inter-IC (I2C) bus master 96 | * [litedram](https://github.com/enjoy-digital/litedram) 97 | * Small footprint and configurable DRAM (litex) 98 | * [liteeth](https://github.com/enjoy-digital/liteeth) 99 | * Small footprint and configurable Ethernet core 100 | * [litescope](https://github.com/enjoy-digital/litescope) 101 | * Small footprint and configurable embedded FPGA logic analyzer 102 | * [litepice](https://github.com/enjoy-digital/litepcie) 103 | * Small footprint and configurable PCIe core 104 | * [nocrouter](https://github.com/agalimberti/NoCRouter) 105 | * Network-on-Chip Router 106 | * [OpenSERDES](https://github.com/SparcLab/OpenSERDES) 107 | * Digitally synthesizable architecture for SerDes using Skywater130 108 | * [pymtl3-net](https://github.com/cornell-brg/pymtl3-net) 109 | * Cornell parameterizable OCN (on-chip network) generator 110 | * [ravenoc](https://github.com/aignacio/ravenoc) 111 | * Configurable HDL NoC (Network-On-Chip) 112 | * [tnoc](https://github.com/taichi-ishitani/tnoc) 113 | * Network on Chip Implementation written in SytemVerilog 114 | * [USB_C_Industrial_Camera_FPGA_USB3](https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3) 115 | * USB C Industrial Camera Project 116 | * [verilog-axis](https://github.com/alexforencich/verilog-axis) 117 | * Verilog AXI stream components for FPGA implementation 118 | * [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) 119 | * Verilog Ethernet components for FPGA implementation 120 | * [verilog-i2c](https://github.com/alexforencich/verilog-i2c) 121 | * Verilog I2C interface for FPGA implementation 122 | * [verilog-uart](https://github.com/alexforencich/verilog-uart) 123 | * Verilog UART 124 | * [verilog-pcie](https://github.com/alexforencich/verilog-pcie) 125 | * Verilog PCI express components 126 | * [verilog-wishbone](https://github.com/alexforencich/verilog-wishbone) 127 | * Verilog wishbone components 128 | * [wav-d2d-hw](https://github.com/waviousllc/wav-d2d-hw) 129 | * 8lane Wlink with D2D and a single AXI Target/Initiator 130 | * [wav-lpddr-hw](https://github.com/waviousllc/wav-lpddr-hw) 131 | * DDR (WDDR) Physical interface (PHY) Hardware 132 | * [wav-slink-hw](https://github.com/waviousllc/wav-slink-hw) 133 | * Chiplet link 134 | * [wav-wlink-hw](https://github.com/waviousllc/wav-wlink-hw) 135 | * Chiplet link 136 | 137 | ## CPU cores 138 | 139 | * [a2i](https://github.com/openpower-cores/a2i) 140 | * A2I POWER processor core RTL (VHDL) 141 | * [black-parrot](https://github.com/black-parrot/black-parrot) 142 | * Linux-capable RISC-V multicore 143 | * [Cores-SweRV](https://github.com/chipsalliance/Cores-SweRV) 144 | * SweRV EH1 RISC-Vcore 145 | * [Cores-SweRV-EL2](https://github.com/chipsalliance/Cores-SweRV-EL2) 146 | * SweRV EL2 RISC-V Core 147 | * [core-v-verif](https://github.com/openhwgroup/core-v-verif) 148 | * Functional verification project for the CORE-V family of RISC-V cores 149 | * [cva6](https://github.com/openhwgroup/cva6) 150 | * Linux capable RISC-V CPU 151 | * [cv32e40p](https://github.com/openhwgroup/cv32e40p) 152 | * RV32IMFCX RISC-V 4-stage RISC-V CPU 153 | * [ibex](https://github.com/lowRISC/ibex) 154 | * Small 32 bit RISC-V CPU core 155 | * [microwatt](https://github.com/antonblanchard/microwatt) 156 | * Open POWER ISA softcore written in VHDL 2008 157 | * [muntjac](https://github.com/lowRISC/muntjac) 158 | * Simple 64-bit RISC-V multicore processor 159 | * [neorv32](https://github.com/stnolting/neorv32) 160 | * Customizable and highly extensible MCU-class 32-bit RISC-V (VHDL) 161 | * [OpenXiangShan](https://github.com/OpenXiangShan/XiangShan) 162 | * Open-source high-performance RISC-V processor 163 | * [picorv32](https://github.com/YosysHQ/picorv32) 164 | * Size-Optimized RISC-V CPU 165 | * [rocket-chip](https://github.com/chipsalliance/rocket-chip) 166 | * Linux capable RISC-V Rocket Chip Generator 167 | * [rioschip](https://github.com/b224hisl/rioschip) 168 | * Out of order RISC-V core 169 | * [serv](https://github.com/olofk/serv) 170 | * SErial RISC-V CPU 171 | * [snitch](https://github.com/pulp-platform/snitch) 172 | * Lean but mean RISC-V system 173 | 174 | ## FPGAs 175 | 176 | * [FABulous](https://github.com/FPGA-Research-Manchester/FABulous) 177 | * Fabric generator and CAD tools 178 | * [fabric_team](https://github.com/ucb-cs250/fabric_team) 179 | * ucb-cs250 FPGA class project 180 | * [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) 181 | * FPGA IP Generator 182 | * [prga](https://github.com/PrincetonUniversity/prga) 183 | * Open-source FPGA research and prototyping framework 184 | 185 | ## Libraries 186 | 187 | * [basejump_stl](https://github.com/bespoke-silicon-group/basejump_stl) 188 | * Library of SystemVerilog components 189 | * [basic_verilog](https://github.com/pConst/basic_verilog) 190 | * Library of SystemVerilog components 191 | * [common_cells](https://github.com/pulp-platform/common_cells) 192 | * Library of SystemVerilog components 193 | * [hdl](https://github.com/analogdevicesinc/hdl) 194 | * Library of Analog Deveices specific components 195 | * [oh](https://github.com/aolofsson/oh) 196 | * Library of Verilog components 197 | * [pzbcm](https://github.com/pezy-computing/pzbcm) 198 | * Basic common modules 199 | * [vlsiffra](https://github.com/antonblanchard/vlsiffra) 200 | * Fast and efficient standard cell based adders, multipliers and multiply-adders 201 | 202 | 203 | ## Memory 204 | * [core_axi_cache](https://github.com/ultraembedded/core_axi_cache) 205 | * 128KB AXI cache (32-bit in, 256-bit out) 206 | * [HuanCun](https://github.com/OpenXiangShan/HuanCun) 207 | * Open-source high-performance non-blocking cache 208 | * [openram](https://github.com/VLSIDA/OpenRAM) 209 | * Static random access memory (SRAM) compiler. 210 | * [lake](https://github.com/StanfordAHA/lake) 211 | * Synthesizable memory generator 212 | 213 | ## Packaging 214 | 215 | * [bsg_packaging](https://github.com/bespoke-silicon-group/bsg_packaging) 216 | * Open-Source Hardware Accelerator Packages and Sockets 217 | 218 | ## Retro 219 | 220 | * [VerilogBoy](https://github.com/zephray/VerilogBoy) 221 | * Game Boy compatible machine with Verilog 222 | 223 | ## Systems 224 | 225 | * [Beagle_SDR_GPS](https://github.com/jks-prv/Beagle_SDR_GPS) 226 | * KiwiSDR: BeagleBone web-accessible GPS/SDR 227 | * [bsg_manycore](https://github.com/bespoke-silicon-group/bsg_manycore) 228 | * Tile based architecture designed for computing efficiency, scalability 229 | * [cep](https://github.com/CommonEvaluationPlatform/CEP) 230 | * RISC-V based Common Evaluation Platform (CEP) 231 | * [esp](https://github.com/sld-columbia/esp) 232 | * Heterogeneous SoC architecture and IP design platform 233 | * [hero](https://github.com/pulp-platform/hero) 234 | * FPGA-based research platform for heterogeneous design 235 | * [litex](https://github.com/enjoy-digital/litex) 236 | * SoC builder framework 237 | * [openFASOC](https://github.com/idea-fasoc/OpenFASOC) 238 | * Open Source FASOC generators 239 | * [openpiton](https://github.com/PrincetonUniversity/openpiton) 240 | * General purpose, multithreaded manycore processor 241 | * [opentitan](https://github.com/lowRISC/opentitan) 242 | * Open source silicon root of trust 243 | * [openwifi-hw](https://github.com/open-sdr/openwifi-hw) 244 | * IEEE 802.11 WiFi baseband FPGA (chip) design 245 | * [pulp](https://github.com/pulp-platform/pulp) 246 | * Multicore RISC-V based SoC 247 | * [pulpissimo](https://github.com/pulp-platform/pulpissimo) 248 | * Single core RISC-V based SoC 249 | * [SensSeq](https://github.com/EMIL-YORKU/SensSeq) 250 | * Mixed-signal system on chip for nanopore-based DNA sequencing 251 | --------------------------------------------------------------------------------