├── project_desc.pdf ├── Screenshots └── overall_schematic.jpg ├── pins.ucf ├── freq_divider.vhd ├── color_generator.vhd ├── LICENSE ├── README.md ├── v_sync_gen.vhd ├── h_sync_gen.vhd └── vga_driver.vhd /project_desc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/arasgungore/256-colors-with-VGA/HEAD/project_desc.pdf -------------------------------------------------------------------------------- /Screenshots/overall_schematic.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/arasgungore/256-colors-with-VGA/HEAD/Screenshots/overall_schematic.jpg -------------------------------------------------------------------------------- /pins.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Pin assignments for the Nexys3 Board. 3 | # 4 | net board_clk loc=V10; # 100 MHz board clock 5 | net vsync loc=P7; # VGA-VSYNC 6 | net hsync loc=N6; # VGA-HSYNC 7 | net red<0> loc=U7; # VGA-RED0 8 | net red<1> loc=V7; # VGA-RED1 9 | net red<2> loc=N7; # VGA-RED2 10 | net green<0> loc=P8; # VGA-GRN0 11 | net green<1> loc=T6; # VGA-GRN1 12 | net green<2> loc=V6; # VGA-GRN2 13 | net blue<0> loc=R7; # VGA-BLU1 14 | net blue<1> loc=T7; # VGA-BLU2 15 | -------------------------------------------------------------------------------- /freq_divider.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | use IEEE.STD_LOGIC_ARITH.ALL; 5 | 6 | 7 | entity frequency_divider is 8 | port ( 9 | Reset : in STD_LOGIC; 10 | Clk_in : in STD_LOGIC; 11 | Clk_out : out STD_LOGIC 12 | ); 13 | end frequency_divider; 14 | 15 | 16 | architecture Behavioral of frequency_divider is 17 | 18 | signal count : STD_LOGIC_VECTOR(1 downto 0) := (others => '0'); 19 | 20 | begin 21 | 22 | my_freq_div : process(Clk_in) 23 | begin 24 | 25 | if rising_edge(Clk_in) then 26 | if Reset = '1' then 27 | count <= (others => '0'); 28 | else 29 | count <= count + 1; 30 | if count = "11" then 31 | Clk_out <= '1'; 32 | else 33 | Clk_out <= '0'; 34 | end if; 35 | end if; 36 | end if; 37 | 38 | end process my_freq_div; 39 | 40 | end Behavioral; -------------------------------------------------------------------------------- /color_generator.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_ARITH.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | 7 | entity color_generator is 8 | port ( 9 | Enable : in STD_LOGIC; 10 | Reset : in STD_LOGIC; 11 | Clk : in STD_LOGIC; 12 | red : out STD_LOGIC_VECTOR(2 downto 0); 13 | green : out STD_LOGIC_VECTOR(2 downto 0); 14 | blue : out STD_LOGIC_VECTOR(1 downto 0) 15 | ); 16 | end color_generator; 17 | 18 | 19 | architecture Behavioral of color_generator is 20 | 21 | signal count : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 22 | 23 | begin 24 | 25 | my_counter : process(Clk) 26 | begin 27 | 28 | if rising_edge(Clk) then 29 | if Reset = '1' then 30 | count <= (others => '0'); 31 | elsif Enable = '1' then 32 | count <= count + 1; 33 | end if; 34 | end if; 35 | 36 | end process my_counter; 37 | 38 | red <= count(7 downto 5); 39 | green <= count(4 downto 2); 40 | blue <= count(1 downto 0); 41 | 42 | end Behavioral; -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Aras Güngöre 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 256-colors-with-VGA 2 | 3 | A VHDL-based VGA driver to display 256 different colors on a monitor. Two-timing signals are generated in this system, vsync and hsync to synchronize the plotting of vertical and horizontal pixels, respectively. The color data of each pixel is generated using an 8-bit counter whose first 3 bits are for red, the next 3 bits are for green and the last 2 bits are for blue color data while the synchronization signals are generated. This way, as the counter counts, 256 different color combinations are displayed on the screen one after another. This counter is implemented on the FPGA board. 4 | 5 | This lab was assigned for the Digital System Design (EE 240) course in the Spring 2021 semester. 6 | 7 | 8 | 9 | ## Overall Schematic 10 | 11 |

12 | Schematic 13 |

14 | 15 | 16 | 17 | ## Author 18 | 19 | 👤 **Aras Güngöre** 20 | 21 | * LinkedIn: [@arasgungore](https://www.linkedin.com/in/arasgungore) 22 | * GitHub: [@arasgungore](https://github.com/arasgungore) 23 | -------------------------------------------------------------------------------- /v_sync_gen.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_ARITH.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | 7 | entity v_sync_generator is 8 | port ( 9 | Clk : in STD_LOGIC; 10 | Enable : in STD_LOGIC; 11 | V_sync : out STD_LOGIC; 12 | Reset_color : out STD_LOGIC 13 | ); 14 | end v_sync_generator; 15 | 16 | 17 | architecture Behavioral of v_sync_generator is 18 | 19 | signal Reset : STD_LOGIC := '0'; 20 | 21 | -- In lines, to get these times by clocks multiply them by 800, which is horizontal sync pulse time. 22 | constant v_sync_pulse_time : integer := 521; 23 | constant v_pulse_width : integer := 2; 24 | constant v_front_porch : integer := 10; 25 | constant v_back_porch : integer := 29; 26 | 27 | begin 28 | 29 | v_process : process(Clk, Enable) 30 | 31 | variable count : integer range 1 to v_sync_pulse_time := 1; 32 | 33 | begin 34 | 35 | -- Behavioral Clock 36 | if rising_edge(Clk) then 37 | if Reset = '1' then 38 | count := 1; 39 | elsif Enable = '1' then 40 | count := count + 1; 41 | end if; 42 | end if; 43 | 44 | -- Sync pulse time = 521 lines, so we reset the clock when count = 521 is reached. 45 | if count = v_sync_pulse_time then 46 | Reset <= '1'; 47 | else 48 | Reset <= '0'; 49 | end if; 50 | 51 | -- Pulse width + back porch = 2 + 29 = 31, sync pulse time - front porch = 521 - 10 = 511. 52 | -- This corresponds to T_disp, beside T_disp we have to reset the colors. 53 | if (v_pulse_width + v_back_porch) < count and count < (v_sync_pulse_time - v_front_porch) then 54 | Reset_color <= '0'; 55 | else 56 | Reset_color <= '1'; 57 | end if; 58 | 59 | -- Pulse width = 2, so if count > pulse_width then V_sync has to be 1. 60 | if v_pulse_width < count then 61 | V_sync <= '1'; 62 | else 63 | V_sync <= '0'; 64 | end if; 65 | 66 | end process v_process; 67 | 68 | end Behavioral; -------------------------------------------------------------------------------- /h_sync_gen.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_ARITH.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | 7 | entity h_sync_generator is 8 | port ( 9 | Clk : in STD_LOGIC; 10 | Enable : in STD_LOGIC; 11 | H_sync : out STD_LOGIC; 12 | Reset_color : out STD_LOGIC; 13 | V_enable : out STD_LOGIC 14 | ); 15 | end h_sync_generator; 16 | 17 | 18 | architecture Behavioral of h_sync_generator is 19 | 20 | signal Reset : STD_LOGIC := '0'; 21 | 22 | -- In clocks 23 | constant h_sync_pulse_time : integer := 800; 24 | constant h_pulse_width : integer := 96; 25 | constant h_front_porch : integer := 16; 26 | constant h_back_porch : integer := 48; 27 | 28 | begin 29 | 30 | h_process : process(Clk, Enable) 31 | 32 | variable count : integer range 1 to h_sync_pulse_time := 1; 33 | 34 | begin 35 | 36 | -- Behavioral Clock 37 | if rising_edge(Clk) then 38 | if Reset = '1' then 39 | count := 1; 40 | elsif Enable = '1' then 41 | count := count + 1; 42 | end if; 43 | end if; 44 | 45 | -- Sync pulse time = 800 clocks, so we reset the clock when count = 800 is reached. 46 | -- Also we set V_enable = 1 because we are moving to a new line since horizontal is finished. 47 | if count = h_sync_pulse_time then 48 | V_enable <= '1'; 49 | Reset <= '1'; 50 | else 51 | V_enable <= '0'; 52 | Reset <= '0'; 53 | end if; 54 | 55 | -- Pulse width + back porch = 96 + 48 = 144, sync pulse time - front porch = 800 - 16 = 784. 56 | -- This corresponds to T_disp, beside T_disp we have to reset the colors. 57 | if (h_pulse_width + h_back_porch) < count and count < (h_sync_pulse_time - h_front_porch) then 58 | Reset_color <= '0'; 59 | else 60 | Reset_color <= '1'; 61 | end if; 62 | 63 | -- Pulse width = 96, so if count > pulse_width then H_sync has to be 1. 64 | if h_pulse_width < count then 65 | H_sync <= '1'; 66 | else 67 | H_sync <= '0'; 68 | end if; 69 | 70 | end process h_process; 71 | 72 | end Behavioral; -------------------------------------------------------------------------------- /vga_driver.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_SIGNED.ALL; 4 | use IEEE.STD_LOGIC_ARITH.ALL; 5 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 6 | 7 | 8 | entity ee240_vgadriver is 9 | port ( 10 | board_clk : in STD_LOGIC; 11 | vsync : out STD_LOGIC; 12 | hsync : out STD_LOGIC; 13 | red : out STD_LOGIC_VECTOR(2 downto 0); 14 | green : out STD_LOGIC_VECTOR(2 downto 0); 15 | blue : out STD_LOGIC_VECTOR(1 downto 0) 16 | ); 17 | end ee240_vgadriver; 18 | 19 | 20 | architecture arch_vga_driver of ee240_vgadriver is 21 | 22 | 23 | component frequency_divider is 24 | port ( 25 | Reset : in STD_LOGIC; 26 | Clk_in : in STD_LOGIC; 27 | Clk_out : out STD_LOGIC 28 | ); 29 | end component; 30 | 31 | component color_generator is 32 | port ( 33 | Enable : in STD_LOGIC; 34 | Reset : in STD_LOGIC; 35 | Clk : in STD_LOGIC; 36 | red : out STD_LOGIC_VECTOR(2 downto 0); 37 | green : out STD_LOGIC_VECTOR(2 downto 0); 38 | blue : out STD_LOGIC_VECTOR(1 downto 0) 39 | ); 40 | end component; 41 | 42 | component h_sync_generator is 43 | port ( 44 | Clk : in STD_LOGIC; 45 | Enable : in STD_LOGIC; 46 | H_sync : out STD_LOGIC; 47 | Reset_color : out STD_LOGIC; 48 | V_enable : out STD_LOGIC 49 | ); 50 | end component; 51 | 52 | component v_sync_generator is 53 | port ( 54 | Clk : in STD_LOGIC; 55 | Enable : in STD_LOGIC; 56 | V_sync : out STD_LOGIC; 57 | Reset_color : out STD_LOGIC 58 | ); 59 | end component; 60 | 61 | 62 | signal clk_div, v_sync_gen_enable, reset, h_reset, v_reset : STD_LOGIC; 63 | signal count : STD_LOGIC_VECTOR(7 downto 0); 64 | 65 | 66 | begin 67 | 68 | freq_div : frequency_divider -- 100 MHz to 25 MHz, divide by 4 69 | port map('0', board_clk, clk_div); 70 | 71 | h_sync_gen : h_sync_generator 72 | port map(board_clk, clk_div, hsync, h_reset, v_sync_gen_enable); 73 | 74 | v_sync_gen : v_sync_generator 75 | port map(board_clk, v_sync_gen_enable, vsync, v_reset); 76 | 77 | reset <= h_reset or v_reset; 78 | 79 | eight_bit_cnt : color_generator 80 | port map(clk_div, reset, board_clk, red, green, blue); 81 | 82 | end arch_vga_driver; --------------------------------------------------------------------------------