├── Matlab_Script
├── 1.png
├── 2.png
└── UART.m
├── README.md
└── src
├── Data_Process.v
├── Data_collect.v
├── Data_collect_tb.v
├── Data_send.v
├── MEM.v
├── MEM_tb.v
├── PLL_9_6K.v
├── PLL_9_6M.v
├── clk_divide.v
├── clk_divide_tb.v
├── integrated.v
├── integrated_test.v
├── receiver_sampler.v
├── receiver_sampler_tb.v
├── reciever.v
├── scan.v
├── scan_new.v
├── scan_test.v
├── semi_systolic.v
├── semi_systolic_final.v
├── systol_new1.v
├── systolic.v
├── systolic_original.v
├── systolic_test.v
├── test_scan_new.v
├── test_systol_new.v
├── test_systolic.v
├── top.ucf
├── top.v
├── top_direct_send.v
├── top_tb.v
└── transmitter.v
/Matlab_Script/1.png:
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https://raw.githubusercontent.com/aravinds92/Systolic-Array/3abee0bd03c160f9652b659168abeb365901e027/Matlab_Script/1.png
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/Matlab_Script/2.png:
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https://raw.githubusercontent.com/aravinds92/Systolic-Array/3abee0bd03c160f9652b659168abeb365901e027/Matlab_Script/2.png
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/Matlab_Script/UART.m:
--------------------------------------------------------------------------------
1 | clear;
2 | close all;
3 | delete(instrfindall);
4 |
5 |
6 | % Read in image and convert to grey scale
7 | Input_IMG = imread('2.png');
8 | subplot(1,3,1), imshow(Input_IMG); title('Original Image');
9 | Input_BW = rgb2gray(Input_IMG);
10 | subplot(1,3,2), imshow(Input_BW); title('Grey Image');
11 |
12 | % Get image size
13 | [row, col] = size(Input_BW);
14 |
15 |
16 | % Open Serial Port
17 | S = serial('COM4', 'BAUD', 9600);
18 | fclose(S);
19 | fopen(S);
20 |
21 |
22 | %{
23 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
24 | % 1.
25 | % Send one image data at a time and read back immediately
26 | % Set the top_direct_send as top_level and program FPGA
27 | % Test this first to determine the functionality of UART on board
28 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
29 | Output_Image = zeros(row, col);
30 | % Send out data row by row
31 | for r = 1 : row
32 | for c = 1 : col
33 | fwrite(S, Input_BW(r,c), 'uint8');
34 | pause(0.000001); % Add delay between each sending!!!!!!!!! Important!
35 | Output_Image(r, c) = fread(S, 1);
36 | end
37 | end
38 | % Plot the received image
39 | subplot(1,3,3), imshow(uint8(Output_Image)); title('Processed Image');
40 | %}
41 |
42 |
43 | %{
44 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
45 | % 2.
46 | % Send a series of data and read back all at once
47 | % Set the top as top_level and program FPGA
48 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
49 | for x = 1:500
50 | fwrite(S, x, 'uint8');
51 | pause(0.000001); % Add delay between each sending!!!!!!!!! Important!
52 | end
53 | for y = 1:5
54 | vec = fread(S, 100);
55 | XXX(y,:) = vec';
56 | end
57 | %}
58 |
59 |
60 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
61 | % 3.
62 | % Send all IMAGE data first then read all back
63 | % Set the top as top_level and program FPGA
64 | % Use this segment of code for Lab
65 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
66 | Output_Image = zeros(row, col);
67 | % Send out data row by row
68 | for r = 1 : row
69 | for c = 1 : col
70 | fwrite(S, Input_BW(r,c), 'uint8');
71 | pause(0.000001); % Add delay between each sending!!!!!!!!! Important!
72 | end
73 | end
74 |
75 | % Add delay between send data and receive data so FPGA can have time to
76 | % process the image data. The delay value is depending on your FPGA
77 | % processing time. If the read operation can't receive data in a certain
78 | % time, the matlab script will timeout and quit.
79 |
80 | % pause(60); % Pause 60 seconds
81 |
82 | for y = 1 : row
83 | vec = fread(S, 100);
84 | Output_Image(y,:) = vec';
85 | end
86 |
87 |
88 | % Plot the received image
89 | subplot(1,3,3), imshow(uint8(Output_Image)); title('Processed Image');
90 |
91 |
92 |
93 | % Close Serial Port
94 | fclose(S);
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # Systolic-Array
2 | Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
3 | Add all the .v files to a Xilinx project
4 | Build the program and get the output .bit file
5 | connect FPGA to PC via a serial connection
6 | run the matlab script on the PC to obtain the processed image from the FPGA
7 |
--------------------------------------------------------------------------------
/src/Data_Process.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 14:50:48 11/02/2015
7 | // Design Name:
8 | // Module Name: Data_Process
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module Data_Process(
22 | input clk,
23 | input rst,
24 | input data_collection_finish,
25 | input data_send_finish,
26 | output reg data_send_run
27 | );
28 | // This is ethan's code for immediately sending all the data back
29 | always@(posedge clk)
30 | begin
31 | if(rst)
32 | data_send_run <= 1'b0;
33 | else if(data_collection_finish) // After 10000 data is received, send 10000 data back to PC
34 | data_send_run <= 1'b1;
35 | else if(data_send_finish) // After sending is finish, clear the data_send signal
36 | data_send_run <= 1'b0;
37 | end
38 | /*
39 |
40 | //my code starts here
41 |
42 | // data_collection_finish is 1 when matlab is done sending all the image data to fpga memory
43 | // data_send_finish is 1 when FPGA is done sending all the processed data to UART
44 | // data_send_run is the output of this file, when we are done processing the data, we will set the data send run to be 1 so that
45 | // we can send the processed data back to UART
46 |
47 | // the major issue is that we have to be sure at what time in seconds we need to start sending data
48 |
49 |
50 | parameter data_collecting = 1, data_processing = 2, data_sending = 3;
51 | wire state = 0;
52 | always@(*)
53 | begin
54 | case(state)
55 | 0: next_state = data_collecting;
56 | 1: begin
57 | if(data_collection_finish)
58 | next_state = data_processing;
59 | end
60 | 2: begin
61 | if(data_process_finish)
62 | next_state = data_sending;
63 | end
64 | default: next_state = 0;
65 |
66 | endcase
67 |
68 | end
69 |
70 | always@(posedge clk)
71 | state = next_state;
72 |
73 | //module scan(read_select, read_data, data_out, clk, start, scan_start);
74 | scan S1 (read_select, read_data, data_out, clk, start, scan_start);*/
75 | endmodule
76 |
--------------------------------------------------------------------------------
/src/Data_collect.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | // Collect 100*100 data from UART
4 | module Data_collect(
5 | input clk,
6 | input rst,
7 | input [7:0] data_input,
8 | input data_ready,
9 | output reg MEM_write_enable,
10 | output reg [13:0] MEM_write_addr,
11 | output reg [7:0] MEM_write_data,
12 | output finish,
13 | output reg collect_finish_display
14 | );
15 |
16 | parameter NUM_DATA = 2500;
17 |
18 | reg [13:0] delayed_write_addr;
19 | reg prev_data_ready;
20 |
21 | assign finish = (MEM_write_addr == NUM_DATA - 1)? 1'b1 : 1'b0; // Collecion is finished after received 10000 data
22 |
23 | always@(posedge finish)
24 | begin
25 | if(rst)
26 | collect_finish_display <= 1'b0;
27 | else
28 | collect_finish_display <= ~collect_finish_display;
29 | end
30 |
31 | always@(posedge clk)
32 | begin
33 | prev_data_ready <= data_ready; // for capturing the rising edge of data_ready
34 | MEM_write_addr <= delayed_write_addr;
35 |
36 | if(rst || MEM_write_addr == NUM_DATA) // Reset when rst == 1 or saved 10000 data
37 | begin
38 | MEM_write_enable <= 1'b0;
39 | delayed_write_addr <= 14'd0;
40 | MEM_write_data <= 8'd0;
41 | end
42 | else if(data_ready == 1'b1 && prev_data_ready == 1'b0)
43 | begin
44 | MEM_write_enable <= 1'b1;
45 | delayed_write_addr <= delayed_write_addr + 1'b1;
46 | MEM_write_data <= data_input;
47 | end
48 | else
49 | begin
50 | MEM_write_enable <= 1'b0;
51 | delayed_write_addr <= delayed_write_addr;
52 | MEM_write_data <= data_input;
53 | end
54 | end
55 | endmodule
56 |
--------------------------------------------------------------------------------
/src/Data_collect_tb.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 15:25:30 11/02/2015
8 | // Design Name: Data_collect
9 | // Module Name: C:/Users/Ethan/Desktop/UART/UART/Data_collect_tb.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: Data_collect
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module Data_collect_tb;
26 |
27 | // Inputs
28 | reg clk;
29 | reg rst;
30 | reg [7:0] data_input;
31 | reg data_ready;
32 |
33 | // Outputs
34 | wire MEM_write_enable;
35 | wire [13:0] MEM_write_addr;
36 | wire [7:0] MEM_write_data;
37 | wire finish;
38 |
39 | // Instantiate the Unit Under Test (UUT)
40 | Data_collect uut (
41 | .clk(clk),
42 | .rst(rst),
43 | .data_input(data_input),
44 | .data_ready(data_ready),
45 | .MEM_write_enable(MEM_write_enable),
46 | .MEM_write_addr(MEM_write_addr),
47 | .MEM_write_data(MEM_write_data),
48 | .finish(finish)
49 | );
50 |
51 | always #1 assign clk = ~clk;
52 | always #5 assign data_ready = ~data_ready;
53 |
54 | initial begin
55 | // Initialize Inputs
56 | clk = 0;
57 | rst = 1;
58 | data_input = 1;
59 | data_ready = 0;
60 |
61 | // Wait 100 ns for global reset to finish
62 | #100;
63 | rst = 0;
64 |
65 | // Add stimulus here
66 |
67 | end
68 |
69 | endmodule
70 |
71 |
--------------------------------------------------------------------------------
/src/Data_send.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 |
4 | // Send 10000 data back to PC
5 | module Data_send(
6 | input clk,
7 | input rst,
8 | input send_start, // Start to send data after this bit is set to 1
9 | input tx_ready, // Send one byte of data after tx_ready
10 | input [7:0] MEM_data,
11 | output reg [13:0] MEM_read_sel,
12 | output [7:0] transmitter_data,
13 | output reg transmitter_start,
14 | output finish
15 | );
16 |
17 | parameter NUM_DATA = 2500; //changed from 10 to 2500
18 |
19 | reg prev_tx_ready;
20 | reg prev_send_start;
21 |
22 | assign transmitter_data = MEM_data;
23 | assign finish = (MEM_read_sel == NUM_DATA)? 1'b1 : 1'b0;
24 |
25 | always@(posedge clk)
26 | begin
27 | prev_tx_ready <= tx_ready;
28 | prev_send_start <= send_start;
29 |
30 | if(rst || MEM_read_sel == NUM_DATA)
31 | begin
32 | MEM_read_sel <= 14'd0;
33 | transmitter_start <= 1'b0;
34 | end
35 | else if(send_start)
36 | begin
37 | if(!prev_send_start && tx_ready)
38 | begin
39 | MEM_read_sel <= 14'd0;
40 | transmitter_start <= 1'b1;
41 | end
42 | if(tx_ready && prev_tx_ready == 0) // Send one byte of data on posedge of tx_ready
43 | begin
44 | MEM_read_sel <= MEM_read_sel + 1'b1;
45 | transmitter_start <= 1'b1;
46 | end
47 | else if(!tx_ready) // Clear the start bit after the transmission is start
48 | begin
49 | MEM_read_sel <= MEM_read_sel;
50 | transmitter_start <= 1'b0;
51 | end
52 | end
53 | end
54 |
55 | endmodule
56 |
--------------------------------------------------------------------------------
/src/MEM.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | // MEM read has no demo in this design
4 |
5 | module MEM(
6 | input clk,
7 | input wr_enable,
8 | input [13:0] write_select,
9 | input [13:0] read_select,
10 | input [7:0] write_data,
11 | output reg [7:0] read_data
12 | );
13 |
14 | parameter NUM_DATA = 2499;
15 |
16 | reg [7:0] Data [NUM_DATA:0];
17 |
18 | always@(posedge clk)
19 | begin
20 | read_data = Data[read_select];
21 | end
22 |
23 |
24 | always@(posedge clk)
25 | begin
26 | if(wr_enable)
27 | Data[write_select] <= write_data;
28 | end
29 |
30 | endmodule
31 |
--------------------------------------------------------------------------------
/src/MEM_tb.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 15:37:31 11/02/2015
8 | // Design Name: MEM
9 | // Module Name: C:/Users/Ethan/Desktop/UART/UART/MEM_tb.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: MEM
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module MEM_tb;
26 |
27 | // Inputs
28 | reg clk;
29 | reg wr_enable;
30 | reg [13:0] write_select;
31 | reg [13:0] read_select;
32 | reg [7:0] write_data;
33 |
34 | // Outputs
35 | wire [7:0] read_data;
36 |
37 | // Instantiate the Unit Under Test (UUT)
38 | MEM uut (
39 | .clk(clk),
40 | .wr_enable(wr_enable),
41 | .write_select(write_select),
42 | .read_select(read_select),
43 | .write_data(write_data),
44 | .read_data(read_data)
45 | );
46 |
47 | always #1 assign clk = ~clk;
48 |
49 | initial begin
50 | // Initialize Inputs
51 | clk = 0;
52 | wr_enable = 0;
53 | write_select = 0;
54 | read_select = 0;
55 | write_data = 0;
56 |
57 | // Wait 100 ns for global reset to finish
58 | #10;
59 | wr_enable = 1;
60 | write_select = 1;
61 | write_data = 9;
62 |
63 | #10;
64 | wr_enable = 0;
65 | read_select = 1;
66 | // Add stimulus here
67 |
68 | end
69 |
70 | endmodule
71 |
72 |
--------------------------------------------------------------------------------
/src/PLL_9_6K.v:
--------------------------------------------------------------------------------
1 | // file: PLL_9_6K.v
2 | //
3 | // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
4 | //
5 | // This file contains confidential and proprietary information
6 | // of Xilinx, Inc. and is protected under U.S. and
7 | // international copyright and other intellectual property
8 | // laws.
9 | //
10 | // DISCLAIMER
11 | // This disclaimer is not a license and does not grant any
12 | // rights to the materials distributed herewith. Except as
13 | // otherwise provided in a valid license issued to you by
14 | // Xilinx, and to the maximum extent permitted by applicable
15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20 | // (2) Xilinx shall not be liable (whether in contract or tort,
21 | // including negligence, or under any other theory of
22 | // liability) for any loss or damage of any kind or nature
23 | // related to, arising under or in connection with these
24 | // materials, including for any direct, or any indirect,
25 | // special, incidental, or consequential loss or damage
26 | // (including loss of data, profits, goodwill, or any type of
27 | // loss or damage suffered as a result of any action brought
28 | // by a third party) even if such damage or loss was
29 | // reasonably foreseeable or Xilinx had been advised of the
30 | // possibility of the same.
31 | //
32 | // CRITICAL APPLICATIONS
33 | // Xilinx products are not designed or intended to be fail-
34 | // safe, or for use in any application requiring fail-safe
35 | // performance, such as life-support or safety devices or
36 | // systems, Class III medical devices, nuclear facilities,
37 | // applications related to the deployment of airbags, or any
38 | // other applications that could lead to death, personal
39 | // injury, or severe property or environmental damage
40 | // (individually and collectively, "Critical
41 | // Applications"). Customer assumes the sole risk and
42 | // liability of any use of Xilinx products in Critical
43 | // Applications, subject only to applicable laws and
44 | // regulations governing limitations on product liability.
45 | //
46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 | // PART OF THIS FILE AT ALL TIMES.
48 | //
49 | //----------------------------------------------------------------------------
50 | // User entered comments
51 | //----------------------------------------------------------------------------
52 | // None
53 | //
54 | //----------------------------------------------------------------------------
55 | // "Output Output Phase Duty Pk-to-Pk Phase"
56 | // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
57 | //----------------------------------------------------------------------------
58 | // CLK_OUT1_____9.600______0.000______50.0______510.000____266.022
59 | //
60 | //----------------------------------------------------------------------------
61 | // "Input Clock Freq (MHz) Input Jitter (UI)"
62 | //----------------------------------------------------------------------------
63 | // __primary_________100.000____________0.010
64 |
65 | `timescale 1ps/1ps
66 |
67 | (* CORE_GENERATION_INFO = "PLL_9_6K,clk_wiz_v3_6,{component_name=PLL_9_6K,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
68 | module PLL_9_6K
69 | (// Clock in ports
70 | input clk_in,
71 | // Clock out ports
72 | output clk_out_9_6k,
73 | // Status and control signals
74 | input rst
75 | );
76 |
77 | // Input buffering
78 | //------------------------------------
79 | IBUFG clkin1_buf
80 | (.O (clkin1),
81 | .I (clk_in));
82 |
83 |
84 | // Clocking primitive
85 | //------------------------------------
86 | // Instantiation of the PLL primitive
87 | // * Unused inputs are tied off
88 | // * Unused outputs are labeled unused
89 | wire [15:0] do_unused;
90 | wire drdy_unused;
91 | wire locked_unused;
92 | wire clkfbout;
93 | wire clkfbout_buf;
94 | wire clkout1_unused;
95 | wire clkout2_unused;
96 | wire clkout3_unused;
97 | wire clkout4_unused;
98 | wire clkout5_unused;
99 |
100 | PLL_BASE
101 | #(.BANDWIDTH ("OPTIMIZED"),
102 | .CLK_FEEDBACK ("CLKFBOUT"),
103 | .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
104 | .DIVCLK_DIVIDE (5),
105 | .CLKFBOUT_MULT (24),
106 | .CLKFBOUT_PHASE (0.000),
107 | .CLKOUT0_DIVIDE (50),
108 | .CLKOUT0_PHASE (0.000),
109 | .CLKOUT0_DUTY_CYCLE (0.500),
110 | .CLKIN_PERIOD (10.000),
111 | .REF_JITTER (0.010))
112 | pll_base_inst
113 | // Output clocks
114 | (.CLKFBOUT (clkfbout),
115 | .CLKOUT0 (clkout0),
116 | .CLKOUT1 (clkout1_unused),
117 | .CLKOUT2 (clkout2_unused),
118 | .CLKOUT3 (clkout3_unused),
119 | .CLKOUT4 (clkout4_unused),
120 | .CLKOUT5 (clkout5_unused),
121 | // Status and control signals
122 | .LOCKED (locked_unused),
123 | .RST (rst),
124 | // Input clock control
125 | .CLKFBIN (clkfbout_buf),
126 | .CLKIN (clkin1));
127 |
128 |
129 | // Output buffering
130 | //-----------------------------------
131 | BUFG clkf_buf
132 | (.O (clkfbout_buf),
133 | .I (clkfbout));
134 |
135 | BUFG clkout1_buf
136 | (.O (clk_out_9_6k),
137 | .I (clkout0));
138 |
139 |
140 |
141 |
142 | endmodule
143 |
--------------------------------------------------------------------------------
/src/PLL_9_6M.v:
--------------------------------------------------------------------------------
1 | // file: PLL_9_6M.v
2 | //
3 | // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
4 | //
5 | // This file contains confidential and proprietary information
6 | // of Xilinx, Inc. and is protected under U.S. and
7 | // international copyright and other intellectual property
8 | // laws.
9 | //
10 | // DISCLAIMER
11 | // This disclaimer is not a license and does not grant any
12 | // rights to the materials distributed herewith. Except as
13 | // otherwise provided in a valid license issued to you by
14 | // Xilinx, and to the maximum extent permitted by applicable
15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20 | // (2) Xilinx shall not be liable (whether in contract or tort,
21 | // including negligence, or under any other theory of
22 | // liability) for any loss or damage of any kind or nature
23 | // related to, arising under or in connection with these
24 | // materials, including for any direct, or any indirect,
25 | // special, incidental, or consequential loss or damage
26 | // (including loss of data, profits, goodwill, or any type of
27 | // loss or damage suffered as a result of any action brought
28 | // by a third party) even if such damage or loss was
29 | // reasonably foreseeable or Xilinx had been advised of the
30 | // possibility of the same.
31 | //
32 | // CRITICAL APPLICATIONS
33 | // Xilinx products are not designed or intended to be fail-
34 | // safe, or for use in any application requiring fail-safe
35 | // performance, such as life-support or safety devices or
36 | // systems, Class III medical devices, nuclear facilities,
37 | // applications related to the deployment of airbags, or any
38 | // other applications that could lead to death, personal
39 | // injury, or severe property or environmental damage
40 | // (individually and collectively, "Critical
41 | // Applications"). Customer assumes the sole risk and
42 | // liability of any use of Xilinx products in Critical
43 | // Applications, subject only to applicable laws and
44 | // regulations governing limitations on product liability.
45 | //
46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 | // PART OF THIS FILE AT ALL TIMES.
48 | //
49 | //----------------------------------------------------------------------------
50 | // User entered comments
51 | //----------------------------------------------------------------------------
52 | // None
53 | //
54 | //----------------------------------------------------------------------------
55 | // "Output Output Phase Duty Pk-to-Pk Phase"
56 | // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
57 | //----------------------------------------------------------------------------
58 | // CLK_OUT1_____9.600______0.000______50.0______510.000____266.022
59 | //
60 | //----------------------------------------------------------------------------
61 | // "Input Clock Freq (MHz) Input Jitter (UI)"
62 | //----------------------------------------------------------------------------
63 | // __primary_________100.000____________0.010
64 |
65 | `timescale 1ps/1ps
66 |
67 | (* CORE_GENERATION_INFO = "PLL_9_6M,clk_wiz_v3_6,{component_name=PLL_9_6M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
68 | module PLL_9_6M
69 | (// Clock in ports
70 | input clk_in,
71 | // Clock out ports
72 | output clk_out_9_6M,
73 | // Status and control signals
74 | input rst
75 | );
76 |
77 | // Input buffering
78 | //------------------------------------
79 | IBUFG clkin1_buf
80 | (.O (clkin1),
81 | .I (clk_in));
82 |
83 |
84 | // Clocking primitive
85 | //------------------------------------
86 | // Instantiation of the PLL primitive
87 | // * Unused inputs are tied off
88 | // * Unused outputs are labeled unused
89 | wire [15:0] do_unused;
90 | wire drdy_unused;
91 | wire locked_unused;
92 | wire clkfbout;
93 | wire clkfbout_buf;
94 | wire clkout1_unused;
95 | wire clkout2_unused;
96 | wire clkout3_unused;
97 | wire clkout4_unused;
98 | wire clkout5_unused;
99 |
100 | PLL_BASE
101 | #(.BANDWIDTH ("OPTIMIZED"),
102 | .CLK_FEEDBACK ("CLKFBOUT"),
103 | .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
104 | .DIVCLK_DIVIDE (5),
105 | .CLKFBOUT_MULT (24),
106 | .CLKFBOUT_PHASE (0.000),
107 | .CLKOUT0_DIVIDE (50),
108 | .CLKOUT0_PHASE (0.000),
109 | .CLKOUT0_DUTY_CYCLE (0.500),
110 | .CLKIN_PERIOD (10.000),
111 | .REF_JITTER (0.010))
112 | pll_base_inst
113 | // Output clocks
114 | (.CLKFBOUT (clkfbout),
115 | .CLKOUT0 (clkout0),
116 | .CLKOUT1 (clkout1_unused),
117 | .CLKOUT2 (clkout2_unused),
118 | .CLKOUT3 (clkout3_unused),
119 | .CLKOUT4 (clkout4_unused),
120 | .CLKOUT5 (clkout5_unused),
121 | // Status and control signals
122 | .LOCKED (locked_unused),
123 | .RST (rst),
124 | // Input clock control
125 | .CLKFBIN (clkfbout_buf),
126 | .CLKIN (clkin1));
127 |
128 |
129 | // Output buffering
130 | //-----------------------------------
131 | BUFG clkf_buf
132 | (.O (clkfbout_buf),
133 | .I (clkfbout));
134 |
135 | BUFG clkout1_buf
136 | (.O (clk_out_9_6M),
137 | .I (clkout0));
138 |
139 |
140 |
141 |
142 | endmodule
143 |
--------------------------------------------------------------------------------
/src/clk_divide.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 14:35:06 10/23/2015
7 | // Design Name:
8 | // Module Name: clk_divide
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module clk_divide(
22 | input clk,
23 | input rst,
24 | output clk_uart,
25 | output clk_sampling
26 | );
27 |
28 | parameter CLK_RATE = 9600000;
29 | parameter BAUD_RATE = 19200; // it was 19200 before
30 | parameter SAMPLE_RATE = 10;
31 |
32 |
33 | wire [15:0] counter_uart_max;
34 | wire [15:0] counter_sampling_max;
35 |
36 | reg [16:0] counter_uart;
37 | reg clk_uart_internal;
38 | reg [16:0] counter_sampling;
39 | reg clk_sampling_internal;
40 |
41 | assign counter_uart_max = CLK_RATE/BAUD_RATE/2-1;
42 | assign counter_sampling_max = CLK_RATE/BAUD_RATE/SAMPLE_RATE/2-1;
43 |
44 | assign clk_uart = clk_uart_internal;
45 | assign clk_sampling = clk_sampling_internal;
46 |
47 |
48 | always@(posedge clk)
49 | begin
50 | if (rst == 1)
51 | begin
52 | counter_uart <= 0;
53 | clk_uart_internal <= 0;
54 | end
55 | else
56 | begin
57 | if (counter_uart == counter_uart_max) // Comment this line if you want to use the testbench
58 | //if (counter_uart == 15)
59 | begin
60 | counter_uart <= 0;
61 | clk_uart_internal <= ~clk_uart_internal;
62 | end
63 | else
64 | counter_uart <= counter_uart+1'b1;
65 | end
66 | end
67 |
68 |
69 | always@(posedge clk)
70 | begin
71 | if (rst == 1)
72 | begin
73 | counter_sampling <= 0;
74 | clk_sampling_internal <= 0;
75 | end
76 | else
77 | begin
78 | if (counter_sampling == counter_sampling_max) // Comment this line if you want to use the testbench
79 | //if (counter_sampling == 1)
80 | begin
81 | counter_sampling <= 0;
82 | clk_sampling_internal <= ~clk_sampling_internal;
83 | end
84 | else
85 | counter_sampling <= counter_sampling+1'b1;
86 | end
87 | end
88 |
89 |
90 |
91 | endmodule
92 |
--------------------------------------------------------------------------------
/src/clk_divide_tb.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 16:47:58 10/30/2015
8 | // Design Name: clk_divide
9 | // Module Name: X:/Desktop/UART/UART/clk_divide_tb.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: clk_divide
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module clk_divide_tb;
26 |
27 | // Inputs
28 | reg clk;
29 | reg rst;
30 |
31 | // Outputs
32 | wire clk_uart;
33 | wire clk_sampling;
34 |
35 | // Instantiate the Unit Under Test (UUT)
36 | clk_divide uut (
37 | .clk(clk),
38 | .rst(rst),
39 | .clk_uart(clk_uart),
40 | .clk_sampling(clk_sampling)
41 | );
42 |
43 | always #1 assign clk = ~clk;
44 |
45 | initial begin
46 | // Initialize Inputs
47 | clk = 0;
48 | rst = 1;
49 |
50 | // Wait 100 ns for global reset to finish
51 | #100;
52 | rst = 0;
53 |
54 | // Add stimulus here
55 |
56 | end
57 |
58 | endmodule
59 |
60 |
--------------------------------------------------------------------------------
/src/integrated.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 19:55:39 11/16/2015
7 | // Design Name:
8 | // Module Name: integrated
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module integrated(clk, rst, start, finish);
22 | input clk, rst, start;
23 | output finish;
24 | wire [13:0]ws1, rs1, rs;
25 | reg we;
26 | wire we1;
27 | reg [13:0] ws;
28 | reg [7:0] wd;
29 | wire [7:0] rd, wd1, rd1;
30 | reg[13:0] i;
31 |
32 | MEM M1(clk, we, ws, rs, wd, rd); //read connected to systol
33 | MEM M2(clk, we1, ws1, rs1, wd1, rd1); //write connected to systol
34 | //module scan_new(read_select, start, clk, rst, rd, wd, ws, we, finish);
35 | scan_new s1(rs, start, clk, rst, rd, wd1, ws1, we1, finish);
36 |
37 | always@(posedge clk)
38 | begin
39 | if(rst)
40 | i<=0;
41 | else if(i<2500)
42 | begin
43 | i<=i+1;
44 | ws<=i;
45 | wd<=i;
46 | we<=1;
47 | end
48 | if(i==2500)
49 | we<=0;
50 | end
51 |
52 | endmodule
53 |
--------------------------------------------------------------------------------
/src/integrated_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 20:09:07 11/16/2015
8 | // Design Name: integrated
9 | // Module Name: X:/Desktop/lab5_working/UART/integrated_test.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: integrated
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module integrated_test;
26 |
27 | // Inputs
28 | reg clk;
29 | reg rst;
30 | reg start;
31 | wire finish;
32 | // Instantiate the Unit Under Test (UUT)
33 | integrated uut (
34 | .clk(clk),
35 | .rst(rst),
36 | .finish(finish),
37 | .start(start)
38 | );
39 | always #1 clk=~clk;
40 | initial begin
41 | // Initialize Inputs
42 | clk = 0;
43 | start=0;
44 | rst = 1;
45 | #5
46 | rst=0;
47 | #6000
48 | start=1;
49 |
50 |
51 |
52 | // Wait 100 ns for global reset to finish
53 | #100;
54 |
55 | // Add stimulus here
56 |
57 | end
58 |
59 | endmodule
60 |
61 |
--------------------------------------------------------------------------------
/src/receiver_sampler.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | // Error checking by sampling multiple times of one bit data
4 | module receiver_sampler(
5 | input rst,
6 | input sample_clk,
7 | input rx_clk,
8 | input RsRx,
9 | output reg data_bit = 1'b1
10 | );
11 |
12 | reg [3:0] zero_counter;
13 | reg [3:0] one_counter;
14 | reg prev_rx_clk;
15 |
16 | wire rx_clk_rising;
17 |
18 | assign rx_clk_rising = (prev_rx_clk == 0 && rx_clk == 1);
19 |
20 | always@(posedge sample_clk)
21 | begin
22 | prev_rx_clk <= rx_clk;
23 |
24 | if (rst || rx_clk_rising)
25 | begin
26 | zero_counter <= 4'd0;
27 | one_counter <= 4'd0;
28 | end
29 | else if (RsRx == 1'b1)
30 | one_counter <= one_counter + 1'b1;
31 | else
32 | zero_counter <= zero_counter + 1'b1;
33 | end
34 |
35 | always@(posedge rx_clk)
36 | begin
37 | if(rst)
38 | data_bit <= 1'b1;
39 | else if(zero_counter >= one_counter)
40 | data_bit <= 1'b0;
41 | else
42 | data_bit <= 1'b1;
43 | end
44 |
45 | endmodule
46 |
--------------------------------------------------------------------------------
/src/receiver_sampler_tb.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 17:09:58 10/30/2015
8 | // Design Name: receiver_sampler
9 | // Module Name: X:/Desktop/UART/UART/receiver_sampler_tb.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: receiver_sampler
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module receiver_sampler_tb;
26 |
27 | // Inputs
28 | reg rst;
29 | reg sample_clk;
30 | reg rx_clk;
31 | reg RsRx;
32 |
33 | // Outputs
34 | wire data_bit;
35 |
36 | // Instantiate the Unit Under Test (UUT)
37 | receiver_sampler uut (
38 | .rst(rst),
39 | .sample_clk(sample_clk),
40 | .rx_clk(rx_clk),
41 | .RsRx(RsRx),
42 | .data_bit(data_bit)
43 | );
44 |
45 | always #1 sample_clk = ~sample_clk;
46 | always #8 rx_clk = ~rx_clk;
47 |
48 | initial begin
49 | // Initialize Inputs
50 | rst = 1;
51 | sample_clk = 0;
52 | rx_clk = 0;
53 | RsRx = 0;
54 |
55 | // Wait 100 ns for global reset to finish
56 | #104;
57 | rst = 0;
58 |
59 | #16 RsRx = 1;
60 | #16 RsRx = 0;
61 | #16 RsRx = 1;
62 | #16 RsRx = 0;
63 | #16 RsRx = 1;
64 | #16 RsRx = 0;
65 | #16 RsRx = 1;
66 | #16 RsRx = 0;
67 | #16 RsRx = 1;
68 | #16 RsRx = 0;
69 | #16 RsRx = 1;
70 | #16 RsRx = 0;
71 |
72 |
73 | // Add stimulus here
74 |
75 | end
76 |
77 | endmodule
78 |
79 |
--------------------------------------------------------------------------------
/src/reciever.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 |
4 | module receiver(
5 | input data_in, // 1 bit data received from Rx bus
6 | input rx_clk, // clk
7 | input reset,
8 | output signal, // when signal == 1, signifies that one byte of data is received
9 | output [7:0] data_out // output of the received data
10 | );
11 |
12 | reg [7:0] data; // Store the received data
13 | reg [7:0] shift; // Shift register to receive the 8 bit data
14 | reg [3:0] state;
15 | reg sig; // sig set when received a data
16 |
17 | assign data_out = data;
18 | assign signal = sig;
19 |
20 |
21 | always @(posedge rx_clk , posedge reset)
22 | begin
23 | if (reset) // clear registers
24 | begin
25 | data <= 0;
26 | state <= 0;
27 | shift <= 0;
28 | sig = 0;
29 | end
30 | else if (state == 0 && data_in == 1)
31 | state <= 0; // stay in state 0 if line is idle (high)
32 | else if (state == 0 && data_in == 0)
33 | state <= 1; // go to state 1 when line goes low
34 | else if (state == 9)
35 | begin // assign data to output port and raise flag when 8 bits have been read
36 | state <= 10;
37 | data <= shift;
38 | sig = 1;
39 | end
40 | else if (state == 10)
41 | begin // one clock cycle delay, clear flag bit.
42 | state <= 11;
43 | sig = 0;
44 | end
45 | else if (state == 11)
46 | begin
47 | state <= 0; // return to state 0.
48 | sig = 0;
49 | end
50 | else
51 | begin
52 | state <= state+1'b1; // increment state and shift in one bit of data
53 | shift[0] <= shift [1];
54 | shift[1] <= shift [2];
55 | shift[2] <= shift [3];
56 | shift[3] <= shift [4];
57 | shift[4] <= shift [5];
58 | shift[5] <= shift [6];
59 | shift[6] <= shift [7];
60 | shift[7] <= data_in;
61 | end
62 | end
63 |
64 |
65 |
66 | endmodule
67 |
--------------------------------------------------------------------------------
/src/scan.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company: Boston University
4 | // Engineer:
5 | //
6 | // Create Date: 23:48:42 11/10/2015
7 | // Design Name:
8 | // Module Name: Scan
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module scan(read_select, read_data, clk, start, rst, ws, we, wd, sys_finish);
22 |
23 | input [7:0] read_data;
24 | input clk, start, rst;
25 | output reg [13:0] read_select, ws;
26 | output [7:0] wd;
27 | output reg sys_finish, we;
28 | reg scan_start=0,stop=0;
29 | integer i=1,k=0,l=50,m=100,flag=1, x1=0, j=0, z=0;
30 | wire [7:0] w [8:0];
31 | reg [15:0] y2;
32 | wire [15:0]yyy;
33 | reg [15:0] y1 = 0;
34 |
35 | assign w[0] = 8'h01;
36 | assign w[1] = 8'h02;
37 | assign w[2] = 8'h01;
38 | assign w[3] = 8'h02;
39 | assign w[4] = 8'h04;
40 | assign w[5] = 8'h02;
41 | assign w[6] = 8'h01;
42 | assign w[7] = 8'h02;
43 | assign w[8] = 8'h01;
44 |
45 | always@(posedge clk)
46 | begin
47 | if(rst)
48 | scan_start<=0;
49 | else if(start ==1)
50 | begin
51 | if(flag == 1)
52 | begin
53 | /*x1=x1+1;
54 | if(x1%1600==0)
55 | begin*/
56 | if(i<4)
57 | begin
58 | read_select <= k;
59 | k<=k+1;
60 | i<=i+1;
61 | end
62 | if(i>3 && i<7)
63 | begin
64 | read_select <= l;
65 | l <= l+1;
66 | i<=i+1;
67 | end
68 | if(i>6 && i<10)
69 | begin
70 | read_select <= m;
71 | m <= m+1;
72 | i<=i+1;
73 | end
74 | if(i == 9)
75 | i <= 1;
76 | if(m == 2499)
77 | flag = 0;
78 | if(k>0)
79 | scan_start<=1;
80 | end
81 | //end
82 | end
83 | end
84 |
85 | always@(posedge clk)
86 | begin
87 | if(rst)
88 | begin
89 | sys_finish<=0;
90 | stop<=0;
91 | end
92 | else
93 | if(scan_start ==1 && stop ==0 )
94 | begin
95 | if(z==9)
96 | begin
97 | z <= 0;
98 | ws<=j;
99 | we<=1;
100 | j<=j+1;
101 | y1<=0;
102 | end
103 | else
104 | begin
105 | we<=0;
106 | z <= z+1;
107 | y1 <= y1 + w[z]*read_data;
108 | end
109 | y2<=y1;
110 | if(j == 2500)
111 | begin
112 | sys_finish <= 1;
113 | stop <=1;
114 | end
115 | else
116 | sys_finish <=0;
117 | end
118 | end
119 |
120 | assign yyy = y2>>4;
121 | assign wd= read_select;
122 |
123 | endmodule
--------------------------------------------------------------------------------
/src/scan_new.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 19:38:18 11/17/2015
7 | // Design Name:
8 | // Module Name: scan_new
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module scan_new(read_select, start, clk, rst, rd, wd, ws, we, finish);
22 |
23 | input clk,rst,start;
24 | input [7:0] rd;
25 | output wire finish;
26 | output reg [13:0] read_select, ws;
27 | output reg we;
28 | output reg [7:0] wd;
29 | reg [15:0] i,k,l,m;
30 | reg flag, flag1;
31 | wire [7:0] result;
32 | reg [7:0] result_temp;
33 | reg sys_start, scan_start;
34 | reg [13:0]ws1;
35 | reg we1;
36 | always@(posedge clk)
37 | begin
38 | if(rst)
39 | begin
40 | scan_start<=0;
41 | i<=0;
42 | k<=0;
43 | l<=50;
44 | m<=100;
45 | flag<=1;
46 | end
47 | else if(start ==1)
48 | begin
49 | if(flag == 1)
50 | begin
51 | /*x1=x1+1;
52 | if(x1%1600==0)
53 | begin*/
54 | if(i%3==0)
55 | begin
56 | read_select <= k;
57 | k<=k+1;
58 | i<=i+1;
59 | end
60 | else if(i%3==1)
61 | begin
62 | read_select <= l;
63 | l <= l+1;
64 | i<=i+1;
65 | end
66 | else if(i%3==2)
67 | begin
68 | read_select <= m;
69 | m <= m+1;
70 | i<=i+1;
71 | end
72 | if(i == 8)
73 | begin
74 | i <= 0;
75 | k<=k-2;
76 | l<=l-2;
77 | m<=m-1;
78 | end
79 | if(m == 2500)
80 | flag <= 0;
81 | if(k>0)
82 | scan_start<=1;
83 | end
84 | //end
85 | end
86 | end
87 |
88 | always@(posedge clk)
89 | begin
90 | if(rst)
91 | begin
92 | we<=we1;
93 | ws<=ws1;
94 | wd<=0;
95 | flag1<=1;
96 | end
97 | else if(ready==0 && flag1==1)
98 | begin
99 | we<=we1;
100 | wd <= result;
101 | end
102 | if(ready==1 && flag1==1)
103 | begin
104 | we<=we1;
105 | ws<=ws1;
106 | end
107 | if(ws == 2499)
108 | flag1<=0;
109 | end
110 |
111 | always@(posedge clk)
112 | begin
113 | if(rst)
114 | begin
115 | we1<=0;
116 | ws1<=0;
117 | end
118 | else if(ready==0 && flag1==1)
119 | begin
120 | we1<=0;
121 | end
122 | if(ready==1 && flag1==1)
123 | begin
124 | we1<=1;
125 | ws1<=ws1+1;
126 | end
127 |
128 | end
129 |
130 |
131 | /*always@(posedge clk)
132 | begin
133 | if(ready)
134 | result_temp = result;
135 | end*/
136 | assign finish = (ws==2499)?1'd1:1'd0;
137 | //module semi_systolic(clk, rst, d, r, ready, start);
138 | semi_systolic ssc1 (clk, rst, rd, result, ready, scan_start);
139 | endmodule
140 |
--------------------------------------------------------------------------------
/src/scan_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 00:41:59 11/11/2015
8 | // Design Name: scan
9 | // Module Name: X:/Desktop/Lab 5 UART_code/UART/UART/scan_test.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: scan
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module scan_test;
26 |
27 | // Inputs
28 | reg [7:0] read_data;
29 | reg clk,rst,start;
30 |
31 | // Outputs
32 | wire [13:0] read_select;
33 | wire [7:0] data_out;
34 | wire scan_start;
35 |
36 |
37 | // Instantiate the Unit Under Test (UUT)
38 | scan uut (
39 | .read_select(read_select),
40 | .read_data(read_data),
41 | .data_out(data_out),
42 | .clk(clk),
43 | .rst(rst),
44 | .start(start),
45 | .scan_start(scan_start)
46 | );
47 | always #5 clk=~clk;
48 | initial begin
49 | // Initialize Inputs
50 | read_data = 0;
51 | clk = 0;
52 | rst=0;
53 | start=1;
54 |
55 | // Wait 100 ns for global reset to finish
56 | #100;
57 |
58 | // Add stimulus here
59 |
60 | end
61 |
62 | endmodule
63 |
64 |
--------------------------------------------------------------------------------
/src/semi_systolic.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 00:13:19 11/17/2015
7 | // Design Name:
8 | // Module Name: semi_systolic
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module semi_systolic(clk, rst, d, r, ready, start);
22 | input clk, rst, start;
23 | input [7:0] d;
24 | output wire [7:0] r;
25 | output wire ready;
26 | reg [7:0] d1, d2, d3, d4, d5, d6, d7, d8, d9;
27 | wire [15:0] r1, r2, r3, r4, r5, r6, r7, r8, r9;
28 | wire [15:0] r_temp1;
29 | wire [15:0] r_temp2;
30 | reg [3:0] cnt;
31 | reg [15:0] i;
32 | reg b1, b2, b3, b4, b5, b6, b7, b8, b9;
33 | reg m1, m2, m3, m4, m5, m6, m7, m8, m9;
34 | //module systolic(r, w, clk, d, rst);
35 | systolic S1(r1, 16'd1, clk, d1, rst, b1, m1);
36 | systolic S2(r2, 16'd2, clk, d2, rst, b1, m1);
37 | systolic S3(r3, 16'd1, clk, d3, rst, b1, m1);
38 | systolic S4(r4, 16'd2, clk, r1, rst, b2, m2);
39 | systolic S5(r5, 16'd4, clk, r2, rst, b2, m2);
40 | systolic S6(r6, 16'd2, clk, r3, rst, b2, m2);
41 | systolic S7(r7, 16'd1, clk, r4, rst, b3, m3);
42 | systolic S8(r8, 16'd2, clk, r5, rst, b3, m3);
43 | systolic S9(r9, 16'd1, clk, r6, rst, b3, m3);
44 |
45 | always@(posedge clk)
46 | begin
47 | if(rst)
48 | begin
49 | cnt<=0;
50 | i<=0;
51 | end
52 | else
53 | if(start==1)
54 | begin
55 | i<=i+1;
56 | cnt<= cnt+1;
57 | if(cnt==8)
58 | cnt<=0;
59 | end
60 | end
61 |
62 | always@(posedge clk)
63 | begin
64 | if(!rst)
65 | begin
66 | if(cnt==0)
67 | begin
68 | d1<=d;
69 | b3<=0;
70 | m3<=1;
71 | b2<=0;
72 | m2<=1;
73 | b1<=0;
74 | m1<=1;
75 | end
76 |
77 | else
78 | if(cnt==1)
79 | d2<=d;
80 | else
81 | if(cnt==2)
82 | begin
83 | d3<=d;
84 | b3<=0;
85 | m3<=0;
86 | b2<=0;
87 | m2<=0;
88 | b1<=0;
89 | m1<=0;
90 | end
91 | else
92 | if(cnt>2 && cnt<6)
93 | begin
94 | b1<=1;
95 | m1<=0;
96 | end
97 | else
98 | if(cnt>5 && cnt<9)
99 | begin
100 | b2<=1;
101 | m2<=0;
102 | b1<=1;
103 | m1<=0;
104 | end
105 | end
106 | end
107 | /*always@(posedge clk)
108 | begin
109 | if(rst)
110 | begin
111 | r_temp1<=0;
112 | i<=0;
113 | end
114 | else
115 | begin
116 | if(i<9)
117 | if(cnt==0)
118 | d1<=d;
119 | else
120 | if(cnt ==1)
121 | d2<=d;
122 | else
123 | if(cnt ==2)
124 | d3<=d;
125 | else
126 | if(cnt ==3)
127 | d4<=d;
128 | else
129 | if(cnt ==4)
130 | d5<=d;
131 | else
132 | if(cnt ==5)
133 | d6<=d;
134 | else
135 | if(cnt ==6)
136 | d7<=d;
137 | else
138 | if(cnt ==7)
139 | d8<=d;
140 | else
141 | if(cnt ==8)
142 | d9<=d;
143 | else
144 | if(cnt == 9)
145 | cnt <= 0;
146 | cnt = cnt + 1;
147 | i <= i+1;
148 | end
149 | end */
150 | assign r_temp1=rst?7'd0:(cnt==1)? 7'd0 : (r1+r2+r3+r4+r5+r6+r7+r8+r9);
151 | assign r = r_temp1>>4;
152 | assign ready=rst?1'd0:(cnt==2 && i>8)?1:0;
153 | //assign r_temp2 = r_temp1>>4;
154 | //assign r=r_temp2[7:0];
155 |
156 | endmodule
157 |
--------------------------------------------------------------------------------
/src/semi_systolic_final.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 20:41:49 11/17/2015
7 | // Design Name:
8 | // Module Name: semi_systolic_final
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module semi_systolic_final(read_select,scan_start, start, clk,rst);
22 |
23 | input clk,rst,start;
24 | output reg [13:0] read_select;
25 | output reg scan_start;
26 | reg [15:0] i,k,l,m;
27 | reg flag;
28 | always@(posedge clk)
29 | begin
30 | if(rst)
31 | begin
32 | scan_start<=0;
33 | i<=0;
34 | k<=0;
35 | l<=50;
36 | m<=100;
37 | flag<=1;
38 | end
39 | else if(start ==1)
40 | begin
41 | if(flag == 1)
42 | begin
43 | /*x1=x1+1;
44 | if(x1%1600==0)
45 | begin*/
46 | if(i%3==0)
47 | begin
48 | read_select <= k;
49 | k<=k+1;
50 | i<=i+1;
51 | end
52 | else if(i%3==1)
53 | begin
54 | read_select <= l;
55 | l <= l+1;
56 | i<=i+1;
57 | end
58 | else if(i%3==2)
59 | begin
60 | read_select <= m;
61 | m <= m+1;
62 | i<=i+1;
63 | end
64 | if(i == 8)
65 | begin
66 | i <= 0;
67 | k<=k-2;
68 | l<=l-2;
69 | m<=m-1;
70 | end
71 | if(m == 2500)
72 | flag = 0;
73 | if(k>0)
74 | scan_start<=1;
75 | end
76 | //end
77 | end
78 | end
79 | endmodule
80 |
--------------------------------------------------------------------------------
/src/systol_new1.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | module systol_new1(read_select, result, finish, start, read_data, clk, rst, we, ws);
4 |
5 | input start,clk,rst;
6 | input [7:0] read_data; //
7 | output reg [13:0]read_select;
8 | output wire [13:0] ws;
9 | output [7:0]result;
10 |
11 | output reg finish;
12 | output wire we;
13 | //parameter read_data = 150; //
14 |
15 | wire [13:0] result_temp;
16 | reg [13:0] result_1;
17 | reg [7:0] d1,d2,d3;
18 | reg [15:0] i ;
19 | reg [13:0] j ;
20 | reg [13:0] k ;
21 | reg [13:0] l ;
22 | reg [13:0] cnt;
23 | wire cnt1;
24 | reg [13:0] address;
25 | reg [7:0] w1,w2,w3,w4,w5,w6,w7,w8,w9;//w1=1,w2=2,w3=1,w4=2,w5=4,w6=2,w7=1,w8=2,w9=1;
26 | reg flag1,flag2;
27 | wire flag;
28 | reg [13:0] sr;
29 | reg [7:0] result_copy;
30 | reg [13:0] ws1, ws2;
31 | reg we1, we2;
32 | assign flag=flag1|flag2;
33 | always@(posedge clk)
34 | begin
35 | if(rst)
36 | begin
37 | d1<=0;
38 | d2<=0;
39 | d3<=0;
40 | i<= 0;
41 | j<= 50;
42 | k<=100;
43 | l<=0;
44 | cnt<=0;
45 | address<=0;
46 | w1<=1;
47 | w2<=2;
48 | w3<=1;
49 | w4<=2;
50 | w5<=4;
51 | w6<=2;
52 | w7<=1;
53 | w8<=2;
54 | w9<=1;
55 | flag1<=0;
56 | flag2<=0;
57 | sr<=0;
58 | ws1<=0;
59 | we1<=0;
60 | end
61 | else if(!rst)
62 | begin
63 | if(start==1 && k<2500)
64 | begin
65 | if (i%3 == 0)
66 | begin
67 | //address <= address + 1;
68 | read_select <= l;
69 | i <= i+1;
70 | l<=l+1;
71 | cnt <= cnt+1;
72 | d2 <= read_data;
73 | //we <= 0;
74 | end
75 | else if (i%3 == 1 && i!=0)
76 | begin
77 | read_select <= j;
78 | i <= i+1;
79 | j <= j+1;
80 | cnt <= cnt+1;
81 | d3 <= read_data;
82 | //we <= 0;
83 | end
84 | else if (i%3 == 2 && i!=0)
85 | begin
86 | read_select <= k;
87 | i <= i+1;
88 | k <= k+1;
89 | cnt <= cnt+1;
90 | d1 <= read_data;
91 | //we <= 0;
92 | end
93 | if(cnt == 8)
94 | begin
95 | cnt <= 0;
96 | l<=l-2'd2;
97 | j<=j-2'd2;
98 | k<=k-2'd1;
99 | end
100 | end
101 | else
102 | if(k==2500)
103 | flag1<=1;
104 | if(flag1==1 && sr<50)
105 | begin
106 | read_select<=sr;
107 | result_copy<=read_data;
108 | ws1<=sr-2;
109 | we1<=1;
110 | sr<=sr+1;
111 | end
112 | if(sr==50)
113 | begin
114 | flag2<=1;
115 | flag1<=0;
116 | we1<=0;
117 | sr<=14'd2449;
118 | end
119 | if(flag2==1 && sr<2500)
120 | begin
121 | read_select<=sr;
122 | result_copy<=read_data;
123 | ws1<=sr;
124 | we1<=1;
125 | sr<=sr+1;
126 | end
127 | if(sr == 2500)
128 | begin
129 | we1<=0;
130 | flag2<=0;
131 | end
132 | end
133 | end
134 |
135 | always@(*)
136 | begin
137 | if(rst)
138 | finish <= 0;
139 | else
140 | /*if(i>8)
141 | ws <= (i/9)-1;
142 | else
143 | ws <= 0;*/
144 | if(k==2500)
145 | finish <= 1;
146 | else
147 | finish <= 0;
148 | end
149 |
150 | /*always@(posedge clk)
151 | begin
152 | if(start==1)
153 | begin
154 | if(cnt == 0 && i!=0)
155 | begin
156 | result_1 <= 0;
157 | ws<=ws+1;
158 | we<=0;
159 | end
160 | else if(i==0)
161 | begin
162 | result_1 <= 0;
163 | ws<=0;
164 | we<=0;
165 | end
166 | if(cnt>0)
167 | begin
168 | if(cnt==3)
169 | begin
170 | result_1 <= result_1 + w1*d1+w2*d2+w3*d3;
171 | end
172 | else
173 | if(cnt==6)
174 | begin
175 | result_1 <= result_1 + w4*d1+w5*d2+w6*d3;
176 | end
177 | else
178 | if(cnt ==9)
179 | begin
180 | result_1 <= result_1 + w7*d1+w8*d2+w9*d3;
181 | we <= 1;
182 | end
183 | end
184 | end
185 | end
186 | */
187 |
188 | always@(negedge clk)
189 | begin
190 | if(rst)
191 | begin
192 | ws2<=50;
193 | we2<=0;
194 | result_1 <= 8'h00;
195 | end
196 |
197 | else if(start == 1)
198 | begin
199 | if(cnt==3)
200 | begin
201 | result_1<=result_1+w1*d1+w2*d2+w3*d3;
202 | end
203 | else if(cnt == 6)
204 | begin
205 | result_1<=result_1+w4*d1+w5*d2+w6*d3;
206 | end
207 | else if(cnt == 0 && i>0)
208 | begin
209 | result_1<=result_1+w7*d1+w8*d2+w9*d3;
210 | end
211 | else if(cnt == 1 && i>8)
212 | begin
213 | we2<=1;
214 | ws2<=ws2+1;
215 | end
216 | else if(cnt == 2)
217 | begin
218 | result_1 <= 0;
219 | we2<=0;
220 | end
221 | end
222 |
223 |
224 | end
225 | assign we= flag?we1:we2;
226 | assign ws= flag?ws1:ws2;
227 | assign result_temp = result_1>>4;
228 | assign result = flag?result_copy:result_temp[7:0]; //assign ws = address[13:0];
229 | //assign result = d1;
230 | //assign result = 8'd127;
231 | endmodule
232 |
233 |
234 |
--------------------------------------------------------------------------------
/src/systolic.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 00:10:37 11/17/2015
7 | // Design Name:
8 | // Module Name: systolic
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module systolic(r, w, clk, d, rst, bcast, m);
22 | input [15:0] w;
23 | input [7:0] d;
24 | input clk, rst, bcast, m;
25 | output reg [15:0] r;
26 | always@(posedge clk)
27 | begin
28 | if(rst)
29 | r <= 0;
30 | else
31 | if(bcast == 1 && m==0)
32 | r <= d;
33 | else
34 | if(bcast == 0 && m==1)
35 | r <= w*d;
36 | end
37 | endmodule
38 |
--------------------------------------------------------------------------------
/src/systolic_original.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 19:24:17 11/17/2015
7 | // Design Name:
8 | // Module Name: systolic_original
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module systolic_original();
22 |
23 |
24 | endmodule
25 |
--------------------------------------------------------------------------------
/src/systolic_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 18:34:12 11/11/2015
8 | // Design Name: systolic
9 | // Module Name: X:/Desktop/Lab 5 UART_code/UART/UART/systolic_test.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: systolic
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module systolic_test;
26 |
27 | // Inputs
28 | reg [7:0] in_data;
29 | reg clk;
30 | reg start;
31 |
32 | // Outputs
33 | wire [7:0] sum_out;
34 | wire [13:0] ws;
35 | wire we;
36 | wire sys_finish;
37 | // Instantiate the Unit Under Test (UUT)
38 | systolic uut (
39 | .sum_out(sum_out),
40 | .in_data(in_data),
41 | .clk(clk),
42 | .start(start),
43 | .ws(ws),
44 | .we(we),
45 | .sys_finish(sys_finish)
46 | );
47 | always #5 clk=~clk;
48 | initial begin
49 | // Initialize Inputs
50 | in_data = 0;
51 | clk = 0;
52 | start = 0;
53 | #20
54 | start =1;
55 | in_data=1;
56 |
57 | // Wait 100 ns for global reset to finish
58 | #100;
59 |
60 | // Add stimulus here
61 |
62 | end
63 |
64 | endmodule
65 |
66 |
--------------------------------------------------------------------------------
/src/test_scan_new.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 19:42:11 11/17/2015
8 | // Design Name: scan_new
9 | // Module Name: X:/Desktop/lab5_working/UART/test_scan_new.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: scan_new
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module test_scan_new;
26 |
27 | // Inputs
28 | reg start;
29 | reg clk;
30 | reg rst;
31 |
32 | // Outputs
33 | wire [13:0] read_select;
34 | wire scan_start;
35 |
36 | // Instantiate the Unit Under Test (UUT)
37 | scan_new uut (
38 | .read_select(read_select),
39 | .scan_start(scan_start),
40 | .start(start),
41 | .clk(clk),
42 | .rst(rst)
43 | );
44 |
45 | always #1 clk = ~clk;
46 | initial begin
47 | // Initialize Inputs
48 | start = 0;
49 | clk = 0;
50 | rst = 1;
51 | // Wait 100 ns for global reset to finish
52 | #100
53 | start = 1;
54 | rst = 0;
55 |
56 |
57 | #100000000 $finish;
58 |
59 | // Add stimulus here
60 |
61 | end
62 |
63 | endmodule
64 |
65 |
--------------------------------------------------------------------------------
/src/test_systol_new.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 04:25:23 11/13/2015
8 | // Design Name: systol_new1
9 | // Module Name: X:/My Documents/xilinx/UART/test_systol_new.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: systol_new1
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module test_systol_new;
26 |
27 | // Inputs
28 | reg start;
29 | reg [7:0] read_data;
30 | reg clk;
31 | reg rst;
32 |
33 | // Outputs
34 | wire [13:0] read_select,ws;
35 | wire [7:0] result;
36 | wire finish;
37 | wire we;
38 |
39 | // Instantiate the Unit Under Test (UUT)
40 | systol_new1 uut (
41 | .read_select(read_select),
42 | .result(result),
43 | .finish(finish),
44 | .start(start),
45 | .read_data(read_data),
46 | .clk(clk),
47 | .rst(rst),
48 | .we(we),
49 | .ws(ws)
50 | );
51 | always #5 clk=~clk;
52 | initial begin
53 | // Initialize Inputs
54 | start = 0;
55 | read_data = 1;
56 | clk = 0;
57 | rst = 1;
58 | #5 rst =0;
59 | #20
60 | start = 1;
61 |
62 | // Wait 100 ns for global reset to finish
63 | #100;
64 |
65 | // Add stimulus here
66 |
67 | end
68 |
69 | endmodule
70 |
71 |
--------------------------------------------------------------------------------
/src/test_systolic.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 01:43:26 11/11/2015
8 | // Design Name: systolic
9 | // Module Name: X:/Desktop/Lab 5 UART_code/UART/UART/test_systolic.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: systolic
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module test_systolic;
26 |
27 | // Inputs
28 | reg [7:0] in_data;
29 | reg clk;
30 |
31 | // Outputs
32 | wire [15:0] sum_out;
33 |
34 | // Instantiate the Unit Under Test (UUT)
35 | systolic uut (
36 | .in_data(in_data),
37 | .sum_out(sum_out),
38 | .clk(clk)
39 | );
40 | always #5 clk = ~clk;
41 | initial begin
42 | // Initialize Inputs
43 | in_data = 0;
44 | clk = 0;
45 | in_data <= 8'hff;
46 | #10 in_data <= 8'hff;
47 | #10 in_data <= 8'hff;
48 | #10 in_data <= 8'hff;
49 | #10 in_data <= 8'hff;
50 | #10 in_data <= 8'hff;
51 | #10 in_data <= 8'hff;
52 | #10 in_data <= 8'hff;
53 | #10 in_data <= 8'hff;
54 | // Wait 100 ns for global reset to finish
55 | #100;
56 |
57 | // Add stimulus here
58 |
59 | end
60 |
61 | endmodule
62 |
63 |
--------------------------------------------------------------------------------
/src/top.ucf:
--------------------------------------------------------------------------------
1 |
2 |
3 | NET "Rx_data[7]" IOSTANDARD = LVCMOS33;
4 |
5 |
6 | NET "Rx_data[6]" LOC = R11;
7 |
8 |
9 | NET "Rx_data[6]" IOSTANDARD = LVCMOS33;
10 |
11 |
12 | NET "Rx_data[5]" LOC = N11;
13 |
14 |
15 | NET "Rx_data[5]" IOSTANDARD = LVCMOS33;
16 |
17 |
18 | NET "Rx_data[4]" LOC = M11;
19 |
20 |
21 | NET "Rx_data[4]" IOSTANDARD = LVCMOS33;
22 |
23 |
24 | NET "Rx_data[3]" LOC = V15;
25 |
26 |
27 | NET "Rx_data[3]" IOSTANDARD = LVCMOS33;
28 |
29 |
30 | NET "Rx_data[2]" LOC = U15;
31 |
32 |
33 | NET "Rx_data[2]" IOSTANDARD = LVCMOS33;
34 |
35 |
36 | NET "Rx_data[1]" LOC = V16;
37 |
38 |
39 | NET "Rx_data[1]" IOSTANDARD = LVCMOS33;
40 |
41 |
42 | NET "Rx_data[0]" LOC = U16;
43 |
44 |
45 | NET "Rx_data[0]" IOSTANDARD = LVCMOS33;
46 |
47 |
48 | NET "clk" LOC = V10;
49 |
50 |
51 | NET "clk" IOSTANDARD = LVCMOS33;
52 |
53 |
54 | NET "rst" LOC = T10;
55 |
56 |
57 | NET "rst" IOSTANDARD = LVCMOS33;
58 |
59 |
60 | NET "RsRx" LOC = N17;
61 |
62 |
63 | NET "RsRx" IOSTANDARD = LVCMOS33;
64 |
65 |
66 |
67 |
68 | NET "RsTx" LOC = N18;
69 |
70 | //PIN "PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
71 |
72 | //PIN "rst_IBUF_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
73 |
74 | //NET "rst" CLOCK_DEDICATED_ROUTE = FALSE;
75 |
76 | # PlanAhead Generated physical constraints
77 |
78 | NET "sys_finish" LOC = T11;
79 |
80 | # PlanAhead Generated IO constraints
81 |
82 | NET "sys_finish" IOSTANDARD = LVCMOS33;
83 |
--------------------------------------------------------------------------------
/src/top.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 |
4 | module top(
5 | input clk,
6 | input rst,
7 | input RsRx, // Connect to RX pin
8 | output [7:0] Rx_data, // Received data
9 | output RsTx, // Connect to TX pin
10 | //output scan_start
11 | output wire sys_finish
12 | );
13 |
14 | parameter NUM_DATA = 2500; // Total number of data points
15 | parameter CLK_RATE = 9600000; // Input CLK freq
16 | parameter BAUD_RATE = 9600; // UART Baud rate
17 | parameter SAMPLE_RATE = 10; // Sampling time per bit
18 |
19 | wire collect_finish_display;
20 | wire clk_9_6M;
21 | wire uart_clk;
22 | wire sample_clk;
23 | wire sampler_data_out;
24 | wire tx_ready; // tx_ready signifies the availability of TX buffer
25 | wire rx_ready; // when signal == 1, signifies that one byte of data is received
26 | wire [7:0] rx_data; // Received data
27 | wire [7:0] tx_data;
28 | wire tx_start; // start to send data when this bit is set to 1
29 |
30 | wire data_collection_finish;
31 | wire data_send_finish;
32 | wire data_send_run;
33 | wire MEM_we;
34 | wire [13:0] MEM_wr_sel;
35 | wire [13:0] MEM_rd_sel;
36 | wire [7:0] MEM_wr_data;
37 | wire [7:0] MEM_rd_data;
38 | wire [7:0] wd, rd, data_out;
39 | wire [13:0] ws, rs;
40 | wire we, scan_start;
41 | wire [7:0] ss1;
42 | wire [13:0] ss2,ss3;
43 | wire ss4;
44 | // MEM M2(clk, we, ws, rs, sum_out[7:0], rd);
45 | // scan S1(rs, rd, data_out, clk, data_collection_finish, scan_start); // we need to change the names
46 | // systolic sys(sum_out, data_out, clk, scan_start, we, ws);
47 |
48 | assign Rx_data = rx_data;
49 |
50 | Data_Process Data_process( // Collect data, process it, and send it back
51 | .clk(clk_9_6M), //clk_9_6M was there
52 | .rst(rst),
53 | .data_collection_finish(sys_finish),
54 | .data_send_finish(data_send_finish),
55 | .data_send_run(data_send_run)
56 | );
57 |
58 | Data_collect // Collect all the data from PC by UART
59 | #(.NUM_DATA(NUM_DATA))
60 | Data_collect(
61 | .clk(clk_9_6M), // why is it 9.6 MHz???
62 | .rst(rst),
63 | .data_input(rx_data),
64 | .data_ready(rx_ready),
65 | .MEM_write_enable(MEM_we),//changed from MEM_we
66 | .MEM_write_addr(MEM_wr_sel), //changed from MEM_wr_sel
67 | .MEM_write_data(MEM_wr_data), //changed from MEM_wr_data
68 | .finish(data_collection_finish),
69 | .collect_finish_display(collect_finish_display)
70 | );
71 |
72 | Data_send // Send all data back to PC by UART
73 | #(.NUM_DATA(NUM_DATA))
74 | Data_send(
75 | .clk(clk_9_6M), // why did u send data at 9.6Mz??
76 | .rst(rst),
77 | .send_start(data_send_run),
78 | .tx_ready(tx_ready),
79 | .MEM_data(rd), //changed from rd // Changed to read data from second memory module
80 | .MEM_read_sel(rs),//changed from rs
81 | .transmitter_data(tx_data),
82 | .transmitter_start(tx_start),
83 | .finish(data_send_finish)
84 | );
85 |
86 |
87 | /*assign MEM_wr_data = scan_start? ss2 : ss1;
88 | assign MEM_wr_sel = scan_start? ws : ss3;
89 | assign MEM_we = scan_start ? we : ss4;
90 | */
91 | receiver_sampler sampler( // Error checking logic
92 | .rst(rst),
93 | .sample_clk(sample_clk),
94 | .rx_clk(uart_clk),
95 | .RsRx(RsRx),
96 | .data_bit(sampler_data_out)
97 | );
98 |
99 | receiver receiver( // UART Receiver
100 | .data_in(sampler_data_out),
101 | //.data_in(RsRx),
102 | .rx_clk(uart_clk),
103 | .reset(rst),
104 | .signal(rx_ready),
105 | .data_out(rx_data)
106 | );
107 |
108 | transmitter transmitter( // UART Transmitter
109 | .data_in(tx_data),
110 | .tx_clk(uart_clk),
111 | .reset(rst),
112 | .start(tx_start),
113 | .data_out(RsTx),
114 | .tx_ready(tx_ready)
115 | );
116 |
117 | clk_divide // Clock generator for TX and RX
118 | #( .CLK_RATE(CLK_RATE),
119 | .BAUD_RATE(BAUD_RATE),
120 | .SAMPLE_RATE(SAMPLE_RATE))
121 | clk_div(
122 | .clk(clk_9_6M),
123 | .rst(rst),
124 | .clk_uart(uart_clk),
125 | .clk_sampling(sample_clk)
126 | );
127 |
128 | PLL_9_6M PLL( // PLL that generate 9.6 MHz clk
129 | .clk_in(clk),
130 | .clk_out_9_6M(clk_9_6M),
131 | .rst(rst)
132 | );
133 |
134 | MEM // MEM module, MEM read has no delay in this design
135 | #(.NUM_DATA(NUM_DATA))
136 | MEM(
137 | .clk(clk_9_6M),
138 | .wr_enable(MEM_we),
139 | .write_select(MEM_wr_sel),
140 | .read_select(MEM_rd_sel),
141 | .write_data(MEM_wr_data),
142 | .read_data(MEM_rd_data)
143 | );
144 |
145 | MEM M2(clk_9_6M, we, ws, rs, wd, rd); //changed from 9.6Mhz
146 | //module MEM(input clk,input wr_enable,input [13:0] write_select,input [13:0] read_select,input [7:0] write_data,output [7:0] read_data);
147 |
148 | //scan S1(MEM_rd_sel, MEM_rd_data, clk_9_6M, collect_finish_display, rst, ws, we, wd, sys_finish); // we need to change the names // clk_9_6M was there
149 | //module scan(read_select, read_data, clk, start, rst, ws, we, wd, sys_finish);
150 |
151 | //systolic sys(sum_out, data_out, clk_9_6M, scan_start, ws, we, sys_finish, rst);
152 | //systolic sys(sum_out, MEM_rd_sel, clk_9_6M, scan_start, ws, we, sys_finish, rst);
153 |
154 | //systol_new1 sys(MEM_rd_sel, wd, sys_finish, collect_finish_display, clk_9_6M, rst, we, ws);
155 | //module systol_new1(read_select, result, finish, start, read_data, clk, rst);
156 |
157 | //module systol_new1(read_select, result, finish, start, read_data, clk, rst, we, ws);
158 |
159 | systol_new1 a1 (MEM_rd_sel, wd, sys_finish, collect_finish_display, MEM_rd_data, clk_9_6M, rst, we, ws);
160 | //module scan_new(read_select, start, clk, rst, rd, wd, ws, we, finish);
161 | //scan_new s1(MEM_rd_sel, collect_finish_display, clk_9_6M, rst, MEM_rd_data, wd, ws, we, sys_finish);
162 |
163 |
164 | endmodule
165 |
--------------------------------------------------------------------------------
/src/top_direct_send.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 |
4 | module top_direct_send(
5 | input clk,
6 | input rst,
7 | input RsRx, // Connect to RX pin
8 | output [7:0] Rx_data, // Received data
9 | output RsTx // Connect to TX pin
10 | );
11 |
12 | parameter CLK_RATE = 9600000;
13 | parameter BAUD_RATE = 9600;
14 | parameter SAMPLE_RATE = 10;
15 |
16 | wire clk_9_6M;
17 | wire uart_clk;
18 | wire sample_clk;
19 | wire sampler_data_out;
20 | wire tx_ready; // tx_ready signifies the availability of TX buffer
21 | wire rx_ready; // when signal == 1, signifies that one byte of data is received
22 | wire [7:0] data; // Received data
23 | reg tx_start; // start to send data when this bit is set to 1
24 |
25 | assign Rx_data = data;
26 |
27 | receiver_sampler sampler( // Error checking logic
28 | .rst(rst),
29 | .sample_clk(sample_clk),
30 | .rx_clk(uart_clk),
31 | .RsRx(RsRx),
32 | .data_bit(sampler_data_out)
33 | );
34 |
35 | receiver receiver( // Receiver
36 | .data_in(sampler_data_out),
37 | //.data_in(RsRx),
38 | .rx_clk(uart_clk),
39 | .reset(rst),
40 | .signal(rx_ready),
41 | .data_out(data)
42 | );
43 |
44 | transmitter transmitter( // Transmitter
45 | .data_in(data),
46 | .tx_clk(uart_clk),
47 | .reset(rst),
48 | .start(tx_start),
49 | .data_out(RsTx),
50 | .tx_ready(tx_ready)
51 | );
52 |
53 | clk_divide // Clock generator for TX and RX
54 | #( .CLK_RATE(CLK_RATE),
55 | .BAUD_RATE(BAUD_RATE),
56 | .SAMPLE_RATE(SAMPLE_RATE))
57 | clk_div(
58 | .clk(clk_9_6M),
59 | .rst(rst),
60 | .clk_uart(uart_clk),
61 | .clk_sampling(sample_clk)
62 | );
63 |
64 | PLL_9_6M PLL(
65 | .clk_in(clk),
66 | .clk_out_9_6M(clk_9_6M),
67 | .rst(rst)
68 | );
69 |
70 | always @(rx_ready, tx_ready)
71 | begin
72 | if (tx_ready && rx_ready) // start to send one byte of data after you received one
73 | tx_start <= 1'b1;
74 | else
75 | tx_start <= 1'b0;
76 | end
77 |
78 | endmodule
79 |
--------------------------------------------------------------------------------
/src/top_tb.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 17:51:05 11/02/2015
8 | // Design Name: top
9 | // Module Name: C:/Users/Ethan/Desktop/UART/UART/top_tb.v
10 | // Project Name: UART
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: top
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module top_tb;
26 |
27 | // Inputs
28 | reg clk;
29 | reg rst;
30 | reg RsRx;
31 |
32 | // Outputs
33 | wire [7:0] Rx_data;
34 | wire RsTx;
35 |
36 | // Instantiate the Unit Under Test (UUT)
37 | top uut (
38 | .clk(clk),
39 | .rst(rst),
40 | .RsRx(RsRx),
41 | .Rx_data(Rx_data),
42 | .RsTx(RsTx)
43 | );
44 |
45 | always #1 assign clk = ~clk;
46 | always #64 RsRx = ~RsRx;
47 | initial begin
48 | // Initialize Inputs
49 | clk = 0;
50 | rst = 1;
51 | RsRx = 1;
52 |
53 | // Wait 100 ns for global reset to finish
54 | #100;
55 | rst = 0;
56 |
57 | /*#95 RsRx = 1;
58 |
59 | #64 RsRx = 1;
60 | #64 RsRx = 1;
61 | #64 RsRx = 1;
62 | #64 RsRx = 1;
63 | #64 RsRx = 1;
64 | #64 RsRx = 1;
65 | #64 RsRx = 1;
66 | #64 RsRx = 1;
67 | #64 RsRx = 1;
68 | #64 RsRx = 1;
69 | #64 RsRx = 1;
70 | #64 RsRx = 1;
71 | #64 RsRx = 1;
72 | #64 RsRx = 1;
73 | #64 RsRx = 1;
74 | #64 RsRx = 0;
75 | // Send data
76 | #64 RsRx = 1;
77 | #64 RsRx = 0;
78 | #64 RsRx = 0;
79 | #64 RsRx = 0;
80 | #64 RsRx = 0;
81 | #64 RsRx = 0;
82 | #64 RsRx = 0;
83 | #64 RsRx = 0;
84 |
85 | #64 RsRx = 1;
86 | #64 RsRx = 1;
87 | #64 RsRx = 1;
88 | #64 RsRx = 1;
89 | #64 RsRx = 1;
90 | #64 RsRx = 0;
91 | // Send data
92 | #64 RsRx = 0;
93 | #64 RsRx = 1;
94 | #64 RsRx = 0;
95 | #64 RsRx = 0;
96 | #64 RsRx = 0;
97 | #64 RsRx = 0;
98 | #64 RsRx = 0;
99 | #64 RsRx = 0;
100 |
101 | #64 RsRx = 1;
102 | #64 RsRx = 1;
103 | #64 RsRx = 1;
104 | #64 RsRx = 1;
105 | #64 RsRx = 1;
106 | #64 RsRx = 0;
107 | // Send data
108 | #64 RsRx = 1;
109 | #64 RsRx = 1;
110 | #64 RsRx = 0;
111 | #64 RsRx = 0;
112 | #64 RsRx = 0;
113 | #64 RsRx = 0;
114 | #64 RsRx = 0;
115 | #64 RsRx = 0;
116 |
117 | #64 RsRx = 1;
118 | #64 RsRx = 1;
119 | #64 RsRx = 1;
120 | #64 RsRx = 1;
121 | #64 RsRx = 1;
122 | #64 RsRx = 0;
123 | // Send data
124 | #64 RsRx = 0;
125 | #64 RsRx = 0;
126 | #64 RsRx = 1;
127 | #64 RsRx = 0;
128 | #64 RsRx = 0;
129 | #64 RsRx = 0;
130 | #64 RsRx = 0;
131 | #64 RsRx = 0;
132 |
133 | #64 RsRx = 1;
134 | #64 RsRx = 1;
135 | #64 RsRx = 1;
136 | #64 RsRx = 1;
137 | #64 RsRx = 1;
138 | #64 RsRx = 0;
139 | // Send data
140 | #64 RsRx = 1;
141 | #64 RsRx = 0;
142 | #64 RsRx = 1;
143 | #64 RsRx = 0;
144 | #64 RsRx = 0;
145 | #64 RsRx = 0;
146 | #64 RsRx = 0;
147 | #64 RsRx = 0;
148 |
149 | #64 RsRx = 1;
150 | #64 RsRx = 1;
151 | #64 RsRx = 1;
152 | #64 RsRx = 1;
153 | #64 RsRx = 1;
154 | #64 RsRx = 0;
155 | // Send data
156 | #64 RsRx = 0;
157 | #64 RsRx = 1;
158 | #64 RsRx = 1;
159 | #64 RsRx = 0;
160 | #64 RsRx = 0;
161 | #64 RsRx = 0;
162 | #64 RsRx = 0;
163 | #64 RsRx = 0;
164 |
165 | #64 RsRx = 1;
166 | #64 RsRx = 1;
167 | #64 RsRx = 1;
168 | #64 RsRx = 1;
169 | #64 RsRx = 1;
170 | #64 RsRx = 0;
171 | // Send data
172 | #64 RsRx = 1;
173 | #64 RsRx = 1;
174 | #64 RsRx = 1;
175 | #64 RsRx = 0;
176 | #64 RsRx = 0;
177 | #64 RsRx = 0;
178 | #64 RsRx = 0;
179 | #64 RsRx = 0;
180 |
181 | #64 RsRx = 1;
182 | #64 RsRx = 1;
183 | #64 RsRx = 1;
184 | #64 RsRx = 1;
185 | #64 RsRx = 1;
186 | #64 RsRx = 0;
187 | // Send data
188 | #64 RsRx = 0;
189 | #64 RsRx = 0;
190 | #64 RsRx = 0;
191 | #64 RsRx = 1;
192 | #64 RsRx = 0;
193 | #64 RsRx = 0;
194 | #64 RsRx = 0;
195 | #64 RsRx = 0;
196 |
197 | #64 RsRx = 1;
198 | #64 RsRx = 1;
199 | #64 RsRx = 1;
200 | #64 RsRx = 1;
201 | #64 RsRx = 1;
202 | #64 RsRx = 0;
203 | // Send data
204 | #64 RsRx = 1;
205 | #64 RsRx = 0;
206 | #64 RsRx = 0;
207 | #64 RsRx = 1;
208 | #64 RsRx = 0;
209 | #64 RsRx = 0;
210 | #64 RsRx = 0;
211 | #64 RsRx = 0;
212 |
213 | #64 RsRx = 1;
214 | #64 RsRx = 1;
215 | #64 RsRx = 1;
216 | #64 RsRx = 1;
217 | #64 RsRx = 1;
218 | #64 RsRx = 0;
219 | // Send data
220 | #64 RsRx = 0;
221 | #64 RsRx = 1;
222 | #64 RsRx = 0;
223 | #64 RsRx = 1;
224 | #64 RsRx = 0;
225 | #64 RsRx = 0;
226 | #64 RsRx = 0;
227 | #64 RsRx = 0;
228 |
229 | #64 RsRx = 1;*/
230 |
231 |
232 | end
233 |
234 | endmodule
235 |
236 |
--------------------------------------------------------------------------------
/src/transmitter.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ns
2 |
3 | module transmitter(
4 | input [7:0] data_in, // one byte of data you want to send out
5 | input tx_clk, // clk
6 | input reset,
7 | input start, // Only start to send out data when start == 1
8 | output data_out, // TX buffer
9 | output tx_ready // tx_ready signifies the availability of TX buffer
10 | );
11 |
12 | reg [10:0] shift; // TX buffer
13 | reg [3:0] state;
14 | reg available; // signify TX's availability
15 |
16 | assign data_out = shift[0];
17 | assign tx_ready = available;
18 |
19 | always @(posedge tx_clk , posedge reset)
20 | begin
21 | if (reset) // On reset, always set the TX bus high
22 | begin
23 | shift <= 10'b1111111111;
24 | state <= 0;
25 | available <= 1'b1;
26 | end
27 | else if (start == 0 && state == 0) // Wait for start signal
28 | begin
29 | state <= 0;
30 | available <= 1;
31 | end
32 | else if (start == 1 && state == 0) // When start signal comes, prepare the data to send, move to next state
33 | begin
34 | shift <= {1'b1,data_in,1'b0,1'b1};
35 | state <= 1;
36 | available <= 0;
37 | end
38 | else if (state == 12 && start == 1) // Wait for the start signal to drop before next TX operation
39 | begin
40 | state <= 12;
41 | available <= 0;
42 | end
43 | else if (state == 12 && start == 0) // Move to the waiting state and wait for the next rising of start signal
44 | begin
45 | state <= 0;
46 | available <= 1;
47 | end
48 | else // send 10 bits of data one at a time
49 | begin
50 | available <= 0;
51 | state <= state+1'b1;
52 | shift[0] <= shift [1];
53 | shift[1] <= shift[2];
54 | shift[2] <= shift [3];
55 | shift[3] <= shift [4];
56 | shift[4] <= shift [5];
57 | shift[5] <= shift [6];
58 | shift[6] <= shift [7];
59 | shift[7] <= shift [8];
60 | shift[8] <= shift [9];
61 | shift[9] <= shift [10];
62 | shift[10] <= 1'b1;
63 | end
64 | end
65 |
66 | endmodule
--------------------------------------------------------------------------------