├── .gitmodules ├── LICENSE ├── README.md ├── common ├── ao486_rst_controller.v ├── bios_loader.v ├── burst_converter.v ├── byteen_converter.v ├── io_bus.v ├── pc_bus_to_vga.v ├── simple_biclk_bidir_ram.v ├── to_driver_sd_avs.v └── to_sdram.v ├── fpga ├── de2-115 │ ├── project │ │ ├── project.qpf │ │ ├── project.qsf │ │ └── project.sdc │ └── rtl │ │ ├── clock │ │ ├── clk_wiz_0.ppf │ │ ├── clk_wiz_0.qip │ │ ├── clk_wiz_0.v │ │ ├── clk_wiz_0_bb.v │ │ └── clock.v │ │ ├── params.v │ │ ├── soc.v │ │ ├── system.v │ │ └── system_sdram.v ├── nexys4 │ ├── constraint │ │ └── Nexys4_Master.xdc │ ├── project │ │ └── project.xpr │ └── rtl │ │ ├── clock │ │ ├── clk_wiz_0.v │ │ ├── clk_wiz_0_clk_wiz.v │ │ └── clock.v │ │ ├── params.v │ │ ├── psramcon.v │ │ ├── soc.v │ │ └── system.v └── nexys4_ddr │ ├── constraint │ └── Nexys4DDR_Master.xdc │ ├── project │ ├── project.srcs │ │ └── sources_1 │ │ │ └── ip │ │ │ └── mig │ │ │ ├── doc │ │ │ └── mig_7series_v2_0_changelog.txt │ │ │ ├── mig.dcp │ │ │ ├── mig.veo │ │ │ ├── mig.xci │ │ │ ├── mig.xml │ │ │ ├── mig │ │ │ ├── datasheet.txt │ │ │ ├── docs │ │ │ │ └── phy_only_support_readme.txt │ │ │ ├── example_design │ │ │ │ ├── log.txt │ │ │ │ ├── par │ │ │ │ │ ├── example_top.xdc │ │ │ │ │ └── readme.txt │ │ │ │ ├── rtl │ │ │ │ │ ├── example_top.v │ │ │ │ │ └── traffic_gen │ │ │ │ │ │ ├── mig_7series_v2_0_afifo.v │ │ │ │ │ │ ├── mig_7series_v2_0_cmd_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_cmd_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_data_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_init_mem_pattern_ctr.v │ │ │ │ │ │ ├── mig_7series_v2_0_memc_flow_vcontrol.v │ │ │ │ │ │ ├── mig_7series_v2_0_memc_traffic_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_rd_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_read_data_path.v │ │ │ │ │ │ ├── mig_7series_v2_0_read_posted_fifo.v │ │ │ │ │ │ ├── mig_7series_v2_0_s7ven_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_tg_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_tg_status.v │ │ │ │ │ │ ├── mig_7series_v2_0_traffic_gen_top.v │ │ │ │ │ │ ├── mig_7series_v2_0_vio_init_pattern_bram.v │ │ │ │ │ │ ├── mig_7series_v2_0_wr_data_gen.v │ │ │ │ │ │ └── mig_7series_v2_0_write_data_path.v │ │ │ │ └── sim │ │ │ │ │ ├── ddr2_model.v │ │ │ │ │ ├── ddr2_model_parameters.vh │ │ │ │ │ ├── ies_run.sh │ │ │ │ │ ├── readme.txt │ │ │ │ │ ├── sim.do │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── vcs_run.sh │ │ │ │ │ ├── wiredly.v │ │ │ │ │ ├── xsim_files.prj │ │ │ │ │ ├── xsim_options.tcl │ │ │ │ │ └── xsim_run.bat │ │ │ ├── mig.prj │ │ │ └── user_design │ │ │ │ ├── constraints │ │ │ │ ├── mig.xdc │ │ │ │ └── mig_ooc.xdc │ │ │ │ ├── log.txt │ │ │ │ └── rtl │ │ │ │ ├── clocking │ │ │ │ ├── mig_7series_v2_0_clk_ibuf.v │ │ │ │ ├── mig_7series_v2_0_infrastructure.v │ │ │ │ ├── mig_7series_v2_0_iodelay_ctrl.v │ │ │ │ └── mig_7series_v2_0_tempmon.v │ │ │ │ ├── controller │ │ │ │ ├── mig_7series_v2_0_arb_mux.v │ │ │ │ ├── mig_7series_v2_0_arb_row_col.v │ │ │ │ ├── mig_7series_v2_0_arb_select.v │ │ │ │ ├── mig_7series_v2_0_bank_cntrl.v │ │ │ │ ├── mig_7series_v2_0_bank_common.v │ │ │ │ ├── mig_7series_v2_0_bank_compare.v │ │ │ │ ├── mig_7series_v2_0_bank_mach.v │ │ │ │ ├── mig_7series_v2_0_bank_queue.v │ │ │ │ ├── mig_7series_v2_0_bank_state.v │ │ │ │ ├── mig_7series_v2_0_col_mach.v │ │ │ │ ├── mig_7series_v2_0_mc.v │ │ │ │ ├── mig_7series_v2_0_rank_cntrl.v │ │ │ │ ├── mig_7series_v2_0_rank_common.v │ │ │ │ ├── mig_7series_v2_0_rank_mach.v │ │ │ │ └── mig_7series_v2_0_round_robin_arb.v │ │ │ │ ├── ecc │ │ │ │ ├── mig_7series_v2_0_ecc_buf.v │ │ │ │ ├── mig_7series_v2_0_ecc_dec_fix.v │ │ │ │ ├── mig_7series_v2_0_ecc_gen.v │ │ │ │ ├── mig_7series_v2_0_ecc_merge_enc.v │ │ │ │ └── mig_7series_v2_0_fi_xor.v │ │ │ │ ├── ip_top │ │ │ │ ├── mig_7series_v2_0_mem_intfc.v │ │ │ │ └── mig_7series_v2_0_memc_ui_top_std.v │ │ │ │ ├── mig.v │ │ │ │ ├── mig_mig.v │ │ │ │ ├── mig_mig_sim.v │ │ │ │ ├── phy │ │ │ │ ├── mig_7series_v2_0_ddr_byte_group_io.v │ │ │ │ ├── mig_7series_v2_0_ddr_byte_lane.v │ │ │ │ ├── mig_7series_v2_0_ddr_calib_top.v │ │ │ │ ├── mig_7series_v2_0_ddr_if_post_fifo.v │ │ │ │ ├── mig_7series_v2_0_ddr_mc_phy.v │ │ │ │ ├── mig_7series_v2_0_ddr_mc_phy_wrapper.v │ │ │ │ ├── mig_7series_v2_0_ddr_of_pre_fifo.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_4lanes.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_dqs_found_cal.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_dqs_found_cal_hr.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_init.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_oclkdelay_cal.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_prbs_rdlvl.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_rdlvl.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_tempmon.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_top.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_wrcal.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_wrlvl_off_delay.v │ │ │ │ └── mig_7series_v2_0_ddr_prbs_gen.v │ │ │ │ └── ui │ │ │ │ ├── mig_7series_v2_0_ui_cmd.v │ │ │ │ ├── mig_7series_v2_0_ui_rd_data.v │ │ │ │ ├── mig_7series_v2_0_ui_top.v │ │ │ │ └── mig_7series_v2_0_ui_wr_data.v │ │ │ ├── mig_a.prj │ │ │ ├── mig_b.prj │ │ │ ├── mig_funcsim.v │ │ │ ├── mig_funcsim.vhdl │ │ │ ├── mig_stub.v │ │ │ ├── mig_stub.vhdl │ │ │ ├── mig_xmdf.tcl │ │ │ ├── tcl.log │ │ │ ├── xil_txt.in │ │ │ └── xil_txt.out │ └── project.xpr │ └── rtl │ ├── cache_4word.v │ ├── clock │ ├── clk_wiz_0.v │ ├── clk_wiz_0_clk_wiz.v │ └── clock.v │ ├── dram.v │ ├── params.v │ ├── soc.v │ └── system.v └── misc ├── ao486 └── ao486.patch └── tinycore ├── config-ao486 └── patch_ao486 /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "ao486"] 2 | path = ao486 3 | url = https://github.com/alfikpl/ao486.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2015, Arch Labolatory 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | * Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation 12 | and/or other materials provided with the distribution. 13 | 14 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 18 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 21 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 23 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | 25 | -------------------------------------------------------------------------------- /common/ao486_rst_controller.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Labolatory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module ao486_rst_controller 28 | ( 29 | input wire clk_sys, 30 | input wire rst, 31 | output reg ao486_rst, 32 | 33 | input wire [1:0] address, 34 | input wire write, 35 | input wire [31:0] writedata 36 | ); 37 | 38 | always @(posedge clk_sys) begin 39 | if(rst) begin 40 | ao486_rst <= 1; 41 | end else begin 42 | if(write && writedata[0] == 1'b0 && address == 4'b0000) 43 | ao486_rst <= 0; 44 | else if(write && writedata[0] == 1'b1 && address == 4'b0000) 45 | ao486_rst <= 1; 46 | end 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /common/bios_loader.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module bios_loader ( 28 | input wire clk, 29 | input wire rst, 30 | output reg [27:0] address, 31 | output reg [3:0] byteenable, 32 | output reg write, 33 | output reg [31:0] writedata, 34 | output reg read, 35 | input wire [31:0] readdata, 36 | input wire waitrequest 37 | ); 38 | 39 | parameter PIO_OUTPUT_ADDR = 32'h00008860; 40 | parameter DRIVER_SD_ADDR = 32'h00000000; 41 | 42 | parameter BIOS_SECTOR = 72; 43 | parameter BIOS_SIZE = (64*1024); 44 | parameter BIOS_ADDR = 32'hF0000 | 32'h8000000; 45 | parameter VBIOS_SECTOR = 8; 46 | parameter VBIOS_SIZE = (32*1024); 47 | parameter VBIOS_ADDR = 32'hC0000 | 32'h8000000; 48 | 49 | parameter CTRL_READ = 2; 50 | 51 | reg [31:0] state; 52 | always @(posedge clk) begin 53 | if(rst) state <= 1; 54 | else if(state != 0 && (!(waitrequest && write))) state <= state + 1; 55 | end 56 | 57 | always @(posedge clk) begin 58 | if(rst) begin 59 | write <= 0; 60 | read <= 0; 61 | writedata <= 0; 62 | address <= 0; 63 | byteenable <= 4'b0000; 64 | end else if(!(waitrequest && write))begin 65 | case(state) 66 | 20000000: begin 67 | // set pio_output to 1 (set ao486_reset to low) 68 | address <= PIO_OUTPUT_ADDR; 69 | writedata <= 32'h1; 70 | write <= 1; 71 | end 72 | 20001000: begin 73 | // load bios 74 | // bios address 75 | write <= 1; 76 | address <= DRIVER_SD_ADDR; 77 | writedata <= BIOS_ADDR; 78 | end 79 | 20002000: begin 80 | // load bios 81 | // SD sector 82 | write <= 1; 83 | address <= DRIVER_SD_ADDR + 4; 84 | writedata <= BIOS_SECTOR; 85 | end 86 | 20003000: begin 87 | // load bios 88 | // sector count 89 | write <= 1; 90 | address <= DRIVER_SD_ADDR + 8; 91 | writedata <= BIOS_SIZE / 512; 92 | end 93 | 20004000: begin 94 | // load bios 95 | // control READ 96 | write <= 1; 97 | address <= DRIVER_SD_ADDR + 12; 98 | writedata <= CTRL_READ; 99 | end 100 | 40004000: begin 101 | // load vbios 102 | // vbios address 103 | write <= 1; 104 | address <= DRIVER_SD_ADDR; 105 | writedata <= VBIOS_ADDR; 106 | end 107 | 40005000: begin 108 | // load vbios 109 | // SD sector 110 | write <= 1; 111 | address <= DRIVER_SD_ADDR + 4; 112 | writedata <= VBIOS_SECTOR; 113 | end 114 | 40006000: begin 115 | // load vbios 116 | // sector count 117 | write <= 1; 118 | address <= DRIVER_SD_ADDR + 8; 119 | writedata <= VBIOS_SIZE / 512; 120 | end 121 | 40007000: begin 122 | // load vbios 123 | // control READ 124 | write <= 1; 125 | address <= DRIVER_SD_ADDR + 12; 126 | writedata <= CTRL_READ; 127 | end 128 | 60007000: begin 129 | // set pio_output to 0 (set ao486_reset to high) 130 | address <= PIO_OUTPUT_ADDR; 131 | writedata <= 32'h0; 132 | write <= 1; 133 | end 134 | default: begin 135 | write <= 0; 136 | writedata <= 0; 137 | address <= 0; 138 | end 139 | endcase 140 | end 141 | end 142 | endmodule 143 | -------------------------------------------------------------------------------- /common/burst_converter.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module burst_converter 28 | #( 29 | parameter IADDR = 32, 30 | parameter OADDR = 32 31 | ) 32 | ( 33 | input wire clk_sys, 34 | input wire rst, 35 | 36 | input wire [IADDR-1:0] addr_in, 37 | input wire write_in, 38 | input wire [31:0] writedata_in, 39 | input wire read_in, 40 | output wire [31:0] readdata_out, 41 | output wire readdatavalid_out, 42 | input wire [3:0] byteenable_in, 43 | input wire [2:0] burstcount_in, 44 | output wire waitrequest_out, 45 | 46 | output wire [OADDR-1:0] addr_out, 47 | output wire write_out, 48 | output wire [31:0] writedata_out, 49 | output wire read_out, 50 | input wire [31:0] readdata_in, 51 | input wire readdatavalid_in, 52 | output wire [3:0] byteenable_out, 53 | input wire waitrequest_in 54 | ); 55 | 56 | 57 | // data 58 | // data[8] = valid bit 59 | reg [IADDR-1:0] raddr, waddr; 60 | reg [3:0] rcount, wcount; 61 | 62 | assign addr_out = (rcount[1]) ? raddr + 4 : 63 | (rcount[2]) ? raddr + 8 : 64 | (rcount[3]) ? raddr + 12 : 65 | (wcount[1]) ? waddr + 4 : 66 | (wcount[2]) ? waddr + 8 : 67 | (wcount[3]) ? waddr + 12 : addr_in; 68 | 69 | assign writedata_out = writedata_in; 70 | assign byteenable_out = byteenable_in; 71 | 72 | assign write_out = write_in; 73 | assign read_out = (read_in && burstcount_in != 0) || rcount; 74 | 75 | assign readdata_out = readdata_in; 76 | assign readdatavalid_out = readdatavalid_in; 77 | assign waitrequest_out = waitrequest_in; 78 | 79 | ///////////////////////////////////////////////////////////////////////// 80 | // burst write 81 | ///////////////////////////////////////////////////////////////////////// 82 | always @(posedge clk_sys) begin 83 | if(rst) begin 84 | wcount <= 0; 85 | waddr <= 0; 86 | end else if(wcount[1] && !waitrequest_in) begin 87 | wcount[1] <= 0; 88 | end else if(wcount[2] && !waitrequest_in) begin 89 | wcount[2] <= 0; 90 | end else if(wcount[3] && !waitrequest_in) begin 91 | wcount[3] <= 0; 92 | end else if(burstcount_in > 1 && write_in && !waitrequest_out) begin 93 | waddr <= addr_in; 94 | 95 | wcount <= (burstcount_in == 4) ? 4'b1110 : 96 | (burstcount_in == 3) ? 4'b0110 : 97 | (burstcount_in == 2) ? 4'b0010 : 0; 98 | end 99 | end 100 | 101 | ///////////////////////////////////////////////////////////////////////// 102 | // burst read 103 | ///////////////////////////////////////////////////////////////////////// 104 | always @(posedge clk_sys) begin 105 | if(rst) begin 106 | rcount <= 0; 107 | raddr <= 0; 108 | end else if(rcount[1] && !waitrequest_in) begin 109 | rcount[1] <= 0; 110 | end else if(rcount[2] && !waitrequest_in) begin 111 | rcount[2] <= 0; 112 | end else if(rcount[3] && !waitrequest_in) begin 113 | rcount[3] <= 0; 114 | end else if(burstcount_in > 1 && read_in && !waitrequest_out) begin 115 | raddr <= addr_in; 116 | 117 | rcount <= (burstcount_in == 4) ? 4'b1110 : 118 | (burstcount_in == 3) ? 4'b0110 : 119 | (burstcount_in == 2) ? 4'b0010 : 0; 120 | end 121 | end 122 | endmodule 123 | -------------------------------------------------------------------------------- /common/byteen_converter.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module byteen_converter 28 | #( 29 | parameter IADDR = 32, 30 | parameter OADDR = 32 31 | ) 32 | ( 33 | input wire clk_sys, 34 | input wire rst, 35 | 36 | input wire [IADDR-1:0] addr_in, 37 | input wire write_in, 38 | input wire [31:0] writedata_in, 39 | input wire read_in, 40 | output reg [31:0] readdata_out, 41 | output reg readdatavalid_out, 42 | input wire [3:0] byteenable_in, 43 | output wire waitrequest_out, 44 | 45 | output wire [OADDR-1:0] addr_out, 46 | output wire write_out, 47 | output wire [7:0] writedata_out, 48 | output wire read_out, 49 | input wire [7:0] readdata_in, 50 | input wire readdatavalid_in, 51 | input wire waitrequest_in 52 | ); 53 | 54 | function [2:0] cnt_bit; 55 | input [3:0] data; 56 | integer index; 57 | begin 58 | cnt_bit = 0; 59 | for(index = 0; index < 4; index = index + 1) 60 | if(data[index]) 61 | cnt_bit = cnt_bit + 1; 62 | end 63 | endfunction 64 | 65 | // data 66 | // data[8] = valid bit 67 | reg [IADDR-1:0] addr0; 68 | reg [8:0] data0; // not used 69 | reg [8:0] data1; // data1 70 | reg [8:0] data2; // data2 71 | reg [8:0] data3; // data3 72 | 73 | reg write_mode, read_mode; 74 | 75 | assign addr_out = (data1[8]) ? addr0 | 1 : 76 | (data2[8]) ? addr0 | 2 : 77 | (data3[8]) ? addr0 | 3 : 78 | (byteenable_in[0]) ? addr_in : 79 | (byteenable_in[1]) ? addr_in | 1 : 80 | (byteenable_in[2]) ? addr_in | 2 : 81 | (byteenable_in[3]) ? addr_in | 3 : 0; 82 | 83 | assign writedata_out = (data1[8] && write_mode) ? data1[7:0] : 84 | (data2[8] && write_mode) ? data2[7:0] : 85 | (data3[8] && write_mode) ? data3[7:0] : 86 | (byteenable_in[0]) ? writedata_in[7:0] : 87 | (byteenable_in[1]) ? writedata_in[15:8] : 88 | (byteenable_in[2]) ? writedata_in[23:16] : 89 | (byteenable_in[3]) ? writedata_in[31:24] : 0; 90 | 91 | assign write_out = (!read_mode) && ((write_in && byteenable_in != 0) || write_mode); 92 | assign read_out = (!write_mode) && ((read_in && byteenable_in != 0) || read_mode); 93 | 94 | assign waitrequest_out = waitrequest_in || read_mode || write_mode; 95 | 96 | always @(posedge clk_sys) begin 97 | if(rst) begin 98 | {data1, data2, data3} <= 0; 99 | {write_mode, read_mode} <= 0; 100 | end else if(data1[8]) begin 101 | data1 <= 0; 102 | write_mode <= write_mode && (data2[8] || data3[8]); 103 | read_mode <= read_mode && (data2[8] || data3[8]); 104 | end else if(data2[8]) begin 105 | data2 <= 0; 106 | write_mode <= write_mode && (data3[8]); 107 | read_mode <= read_mode && (data3[8]); 108 | end else if(data3[8]) begin 109 | data3 <= 0; 110 | write_mode <= 0; 111 | read_mode <= 0; 112 | end else if(cnt_bit(byteenable_in) > 1 && (write_in || read_in)) begin 113 | write_mode <= write_in; 114 | read_mode <= read_in; 115 | addr0 <= addr_in; 116 | 117 | data1[8] <= (byteenable_in[0] && byteenable_in[1]) ? 1 : 0; 118 | data2[8] <= (byteenable_in[1:0] && byteenable_in[2]) ? 1 : 0; 119 | data3[8] <= (byteenable_in[2:0] && byteenable_in[3]) ? 1 : 0; 120 | 121 | data1[7:0] <= (byteenable_in[0] && byteenable_in[1]) ? writedata_in[15: 8] : 0; 122 | data2[7:0] <= (byteenable_in[1:0] && byteenable_in[2]) ? writedata_in[23:16] : 0; 123 | data3[7:0] <= (byteenable_in[2:0] && byteenable_in[3]) ? writedata_in[31:24] : 0; 124 | end 125 | end 126 | 127 | 128 | ///////////////////////////////////////////////////////////////////////// 129 | reg [3:0] rflag; 130 | 131 | always @(posedge clk_sys) begin 132 | if(rst) begin 133 | rflag <= 0; 134 | readdata_out <= 0; 135 | readdatavalid_out <= 0; 136 | end else begin 137 | if(rflag[0] && readdatavalid_in) begin 138 | rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3:1], 1'b0}; 139 | 140 | readdata_out <= {readdata_out[31:8], readdata_in}; 141 | readdatavalid_out <= !(rflag[3:1]); 142 | end else if(rflag[1] && readdatavalid_in) begin 143 | rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3:2], 2'b0}; 144 | 145 | readdata_out <= {readdata_out[31:16], readdata_in, readdata_out[7:0]}; 146 | readdatavalid_out <= !(rflag[3:2]); 147 | end else if(rflag[2] && readdatavalid_in) begin 148 | rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3], 3'b0}; 149 | 150 | readdata_out <= {readdata_out[31:24], readdata_in[7:0], readdata_out[15:0]}; 151 | readdatavalid_out <= !(rflag[3]); 152 | end else if(rflag[3] && readdatavalid_in) begin 153 | rflag <= (read_in && !waitrequest_out) ? byteenable_in : 0; 154 | 155 | readdata_out <= {readdata_in[7:0], readdata_out[23:0]}; 156 | readdatavalid_out <= 1; 157 | end else if(read_in && !waitrequest_out) begin 158 | rflag <= byteenable_in; 159 | readdatavalid_out <= 0; 160 | end else begin 161 | readdatavalid_out <= 0; 162 | end 163 | end 164 | end 165 | endmodule 166 | -------------------------------------------------------------------------------- /common/pc_bus_to_vga.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module pc_bus_to_vga 28 | ( 29 | input wire clk_sys, 30 | input wire rst, 31 | 32 | // input pc_bus_vga 33 | input wire [31:0] pc_bus_vga_address, 34 | input wire [3:0] pc_bus_vga_byteenable, 35 | input wire pc_bus_vga_read, 36 | output wire [31:0] pc_bus_vga_readdata, 37 | input wire pc_bus_vga_write, 38 | input wire [31:0] pc_bus_vga_writedata, 39 | output wire pc_bus_vga_waitrequest, 40 | output wire pc_bus_vga_readdatavalid, 41 | input wire [2:0] pc_bus_vga_burstcount, 42 | 43 | // output vga_mem 44 | output wire [16:0] vga_mem_address, 45 | output wire vga_mem_read, 46 | input wire [7:0] vga_mem_readdata, 47 | output wire vga_mem_write, 48 | output wire [7:0] vga_mem_writedata 49 | ); 50 | 51 | wire [31:0] burst_converted_address; 52 | wire burst_converted_write; 53 | wire [31:0] burst_converted_writedata; 54 | wire burst_converted_read; 55 | wire [31:0] burst_converted_readdata; 56 | wire burst_converted_readdatavalid; 57 | wire [3:0] burst_converted_byteenable; 58 | wire burst_converted_waitrequest; 59 | 60 | burst_converter #(.IADDR(32), .OADDR(32)) 61 | burst_converter ( 62 | .clk_sys (clk_sys), 63 | .rst (rst), 64 | .addr_in (pc_bus_vga_address), 65 | .write_in (pc_bus_vga_write), 66 | .writedata_in (pc_bus_vga_writedata), 67 | .read_in (pc_bus_vga_read), 68 | .readdata_out (pc_bus_vga_readdata), 69 | .readdatavalid_out (pc_bus_vga_readdatavalid), 70 | .byteenable_in (pc_bus_vga_byteenable), 71 | .burstcount_in (pc_bus_vga_burstcount), 72 | .waitrequest_out (pc_bus_vga_waitrequest), 73 | 74 | .addr_out (burst_converted_address), 75 | .write_out (burst_converted_write), 76 | .writedata_out (burst_converted_writedata), 77 | .read_out (burst_converted_read), 78 | .readdata_in (burst_converted_readdata), 79 | .readdatavalid_in (burst_converted_readdatavalid), 80 | .byteenable_out (burst_converted_byteenable), 81 | .waitrequest_in (burst_converted_waitrequest) 82 | ); 83 | 84 | reg vga_mem_readdatavalid; 85 | always @(posedge clk_sys) vga_mem_readdatavalid <= vga_mem_read; 86 | 87 | byteen_converter #(.IADDR(32), .OADDR(17)) 88 | byteen_converter ( 89 | .clk_sys (clk_sys), 90 | .rst (rst), 91 | .addr_in (burst_converted_address), 92 | .write_in (burst_converted_write), 93 | .writedata_in (burst_converted_writedata), 94 | .read_in (burst_converted_read), 95 | .readdata_out (burst_converted_readdata), 96 | .readdatavalid_out (burst_converted_readdatavalid), 97 | .byteenable_in (burst_converted_byteenable), 98 | .waitrequest_out (burst_converted_waitrequest), 99 | 100 | .addr_out (vga_mem_address), 101 | .write_out (vga_mem_write), 102 | .writedata_out (vga_mem_writedata), 103 | .read_out (vga_mem_read), 104 | .readdata_in (vga_mem_readdata), 105 | .readdatavalid_in (vga_mem_readdatavalid), 106 | .waitrequest_in (0) 107 | ); 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /common/simple_biclk_bidir_ram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, Aleksander Osman 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 19 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 | */ 26 | 27 | module simple_biclk_bidir_ram 28 | #(parameter width = 1, 29 | parameter widthad = 1) 30 | 31 | ( 32 | input clk, 33 | 34 | input [widthad-1:0] address_a, 35 | input wren_a, 36 | input [width-1:0] data_a, 37 | output reg [width-1:0] q_a, 38 | 39 | input clk2, 40 | input [widthad-1:0] address_b, 41 | output reg [width-1:0] q_b 42 | ); 43 | 44 | reg [width-1:0] mem [(2**widthad)-1:0]; 45 | 46 | always @(posedge clk) begin 47 | if(wren_a) mem[address_a] <= data_a; 48 | 49 | q_a <= mem[address_a]; 50 | end 51 | 52 | always @(posedge clk2) begin 53 | q_b <= mem[address_b]; 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /common/to_driver_sd_avs.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module to_driver_sd_avs( 28 | input wire clk_sys, 29 | input wire rst, 30 | input wire ao486_rst, 31 | 32 | // input hdd_avalon_master 33 | input wire [31:0] hdd_avalon_master_address, 34 | input wire hdd_avalon_master_read, 35 | output wire [31:0] hdd_avalon_master_readdata, 36 | input wire hdd_avalon_master_write, 37 | input wire [31:0] hdd_avalon_master_writedata, 38 | output wire hdd_avalon_master_waitrequest, 39 | output reg hdd_avalon_master_readdatavalid, 40 | 41 | // input bios_loader 42 | input wire [31:0] bios_loader_address, 43 | input wire bios_loader_read, 44 | output wire [31:0] bios_loader_readdata, 45 | input wire bios_loader_write, 46 | input wire [31:0] bios_loader_writedata, 47 | output wire bios_loader_waitrequest, 48 | input wire [3:0] bios_loader_byteenable, 49 | 50 | // output driver_sd_avs 51 | output wire [1:0] driver_sd_avs_address, 52 | output wire driver_sd_avs_read, 53 | input wire [31:0] driver_sd_avs_readdata, 54 | output wire driver_sd_avs_write, 55 | output wire [31:0] driver_sd_avs_writedata 56 | ); 57 | 58 | assign driver_sd_avs_address = (~ao486_rst) ? hdd_avalon_master_address[3:2] : bios_loader_address[3:2]; 59 | assign driver_sd_avs_read = (~ao486_rst) ? hdd_avalon_master_read : bios_loader_read && bios_loader_address[31:4] == 28'h0; 60 | assign driver_sd_avs_write = (~ao486_rst) ? hdd_avalon_master_write : bios_loader_write && bios_loader_address[31:4] == 28'h0; 61 | assign driver_sd_avs_writedata = (~ao486_rst) ? hdd_avalon_master_writedata : bios_loader_writedata; 62 | 63 | assign hdd_avalon_master_readdata = (~ao486_rst) ? driver_sd_avs_readdata : 0; 64 | assign hdd_avalon_master_waitrequest = 0; 65 | always @(posedge clk_sys) hdd_avalon_master_readdatavalid <= (~ao486_rst) ? driver_sd_avs_read : 0; 66 | 67 | assign bios_loader_readdata = (~ao486_rst) ? 0 : driver_sd_avs_readdata; 68 | assign bios_loader_waitrequest = 0; 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /common/to_sdram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module to_sdram 28 | ( 29 | input wire clk_sys, 30 | input wire rst, 31 | input wire ao486_rst, 32 | 33 | // input pc_bus_sdram 34 | input wire [31:0] pc_bus_sdram_address, 35 | input wire [3:0] pc_bus_sdram_byteenable, 36 | input wire pc_bus_sdram_read, 37 | output wire [31:0] pc_bus_sdram_readdata, 38 | input wire pc_bus_sdram_write, 39 | input wire [31:0] pc_bus_sdram_writedata, 40 | output wire pc_bus_sdram_waitrequest, 41 | output wire pc_bus_sdram_readdatavalid, 42 | input wire [2:0] pc_bus_sdram_burstcount, 43 | 44 | // input driver_sd_avm 45 | input wire [31:0] driver_sd_avm_address, 46 | input wire driver_sd_avm_read, 47 | output wire [31:0] driver_sd_avm_readdata, 48 | input wire driver_sd_avm_write, 49 | input wire [31:0] driver_sd_avm_writedata, 50 | output wire driver_sd_avm_waitrequest, 51 | output wire driver_sd_avm_readdatavalid, 52 | 53 | // output sdram_mem 54 | output wire [24:0] sdram_address, 55 | output wire [3:0] sdram_byteenable, 56 | output wire sdram_read, 57 | input wire [31:0] sdram_readdata, 58 | output wire sdram_write, 59 | output wire [31:0] sdram_writedata, 60 | input wire sdram_waitrequest, 61 | input wire sdram_readdatavalid, 62 | input wire sdram_chipselect 63 | ); 64 | 65 | wire [31:0] burst_converted_address; 66 | wire burst_converted_write; 67 | wire [31:0] burst_converted_writedata; 68 | wire burst_converted_read; 69 | wire [31:0] burst_converted_readdata; 70 | wire burst_converted_readdatavalid; 71 | wire [3:0] burst_converted_byteenable; 72 | wire burst_converted_waitrequest; 73 | 74 | burst_converter #(.IADDR(32), .OADDR(27)) 75 | burst_converter ( 76 | .clk_sys (clk_sys), 77 | .rst (rst), 78 | .addr_in (pc_bus_sdram_address), 79 | .write_in (pc_bus_sdram_write), 80 | .writedata_in (pc_bus_sdram_writedata), 81 | .read_in (pc_bus_sdram_read), 82 | .readdata_out (pc_bus_sdram_readdata), 83 | .readdatavalid_out (pc_bus_sdram_readdatavalid), 84 | .byteenable_in (pc_bus_sdram_byteenable), 85 | .burstcount_in (pc_bus_sdram_burstcount), 86 | .waitrequest_out (pc_bus_sdram_waitrequest), 87 | 88 | .addr_out (burst_converted_address), 89 | .write_out (burst_converted_write), 90 | .writedata_out (burst_converted_writedata), 91 | .read_out (burst_converted_read), 92 | .readdata_in (burst_converted_readdata), 93 | .readdatavalid_in (burst_converted_readdatavalid), 94 | .byteenable_out (burst_converted_byteenable), 95 | .waitrequest_in (burst_converted_waitrequest) 96 | ); 97 | 98 | assign sdram_address = (~ao486_rst) ? burst_converted_address[26:2] : driver_sd_avm_address[26:2]; 99 | assign sdram_byteenable = (~ao486_rst) ? burst_converted_byteenable : 4'b1111; 100 | assign sdram_read = (~ao486_rst) ? burst_converted_read : (driver_sd_avm_read && driver_sd_avm_address[27]); 101 | assign sdram_write = (~ao486_rst) ? burst_converted_write : (driver_sd_avm_write && driver_sd_avm_address[27]); 102 | assign sdram_writedata = (~ao486_rst) ? burst_converted_writedata : driver_sd_avm_writedata; 103 | 104 | assign burst_converted_readdata = (~ao486_rst) ? sdram_readdata : 0; 105 | assign burst_converted_readdatavalid = (~ao486_rst) ? sdram_readdatavalid : 0; 106 | assign burst_converted_waitrequest = (~ao486_rst) ? sdram_waitrequest : 0; 107 | 108 | assign driver_sd_avm_readdata = (ao486_rst) ? sdram_readdata : 0; 109 | assign driver_sd_avm_readdatavalid = (ao486_rst) ? sdram_readdatavalid : 0; 110 | assign driver_sd_avm_waitrequest = (ao486_rst) ? sdram_waitrequest : 0; 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /fpga/de2-115/project/project.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 14.1.0 Build 186 12/03/2014 SJ Web Edition 22 | # Date created = 21:35:21 October 27, 2015 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "14.1" 27 | DATE = "21:35:21 October 27, 2015" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "project" 32 | -------------------------------------------------------------------------------- /fpga/de2-115/project/project.sdc: -------------------------------------------------------------------------------- 1 | ## Generated SDC file "project.out.sdc" 2 | 3 | ## Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 4 | ## Your use of Altera Corporation's design tools, logic functions 5 | ## and other software and tools, and its AMPP partner logic 6 | ## functions, and any output files from any of the foregoing 7 | ## (including device programming or simulation files), and any 8 | ## associated documentation or information are expressly subject 9 | ## to the terms and conditions of the Altera Program License 10 | ## Subscription Agreement, the Altera Quartus II License Agreement, 11 | ## the Altera MegaCore Function License Agreement, or other 12 | ## applicable license agreement, including, without limitation, 13 | ## that your use is for the sole purpose of programming logic 14 | ## devices manufactured by Altera and sold by Altera or its 15 | ## authorized distributors. Please refer to the applicable 16 | ## agreement for further details. 17 | 18 | 19 | ## VENDOR "Altera" 20 | ## PROGRAM "Quartus II" 21 | ## VERSION "Version 14.1.0 Build 186 12/03/2014 SJ Web Edition" 22 | 23 | ## DATE "Wed Oct 28 13:50:15 2015" 24 | 25 | ## 26 | ## DEVICE "EP4CE115F29C7" 27 | ## 28 | 29 | 30 | #************************************************************** 31 | # Time Information 32 | #************************************************************** 33 | 34 | set_time_format -unit ns -decimal_places 3 35 | 36 | 37 | 38 | #************************************************************** 39 | # Create Clock 40 | #************************************************************** 41 | 42 | create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}] 43 | 44 | 45 | #************************************************************** 46 | # Create Generated Clock 47 | #************************************************************** 48 | 49 | derive_pll_clocks 50 | 51 | 52 | #************************************************************** 53 | # Set Clock Latency 54 | #************************************************************** 55 | 56 | 57 | 58 | #************************************************************** 59 | # Set Clock Uncertainty 60 | #************************************************************** 61 | 62 | derive_clock_uncertainty 63 | 64 | 65 | #************************************************************** 66 | # Set Input Delay 67 | #************************************************************** 68 | 69 | 70 | 71 | #************************************************************** 72 | # Set Output Delay 73 | #************************************************************** 74 | 75 | 76 | 77 | #************************************************************** 78 | # Set Clock Groups 79 | #************************************************************** 80 | 81 | 82 | 83 | #************************************************************** 84 | # Set False Path 85 | #************************************************************** 86 | 87 | set_false_path -from [get_clocks {gen|clkgen|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {gen|clkgen|altpll_component|auto_generated|pll1|clk[1]}] 88 | set_false_path -from [get_clocks {gen|clkgen|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {gen|clkgen|altpll_component|auto_generated|pll1|clk[0]}] 89 | 90 | 91 | #************************************************************** 92 | # Set Multicycle Path 93 | #************************************************************** 94 | 95 | 96 | 97 | #************************************************************** 98 | # Set Maximum Delay 99 | #************************************************************** 100 | 101 | 102 | 103 | #************************************************************** 104 | # Set Minimum Delay 105 | #************************************************************** 106 | 107 | 108 | 109 | #************************************************************** 110 | # Set Input Transition 111 | #************************************************************** 112 | -------------------------------------------------------------------------------- /fpga/de2-115/rtl/clock/clk_wiz_0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /fpga/de2-115/rtl/clock/clk_wiz_0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "14.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_wiz_0.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_wiz_0_bb.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_wiz_0.ppf"] 7 | -------------------------------------------------------------------------------- /fpga/de2-115/rtl/clock/clock.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Labolatory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module GEN( input wire CLK_IN, 28 | input wire RST_X_IN, 29 | output wire CLK_OUT, 30 | output wire VGA_CLK_OUT, 31 | output wire RST_X_OUT 32 | ); 33 | 34 | wire LOCKED, VLOCKED, CLK_IBUF; 35 | wire RST_X_BUF; 36 | 37 | clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED); 38 | RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT); 39 | endmodule 40 | 41 | module RSTGEN(CLK, RST_X_I, RST_X_O); 42 | input CLK, RST_X_I; 43 | output RST_X_O; 44 | 45 | reg [7:0] cnt; 46 | assign RST_X_O = cnt[7]; 47 | 48 | always @(posedge CLK or negedge RST_X_I) begin 49 | if (!RST_X_I) cnt <= 0; 50 | else if (~RST_X_O) cnt <= (cnt + 1'b1); 51 | end 52 | endmodule 53 | -------------------------------------------------------------------------------- /fpga/de2-115/rtl/soc.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | `default_nettype wire 28 | 29 | `define SYSTEM_DE2_115 30 | 31 | module Frix( 32 | input wire CLOCK_50, 33 | 34 | // KEY 35 | input wire [3:0] KEY, 36 | 37 | // SDRAM 38 | output wire [12:0] DRAM_ADDR, 39 | output wire [1:0] DRAM_BA, 40 | output wire DRAM_CAS_N, 41 | output wire DRAM_CKE, 42 | output wire DRAM_CLK, 43 | output wire DRAM_CS_N, 44 | inout wire [31:0] DRAM_DQ, 45 | output wire [3:0] DRAM_DQM, 46 | output wire DRAM_RAS_N, 47 | output wire DRAM_WE_N, 48 | 49 | 50 | // PS2 KEYBOARD 51 | inout wire PS2_CLK, 52 | inout wire PS2_DAT, 53 | 54 | // SD 55 | output wire SD_CLK, 56 | inout wire SD_CMD, 57 | inout wire [3:0] SD_DAT, 58 | input wire SD_WP_N, 59 | 60 | // VGA 61 | output wire VGA_CLK, 62 | output wire VGA_SYNC_N, 63 | output wire VGA_BLANK_N, 64 | output wire VGA_HS, 65 | output wire VGA_VS, 66 | 67 | output wire [7:0] VGA_R, 68 | output wire [7:0] VGA_G, 69 | output wire [7:0] VGA_B, 70 | 71 | // LED 72 | output reg [17:0] LEDR, 73 | output reg [ 8:0] LEDG 74 | ); 75 | 76 | 77 | //------------------------------------------------------------------------------ 78 | 79 | wire clk_sys; 80 | wire clk_vga; 81 | wire clk_sound; 82 | 83 | wire rst; 84 | wire rst_n; 85 | 86 | wire RST_X_IN; 87 | 88 | assign RST_X_IN = KEY[3]; 89 | assign DRAM_CLK = clk_sys; 90 | 91 | GEN gen( 92 | .CLK_IN (CLOCK_50), 93 | .RST_X_IN (RST_X_IN), 94 | .CLK_OUT (clk_sys), 95 | .VGA_CLK_OUT (clk_vga), 96 | .RST_X_OUT (rst_n) 97 | ); 98 | 99 | assign rst = ~rst_n; 100 | 101 | //------------------------------------------------------------------------------ 102 | 103 | wire ao486_reset; 104 | 105 | //------------------------------------------------------------------------------ 106 | 107 | wire cache_waitrequest; 108 | 109 | reg [25:0] cnt; 110 | 111 | always @(posedge clk_sys) cnt <= cnt + 1; 112 | 113 | always @(posedge clk_sys) begin 114 | LEDG[0] <= cnt[25]; 115 | LEDG[1] <= ~rst; 116 | LEDG[2] <= ~ao486_reset; 117 | LEDG[3] <= ~SD_WP_N; 118 | LEDG[5:4] <= {~PS2_CLK, ~PS2_DAT}; 119 | LEDG[8:6] <= {~SD_DAT[1:0], ~SD_CMD}; 120 | LEDR[17:0] <= {DRAM_ADDR[11:0], DRAM_BA, DRAM_CAS_N, DRAM_CKE, DRAM_CS_N}; 121 | end 122 | 123 | //------------------------------------------------------------------------------ 124 | 125 | system u0( 126 | .clk_sys (clk_sys), 127 | .reset_sys (rst), 128 | 129 | .clk_vga (clk_vga), 130 | .reset_vga (rst), 131 | 132 | .vga_clock (VGA_CLK), 133 | .vga_sync_n (VGA_SYNC_N), 134 | .vga_blank_n (VGA_BLANK_N), 135 | .vga_horiz_sync (VGA_HS), 136 | .vga_vert_sync (VGA_VS), 137 | .vga_r (VGA_R), 138 | .vga_g (VGA_G), 139 | .vga_b (VGA_B), 140 | 141 | .sdram_addr (DRAM_ADDR), 142 | .sdram_ba (DRAM_BA), 143 | .sdram_cas_n (DRAM_CAS_N), 144 | .sdram_cke (DRAM_CKE), 145 | .sdram_cs_n (DRAM_CS_N), 146 | .sdram_dq (DRAM_DQ), 147 | .sdram_dqm (DRAM_DQM), 148 | .sdram_ras_n (DRAM_RAS_N), 149 | .sdram_we_n (DRAM_WE_N), 150 | 151 | .sd_clk (SD_CLK), 152 | .sd_dat (SD_DAT), 153 | .sd_cmd (SD_CMD), 154 | 155 | .ps2_kbclk (PS2_CLK), 156 | .ps2_kbdat (PS2_DAT), 157 | 158 | .reset_only_ao486 (ao486_reset) 159 | ); 160 | 161 | endmodule 162 | -------------------------------------------------------------------------------- /fpga/nexys4/rtl/clock/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | // file: clk_wiz_0.v 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // CLK_OUT1____50.000______0.000______50.0______151.636_____98.575 59 | // CLK_OUT2____25.000______0.000______50.0______175.402_____98.575 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 69 | 70 | module clk_wiz_0 71 | ( 72 | // Clock in ports 73 | input clk_in1, 74 | // Clock out ports 75 | output clk_out1, 76 | output clk_out2, 77 | // Status and control signals 78 | output locked 79 | ); 80 | 81 | clk_wiz_0_clk_wiz inst 82 | ( 83 | // Clock in ports 84 | .clk_in1(clk_in1), 85 | // Clock out ports 86 | .clk_out1(clk_out1), 87 | .clk_out2(clk_out2), 88 | // Status and control signals 89 | .locked(locked) 90 | ); 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /fpga/nexys4/rtl/clock/clk_wiz_0_clk_wiz.v: -------------------------------------------------------------------------------- 1 | // file: clk_wiz_0.v 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // CLK_OUT1____50.000______0.000______50.0______151.636_____98.575 59 | // CLK_OUT2____25.000______0.000______50.0______175.402_____98.575 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | module clk_wiz_0_clk_wiz 69 | (// Clock in ports 70 | input clk_in1, 71 | // Clock out ports 72 | output clk_out1, 73 | output clk_out2, 74 | // Status and control signals 75 | output locked 76 | ); 77 | 78 | // Input buffering 79 | //------------------------------------ 80 | IBUF clkin1_ibufg 81 | (.O (clk_in1_clk_wiz_0), 82 | .I (clk_in1)); 83 | 84 | 85 | 86 | // Clocking PRIMITIVE 87 | //------------------------------------ 88 | // Instantiation of the MMCM PRIMITIVE 89 | // * Unused inputs are tied off 90 | // * Unused outputs are labeled unused 91 | wire [15:0] do_unused; 92 | wire drdy_unused; 93 | wire psdone_unused; 94 | wire locked_int; 95 | wire clkfbout_clk_wiz_0; 96 | wire clkfbout_buf_clk_wiz_0; 97 | wire clkfboutb_unused; 98 | wire clkout0b_unused; 99 | wire clkout1b_unused; 100 | wire clkout2_unused; 101 | wire clkout2b_unused; 102 | wire clkout3_unused; 103 | wire clkout3b_unused; 104 | wire clkout4_unused; 105 | wire clkout5_unused; 106 | wire clkout6_unused; 107 | wire clkfbstopped_unused; 108 | wire clkinstopped_unused; 109 | 110 | MMCME2_ADV 111 | #(.BANDWIDTH ("OPTIMIZED"), 112 | .CLKOUT4_CASCADE ("FALSE"), 113 | .COMPENSATION ("ZHOLD"), 114 | .STARTUP_WAIT ("FALSE"), 115 | .DIVCLK_DIVIDE (1), 116 | .CLKFBOUT_MULT_F (8.000), 117 | .CLKFBOUT_PHASE (0.000), 118 | .CLKFBOUT_USE_FINE_PS ("FALSE"), 119 | .CLKOUT0_DIVIDE_F (20.000), 120 | .CLKOUT0_PHASE (0.000), 121 | .CLKOUT0_DUTY_CYCLE (0.500), 122 | .CLKOUT0_USE_FINE_PS ("FALSE"), 123 | .CLKOUT1_DIVIDE (40), 124 | .CLKOUT1_PHASE (0.000), 125 | .CLKOUT1_DUTY_CYCLE (0.500), 126 | .CLKOUT1_USE_FINE_PS ("FALSE"), 127 | .CLKIN1_PERIOD (10.0), 128 | .REF_JITTER1 (0.010)) 129 | mmcm_adv_inst 130 | // Output clocks 131 | ( 132 | .CLKFBOUT (clkfbout_clk_wiz_0), 133 | .CLKFBOUTB (clkfboutb_unused), 134 | .CLKOUT0 (clk_out1_clk_wiz_0), 135 | .CLKOUT0B (clkout0b_unused), 136 | .CLKOUT1 (clk_out2_clk_wiz_0), 137 | .CLKOUT1B (clkout1b_unused), 138 | .CLKOUT2 (clkout2_unused), 139 | .CLKOUT2B (clkout2b_unused), 140 | .CLKOUT3 (clkout3_unused), 141 | .CLKOUT3B (clkout3b_unused), 142 | .CLKOUT4 (clkout4_unused), 143 | .CLKOUT5 (clkout5_unused), 144 | .CLKOUT6 (clkout6_unused), 145 | // Input clock control 146 | .CLKFBIN (clkfbout_buf_clk_wiz_0), 147 | .CLKIN1 (clk_in1_clk_wiz_0), 148 | .CLKIN2 (1'b0), 149 | // Tied to always select the primary input clock 150 | .CLKINSEL (1'b1), 151 | // Ports for dynamic reconfiguration 152 | .DADDR (7'h0), 153 | .DCLK (1'b0), 154 | .DEN (1'b0), 155 | .DI (16'h0), 156 | .DO (do_unused), 157 | .DRDY (drdy_unused), 158 | .DWE (1'b0), 159 | // Ports for dynamic phase shift 160 | .PSCLK (1'b0), 161 | .PSEN (1'b0), 162 | .PSINCDEC (1'b0), 163 | .PSDONE (psdone_unused), 164 | // Other control and status signals 165 | .LOCKED (locked_int), 166 | .CLKINSTOPPED (clkinstopped_unused), 167 | .CLKFBSTOPPED (clkfbstopped_unused), 168 | .PWRDWN (1'b0), 169 | .RST (1'b0)); 170 | 171 | 172 | assign locked = locked_int; 173 | 174 | // Output buffering 175 | //----------------------------------- 176 | 177 | BUFG clkf_buf 178 | (.O (clkfbout_buf_clk_wiz_0), 179 | .I (clkfbout_clk_wiz_0)); 180 | 181 | 182 | 183 | BUFG clkout1_buf 184 | (.O (clk_out1), 185 | .I (clk_out1_clk_wiz_0)); 186 | 187 | 188 | BUFG clkout2_buf 189 | (.O (clk_out2), 190 | .I (clk_out2_clk_wiz_0)); 191 | 192 | 193 | 194 | endmodule 195 | -------------------------------------------------------------------------------- /fpga/nexys4/rtl/clock/clock.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Labolatory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | module GEN( input wire CLK_IN, 28 | input wire RST_X_IN, 29 | output wire CLK_OUT, 30 | output wire VGA_CLK_OUT, 31 | output wire RST_X_OUT 32 | ); 33 | 34 | wire LOCKED, VLOCKED, CLK_IBUF; 35 | wire RST_X_BUF; 36 | 37 | clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED); 38 | RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT); 39 | endmodule 40 | 41 | module RSTGEN(CLK, RST_X_I, RST_X_O); 42 | input CLK, RST_X_I; 43 | output RST_X_O; 44 | 45 | reg [23:0] cnt; 46 | assign RST_X_O = cnt[23]; 47 | 48 | always @(posedge CLK or negedge RST_X_I) begin 49 | if (!RST_X_I) cnt <= 0; 50 | else if (~RST_X_O) cnt <= (cnt + 1'b1); 51 | end 52 | endmodule 53 | -------------------------------------------------------------------------------- /fpga/nexys4/rtl/soc.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Arch Laboratory 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | */ 26 | 27 | `default_nettype wire 28 | 29 | module Frix( 30 | input wire CLOCK_100, 31 | input wire RST_IN, 32 | 33 | // PSRAM 34 | output wire PSRAM_CLK, 35 | output wire PSRAM_ADV_N, 36 | output wire PSRAM_CE_N, 37 | output wire PSRAM_OE_N, 38 | output wire PSRAM_WE_N, 39 | output wire PSRAM_LB_N, 40 | output wire PSRAM_UB_N, 41 | inout wire [15:0] PSRAM_DATA, 42 | output wire [22:0] PSRAM_ADDR, 43 | 44 | 45 | //PS2 KEYBOARD 46 | inout wire PS2_CLK, 47 | inout wire PS2_DAT, 48 | 49 | //SD 50 | output wire SD_CLK, 51 | inout wire SD_CMD, 52 | inout wire [3:0] SD_DAT, 53 | input wire SD_CD, 54 | output wire SD_RESET, 55 | 56 | //VGA 57 | output wire VGA_HS, 58 | output wire VGA_VS, 59 | 60 | output wire [3:0] VGA_R, 61 | output wire [3:0] VGA_G, 62 | output wire [3:0] VGA_B, 63 | 64 | //LED 65 | output reg [15:0] LED 66 | ); 67 | 68 | //------------------------------------------------------------------------------ 69 | 70 | wire clk_sys; 71 | wire clk_vga; 72 | wire clk_sound; 73 | 74 | wire rst; 75 | wire rst_n; 76 | 77 | assign DRAM_CLK = clk_sys; 78 | 79 | GEN gen( 80 | .CLK_IN (CLOCK_100), 81 | .RST_X_IN (~RST_IN), 82 | .CLK_OUT (clk_sys), 83 | .VGA_CLK_OUT (clk_vga), 84 | .RST_X_OUT (rst_n) 85 | ); 86 | 87 | assign SD_RESET = rst; 88 | 89 | assign rst = ~rst_n; 90 | 91 | //------------------------------------------------------------------------------ 92 | 93 | wire ao486_reset; 94 | 95 | wire [7:0] VGA_R_8, VGA_G_8, VGA_B_8; 96 | assign VGA_R = VGA_R_8[7:4]; 97 | assign VGA_G = VGA_G_8[7:4]; 98 | assign VGA_B = VGA_B_8[7:4]; 99 | 100 | //------------------------------------------------------------------------------ 101 | 102 | reg [25:0] cnt; 103 | 104 | always @(posedge clk_sys) cnt <= cnt + 1; 105 | 106 | always @(posedge clk_sys) begin 107 | LED[0] <= cnt[25]; 108 | LED[1] <= ~rst; 109 | LED[2] <= ~ao486_reset; 110 | LED[3] <= ~SD_CD; 111 | LED[4] <= ~SD_RESET; 112 | LED[9:5] <= {~SD_CMD, ~SD_DAT}; 113 | LED[13:10] <= {~PSRAM_CE_N, ~PSRAM_OE_N, ~PSRAM_WE_N, ~PSRAM_ADV_N}; 114 | LED[15:14] <= {~PS2_CLK, ~PS2_DAT}; 115 | end 116 | 117 | //------------------------------------------------------------------------------ 118 | 119 | system u0( 120 | .clk_sys (clk_sys), 121 | .reset_sys (rst), 122 | 123 | .clk_vga (clk_vga), 124 | .reset_vga (rst), 125 | 126 | .vga_clock (VGA_CLK), 127 | .vga_horiz_sync (VGA_HS), 128 | .vga_vert_sync (VGA_VS), 129 | .vga_r (VGA_R_8), 130 | .vga_g (VGA_G_8), 131 | .vga_b (VGA_B_8), 132 | 133 | .PSRAM_CLK (PSRAM_CLK), 134 | .PSRAM_ADV_N (PSRAM_ADV_N), 135 | .PSRAM_CE_N (PSRAM_CE_N), 136 | .PSRAM_OE_N (PSRAM_OE_N), 137 | .PSRAM_WE_N (PSRAM_WE_N), 138 | .PSRAM_LB_N (PSRAM_LB_N), 139 | .PSRAM_UB_N (PSRAM_UB_N), 140 | .PSRAM_DATA (PSRAM_DATA), 141 | .PSRAM_ADDR (PSRAM_ADDR), 142 | 143 | .sd_clk (SD_CLK), 144 | .sd_dat (SD_DAT), 145 | .sd_cmd (SD_CMD), 146 | 147 | .ps2_kbclk (PS2_CLK), 148 | .ps2_kbdat (PS2_DAT), 149 | 150 | .reset_only_ao486 (ao486_reset) 151 | ); 152 | endmodule 153 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/doc/mig_7series_v2_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.1: 2 | * Version 2.0 (Rev. 3) 3 | * Extended IES and VCS support to Multi-Controller and Multi-Interface designs 4 | * Added Support for Artix XC7A35T and XC7A50T devices (See Xilinx Answer 59632) 5 | * Resolved recustomization and file generation issue (See Xilinx Answer 59714) 6 | * Resolved Vivado not generating correct VHDL template issue(See Xilinx Answer 59515) 7 | * Resolved unability to derive 150MHz input clock frequency issue (See Xilinx Answer 58647) 8 | * Resolved IP generation error message for 8Gb part (See Xilinx Answer 58894) 9 | * Resolved non-ideal RC settings for DIMMs (See Xilinx Answer 57221) 10 | * Resolved timing failures with the VIO/ILA 2.0 cores when using multiple clock domains (See Xilinx Answer 56387) 11 | * Added stand-alone support for XSIM through Vivado (See Xilinx Answer 58668) 12 | * Resolved VCS and IES simulation failures (See Xilinx Answer 58636) 13 | * Resolved RLDRAM3 simulation failures (See Xilinx Answer 58635) 14 | * Resolved RLDRAM3 memory model out of date (See Xilinx Answer 58620) 15 | 16 | 2013.4: 17 | * Version 2.0 (Rev. 2) 18 | * Added OOC support 19 | * Added support for IES and VCS Simulators 20 | 21 | 2013.3: 22 | * Version 2.0 (Rev. 1) 23 | * Added support for ILA 3.0 and VIO 3.0 24 | * Resolved controller hang issues on read-modify-write commands (See Xilinx Answer 54710) 25 | * Resolved Clock Driver Enable settings for RC1 on RDIMM interfaces (See Xilinx Answer 57279) 26 | * Updated Chipscope debug signals for OCLKDELAY calibration (See Xilinx Answer 54918) 27 | * Resolved timing failures with larger SSI devices (See Xilinx Answer 56385) 28 | * Added AXI addressing support over 32 bits for DDR2 and DDR3 29 | * Corrected Chip Select width for single rank RDIMM devices (See Xilinx Answer 57436) 30 | 31 | 2013.2: 32 | * Version 2.0 33 | * 2013.2 software support 34 | * Added support for ILA 2.0 and VIO 2.0 35 | 36 | 2013.1: 37 | * Version 1.9.a 38 | * 2013.1 software support 39 | * Questa SIM 10.1b Support 40 | * Synplify Pro supported version G-2012.09-SP1 41 | * Support of LPDDR2 SDRAM Verilog designs 42 | * System Reset Pin Polarity selection 43 | * Additional clocks selection for AXI interface designs 44 | 45 | (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. 46 | 47 | This file contains confidential and proprietary information 48 | of Xilinx, Inc. and is protected under U.S. and 49 | international copyright and other intellectual property 50 | laws. 51 | 52 | DISCLAIMER 53 | This disclaimer is not a license and does not grant any 54 | rights to the materials distributed herewith. Except as 55 | otherwise provided in a valid license issued to you by 56 | Xilinx, and to the maximum extent permitted by applicable 57 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 58 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 59 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 60 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 61 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 62 | (2) Xilinx shall not be liable (whether in contract or tort, 63 | including negligence, or under any other theory of 64 | liability) for any loss or damage of any kind or nature 65 | related to, arising under or in connection with these 66 | materials, including for any direct, or any indirect, 67 | special, incidental, or consequential loss or damage 68 | (including loss of data, profits, goodwill, or any type of 69 | loss or damage suffered as a result of any action brought 70 | by a third party) even if such damage or loss was 71 | reasonably foreseeable or Xilinx had been advised of the 72 | possibility of the same. 73 | 74 | CRITICAL APPLICATIONS 75 | Xilinx products are not designed or intended to be fail- 76 | safe, or for use in any application requiring fail-safe 77 | performance, such as life-support or safety devices or 78 | systems, Class III medical devices, nuclear facilities, 79 | applications related to the deployment of airbags, or any 80 | other applications that could lead to death, personal 81 | injury, or severe property or environmental damage 82 | (individually and collectively, "Critical 83 | Applications"). Customer assumes the sole risk and 84 | liability of any use of Xilinx products in Critical 85 | Applications, subject only to applicable laws and 86 | regulations governing limitations on product liability. 87 | 88 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 89 | PART OF THIS FILE AT ALL TIMES. 90 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/archlabo/Frix/98204eccf4d785b0057e1db0003610a3967fbd90/fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig.dcp -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig.veo: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : 2.0 53 | // \ \ Application : MIG 54 | // / / Filename : mig.veo 55 | // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:34:47 $ 56 | // \ \ / \ Date Created : Fri Oct 14 2011 57 | // \___\/\___\ 58 | // 59 | // Device : 7 Series 60 | // Design Name : DDR2 SDRAM 61 | // Purpose : Template file containing code that can be used as a model 62 | // for instantiating a CORE Generator module in a HDL design. 63 | // Revision History : 64 | //***************************************************************************** 65 | 66 | // The following must be inserted into your Verilog file for this 67 | // core to be instantiated. Change the instance name and port connections 68 | // (in parentheses) to your own signal names. 69 | 70 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 71 | 72 | mig u_mig ( 73 | 74 | // Memory interface ports 75 | .ddr2_addr (ddr2_addr), // output [12:0] ddr2_addr 76 | .ddr2_ba (ddr2_ba), // output [2:0] ddr2_ba 77 | .ddr2_cas_n (ddr2_cas_n), // output ddr2_cas_n 78 | .ddr2_ck_n (ddr2_ck_n), // output [0:0] ddr2_ck_n 79 | .ddr2_ck_p (ddr2_ck_p), // output [0:0] ddr2_ck_p 80 | .ddr2_cke (ddr2_cke), // output [0:0] ddr2_cke 81 | .ddr2_ras_n (ddr2_ras_n), // output ddr2_ras_n 82 | .ddr2_we_n (ddr2_we_n), // output ddr2_we_n 83 | .ddr2_dq (ddr2_dq), // inout [15:0] ddr2_dq 84 | .ddr2_dqs_n (ddr2_dqs_n), // inout [1:0] ddr2_dqs_n 85 | .ddr2_dqs_p (ddr2_dqs_p), // inout [1:0] ddr2_dqs_p 86 | .init_calib_complete (init_calib_complete), // output init_calib_complete 87 | 88 | .ddr2_cs_n (ddr2_cs_n), // output [0:0] ddr2_cs_n 89 | .ddr2_dm (ddr2_dm), // output [1:0] ddr2_dm 90 | .ddr2_odt (ddr2_odt), // output [0:0] ddr2_odt 91 | // Application interface ports 92 | .app_addr (app_addr), // input [26:0] app_addr 93 | .app_cmd (app_cmd), // input [2:0] app_cmd 94 | .app_en (app_en), // input app_en 95 | .app_wdf_data (app_wdf_data), // input [127:0] app_wdf_data 96 | .app_wdf_end (app_wdf_end), // input app_wdf_end 97 | .app_wdf_wren (app_wdf_wren), // input app_wdf_wren 98 | .app_rd_data (app_rd_data), // output [127:0] app_rd_data 99 | .app_rd_data_end (app_rd_data_end), // output app_rd_data_end 100 | .app_rd_data_valid (app_rd_data_valid), // output app_rd_data_valid 101 | .app_rdy (app_rdy), // output app_rdy 102 | .app_wdf_rdy (app_wdf_rdy), // output app_wdf_rdy 103 | .app_sr_req (app_sr_req), // input app_sr_req 104 | .app_ref_req (app_ref_req), // input app_ref_req 105 | .app_zq_req (app_zq_req), // input app_zq_req 106 | .app_sr_active (app_sr_active), // output app_sr_active 107 | .app_ref_ack (app_ref_ack), // output app_ref_ack 108 | .app_zq_ack (app_zq_ack), // output app_zq_ack 109 | .ui_clk (ui_clk), // output ui_clk 110 | .ui_clk_sync_rst (ui_clk_sync_rst), // output ui_clk_sync_rst 111 | 112 | .app_wdf_mask (app_wdf_mask), // input [15:0] app_wdf_mask 113 | 114 | // System Clock Ports 115 | .sys_clk_i (sys_clk_i), 116 | .sys_rst (sys_rst) // input sys_rst 117 | ); 118 | 119 | // INST_TAG_END ------ End INSTANTIATION Template --------- 120 | 121 | // You must compile the wrapper file mig.v when simulating 122 | // the core, mig. When compiling the wrapper file, be sure to 123 | // reference the XilinxCoreLib Verilog simulation library. For detailed 124 | // instructions, please refer to the "CORE Generator Help". 125 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/datasheet.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | Vivado Project Options: 4 | Target Device : xc7a100t-csg324 5 | Speed Grade : -1 6 | HDL : verilog 7 | Synthesis Tool : VIVADO 8 | 9 | MIG Output Options: 10 | Module Name : mig 11 | No of Controllers : 1 12 | Selected Compatible Device(s) : -- 13 | 14 | FPGA Options: 15 | System Clock Type : No Buffer 16 | Reference Clock Type : Use System Clock 17 | Debug Port : OFF 18 | Internal Vref : enabled 19 | IO Power Reduction : ON 20 | XADC instantiation in MIG : Enabled 21 | 22 | Extended FPGA Options: 23 | DCI for DQ,DQS/DQS#,DM : enabled 24 | Internal Termination (HR Banks) : 50 Ohms 25 | 26 | /*******************************************************/ 27 | /* Controller 0 */ 28 | /*******************************************************/ 29 | Controller Options : 30 | Memory : DDR2_SDRAM 31 | Interface : NATIVE 32 | Design Clock Frequency : 5000 ps (200.00 MHz) 33 | Phy to Controller Clock Ratio : 4:1 34 | Input Clock Period : 5000 ps 35 | CLKFBOUT_MULT (PLL) : 4 36 | DIVCLK_DIVIDE (PLL) : 1 37 | VCC_AUX IO : 1.8V 38 | Memory Type : Components 39 | Memory Part : MT47H64M16HR-25E 40 | Equivalent Part(s) : -- 41 | Data Width : 16 42 | ECC : Disabled 43 | Data Mask : enabled 44 | ORDERING : Strict 45 | 46 | AXI Parameters : 47 | Data Width : 128 48 | Arbitration Scheme : RD_PRI_REG 49 | Narrow Burst Support : 1 50 | ID Width : 4 51 | 52 | Memory Options: 53 | Burst Length (MR0[1:0]) : 8 54 | CAS Latency (MR0[6:4]) : 3 55 | Output Drive Strength (MR1[5,1]) : Fullstrength 56 | Controller CS option : Enable 57 | Rtt_NOM - ODT (MR1[9,6,2]) : 50ohms 58 | Memory Address Mapping : ROW_BANK_COLUMN 59 | 60 | 61 | Bank Selections: 62 | 63 | System_Control: 64 | SignalName: sys_rst 65 | PadLocation: No connect Bank: Select Bank 66 | SignalName: init_calib_complete 67 | PadLocation: No connect Bank: Select Bank 68 | SignalName: tg_compare_error 69 | PadLocation: No connect Bank: Select Bank 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/docs/phy_only_support_readme.txt: -------------------------------------------------------------------------------- 1 | This file includes the information about the PHY layer support: 2 | 3 | - Folder "/user_design/rtl/phy" includes the PHY layer 4 | RTL modules. 5 | - The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v) 6 | - PHY modules can be used in any environment by taking the RTL modules 7 | listed in "phy" folder and PHY layer needs to be connected to 8 | the memory controller. 9 | - Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory 10 | Controller Design)" for more details on PHY interface signaling, 11 | parameter(s) and timing information. 12 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/log.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/archlabo/Frix/98204eccf4d785b0057e1db0003610a3967fbd90/fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/log.txt -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/par/example_top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/archlabo/Frix/98204eccf4d785b0057e1db0003610a3967fbd90/fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/par/example_top.xdc -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/par/readme.txt: -------------------------------------------------------------------------------- 1 | Files in PAR folder : 2 | 3 | * "example_top.xdc" file is the constraint file for the design. This is used 4 | by Vivado. It has clock constraints, location constraints, IO standards 5 | and false path/SLICE constraints if any. 6 | 7 | * LTX/probe file is required when programming BIT file to FPGA as it contains 8 | the information of debug signals like signal name and position with respect 9 | to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by 10 | vivado tool and is found in .runs/impl_1/debug_nets.ltx 11 | 12 | 13 | compatible_ucf folder: 14 | 15 | * MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI 16 | (Pin Compatible FPGAs page in GUI). It generates the XDC files for all 17 | the Compatible FPGAs selected in GUI. If you want to switch to any of the 18 | Compatible FPGAs follow the steps mentioned below. 19 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v2_0_afifo.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: afifo.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $ 56 | // \ \ / \ Date Created: Oct 21 2008 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: A generic synchronous fifo. 62 | //Reference: 63 | //Revision History: 1.2 11/8/2010 Removed unused signals. 64 | 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | module mig_7series_v2_0_afifo # 70 | ( 71 | parameter TCQ = 100, 72 | parameter DSIZE = 32, 73 | parameter FIFO_DEPTH = 16, 74 | parameter ASIZE = 4, 75 | parameter SYNC = 1 // only has always '1' logic. 76 | ) 77 | ( 78 | input wr_clk, 79 | input rst, 80 | input wr_en, 81 | input [DSIZE-1:0] wr_data, 82 | input rd_en, 83 | input rd_clk, 84 | output [DSIZE-1:0] rd_data, 85 | output reg full, 86 | output reg empty, 87 | output reg almost_full 88 | ); 89 | 90 | // memory array 91 | reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1]; 92 | 93 | //Read Capture Logic 94 | // if Sync = 1, then no need to remove metastability logic because wrclk = rdclk 95 | reg [ASIZE:0] rd_capture_ptr; 96 | reg [ASIZE:0] pre_rd_capture_gray_ptr; 97 | reg [ASIZE:0] rd_capture_gray_ptr; 98 | 99 | reg [ASIZE:0] wr_capture_ptr; 100 | reg [ASIZE:0] pre_wr_capture_gray_ptr; 101 | reg [ASIZE:0] wr_capture_gray_ptr; 102 | wire [ASIZE:0] buf_avail; 103 | wire [ASIZE:0] buf_filled; 104 | wire [ASIZE-1:0] wr_addr, rd_addr; 105 | wire COutb,COutd; 106 | reg COuta,COutc; 107 | reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp; 108 | integer i,j,k; 109 | 110 | 111 | always @ (rd_ptr) 112 | rd_capture_ptr = rd_ptr; 113 | 114 | 115 | 116 | //capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers 117 | // before do comparison. 118 | 119 | 120 | 121 | always @ (wr_ptr) 122 | wr_capture_ptr = wr_ptr; 123 | 124 | // dualport ram 125 | // Memory (RAM) that holds the contents of the FIFO 126 | 127 | 128 | assign wr_addr = wr_ptr[ASIZE-1:0]; 129 | assign rd_data = mem[rd_addr]; 130 | always @(posedge wr_clk) 131 | begin 132 | if (wr_en && !full) 133 | mem[wr_addr] <= #TCQ wr_data; 134 | 135 | end 136 | 137 | 138 | // Read Side Logic 139 | 140 | 141 | assign rd_addr = rd_ptr_cp[ASIZE-1:0]; 142 | assign rd_strobe = rd_en && !empty; 143 | 144 | integer n; 145 | // change the binary pointer to gray pointer 146 | 147 | 148 | always @(posedge rd_clk) 149 | begin 150 | if (rst) 151 | begin 152 | rd_ptr <= #TCQ 'b0; 153 | rd_ptr_cp <= #TCQ 'b0; 154 | 155 | end 156 | else begin 157 | if (rd_strobe) begin 158 | {COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1; 159 | rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1; 160 | 161 | end 162 | 163 | // change the binary pointer to gray pointer 164 | end 165 | 166 | end 167 | 168 | //generate empty signal 169 | assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr; 170 | 171 | always @ (posedge rd_clk ) 172 | begin 173 | if (rst) 174 | empty <= #TCQ 1'b1; 175 | else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe)) 176 | empty <= #TCQ 1'b1; 177 | else 178 | empty <= #TCQ 1'b0; 179 | end 180 | 181 | 182 | // write side logic; 183 | 184 | reg [ASIZE:0] wbin; 185 | wire [ASIZE:0] wgraynext, wbinnext; 186 | 187 | 188 | 189 | always @(posedge rd_clk) 190 | begin 191 | if (rst) 192 | begin 193 | wr_ptr <= #TCQ 'b0; 194 | end 195 | else begin 196 | if (wr_en) 197 | {COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1; 198 | 199 | // change the binary pointer to gray pointer 200 | end 201 | 202 | end 203 | 204 | 205 | // calculate how many buf still available 206 | //assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr; 207 | assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16; 208 | 209 | 210 | always @ (posedge wr_clk ) 211 | begin 212 | if (rst) 213 | full <= #TCQ 1'b0; 214 | else if ((buf_avail == 0) || (buf_avail == 1 && wr_en)) 215 | full <= #TCQ 1'b1; 216 | else 217 | full <= #TCQ 1'b0; 218 | end 219 | 220 | 221 | always @ (posedge wr_clk ) 222 | begin 223 | if (rst) 224 | almost_full <= #TCQ 1'b0; 225 | else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en)) 226 | almost_full <= #TCQ 1'b1; 227 | else 228 | almost_full <= #TCQ 1'b0; 229 | end 230 | 231 | endmodule 232 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v2_0_data_prbs_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: data_prbs_gen.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module is used LFSR to generate random data for memory 62 | // data write or memory data read comparison.The first data is 63 | // seeded by the input prbs_seed_i which is connected to memory address. 64 | //Reference: 65 | //Revision History: 66 | //***************************************************************************** 67 | 68 | `timescale 1ps/1ps 69 | 70 | module mig_7series_v2_0_data_prbs_gen # 71 | ( 72 | parameter TCQ = 100, 73 | 74 | parameter EYE_TEST = "FALSE", 75 | parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" 76 | parameter SEED_WIDTH = 32 77 | ) 78 | ( 79 | input clk_i, 80 | input clk_en, 81 | input rst_i, 82 | input prbs_seed_init, // when high the prbs_x_seed will be loaded 83 | input [PRBS_WIDTH - 1:0] prbs_seed_i, 84 | 85 | output [PRBS_WIDTH - 1:0] prbs_o // generated address 86 | ); 87 | 88 | reg [PRBS_WIDTH - 1 :0] prbs; 89 | reg [PRBS_WIDTH :1] lfsr_q; 90 | integer i; 91 | 92 | 93 | 94 | always @ (posedge clk_i) 95 | begin 96 | if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up 97 | // if (rst_i ) //reset it to a known good state to prevent it locks up 98 | 99 | begin 100 | lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; 101 | // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 102 | 103 | lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 104 | end 105 | else if (clk_en) begin 106 | 107 | lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; 108 | lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; 109 | lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; 110 | lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; 111 | 112 | lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; 113 | lfsr_q[2] <= #TCQ lfsr_q[1] ; 114 | lfsr_q[1] <= #TCQ lfsr_q[32]; 115 | 116 | 117 | end 118 | end 119 | 120 | always @ (lfsr_q[PRBS_WIDTH:1]) begin 121 | prbs = lfsr_q[PRBS_WIDTH:1]; 122 | end 123 | 124 | assign prbs_o = prbs; 125 | 126 | endmodule 127 | 128 | 129 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v2_0_tg_status.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: tg_status.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. 62 | // Error signal will be asserted if the comparsion is not equal. 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | 70 | module mig_7series_v2_0_tg_status #( 71 | parameter TCQ = 100, 72 | 73 | parameter DWIDTH = 32 74 | ) 75 | ( 76 | 77 | 78 | input clk_i , 79 | input rst_i , 80 | input manual_clear_error, 81 | input data_error_i , 82 | input [DWIDTH-1:0] cmp_data_i, 83 | input [DWIDTH-1:0] rd_data_i , 84 | input [31:0] cmp_addr_i , 85 | input [5:0] cmp_bl_i , 86 | input mcb_cmd_full_i , 87 | input mcb_wr_full_i, 88 | input mcb_rd_empty_i, 89 | output reg [64 + (2*DWIDTH - 1):0] error_status, 90 | output error 91 | ); 92 | 93 | reg data_error_r; 94 | reg error_set; 95 | assign error = error_set; 96 | 97 | always @ (posedge clk_i) 98 | data_error_r <= #TCQ data_error_i; 99 | 100 | always @ (posedge clk_i) 101 | begin 102 | 103 | if (rst_i || manual_clear_error) begin 104 | error_status <= #TCQ 'b0; 105 | error_set <= #TCQ 1'b0; 106 | end 107 | else begin 108 | // latch the first error only 109 | if (data_error_i && ~data_error_r && ~error_set ) begin 110 | error_status[31:0] <= #TCQ cmp_addr_i; 111 | error_status[37:32] <= #TCQ cmp_bl_i; 112 | error_status[40] <= #TCQ mcb_cmd_full_i; 113 | error_status[41] <= #TCQ mcb_wr_full_i; 114 | error_status[42] <= #TCQ mcb_rd_empty_i; 115 | error_set <= #TCQ 1'b1; 116 | error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; 117 | error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; 118 | 119 | end 120 | 121 | error_status[39:38] <= #TCQ 'b0; // reserved 122 | error_status[63:43] <= #TCQ 'b0; // reserved 123 | 124 | 125 | end end 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v2_0_write_data_path.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: write_data_path.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This is top level of write path . 62 | 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | 70 | module mig_7series_v2_0_write_data_path #( 71 | parameter TCQ = 100, 72 | parameter FAMILY = "SPARTAN6", 73 | parameter MEM_TYPE = "DDR3", 74 | 75 | parameter ADDR_WIDTH = 32, 76 | parameter START_ADDR = 32'h00000000, 77 | parameter BL_WIDTH = 6, 78 | parameter nCK_PER_CLK = 4, // DRAM clock : MC clock 79 | parameter MEM_BURST_LEN = 8, 80 | parameter DWIDTH = 32, 81 | parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" 82 | parameter NUM_DQ_PINS = 8, 83 | parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern 84 | 85 | parameter MEM_COL_WIDTH = 10, 86 | parameter EYE_TEST = "FALSE" 87 | 88 | ) 89 | ( 90 | 91 | input clk_i, 92 | input [9:0] rst_i, 93 | output cmd_rdy_o, 94 | input cmd_valid_i, 95 | input cmd_validB_i, 96 | input cmd_validC_i, 97 | input [31:0] prbs_fseed_i, 98 | input [3:0] data_mode_i, 99 | input mem_init_done_i, 100 | input wr_data_mask_gen_i, 101 | // input [31:0] m_addr_i, 102 | 103 | input [31:0] simple_data0 , 104 | input [31:0] simple_data1 , 105 | input [31:0] simple_data2 , 106 | input [31:0] simple_data3 , 107 | input [31:0] simple_data4 , 108 | input [31:0] simple_data5 , 109 | input [31:0] simple_data6 , 110 | input [31:0] simple_data7 , 111 | 112 | input [31:0] fixed_data_i, 113 | input mode_load_i, 114 | 115 | input [31:0] addr_i, 116 | input [BL_WIDTH-1:0] bl_i, 117 | 118 | // input [5:0] port_data_counts_i,// connect to data port fifo counts 119 | input memc_cmd_full_i, 120 | input data_rdy_i, 121 | output data_valid_o, 122 | output last_word_wr_o, 123 | output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, 124 | output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o, 125 | output data_wr_end_o 126 | 127 | ); 128 | 129 | wire data_valid; 130 | reg cmd_rdy; 131 | 132 | assign data_valid_o = data_valid;// & data_rdy_i; 133 | 134 | 135 | mig_7series_v2_0_wr_data_gen # 136 | ( 137 | .TCQ (TCQ), 138 | .FAMILY (FAMILY), 139 | .MEM_TYPE (MEM_TYPE), 140 | .NUM_DQ_PINS (NUM_DQ_PINS), 141 | .MEM_BURST_LEN (MEM_BURST_LEN), 142 | .BL_WIDTH (BL_WIDTH), 143 | .START_ADDR (START_ADDR), 144 | .nCK_PER_CLK (nCK_PER_CLK), 145 | .SEL_VICTIM_LINE (SEL_VICTIM_LINE), 146 | .DATA_PATTERN (DATA_PATTERN), 147 | .DWIDTH (DWIDTH), 148 | .COLUMN_WIDTH (MEM_COL_WIDTH), 149 | .EYE_TEST (EYE_TEST) 150 | 151 | ) 152 | wr_data_gen( 153 | .clk_i (clk_i ), 154 | .rst_i (rst_i[9:5]), 155 | .prbs_fseed_i (prbs_fseed_i), 156 | .wr_data_mask_gen_i (wr_data_mask_gen_i), 157 | .mem_init_done_i (mem_init_done_i), 158 | .data_mode_i (data_mode_i ), 159 | .cmd_rdy_o (cmd_rdy_o ), 160 | .cmd_valid_i (cmd_valid_i ), 161 | .cmd_validB_i (cmd_validB_i ), 162 | .cmd_validC_i (cmd_validC_i ), 163 | 164 | .last_word_o (last_word_wr_o ), 165 | // .port_data_counts_i (port_data_counts_i), 166 | // .m_addr_i (m_addr_i ), 167 | .fixed_data_i (fixed_data_i), 168 | .simple_data0 (simple_data0), 169 | .simple_data1 (simple_data1), 170 | .simple_data2 (simple_data2), 171 | .simple_data3 (simple_data3), 172 | .simple_data4 (simple_data4), 173 | .simple_data5 (simple_data5), 174 | .simple_data6 (simple_data6), 175 | .simple_data7 (simple_data7), 176 | 177 | 178 | .mode_load_i (mode_load_i), 179 | 180 | .addr_i (addr_i ), 181 | .bl_i (bl_i ), 182 | .memc_cmd_full_i (memc_cmd_full_i), 183 | 184 | .data_rdy_i (data_rdy_i ), 185 | .data_valid_o ( data_valid ), 186 | .data_o (data_o ), 187 | .data_wr_end_o (data_wr_end_o), 188 | .data_mask_o (data_mask_o) 189 | ); 190 | 191 | 192 | 193 | endmodule 194 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/sim/ies_run.sh: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2008 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 2.0 53 | ## \ \ Application : MIG 54 | ## / / Filename : ies_run.sh 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ 56 | ## \ \ / \ Date Created : Tue Oct 29 2013 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Purpose : 61 | ## Sample ies_run.sh file to compile and simulate memory interface 62 | ## design and run the simulation for specified period of time. 63 | ## Display the waveforms that are listed with "add wave" command. 64 | ## Assumptions : 65 | ## Simulation takes place in \sim folder of MIG output directory. 66 | ## Reference : 67 | ## Revision History : 68 | ############################################################################### 69 | 70 | #echo Simulation Tool: IES 71 | 72 | #Compile the required libraries here# 73 | #libraries path# 74 | 75 | #Compile all modules# 76 | ncvlog -sv -work worklib -messages ../../../../../imports/rtl/*.v >> ies_sim.log 77 | ncvlog -work worklib -messages -sv ../../../../../imports/rtl/traffic_gen/*.v >> ies_sim.log 78 | ncvlog -sv -work worklib -messages ../../user_design/rtl/mig.v >> ies_sim.log 79 | ncvlog -sv -work worklib -messages ../../user_design/rtl/mig_mig_sim.v >> ies_sim.log 80 | ncvlog -work worklib -messages -sv ../../user_design/rtl/clocking/*.v >> ies_sim.log 81 | ncvlog -work worklib -messages -sv ../../user_design/rtl/controller/*.v >> ies_sim.log 82 | ncvlog -work worklib -messages -sv ../../user_design/rtl/ecc/*.v >> ies_sim.log 83 | ncvlog -work worklib -messages -sv ../../user_design/rtl/ip_top/*.v >> ies_sim.log 84 | ncvlog -work worklib -messages -sv ../../user_design/rtl/phy/*.v >> ies_sim.log 85 | ncvlog -work worklib -messages -sv ../../user_design/rtl/ui/*.v >> ies_sim.log 86 | 87 | 88 | 89 | #Compile files in sim folder (excluding model parameter file)# 90 | #$XILINX variable must be set 91 | ncvlog -work worklib -messages $XILINX_VIVADO/data/verilog/src/glbl.v >> ies_sim.log 92 | ncvlog -work worklib -messages ../../../../../../sim_1/imports/sim/wiredly.v >> ies_sim.log 93 | ncvlog -work worklib -messages ../../../../../../sim_1/imports/sim/sim_tb_top.v >> ies_sim.log 94 | 95 | #Pass the parameters for memory model parameter file# 96 | ncvlog -work worklib -messages -sv +define+x1Gb +define+sg25E +define+x16 ../../../../../../sim_1/imports/sim/ddr2_model.v >> ies_sim.log 97 | 98 | #Simulate the design with sim_tb_top as the top module 99 | ncelab -timescale '1ps/1ps' -vhdlsync -v93 -messages -nettype_port_relax -access +rwc sim_tb_top glbl >> ies_sim.log 100 | ncsim sim_tb_top >> ies_sim.log 101 | #echo done 102 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/sim/readme.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 2.0 53 | ## \ \ Application : MIG 54 | ## / / Filename : readme.txt 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | ## \ \ / \ Date Created : Fri Oct 14 2011 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Design Name : DDR2 SDRAM 61 | ## Purpose : Steps to run simulations using Modelsim, Cadence IES, and 62 | ## Synopsys VCS 63 | ## Assumptions : Simulations are run in \sim folder of MIG output "Open IP 64 | ## Example Design" directory 65 | ## Reference : 66 | ## Revision History: 67 | ############################################################################### 68 | 69 | MIG outputs script files required to run the simulations for Modelsim, IES and 70 | VCS. These scripts are valid only for running simulations for 71 | "Open IP Example Design" 72 | 73 | 1. How to run simulations in Modelsim simulator 74 | 75 | A) sim.do File : 76 | 77 | a) The 'sim.do' file has commands to compile and simulate memory 78 | interface design and run the simulation for specified period of time. 79 | 80 | b) It has the syntax to Map the required libraries (unisims_ver, 81 | unisim and secureip). The libraries should be mapped using 82 | the following command 83 | vmap unisims_ver 84 | vmap unisim 85 | vmap secureip 86 | 87 | Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file 88 | 89 | c) Displays the waveforms that are listed with "add wave" command. 90 | 91 | B) Steps to run the Modelsim simulation: 92 | 93 | a) The user should invoke the Modelsim simulator GUI. 94 | 95 | b) Change the present working directory path to the sim folder. 96 | In Transcript window, at Modelsim prompt, type the following command to 97 | change directory path. 98 | cd 99 | 100 | c) Run the simulation using sim.do file. 101 | At Modelsim prompt, type the following command: 102 | do sim.do 103 | 104 | d) To exit simulation, type the following command at Modelsim prompt: 105 | quit -f 106 | 107 | e) Verify the transcript file for the memory transactions. 108 | 109 | 2. How to run Cadence IES Simulations 110 | 111 | A) Following files are provided : 112 | 113 | a) The "ies_run.sh" file contains the commands for simulation of the 114 | hdl files. 115 | 116 | b) Libraries must be added to the "ies_run.sh" file before running 117 | simulations. Following lines must be added to the file, just below the 118 | comment line #libraries path# 119 | 120 | ncvlog -work worklib -messages $XILINX_VIVADO/data/verilog/src/unisims/*.v >> ies_sim.log 121 | ncvlog -work worklib -messages $XILINX_VIVADO/data/verilog/src/retarget/*.v >> ies_sim.log 122 | ncvlog -work worklib -messages -file $XILINX_VIVADO/data/secureip/secureip_cell.list.f >> ies_sim.log 123 | 124 | Also, $XILINX_VIVADO environment variable must be set in order to 125 | compile glbl.v file and the above mentioned library files 126 | 127 | B) Steps to run the IES simulation: 128 | 129 | a) Change the present working directory path to the sim folder of "Open 130 | IP Example Design" path in the OS terminal. 131 | 132 | b) Run the simulation using ies_run.sh file. Type the following command: 133 | ./ies_run.sh 134 | 135 | c) Verify the ies_sim.log file for the memory transactions. 136 | 137 | 3. How to run Synopsys VCS Simulations 138 | 139 | A) Following files are provided : 140 | 141 | a) The "vcs_run.sh" file contains the commands for simulation of hdl files. 142 | 143 | b) Libraries must be added to the "vcs_run.sh" file before running 144 | simulations. Following lines must be added to the file, just below the 145 | comment line #libraries path# 146 | 147 | vlogan $XILINX_VIVADO/data/verilog/src/unisims/*.v >> vcs_sim.log 148 | vlogan $XILINX_VIVADO/data/verilog/src/retarget/*.v >> vcs_sim.log 149 | vlogan -f $XILINX_VIVADO/data/secureip/secureip_cell.list.f >> vcs_sim.log 150 | 151 | Also, $XILINX_VIVADO environment variable must be set in order to 152 | compile glbl.v file and the above mentioned library files 153 | 154 | B) Steps to run the VCS simulation: 155 | 156 | a) Change the present working directory path to the sim folder of "Open 157 | IP Example Design" path in the OS terminal. 158 | 159 | b) Run the simulation using vcs_run.sh file. Type the following command: 160 | ./vcs_run.sh 161 | 162 | c) Verify the vcs_sim.log file for the memory transactions. 163 | 164 | 4. SIM_BYPASS_INIT_CAL parameter value of SKIP, skips memory initialization sequence 165 | and calibration sequence. This could lead to simulation errors since design is not 166 | calibrated at all. Preferred values for parameter SIM_BYPASS_INIT_CAL to run 167 | simulations are FAST and OFF. 168 | 169 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/sim/sim.do: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2008 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 2.0 53 | ## \ \ Application : MIG 54 | ## / / Filename : sim.do 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ 56 | ## \ \ / \ Date Created : Fri Oct 14 2011 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Purpose : 61 | ## Sample sim .do file to compile and simulate memory interface 62 | ## design and run the simulation for specified period of time. 63 | ## Display the waveforms that are listed with "add wave" command. 64 | ## Assumptions : 65 | ## Simulation takes place in \sim folder of MIG output directory. 66 | ## Reference : 67 | ## Revision History : 68 | ############################################################################### 69 | 70 | #This design is simulated with ModelSim 6.6d version 71 | 72 | vlib work 73 | 74 | #Map the required libraries here# 75 | #vmap unisims_ver 76 | #vmap unisim 77 | #vmap secureip 78 | 79 | #Compile all modules# 80 | vlog ../../../../../imports/rtl/*.v 81 | vlog -incr ../../../../../imports/rtl/traffic_gen/*.v 82 | vlog ../../user_design/rtl/mig.v 83 | vlog ../../user_design/rtl/mig_mig_sim.v 84 | vlog -incr ../../user_design/rtl/clocking/*.v 85 | vlog -incr ../../user_design/rtl/controller/*.v 86 | vlog -incr ../../user_design/rtl/ecc/*.v 87 | vlog -incr ../../user_design/rtl/ip_top/*.v 88 | vlog -incr ../../user_design/rtl/phy/*.v 89 | vlog -incr ../../user_design/rtl/ui/*.v 90 | 91 | 92 | #Compile files in sim folder (excluding model parameter file)# 93 | #$XILINX variable must be set 94 | vlog -incr $env(XILINX_VIVADO)/data/verilog/src/glbl.v 95 | vlog -incr ../../../../../../sim_1/imports/sim/wiredly.v 96 | vlog -incr ../../../../../../sim_1/imports/sim/sim_tb_top.v 97 | 98 | #Pass the parameters for memory model parameter file# 99 | vlog -incr +incdir+../../../../../../sim_1/imports/sim +define+x1Gb +define+sg25E +define+x16 ../../../../../../sim_1/imports/sim/ddr2_model.v 100 | 101 | #Load the design. Use required libraries.# 102 | vsim -t fs -novopt +notimingchecks -L unisims_ver -L secureip work.sim_tb_top glbl 103 | 104 | onerror {resume} 105 | #Log all the objects in design. These will appear in .wlf file# 106 | #This helps in viewing all signals of the design instead of 107 | #re-running the simulation for viewing the signals. 108 | #Uncomment below line to log all objects in the design. 109 | #log -r /* 110 | 111 | #View sim_tb_top signals in waveform# 112 | add wave sim:/sim_tb_top/* 113 | #Change radix to Hexadecimal# 114 | radix hex 115 | #Supress Numeric Std package and Arith package warnings.# 116 | #For VHDL designs we get some warnings due to unknown values on some signals at startup# 117 | # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0# 118 | #We may also get some Arithmetic packeage warnings because of unknown values on# 119 | #some of the signals that are used in an Arithmetic operation.# 120 | #In order to suppress these warnings, we use following two commands# 121 | set NumericStdNoWarnings 1 122 | set StdArithNoWarnings 1 123 | 124 | # Choose simulation run time by inserting a breakpoint and then run for specified # 125 | # period. For more details, refer to user guide (UG586).# 126 | # Status reporting logic exists both in simulation test bench (sim_tb_top) 127 | # and sim.do file for ModelSim. Any update in simulation run time or time out 128 | # in this file need to be updated in sim_tb_top file as well. 129 | when {/sim_tb_top/init_calib_complete = 1} { 130 | if {[when -label a_100] == ""} { 131 | when -label a_100 { $now = 50 us } { 132 | nowhen a_100 133 | report simulator control 134 | report simulator state 135 | if {[examine /sim_tb_top/tg_compare_error] == 0} { 136 | echo "TEST PASSED" 137 | stop 138 | } 139 | if {[examine /sim_tb_top/tg_compare_error] != 0} { 140 | echo "TEST FAILED: DATA ERROR" 141 | stop 142 | } 143 | } 144 | } 145 | } 146 | 147 | #In case calibration fails to complete, choose the run time and then stop# 148 | when {$now = @1000 us and /sim_tb_top/init_calib_complete != 1} { 149 | echo "TEST FAILED: CALIBRATION DID NOT COMPLETE" 150 | stop 151 | } 152 | 153 | run -all 154 | stop 155 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/sim/vcs_run.sh: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2008 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 2.0 53 | ## \ \ Application : MIG 54 | ## / / Filename : vcs_run.sh 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ 56 | ## \ \ / \ Date Created : Tue Oct 29 2013 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Purpose : 61 | ## Sample vcs_run.sh file to compile and simulate memory interface 62 | ## design and run the simulation for specified period of time. 63 | ## Display the waveforms that are listed with "add wave" command. 64 | ## Assumptions : 65 | ## Simulation takes place in \sim folder of MIG output directory. 66 | ## Reference : 67 | ## Revision History : 68 | ############################################################################### 69 | 70 | #echo Simulation Tool: VCS 71 | #Compile the required libraries here# 72 | #libraries path# 73 | 74 | #Compile all modules# 75 | vlogan -sverilog ../../user_design/rtl/mig.v >> vcs_sim.log 76 | vlogan -sverilog ../../user_design/rtl/mig_mig_sim.v >> vcs_sim.log 77 | vlogan -sverilog ../../../../../imports/rtl/*.v >> vcs_sim.log 78 | vlogan -sverilog ../../user_design/rtl/clocking/*.v >> vcs_sim.log 79 | vlogan -sverilog ../../user_design/rtl/controller/*.v >> vcs_sim.log 80 | vlogan -sverilog ../../user_design/rtl/ecc/*.v >> vcs_sim.log 81 | vlogan -sverilog ../../user_design/rtl/ip_top/*.v >> vcs_sim.log 82 | vlogan -sverilog ../../user_design/rtl/phy/*.v >> vcs_sim.log 83 | vlogan -sverilog ../../user_design/rtl/ui/*.v >> vcs_sim.log 84 | vlogan -sverilog ../../../../../imports/rtl/traffic_gen/*.v >> vcs_sim.log 85 | 86 | 87 | 88 | 89 | #Compile files in sim folder (excluding model parameter file)# 90 | #$XILINX variable must be set 91 | vlogan $XILINX_VIVADO/data/verilog/src/glbl.v >> vcs_sim.log 92 | vlogan -sverilog ../../../../../../sim_1/imports/sim/wiredly.v >> vcs_sim.log 93 | vlogan -sverilog ../../../../../../sim_1/imports/sim/sim_tb_top.v >> vcs_sim.log 94 | 95 | #Pass the parameters for memory model parameter file# 96 | vlogan -Xcheck_p1800_2009=char -sverilog +incdir+../../../../../../sim_1/imports/sim/ +define+x1Gb +define+sg25E +define+x16 ../../../../../../sim_1/imports/sim/ddr2_model.v >> vcs_sim.log 97 | 98 | #Simulate the design with sim_tb_top as the top module 99 | vcs -R -debug_pp -lca sim_tb_top glbl >> vcs_sim.log 100 | 101 | #echo done 102 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/sim/wiredly.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : 2.0 53 | // \ \ Application : MIG 54 | // / / Filename : wiredly.v 55 | // /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ 56 | // \ \ / \ Date Created : Fri Oct 14 2011 57 | // \___\/\___\ 58 | // 59 | // Device : 7Series 60 | // Design Name : DDR2 SDRAM 61 | // Purpose : 62 | // This module provide the definition of a zero ohm component (A, B). 63 | // 64 | // The applications of this component include: 65 | // . Normal operation of a jumper wire (data flowing in both directions) 66 | // This can corrupt data from DRAM to FPGA useful for verifying ECC function. 67 | // 68 | // The component consists of 2 ports: 69 | // . Port A: One side of the pass-through switch 70 | // . Port B: The other side of the pass-through switch 71 | 72 | // The model is sensitive to transactions on all ports. Once a transaction 73 | // is detected, all other transactions are ignored for that simulation time 74 | // (i.e. further transactions in that delta time are ignored). 75 | 76 | // Model Limitations and Restrictions: 77 | // Signals asserted on the ports of the error injector should not have 78 | // transactions occuring in multiple delta times because the model 79 | // is sensitive to transactions on port A, B ONLY ONCE during 80 | // a simulation time. Thus, once fired, a process will 81 | // not refire if there are multiple transactions occuring in delta times. 82 | // This condition may occur in gate level simulations with 83 | // ZERO delays because transactions may occur in multiple delta times. 84 | // 85 | // Reference : 86 | // Revision History : 87 | //***************************************************************************** 88 | 89 | `timescale 1ns / 1ps 90 | 91 | module WireDelay # ( 92 | parameter Delay_g = 0, 93 | parameter Delay_rd = 0, 94 | parameter ERR_INSERT = "OFF" 95 | ) 96 | ( 97 | inout A, 98 | inout B, 99 | input reset, 100 | input phy_init_done 101 | ); 102 | 103 | reg A_r; 104 | reg B_r; 105 | reg B_inv ; 106 | reg line_en; 107 | 108 | reg B_nonX; 109 | 110 | assign A = A_r; 111 | assign B = B_r; 112 | 113 | always @ (*) 114 | begin 115 | if (B === 1'bx) 116 | B_nonX <= $random; 117 | else 118 | B_nonX <= B; 119 | end 120 | 121 | always@(*) 122 | begin 123 | if((B_nonX == 'b1) || (B_nonX == 'b0)) 124 | B_inv <= #0 ~B_nonX ; 125 | else 126 | B_inv <= #0 'bz ; 127 | end 128 | 129 | always @(*) begin 130 | if (!reset) begin 131 | A_r <= 1'bz; 132 | B_r <= 1'bz; 133 | line_en <= 1'b0; 134 | end else begin 135 | if (line_en) begin 136 | B_r <= 1'bz; 137 | if ((ERR_INSERT == "ON") & (phy_init_done)) 138 | A_r <= #Delay_rd B_inv; 139 | else 140 | A_r <= #Delay_rd B_nonX; 141 | end else begin 142 | B_r <= #Delay_g A; 143 | A_r <= 1'bz; 144 | end 145 | end 146 | end 147 | 148 | always @(A or B) begin 149 | if (!reset) begin 150 | line_en <= 1'b0; 151 | end else if (A !== A_r) begin 152 | line_en <= 1'b0; 153 | end else if (B_r !== B) begin 154 | line_en <= 1'b1; 155 | end else begin 156 | line_en <= line_en; 157 | end 158 | end 159 | endmodule 160 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/sim/xsim_options.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2012 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 2.0 53 | ## \ \ Application : MIG 54 | ## / / Filename : xsim_options.tcl 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | ## \ \ / \ Date Created : Tue Jun 05 2012 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Design Name : DDR2 SDRAM 61 | ## Purpose : To give commands to XSIM Simulator through batch mode 62 | ## Assumptions: 63 | ## - Simulation takes place in \sim folder of MIG output directory 64 | ## Reference : 65 | ## Revision History: 66 | ############################################################################### 67 | 68 | 69 | add_wave -radix hex /sim_tb_top 70 | run 1000 us 71 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/sim/xsim_run.bat: -------------------------------------------------------------------------------- 1 | ::!/bin/csh -f 2 | ::***************************************************************************** 3 | :: (c) Copyright 2012 Xilinx, Inc. All rights reserved. 4 | :: 5 | :: This file contains confidential and proprietary information 6 | :: of Xilinx, Inc. and is protected under U.S. and 7 | :: international copyright and other intellectual property 8 | :: laws. 9 | :: 10 | :: DISCLAIMER 11 | :: This disclaimer is not a license and does not grant any 12 | :: rights to the materials distributed herewith. Except as 13 | :: otherwise provided in a valid license issued to you by 14 | :: Xilinx, and to the maximum extent permitted by applicable 15 | :: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | :: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | :: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | :: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | :: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | :: (2) Xilinx shall not be liable (whether in contract or tort, 21 | :: including negligence, or under any other theory of 22 | :: liability) for any loss or damage of any kind or nature 23 | :: related to, arising under or in connection with these 24 | :: materials, including for any direct, or any indirect, 25 | :: special, incidental, or consequential loss or damage 26 | :: (including loss of data, profits, goodwill, or any type of 27 | :: loss or damage suffered as a result of any action brought 28 | :: by a third party) even if such damage or loss was 29 | :: reasonably foreseeable or Xilinx had been advised of the 30 | :: possibility of the same. 31 | :: 32 | :: CRITICAL APPLICATIONS 33 | :: Xilinx products are not designed or intended to be fail- 34 | :: safe, or for use in any application requiring fail-safe 35 | :: performance, such as life-support or safety devices or 36 | :: systems, Class III medical devices, nuclear facilities, 37 | :: applications related to the deployment of airbags, or any 38 | :: other applications that could lead to death, personal 39 | :: injury, or severe property or environmental damage 40 | :: (individually and collectively, "Critical 41 | :: Applications"). Customer assumes the sole risk and 42 | :: liability of any use of Xilinx products in Critical 43 | :: Applications, subject only to applicable laws and 44 | :: regulations governing limitations on product liability. 45 | :: 46 | :: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | :: PART OF THIS FILE AT ALL TIMES. 48 | :: 49 | :: **************************************************************************** 50 | :: ____ ____ 51 | :: / /\/ / 52 | :: /___/ \ / Vendor : Xilinx 53 | :: \ \ \/ Version : 2.0 54 | :: \ \ Application : MIG 55 | :: / / Filename : xsim_run.bat 56 | :: /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 57 | :: \ \ / \ Date Created : Tue Jun 05 2012 58 | :: \___\/\___\ 59 | :: 60 | :: Device : 7 Series 61 | :: Design Name : DDR2 SDRAM 62 | :: Purpose : Batch file to run Simulation through Vivado Simulator 63 | :: Reference : 64 | :: Revision History : 65 | :: **************************************************************************** 66 | 67 | 68 | echo Simulation Tool: Viavdo Simulator 69 | call xelab work.sim_tb_top work.glbl -prj xsim_files.prj -L unisims_ver -L secureip -s xsim_test -debug typical 70 | xsim -g -t xsim_options.tcl -wdb xsim_database.wdb xsim_test 71 | echo done 72 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/archlabo/Frix/98204eccf4d785b0057e1db0003610a3967fbd90/fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/constraints/mig_ooc.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/archlabo/Frix/98204eccf4d785b0057e1db0003610a3967fbd90/fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/constraints/mig_ooc.xdc -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/log.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/archlabo/Frix/98204eccf4d785b0057e1db0003610a3967fbd90/fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/log.txt -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v2_0_clk_ibuf.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version:%version 53 | // \ \ Application: MIG 54 | // / / Filename: clk_ibuf.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ 56 | // \ \ / \ Date Created:Mon Aug 3 2009 57 | // \___\/\___\ 58 | // 59 | //Device: Virtex-6 60 | //Design Name: DDR3 SDRAM 61 | //Purpose: 62 | // Clock generation/distribution and reset synchronization 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | `timescale 1ns/1ps 67 | 68 | module mig_7series_v2_0_clk_ibuf # 69 | ( 70 | parameter SYSCLK_TYPE = "DIFFERENTIAL", 71 | // input clock type 72 | parameter DIFF_TERM_SYSCLK = "TRUE" 73 | // Differential Termination 74 | ) 75 | ( 76 | // Clock inputs 77 | input sys_clk_p, // System clock diff input 78 | input sys_clk_n, 79 | input sys_clk_i, 80 | output mmcm_clk 81 | ); 82 | 83 | (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */; 84 | 85 | generate 86 | if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk 87 | 88 | //*********************************************************************** 89 | // Differential input clock input buffers 90 | //*********************************************************************** 91 | 92 | IBUFGDS # 93 | ( 94 | .DIFF_TERM (DIFF_TERM_SYSCLK), 95 | .IBUF_LOW_PWR ("FALSE") 96 | ) 97 | u_ibufg_sys_clk 98 | ( 99 | .I (sys_clk_p), 100 | .IB (sys_clk_n), 101 | .O (sys_clk_ibufg) 102 | ); 103 | 104 | end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk 105 | 106 | //*********************************************************************** 107 | // SINGLE_ENDED input clock input buffers 108 | //*********************************************************************** 109 | 110 | IBUFG # 111 | ( 112 | .IBUF_LOW_PWR ("FALSE") 113 | ) 114 | u_ibufg_sys_clk 115 | ( 116 | .I (sys_clk_i), 117 | .O (sys_clk_ibufg) 118 | ); 119 | end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk 120 | 121 | //*********************************************************************** 122 | // System clock is driven from FPGA internal clock (clock from fabric) 123 | //*********************************************************************** 124 | assign sys_clk_ibufg = sys_clk_i; 125 | end 126 | endgenerate 127 | 128 | assign mmcm_clk = sys_clk_ibufg; 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v2_0_ecc_buf.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : %version 53 | // \ \ Application : MIG 54 | // / / Filename : ecc_buf.v 55 | // /___/ /\ Date Last Modified : $date$ 56 | // \ \ / \ Date Created : Tue Jun 30 2009 57 | // \___\/\___\ 58 | // 59 | //Device : 7-Series 60 | //Design Name : DDR3 SDRAM 61 | //Purpose : 62 | //Reference : 63 | //Revision History : 64 | //***************************************************************************** 65 | 66 | `timescale 1ps/1ps 67 | 68 | module mig_7series_v2_0_ecc_buf 69 | #( 70 | parameter TCQ = 100, 71 | parameter PAYLOAD_WIDTH = 64, 72 | parameter DATA_BUF_ADDR_WIDTH = 4, 73 | parameter DATA_BUF_OFFSET_WIDTH = 1, 74 | parameter DATA_WIDTH = 64, 75 | parameter nCK_PER_CLK = 4 76 | ) 77 | ( 78 | /*AUTOARG*/ 79 | // Outputs 80 | rd_merge_data, 81 | // Inputs 82 | clk, rst, rd_data_addr, rd_data_offset, wr_data_addr, 83 | wr_data_offset, rd_data, wr_ecc_buf 84 | ); 85 | 86 | input clk; 87 | input rst; 88 | 89 | // RMW architecture supports only 16 data buffer entries. 90 | // Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but 91 | // assume the upper bits are used for tagging. 92 | 93 | input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; 94 | input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; 95 | wire [4:0] buf_wr_addr; 96 | 97 | input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; 98 | input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; 99 | reg [4:0] buf_rd_addr_r; 100 | 101 | generate 102 | if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits 103 | always @(posedge clk) 104 | buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset}; 105 | assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset}; 106 | end 107 | else begin : lt_4_addr_bits 108 | always @(posedge clk) 109 | buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}}, 110 | wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0], 111 | wr_data_offset}; 112 | assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}}, 113 | rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0], 114 | rd_data_offset}; 115 | end 116 | endgenerate 117 | 118 | input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; 119 | reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload; 120 | integer h; 121 | always @(/*AS*/rd_data) 122 | for (h=0; h<2*nCK_PER_CLK; h=h+1) 123 | payload[h*DATA_WIDTH+:DATA_WIDTH] = 124 | rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH]; 125 | 126 | input wr_ecc_buf; 127 | localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH; 128 | localparam FULL_RAM_CNT = (BUF_WIDTH/6); 129 | localparam REMAINDER = BUF_WIDTH % 6; 130 | localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); 131 | localparam RAM_WIDTH = (RAM_CNT*6); 132 | wire [RAM_WIDTH-1:0] buf_out_data; 133 | generate 134 | begin : ram_buf 135 | wire [RAM_WIDTH-1:0] buf_in_data; 136 | if (REMAINDER == 0) 137 | assign buf_in_data = payload; 138 | else 139 | assign buf_in_data = {{6-REMAINDER{1'b0}}, payload}; 140 | 141 | genvar i; 142 | for (i=0; i 0) 161 | for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits 162 | always @(/*AS*/ecc_rddata_r) 163 | rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] = 164 | ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH]; 165 | end 166 | endgenerate 167 | 168 | // Generate status information. 169 | input ecc_status_valid; 170 | output wire [2*nCK_PER_CLK-1:0] ecc_single; 171 | output wire [2*nCK_PER_CLK-1:0] ecc_multiple; 172 | genvar v; 173 | generate 174 | for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status 175 | wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; 176 | wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; 177 | assign ecc_single[v] = ecc_status_valid && ~zero && odd; 178 | assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd; 179 | end 180 | endgenerate 181 | 182 | endmodule 183 | -------------------------------------------------------------------------------- /fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v2_0_ecc_merge_enc.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : %version 53 | // \ \ Application : MIG 54 | // / / Filename : ecc_merge_enc.v 55 | // /___/ /\ Date Last Modified : $date$ 56 | // \ \ / \ Date Created : Tue Jun 30 2009 57 | // \___\/\___\ 58 | // 59 | //Device : 7-Series 60 | //Design Name : DDR3 SDRAM 61 | //Purpose : 62 | //Reference : 63 | //Revision History : 64 | //***************************************************************************** 65 | 66 | `timescale 1ps/1ps 67 | 68 | module mig_7series_v2_0_ecc_merge_enc 69 | #( 70 | parameter TCQ = 100, 71 | parameter PAYLOAD_WIDTH = 64, 72 | parameter CODE_WIDTH = 72, 73 | parameter DATA_BUF_ADDR_WIDTH = 4, 74 | parameter DATA_BUF_OFFSET_WIDTH = 1, 75 | parameter DATA_WIDTH = 64, 76 | parameter DQ_WIDTH = 72, 77 | parameter ECC_WIDTH = 8, 78 | parameter nCK_PER_CLK = 4 79 | ) 80 | ( 81 | /*AUTOARG*/ 82 | // Outputs 83 | mc_wrdata, mc_wrdata_mask, 84 | // Inputs 85 | clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc 86 | ); 87 | 88 | input clk; 89 | input rst; 90 | 91 | input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; 92 | input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask; 93 | input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; 94 | 95 | reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r; 96 | reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r; 97 | reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r; 98 | 99 | always @(posedge clk) wr_data_r <= #TCQ wr_data; 100 | always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask; 101 | always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data; 102 | 103 | // Merge new data with memory read data. 104 | wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data; 105 | genvar h; 106 | genvar i; 107 | generate 108 | for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer 109 | for (i=0; i DATA_WIDTH) 116 | assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]= 117 | wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]; 118 | 119 | end 120 | endgenerate 121 | 122 | // Generate ECC and overlay onto mc_wrdata. 123 | input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; 124 | input [2*nCK_PER_CLK-1:0] raw_not_ecc; 125 | reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r; 126 | always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc; 127 | output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata; 128 | reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c; 129 | genvar j; 130 | integer k; 131 | generate 132 | for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word 133 | always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin 134 | mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] = 135 | {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}}, 136 | merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]}; 137 | for (k=0; k= 0) { 82 | /* A CPU has %cr4 if and only if it has CPUID */ 83 | - mmu_cr4_features = read_cr4(); 84 | + mmu_cr4_features = 0; //read_cr4(); 85 | if (trampoline_cr4_features) 86 | *trampoline_cr4_features = mmu_cr4_features; 87 | } 88 | --------------------------------------------------------------------------------