├── .gitmodules ├── LICENSE ├── README.md ├── common ├── ao486_rst_controller.v ├── bios_loader.v ├── burst_converter.v ├── byteen_converter.v ├── io_bus.v ├── pc_bus_to_vga.v ├── simple_biclk_bidir_ram.v ├── to_driver_sd_avs.v └── to_sdram.v ├── fpga ├── de2-115 │ ├── project │ │ ├── project.qpf │ │ ├── project.qsf │ │ └── project.sdc │ └── rtl │ │ ├── clock │ │ ├── clk_wiz_0.ppf │ │ ├── clk_wiz_0.qip │ │ ├── clk_wiz_0.v │ │ ├── clk_wiz_0_bb.v │ │ └── clock.v │ │ ├── params.v │ │ ├── soc.v │ │ ├── system.v │ │ └── system_sdram.v ├── nexys4 │ ├── constraint │ │ └── Nexys4_Master.xdc │ ├── project │ │ └── project.xpr │ └── rtl │ │ ├── clock │ │ ├── clk_wiz_0.v │ │ ├── clk_wiz_0_clk_wiz.v │ │ └── clock.v │ │ ├── params.v │ │ ├── psramcon.v │ │ ├── soc.v │ │ └── system.v └── nexys4_ddr │ ├── constraint │ └── Nexys4DDR_Master.xdc │ ├── project │ ├── project.srcs │ │ └── sources_1 │ │ │ └── ip │ │ │ └── mig │ │ │ ├── doc │ │ │ └── mig_7series_v2_0_changelog.txt │ │ │ ├── mig.dcp │ │ │ ├── mig.veo │ │ │ ├── mig.xci │ │ │ ├── mig.xml │ │ │ ├── mig │ │ │ ├── datasheet.txt │ │ │ ├── docs │ │ │ │ └── phy_only_support_readme.txt │ │ │ ├── example_design │ │ │ │ ├── log.txt │ │ │ │ ├── par │ │ │ │ │ ├── example_top.xdc │ │ │ │ │ └── readme.txt │ │ │ │ ├── rtl │ │ │ │ │ ├── example_top.v │ │ │ │ │ └── traffic_gen │ │ │ │ │ │ ├── mig_7series_v2_0_afifo.v │ │ │ │ │ │ ├── mig_7series_v2_0_cmd_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_cmd_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_data_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_init_mem_pattern_ctr.v │ │ │ │ │ │ ├── mig_7series_v2_0_memc_flow_vcontrol.v │ │ │ │ │ │ ├── mig_7series_v2_0_memc_traffic_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_rd_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_read_data_path.v │ │ │ │ │ │ ├── mig_7series_v2_0_read_posted_fifo.v │ │ │ │ │ │ ├── mig_7series_v2_0_s7ven_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_tg_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_0_tg_status.v │ │ │ │ │ │ ├── mig_7series_v2_0_traffic_gen_top.v │ │ │ │ │ │ ├── mig_7series_v2_0_vio_init_pattern_bram.v │ │ │ │ │ │ ├── mig_7series_v2_0_wr_data_gen.v │ │ │ │ │ │ └── mig_7series_v2_0_write_data_path.v │ │ │ │ └── sim │ │ │ │ │ ├── ddr2_model.v │ │ │ │ │ ├── ddr2_model_parameters.vh │ │ │ │ │ ├── ies_run.sh │ │ │ │ │ ├── readme.txt │ │ │ │ │ ├── sim.do │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── vcs_run.sh │ │ │ │ │ ├── wiredly.v │ │ │ │ │ ├── xsim_files.prj │ │ │ │ │ ├── xsim_options.tcl │ │ │ │ │ └── xsim_run.bat │ │ │ ├── mig.prj │ │ │ └── user_design │ │ │ │ ├── constraints │ │ │ │ ├── mig.xdc │ │ │ │ └── mig_ooc.xdc │ │ │ │ ├── log.txt │ │ │ │ └── rtl │ │ │ │ ├── clocking │ │ │ │ ├── mig_7series_v2_0_clk_ibuf.v │ │ │ │ ├── mig_7series_v2_0_infrastructure.v │ │ │ │ ├── mig_7series_v2_0_iodelay_ctrl.v │ │ │ │ └── mig_7series_v2_0_tempmon.v │ │ │ │ ├── controller │ │ │ │ ├── mig_7series_v2_0_arb_mux.v │ │ │ │ ├── mig_7series_v2_0_arb_row_col.v │ │ │ │ ├── mig_7series_v2_0_arb_select.v │ │ │ │ ├── mig_7series_v2_0_bank_cntrl.v │ │ │ │ ├── mig_7series_v2_0_bank_common.v │ │ │ │ ├── mig_7series_v2_0_bank_compare.v │ │ │ │ ├── mig_7series_v2_0_bank_mach.v │ │ │ │ ├── mig_7series_v2_0_bank_queue.v │ │ │ │ ├── mig_7series_v2_0_bank_state.v │ │ │ │ ├── mig_7series_v2_0_col_mach.v │ │ │ │ ├── mig_7series_v2_0_mc.v │ │ │ │ ├── mig_7series_v2_0_rank_cntrl.v │ │ │ │ ├── mig_7series_v2_0_rank_common.v │ │ │ │ ├── mig_7series_v2_0_rank_mach.v │ │ │ │ └── mig_7series_v2_0_round_robin_arb.v │ │ │ │ ├── ecc │ │ │ │ ├── mig_7series_v2_0_ecc_buf.v │ │ │ │ ├── mig_7series_v2_0_ecc_dec_fix.v │ │ │ │ ├── mig_7series_v2_0_ecc_gen.v │ │ │ │ ├── mig_7series_v2_0_ecc_merge_enc.v │ │ │ │ └── mig_7series_v2_0_fi_xor.v │ │ │ │ ├── ip_top │ │ │ │ ├── mig_7series_v2_0_mem_intfc.v │ │ │ │ └── mig_7series_v2_0_memc_ui_top_std.v │ │ │ │ ├── mig.v │ │ │ │ ├── mig_mig.v │ │ │ │ ├── mig_mig_sim.v │ │ │ │ ├── phy │ │ │ │ ├── mig_7series_v2_0_ddr_byte_group_io.v │ │ │ │ ├── mig_7series_v2_0_ddr_byte_lane.v │ │ │ │ ├── mig_7series_v2_0_ddr_calib_top.v │ │ │ │ ├── mig_7series_v2_0_ddr_if_post_fifo.v │ │ │ │ ├── mig_7series_v2_0_ddr_mc_phy.v │ │ │ │ ├── mig_7series_v2_0_ddr_mc_phy_wrapper.v │ │ │ │ ├── mig_7series_v2_0_ddr_of_pre_fifo.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_4lanes.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_dqs_found_cal.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_dqs_found_cal_hr.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_init.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_oclkdelay_cal.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_prbs_rdlvl.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_rdlvl.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_tempmon.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_top.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_wrcal.v │ │ │ │ ├── mig_7series_v2_0_ddr_phy_wrlvl_off_delay.v │ │ │ │ └── mig_7series_v2_0_ddr_prbs_gen.v │ │ │ │ └── ui │ │ │ │ ├── mig_7series_v2_0_ui_cmd.v │ │ │ │ ├── mig_7series_v2_0_ui_rd_data.v │ │ │ │ ├── mig_7series_v2_0_ui_top.v │ │ │ │ └── mig_7series_v2_0_ui_wr_data.v │ │ │ ├── mig_a.prj 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