├── .gitignore ├── .gitattributes ├── platformio.ini ├── lib └── N76E003 │ ├── Delay.h │ ├── examples │ ├── gpio_toggle │ │ └── main.c │ └── uart_echo_interrupt │ │ └── main.c │ ├── Common.h │ ├── Delay.c │ ├── Common.c │ ├── N76E003.h │ ├── Function_Define.h │ └── SFR_Macro.h ├── src └── main.c ├── README.md └── extra_script.py /.gitignore: -------------------------------------------------------------------------------- 1 | .pio 2 | .vscode 3 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /platformio.ini: -------------------------------------------------------------------------------- 1 | [platformio] 2 | default_envs = n76e003 3 | 4 | [env:n76e003] 5 | platform_packages = platformio/tool-stcgal@^1.110.0 ; may not work for linux 6 | platform = https://github.com/arduino12/platform-intel_mcs51.git 7 | board = n76e003 8 | build_flags = -DFOSC_160000 9 | upload_protocol = custom 10 | extra_scripts = extra_script.py 11 | -------------------------------------------------------------------------------- /lib/N76E003/Delay.h: -------------------------------------------------------------------------------- 1 | #ifndef _DELAY_H_ 2 | #define _DELAY_H_ 3 | 4 | void Timer0_Delay100us(uint32_t count); 5 | void Timer0_Delay1ms(uint32_t count); 6 | void Timer0_Delay40ms(uint32_t count); 7 | void Timer1_Delay10ms(uint32_t count); 8 | void Timer2_Delay500us(uint32_t count); 9 | void Timer3_Delay10us(uint32_t count); 10 | void Timer3_Delay100ms(uint32_t count); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * N76E003 GPIOs toggle. 3 | * 4 | * arad.rgb@gmail.com 5 | */ 6 | #include "N76E003.h" 7 | #include "SFR_Macro.h" 8 | #include "Function_define.h" 9 | #include "Common.h" 10 | #include "Delay.h" 11 | 12 | void main(void) 13 | { 14 | Set_All_GPIO_Quasi_Mode; // Reset all GPIOs to inputs 15 | 16 | P0M1 = P1M1 = 0x00; // set P0.0-P0.7 and P1.0-P1.7 GPIOs to PushPull 17 | P0M2 = P1M2 = 0xff; 18 | 19 | P30_PushPull_Mode; // set P3.0 to PushPull 20 | 21 | while(1) { // Toggle GPIOs every 100ms 22 | P0 ^= 0xff; 23 | P1 = ~P1; 24 | P30 = !P30; 25 | Timer0_Delay1ms(1000); 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /lib/N76E003/examples/gpio_toggle/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * N76E003 GPIOs toggle. 3 | * 4 | * arad.rgb@gmail.com 5 | */ 6 | #include "N76E003.h" 7 | #include "SFR_Macro.h" 8 | #include "Function_define.h" 9 | #include "Common.h" 10 | #include "Delay.h" 11 | 12 | void main(void) 13 | { 14 | Set_All_GPIO_Quasi_Mode; // Reset all GPIOs to inputs 15 | 16 | P0M1 = P1M1 = 0x00; // set P0.0-P0.7 and P1.0-P1.7 GPIOs to PushPull 17 | P0M2 = P1M2 = 0xff; 18 | 19 | P30_PushPull_Mode; // set P3.0 to PushPull 20 | 21 | while(1) { // Toggle GPIOs every 100ms 22 | P0 ^= 0xff; 23 | P1 = ~P1; 24 | P30 = !P30; 25 | Timer0_Delay1ms(100); 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /lib/N76E003/Common.h: -------------------------------------------------------------------------------- 1 | #ifndef _COMMON_H_ 2 | #define _COMMON_H_ 3 | 4 | #include 5 | 6 | #define CID_READ 0x0B 7 | #define DID_READ 0x0C 8 | #define ERASE_APROM 0x22 9 | #define READ_APROM 0x00 10 | #define PROGRAM_APROM 0x21 11 | #define ERASE_LDROM 12 | #define READ_LDROM 13 | #define PROGRAM_LDROM 14 | #define READ_CFG 0xC0 15 | #define PROGRAM_CFG 0xE1 16 | #define READ_UID 0x04 17 | 18 | typedef __bit bit_t; 19 | 20 | void InitialUART0_Timer1(uint32_t baudrate); 21 | void InitialUART0_Timer3(uint32_t baudrate); 22 | void InitialUART1_Timer3(uint32_t baudrate); 23 | void Send_Data_To_UART0(uint8_t c); 24 | uint8_t Receive_Data_From_UART0(void); 25 | void Send_Data_To_UART1(uint8_t c); 26 | uint8_t Receive_Data_From_UART1(void); 27 | void InitialUART1(uint32_t baudrate); 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /lib/N76E003/examples/uart_echo_interrupt/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * N76E003 UART echo with interrupt. 3 | * UART0: P0.7(RXD) P0.6(TXD) 4 | * UART1: P0.2(RXD) P1.6(TXD) 5 | * 6 | * arad.rgb@gmail.com 7 | */ 8 | #include "N76E003.h" 9 | #include "Common.h" 10 | #include "Delay.h" 11 | #include "SFR_Macro.h" 12 | #include "Function_define.h" 13 | 14 | #define UART_INDEX (1) 15 | #define UART_BAUDRATE (115200) 16 | 17 | uint8_t uart_data; 18 | bit_t uart_ri_flag; 19 | 20 | #if UART_INDEX 21 | void SerialPort1_ISR(void) __interrupt 15 22 | { 23 | if (RI_1) { // uart rx done 24 | clr_RI_1; // clear rx flag 25 | uart_data = SBUF_1; 26 | uart_ri_flag = 1; 27 | } 28 | if(TI_1) { // uart tx done 29 | clr_TI_1; // clear tx flag 30 | } 31 | } 32 | #else 33 | void SerialPort0_ISR(void) __interrupt 4 34 | { 35 | if (RI) { // uart rx done 36 | clr_RI; // clear rx flag 37 | uart_data = SBUF; 38 | uart_ri_flag = 1; 39 | } 40 | if(TI) { // uart tx done 41 | clr_TI; // clear tx flag 42 | } 43 | } 44 | #endif 45 | 46 | void main(void) 47 | { 48 | #if UART_INDEX 49 | InitialUART1_Timer3(UART_BAUDRATE); 50 | set_ES_1; // enable uart interrupt 51 | #else 52 | InitialUART0_Timer3(UART_BAUDRATE); 53 | set_ES; // enable uart interrupt 54 | #endif 55 | set_EA; 56 | 57 | while(1) { 58 | if (uart_ri_flag) { 59 | uart_ri_flag = 0; 60 | #if UART_INDEX 61 | Send_Data_To_UART1(uart_data); 62 | #else 63 | Send_Data_To_UART0(uart_data); 64 | #endif 65 | } 66 | } 67 | } 68 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # n76e003_platformio 2 | Nuvoton MCUs (N76E003) example project with PlatformIO 3 | 4 | 5 | ## Introduction 6 | I just got many N76E003 based modules and I want to develop and upload them my own firmware! 7 | Afte some searching it seems everyone uses keil + uVision IDE (free is limited to 4KB flash out of 18KB), 8 | So I knew my next project is to add this N76E003 board to [PlatformIO](https://platformio.org/) using free [SDCC](http://sdcc.sourceforge.net)! 9 | 10 | ## Features 11 | * I wrote uploader script- currently `upload_protocol` = `custom` but I want to make tool-nulink so it will be `nulink`. 12 | * The uploader script can use Nuvoton CLI tool or GUI tool for uploading - the GUI works much better and faster (~4s vs ~20s). 13 | * Fully free, no code size limit and open source thanks to SDCC + PlatformIO. 14 | 15 | ## Getting Started 16 | 17 | ### Hardware 18 | * Buy Nu-Link ICP programmer: [this](https://www.aliexpress.com/item/32815222785.html) and [this](https://www.aliexpress.com/item/4000410409070.html) works for me. 19 | * Buy N76E003 EVB: [this](https://www.aliexpress.com/item/1005002134285257.html) and [this](https://www.aliexpress.com/item/1005001893572711.html) works for me, also many modules use them like [this](https://www.aliexpress.com/item/33034099678.html) 20 | 21 | ### Software 22 | * Download and install [Visual code](https://code.visualstudio.com/download) 23 | * Install [PlatformIO](https://platformio.org/platformio-ide) extension to Visual code. 24 | * Download and install the NuMicroICP and/or NuLinkCLI from [Nuvoton tools](https://www.nuvoton.com/tool-and-software/software-development-tool/programmer). 25 | * Clone this [repo](https://github.com/arduino12/n76e003_platformio), open it with Visual code and upload it via PlatformIO-upload command. 26 | 27 | ## TODO 28 | * Add more examples. 29 | * PR to [platform-intel_mcs51](https://github.com/platformio/platform-intel_mcs51) to add N76E003 board and examples. 30 | * Move [uploader script](https://github.com/arduino12/n76e003_platformio/blob/main/extra_script.py) into a tool-nulink package repo of PlatformIO. 31 | * Move [N76E003 lib](https://github.com/arduino12/n76e003_platformio/tree/main/lib/N76E003) into a freamwork package of PlatformIO or into tool-SDCC. 32 | * Implement Arduino-like API like [this](https://tenbaht.github.io/sduino/api/migration/) amazing project - because the N76E003 is VERY simular to STM8S103. 33 | 34 | ## Enjoy! 35 | A.E.TECH 36 | 37 | -------------------------------------------------------------------------------- /lib/N76E003/Delay.c: -------------------------------------------------------------------------------- 1 | #include "N76E003.h" 2 | #include "Common.h" 3 | #include "Delay.h" 4 | #include "SFR_Macro.h" 5 | #include "Function_define.h" 6 | 7 | void Timer0_Delay100us(uint32_t count) 8 | { 9 | clr_T0M; //T0M=0, Timer0 Clock = Fsys/12 10 | TMOD |= 0x01; //Timer0 is 16-bit mode 11 | set_TR0; //Start Timer0 12 | while (count--) { 13 | TL0 = LOBYTE(TIMER_DIV12_VALUE_100us); 14 | TH0 = HIBYTE(TIMER_DIV12_VALUE_100us); 15 | while (TF0 != 1); //Check Timer0 Time-Out Flag 16 | clr_TF0; 17 | } 18 | clr_TR0; //Stop Timer0 19 | } 20 | 21 | void Timer0_Delay1ms(uint32_t count) 22 | { 23 | clr_T0M; //T0M=0, Timer0 Clock = Fsys/12 24 | TMOD |= 0x01; //Timer0 is 16-bit mode 25 | set_TR0; //Start Timer0 26 | while (count--) { 27 | TL0 = LOBYTE(TIMER_DIV12_VALUE_1ms); 28 | TH0 = HIBYTE(TIMER_DIV12_VALUE_1ms); 29 | while (TF0 != 1); //Check Timer0 Time-Out Flag 30 | clr_TF0; 31 | } 32 | clr_TR0; //Stop Timer0 33 | } 34 | 35 | void Timer0_Delay40ms(uint32_t count) 36 | { 37 | clr_T0M; //T0M=0, Timer0 Clock = Fsys/12 38 | TMOD |= 0x01; //Timer0 is 16-bit mode 39 | set_TR0; //Start Timer0 40 | while (count--) { 41 | TL0 = LOBYTE(TIMER_DIV12_VALUE_40ms); 42 | TH0 = HIBYTE(TIMER_DIV12_VALUE_40ms); 43 | while (TF0 != 1); //Check Timer0 Time-Out Flag 44 | clr_TF0; 45 | } 46 | clr_TR0; //Stop Timer0 47 | } 48 | 49 | void Timer1_Delay10ms(uint32_t count) 50 | { 51 | clr_T1M; //T1M=0, Timer1 Clock = Fsys/12 52 | TMOD |= 0x10; //Timer1 is 16-bit mode 53 | set_TR1; //Start Timer1 54 | while (count--) { 55 | TL1 = LOBYTE(TIMER_DIV12_VALUE_10ms); 56 | TH1 = HIBYTE(TIMER_DIV12_VALUE_10ms); 57 | while (TF1 != 1); //Check Timer1 Time-Out Flag 58 | clr_TF1; 59 | } 60 | clr_TR1; //Stop Timer1 61 | } 62 | 63 | void Timer2_Delay500us(uint32_t count) 64 | { 65 | clr_T2DIV2; //Timer2 Clock = Fsys/4 66 | clr_T2DIV1; 67 | set_T2DIV0; 68 | set_TR2; //Start Timer2 69 | while (count--) { 70 | TL2 = LOBYTE(TIMER_DIV4_VALUE_500us); 71 | TH2 = HIBYTE(TIMER_DIV4_VALUE_500us); 72 | while (TF2 != 1); //Check Timer2 Time-Out Flag 73 | clr_TF2; 74 | } 75 | clr_TR2; //Stop Timer2 76 | } 77 | 78 | void Timer3_Delay10us(uint32_t count) 79 | { 80 | T3CON = 0x07; //Timer3 Clock = Fsys/128 81 | set_TR3; //Trigger Timer3 82 | while (count--) { 83 | RL3 = LOBYTE(TIMER_DIV4_VALUE_10us); 84 | RH3 = HIBYTE(TIMER_DIV4_VALUE_10us); 85 | while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag 86 | clr_TF3; 87 | } 88 | clr_TR3; //Stop Timer3 89 | } 90 | 91 | void Timer3_Delay100ms(uint32_t count) 92 | { 93 | T3CON = 0x07; //Timer3 Clock = Fsys/128 94 | set_TR3; //Trigger Timer3 95 | while (count--) { 96 | RL3 = LOBYTE(TIMER_DIV128_VALUE_100ms); 97 | RH3 = HIBYTE(TIMER_DIV128_VALUE_100ms); 98 | while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag 99 | clr_TF3; 100 | } 101 | clr_TR3; //Stop Timer3 102 | } 103 | -------------------------------------------------------------------------------- /lib/N76E003/Common.c: -------------------------------------------------------------------------------- 1 | #include "N76E003.h" 2 | #include "Common.h" 3 | #include "SFR_Macro.h" 4 | #include "Function_define.h" 5 | 6 | bit_t BIT_TMP; 7 | 8 | void InitialUART0_Timer1(uint32_t baudrate) //T1M = 1, SMOD = 1 9 | { 10 | P06_Quasi_Mode; //Setting UART pin as Quasi mode for transmit 11 | P07_Quasi_Mode; //Setting UART pin as Quasi mode for transmit 12 | 13 | SCON = 0x50; //UART0 Mode1,REN=1,TI=1 14 | TMOD |= 0x20; //Timer1 Mode1 15 | 16 | set_SMOD; //UART0 Double Rate Enable 17 | set_T1M; 18 | clr_BRCK; //Serial port 0 baud rate clock source = Timer1 19 | 20 | #if defined(FOSC_160000) //16 MHz 21 | TH1 = 256 - (1000000/baudrate+1); 22 | #elif defined(FOSC_166000) //16.6 MHz 23 | TH1 = 256 - (1037500/baudrate); 24 | #endif 25 | 26 | set_TR1; 27 | set_TI; //For printf function must setting TI = 1 28 | } 29 | 30 | void InitialUART0_Timer3(uint32_t baudrate) //use timer3 as Baudrate generator 31 | { 32 | P06_Quasi_Mode; //Setting UART pin as Quasi mode for transmit 33 | P07_Quasi_Mode; //Setting UART pin as Quasi mode for transmit 34 | 35 | SCON = 0x50; //UART0 Mode1,REN=1,TI=1 36 | set_SMOD; //UART0 Double Rate Enable 37 | T3CON &= 0xF8; //T3PS2=0,T3PS1=0,T3PS0=0(Prescale=1) 38 | set_BRCK; //UART0 baud rate clock source = Timer3 39 | 40 | #if defined(FOSC_160000) //16 MHz 41 | RH3 = HIBYTE(65536 - (1000000/baudrate)-1); 42 | RL3 = LOBYTE(65536 - (1000000/baudrate)-1); 43 | #elif defined(FOSC_166000) //16.6 MHz 44 | RH3 = HIBYTE(65536 - (1037500/baudrate)); 45 | RL3 = LOBYTE(65536 - (1037500/baudrate)); 46 | #endif 47 | 48 | set_TR3; //Trigger Timer3 49 | set_TI; //For printf function must setting TI = 1 50 | } 51 | 52 | uint8_t Receive_Data_From_UART0(void) 53 | { 54 | uint8_t c; 55 | while (!RI); 56 | c = SBUF; 57 | RI = 0; 58 | return (c); 59 | } 60 | 61 | void Send_Data_To_UART0 (uint8_t c) 62 | { 63 | TI = 0; 64 | SBUF = c; 65 | while(TI==0); 66 | } 67 | 68 | void InitialUART1_Timer3(uint32_t baudrate) //use timer3 as Baudrate generator 69 | { 70 | P02_Quasi_Mode; //Setting UART pin as Quasi mode for transmit 71 | P16_Quasi_Mode; //Setting UART pin as Quasi mode for transmit 72 | 73 | SCON_1 = 0x50; //UART1 Mode1,REN_1=1,TI_1=1 74 | T3CON = 0x08; //T3PS2=0,T3PS1=0,T3PS0=0(Prescale=1), UART1 in MODE 1 75 | clr_BRCK; 76 | 77 | #if defined(FOSC_160000) //16 MHz 78 | RH3 = HIBYTE(65536 - (1000000/baudrate)-1); 79 | RL3 = LOBYTE(65536 - (1000000/baudrate)-1); 80 | #elif defined(FOSC_166000) //16.6 MHz 81 | RH3 = HIBYTE(65536 - (1037500/baudrate)); 82 | RL3 = LOBYTE(65536 - (1037500/baudrate)); 83 | #endif 84 | 85 | set_TR3; //Trigger Timer3 86 | } 87 | 88 | uint8_t Receive_Data_From_UART1(void) 89 | { 90 | uint8_t c; 91 | while (!RI_1); 92 | c = SBUF_1; 93 | RI_1 = 0; 94 | return (c); 95 | } 96 | 97 | void Send_Data_To_UART1 (uint8_t c) 98 | { 99 | TI_1 = 0; 100 | SBUF_1 = c; 101 | while(TI_1==0); 102 | } 103 | 104 | #ifdef SW_Reset 105 | void SW_Reset(void) 106 | { 107 | TA = 0xAA; 108 | TA = 0x55; 109 | set_SWRST; 110 | } 111 | #endif 112 | -------------------------------------------------------------------------------- /extra_script.py: -------------------------------------------------------------------------------- 1 | # 2 | # python3 script for uploading firmware to Nuvoton MCUs via NuLink programmer using their windows apps. 3 | # arad.rgb@gmail.com 01/05/2021 4 | # 5 | import os.path 6 | import warnings 7 | 8 | Import('env') 9 | 10 | NULINK_CLI_EXE = '"%PROGRAMFILES(X86)%\\Nuvoton Tools\\NuLink Command Tool\\NuLink.exe"' 11 | NUMICRO_GUI_EXE = '%PROGRAMFILES(X86)%\\Nuvoton Tools\\ICPTool\\NuMicro ICP Programming Tool.exe' 12 | NULINK_NOT_FOUND_MSG = ''' 13 | Please install %s from: 14 | https://www.nuvoton.com/tool-and-software/software-development-tool/programmer 15 | ''' 16 | 17 | # select whether to upload using NULINK_CLI_EXE (USE_FASTER_NUMICRO = False) or 18 | # using NUMICRO_GUI_EXE (USE_FASTER_NUMICRO = True) - this uses pywinauto but still much faster to upload relative to the CLI... 19 | # USE_FASTER_NUMICRO = False 20 | USE_FASTER_NUMICRO = True 21 | 22 | 23 | def on_upload(source, target, env): 24 | firmware_path = os.path.abspath(str(source[0])) 25 | if USE_FASTER_NUMICRO: 26 | # install pywinauto if needed 27 | try: 28 | import pywinauto 29 | except ImportError: 30 | env.Execute(env.VerboseAction('$PYTHONEXE -m pip install pywinauto', 'Installing Python dependencies...')) 31 | warnings.warn('Please run again!') 32 | exit(1) 33 | 34 | # connect to NuMicro app (run it if needed) 35 | numicro_gui_exe = os.path.expandvars(NUMICRO_GUI_EXE) 36 | app = pywinauto.Application(backend='win32') 37 | # dont print 32/64bit application warning 38 | warnings.simplefilter('ignore') 39 | try: 40 | app.connect(path=numicro_gui_exe) 41 | print('Connected to NuMicro app') 42 | except: 43 | try: 44 | app.start(numicro_gui_exe) 45 | print('Started NuMicro app') 46 | except: 47 | app = None 48 | warnings.simplefilter('default') 49 | if app is None: 50 | warnings.warn(NULINK_NOT_FOUND_MSG % 'NuMicroICP') 51 | exit(2) 52 | 53 | # config startup dialog if needed 54 | window = app.window(title_re='^Nuvoton') 55 | window.set_focus() 56 | window.wait('enabled') 57 | if window.control_count() < 50: 58 | window.SelectTargetChipComboBox.select('8051 1T Series') 59 | window.ContinueButton.click() 60 | 61 | # helper to manage connection state 62 | def set_connection(is_connected): 63 | STATES = ('Disconnect', 'Connect') 64 | is_connected = 1 if is_connected else 0 65 | window.ConnectButton.wait('enabled') 66 | if window.ConnectButton.window_text() == STATES[is_connected]: 67 | window.ConnectButton.check_by_click() 68 | pywinauto.timings.wait_until(3, 0.1, window.ConnectButton.window_text, STATES[1 - is_connected]) 69 | print(f'{"Connected to" if is_connected else "Disconnected from"} NuLink programmer') 70 | 71 | set_connection(True) 72 | window.set_focus() 73 | 74 | # flash only APROM 75 | window.ConfigCheckBox.uncheck_by_click() 76 | window.LDROMCheckBox.uncheck_by_click() 77 | window.APROMCheckBox.check_by_click() 78 | 79 | # set APROM file path if needed 80 | if firmware_path != window.FileNameEdit0.window_text(): 81 | print(f'Setting APROM file to {firmware_path}') 82 | window.APROMButton.set_focus() 83 | window.APROMButton.click_input() 84 | app.Open.wait('enabled') 85 | app.Open.FileNameEdit.set_text(firmware_path) 86 | app.Open.OpenButton.click_input() 87 | window.wait('enabled') 88 | 89 | # handle dialogs 90 | window.StartButton.click_input() 91 | dialog = app.window(title_re='^NuMicro') 92 | while True: 93 | dialog.wait('enabled') 94 | text = dialog.static.window_text() 95 | dialog.send_keystrokes('{ENTER}{ESC}') 96 | if text == 'Programming flash, OK!': 97 | break 98 | 99 | set_connection(False) 100 | window.minimize() 101 | 102 | else: 103 | # erase APROM and write firmware to APROM 104 | try: 105 | env.Execute(f'{NULINK_CLI_EXE} -e aprom') 106 | env.Execute(f'{NULINK_CLI_EXE} -w aprom {firmware_path}') 107 | # env.Execute(f'{NULINK_CLI_EXE} -disconnect') # doesn't disconnect.... 108 | except: 109 | warnings.warn(NULINK_NOT_FOUND_MSG % 'NuLinkCLI') 110 | exit(2) 111 | # warn user to manually disconnect by pressing the button on the NuLink because -disconnect doesn't work.. 112 | __import__('time').sleep(0.1) 113 | warnings.warn(''' 114 | Press NuLink button to release (disconnect) mcu if needed!''') 115 | 116 | 117 | env.Replace(UPLOADCMD=on_upload) 118 | -------------------------------------------------------------------------------- /lib/N76E003/N76E003.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Header files for Nuvoton N76E003 for SDCC. 3 | * 4 | * Nuvoton Technoledge Corp, http://www.nuvoton.com MicroC-8bit@nuvoton.com 5 | * Copyright(c) 2016 Nuvoton Technology Corp. All rights reserved. 6 | */ 7 | #ifndef _N76E003_H_ 8 | #define _N76E003_H_ 9 | 10 | __sfr __at (0x80) P0 ; 11 | __sfr __at (0x81) SP ; 12 | __sfr __at (0x82) DPL ; 13 | __sfr __at (0x83) DPH ; 14 | __sfr __at (0x84) RCTRIM0 ; 15 | __sfr __at (0x85) RCTRIM1 ; 16 | __sfr __at (0x86) RWK ; 17 | __sfr __at (0x87) PCON ; 18 | 19 | __sfr __at (0x88) TCON ; 20 | __sfr __at (0x89) TMOD ; 21 | __sfr __at (0x8A) TL0 ; 22 | __sfr __at (0x8B) TL1 ; 23 | __sfr __at (0x8C) TH0 ; 24 | __sfr __at (0x8D) TH1 ; 25 | __sfr __at (0x8E) CKCON ; 26 | __sfr __at (0x8F) WKCON ; 27 | 28 | __sfr __at (0x90) P1 ; 29 | __sfr __at (0x91) SFRS ; //TA Protection 30 | __sfr __at (0x92) CAPCON0 ; 31 | __sfr __at (0x93) CAPCON1 ; 32 | __sfr __at (0x94) CAPCON2 ; 33 | __sfr __at (0x95) CKDIV ; 34 | __sfr __at (0x96) CKSWT ; //TA Protection 35 | __sfr __at (0x97) CKEN ; //TA Protection 36 | 37 | __sfr __at (0x98) SCON ; 38 | __sfr __at (0x99) SBUF ; 39 | __sfr __at (0x9A) SBUF_1 ; 40 | __sfr __at (0x9B) EIE ; 41 | __sfr __at (0x9C) EIE1 ; 42 | __sfr __at (0x9F) CHPCON ; //TA Protection 43 | 44 | __sfr __at (0xA0) P2 ; 45 | __sfr __at (0xA2) AUXR1 ; 46 | __sfr __at (0xA3) BODCON0 ; //TA Protection 47 | __sfr __at (0xA4) IAPTRG ; //TA Protection 48 | __sfr __at (0xA5) IAPUEN ; //TA Protection 49 | __sfr __at (0xA6) IAPAL ; 50 | __sfr __at (0xA7) IAPAH ; 51 | 52 | __sfr __at (0xA8) IE ; 53 | __sfr __at (0xA9) SADDR ; 54 | __sfr __at (0xAA) WDCON ; //TA Protection 55 | __sfr __at (0xAB) BODCON1 ; //TA Protection 56 | __sfr __at (0xAC) P3M1 ; 57 | __sfr __at (0xAC) P3S ; //Page1 58 | __sfr __at (0xAD) P3M2 ; 59 | __sfr __at (0xAD) P3SR ; //Page1 60 | __sfr __at (0xAE) IAPFD ; 61 | __sfr __at (0xAF) IAPCN ; 62 | 63 | __sfr __at (0xB0) P3 ; 64 | __sfr __at (0xB1) P0M1 ; 65 | __sfr __at (0xB1) P0S ; //Page1 66 | __sfr __at (0xB2) P0M2 ; 67 | __sfr __at (0xB2) P0SR ; //Page1 68 | __sfr __at (0xB3) P1M1 ; 69 | __sfr __at (0xB3) P1S ; //Page1 70 | __sfr __at (0xB4) P1M2 ; 71 | __sfr __at (0xB4) P1SR ; //Page1 72 | __sfr __at (0xB5) P2S ; 73 | __sfr __at (0xB7) IPH ; 74 | __sfr __at (0xB7) PWMINTC ; //Page1 75 | 76 | __sfr __at (0xB8) IP ; 77 | __sfr __at (0xB9) SADEN ; 78 | __sfr __at (0xBA) SADEN_1 ; 79 | __sfr __at (0xBB) SADDR_1 ; 80 | __sfr __at (0xBC) I2DAT ; 81 | __sfr __at (0xBD) I2STAT ; 82 | __sfr __at (0xBE) I2CLK ; 83 | __sfr __at (0xBF) I2TOC ; 84 | 85 | __sfr __at (0xC0) I2CON ; 86 | __sfr __at (0xC1) I2ADDR ; 87 | __sfr __at (0xC2) ADCRL ; 88 | __sfr __at (0xC3) ADCRH ; 89 | __sfr __at (0xC4) T3CON ; 90 | __sfr __at (0xC4) PWM4H ; //Page1 91 | __sfr __at (0xC5) RL3 ; 92 | __sfr __at (0xC5) PWM5H ; //Page1 93 | __sfr __at (0xC6) RH3 ; 94 | __sfr __at (0xC6) PIOCON1 ; //Page1 95 | __sfr __at (0xC7) TA ; 96 | 97 | __sfr __at (0xC8) T2CON ; 98 | __sfr __at (0xC9) T2MOD ; 99 | __sfr __at (0xCA) RCMP2L ; 100 | __sfr __at (0xCB) RCMP2H ; 101 | __sfr __at (0xCC) TL2 ; 102 | __sfr __at (0xCC) PWM4L ; //Page1 103 | __sfr __at (0xCD) TH2 ; 104 | __sfr __at (0xCD) PWM5L ; //Page1 105 | __sfr __at (0xCE) ADCMPL ; 106 | __sfr __at (0xCF) ADCMPH ; 107 | 108 | __sfr __at (0xD0) PSW ; 109 | __sfr __at (0xD1) PWMPH ; 110 | __sfr __at (0xD2) PWM0H ; 111 | __sfr __at (0xD3) PWM1H ; 112 | __sfr __at (0xD4) PWM2H ; 113 | __sfr __at (0xD5) PWM3H ; 114 | __sfr __at (0xD6) PNP ; 115 | __sfr __at (0xD7) FBD ; 116 | 117 | __sfr __at (0xD8) PWMCON0 ; 118 | __sfr __at (0xD9) PWMPL ; 119 | __sfr __at (0xDA) PWM0L ; 120 | __sfr __at (0xDB) PWM1L ; 121 | __sfr __at (0xDC) PWM2L ; 122 | __sfr __at (0xDD) PWM3L ; 123 | __sfr __at (0xDE) PIOCON0 ; 124 | __sfr __at (0xDF) PWMCON1 ; 125 | 126 | __sfr __at (0xE0) ACC ; 127 | __sfr __at (0xE1) ADCCON1 ; 128 | __sfr __at (0xE2) ADCCON2 ; 129 | __sfr __at (0xE3) ADCDLY ; 130 | __sfr __at (0xE4) C0L ; 131 | __sfr __at (0xE5) C0H ; 132 | __sfr __at (0xE6) C1L ; 133 | __sfr __at (0xE7) C1H ; 134 | 135 | __sfr __at (0xE8) ADCCON0 ; 136 | __sfr __at (0xE9) PICON ; 137 | __sfr __at (0xEA) PINEN ; 138 | __sfr __at (0xEB) PIPEN ; 139 | __sfr __at (0xEC) PIF ; 140 | __sfr __at (0xED) C2L ; 141 | __sfr __at (0xEE) C2H ; 142 | __sfr __at (0xEF) EIP ; 143 | 144 | __sfr __at (0xF0) B ; 145 | __sfr __at (0xF1) CAPCON3 ; 146 | __sfr __at (0xF2) CAPCON4 ; 147 | __sfr __at (0xF3) SPCR ; 148 | __sfr __at (0xF3) SPCR2 ; //Page1 149 | __sfr __at (0xF4) SPSR ; 150 | __sfr __at (0xF5) SPDR ; 151 | __sfr __at (0xF6) AINDIDS ; 152 | __sfr __at (0xF7) EIPH ; 153 | 154 | __sfr __at (0xF8) SCON_1 ; 155 | __sfr __at (0xF9) PDTEN ; //TA Protection 156 | __sfr __at (0xFA) PDTCNT ; //TA Protection 157 | __sfr __at (0xFB) PMEN ; 158 | __sfr __at (0xFC) PMD ; 159 | __sfr __at (0xFD) PORDIS ; 160 | __sfr __at (0xFE) EIP1 ; 161 | __sfr __at (0xFF) EIPH1 ; 162 | 163 | // SCON_1 164 | __sbit __at (0xFF) SM0_1 ; // SCON_1^7; 165 | __sbit __at (0xFF) FE_1 ; // SCON_1^7; 166 | __sbit __at (0xFE) SM1_1 ; // SCON_1^6; 167 | __sbit __at (0xFD) SM2_1 ; // SCON_1^5; 168 | __sbit __at (0xFC) REN_1 ; // SCON_1^4; 169 | __sbit __at (0xFB) TB8_1 ; // SCON_1^3; 170 | __sbit __at (0xFA) RB8_1 ; // SCON_1^2; 171 | __sbit __at (0xF9) TI_1 ; // SCON_1^1; 172 | __sbit __at (0xF8) RI_1 ; // SCON_1^0; 173 | 174 | // ADCCON0 175 | __sbit __at (0xEF) ADCF ; // ADCCON0^7; 176 | __sbit __at (0xEE) ADCS ; // ADCCON0^6; 177 | __sbit __at (0xED) ETGSEL1 ; // ADCCON0^5; 178 | __sbit __at (0xEC) ETGSEL0 ; // ADCCON0^4; 179 | __sbit __at (0xEB) ADCHS3 ; // ADCCON0^3; 180 | __sbit __at (0xEA) ADCHS2 ; // ADCCON0^2; 181 | __sbit __at (0xE9) ADCHS1 ; // ADCCON0^1; 182 | __sbit __at (0xE8) ADCHS0 ; // ADCCON0^0; 183 | 184 | // PWMCON0 185 | __sbit __at (0xDF) PWMRUN ; // PWMCON0^7; 186 | __sbit __at (0xDE) LOAD ; // PWMCON0^6; 187 | __sbit __at (0xDD) PWMF ; // PWMCON0^5; 188 | __sbit __at (0xDC) CLRPWM ; // PWMCON0^4; 189 | 190 | // PSW */ 191 | __sbit __at (0xD7) CY ; // PSW^7; 192 | __sbit __at (0xD6) AC ; // PSW^6; 193 | __sbit __at (0xD5) F0 ; // PSW^5; 194 | __sbit __at (0xD4) RS1 ; // PSW^4; 195 | __sbit __at (0xD3) RS0 ; // PSW^3; 196 | __sbit __at (0xD2) OV ; // PSW^2; 197 | __sbit __at (0xD0) P ; // PSW^0; 198 | 199 | // T2CON 200 | __sbit __at (0xCF) TF2 ; // T2CON^7; 201 | __sbit __at (0xCA) TR2 ; // T2CON^2; 202 | __sbit __at (0xC8) CM_RL2 ; // T2CON^0; 203 | 204 | // I2CON 205 | __sbit __at (0xC6) I2CEN ; // I2CON^6; 206 | __sbit __at (0xC5) STA ; // I2CON^5; 207 | __sbit __at (0xC4) STO ; // I2CON^4; 208 | __sbit __at (0xC3) SI ; // I2CON^3; 209 | __sbit __at (0xC2) AA ; // I2CON^2; 210 | __sbit __at (0xC0) I2CPX ; // I2CON^0; 211 | 212 | // IP 213 | __sbit __at (0xBE) PADC ; // IP^6; 214 | __sbit __at (0xBD) PBOD ; // IP^5; 215 | __sbit __at (0xBC) PS ; // IP^4; 216 | __sbit __at (0xBB) PT1 ; // IP^3; 217 | __sbit __at (0xBA) PX1 ; // IP^2; 218 | __sbit __at (0xB9) PT0 ; // IP^1; 219 | __sbit __at (0xB8) PX0 ; // IP^0; 220 | 221 | // P3 222 | __sbit __at (0xB0) P30 ; // P3^0; 223 | 224 | // IE 225 | __sbit __at (0xAF) EA ; // IE^7; 226 | __sbit __at (0xAE) EADC ; // IE^6; 227 | __sbit __at (0xAD) EBOD ; // IE^5; 228 | __sbit __at (0xAC) ES ; // IE^4; 229 | __sbit __at (0xAB) ET1 ; // IE^3; 230 | __sbit __at (0xAA) EX1 ; // IE^2; 231 | __sbit __at (0xA9) ET0 ; // IE^1; 232 | __sbit __at (0xA8) EX0 ; // IE^0; 233 | 234 | // P2 235 | __sbit __at (0xA0) P20 ; // P2^0; 236 | 237 | // SCON 238 | __sbit __at (0x9F) SM0 ; // SCON^7; 239 | __sbit __at (0x9F) FE ; // SCON^7; 240 | __sbit __at (0x9E) SM1 ; // SCON^6; 241 | __sbit __at (0x9D) SM2 ; // SCON^5; 242 | __sbit __at (0x9C) REN ; // SCON^4; 243 | __sbit __at (0x9B) TB8 ; // SCON^3; 244 | __sbit __at (0x9A) RB8 ; // SCON^2; 245 | __sbit __at (0x99) TI ; // SCON^1; 246 | __sbit __at (0x98) RI ; // SCON^0; 247 | 248 | // P1 249 | __sbit __at (0x97) P17 ; // P1^7; 250 | __sbit __at (0x96) P16 ; // P1^6; 251 | __sbit __at (0x96) TXD_1 ; // P1^6; 252 | __sbit __at (0x95) P15 ; // P1^5; 253 | __sbit __at (0x94) P14 ; // P1^4; 254 | __sbit __at (0x94) SDA ; // P1^4; 255 | __sbit __at (0x93) P13 ; // P1^3; 256 | __sbit __at (0x93) SCL ; // P1^3; 257 | __sbit __at (0x92) P12 ; // P1^2; 258 | __sbit __at (0x91) P11 ; // P1^1; 259 | __sbit __at (0x90) P10 ; // P1^0; 260 | 261 | // TCON 262 | __sbit __at (0x8F) TF1 ; // TCON^7; 263 | __sbit __at (0x8E) TR1 ; // TCON^6; 264 | __sbit __at (0x8D) TF0 ; // TCON^5; 265 | __sbit __at (0x8C) TR0 ; // TCON^4; 266 | __sbit __at (0x8B) IE1 ; // TCON^3; 267 | __sbit __at (0x8A) IT1 ; // TCON^2; 268 | __sbit __at (0x89) IE0 ; // TCON^1; 269 | __sbit __at (0x88) IT0 ; // TCON^0; 270 | 271 | // P0 272 | __sbit __at (0x87) P07 ; // P0^7; 273 | __sbit __at (0x87) RXD ; // P0^7; 274 | __sbit __at (0x86) P06 ; // P0^6; 275 | __sbit __at (0x86) TXD ; // P0^6; 276 | __sbit __at (0x85) P05 ; // P0^5; 277 | __sbit __at (0x84) P04 ; // P0^4; 278 | __sbit __at (0x84) STADC ; // P0^4; 279 | __sbit __at (0x83) P03 ; // P0^3; 280 | __sbit __at (0x82) P02 ; // P0^2; 281 | __sbit __at (0x82) RXD_1 ; // P0^2; 282 | __sbit __at (0x81) P01 ; // P0^1; 283 | __sbit __at (0x81) MISO ; // P0^1; 284 | __sbit __at (0x80) P00 ; // P0^0; 285 | __sbit __at (0x80) MOSI ; // P0^0; 286 | 287 | #endif 288 | -------------------------------------------------------------------------------- /lib/N76E003/Function_Define.h: -------------------------------------------------------------------------------- 1 | #ifndef _FUNCTION_DEFINE_H_ 2 | #define _FUNCTION_DEFINE_H_ 3 | 4 | #include "N76E003.h" 5 | #include "Common.h" 6 | #include "SFR_Macro.h" 7 | 8 | extern bit_t BIT_TMP; 9 | 10 | #define nop _nop_(); 11 | 12 | //16 --> 8 x 2 13 | #define HIBYTE(v1) ((uint8_t)((v1)>>8)) 14 | #define LOBYTE(v1) ((uint8_t)((v1)&0xFF)) 15 | //8 x 2 --> 16 16 | #define MAKEWORD(v1,v2) ((((uint16_t)(v1))<<8)+(uint16_t)(v2)) 17 | //8 x 4 --> 32 18 | #define MAKELONG(v1,v2,v3,v4) (uint32_t)((v1<<32)+(v2<<16)+(v3<<8)+v4) 19 | //32 --> 16 x 2 20 | #define YBYTE1(v1) ((uint16_t)((v1)>>16)) 21 | #define YBYTE0(v1) ((uint16_t)((v1)&0xFFFF)) 22 | //32 --> 8 x 4 23 | #define TBYTE3(v1) ((uint8_t)((v1)>>24)) 24 | #define TBYTE2(v1) ((uint8_t)((v1)>>16)) 25 | #define TBYTE1(v1) ((uint8_t)((v1)>>8)) 26 | #define TBYTE0(v1) ((uint8_t)((v1)&0xFF)) 27 | 28 | #define SET_BIT0 0x01 29 | #define SET_BIT1 0x02 30 | #define SET_BIT2 0x04 31 | #define SET_BIT3 0x08 32 | #define SET_BIT4 0x10 33 | #define SET_BIT5 0x20 34 | #define SET_BIT6 0x40 35 | #define SET_BIT7 0x80 36 | #define SET_BIT8 0x0100 37 | #define SET_BIT9 0x0200 38 | #define SET_BIT10 0x0400 39 | #define SET_BIT11 0x0800 40 | #define SET_BIT12 0x1000 41 | #define SET_BIT13 0x2000 42 | #define SET_BIT14 0x4000 43 | #define SET_BIT15 0x8000 44 | 45 | #define CLR_BIT0 0xFE 46 | #define CLR_BIT1 0xFD 47 | #define CLR_BIT2 0xFB 48 | #define CLR_BIT3 0xF7 49 | #define CLR_BIT4 0xEF 50 | #define CLR_BIT5 0xDF 51 | #define CLR_BIT6 0xBF 52 | #define CLR_BIT7 0x7F 53 | 54 | #define CLR_BIT8 0xFEFF 55 | #define CLR_BIT9 0xFDFF 56 | #define CLR_BIT10 0xFBFF 57 | #define CLR_BIT11 0xF7FF 58 | #define CLR_BIT12 0xEFFF 59 | #define CLR_BIT13 0xDFFF 60 | #define CLR_BIT14 0xBFFF 61 | #define CLR_BIT15 0x7FFF 62 | 63 | #define FAIL 1 64 | #define PASS 0 65 | 66 | // GPIO Quasi mode 67 | #define P00_Quasi_Mode do{P0M1&=~SET_BIT0;P0M2&=~SET_BIT0;}while(0) 68 | #define P01_Quasi_Mode do{P0M1&=~SET_BIT1;P0M2&=~SET_BIT1;}while(0) 69 | #define P02_Quasi_Mode do{P0M1&=~SET_BIT2;P0M2&=~SET_BIT2;}while(0) 70 | #define P03_Quasi_Mode do{P0M1&=~SET_BIT3;P0M2&=~SET_BIT3;}while(0) 71 | #define P04_Quasi_Mode do{P0M1&=~SET_BIT4;P0M2&=~SET_BIT4;}while(0) 72 | #define P05_Quasi_Mode do{P0M1&=~SET_BIT5;P0M2&=~SET_BIT5;}while(0) 73 | #define P06_Quasi_Mode do{P0M1&=~SET_BIT6;P0M2&=~SET_BIT6;}while(0) 74 | #define P07_Quasi_Mode do{P0M1&=~SET_BIT7;P0M2&=~SET_BIT7;}while(0) 75 | #define P10_Quasi_Mode do{P1M1&=~SET_BIT0;P1M2&=~SET_BIT0;}while(0) 76 | #define P11_Quasi_Mode do{P1M1&=~SET_BIT1;P1M2&=~SET_BIT1;}while(0) 77 | #define P12_Quasi_Mode do{P1M1&=~SET_BIT2;P1M2&=~SET_BIT2;}while(0) 78 | #define P13_Quasi_Mode do{P1M1&=~SET_BIT3;P1M2&=~SET_BIT3;}while(0) 79 | #define P14_Quasi_Mode do{P1M1&=~SET_BIT4;P1M2&=~SET_BIT4;}while(0) 80 | #define P15_Quasi_Mode do{P1M1&=~SET_BIT5;P1M2&=~SET_BIT5;}while(0) 81 | #define P16_Quasi_Mode do{P1M1&=~SET_BIT6;P1M2&=~SET_BIT6;}while(0) 82 | #define P17_Quasi_Mode do{P1M1&=~SET_BIT7;P1M2&=~SET_BIT7;}while(0) 83 | #define P30_Quasi_Mode do{P3M1&=~SET_BIT0;P3M2&=~SET_BIT0;}while(0) 84 | 85 | // GPIO Push Pull mode 86 | #define P00_PushPull_Mode do{P0M1&=~SET_BIT0;P0M2|=SET_BIT0;}while(0) 87 | #define P01_PushPull_Mode do{P0M1&=~SET_BIT1;P0M2|=SET_BIT1;}while(0) 88 | #define P02_PushPull_Mode do{P0M1&=~SET_BIT2;P0M2|=SET_BIT2;}while(0) 89 | #define P03_PushPull_Mode do{P0M1&=~SET_BIT3;P0M2|=SET_BIT3;}while(0) 90 | #define P04_PushPull_Mode do{P0M1&=~SET_BIT4;P0M2|=SET_BIT4;}while(0) 91 | #define P05_PushPull_Mode do{P0M1&=~SET_BIT5;P0M2|=SET_BIT5;}while(0) 92 | #define P06_PushPull_Mode do{P0M1&=~SET_BIT6;P0M2|=SET_BIT6;}while(0) 93 | #define P07_PushPull_Mode do{P0M1&=~SET_BIT7;P0M2|=SET_BIT7;}while(0) 94 | #define P10_PushPull_Mode do{P1M1&=~SET_BIT0;P1M2|=SET_BIT0;}while(0) 95 | #define P11_PushPull_Mode do{P1M1&=~SET_BIT1;P1M2|=SET_BIT1;}while(0) 96 | #define P12_PushPull_Mode do{P1M1&=~SET_BIT2;P1M2|=SET_BIT2;}while(0) 97 | #define P13_PushPull_Mode do{P1M1&=~SET_BIT3;P1M2|=SET_BIT3;}while(0) 98 | #define P14_PushPull_Mode do{P1M1&=~SET_BIT4;P1M2|=SET_BIT4;}while(0) 99 | #define P15_PushPull_Mode do{P1M1&=~SET_BIT5;P1M2|=SET_BIT5;}while(0) 100 | #define P16_PushPull_Mode do{P1M1&=~SET_BIT6;P1M2|=SET_BIT6;}while(0) 101 | #define P17_PushPull_Mode do{P1M1&=~SET_BIT7;P1M2|=SET_BIT7;}while(0) 102 | #define P30_PushPull_Mode do{P3M1&=~SET_BIT0;P3M2|=SET_BIT0;}while(0) 103 | 104 | // GPIO Input Only mode 105 | #define P00_Input_Mode do{P0M1|=SET_BIT0;P0M2&=~SET_BIT0;}while(0) 106 | #define P01_Input_Mode do{P0M1|=SET_BIT1;P0M2&=~SET_BIT1;}while(0) 107 | #define P02_Input_Mode do{P0M1|=SET_BIT2;P0M2&=~SET_BIT2;}while(0) 108 | #define P03_Input_Mode do{P0M1|=SET_BIT3;P0M2&=~SET_BIT3;}while(0) 109 | #define P04_Input_Mode do{P0M1|=SET_BIT4;P0M2&=~SET_BIT4;}while(0) 110 | #define P05_Input_Mode do{P0M1|=SET_BIT5;P0M2&=~SET_BIT5;}while(0) 111 | #define P06_Input_Mode do{P0M1|=SET_BIT6;P0M2&=~SET_BIT6;}while(0) 112 | #define P07_Input_Mode do{P0M1|=SET_BIT7;P0M2&=~SET_BIT7;}while(0) 113 | #define P10_Input_Mode do{P1M1|=SET_BIT0;P1M2&=~SET_BIT0;}while(0) 114 | #define P11_Input_Mode do{P1M1|=SET_BIT1;P1M2&=~SET_BIT1;}while(0) 115 | #define P12_Input_Mode do{P1M1|=SET_BIT2;P1M2&=~SET_BIT2;}while(0) 116 | #define P13_Input_Mode do{P1M1|=SET_BIT3;P1M2&=~SET_BIT3;}while(0) 117 | #define P14_Input_Mode do{P1M1|=SET_BIT4;P1M2&=~SET_BIT4;}while(0) 118 | #define P15_Input_Mode do{P1M1|=SET_BIT5;P1M2&=~SET_BIT5;}while(0) 119 | #define P16_Input_Mode do{P1M1|=SET_BIT6;P1M2&=~SET_BIT6;}while(0) 120 | #define P17_Input_Mode do{P1M1|=SET_BIT7;P1M2&=~SET_BIT7;}while(0) 121 | #define P30_Input_Mode do{P3M1|=SET_BIT0;P3M2&=~SET_BIT0;}while(0) 122 | 123 | // GPIO as Open Drain mode 124 | #define P00_OpenDrain_Mode do{P0M1|=SET_BIT0;P0M2|=SET_BIT0;}while(0) 125 | #define P01_OpenDrain_Mode do{P0M1|=SET_BIT1;P0M2|=SET_BIT1;}while(0) 126 | #define P02_OpenDrain_Mode do{P0M1|=SET_BIT2;P0M2|=SET_BIT2;}while(0) 127 | #define P03_OpenDrain_Mode do{P0M1|=SET_BIT3;P0M2|=SET_BIT3;}while(0) 128 | #define P04_OpenDrain_Mode do{P0M1|=SET_BIT4;P0M2|=SET_BIT4;}while(0) 129 | #define P05_OpenDrain_Mode do{P0M1|=SET_BIT5;P0M2|=SET_BIT5;}while(0) 130 | #define P06_OpenDrain_Mode do{P0M1|=SET_BIT6;P0M2|=SET_BIT6;}while(0) 131 | #define P07_OpenDrain_Mode do{P0M1|=SET_BIT7;P0M2|=SET_BIT7;}while(0) 132 | #define P10_OpenDrain_Mode do{P1M1|=SET_BIT0;P1M2|=SET_BIT0;}while(0) 133 | #define P11_OpenDrain_Mode do{P1M1|=SET_BIT1;P1M2|=SET_BIT1;}while(0) 134 | #define P12_OpenDrain_Mode do{P1M1|=SET_BIT2;P1M2|=SET_BIT2;}while(0) 135 | #define P13_OpenDrain_Mode do{P1M1|=SET_BIT3;P1M2|=SET_BIT3;}while(0) 136 | #define P14_OpenDrain_Mode do{P1M1|=SET_BIT4;P1M2|=SET_BIT4;}while(0) 137 | #define P15_OpenDrain_Mode do{P1M1|=SET_BIT5;P1M2|=SET_BIT5;}while(0) 138 | #define P16_OpenDrain_Mode do{P1M1|=SET_BIT6;P1M2|=SET_BIT6;}while(0) 139 | #define P17_OpenDrain_Mode do{P1M1|=SET_BIT7;P1M2|=SET_BIT7;}while(0) 140 | #define P30_OpenDrain_Mode do{P3M1|=SET_BIT0;P3M2|=SET_BIT0;}while(0) 141 | 142 | // GPIO all quasi mode 143 | #define Set_All_GPIO_Quasi_Mode do{P0M1=0;P0M2=0;P1M1=0;P1M2=0;P3M1=0;P3M2=0;}while(0) 144 | 145 | // Enable INT GPIO port 0~3 146 | #define Enable_INT_Port0 do{clr_PIPS1;clr_PIPS0;}while(0) 147 | #define Enable_INT_Port1 do{clr_PIPS1;set_PIPS0;}while(0) 148 | #define Enable_INT_Port2 do{set_PIPS1;clr_PIPS0;}while(0) 149 | #define Enable_INT_Port3 do{set_PIPS1;set_PIPS0;}while(0) 150 | 151 | // Enable each bit low level trig mode 152 | #define Enable_BIT7_LowLevel_Trig do{PICON&=0x7F;PINEN|=0x80;PIPEN&=0x7F;}while(0) 153 | #define Enable_BIT6_LowLevel_Trig do{PICON&=0x7F;PINEN|=0x40;PIPEN&=0xBF;}while(0) 154 | #define Enable_BIT5_LowLevel_Trig do{PICON&=0xBF;PINEN|=0x20;PIPEN&=0xDF;}while(0) 155 | #define Enable_BIT4_LowLevel_Trig do{PICON&=0xBF;PINEN|=0x10;PIPEN&=0xEF;}while(0) 156 | #define Enable_BIT3_LowLevel_Trig do{PICON&=0xDF;PINEN|=0x08;PIPEN&=0xF7;}while(0) 157 | #define Enable_BIT2_LowLevel_Trig do{PICON&=0xEF;PINEN|=0x04;PIPEN&=0xFB;}while(0) 158 | #define Enable_BIT1_LowLevel_Trig do{PICON&=0xF7;PINEN|=0x02;PIPEN&=0xFD;}while(0) 159 | #define Enable_BIT0_LowLevel_Trig do{PICON&=0xFD;PINEN|=0x01;PIPEN&=0xFE;}while(0) 160 | 161 | // Enable each bit high level trig mode 162 | #define Enable_BIT7_HighLevel_Trig do{PICON&=0x7F;PINEN&=0x7F;PIPEN|=0x80;}while(0) 163 | #define Enable_BIT6_HighLevel_Trig do{PICON&=0x7F;PINEN&=0xBF;PIPEN|=0x40;}while(0) 164 | #define Enable_BIT5_HighLevel_Trig do{PICON&=0xBF;PINEN&=0xDF;PIPEN|=0x20;}while(0) 165 | #define Enable_BIT4_HighLevel_Trig do{PICON&=0xBF;PINEN&=0xEF;PIPEN|=0x10;}while(0) 166 | #define Enable_BIT3_HighLevel_Trig do{PICON&=0xDF;PINEN&=0xF7;PIPEN|=0x08;}while(0) 167 | #define Enable_BIT2_HighLevel_Trig do{PICON&=0xEF;PINEN&=0xFB;PIPEN|=0x04;}while(0) 168 | #define Enable_BIT1_HighLevel_Trig do{PICON&=0xF7;PINEN&=0xFD;PIPEN|=0x02;}while(0) 169 | #define Enable_BIT0_HighLevel_Trig do{PICON&=0xFD;PINEN&=0xFE;PIPEN|=0x01;}while(0) 170 | 171 | // Enable each bit falling edge trig mode 172 | #define Enable_BIT7_FallEdge_Trig do{PICON|=0x80;PINEN|=0x80;PIPEN&=0x7F;}while(0) 173 | #define Enable_BIT6_FallEdge_Trig do{PICON|=0x80;PINEN|=0x40;PIPEN&=0xBF;}while(0) 174 | #define Enable_BIT5_FallEdge_Trig do{PICON|=0x40;PINEN|=0x20;PIPEN&=0xDF;}while(0) 175 | #define Enable_BIT4_FallEdge_Trig do{PICON|=0x40;PINEN|=0x10;PIPEN&=0xEF;}while(0) 176 | #define Enable_BIT3_FallEdge_Trig do{PICON|=0x20;PINEN|=0x08;PIPEN&=0xF7;}while(0) 177 | #define Enable_BIT2_FallEdge_Trig do{PICON|=0x10;PINEN|=0x04;PIPEN&=0xFB;}while(0) 178 | #define Enable_BIT1_FallEdge_Trig do{PICON|=0x08;PINEN|=0x02;PIPEN&=0xFD;}while(0) 179 | #define Enable_BIT0_FallEdge_Trig do{PICON|=0x04;PINEN|=0x01;PIPEN&=0xFE;}while(0) 180 | 181 | // Enable each bit rasing edge trig mode 182 | #define Enable_BIT7_RasingEdge_Trig do{PICON|=0x80;PINEN&=0x7F;PIPEN|=0x80;}while(0) 183 | #define Enable_BIT6_RasingEdge_Trig do{PICON|=0x80;PINEN&=0xBF;PIPEN|=0x40;}while(0) 184 | #define Enable_BIT5_RasingEdge_Trig do{PICON|=0x40;PINEN&=0xDF;PIPEN|=0x20;}while(0) 185 | #define Enable_BIT4_RasingEdge_Trig do{PICON|=0x40;PINEN&=0xEF;PIPEN|=0x10;}while(0) 186 | #define Enable_BIT3_RasingEdge_Trig do{PICON|=0x20;PINEN&=0xF7;PIPEN|=0x08;}while(0) 187 | #define Enable_BIT2_RasingEdge_Trig do{PICON|=0x10;PINEN&=0xFB;PIPEN|=0x04;}while(0) 188 | #define Enable_BIT1_RasingEdge_Trig do{PICON|=0x08;PINEN&=0xFD;PIPEN|=0x02;}while(0) 189 | #define Enable_BIT0_RasingEdge_Trig do{PICON|=0x04;PINEN&=0xFE;PIPEN|=0x01;}while(0) 190 | 191 | // TIMER_DIVs 192 | #if defined(FOSC_110592) // Fsys = 11.0592MHz 193 | #define TIMER_DIV12_VALUE_10us 65536-9 //9*12/11.0592 = 10 us Timer divider = 12 for TM0/TM1 194 | #define TIMER_DIV12_VALUE_1ms 65536-923 //923*12/11.0592 = 1 ms Timer divider = 12 195 | #define TIMER_DIV12_VALUE_10ms 65536-9216 //18432*12/22118400 = 10 ms Timer divider = 12 196 | #define TIMER_DIV4_VALUE_10us 65536-28 //28*4/11.0592 = 10 us Timer divider = 4 for TM2/TM3 197 | #define TIMER_DIV4_VALUE_1ms 65536-2765 //2765*4/11.0592 = 1 ms Timer divider = 4 198 | #define TIMER_DIV4_VALUE_100us 65536-277 //553*4/22118400 = 100 us Timer divider = 4 199 | #define TIMER_DIV4_VALUE_200us 65536-553 //1106*4/22118400 = 200 us Timer divider = 4 200 | #define TIMER_DIV4_VALUE_500us 65536-1383 //2765*4/22118400 = 500 us Timer divider = 4 201 | #define TIMER_DIV16_VALUE_10ms 65536-6912 //1500*16/22118400 = 10 ms Timer divider = 16 202 | #define TIMER_DIV64_VALUE_30ms 65536-5184 //10368*64/22118400 = 30 ms Timer divider = 64 203 | #define TIMER_DIV128_VALUE_100ms 65536-8640 //17280*128/22118400 = 100 ms Timer divider = 128 204 | #define TIMER_DIV128_VALUE_200ms 65536-17280 //34560*128/22118400 = 200 ms Timer divider = 128 205 | #define TIMER_DIV256_VALUE_500ms 65536-21600 //43200*256/22118400 = 500 ms Timer divider = 256 206 | #define TIMER_DIV512_VALUE_1s 65536-21600 //43200*512/22118400 = 1 s Timer divider = 512 207 | #elif defined(FOSC_160000) // Fsys = 16MHz 208 | #define TIMER_DIV12_VALUE_10us 65536-13 //13*12/16000000 = 10 us Timer divider = 12 for TM0/TM1 209 | #define TIMER_DIV12_VALUE_100us 65536-130 //130*12/16000000 = 10 us Timer divider = 12 210 | #define TIMER_DIV12_VALUE_1ms 65536-1334 //1334*12/16000000 = 1 ms Timer divider = 12 211 | #define TIMER_DIV12_VALUE_10ms 65536-13334 //13334*12/16000000 = 10 ms Timer divider = 12 212 | #define TIMER_DIV12_VALUE_40ms 65536-53336 //53336*12/16000000 = 40 ms Timer divider = 12 213 | #define TIMER_DIV4_VALUE_10us 65536-40 //40*4/16000000 = 10 us Timer divider = 4 for TM2/TM3 214 | #define TIMER_DIV4_VALUE_100us 65536-400 //400*4/16000000 = 100 us Timer divider = 4 215 | #define TIMER_DIV4_VALUE_200us 65536-800 //800*4/16000000 = 200 us Timer divider = 4 216 | #define TIMER_DIV4_VALUE_500us 65536-2000 //2000*4/16000000 = 500 us Timer divider = 4 217 | #define TIMER_DIV4_VALUE_1ms 65536-4000 //4000*4/16000000 = 1 ms Timer divider = 4 218 | #define TIMER_DIV16_VALUE_10ms 65536-10000 //10000*16/16000000 = 10 ms Timer divider = 16 219 | #define TIMER_DIV64_VALUE_30ms 65536-7500 //7500*64/16000000 = 30 ms Timer divider = 64 220 | #define TIMER_DIV128_VALUE_100ms 65536-12500 //12500*128/16000000 = 100 ms Timer divider = 128 221 | #define TIMER_DIV128_VALUE_200ms 65536-25000 //25000*128/16000000 = 200 ms Timer divider = 128 222 | #define TIMER_DIV256_VALUE_500ms 65536-31250 //31250*256/16000000 = 500 ms Timer divider = 256 223 | #define TIMER_DIV512_VALUE_1s 65536-31250 //31250*512/16000000 = 1 s Timer Divider = 512 224 | #elif defined(FOSC_184320) // Fsys = 18.432MHz 225 | #define TIMER_DIV12_VALUE_10us 65536-15 //15*12/18.432 = 10 us Timer Clock = Fsys/12 226 | #define TIMER_DIV12_VALUE_1ms 65536-1536 //1536*12/18.432 = 1 ms Timer Clock = Fsys/12 227 | #define TIMER_DIV4_VALUE_10us 65536-46 //46*4/18.432 = 10 us Timer Clock = Fsys/4 228 | #define TIMER_DIV4_VALUE_1ms 65536-4608 //4608*4/18.432 = 1 ms Timer Clock = Fsys/4 229 | #elif defined(FOSC_200000) // Fsys = 20 MHz 230 | #define TIMER_DIV12_VALUE_10us 65536-17 //17*12/20000000 = 10 us Timer Clock = Fsys/12 231 | #define TIMER_DIV12_VALUE_1ms 65536-1667 //1667*12/20000000 = 1 ms Timer Clock = Fsys/12 232 | #define TIMER_DIV4_VALUE_10us 65536-50 //50*4/20000000 = 10 us Timer Clock = Fsys/4 233 | #define TIMER_DIV4_VALUE_1ms 65536-5000 //5000*4/20000000 = 1 ms Timer Clock = Fsys/4 234 | #elif defined(FOSC_221184) // Fsys = 22.1184 MHz 235 | #define TIMER_DIV12_VALUE_10us 65536-18 //18*12/22118400 = 10 us Timer divider = 12 236 | #define TIMER_DIV12_VALUE_1ms 65536-1843 //1843*12/22118400 = 1 ms Timer divider = 12 237 | #define TIMER_DIV12_VALUE_10ms 65536-18432 //18432*12/22118400 = 10 ms Timer divider = 12 238 | #define TIMER_DIV4_VALUE_10us 65536-56 //9*4/22118400 = 10 us Timer divider = 4 239 | #define TIMER_DIV4_VALUE_1ms 65536-5530 //923*4/22118400 = 1 ms Timer divider = 4 240 | #define TIMER_DIV4_VALUE_100us 65536-553 //553*4/22118400 = 100 us Timer divider = 4 241 | #define TIMER_DIV4_VALUE_200us 65536-1106 //1106*4/22118400 = 200 us Timer divider = 4 242 | #define TIMER_DIV4_VALUE_500us 65536-2765 //2765*4/22118400 = 500 us Timer divider = 4 243 | #define TIMER_DIV16_VALUE_10ms 65536-13824 //1500*16/22118400 = 10 ms Timer divider = 16 244 | #define TIMER_DIV64_VALUE_30ms 65536-10368 //10368*64/22118400 = 30 ms Timer divider = 64 245 | #define TIMER_DIV128_VALUE_100ms 65536-17280 //17280*128/22118400 = 100 ms Timer divider = 128 246 | #define TIMER_DIV128_VALUE_200ms 65536-34560 //34560*128/22118400 = 200 ms Timer divider = 128 247 | #define TIMER_DIV256_VALUE_500ms 65536-43200 //43200*256/22118400 = 500 ms Timer divider = 256 248 | #define TIMER_DIV512_VALUE_1s 65536-43200 //43200*512/22118400 = 1 s Timer divider = 512 249 | #elif defined(FOSC_240000) // if Fsys = 20 MHz 250 | #define TIMER_DIV12_VALUE_10us 65536-20 //20*12/24000000 = 10 us Timer divider = 12 251 | #define TIMER_DIV12_VALUE_1ms 65536-2000 //2000*12/24000000 = 1 ms Timer divider = 12 252 | #define TIMER_DIV12_VALUE_10ms 65536-20000 //2000*12/24000000 = 10 ms Timer divider = 12 253 | #define TIMER_DIV4_VALUE_10us 65536-60 //60*4/24000000 = 10 us Timer divider = 4 254 | #define TIMER_DIV4_VALUE_100us 65536-600 //600*4/24000000 = 100 us Timer divider = 4 255 | #define TIMER_DIV4_VALUE_200us 65536-1200 //1200*4/24000000 = 200 us Timer divider = 4 256 | #define TIMER_DIV4_VALUE_500us 65536-3000 //3000*4/24000000 = 500 us Timer divider = 4 257 | #define TIMER_DIV4_VALUE_1ms 65536-6000 //6000*4/24000000 = 1 ms Timer divider = 4 258 | #define TIMER_DIV16_VALUE_10ms 65536-15000 //15000*16/24000000 = 10 ms Timer divider = 16 259 | #define TIMER_DIV64_VALUE_30ms 65536-11250 //11250*64/24000000 = 30 ms Timer divider = 64 260 | #define TIMER_DIV128_VALUE_100ms 65536-18750 //37500*128/24000000 = 200 ms Timer divider = 128 261 | #define TIMER_DIV128_VALUE_200ms 65536-37500 //37500*128/24000000 = 200 ms Timer divider = 128 262 | #define TIMER_DIV256_VALUE_500ms 65536-46875 //46875*256/24000000 = 500 ms Timer divider = 256 263 | #define TIMER_DIV512_VALUE_1s 65536-46875 //46875*512/24000000 = 1 s Timer Divider = 512 264 | #endif 265 | 266 | // Timer0 267 | #define TIMER0_MODE0_ENABLE TMOD&=0xF0 268 | #define TIMER0_MODE1_ENABLE do{TMOD&=0xF0;TMOD|=0x01;}while(0) 269 | #define TIMER0_MODE2_ENABLE do{TMOD&=0xF0;TMOD|=0x02;}while(0) 270 | #define TIMER0_MODE3_ENABLE do{TMOD&=0xF0;TMOD|=0x03;}while(0) 271 | 272 | // Timer1 273 | #define TIMER1_MODE0_ENABLE TMOD&=0x0F 274 | #define TIMER1_MODE1_ENABLE do{TMOD&=0x0F;TMOD|=0x10;}while(0) 275 | #define TIMER1_MODE2_ENABLE do{TMOD&=0x0F;TMOD|=0x20;}while(0) 276 | #define TIMER1_MODE3_ENABLE do{TMOD&=0x0F;TMOD|=0x30;}while(0) 277 | 278 | // Timer2 279 | #define TIMER2_DIV_4 do{T2MOD|=0x10;T2MOD&=0x9F;}while(0) 280 | #define TIMER2_DIV_16 do{T2MOD|=0x20;T2MOD&=0xAF;}while(0) 281 | #define TIMER2_DIV_32 do{T2MOD|=0x30;T2MOD&=0xBF;}while(0) 282 | #define TIMER2_DIV_64 do{T2MOD|=0x40;T2MOD&=0xCF;}while(0) 283 | #define TIMER2_DIV_128 do{T2MOD|=0x50;T2MOD&=0xDF;}while(0) 284 | #define TIMER2_DIV_256 do{T2MOD|=0x60;T2MOD&=0xEF;}while(0) 285 | #define TIMER2_DIV_512 T2MOD|=0x70 286 | #define TIMER2_Auto_Reload_Delay_Mode do{T2CON&=~SET_BIT0;T2MOD|=SET_BIT7;T2MOD|=SET_BIT3;}while(0) 287 | #define TIMER2_Compare_Capture_Mode do{T2CON|=SET_BIT0;T2MOD&=~SET_BIT7;T2MOD|=SET_BIT2;}while(0) 288 | #define TIMER2_CAP0_Capture_Mode do{T2CON&=~SET_BIT0;T2MOD=0x89;}while(0) 289 | #define TIMER2_CAP1_Capture_Mode do{T2CON&=~SET_BIT0;T2MOD=0x8A;}while(0) 290 | #define TIMER2_CAP2_Capture_Mode do{T2CON&=~SET_BIT0;T2MOD=0x8B;}while(0) 291 | 292 | // Timer2 Capture 293 | // Falling Edge 294 | #define IC0_P12_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 295 | #define IC1_P11_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 296 | #define IC2_P10_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 297 | #define IC3_P00_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 298 | #define IC3_P04_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 299 | #define IC4_P01_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 300 | #define IC5_P03_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 301 | #define IC6_P05_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 302 | #define IC7_P15_CAP0_FallingEdge_Capture do{CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 303 | 304 | #define IC0_P12_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 305 | #define IC1_P11_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON0|=SET_BIT5;}while(0) 306 | #define IC2_P10_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 307 | #define IC3_P00_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 308 | #define IC3_P04_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 309 | #define IC4_P01_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 310 | #define IC5_P03_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 311 | #define IC6_P05_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 312 | #define IC7_P15_CAP1_FallingEdge_Capture do{CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 313 | 314 | #define IC0_P12_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 315 | #define IC1_P11_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x10;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 316 | #define IC2_P10_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x20;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 317 | #define IC3_P00_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x30;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 318 | #define IC3_P04_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x40;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 319 | #define IC4_P01_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x50;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 320 | #define IC5_P03_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x60;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 321 | #define IC6_P05_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x70;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 322 | #define IC7_P15_CAP2_FallingEdge_Capture do{CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x80;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 323 | 324 | // Rising edge 325 | #define IC0_P12_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 326 | #define IC1_P11_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 327 | #define IC2_P10_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 328 | #define IC3_P00_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 329 | #define IC3_P04_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 330 | #define IC4_P01_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 331 | #define IC5_P03_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 332 | #define IC6_P05_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 333 | #define IC7_P15_CAP0_RisingEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 334 | 335 | #define IC0_P12_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 336 | #define IC1_P11_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 337 | #define IC2_P10_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 338 | #define IC3_P00_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 339 | #define IC3_P04_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 340 | #define IC4_P01_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 341 | #define IC5_P03_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 342 | #define IC6_P05_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 343 | #define IC7_P15_CAP1_RisingEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 344 | 345 | #define IC0_P12_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 346 | #define IC1_P11_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x01;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 347 | #define IC2_P10_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x02;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 348 | #define IC3_P00_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x03;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 349 | #define IC3_P04_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x04;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 350 | #define IC4_P01_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x05;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 351 | #define IC5_P03_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x06;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 352 | #define IC6_P05_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x07;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 353 | #define IC7_P15_CAP3_RisingEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x08;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 354 | 355 | // Both edge 356 | #define IC0_P12_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 357 | #define IC1_P11_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 358 | #define IC2_P10_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 359 | #define IC3_P00_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 360 | #define IC3_P04_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 361 | #define IC4_P01_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 362 | #define IC5_P03_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 363 | #define IC6_P05_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 364 | #define IC7_P15_CAP0_BothEdge_Capture do{CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;}while(0) 365 | 366 | #define IC0_P12_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 367 | #define IC1_P11_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 368 | #define IC2_P10_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 369 | #define IC3_P00_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 370 | #define IC3_P04_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 371 | #define IC4_P01_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 372 | #define IC5_P03_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 373 | #define IC6_P05_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 374 | #define IC7_P15_CAP1_BothEdge_Capture do{CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;}while(0) 375 | 376 | #define IC0_P12_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 377 | #define IC1_P11_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x01;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 378 | #define IC2_P10_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x02;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 379 | #define IC3_P00_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x03;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 380 | #define IC3_P04_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x04;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 381 | #define IC4_P01_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x05;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 382 | #define IC5_P03_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x06;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 383 | #define IC6_P05_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x07;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 384 | #define IC7_P15_CAP3_BothEdge_Capture do{CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x08;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;}while(0) 385 | 386 | #define TIMER2_IC2_DISABLE CAPCON0&=~SET_BIT6 387 | #define TIMER2_IC1_DISABLE CAPCON0&=~SET_BIT5 388 | #define TIMER2_IC0_DISABLE CAPCON0&=~SET_BIT4 389 | 390 | // PMW clock source select 391 | #define PWM_CLOCK_FSYS CKCON&=0xBF 392 | #define PWM_CLOCK_TIMER1 CKCON|=0x40 393 | 394 | // PWM clock devide 395 | #define PWM_CLOCK_DIV_2 do{PWMCON1|=0x01;PWMCON1&=0xF9;}while(0) 396 | #define PWM_CLOCK_DIV_4 do{PWMCON1|=0x02;PWMCON1&=0xFA;}while(0) 397 | #define PWM_CLOCK_DIV_8 do{PWMCON1|=0x03;PWMCON1&=0xFB;}while(0) 398 | #define PWM_CLOCK_DIV_16 do{PWMCON1|=0x04;PWMCON1&=0xFC;}while(0) 399 | #define PWM_CLOCK_DIV_32 do{PWMCON1|=0x05;PWMCON1&=0xFD;}while(0) 400 | #define PWM_CLOCK_DIV_64 do{PWMCON1|=0x06;PWMCON1&=0xFE;}while(0) 401 | #define PWM_CLOCK_DIV_128 PWMCON1|=0x07 402 | 403 | // PWM I/O select 404 | #define PWM5_P15_OUTPUT_ENABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x20;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P1.5 as PWM5 output enable 405 | #define PWM5_P03_OUTPUT_ENABLE PIOCON0|=0x20 //P0.3 as PWM5 406 | #define PWM4_P01_OUTPUT_ENABLE PIOCON0|=0x10 //P0.1 as PWM4 output enable 407 | #define PWM3_P04_OUTPUT_ENABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x08;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P0.4 as PWM3 output enable 408 | #define PWM3_P00_OUTPUT_ENABLE PIOCON0|=0x08 //P0.0 as PWM3 409 | #define PWM2_P05_OUTPUT_ENABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x04;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P1.0 as PWM2 output enable 410 | #define PWM2_P10_OUTPUT_ENABLE PIOCON0|=0x04 //P1.0 as PWM2 411 | #define PWM1_P14_OUTPUT_ENABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x02;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P1.4 as PWM1 output enable 412 | #define PWM1_P11_OUTPUT_ENABLE PIOCON0|=0x02 //P1.1 as PWM1 413 | #define PWM0_P12_OUTPUT_ENABLE PIOCON0|=0x01 //P1.2 as PWM0 output enable 414 | #define ALL_PWM_OUTPUT_ENABLE do{PIOCON0=0xFF;PIOCON1=0xFF;}while(0) 415 | #define PWM5_P15_OUTPUT_DISABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xDF;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P1.5 as PWM5 output disable 416 | #define PWM5_P03_OUTPUT_DISABLE PIOCON0&=0xDF //P0.3 as PWM5 417 | #define PWM4_P01_OUTPUT_DISABLE PIOCON0&=0xEF //P0.1 as PWM4 output disable 418 | #define PWM3_P04_OUTPUT_DISABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xF7;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P0.4 as PWM3 output disable 419 | #define PWM3_P00_OUTPUT_DISABLE PIOCON0&=0xF7 //P0.0 as PWM3 420 | #define PWM2_P05_OUTPUT_DISABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xFB;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P1.0 as PWM2 output disable 421 | #define PWM2_P10_OUTPUT_DISABLE PIOCON0&=0xFB //P1.0 as PWM2 422 | #define PWM1_P14_OUTPUT_DISABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xFD;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;}while(0) //P1.4 as PWM1 output disable 423 | #define PWM1_P11_OUTPUT_DISABLE PIOCON0&=0xFD //P1.1 as PWM1 424 | #define PWM0_P12_OUTPUT_DISABLE PIOCON0&=0xFE //P1.2 as PWM0 output disable 425 | #define ALL_PWM_OUTPUT_DISABLE do{PIOCON0=0x00;PIOCON1=0x00;}while(0) 426 | 427 | // PWM I/O Polarity Control 428 | #define PWM5_OUTPUT_INVERSE PNP|=0x20 429 | #define PWM4_OUTPUT_INVERSE PNP|=0x10 430 | #define PWM3_OUTPUT_INVERSE PNP|=0x08 431 | #define PWM2_OUTPUT_INVERSE PNP|=0x04 432 | #define PWM1_OUTPUT_INVERSE PNP|=0x02 433 | #define PWM0_OUTPUT_INVERSE PNP|=0x01 434 | #define PWM_OUTPUT_ALL_INVERSE PNP=0xFF 435 | #define PWM5_OUTPUT_NORMAL PNP&=0xDF 436 | #define PWM4_OUTPUT_NORMAL PNP&=0xEF 437 | #define PWM3_OUTPUT_NORMAL PNP&=0xF7 438 | #define PWM2_OUTPUT_NORMAL PNP&=0xFB 439 | #define PWM1_OUTPUT_NORMAL PNP&=0xFD 440 | #define PWM0_OUTPUT_NORMAL PNP&=0xFE 441 | #define PWM_OUTPUT_ALL_NORMAL PNP=0x00 442 | 443 | // PWM type 444 | #define PWM_EDGE_TYPE PWMCON1&=~SET_BIT4 445 | #define PWM_CENTER_TYPE PWMCON1|=SET_BIT4 446 | 447 | // PWM mode 448 | #define PWM_IMDEPENDENT_MODE PWMCON1&=0x3F 449 | #define PWM_COMPLEMENTARY_MODE do{PWMCON1|=0x40;PWMCON1&=0x7F;}while(0) 450 | #define PWM_SYNCHRONIZED_MODE do{PWMCON1|=0x80;PWMCON1&=0xBF;}while(0) 451 | #define PWM_GP_MODE_ENABLE PWMCON1|=0x20 452 | #define PWM_GP_MODE_DISABLE PWMCON1&=0xDF 453 | 454 | // PMW interrupt setting 455 | #define PWM_FALLING_INT do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xCF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 456 | #define PWM_RISING_INT do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x10;PWMCON0&=0xDF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 457 | #define PWM_CENTRAL_POINT_INT do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x20;PWMCON0&=0xEF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 458 | #define PWM_PERIOD_END_INT do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x30;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 459 | 460 | // PWM interrupt pin select 461 | #define PWM_INT_PWM0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 462 | #define PWM_INT_PWM1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x01;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 463 | #define PWM_INT_PWM2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x02;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 464 | #define PWM_INT_PWM3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x03;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 465 | #define PWM_INT_PWM4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x04;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 466 | #define PWM_INT_PWM5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x05;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 467 | 468 | // PWM Dead time setting 469 | #define PWM45_DEADTIME_ENABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x04;EA=BIT_TMP;}while(0) 470 | #define PWM34_DEADTIME_ENABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x02;EA=BIT_TMP;}while(0) 471 | #define PWM01_DEADTIME_ENABLE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x01;EA=BIT_TMP;}while(0) 472 | 473 | // For ADC INIT setting 474 | #define Enable_ADC_AIN0 do{ADCCON0&=0xF0;P17_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT0;ADCCON1|=SET_BIT0;}while(0) //P17 475 | #define Enable_ADC_AIN1 do{ADCCON0&=0xF0;ADCCON0|=0x01;P30_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT1;ADCCON1|=SET_BIT0;}while(0) //P30 476 | #define Enable_ADC_AIN2 do{ADCCON0&=0xF0;ADCCON0|=0x02;P07_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT2;ADCCON1|=SET_BIT0;}while(0) //P07 477 | #define Enable_ADC_AIN3 do{ADCCON0&=0xF0;ADCCON0|=0x03;P06_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT3;ADCCON1|=SET_BIT0;}while(0) //P06 478 | #define Enable_ADC_AIN4 do{ADCCON0&=0xF0;ADCCON0|=0x04;P05_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT4;ADCCON1|=SET_BIT0;}while(0) //P05 479 | #define Enable_ADC_AIN5 do{ADCCON0&=0xF0;ADCCON0|=0x05;P04_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT5;ADCCON1|=SET_BIT0;}while(0) //P04 480 | #define Enable_ADC_AIN6 do{ADCCON0&=0xF0;ADCCON0|=0x06;P03_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT6;ADCCON1|=SET_BIT0;}while(0) //P03 481 | #define Enable_ADC_AIN7 do{ADCCON0&=0xF0;ADCCON0|=0x07;P11_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT7;ADCCON1|=SET_BIT0;}while(0) //P11 482 | #define Enable_ADC_BandGap do{ADCCON0|=SET_BIT3;ADCCON0&=0xF8;ADCCON1|=SET_BIT0 //Band-gap 1.22V 483 | #define Disable_ADC ADCCON1&=0xFE; 484 | 485 | #define PWM0_FALLINGEDGE_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 486 | #define PWM2_FALLINGEDGE_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 487 | #define PWM4_FALLINGEDGE_TRIG_ADC do{ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 488 | #define PWM0_RISINGEDGE_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 489 | #define PWM2_RISINGEDGE_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 490 | #define PWM4_RISINGEDGE_TRIG_ADC do{ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 491 | #define PWM0_CENTRAL_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 492 | #define PWM2_CENTRAL_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 493 | #define PWM4_CENTRAL_TRIG_ADC do{ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 494 | #define PWM0_END_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 495 | #define PWM2_END_TRIG_ADC do{ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 496 | #define PWM4_END_TRIG_ADC do{ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;}while(0) 497 | 498 | #define P04_FALLINGEDGE_TRIG_ADC do{ADCCON0|=0x30;ADCCON1&=0xF3;ADCCON1|=SET_BIT1;ADCCON1&=~SET_BIT6;}while(0) 499 | #define P13_FALLINGEDGE_TRIG_ADC do{ADCCON0|=0x30;ADCCON1&=0xF3;ADCCON1|=SET_BIT1;ADCCON1|=SET_BIT6;}while(0) 500 | #define P04_RISINGEDGE_TRIG_ADC do{ADCCON0|=0x30;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;ADCCON1&=~SET_BIT6;}while(0) 501 | #define P13_RISINGEDGE_TRIG_ADC do{ADCCON0|=0x30;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;ADCCON1|=SET_BIT6;}while(0) 502 | 503 | // For SPI INIT setting 504 | #define SPICLK_DIV2 do{clr_SPR0;clr_SPR1;}while(0) 505 | #define SPICLK_DIV4 do{set_SPR0;clr_SPR1;}while(0) 506 | #define SPICLK_DIV8 do{clr_SPR0;set_SPR1;}while(0) 507 | #define SPICLK_DIV16 do{set_SPR0;set_SPR1;}while(0) 508 | #define Enable_SPI_Interrupt do{set_ESPI;set_EA;}while(0) 509 | #define SS P15 510 | 511 | #define Disable_POR do{TA=0xAA;TA=0x55;PORDIS=0x5A;TA=0xAA;TA=0x55;PORDIS=0xA5;}while(0) 512 | 513 | #endif 514 | -------------------------------------------------------------------------------- /lib/N76E003/SFR_Macro.h: -------------------------------------------------------------------------------- 1 | #ifndef _SFR_Macro_H_ 2 | #define _SFR_Macro_H_ 3 | 4 | #include "N76E003.h" 5 | #include "Common.h" 6 | 7 | extern bit_t BIT_TMP; 8 | 9 | // P0 80H 10 | #define set_P00 P00=1 11 | #define set_P01 P01=1 12 | #define set_P02 P02=1 13 | #define set_P03 P03=1 14 | #define set_P04 P04=1 15 | #define set_P05 P05=1 16 | #define set_P06 P06=1 17 | #define set_P07 P07=1 18 | #define clr_P00 P00=0 19 | #define clr_P01 P01=0 20 | #define clr_P02 P02=0 21 | #define clr_P03 P03=0 22 | #define clr_P04 P04=0 23 | #define clr_P05 P05=0 24 | #define clr_P06 P06=0 25 | #define clr_P07 P07=0 26 | 27 | // PCON 87H 28 | #define set_SMOD PCON|=SET_BIT7 29 | #define set_SMOD0 PCON|=SET_BIT6 30 | #define set_POF PCON|=SET_BIT4 31 | #define set_GF1 PCON|=SET_BIT3 32 | #define set_GF0 PCON|=SET_BIT2 33 | #define set_PD PCON|=SET_BIT1 34 | #define set_IDL PCON|=SET_BIT0 35 | #define clr_SMOD PCON&=~SET_BIT7 36 | #define clr_SMOD0 PCON&=~SET_BIT6 37 | #define clr_POF PCON&=~SET_BIT4 38 | #define clr_GF1 PCON&=~SET_BIT3 39 | #define clr_GF0 PCON&=~SET_BIT2 40 | #define clr_PD PCON&=~SET_BIT1 41 | #define clr_IDL PCON&=~SET_BIT0 42 | 43 | // TCON 88H 44 | #define set_TF1 TF1=1 45 | #define set_TR1 TR1=1 46 | #define set_TF0 TF0=1 47 | #define set_TR0 TR0=1 48 | #define set_IE1 IE1=1 49 | #define set_IT1 IT1=1 50 | #define set_IE0 IE0=1 51 | #define set_IT0 IT0=1 52 | #define clr_TF1 TF1=0 53 | #define clr_TR1 TR1=0 54 | #define clr_TF0 TF0=0 55 | #define clr_TR0 TR0=0 56 | #define clr_IE1 IE1=0 57 | #define clr_IT1 IT1=0 58 | #define clr_IE0 IE0=0 59 | #define clr_IT0 IT0=0 60 | 61 | // TMOD 89H 62 | #define set_GATE_T1 TMOD|=SET_BIT7 63 | #define set_CT_T1 TMOD|=SET_BIT6 64 | #define set_M1_T1 TMOD|=SET_BIT5 65 | #define set_M0_T1 TMOD|=SET_BIT4 66 | #define set_GATE_T0 TMOD|=SET_BIT3 67 | #define set_CT_T0 TMOD|=SET_BIT2 68 | #define set_M1_T0 TMOD|=SET_BIT1 69 | #define set_M0_T0 TMOD|=SET_BIT0 70 | #define clr_GATE_T1 TMOD&=~SET_BIT7 71 | #define clr_CT_T1 TMOD&=~SET_BIT6 72 | #define clr_M1_T1 TMOD&=~SET_BIT5 73 | #define clr_M0_T1 TMOD&=~SET_BIT4 74 | #define clr_GATE_T0 TMOD&=~SET_BIT3 75 | #define clr_CT_T0 TMOD&=~SET_BIT2 76 | #define clr_M1_T0 TMOD&=~SET_BIT1 77 | #define clr_M0_T0 TMOD&=~SET_BIT0 78 | 79 | // CKCON 8EH 80 | #define set_PWMCKS CKCON|=SET_BIT6 81 | #define set_T1M CKCON|=SET_BIT4 82 | #define set_T0M CKCON|=SET_BIT3 83 | #define set_CLOEN CKCON|=SET_BIT1 84 | #define clr_PWMCKS CKCON&=~SET_BIT6 85 | #define clr_T1M CKCON&=~SET_BIT4 86 | #define clr_T0M CKCON&=~SET_BIT3 87 | #define clr_CLOEN CKCON&=~SET_BIT1 88 | 89 | // WKCON 8FH 90 | #define set_WKTCK WKCON|=SET_BIT5 91 | #define set_WKTF WKCON|=SET_BIT4 92 | #define set_WKTR WKCON|=SET_BIT3 93 | #define set_WKPS2 WKCON|=SET_BIT2 94 | #define set_WKPS1 WKCON|=SET_BIT1 95 | #define set_WKPS0 WKCON|=SET_BIT0 96 | #define clr_WKTCK WKCON&=~SET_BIT5 97 | #define clr_WKTF WKCON&=~SET_BIT4 98 | #define clr_WKTR WKCON&=~SET_BIT3 99 | #define clr_WKPS2 WKCON&=~SET_BIT2 100 | #define clr_WKPS1 WKCON&=~SET_BIT1 101 | #define clr_WKPS0 WKCON&=~SET_BIT0 102 | 103 | // P1 90H 104 | #define set_P10 P10=1 105 | #define set_P11 P11=1 106 | #define set_P12 P12=1 107 | #define set_P13 P13=1 108 | #define set_P14 P14=1 109 | #define set_P15 P15=1 110 | #define set_P16 P16=1 111 | #define set_P17 P17=1 112 | #define clr_P10 P10=0 113 | #define clr_P11 P11=0 114 | #define clr_P12 P12=0 115 | #define clr_P13 P13=0 116 | #define clr_P14 P14=0 117 | #define clr_P15 P15=0 118 | #define clr_P16 P16=0 119 | #define clr_P17 P17=0 120 | 121 | // SFRS 91H 122 | #define set_SFRPAGE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=SET_BIT0;EA=BIT_TMP;}while(0) 123 | #define clr_SFRPAGE do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS&=~SET_BIT0;EA=BIT_TMP;}while(0) 124 | 125 | // CAPCON0 92H 126 | #define set_CAPEN2 CAPCON0|=SET_BIT6 127 | #define set_CAPEN1 CAPCON0|=SET_BIT5 128 | #define set_CAPEN0 CAPCON0|=SET_BIT4 129 | #define set_CAPF2 CAPCON0|=SET_BIT2 130 | #define set_CAPF1 CAPCON0|=SET_BIT1 131 | #define set_CAPF0 CAPCON0|=SET_BIT0 132 | #define clr_CAPEN2 CAPCON0&=~SET_BIT6 133 | #define clr_CAPEN1 CAPCON0&=~SET_BIT5 134 | #define clr_CAPEN0 CAPCON0&=~SET_BIT4 135 | #define clr_CAPF2 CAPCON0&=~SET_BIT2 136 | #define clr_CAPF1 CAPCON0&=~SET_BIT1 137 | #define clr_CAPF0 CAPCON0&=~SET_BIT0 138 | 139 | // CAPCON1 93H 140 | #define set_CAP2LS1 CAPCON1|=SET_BIT5 141 | #define set_CAP2LS0 CAPCON1|=SET_BIT4 142 | #define set_CAP1LS1 CAPCON1|=SET_BIT3 143 | #define set_CAP1LS0 CAPCON1|=SET_BIT2 144 | #define set_CAP0LS1 CAPCON1|=SET_BIT1 145 | #define set_CAP0LS0 CAPCON1|=SET_BIT0 146 | #define clr_CAP2LS1 CAPCON1&=~SET_BIT5 147 | #define clr_CAP2LS0 CAPCON1&=~SET_BIT4 148 | #define clr_CAP1LS1 CAPCON1&=~SET_BIT3 149 | #define clr_CAP1LS0 CAPCON1&=~SET_BIT2 150 | #define clr_CAP0LS1 CAPCON1&=~SET_BIT1 151 | #define clr_CAP0LS0 CAPCON1&=~SET_BIT0 152 | 153 | // CAPCON2 94H 154 | #define set_ENF2 CAPCON2|=SET_BIT6 155 | #define set_ENF1 CAPCON2|=SET_BIT5 156 | #define set_ENF0 CAPCON2|=SET_BIT4 157 | #define clr_ENF2 CAPCON2&=~SET_BIT6 158 | #define clr_ENF1 CAPCON2&=~SET_BIT5 159 | #define clr_ENF0 CAPCON2&=~SET_BIT4 160 | 161 | // CKSWT 96H TA protect register 162 | #define set_HIRCST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT5;EA=BIT_TMP;}while(0) 163 | #define set_LIRCST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT4;EA=BIT_TMP;}while(0) 164 | #define set_ECLKST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT3;EA=BIT_TMP;}while(0) 165 | #define set_OSC1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT2;EA=BIT_TMP;}while(0) 166 | #define set_OSC0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT1;EA=BIT_TMP;}while(0) 167 | #define clr_HIRCST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT5;EA=BIT_TMP;}while(0) 168 | #define clr_LIRCST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT4;EA=BIT_TMP;}while(0) 169 | #define clr_ECLKST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT3;EA=BIT_TMP;}while(0) 170 | #define clr_OSC1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT2;EA=BIT_TMP;}while(0) 171 | #define clr_OSC0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT1;EA=BIT_TMP;}while(0) 172 | 173 | // CKEN 97H TA protect register 174 | #define set_EXTEN1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT7;EA=BIT_TMP;}while(0) 175 | #define set_EXTEN0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT6;EA=BIT_TMP;}while(0) 176 | #define set_HIRCEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT5;EA=BIT_TMP;}while(0) 177 | #define set_CKSWTF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT0;EA=BIT_TMP;}while(0) 178 | #define clr_EXTEN1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT7;EA=BIT_TMP;}while(0) 179 | #define clr_EXTEN0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT6;EA=BIT_TMP;}while(0) 180 | #define clr_HIRCEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT5;EA=BIT_TMP;}while(0) 181 | #define clr_CKSWTF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT0;EA=BIT_TMP;}while(0) 182 | 183 | // SCON 98H 184 | #define set_FE FE=1 185 | #define set_SM1 SM1=1 186 | #define set_SM2 SM2=1 187 | #define set_REN REN=1 188 | #define set_TB8 TB8=1 189 | #define set_RB8 RB8=1 190 | #define set_TI TI=1 191 | #define set_RI RI=1 192 | #define clr_FE FE=0 193 | #define clr_SM1 SM1=0 194 | #define clr_SM2 SM2=0 195 | #define clr_REN REN=0 196 | #define clr_TB8 TB8=0 197 | #define clr_RB8 RB8=0 198 | #define clr_TI TI=0 199 | #define clr_RI RI=0 200 | 201 | // EIE 9BH 202 | #define set_ET2 EIE|=SET_BIT7 203 | #define set_ESPI EIE|=SET_BIT6 204 | #define set_EFB EIE|=SET_BIT5 205 | #define set_EWDT EIE|=SET_BIT4 206 | #define set_EPWM EIE|=SET_BIT3 207 | #define set_ECAP EIE|=SET_BIT2 208 | #define set_EPI EIE|=SET_BIT1 209 | #define set_EI2C EIE|=SET_BIT0 210 | #define clr_ET2 EIE&=~SET_BIT7 211 | #define clr_ESPI EIE&=~SET_BIT6 212 | #define clr_EFB EIE&=~SET_BIT5 213 | #define clr_EWDT EIE&=~SET_BIT4 214 | #define clr_EPWM EIE&=~SET_BIT3 215 | #define clr_ECAP EIE&=~SET_BIT2 216 | #define clr_EPI EIE&=~SET_BIT1 217 | #define clr_EI2C EIE&=~SET_BIT0 218 | 219 | // EIE1 9CH 220 | #define set_EWKT EIE1|=SET_BIT2 221 | #define set_ET3 EIE1|=SET_BIT1 222 | #define set_ES_1 EIE1|=SET_BIT0 223 | #define clr_EWKT EIE1&=~SET_BIT2 224 | #define clr_ET3 EIE1&=~SET_BIT1 225 | #define clr_ES_1 EIE1&=~SET_BIT0 226 | 227 | // CHPCON 9DH TA protect register 228 | #define set_SWRST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT7;EA=BIT_TMP;}while(0) 229 | #define set_IAPFF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT6 ;EA=BIT_TMP;}while(0) 230 | #define set_BS do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT1 ;EA=BIT_TMP;}while(0) 231 | #define set_IAPEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT0 ;EA=BIT_TMP;}while(0) 232 | #define clr_SWRST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT7;EA=BIT_TMP;}while(0) 233 | #define clr_IAPFF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT6;EA=BIT_TMP;}while(0) 234 | #define clr_BS do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT1;EA=BIT_TMP;}while(0) 235 | #define clr_IAPEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT0;EA=BIT_TMP;}while(0) 236 | 237 | // AUXR1 A2H 238 | #define set_SWRF AUXR1|=SET_BIT7 239 | #define set_RSTPINF AUXR1|=SET_BIT6 240 | #define set_HARDF AUXR1|=SET_BIT5 241 | #define set_GF2 AUXR1|=SET_BIT3 242 | #define set_UART0PX AUXR1|=SET_BIT2 243 | #define set_DPS AUXR1|=SET_BIT0 244 | #define clr_SWRF AUXR1&=~SET_BIT7 245 | #define clr_RSTPINF AUXR1&=~SET_BIT6 246 | #define clr_HARDF AUXR1&=~SET_BIT5 247 | #define clr_GF2 AUXR1&=~SET_BIT3 248 | #define clr_UART0PX AUXR1&=~SET_BIT2 249 | #define clr_DPS AUXR1&=~SET_BIT0 250 | 251 | // BODCON0 A3H TA protect register 252 | #define set_BODEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT7;EA=BIT_TMP;}while(0) 253 | #define set_BOV1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT5;EA=BIT_TMP;}while(0) 254 | #define set_BOV0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT4;EA=BIT_TMP;}while(0) 255 | #define set_BOF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT3;EA=BIT_TMP;}while(0) 256 | #define set_BORST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT2;EA=BIT_TMP;}while(0) 257 | #define set_BORF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT1;EA=BIT_TMP;}while(0) 258 | #define set_BOS do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT0;EA=BIT_TMP;}while(0) 259 | #define clr_BODEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT7;EA=BIT_TMP;}while(0) 260 | #define clr_BOV2 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT6;EA=BIT_TMP;}while(0) 261 | #define clr_BOV1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT5;EA=BIT_TMP;}while(0) 262 | #define clr_BOV0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT4;EA=BIT_TMP;}while(0) 263 | #define clr_BOF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT3;EA=BIT_TMP;}while(0) 264 | #define clr_BORST do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT2;EA=BIT_TMP;}while(0) 265 | #define clr_BORF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT1;EA=BIT_TMP;}while(0) 266 | #define clr_BOS do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT0;EA=BIT_TMP;}while(0) 267 | 268 | // IAPTRG A4H TA protect register 269 | #define set_IAPGO do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG|=SET_BIT0 ;EA=BIT_TMP;}while(0) 270 | #define clr_IAPGO do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG&=~SET_BIT0;EA=BIT_TMP;}while(0) 271 | 272 | // IAPUEN A5H TA protect register 273 | #define set_CFUEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT2;EA=BIT_TMP;}while(0) 274 | #define set_LDUEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT1;EA=BIT_TMP;}while(0) 275 | #define set_APUEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT0;EA=BIT_TMP;}while(0) 276 | #define clr_CFUEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT2;EA=BIT_TMP_ 277 | #define clr_LDUEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT1;EA=BIT_TMP_ 278 | #define clr_APUEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT0;EA=BIT_TMP_ 279 | 280 | // IE A8H 281 | #define set_EA EA=1 282 | #define set_EADC EADC=1 283 | #define set_EBOD EBOD=1 284 | #define set_ES ES=1 285 | #define set_ET1 ET1=1 286 | #define set_EX1 EX1=1 287 | #define set_ET0 ET0=1 288 | #define set_EX0 EX0=1 289 | #define clr_EA EA=0 290 | #define clr_EADC EADC=0 291 | #define clr_EBOD EBOD=0 292 | #define clr_ES ES=0 293 | #define clr_ET1 ET1=0 294 | #define clr_EX1 EX1=0 295 | #define clr_ET0 ET0=0 296 | #define clr_EX0 EX0=0 297 | 298 | // WDCON AAH TA protect register 299 | #define set_WDTR do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT7;EA=BIT_TMP;}while(0) 300 | #define set_WDCLR do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT6;EA=BIT_TMP;}while(0) 301 | #define set_WDTF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT5;EA=BIT_TMP;}while(0) 302 | #define set_WIDPD do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT4;EA=BIT_TMP;}while(0) 303 | #define set_WDTRF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT3;EA=BIT_TMP;}while(0) 304 | #define set_WPS2 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT2;EA=BIT_TMP;}while(0) 305 | #define set_WPS1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT1;EA=BIT_TMP;}while(0) 306 | #define set_WPS0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT0;EA=BIT_TMP;}while(0) 307 | #define clr_WDTEN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT7;EA=BIT_TMP;}while(0) 308 | #define clr_WDCLR do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT6;EA=BIT_TMP;}while(0) 309 | #define clr_WDTF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT5;EA=BIT_TMP;}while(0) 310 | #define clr_WDTRF do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT3;EA=BIT_TMP;}while(0) 311 | #define clr_WPS2 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT2;EA=BIT_TMP;}while(0) 312 | #define clr_WPS1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT1;EA=BIT_TMP;}while(0) 313 | #define clr_WPS0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT0;EA=BIT_TMP;}while(0) 314 | 315 | // BODCON1 ABH TA protect register 316 | #define set_LPBOD1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT2 ;EA=BIT_TMP;}while(0) 317 | #define set_LPBOD0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT1 ;EA=BIT_TMP;}while(0) 318 | #define set_BODFLT do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT0 ;EA=BIT_TMP;}while(0) 319 | #define clr_LPBOD1 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT2;EA=BIT_TMP;}while(0) 320 | #define clr_LPBOD0 do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT1;EA=BIT_TMP;}while(0) 321 | #define clr_BODFLT do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT0;EA=BIT_TMP;}while(0) 322 | 323 | // P3M1 ACH PAGE0 324 | #define set_P3M1_0 P3M1|=SET_BIT0 325 | #define clr_P3M1_0 P3M1&=~SET_BIT0 326 | 327 | // P3S ACH PAGE1 SFRS must set as 1 to modify this register 328 | #define set_P3S_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 329 | #define clr_P3S_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 330 | 331 | // P3M2 ADH PAGE0 332 | #define set_P3M2_0 P3M2|=SET_BIT0 333 | #define clr_P3M2_0 P3M2&=~SET_BIT0 334 | 335 | // P3SR ADH PAGE1 SFRS must set as 1 to modify this register 336 | #define set_P3SR_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 337 | #define clr_P3SR_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 338 | 339 | // IAPCN AFH 340 | #define set_FOEN IAPN|=SET_BIT5 341 | #define set_FCEN IAPN|=SET_BIT4 342 | #define set_FCTRL3 IAPN|=SET_BIT3 343 | #define set_FCTRL2 IAPN|=SET_BIT2 344 | #define set_FCTRL1 IAPN|=SET_BIT1 345 | #define set_FCTRL0 IAPN|=SET_BIT0 346 | #define clr_FOEN IAPN&=~SET_BIT5 347 | #define clr_FCEN IAPN&=~SET_BIT4 348 | #define clr_FCTRL3 IAPN&=~SET_BIT3 349 | #define clr_FCTRL2 IAPN&=~SET_BIT2 350 | #define clr_FCTRL1 IAPN&=~SET_BIT1 351 | #define clr_FCTRL0 IAPN&=~SET_BIT0 352 | 353 | // P3 B0H 354 | #define set_P30 P30=1 355 | #define clr_P30 P30=0 356 | 357 | // P0M1 B1H PAGE0 358 | #define set_P0M1_7 P0M1|=SET_BIT7 359 | #define set_P0M1_6 P0M1|=SET_BIT6 360 | #define set_P0M1_5 P0M1|=SET_BIT5 361 | #define set_P0M1_4 P0M1|=SET_BIT4 362 | #define set_P0M1_3 P0M1|=SET_BIT3 363 | #define set_P0M1_2 P0M1|=SET_BIT2 364 | #define set_P0M1_1 P0M1|=SET_BIT1 365 | #define set_P0M1_0 P0M1|=SET_BIT0 366 | #define clr_P0M1_7 P0M1&=~SET_BIT7 367 | #define clr_P0M1_6 P0M1&=~SET_BIT6 368 | #define clr_P0M1_5 P0M1&=~SET_BIT5 369 | #define clr_P0M1_4 P0M1&=~SET_BIT4 370 | #define clr_P0M1_3 P0M1&=~SET_BIT3 371 | #define clr_P0M1_2 P0M1&=~SET_BIT2 372 | #define clr_P0M1_1 P0M1&=~SET_BIT1 373 | #define clr_P0M1_0 P0M1&=~SET_BIT0 374 | 375 | // P0S B2H PAGE1 SFRS must set as 1 to modify this register 376 | #define set_P0S_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 377 | #define set_P0S_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 378 | #define set_P0S_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 379 | #define set_P0S_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 380 | #define set_P0S_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 381 | #define set_P0S_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 382 | #define set_P0S_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 383 | #define set_P0S_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 384 | #define clr_P0S_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 385 | #define clr_P0S_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 386 | #define clr_P0S_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 387 | #define clr_P0S_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 388 | #define clr_P0S_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 389 | #define clr_P0S_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 390 | #define clr_P0S_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 391 | #define clr_P0S_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 392 | 393 | // P0M2 B2H PAGE0 394 | #define set_P0M2_7 P0M2|=SET_BIT7 395 | #define set_P0M2_6 P0M2|=SET_BIT6 396 | #define set_P0M2_5 P0M2|=SET_BIT5 397 | #define set_P0M2_4 P0M2|=SET_BIT4 398 | #define set_P0M2_3 P0M2|=SET_BIT3 399 | #define set_P0M2_2 P0M2|=SET_BIT2 400 | #define set_P0M2_1 P0M2|=SET_BIT1 401 | #define set_P0M2_0 P0M2|=SET_BIT0 402 | #define clr_P0M2_7 P0M2&=~SET_BIT7 403 | #define clr_P0M2_6 P0M2&=~SET_BIT6 404 | #define clr_P0M2_5 P0M2&=~SET_BIT5 405 | #define clr_P0M2_4 P0M2&=~SET_BIT4 406 | #define clr_P0M2_3 P0M2&=~SET_BIT3 407 | #define clr_P0M2_2 P0M2&=~SET_BIT2 408 | #define clr_P0M2_1 P0M2&=~SET_BIT1 409 | #define clr_P0M2_0 P0M2&=~SET_BIT0 410 | 411 | // P0SR B0H PAGE1 SFRS must set as 1 to modify this register 412 | #define set_P0SR_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 413 | #define set_P0SR_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 414 | #define set_P0SR_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 415 | #define set_P0SR_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 416 | #define set_P0SR_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 417 | #define set_P0SR_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 418 | #define set_P0SR_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 419 | #define set_P0SR_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 420 | #define clr_P0SR_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 421 | #define clr_P0SR_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 422 | #define clr_P0SR_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 423 | #define clr_P0SR_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 424 | #define clr_P0SR_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 425 | #define clr_P0SR_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 426 | #define clr_P0SR_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 427 | #define clr_P0SR_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 428 | 429 | // P1M1 B3H PAGE0 430 | #define set_P1M1_7 P1M1|=SET_BIT7 431 | #define set_P1M1_6 P1M1|=SET_BIT6 432 | #define set_P1M1_5 P1M1|=SET_BIT5 433 | #define set_P1M1_4 P1M1|=SET_BIT4 434 | #define set_P1M1_3 P1M1|=SET_BIT3 435 | #define set_P1M1_2 P1M1|=SET_BIT2 436 | #define set_P1M1_1 P1M1|=SET_BIT1 437 | #define set_P1M1_0 P1M1|=SET_BIT0 438 | #define clr_P1M1_7 P1M1&=~SET_BIT7 439 | #define clr_P1M1_6 P1M1&=~SET_BIT6 440 | #define clr_P1M1_5 P1M1&=~SET_BIT5 441 | #define clr_P1M1_4 P1M1&=~SET_BIT4 442 | #define clr_P1M1_3 P1M1&=~SET_BIT3 443 | #define clr_P1M1_2 P1M1&=~SET_BIT2 444 | #define clr_P1M1_1 P1M1&=~SET_BIT1 445 | #define clr_P1M1_0 P1M1&=~SET_BIT0 446 | 447 | // P1S B3H PAGE1 SFRS must set as 1 to modify this register 448 | #define set_P1S_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 449 | #define set_P1S_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 450 | #define set_P1S_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 451 | #define set_P1S_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 452 | #define set_P1S_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 453 | #define set_P1S_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 454 | #define set_P1S_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 455 | #define set_P1S_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 456 | #define clr_P1S_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 457 | #define clr_P1S_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 458 | #define clr_P1S_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 459 | #define clr_P1S_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 460 | #define clr_P1S_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 461 | #define clr_P1S_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 462 | #define clr_P1S_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 463 | #define clr_P1S_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 464 | 465 | // P1M2 B4H PAGE0 466 | #define set_P12UP P1M2|=SET_BIT2 467 | #define set_P1M2_1 P1M2|=SET_BIT1 468 | #define set_P1M2_0 P1M2|=SET_BIT0 469 | #define clr_P12UP P1M2&=~SET_BIT2 470 | #define clr_P1M2_1 P1M2&=~SET_BIT1 471 | #define clr_P1M2_0 P1M2&=~SET_BIT0 472 | 473 | // P1SR B4H PAGE1 SFRS must set as 1 to modify this register 474 | #define set_P1SR_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 475 | #define set_P1SR_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 476 | #define set_P1SR_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 477 | #define set_P1SR_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 478 | #define set_P1SR_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 479 | #define set_P1SR_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 480 | #define set_P1SR_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 481 | #define set_P1SR_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 482 | #define clr_P1SR_7 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 483 | #define clr_P1SR_6 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 484 | #define clr_P1SR_5 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 485 | #define clr_P1SR_4 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 486 | #define clr_P1SR_3 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 487 | #define clr_P1SR_2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 488 | #define clr_P1SR_1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 489 | #define clr_P1SR_0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 490 | 491 | // P2S B5H 492 | #define set_P2S_0 P2S|=SET_BIT0 493 | #define clr_P2S_0 P2S&=~SET_BIT0 494 | 495 | // IPH B7H PAGE0 496 | #define set_PADCH IPH|=SET_BIT6 497 | #define set_PBODH IPH|=SET_BIT5 498 | #define set_PSH IPH|=SET_BIT4 499 | #define set_PT1H IPH|=SET_BIT3 500 | #define set_PX11 IPH|=SET_BIT2 501 | #define set_PT0H IPH|=SET_BIT1 502 | #define set_PX0H IPH|=SET_BIT0 503 | #define clr_PADCH IPH&=~SET_BIT6 504 | #define clr_PBODH IPH&=~SET_BIT5 505 | #define clr_PSH IPH&=~SET_BIT4 506 | #define clr_PT1H IPH&=~SET_BIT3 507 | #define clr_PX11 IPH&=~SET_BIT2 508 | #define clr_PT0H IPH&=~SET_BIT1 509 | #define clr_PX0H IPH&=~SET_BIT0 510 | 511 | // PWMINTC B7H PAGE1 SFRS must set as 1 to modify this register 512 | #define set_INTTYP1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 513 | #define set_INTTYP0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 514 | #define set_INTSEL2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 515 | #define set_INTSEL1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 516 | #define set_INTSEL0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 517 | #define clr_INTTYP1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 518 | #define clr_INTTYP0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 519 | #define clr_INTSEL2 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 520 | #define clr_INTSEL1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 521 | #define clr_INTSEL0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 522 | 523 | // IP B8H 524 | #define set_PADC PADC=1 525 | #define set_PBOD PBOD=1 526 | #define set_PS PS=1 527 | #define set_PT1 PT1=1 528 | #define set_PX1 PX1=1 529 | #define set_PT0 PT0=1 530 | #define set_PX0 PX0=1 531 | #define clr_PADC PADC=0 532 | #define clr_PBOD PBOD=0 533 | #define clr_PS PS=0 534 | #define clr_PT1 PT1=0 535 | #define clr_PX1 PX1=0 536 | #define clr_PT0 PT0=0 537 | #define clr_PX0 PX0=0 538 | 539 | // I2TOC BFH 540 | #define set_I2TOCEN I2TOC|=SET_BIT2 541 | #define set_DIV I2TOC|=SET_BIT1 542 | #define set_I2TOF I2TOC|=SET_BIT0 543 | #define clr_I2TOCEN I2TOC&=~SET_BIT2 544 | #define clr_DIV I2TOC&=~SET_BIT1 545 | #define clr_I2TOF I2TOC&=~SET_BIT0 546 | 547 | // I2CON C0H 548 | #define set_I2CEN I2CEN=1 549 | #define set_STA STA=1 550 | #define set_STO STO=1 551 | #define set_SI SI=1 552 | #define set_AA AA=1 553 | #define set_I2CPX I2CPX=1 554 | #define clr_I2CEN I2CEN=0 555 | #define clr_STA STA=0 556 | #define clr_STO STO=0 557 | #define clr_SI SI=0 558 | #define clr_AA AA=0 559 | #define clr_I2CPX I2CPX=0 560 | 561 | // I2ADDR C1H 562 | #define set_GC I2ADDR|=SET_BIT0 563 | #define clr_GC I2ADDR&=~SET_BIT0 564 | 565 | // T3CON C4H PAGE0 566 | #define set_SMOD_1 T3CON|=SET_BIT7 567 | #define set_SMOD0_1 T3CON|=SET_BIT6 568 | #define set_BRCK T3CON|=SET_BIT5 569 | #define set_TF3 T3CON|=SET_BIT4 570 | #define set_TR3 T3CON|=SET_BIT3 571 | #define set_T3PS2 T3CON|=SET_BIT2 572 | #define set_T3PS1 T3CON|=SET_BIT1 573 | #define set_T3PS0 T3CON|=SET_BIT0 574 | #define clr_SMOD_1 T3CON&=~SET_BIT7 575 | #define clr_SMOD0_1 T3CON&=~SET_BIT6 576 | #define clr_BRCK T3CON&=~SET_BIT5 577 | #define clr_TF3 T3CON&=~SET_BIT4 578 | #define clr_TR3 T3CON&=~SET_BIT3 579 | #define clr_T3PS2 T3CON&=~SET_BIT2 580 | #define clr_T3PS1 T3CON&=~SET_BIT1 581 | #define clr_T3PS0 T3CON&=~SET_BIT0 582 | 583 | // PIOCON1 C6H PAGE1 SFRS must set as 1 to modify this register 584 | #define set_PIO15 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 585 | #define set_PIO13 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 586 | #define set_PIO12 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 587 | #define set_PIO11 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 588 | #define clr_PIO15 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 589 | #define clr_PIO13 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 590 | #define clr_PIO12 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 591 | #define clr_PIO11 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 592 | 593 | // T2CON C8H 594 | #define set_TF2 TF2=1 595 | #define set_TR2 TR2=1 596 | #define set_CMRL2 CMRL2=1 597 | #define clr_TF2 TF2=0 598 | #define clr_TR2 TR2=0 599 | #define clr_CMRL2 CMRL2=0 600 | 601 | // T2MOD C9H 602 | #define set_LDEN T2MOD|=SET_BIT7 603 | #define set_T2DIV2 T2MOD|=SET_BIT6 604 | #define set_T2DIV1 T2MOD|=SET_BIT5 605 | #define set_T2DIV0 T2MOD|=SET_BIT4 606 | #define set_CAPCR T2MOD|=SET_BIT3 607 | #define set_CMPCR T2MOD|=SET_BIT2 608 | #define set_LDTS1 T2MOD|=SET_BIT1 609 | #define set_LDTS0 T2MOD|=SET_BIT0 610 | #define clr_LDEN T2MOD&=~SET_BIT7 611 | #define clr_T2DIV2 T2MOD&=~SET_BIT6 612 | #define clr_T2DIV1 T2MOD&=~SET_BIT5 613 | #define clr_T2DIV0 T2MOD&=~SET_BIT4 614 | #define clr_CAPCR T2MOD&=~SET_BIT3 615 | #define clr_CMPCR T2MOD&=~SET_BIT2 616 | #define clr_LDTS1 T2MOD&=~SET_BIT1 617 | #define clr_LDTS0 T2MOD&=~SET_BIT0 618 | 619 | // PSW D0H 620 | #define set_CY CY=1 621 | #define set_AC AC=1 622 | #define set_F0 F0=1 623 | #define set_RS1 RS1=1 624 | #define set_RS0 RS0=1 625 | #define set_OV OV=1 626 | #define set_P P=1 627 | #define clr_CY CY=0 628 | #define clr_AC AC=0 629 | #define clr_F0 F0=0 630 | #define clr_RS1 RS1=0 631 | #define clr_RS0 RS0=0 632 | #define clr_OV OV=0 633 | #define clr_P P=0 634 | 635 | // PNP D6H 636 | #define set_PNP5 PNP|=SET_BIT5 637 | #define set_PNP4 PNP|=SET_BIT4 638 | #define set_PNP3 PNP|=SET_BIT3 639 | #define set_PNP2 PNP|=SET_BIT2 640 | #define set_PNP1 PNP|=SET_BIT1 641 | #define set_PNP0 PNP|=SET_BIT0 642 | #define clr_PNP5 PNP&=~SET_BIT5 643 | #define clr_PNP4 PNP&=~SET_BIT4 644 | #define clr_PNP3 PNP&=~SET_BIT3 645 | #define clr_PNP2 PNP&=~SET_BIT2 646 | #define clr_PNP1 PNP&=~SET_BIT1 647 | #define clr_PNP0 PNP&=~SET_BIT0 648 | 649 | // FBD D7H 650 | #define set_FBF FBD|=SET_BIT7 651 | #define set_FBINLS FBD|=SET_BIT6 652 | #define set_FBD5 FBD|=SET_BIT5 653 | #define set_FBD4 FBD|=SET_BIT4 654 | #define set_FBD3 FBD|=SET_BIT3 655 | #define set_FBD2 FBD|=SET_BIT2 656 | #define set_FBD1 FBD|=SET_BIT1 657 | #define set_FBD0 FBD|=SET_BIT0 658 | #define clr_FBF FBD&=~SET_BIT7 659 | #define clr_FBINLS FBD&=~SET_BIT6 660 | #define clr_FBD5 FBD&=~SET_BIT5 661 | #define clr_FBD4 FBD&=~SET_BIT4 662 | #define clr_FBD3 FBD&=~SET_BIT3 663 | #define clr_FBD2 FBD&=~SET_BIT2 664 | #define clr_FBD1 FBD&=~SET_BIT1 665 | #define clr_FBD0 FBD&=~SET_BIT0 666 | 667 | // PWMCON0 D8H 668 | #define set_PWMRUN PWMRUN=1 669 | #define set_LOAD LOAD=1 670 | #define set_PWMF PWMF=1 671 | #define set_CLRPWM CLRPWM=1 672 | #define clr_PWMRUN PWMRUN=0 673 | #define clr_LOAD LOAD=0 674 | #define clr_PWMF PWMF=0 675 | #define clr_CLRPWM CLRPWM=0 676 | 677 | // PIOCON0 DEH 678 | #define set_PIO05 PIOCON0|=SET_BIT5 679 | #define set_PIO04 PIOCON0|=SET_BIT4 680 | #define set_PIO03 PIOCON0|=SET_BIT3 681 | #define set_PIO02 PIOCON0|=SET_BIT2 682 | #define set_PIO01 PIOCON0|=SET_BIT1 683 | #define set_PIO00 PIOCON0|=SET_BIT0 684 | #define clr_PIO05 PIOCON0&=~SET_BIT5 685 | #define clr_PIO04 PIOCON0&=~SET_BIT4 686 | #define clr_PIO03 PIOCON0&=~SET_BIT3 687 | #define clr_PIO02 PIOCON0&=~SET_BIT2 688 | #define clr_PIO01 PIOCON0&=~SET_BIT1 689 | #define clr_PIO00 PIOCON0&=~SET_BIT0 690 | 691 | // PWMCON1 DFH 692 | #define set_PWMMOD1 PWMCON1|=SET_BIT7 693 | #define set_PWMMOD0 PWMCON1|=SET_BIT6 694 | #define set_GP PWMCON1|=SET_BIT5 695 | #define set_PWMTYP PWMCON1|=SET_BIT4 696 | #define set_FBINEN PWMCON1|=SET_BIT3 697 | #define set_PWMDIV2 PWMCON1|=SET_BIT2 698 | #define set_PWMDIV1 PWMCON1|=SET_BIT1 699 | #define set_PWMDIV0 PWMCON1|=SET_BIT0 700 | #define clr_PWMMOD1 PWMCON1&=~SET_BIT7 701 | #define clr_PWMMOD0 PWMCON1&=~SET_BIT6 702 | #define clr_GP PWMCON1&=~SET_BIT5 703 | #define clr_PWMTYP PWMCON1&=~SET_BIT4 704 | #define clr_FBINEN PWMCON1&=~SET_BIT3 705 | #define clr_PWMDIV2 PWMCON1&=~SET_BIT2 706 | #define clr_PWMDIV1 PWMCON1&=~SET_BIT1 707 | #define clr_PWMDIV0 PWMCON1&=~SET_BIT0 708 | 709 | // ADCCON1 E1H 710 | #define set_STADCPX ADCCON1|=SET_BIT6 711 | #define set_ETGTYP1 ADCCON1|=SET_BIT3 712 | #define set_ETGTYP0 ADCCON1|=SET_BIT2 713 | #define set_ADCEX ADCCON1|=SET_BIT1 714 | #define set_ADCEN ADCCON1|=SET_BIT0 715 | #define clr_STADCPX ADCCON1&=~SET_BIT6 716 | #define clr_ETGTYP1 ADCCON1&=~SET_BIT3 717 | #define clr_ETGTYP0 ADCCON1&=~SET_BIT2 718 | #define clr_ADCEX ADCCON1&=~SET_BIT1 719 | #define clr_ADCEN ADCCON1&=~SET_BIT0 720 | 721 | // ADCON2 E2H 722 | #define set_ADFBEN ADCCON2|=SET_BIT7 723 | #define set_ADCMPOP ADCCON2|=SET_BIT6 724 | #define set_ADCMPEN ADCCON2|=SET_BIT5 725 | #define set_ADCMPO ADCCON2|=SET_BIT4 726 | #define clr_ADFBEN ADCCON2&=~SET_BIT7 727 | #define clr_ADCMPOP ADCCON2&=~SET_BIT6 728 | #define clr_ADCMPEN ADCCON2&=~SET_BIT5 729 | #define clr_ADCMPO ADCCON2&=~SET_BIT4 730 | 731 | // ADCCON0 EAH 732 | #define set_ADCF ADCF=1 733 | #define set_ADCS ADCS=1 734 | #define set_ETGSEL1 ETGSEL1=1 735 | #define set_ETGSEL0 ETGSEL0=1 736 | #define set_ADCHS3 ADCHS3=1 737 | #define set_ADCHS2 ADCHS2=1 738 | #define set_ADCHS1 ADCHS1=1 739 | #define set_ADCHS0 ADCHS0=1 740 | #define clr_ADCF ADCF=0 741 | #define clr_ADCS ADCS=0 742 | #define clr_ETGSEL1 ETGSEL1=0 743 | #define clr_ETGSEL0 ETGSEL0=0 744 | #define clr_ADCHS3 ADCHS3=0 745 | #define clr_ADCHS2 ADCHS2=0 746 | #define clr_ADCHS1 ADCHS1=0 747 | #define clr_ADCHS0 ADCHS0=0 748 | 749 | // PICON E9H 750 | #define set_PIT67 PICON|=SET_BIT7 751 | #define set_PIT45 PICON|=SET_BIT6 752 | #define set_PIT3 PICON|=SET_BIT5 753 | #define set_PIT2 PICON|=SET_BIT4 754 | #define set_PIT1 PICON|=SET_BIT3 755 | #define set_PIT0 PICON|=SET_BIT2 756 | #define set_PIPS1 PICON|=SET_BIT1 757 | #define set_PIPS0 PICON|=SET_BIT0 758 | #define clr_PIT67 PICON&=~SET_BIT7 759 | #define clr_PIT45 PICON&=~SET_BIT6 760 | #define clr_PIT3 PICON&=~SET_BIT5 761 | #define clr_PIT2 PICON&=~SET_BIT4 762 | #define clr_PIT1 PICON&=~SET_BIT3 763 | #define clr_PIT0 PICON&=~SET_BIT2 764 | #define clr_PIPS1 PICON&=~SET_BIT1 765 | #define clr_PIPS0 PICON&=~SET_BIT0 766 | 767 | // PINEN EAH 768 | #define set_PINEN7 PINEN|=SET_BIT7 769 | #define set_PINEN6 PINEN|=SET_BIT6 770 | #define set_PINEN5 PINEN|=SET_BIT5 771 | #define set_PINEN4 PINEN|=SET_BIT4 772 | #define set_PINEN3 PINEN|=SET_BIT3 773 | #define set_PINEN2 PINEN|=SET_BIT2 774 | #define set_PINEN1 PINEN|=SET_BIT1 775 | #define set_PINEN0 PINEN|=SET_BIT0 776 | #define clr_PINEN7 PINEN&=~SET_BIT7 777 | #define clr_PINEN6 PINEN&=~SET_BIT6 778 | #define clr_PINEN5 PINEN&=~SET_BIT5 779 | #define clr_PINEN4 PINEN&=~SET_BIT4 780 | #define clr_PINEN3 PINEN&=~SET_BIT3 781 | #define clr_PINEN2 PINEN&=~SET_BIT2 782 | #define clr_PINEN1 PINEN&=~SET_BIT1 783 | #define clr_PINEN0 PINEN&=~SET_BIT0 784 | 785 | // PIPEN EBH 786 | #define set_PIPEN7 PIPEN|=SET_BIT7 787 | #define set_PIPEN6 PIPEN|=SET_BIT6 788 | #define set_PIPEN5 PIPEN|=SET_BIT5 789 | #define set_PIPEN4 PIPEN|=SET_BIT4 790 | #define set_PIPEN3 PIPEN|=SET_BIT3 791 | #define set_PIPEN2 PIPEN|=SET_BIT2 792 | #define set_PIPEN1 PIPEN|=SET_BIT1 793 | #define set_PIPEN0 PIPEN|=SET_BIT0 794 | #define clr_PIPEN7 PIPEN&=~SET_BIT7 795 | #define clr_PIPEN6 PIPEN&=~SET_BIT6 796 | #define clr_PIPEN5 PIPEN&=~SET_BIT5 797 | #define clr_PIPEN4 PIPEN&=~SET_BIT4 798 | #define clr_PIPEN3 PIPEN&=~SET_BIT3 799 | #define clr_PIPEN2 PIPEN&=~SET_BIT2 800 | #define clr_PIPEN1 PIPEN&=~SET_BIT1 801 | #define clr_PIPEN0 PIPEN&=~SET_BIT0 802 | 803 | // PIF ECH 804 | #define set_PIF7 PIF|=SET_BIT7 805 | #define set_PIF6 PIF|=SET_BIT6 806 | #define set_PIF5 PIF|=SET_BIT5 807 | #define set_PIF4 PIF|=SET_BIT4 808 | #define set_PIF3 PIF|=SET_BIT3 809 | #define set_PIF2 PIF|=SET_BIT2 810 | #define set_PIF1 PIF|=SET_BIT1 811 | #define set_PIF0 PIF|=SET_BIT0 812 | #define clr_PIF7 PIF&=~SET_BIT7 813 | #define clr_PIF6 PIF&=~SET_BIT6 814 | #define clr_PIF5 PIF&=~SET_BIT5 815 | #define clr_PIF4 PIF&=~SET_BIT4 816 | #define clr_PIF3 PIF&=~SET_BIT3 817 | #define clr_PIF2 PIF&=~SET_BIT2 818 | #define clr_PIF1 PIF&=~SET_BIT1 819 | #define clr_PIF0 PIF&=~SET_BIT0 820 | 821 | // EIP EFH 822 | #define set_PT2 EIP|=SET_BIT7 823 | #define set_PSPI EIP|=SET_BIT6 824 | #define set_PFB EIP|=SET_BIT5 825 | #define set_PWDT EIP|=SET_BIT4 826 | #define set_PPWM EIP|=SET_BIT3 827 | #define set_PCAP EIP|=SET_BIT2 828 | #define set_PPI EIP|=SET_BIT1 829 | #define set_PI2C EIP|=SET_BIT0 830 | #define clr_PT2 EIP&=~SET_BIT7 831 | #define clr_PSPI EIP&=~SET_BIT6 832 | #define clr_PFB EIP&=~SET_BIT5 833 | #define clr_PWDT EIP&=~SET_BIT4 834 | #define clr_PPWM EIP&=~SET_BIT3 835 | #define clr_PCAP EIP&=~SET_BIT2 836 | #define clr_PPI EIP&=~SET_BIT1 837 | #define clr_PI2C EIP&=~SET_BIT0 838 | 839 | // CAPCON3 F1H 840 | #define set_CAP13 CAPCON3|=SET_BIT7 841 | #define set_CAP12 CAPCON3|=SET_BIT6 842 | #define set_CAP11 CAPCON3|=SET_BIT5 843 | #define set_CAP10 CAPCON3|=SET_BIT4 844 | #define set_CAP03 CAPCON3|=SET_BIT3 845 | #define set_CAP02 CAPCON3|=SET_BIT2 846 | #define set_CAP01 CAPCON3|=SET_BIT1 847 | #define set_CAP00 CAPCON3|=SET_BIT0 848 | #define clr_CAP13 CAPCON3&=~SET_BIT7 849 | #define clr_CAP12 CAPCON3&=~SET_BIT6 850 | #define clr_CAP11 CAPCON3&=~SET_BIT5 851 | #define clr_CAP10 CAPCON3&=~SET_BIT4 852 | #define clr_CAP03 CAPCON3&=~SET_BIT3 853 | #define clr_CAP02 CAPCON3&=~SET_BIT2 854 | #define clr_CAP01 CAPCON3&=~SET_BIT1 855 | #define clr_CAP00 CAPCON3&=~SET_BIT0 856 | 857 | // CAPCON4 F2H 858 | #define set_CAP23 CAPCON4|=SET_BIT3 859 | #define set_CAP22 CAPCON4|=SET_BIT2 860 | #define set_CAP21 CAPCON4|=SET_BIT1 861 | #define set_CAP20 CAPCON4|=SET_BIT0 862 | #define clr_CAP23 CAPCON4&=~SET_BIT3 863 | #define clr_CAP22 CAPCON4&=~SET_BIT2 864 | #define clr_CAP21 CAPCON4&=~SET_BIT1 865 | #define clr_CAP20 CAPCON4&=~SET_BIT0 866 | 867 | // SPCR F3H PAGE0 868 | #define set_SSOE SPCR|=SET_BIT7 869 | #define set_SPIEN SPCR|=SET_BIT6 870 | #define set_LSBFE SPCR|=SET_BIT5 871 | #define set_MSTR SPCR|=SET_BIT4 872 | #define set_CPOL SPCR|=SET_BIT3 873 | #define set_CPHA SPCR|=SET_BIT2 874 | #define set_SPR1 SPCR|=SET_BIT1 875 | #define set_SPR0 SPCR|=SET_BIT0 876 | #define clr_SSOE SPCR&=~SET_BIT7 877 | #define clr_SPIEN SPCR&=~SET_BIT6 878 | #define clr_LSBFE SPCR&=~SET_BIT5 879 | #define clr_MSTR SPCR&=~SET_BIT4 880 | #define clr_CPOL SPCR&=~SET_BIT3 881 | #define clr_CPHA SPCR&=~SET_BIT2 882 | #define clr_SPR1 SPCR&=~SET_BIT1 883 | #define clr_SPR0 SPCR&=~SET_BIT0 884 | 885 | // SPCR2 F3H PAGE1 SFRS must set as 1 to modify this register 886 | #define set_SPIS1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 887 | #define set_SPIS0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 888 | #define clr_SPIS1 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 889 | #define clr_SPIS0 do{BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP;}while(0) 890 | 891 | // SPSR F4H 892 | #define set_SPIF SPSR|=SET_BIT7 893 | #define set_WCOL SPSR|=SET_BIT6 894 | #define set_SPIOVF SPSR|=SET_BIT5 895 | #define set_MODF SPSR|=SET_BIT4 896 | #define set_DISMODF SPSR|=SET_BIT3 897 | #define clr_SPIF SPSR&=~SET_BIT7 898 | #define clr_WCOL SPSR&=~SET_BIT6 899 | #define clr_SPIOVF SPSR&=~SET_BIT5 900 | #define clr_MODF SPSR&=~SET_BIT4 901 | #define clr_DISMODF SPSR&=~SET_BIT3 902 | 903 | // AINDIDS F6H 904 | #define set_P11DIDS AINDIDS|=SET_BIT7 905 | #define set_P03DIDS AINDIDS|=SET_BIT6 906 | #define set_P04DIDS AINDIDS|=SET_BIT5 907 | #define set_P05DIDS AINDIDS|=SET_BIT4 908 | #define set_P06DIDS AINDIDS|=SET_BIT3 909 | #define set_P07DIDS AINDIDS|=SET_BIT2 910 | #define set_P30DIDS AINDIDS|=SET_BIT1 911 | #define set_P17DIDS AINDIDS|=SET_BIT0 912 | #define clr_P11DIDS AINDIDS&=~SET_BIT7 913 | #define clr_P03DIDS AINDIDS&=~SET_BIT6 914 | #define clr_P04DIDS AINDIDS&=~SET_BIT5 915 | #define clr_P05DIDS AINDIDS&=~SET_BIT4 916 | #define clr_P06DIDS AINDIDS&=~SET_BIT3 917 | #define clr_P07DIDS AINDIDS&=~SET_BIT2 918 | #define clr_P30DIDS AINDIDS&=~SET_BIT1 919 | #define clr_P17DIDS AINDIDS&=~SET_BIT0 920 | 921 | // EIPH F7H 922 | #define set_PT2H EIPH|=SET_BIT7 923 | #define set_PSPIH EIPH|=SET_BIT6 924 | #define set_PFBH EIPH|=SET_BIT5 925 | #define set_PWDTH EIPH|=SET_BIT4 926 | #define set_PPWMH EIPH|=SET_BIT3 927 | #define set_PCAPH EIPH|=SET_BIT2 928 | #define set_PPIH EIPH|=SET_BIT1 929 | #define set_PI2CH EIPH|=SET_BIT0 930 | #define clr_PT2H EIPH&=~SET_BIT7 931 | #define clr_PSPIH EIPH&=~SET_BIT6 932 | #define clr_PFBH EIPH&=~SET_BIT5 933 | #define clr_PWDTH EIPH&=~SET_BIT4 934 | #define clr_PPWMH EIPH&=~SET_BIT3 935 | #define clr_PCAPH EIPH&=~SET_BIT2 936 | #define clr_PPIH EIPH&=~SET_BIT1 937 | #define clr_PI2CH EIPH&=~SET_BIT0 938 | 939 | // SCON_1 F8H 940 | #define set_FE_1 FE_1=1 941 | #define set_SM1_1 SM1_1=1 942 | #define set_SM2_1 SM2_1=1 943 | #define set_REN_1 REN_1=1 944 | #define set_TB8_1 TB8_1=1 945 | #define set_RB8_1 RB8_1=1 946 | #define set_TI_1 TI_1=1 947 | #define set_RI_1 RI_1=1 948 | #define clr_FE_1 FE_1=0 949 | #define clr_SM1_1 SM1_1=0 950 | #define clr_SM2_1 SM2_1=0 951 | #define clr_REN_1 REN_1=0 952 | #define clr_TB8_1 TB8_1=0 953 | #define clr_RB8_1 RB8_1=0 954 | #define clr_TI_1 TI_1=0 955 | #define clr_RI_1 RI_1=0 956 | 957 | // PDTEN F9H 958 | #define set_PDT45EN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=SET_BIT2;EA=BIT_TMP;}while(0) 959 | #define set_PDT23EN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=SET_BIT1;EA=BIT_TMP;}while(0) 960 | #define set_PDT01EN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=SET_BIT0;EA=BIT_TMP;}while(0) 961 | #define clr_PDT45EN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN&=~SET_BIT2;EA=BIT_TMP;}while(0) 962 | #define clr_PDT23EN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN&=~SET_BIT1;EA=BIT_TMP;}while(0) 963 | #define clr_PDT01EN do{BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN&=~SET_BIT0;EA=BIT_TMP;}while(0) 964 | 965 | // PMEN FBH 966 | #define set_PMEN5 PMEN|=SET_BIT5 967 | #define set_PMEN4 PMEN|=SET_BIT4 968 | #define set_PMEN3 PMEN|=SET_BIT3 969 | #define set_PMEN2 PMEN|=SET_BIT2 970 | #define set_PMEN1 PMEN|=SET_BIT1 971 | #define set_PMEN0 PMEN|=SET_BIT0 972 | #define clr_PMEN5 PMEN&=~SET_BIT5 973 | #define clr_PMEN4 PMEN&=~SET_BIT4 974 | #define clr_PMEN3 PMEN&=~SET_BIT3 975 | #define clr_PMEN2 PMEN&=~SET_BIT2 976 | #define clr_PMEN1 PMEN&=~SET_BIT1 977 | #define clr_PMEN0 PMEN&=~SET_BIT0 978 | 979 | // PMD FCH 980 | #define set_PMD7 PMD|=SET_BIT7 981 | #define set_PMD6 PMD|=SET_BIT6 982 | #define set_PMD5 PMD|=SET_BIT5 983 | #define set_PMD4 PMD|=SET_BIT4 984 | #define set_PMD3 PMD|=SET_BIT3 985 | #define set_PMD2 PMD|=SET_BIT2 986 | #define set_PMD1 PMD|=SET_BIT1 987 | #define set_PMD0 PMD|=SET_BIT0 988 | #define clr_PMD7 PMD&=~SET_BIT7 989 | #define clr_PMD6 PMD&=~SET_BIT6 990 | #define clr_PMD5 PMD&=~SET_BIT5 991 | #define clr_PMD4 PMD&=~SET_BIT4 992 | #define clr_PMD3 PMD&=~SET_BIT3 993 | #define clr_PMD2 PMD&=~SET_BIT2 994 | #define clr_PMD1 PMD&=~SET_BIT1 995 | #define clr_PMD0 PMD&=~SET_BIT0 996 | 997 | // EIP1 FEH 998 | #define set_PWKT EIP1|=SET_BIT2 999 | #define set_PT3 EIP1|=SET_BIT1 1000 | #define set_PS_1 EIP1|=SET_BIT0 1001 | #define clr_PWKT EIP1&=~SET_BIT2 1002 | #define clr_PT3 EIP1&=~SET_BIT1 1003 | #define clr_PS_1 EIP1&=~SET_BIT0 1004 | 1005 | // EIPH1 FFH 1006 | #define set_PWKTH EIPH1|=SET_BIT2 1007 | #define set_PT3H EIPH1|=SET_BIT1 1008 | #define set_PSH_1 EIPH1|=SET_BIT0 1009 | #define clr_PWKTH EIPH1&=~SET_BIT2 1010 | #define clr_PT3H EIPH1&=~SET_BIT1 1011 | #define clr_PSH_1 EIPH1&=~SET_BIT0 1012 | 1013 | #endif 1014 | --------------------------------------------------------------------------------