├── 2023 ├── README.md ├── T3_floataddRISCV.md ├── assemblyriscV.md ├── code_riscv.md ├── exemploASM.md ├── exemplos_fsm.md ├── exemplos_riscv.md ├── figuras │ ├── README.md │ ├── alu_datapath.png │ ├── beq_example.excalidraw │ ├── beq_example.png │ ├── fetch_decodeDatapath1.png │ ├── fsmryr.png │ ├── green.png │ ├── patterson.jpg │ ├── qr_code_forward.png │ ├── qr_sinal.png │ ├── qra2h.png │ ├── qrh2a.png │ ├── red.png │ ├── ris_type-riscv.excalidraw │ ├── ris_type-riscv.png │ ├── riscv_instructioncode.png │ ├── riscv_singledatapath1.png │ ├── wr_.png │ ├── wr_d.png │ ├── wr_f.png │ ├── wr_fd.png │ └── yellow.png ├── float.md ├── fsm.md ├── kmeans.md ├── monociclo.md ├── morepipeline.md ├── pipeline.md ├── riscv_desvios.md ├── riscv_vetores.md └── verilog_pipeline.md ├── 2024 ├── README.md ├── assembly.md ├── codificacao.md ├── float24.md ├── fsm.md ├── gerador_add_mult_float7.png ├── inf250_2024_aula_1_Float-1.pdf ├── merged (11).pdf ├── monociclo.md ├── pipe_branch_2st_forward.svg ├── pipe_para_completar_branch_2st_forward.svg ├── pipe_para_completar_forward_hazard.svg ├── prova2.md ├── qrRiscVALU_generator.png └── qrfloat7conversor.png ├── 2025 └── README.md ├── Assembler_Risc_V ├── README.md ├── download │ ├── README.md │ ├── desvio_beq.excalidraw │ ├── desvio_com_beq.svg │ ├── exemplo_add_lw_addi.excalidraw │ ├── exemplo_add_lw_addi.svg │ ├── formato │ │ ├── README.md │ │ ├── beq_16.excalidraw │ │ ├── beq_16.png │ │ ├── beq_menos12.excalidraw │ │ ├── beq_menos12.png │ │ ├── decode1.png │ │ ├── exemplo_addI.excalidraw │ │ ├── exemplo_add_t0_t1_t2.excalidraw │ │ ├── exemplo_add_t0_t1_t2.svg │ │ ├── exemplo_addi.svg │ │ ├── exemplo_lw.excalidraw │ │ ├── exemplo_lw.svg │ │ ├── exemplo_sw.excalidraw │ │ ├── exemplo_sw.svg │ │ ├── fetch_example.png │ │ └── riscv_5instructionBinaryCodeExample.png │ ├── introducao_aos_processadores.svg │ ├── introducao_processadores.excalidraw │ ├── soma_float.excalidraw │ ├── soma_float.svg │ ├── somatorio_vetor.excalidraw │ └── somatorio_vetor.svg └── prova2_2022 │ ├── README.md │ ├── p19.pdf │ └── prova3_2015.pdf ├── Float ├── README.md └── download │ ├── README.md │ ├── apresentacao_inf250_2021_2.excalidraw │ ├── avaliacao_e_livros_Inf250.excalidraw │ ├── binario_para_float_numero_3.excalidraw │ ├── explicacao_waveform.svg │ └── soma_multiplicacao │ ├── 1_5_mais_1_1_18.excalidraw │ ├── 1_mais_1.excalidraw │ ├── README.md │ ├── expoente_diferente_3_mais_1_e_meio.excalidraw │ ├── multiplicacao_codigo_verilog.excalidraw │ ├── multiplicacao_ponto_flutuante_3_vezes_3.excalidraw │ ├── outros_exemplos_expoentes_diferentes.excalidraw │ ├── verilog_expoente_a_maior_que_b.excalidraw │ └── verilog_expoentes_iguais.excalidraw ├── Maquina de Estados Finitos ├── README.md ├── download │ ├── Captura de tela de 2022-09-20 05-42-12.png │ ├── MAQCOMPRAVENDA.png │ ├── MAQCOMPRAVENDA.svg │ ├── README.md │ ├── Sem título-2022-09-19-1910.svg │ ├── Semaforo │ │ ├── README.md │ │ ├── Solucao_com_memoria.png │ │ ├── Solucao_simbolica.excalidraw │ │ ├── Varias_cores_Solucao_simbolica_em_verilog.excalidraw │ │ ├── Varias_cores_Solucao_simbolica_em_verilog.svg │ │ ├── calculo_p1_sinal_simples.excalidraw │ │ ├── calculo_p1_sinal_simples.svg │ │ ├── dicas_para_exercicio_2.excalidraw │ │ ├── dicas_para_exercicio_2.svg │ │ ├── exerc2_3_com_porta_logica.excalidraw │ │ ├── exerc2_3_com_porta_logica.svg │ │ ├── memoria_semaforo_verilog.svg │ │ ├── pisca_tres_memoria.excalidraw │ │ ├── pisca_tres_memoria.svg │ │ ├── porta_logica_semaforo.svg │ │ ├── porta_logica_semaforo_verilog.svg │ │ ├── portalogica_semaforo.png │ │ ├── portalogica_semaforo_verilog.png │ │ ├── semaforo_memoria.excalidraw │ │ ├── semaforo_porta_logica.excalidraw │ │ ├── semaforo_porta_logica_verilog.excalidraw │ │ ├── simbolica_semaforo_verilo.svg │ │ ├── simbolica_semaforo_verilog.png │ │ ├── tabela2_2.excalidraw │ │ └── tabela2_2.svg │ ├── Sequencias │ │ ├── README.md │ │ ├── dicas_iniciais_trabalho_3.excalidraw │ │ ├── dicas_iniciais_trabalho_3.svg │ │ ├── montando_tabela_contador_de_sequencia.excalidraw │ │ ├── montando_tabela_contador_de_sequencia.svg │ │ ├── trab3_implementacao_memoria.excalidraw │ │ ├── trab3_implementacao_memoria.svg │ │ ├── trab3_implementacao_porta.excalidraw │ │ ├── trab3_implementacao_porta.svg │ │ ├── trab3_maquina_estados_diagrama.excalidraw │ │ └── trab3_maquina_estados_diagrama.svg │ ├── Tripla │ │ ├── Exercicio_2_com_codigos_diferentes_tripla.excalidraw │ │ ├── Exercicio_2_com_codigos_diferentes_tripla.svg │ │ ├── README.md │ │ ├── outras_dicas_trabalho2_triplas.excalidraw │ │ ├── outras_dicas_trabalho2_triplas.svg │ │ ├── paridade.excalidraw │ │ ├── paridade.svg │ │ ├── triplas.excalidraw │ │ └── triplas.svg │ ├── fsm.pdf │ ├── introducao.odp │ ├── introducao.pdf │ ├── paridade_implementacao_memoria.png │ ├── provas17_19_FSM.zip │ ├── testefsm_sol.odp │ ├── testefsm_sol.pdf │ ├── vendas_diagrama_gate_vhdl.odp │ └── vendas_diagrama_gate_vhdl.pdf ├── fundamentals.png ├── fundamentals_slides.pdf ├── introductionToVerilog.png └── verilog.pdf ├── Processador_single_RISCV ├── Desvio_Incondicional │ ├── README.md │ ├── Screenshot from 2022-02-08 15-18-05.png │ └── jalx0.png ├── README.md ├── animacao_execucao.md └── download │ ├── README.md │ ├── datapath_add.png │ ├── datapath_beq.png │ ├── ezgif.com-gif-maker (1).gif │ └── phpYI6eip.png ├── README.md ├── Verilog_e_FPGA ├── 3folhas.png ├── 65_slides.png ├── README.md ├── SystemVerilogCheatSheet.pdf ├── Verilog tutorial_65slides.pdf ├── Verilog_cheat.pdf ├── codesamples(1).pdf ├── onechaet.png ├── verilog_examples14pages.pdf ├── verilog_x1ch.pdf └── verilogexamples14pages.png ├── calculo_p1_sinal_simples.excalidraw ├── calculo_p1_sinal_simples.svg ├── dicas_para_exercicio_2.excalidraw ├── dicas_para_exercicio_2.svg ├── download ├── 618px-IEEE_754_Single_Floating_Point_Format.svg.png ├── Exercicio_float_cod_soma_mul.odt ├── Exercicio_float_cod_soma_mul.pdf ├── README.md ├── apostila_float.pdf ├── apresentacao_inf250_2021_2.excalidraw ├── codificacao_1.odp ├── codificacao_1.pdf ├── codigos │ └── Float │ │ ├── README.md │ │ ├── add_exp_eaGTeb.v │ │ ├── add_exp_eaGTeb_1.v │ │ ├── add_exp_equal.v │ │ ├── add_exp_equal1.v │ │ ├── add_exp_equal_FOR.v │ │ ├── add_exp_over.v │ │ ├── add_exp_round.v │ │ └── mult.v ├── exerc_float_verilog.odt ├── exerc_float_verilog.pdf ├── float.odp ├── float.pdf ├── float754.jpeg ├── floatMultiplicacao.odt ├── floatMultiplicacao.pdf └── iee754.png ├── float.pdf ├── microprogramação └── README.md └── pipeline ├── README.md ├── animacao_execucao.md └── figuras ├── 5stage_wo_fwd_haz_brch_4th.png ├── README.md ├── Untitled-2023-01-10-1028.png ├── Untitled-2023-01-10-1029.png ├── Untitled-2023-01-10-1030.png ├── Untitled-2023-01-10-1031.png ├── Untitled-2023-01-10-1032.png ├── datapath_haz_forward_branch2_5stage_instrucoes.png ├── exemplo_datapath_5instrucoes_cor.png ├── ezgif.com-gif-maker.gif ├── flush.png ├── forward_in_5stage.png ├── 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