├── .gitignore ├── README.md ├── caches ├── DCache.v ├── ICache.v ├── IPrefetcher.v ├── hellacache.v ├── hellacache_modelsim.v └── sram.v ├── csrc ├── common.h ├── dc_bc_main.cc ├── dc_bc_model.cc ├── dc_bc_model.h ├── dc_bc_param.h ├── dc_bc_types.h ├── dc_hc_main.cc ├── dc_hc_model.cc ├── dc_hc_model.h ├── dc_hc_param.h ├── dc_hc_types.h ├── disasm-modelsim.cc ├── disasm-modelsim.h ├── disasm-vcs.cc ├── disasm.cc ├── disasm.h ├── htif-modelsim.cc ├── htif-modelsim.h ├── htif_main.cc ├── htif_model.cc ├── htif_model.h ├── ic_main.cc ├── ic_model.cc ├── ic_model.h ├── ic_param.h ├── ic_types.h ├── mac_fedriver.c ├── mac_fedriver.h ├── mm_main.cc ├── mm_model.cc ├── mm_model.h ├── mm_param.h └── mm_types.h ├── fpgasrc ├── EthernetDDRAdapter.sv ├── HTIFChipAdapater.v ├── HTIFEthernetAdapter.v ├── blink.v ├── fpga_clocking.v ├── fpga_top.sv ├── mac_gmii.v ├── offchip_phy.v ├── resiliency_fpga.v ├── riscvCoreDRAMAdapter.sv ├── riscvFPGA.v ├── riscvFPGATestHarness.v ├── riscvFPGATestHarness_no_htif.v ├── riscvHTIF.sv ├── rs232_tx.v └── serdes.v ├── hardfloat ├── ALT-normalize128.v ├── ALT-normalize256.v ├── ALT-normalize32.v ├── ALT-normalize64.v ├── README.txt ├── addSubRecodedFloat32_1.v ├── addSubRecodedFloat64_1.v ├── addSubRecodedFloatN_1.v ├── anyToFloat32.v ├── anyToRecodedFloat32.v ├── anyToRecodedFloat64.v ├── compareRecodedFloatN.v ├── estNormDistP24NegSum50.v ├── estNormDistP24PosSum50.v ├── estNormDistP53NegSum108.v ├── estNormDistP53PosSum108.v ├── estNormDistPNNegSumN.v ├── estNormDistPNPosSumN.v ├── float32ToAny.v ├── float32ToRecodedFloat32.v ├── float64ToRecodedFloat64.v ├── floatNToRecodedFloatN.v ├── fpu_recoded.vh ├── mulAddSubRecodedFloat32_1.v ├── mulAddSubRecodedFloat64_1.v ├── mulAddSubRecodedFloatN_1.v ├── mulRecodedFloat32_1.v ├── mulRecodedFloat64_1.v ├── mulRecodedFloatN_1.v ├── normalize32.v ├── normalize64.v ├── normalizeN.v ├── recodedFloat32Compare.v ├── recodedFloat32ToAny.v ├── recodedFloat32ToFloat32.v ├── recodedFloat32ToRecodedFloat64.v ├── recodedFloat64ToAny.v ├── recodedFloat64ToFloat64.v ├── recodedFloat64ToRecodedFloat32.v ├── recodedFloatNToFloatN.v ├── recodedFloatNToIntM.v ├── shift_right_track_lsbs.v └── shift_round_position.v ├── include ├── ansidecl.h ├── bfd.h ├── bfdlink.h ├── dis-asm.h └── symcat.h ├── lib ├── Makefile └── scripts │ ├── config.guess │ └── config.sub ├── rampgold ├── cpu │ ├── clkrst_gen.sv │ ├── libcache.sv │ ├── libdebug.sv │ ├── libfp.sv │ ├── libiu.sv │ ├── libmmu.sv │ ├── libucode.sv │ ├── libxalu.sv │ └── opcodes.sv ├── eth │ ├── dma_control.sv │ ├── eth_cpu_control.sv │ ├── eth_dma_controller.sv │ ├── eth_dma_master.sv │ ├── eth_mac_ram.sv │ ├── eth_rx.sv │ ├── eth_tm_control.sv │ ├── eth_tx.sv │ ├── gmii_if.v │ ├── libeth.sv │ ├── readme.txt │ ├── rx_block.sv │ ├── tx_block.sv │ ├── v5_emac_v1_5.v │ └── v5_emac_v1_5_block.v ├── io │ └── libio.sv ├── lcd │ ├── lcd.sv │ ├── liblcd.sv │ ├── rs232_rx.sv │ └── rs232_tx.sv ├── libconf.sv ├── mem │ ├── ddr2memctrl.sv │ ├── ddr2memctrl_fast.sv │ ├── dramctrl_network.sv │ ├── dramif.sv │ ├── libmemif.sv │ └── memif.sv ├── sim │ ├── ddr2 │ │ ├── 1Gb │ │ │ ├── ddr2.v │ │ │ ├── ddr2_mcp.v │ │ │ ├── ddr2_module.v │ │ │ ├── ddr2_parameters.vh │ │ │ ├── mt16htf25664hy.sv │ │ │ ├── mt36htf51272pz.sv │ │ │ ├── readme.txt │ │ │ ├── subtest.vh │ │ │ ├── tb.do │ │ │ └── tb.v │ │ └── 512Mb │ │ │ ├── ddr2.v │ │ │ ├── ddr2_mcp.v │ │ │ ├── ddr2_module.v │ │ │ ├── ddr2_parameters.vh │ │ │ ├── mt4htf3264hy.sv │ │ │ ├── readme.txt │ │ │ ├── subtest.vh │ │ │ ├── tb.do │ │ │ └── tb.v │ ├── disasm │ │ ├── Makefile │ │ ├── disasm.c │ │ ├── disasm.h │ │ ├── disasm.so │ │ └── disasm.sv │ ├── dumpreg │ │ ├── Makefile │ │ ├── dumpreg.c │ │ ├── dumpreg.h │ │ └── dumpreg.sv │ ├── mac_fedriver │ │ ├── Makefile │ │ ├── mac_fedriver.c │ │ ├── mac_fedriver.h │ │ ├── mac_fedriver.o │ │ ├── mac_fedriver.so │ │ ├── mac_fedriver.sv │ │ ├── socket.c │ │ ├── socket.h │ │ └── socket.o │ └── memctrl │ │ └── sim_memctrl.sv ├── sim_top.sv ├── stdlib │ ├── bram_blocks.sv │ ├── libstd.sv │ └── sync_lutram_fifo.sv ├── tech │ ├── libtech.sv │ ├── techmap.sv │ └── xilinx │ │ ├── tech_xilinx.sv │ │ └── virtex5 │ │ ├── aludiv.sv │ │ ├── alulogic.sv │ │ ├── alumul.sv │ │ ├── bee3rdimm │ │ ├── AF.v │ │ ├── RB.v │ │ ├── TC5.v │ │ ├── Tester.v │ │ ├── WB.v │ │ ├── camx.v │ │ ├── ddrBank.v │ │ ├── ddrController.v │ │ ├── ddrTop.v │ │ ├── ddrTopDPITest.v │ │ ├── dpbram.v │ │ ├── dpram.v │ │ ├── dq_iob.v │ │ ├── dqs_iob.v │ │ ├── im_mem.v │ │ ├── mem │ │ │ ├── im.bmm │ │ │ ├── rfa.bmm │ │ │ ├── rfb.bmm │ │ │ ├── tc5mem │ │ │ └── testTC5.txt │ │ ├── rfa_mem.v │ │ ├── rfb_mem.v │ │ └── rs232rcv.v │ │ ├── bee3sodimm │ │ ├── AF.v │ │ ├── RB.v │ │ ├── TC5.v │ │ ├── Tester.v │ │ ├── WB.v │ │ ├── camx.v │ │ ├── ddrBank.v │ │ ├── ddrController.v │ │ ├── ddrTop.v │ │ ├── ddrTopDPITest.v │ │ ├── dpbram.sv │ │ ├── dpbram.v │ │ ├── dpram.v │ │ ├── dq_iob.v │ │ ├── dqs_iob.v │ │ ├── im_mem.v │ │ ├── mem │ │ │ ├── im.bmm │ │ │ ├── mem0.mem │ │ │ ├── mem0.mem.rank0 │ │ │ ├── mem1.mem │ │ │ ├── mem1.mem.rank0 │ │ │ ├── rfa.bmm │ │ │ ├── rfb.bmm │ │ │ ├── tc5mem │ │ │ └── testTC5.txt │ │ ├── rfa_mem.v │ │ ├── rfb_mem.v │ │ └── rs232rcv.v │ │ ├── bram_memory_128.sv │ │ ├── bram_rom_32.sv │ │ ├── clkgen.sv │ │ ├── dcacheram.sv │ │ ├── demo_bram_128.sv │ │ ├── diab │ │ ├── atm │ │ │ ├── atm_l1_ram.sv │ │ │ └── link_ram.sv │ │ └── packet │ │ │ ├── fifo_blocks.sv │ │ │ └── voq_hc_buf.sv │ │ ├── dmabuf.sv │ │ ├── dram_clkgen.sv │ │ ├── dramctrl_bee3.sv │ │ ├── dramctrl_mig.sv │ │ ├── dtlbram.sv │ │ ├── fpregfile.sv │ │ ├── icacheram.sv │ │ ├── itlbram.sv │ │ ├── mac_gmii.sv │ │ ├── mig_23 │ │ ├── ddr2_chipscope.v │ │ ├── ddr2_ctrl.v │ │ ├── ddr2_idelay_ctrl.v │ │ ├── ddr2_infrastructure.v │ │ ├── ddr2_mem_if_top.v │ │ ├── ddr2_phy_calib.v │ │ ├── ddr2_phy_ctl_io.v │ │ ├── ddr2_phy_dm_iob.v │ │ ├── ddr2_phy_dq_iob.v │ │ ├── ddr2_phy_dqs_iob.v │ │ ├── ddr2_phy_init.v │ │ ├── ddr2_phy_io.v │ │ ├── ddr2_phy_top.v │ │ ├── ddr2_phy_write.v │ │ ├── ddr2_sdram.v │ │ ├── ddr2_top.v │ │ ├── ddr2_usr_addr_fifo.v │ │ ├── ddr2_usr_rd.v │ │ ├── ddr2_usr_top.v │ │ └── ddr2_usr_wr.v │ │ ├── regfile.sv │ │ └── simdma_rom.sv └── tm │ └── libtm.sv ├── riscv-bmarks ├── Makefile ├── console │ ├── bmark.mk │ └── console_main.c ├── median │ ├── bmark.mk │ ├── dataset1.h │ ├── median.c │ ├── median.h │ ├── median_gendata.pl │ └── median_main.c ├── multiply │ ├── bmark.mk │ ├── dataset1.h │ ├── multiply.c │ ├── multiply.h │ ├── multiply_gendata.pl │ └── multiply_main.c ├── qsort │ ├── bmark.mk │ ├── dataset1.h │ ├── qsort_gendata.pl │ └── qsort_main.c ├── readme.txt ├── stuff │ ├── Makefile │ ├── crt.S │ ├── crt.o │ └── test.ld ├── towers │ ├── bmark.mk │ └── towers_main.c └── vvadd │ ├── bmark.mk │ ├── dataset1-large.h │ ├── dataset1.h │ ├── vvadd_gendata.pl │ └── vvadd_main.c ├── riscv-tests ├── .gitignore ├── Makefile ├── riscv_add.S ├── riscv_addi.S ├── riscv_addiw.S ├── riscv_addw.S ├── riscv_amoadd_d.S ├── riscv_amoadd_w.S ├── riscv_amoand_d.S ├── riscv_amoand_w.S ├── riscv_amomax_d.S ├── riscv_amomax_w.S ├── riscv_amomaxu_d.S ├── riscv_amomaxu_w.S ├── riscv_amomin_d.S ├── riscv_amomin_w.S ├── riscv_amominu_d.S ├── riscv_amominu_w.S ├── riscv_amoor_d.S ├── riscv_amoor_w.S ├── riscv_amoswap_d.S ├── riscv_amoswap_w.S ├── riscv_and.S ├── riscv_andi.S ├── riscv_beq.S ├── riscv_bge.S ├── riscv_bgeu.S ├── riscv_blt.S ├── riscv_bltu.S ├── riscv_bne.S ├── riscv_coreid.S ├── riscv_div.S ├── riscv_divu.S ├── riscv_divuw.S ├── riscv_divw.S ├── riscv_example.S ├── riscv_fadd.S ├── riscv_fcmp.S ├── riscv_fcvt.S ├── riscv_fcvt_w.S ├── riscv_fmadd.S ├── riscv_fmin.S ├── riscv_fp_ldst.S ├── riscv_fp_move.S ├── riscv_fp_structural.S ├── riscv_fsgnj.S ├── riscv_j.S ├── riscv_jal.S ├── riscv_jalr.S ├── riscv_jalr_j.S ├── riscv_jalr_r.S ├── riscv_lb.S ├── riscv_lbu.S ├── riscv_ld.S ├── riscv_lh.S ├── riscv_lhu.S ├── riscv_lui.S ├── riscv_lw.S ├── riscv_lwu.S ├── riscv_mul.S ├── riscv_mulh.S ├── riscv_mulhsu.S ├── riscv_mulhu.S ├── riscv_mulw.S ├── riscv_or.S ├── riscv_ori.S ├── riscv_rdnpc.S ├── riscv_rem.S ├── riscv_remu.S ├── riscv_remuw.S ├── riscv_remw.S ├── riscv_sb.S ├── riscv_sd.S ├── riscv_sh.S ├── riscv_simple.S ├── riscv_sll.S ├── riscv_slli.S ├── riscv_slliw.S ├── riscv_sllw.S ├── riscv_slt.S ├── riscv_slti.S ├── riscv_sltiu.S ├── riscv_sltu.S ├── riscv_sra.S ├── riscv_srai.S ├── riscv_sraiw.S ├── riscv_sraw.S ├── riscv_srl.S ├── riscv_srli.S ├── riscv_srliw.S ├── riscv_srlw.S ├── riscv_sub.S ├── riscv_subw.S ├── riscv_sw.S ├── riscv_vec_amoadd_d.S ├── riscv_vec_amoadd_w.S ├── riscv_vec_amoand_d.S ├── riscv_vec_amoand_w.S ├── riscv_vec_amomax_d.S ├── riscv_vec_amomax_w.S ├── riscv_vec_amomaxu_d.S ├── riscv_vec_amomaxu_w.S ├── riscv_vec_amomin_d.S ├── riscv_vec_amomin_w.S ├── riscv_vec_amominu_d.S ├── riscv_vec_amominu_w.S ├── riscv_vec_amoor_d.S ├── riscv_vec_amoor_w.S ├── riscv_vec_amoswap_d.S ├── riscv_vec_amoswap_w.S ├── riscv_vec_d_data.S ├── riscv_vec_fcvt-d-l.S ├── riscv_vec_fd_data.S ├── riscv_vec_fence.S ├── riscv_vec_fld.S ├── riscv_vec_flw.S ├── riscv_vec_fma.S ├── riscv_vec_fmovn.S ├── riscv_vec_fmovz.S ├── riscv_vec_fsd.S ├── riscv_vec_fsw.S ├── riscv_vec_fw_data.S ├── riscv_vec_imul.S ├── riscv_vec_lb.S ├── riscv_vec_lbu.S ├── riscv_vec_ld.S ├── riscv_vec_lh.S ├── riscv_vec_lhu.S ├── riscv_vec_lw.S ├── riscv_vec_lwu.S ├── riscv_vec_movn.S ├── riscv_vec_movz.S ├── riscv_vec_sb.S ├── riscv_vec_sd.S ├── riscv_vec_sh.S ├── riscv_vec_sw.S ├── riscv_vec_utidx.S ├── riscv_vec_vfmvv.S ├── riscv_vec_vmsv.S ├── riscv_vec_vmvv.S ├── riscv_vec_vvadd_d.S ├── riscv_vec_vvadd_fd.S ├── riscv_vec_vvadd_fw.S ├── riscv_vec_vvadd_w.S ├── riscv_vec_vvmul_d.S ├── riscv_vec_w_data.S ├── riscv_vec_wakeup.S ├── riscv_vsetvl.S ├── riscv_vvcfgivl.S ├── riscv_xor.S ├── riscv_xori.S ├── test.ld ├── test_macros.h └── test_macros_vec.h ├── src ├── asic.vh ├── defCommon.vh ├── fpu.v ├── fpu_common.v ├── fpu_config.v ├── fpu_fma_dp_pipeline.v ├── fpu_fma_sp_pipeline.v ├── fpu_recode_dp_pipeline.v ├── fpu_recode_sp_pipeline.v ├── inst.v ├── macros.vh ├── riscvConst.vh ├── riscvCore.v ├── riscvCoreNoCache.v ├── riscvDCacheArbiter.v ├── riscvInst.vh ├── riscvProc.v ├── riscvProcCtrl.v ├── riscvProcCtrlCnt.v ├── riscvProcCtrlSboard.v ├── riscvProcDivider.v ├── riscvProcDpath.v ├── riscvProcDpath_ALU.v ├── riscvProcDpath_BTB.v ├── riscvProcDpath_FSR.v ├── riscvProcDpath_PCR.v ├── riscvProcDpath_Regfile.v ├── riscvProcDpath_VEC.v ├── riscvProcMemory.v ├── riscvProcMultiplier.v ├── riscvProcWriteback.v ├── riscvProcWritebackArbiter.v ├── riscvScalarOnly.vh ├── riscvSingleCore.v ├── riscvTestHarness.v ├── vuVXU-B8-Config.vh ├── vuVXU-Opcode.vh ├── xbarCacheRefill_2ports.v ├── xbarCacheRefill_3ports.v └── xbarProcCache.v ├── top ├── L2TestHarness.v ├── htifOnChip.v ├── htifOnChip_1clk.v ├── offchip_HTIF.v ├── resiliency-scalar.v ├── resiliency.v ├── resiliency_onecache.v ├── riscvTop-scalar.v ├── riscvTop.v ├── sramL2.v ├── sramL2_256K.v ├── sramL2_64K.v ├── topTestHarness.v ├── xbarCoreL2-scalar.v └── xbarCoreL2.v ├── vclib ├── vcArith.v ├── vcDecoders.v ├── vcMemories.v ├── vcMuxes.v ├── vcQueues.v ├── vcRAMs.v ├── vcStateElements.v ├── vcTest.v ├── vcTestSink.v ├── vcTestSource.v └── vcTrace.v └── vector ├── interface.vh ├── rf-1r1w.v ├── vu.v ├── vuVCU.v ├── vuVMU-BHWDsel.v ├── vuVMU-Ctrl-ut-issue.v ├── vuVMU-Ctrl-ut-store.v ├── vuVMU-Ctrl-ut-top.v ├── vuVMU-Ctrl-ut-wb.v ├── vuVMU-Ctrl-ut.v ├── vuVMU-Ctrl-vec-load-issue.v ├── vuVMU-Ctrl-vec-load-wb.v ├── vuVMU-Ctrl-vec-store.v ├── vuVMU-Ctrl-vec-top.v ├── vuVMU-Ctrl-vec.v ├── vuVMU-QueueCount.v ├── vuVMU-ROQ-tag.v ├── vuVMU-ROQ.v ├── vuVMU.v ├── vuVXU-B8-Bank-Regfile.v ├── vuVXU-B8-Bank.v ├── vuVXU-B8-Config.vh ├── vuVXU-B8-Expand.v ├── vuVXU-B8-FU-alu.v ├── vuVXU-B8-FU-conv.v ├── vuVXU-B8-FU-fma.v ├── vuVXU-B8-FU-imul.v ├── vuVXU-B8-Fire.v ├── vuVXU-B8-Hazard.v ├── vuVXU-B8-Lane-LFU.v ├── vuVXU-B8-Lane-Xbar.v ├── vuVXU-B8-Lane.v ├── vuVXU-B8-Seq.v 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