├── .github ├── FUNDING.yml └── workflows │ └── build-test-on-push.yml ├── .gitignore ├── .vscode └── extensions.json ├── CMakeLists.txt ├── README.md ├── data └── test.mp3 ├── include └── README ├── lib ├── README ├── audio_output │ ├── library.json │ └── src │ │ ├── DACOutput.cpp │ │ ├── DACOutput.h │ │ ├── I2SOutput.cpp │ │ ├── I2SOutput.h │ │ ├── Output.cpp │ │ └── Output.h └── spiffs │ └── src │ ├── SPIFFS.cpp │ └── SPIFFS.h ├── partitions.csv ├── platformio.ini ├── sdkconfig.esp32dev ├── sdkconfig.esp32dev.old ├── src ├── CMakeLists.txt ├── config.cpp ├── config.h ├── main.cpp └── minimp3.h └── test └── README /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | github: [atomic14] 4 | patreon: atomic14 5 | ko_fi: atomic14 6 | -------------------------------------------------------------------------------- /.github/workflows/build-test-on-push.yml: -------------------------------------------------------------------------------- 1 | name: Build on push 2 | 3 | on: [push] 4 | 5 | jobs: 6 | build-test: 7 | runs-on: ubuntu-latest 8 | 9 | steps: 10 | - uses: actions/checkout@v2 11 | with: 12 | submodules: recursive 13 | - name: Cache pip 14 | uses: actions/cache@v2 15 | with: 16 | path: ~/.cache/pip 17 | key: ${{ runner.os }}-pip-${{ hashFiles('**/requirements.txt') }} 18 | restore-keys: | 19 | ${{ runner.os }}-pip- 20 | - name: Cache PlatformIO 21 | uses: actions/cache@v2 22 | with: 23 | path: ~/.platformio 24 | key: ${{ runner.os }}-${{ hashFiles('**/lockfiles') }} 25 | - name: Set up Python 26 | uses: actions/setup-python@v2 27 | with: 28 | python-version: 3.11 29 | - name: Install PlatformIO 30 | run: | 31 | python -m pip install --upgrade pip 32 | pip install --upgrade platformio 33 | - name: Run PlatformIO 34 | run: pio run 35 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .pio 2 | .vscode/.browse.c_cpp.db* 3 | .vscode/c_cpp_properties.json 4 | .vscode/launch.json 5 | .vscode/ipch 6 | -------------------------------------------------------------------------------- /.vscode/extensions.json: -------------------------------------------------------------------------------- 1 | { 2 | // See http://go.microsoft.com/fwlink/?LinkId=827846 3 | // for the documentation about the extensions.json format 4 | "recommendations": [ 5 | "platformio.platformio-ide" 6 | ], 7 | "unwantedRecommendations": [ 8 | "ms-vscode.cpptools-extension-pack" 9 | ] 10 | } 11 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.16.0) 2 | include($ENV{IDF_PATH}/tools/cmake/project.cmake) 3 | project(mp3-decoder-idf) 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | [![Build on push](https://github.com/cgreening/esp32-play-mp3-demo/actions/workflows/build-test-on-push.yml/badge.svg)](https://github.com/cgreening/esp32-play-mp3-demo/actions/workflows/build-test-on-push.yml) 2 | 3 | # ESP32 MP3 Player 4 | 5 | You can watch a video explanation of this code [here](https://youtu.be/kdKnddqCJbY) 6 | 7 | [![Demo Video](https://img.youtube.com/vi/kdKnddqCJbY/0.jpg)](https://www.youtube.com/watch?v=kdKnddqCJbY) 8 | 9 | This repo contains a simple demonstration of how to play an MP3 file on the ESP32. 10 | 11 | You'll need to use PlatformIO to run the code but you should be able to take the code accross to Arduino quite easily. 12 | 13 | You can configure the output to be either an I2S device or the built-in DAC to output the audio to a set of headphones or an analogue amplifier. 14 | 15 | Be aware that the DAC is extremely noisy so at low vollume levels most of the sound will be dominated by noise. It may be possible to reduce the noise by using a low pass filter on the output. 16 | 17 | In theory you should have a DC blocking capacitor between the output and headphones, but I found this to cause a large amount of noise. 18 | 19 | When using the DAC the left channel will be output on GPIO26 and the right channel will be output on GPIO25. 20 | 21 | I've added an optional volume control. You can connect a potentiometer between 3.3v and ground and connect it to one of the ADC channels. 22 | 23 | Make sure you upload the filesystem as the sample mp3 file is stored on SPIFFS. 24 | 25 | ## Configuration 26 | 27 | All the configuration settings are in the `config.h` file. 28 | 29 | ```c 30 | // comment this line out if you want to use the built-in DAC 31 | #define USE_I2S 32 | 33 | // speaker settings - if using I2S 34 | #define I2S_SPEAKER_SERIAL_CLOCK GPIO_NUM_19 35 | #define I2S_SPEAKER_LEFT_RIGHT_CLOCK GPIO_NUM_21 36 | #define I2S_SPEAKER_SERIAL_DATA GPIO_NUM_18 37 | #define I2S_SPEAKDER_SD_PIN GPIO_NUM_5 38 | 39 | // volume control - if required - comment this out if you don't want it 40 | #define VOLUME_CONTROL ADC1_CHANNEL_7 41 | 42 | // button - GPIO 0 is the built in button on most dev boards 43 | #define GPIO_BUTTON GPIO_NUM_0 44 | ``` 45 | -------------------------------------------------------------------------------- /data/test.mp3: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/atomic14/esp32-play-mp3-demo/332909583f1cf79388beffddd4ef0a95a1f347cc/data/test.mp3 -------------------------------------------------------------------------------- /include/README: -------------------------------------------------------------------------------- 1 | 2 | This directory is intended for project header files. 3 | 4 | A header file is a file containing C declarations and macro definitions 5 | to be shared between several project source files. You request the use of a 6 | header file in your project source file (C, C++, etc) located in `src` folder 7 | by including it, with the C preprocessing directive `#include'. 8 | 9 | ```src/main.c 10 | 11 | #include "header.h" 12 | 13 | int main (void) 14 | { 15 | ... 16 | } 17 | ``` 18 | 19 | Including a header file produces the same results as copying the header file 20 | into each source file that needs it. Such copying would be time-consuming 21 | and error-prone. With a header file, the related declarations appear 22 | in only one place. If they need to be changed, they can be changed in one 23 | place, and programs that include the header file will automatically use the 24 | new version when next recompiled. The header file eliminates the labor of 25 | finding and changing all the copies as well as the risk that a failure to 26 | find one copy will result in inconsistencies within a program. 27 | 28 | In C, the usual convention is to give header files names that end with `.h'. 29 | It is most portable to use only letters, digits, dashes, and underscores in 30 | header file names, and at most one dot. 31 | 32 | Read more about using header files in official GCC documentation: 33 | 34 | * Include Syntax 35 | * Include Operation 36 | * Once-Only Headers 37 | * Computed Includes 38 | 39 | https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html 40 | -------------------------------------------------------------------------------- /lib/README: -------------------------------------------------------------------------------- 1 | 2 | This directory is intended for project specific (private) libraries. 3 | PlatformIO will compile them to static libraries and link into executable file. 4 | 5 | The source code of each library should be placed in a an own separate directory 6 | ("lib/your_library_name/[here are source files]"). 7 | 8 | For example, see a structure of the following two libraries `Foo` and `Bar`: 9 | 10 | |--lib 11 | | | 12 | | |--Bar 13 | | | |--docs 14 | | | |--examples 15 | | | |--src 16 | | | |- Bar.c 17 | | | |- Bar.h 18 | | | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html 19 | | | 20 | | |--Foo 21 | | | |- Foo.c 22 | | | |- Foo.h 23 | | | 24 | | |- README --> THIS FILE 25 | | 26 | |- platformio.ini 27 | |--src 28 | |- main.c 29 | 30 | and a contents of `src/main.c`: 31 | ``` 32 | #include 33 | #include 34 | 35 | int main (void) 36 | { 37 | ... 38 | } 39 | 40 | ``` 41 | 42 | PlatformIO Library Dependency Finder will find automatically dependent 43 | libraries scanning project source files. 44 | 45 | More information about PlatformIO Library Dependency Finder 46 | - https://docs.platformio.org/page/librarymanager/ldf.html 47 | -------------------------------------------------------------------------------- /lib/audio_output/library.json: -------------------------------------------------------------------------------- 1 | { 2 | "build": { 3 | "flags": "-Ofast" 4 | } 5 | } -------------------------------------------------------------------------------- /lib/audio_output/src/DACOutput.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include "DACOutput.h" 3 | 4 | void DACOutput::start(int sample_rate) 5 | { 6 | // i2s config for writing both channels of I2S 7 | i2s_config_t i2s_config = { 8 | .mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_DAC_BUILT_IN), 9 | .sample_rate = (uint32_t)sample_rate, 10 | .bits_per_sample = I2S_BITS_PER_SAMPLE_16BIT, 11 | .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, 12 | .communication_format = I2S_COMM_FORMAT_STAND_MSB, 13 | .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, 14 | .dma_buf_count = 4, 15 | .dma_buf_len = 1024, 16 | .use_apll = false, 17 | .tx_desc_auto_clear = true, 18 | .fixed_mclk = 0}; 19 | //install and start i2s driver 20 | i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL); 21 | // enable the DAC channels 22 | i2s_set_dac_mode(I2S_DAC_CHANNEL_BOTH_EN); 23 | // clear the DMA buffers 24 | i2s_zero_dma_buffer(I2S_NUM_0); 25 | 26 | i2s_start(I2S_NUM_0); 27 | } 28 | -------------------------------------------------------------------------------- /lib/audio_output/src/DACOutput.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include "Output.h" 4 | 5 | /** 6 | * Base Class for both the ADC and I2S sampler 7 | **/ 8 | class DACOutput : public Output 9 | { 10 | public: 11 | // DAC can only be used with I2S_NUM_0 12 | DACOutput() : Output(I2S_NUM_0){}; 13 | void start(int sample_rate); 14 | virtual uint16_t process_sample(int16_t sample) 15 | { 16 | //return sample; 17 | int32_t raw = sample; 18 | // DAC needs unsigned 16 bit samples 19 | return (uint16_t)(raw + 32768); 20 | } 21 | }; 22 | -------------------------------------------------------------------------------- /lib/audio_output/src/I2SOutput.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include "I2SOutput.h" 3 | 4 | I2SOutput::I2SOutput(i2s_port_t i2s_port, i2s_pin_config_t &i2s_pins) : Output(i2s_port), m_i2s_pins(i2s_pins) 5 | { 6 | } 7 | 8 | void I2SOutput::start(int sample_rate) 9 | { 10 | // i2s config for writing both channels of I2S 11 | i2s_config_t i2s_config = { 12 | .mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_TX), 13 | .sample_rate = (uint32_t)sample_rate, 14 | .bits_per_sample = I2S_BITS_PER_SAMPLE_16BIT, 15 | .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, 16 | .communication_format = I2S_COMM_FORMAT_STAND_I2S, 17 | .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, 18 | .dma_buf_count = 4, 19 | .dma_buf_len = 1024, 20 | .use_apll = false, 21 | .tx_desc_auto_clear = true, 22 | .fixed_mclk = 0}; 23 | //install and start i2s driver 24 | i2s_driver_install(m_i2s_port, &i2s_config, 0, NULL); 25 | // set up the i2s pins 26 | i2s_set_pin(m_i2s_port, &m_i2s_pins); 27 | // clear the DMA buffers 28 | i2s_zero_dma_buffer(m_i2s_port); 29 | 30 | i2s_start(m_i2s_port); 31 | } 32 | -------------------------------------------------------------------------------- /lib/audio_output/src/I2SOutput.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include "Output.h" 4 | 5 | /** 6 | * Base Class for both the ADC and I2S sampler 7 | **/ 8 | class I2SOutput : public Output 9 | { 10 | private: 11 | i2s_pin_config_t m_i2s_pins; 12 | 13 | public: 14 | I2SOutput(i2s_port_t i2s_port, i2s_pin_config_t &i2s_pins); 15 | void start(int sample_rate); 16 | }; 17 | -------------------------------------------------------------------------------- /lib/audio_output/src/Output.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include "Output.h" 3 | #include 4 | #include 5 | 6 | static const char *TAG = "OUT"; 7 | 8 | // number of frames to try and send at once (a frame is a left and right sample) 9 | const int NUM_FRAMES_TO_SEND = 256; 10 | 11 | Output::Output(i2s_port_t i2s_port) : m_i2s_port(i2s_port) 12 | { 13 | frames_buffer = (int16_t *)malloc(2 * sizeof(int16_t) * NUM_FRAMES_TO_SEND); 14 | } 15 | 16 | Output::~Output() 17 | { 18 | free(frames_buffer); 19 | } 20 | 21 | void Output::stop() 22 | { 23 | // stop the i2S driver 24 | i2s_stop(m_i2s_port); 25 | i2s_driver_uninstall(m_i2s_port); 26 | } 27 | 28 | void Output::write(int16_t *samples, int frames) 29 | { 30 | // this will contain the prepared samples for sending to the I2S device 31 | int frame_index = 0; 32 | while (frame_index < frames) 33 | { 34 | // fill up the frames buffer with the next NUM_FRAMES_TO_SEND frames 35 | int frames_to_send = 0; 36 | for (int i = 0; i < NUM_FRAMES_TO_SEND && frame_index < frames; i++) 37 | { 38 | int left_sample = process_sample(volume * float(samples[frame_index * 2])); 39 | int right_sample = process_sample(volume * float(samples[frame_index * 2 + 1])); 40 | frames_buffer[i * 2] = left_sample; 41 | frames_buffer[i * 2 + 1] = right_sample; 42 | frames_to_send++; 43 | frame_index++; 44 | } 45 | // write data to the i2s peripheral - this will block until the data is sent 46 | size_t bytes_written = 0; 47 | i2s_write(m_i2s_port, frames_buffer, frames_to_send * sizeof(int16_t) * 2, &bytes_written, portMAX_DELAY); 48 | if (bytes_written != frames_to_send * sizeof(int16_t) * 2) 49 | { 50 | ESP_LOGE(TAG, "Did not write all bytes"); 51 | } 52 | } 53 | } 54 | -------------------------------------------------------------------------------- /lib/audio_output/src/Output.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | 6 | /** 7 | * Base Class for both the DAC and I2S output 8 | **/ 9 | class Output 10 | { 11 | protected: 12 | i2s_port_t m_i2s_port = I2S_NUM_0; 13 | 14 | int16_t *frames_buffer; 15 | float volume = 1.0f; 16 | 17 | public: 18 | Output(i2s_port_t i2s_port); 19 | virtual ~Output(); 20 | virtual void start(int sample_rate) = 0; 21 | void stop(); 22 | // override this in derived classes to turn the sample into 23 | // something the output device expects - for the default case 24 | // this is simply a pass through 25 | virtual uint16_t process_sample(int16_t sample) { return sample; } 26 | // NOTE - a frame consists of both a left and a right sample 27 | void write(int16_t *samples, int frames); 28 | // set the volume between 0 and 4096 29 | void set_volume(float volume) 30 | { 31 | this->volume = volume; 32 | } 33 | }; 34 | -------------------------------------------------------------------------------- /lib/spiffs/src/SPIFFS.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include "esp_err.h" 6 | #include "esp_log.h" 7 | #include "esp_spiffs.h" 8 | 9 | #include "SPIFFS.h" 10 | 11 | static const char *TAG = "SPIFFS"; 12 | 13 | #define SPI_DMA_CHAN 1 14 | 15 | SPIFFS::SPIFFS(const char *mount_point) 16 | { 17 | m_mount_point = mount_point; 18 | 19 | esp_vfs_spiffs_conf_t mount_cofig = { 20 | .base_path = mount_point, 21 | .partition_label = NULL, 22 | .max_files = 5, 23 | .format_if_mount_failed = true}; 24 | 25 | ESP_LOGI(TAG, "Initializing SPIFFS"); 26 | 27 | esp_err_t ret = esp_vfs_spiffs_register(&mount_cofig); 28 | 29 | if (ret != ESP_OK) 30 | { 31 | ESP_LOGE(TAG, "Failed to initialize SPIFFS"); 32 | return; 33 | } 34 | } 35 | 36 | SPIFFS::~SPIFFS() 37 | { 38 | esp_vfs_spiffs_unregister(NULL); 39 | ESP_LOGI(TAG, "SPIFFS unmounted"); 40 | } -------------------------------------------------------------------------------- /lib/spiffs/src/SPIFFS.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | class SPIFFS 6 | { 7 | private: 8 | std::string m_mount_point; 9 | public: 10 | SPIFFS(const char *mount_point); 11 | ~SPIFFS(); 12 | const std::string &get_mount_point() { return m_mount_point; } 13 | }; -------------------------------------------------------------------------------- /partitions.csv: -------------------------------------------------------------------------------- 1 | # Name, Type, SubType, Offset, Size, Flags 2 | nvs, data, nvs, 0x9000, 0x5000, 3 | otadata, data, ota, 0xe000, 0x2000, 4 | app0, app, ota_0, 0x10000, 0x100000, 5 | spiffs, data, spiffs, 0x110000,0x2F0000, -------------------------------------------------------------------------------- /platformio.ini: -------------------------------------------------------------------------------- 1 | ; PlatformIO Project Configuration File 2 | ; 3 | ; Build options: build flags, source filter 4 | ; Upload options: custom upload port, speed and extra flags 5 | ; Library options: dependencies, extra library storages 6 | ; Advanced options: extra scripting 7 | ; 8 | ; Please visit documentation for the other options and examples 9 | ; https://docs.platformio.org/page/projectconf.html 10 | 11 | [env:esp32dev] 12 | platform = espressif32 13 | board = esp32dev 14 | framework = espidf 15 | upload_port = /dev/cu.SLAB_USBtoUART 16 | monitor_port = /dev/cu.SLAB_USBtoUART 17 | monitor_speed = 115200 18 | monitor_filters = esp32_exception_decoder 19 | board_build.partitions = partitions.csv 20 | build_flags = -Ofast -------------------------------------------------------------------------------- /sdkconfig.esp32dev: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file. DO NOT EDIT. 3 | # Espressif IoT Development Framework (ESP-IDF) Project Configuration 4 | # 5 | CONFIG_SOC_BROWNOUT_RESET_SUPPORTED="Not determined" 6 | CONFIG_SOC_TWAI_BRP_DIV_SUPPORTED="Not determined" 7 | CONFIG_SOC_DPORT_WORKAROUND="Not determined" 8 | CONFIG_SOC_CAPS_ECO_VER_MAX=3 9 | CONFIG_SOC_ADC_SUPPORTED=y 10 | CONFIG_SOC_DAC_SUPPORTED=y 11 | CONFIG_SOC_MCPWM_SUPPORTED=y 12 | CONFIG_SOC_SDMMC_HOST_SUPPORTED=y 13 | CONFIG_SOC_BT_SUPPORTED=y 14 | CONFIG_SOC_PCNT_SUPPORTED=y 15 | CONFIG_SOC_WIFI_SUPPORTED=y 16 | CONFIG_SOC_SDIO_SLAVE_SUPPORTED=y 17 | CONFIG_SOC_TWAI_SUPPORTED=y 18 | CONFIG_SOC_EMAC_SUPPORTED=y 19 | CONFIG_SOC_ULP_SUPPORTED=y 20 | CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y 21 | CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y 22 | CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y 23 | CONFIG_SOC_RTC_MEM_SUPPORTED=y 24 | CONFIG_SOC_I2S_SUPPORTED=y 25 | CONFIG_SOC_RMT_SUPPORTED=y 26 | CONFIG_SOC_SDM_SUPPORTED=y 27 | CONFIG_SOC_SUPPORT_COEXISTENCE=y 28 | CONFIG_SOC_AES_SUPPORTED=y 29 | CONFIG_SOC_MPI_SUPPORTED=y 30 | CONFIG_SOC_SHA_SUPPORTED=y 31 | CONFIG_SOC_FLASH_ENC_SUPPORTED=y 32 | CONFIG_SOC_SECURE_BOOT_SUPPORTED=y 33 | CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y 34 | CONFIG_SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL=5 35 | CONFIG_SOC_XTAL_SUPPORT_26M=y 36 | CONFIG_SOC_XTAL_SUPPORT_40M=y 37 | CONFIG_SOC_XTAL_SUPPORT_AUTO_DETECT=y 38 | CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y 39 | CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y 40 | CONFIG_SOC_ADC_DMA_SUPPORTED=y 41 | CONFIG_SOC_ADC_PERIPH_NUM=2 42 | CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10 43 | CONFIG_SOC_ADC_ATTEN_NUM=4 44 | CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2 45 | CONFIG_SOC_ADC_PATT_LEN_MAX=16 46 | CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=9 47 | CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 48 | CONFIG_SOC_ADC_DIGI_RESULT_BYTES=2 49 | CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 50 | CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=2 51 | CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=20 52 | CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=9 53 | CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 54 | CONFIG_SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256=y 55 | CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y 56 | CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=5 57 | CONFIG_SOC_CPU_CORES_NUM=2 58 | CONFIG_SOC_CPU_INTR_NUM=32 59 | CONFIG_SOC_CPU_HAS_FPU=y 60 | CONFIG_SOC_CPU_BREAKPOINTS_NUM=2 61 | CONFIG_SOC_CPU_WATCHPOINTS_NUM=2 62 | CONFIG_SOC_CPU_WATCHPOINT_SIZE=64 63 | CONFIG_SOC_DAC_PERIPH_NUM=2 64 | CONFIG_SOC_DAC_RESOLUTION=8 65 | CONFIG_SOC_GPIO_PORT=1 66 | CONFIG_SOC_GPIO_PIN_COUNT=40 67 | CONFIG_SOC_GPIO_VALID_GPIO_MASK=0xFFFFFFFFFF 68 | CONFIG_SOC_GPIO_SUPPORT_SLP_SWITCH=y 69 | CONFIG_SOC_I2C_NUM=2 70 | CONFIG_SOC_I2C_FIFO_LEN=32 71 | CONFIG_SOC_I2C_SUPPORT_SLAVE=y 72 | CONFIG_SOC_I2C_SUPPORT_APB=y 73 | CONFIG_SOC_CLK_APLL_SUPPORTED=y 74 | CONFIG_SOC_APLL_MULTIPLIER_OUT_MIN_HZ=350000000 75 | CONFIG_SOC_APLL_MULTIPLIER_OUT_MAX_HZ=500000000 76 | CONFIG_SOC_APLL_MIN_HZ=5303031 77 | CONFIG_SOC_APLL_MAX_HZ=125000000 78 | CONFIG_SOC_I2S_NUM=2 79 | CONFIG_SOC_I2S_HW_VERSION_1=y 80 | CONFIG_SOC_I2S_SUPPORTS_APLL=y 81 | CONFIG_SOC_I2S_SUPPORTS_PDM=y 82 | CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y 83 | CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y 84 | CONFIG_SOC_I2S_SUPPORTS_ADC_DAC=y 85 | CONFIG_SOC_I2S_SUPPORTS_ADC=y 86 | CONFIG_SOC_I2S_SUPPORTS_DAC=y 87 | CONFIG_SOC_I2S_SUPPORTS_LCD_CAMERA=y 88 | CONFIG_SOC_I2S_TRANS_SIZE_ALIGN_WORD=y 89 | CONFIG_SOC_I2S_LCD_I80_VARIANT=y 90 | CONFIG_SOC_LCD_I80_SUPPORTED=y 91 | CONFIG_SOC_LCD_I80_BUSES=2 92 | CONFIG_SOC_LCD_I80_BUS_WIDTH=24 93 | CONFIG_SOC_LEDC_HAS_TIMER_SPECIFIC_MUX=y 94 | CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y 95 | CONFIG_SOC_LEDC_SUPPORT_REF_TICK=y 96 | CONFIG_SOC_LEDC_SUPPORT_HS_MODE=y 97 | CONFIG_SOC_LEDC_CHANNEL_NUM=8 98 | CONFIG_SOC_LEDC_TIMER_BIT_WIDE_NUM=20 99 | CONFIG_SOC_MCPWM_GROUPS=2 100 | CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3 101 | CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3 102 | CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2 103 | CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2 104 | CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2 105 | CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3 106 | CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y 107 | CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3 108 | CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3 109 | CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 110 | CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 111 | CONFIG_SOC_PCNT_GROUPS=1 112 | CONFIG_SOC_PCNT_UNITS_PER_GROUP=8 113 | CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2 114 | CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2 115 | CONFIG_SOC_RMT_GROUPS=1 116 | CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=8 117 | CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=8 118 | CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8 119 | CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=64 120 | CONFIG_SOC_RMT_SUPPORT_REF_TICK=y 121 | CONFIG_SOC_RMT_SUPPORT_APB=y 122 | CONFIG_SOC_RMT_CHANNEL_CLK_INDEPENDENT=y 123 | CONFIG_SOC_RTCIO_PIN_COUNT=18 124 | CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y 125 | CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y 126 | CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y 127 | CONFIG_SOC_SDM_GROUPS=1 128 | CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8 129 | CONFIG_SOC_SPI_HD_BOTH_INOUT_SUPPORTED=y 130 | CONFIG_SOC_SPI_AS_CS_SUPPORTED=y 131 | CONFIG_SOC_SPI_PERIPH_NUM=3 132 | CONFIG_SOC_SPI_DMA_CHAN_NUM=2 133 | CONFIG_SOC_SPI_MAX_CS_NUM=3 134 | CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 135 | CONFIG_SOC_SPI_MAX_PRE_DIVIDER=8192 136 | CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y 137 | CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y 138 | CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y 139 | CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y 140 | CONFIG_SOC_TIMER_GROUPS=2 141 | CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2 142 | CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=64 143 | CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4 144 | CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y 145 | CONFIG_SOC_TOUCH_VERSION_1=y 146 | CONFIG_SOC_TOUCH_SENSOR_NUM=10 147 | CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF 148 | CONFIG_SOC_TWAI_BRP_MIN=2 149 | CONFIG_SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT=y 150 | CONFIG_SOC_UART_NUM=3 151 | CONFIG_SOC_UART_SUPPORT_APB_CLK=y 152 | CONFIG_SOC_UART_SUPPORT_REF_TICK=y 153 | CONFIG_SOC_UART_FIFO_LEN=128 154 | CONFIG_SOC_UART_BITRATE_MAX=5000000 155 | CONFIG_SOC_SPIRAM_SUPPORTED=y 156 | CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y 157 | CONFIG_SOC_SHA_SUPPORT_PARALLEL_ENG=y 158 | CONFIG_SOC_SHA_SUPPORT_SHA1=y 159 | CONFIG_SOC_SHA_SUPPORT_SHA256=y 160 | CONFIG_SOC_SHA_SUPPORT_SHA384=y 161 | CONFIG_SOC_SHA_SUPPORT_SHA512=y 162 | CONFIG_SOC_RSA_MAX_BIT_LEN=4096 163 | CONFIG_SOC_AES_SUPPORT_AES_128=y 164 | CONFIG_SOC_AES_SUPPORT_AES_192=y 165 | CONFIG_SOC_AES_SUPPORT_AES_256=y 166 | CONFIG_SOC_SECURE_BOOT_V1=y 167 | CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=y 168 | CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32 169 | CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 170 | CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y 171 | CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y 172 | CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y 173 | CONFIG_SOC_PM_SUPPORT_RTC_FAST_MEM_PD=y 174 | CONFIG_SOC_PM_SUPPORT_RTC_SLOW_MEM_PD=y 175 | CONFIG_SOC_SDMMC_USE_IOMUX=y 176 | CONFIG_SOC_SDMMC_NUM_SLOTS=2 177 | CONFIG_SOC_WIFI_WAPI_SUPPORT=y 178 | CONFIG_SOC_WIFI_CSI_SUPPORT=y 179 | CONFIG_SOC_WIFI_MESH_SUPPORT=y 180 | CONFIG_SOC_BLE_SUPPORTED=y 181 | CONFIG_SOC_BLE_MESH_SUPPORTED=y 182 | CONFIG_SOC_BT_CLASSIC_SUPPORTED=y 183 | CONFIG_IDF_CMAKE=y 184 | CONFIG_IDF_TARGET_ARCH_XTENSA=y 185 | CONFIG_IDF_TARGET_ARCH="xtensa" 186 | CONFIG_IDF_TARGET="esp32" 187 | CONFIG_IDF_TARGET_ESP32=y 188 | CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000 189 | 190 | # 191 | # Build type 192 | # 193 | CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y 194 | # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set 195 | CONFIG_APP_BUILD_GENERATE_BINARIES=y 196 | CONFIG_APP_BUILD_BOOTLOADER=y 197 | CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y 198 | # CONFIG_APP_REPRODUCIBLE_BUILD is not set 199 | # CONFIG_APP_NO_BLOBS is not set 200 | # CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set 201 | # CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set 202 | # end of Build type 203 | 204 | # 205 | # Bootloader config 206 | # 207 | CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 208 | CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y 209 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set 210 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set 211 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set 212 | # CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set 213 | # CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set 214 | # CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set 215 | CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y 216 | # CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set 217 | # CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set 218 | CONFIG_BOOTLOADER_LOG_LEVEL=3 219 | # CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set 220 | CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y 221 | # CONFIG_BOOTLOADER_FACTORY_RESET is not set 222 | # CONFIG_BOOTLOADER_APP_TEST is not set 223 | CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y 224 | CONFIG_BOOTLOADER_WDT_ENABLE=y 225 | # CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set 226 | CONFIG_BOOTLOADER_WDT_TIME_MS=9000 227 | # CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set 228 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set 229 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set 230 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set 231 | CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 232 | # CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set 233 | CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y 234 | # end of Bootloader config 235 | 236 | # 237 | # Security features 238 | # 239 | CONFIG_SECURE_BOOT_V1_SUPPORTED=y 240 | # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set 241 | # CONFIG_SECURE_BOOT is not set 242 | # CONFIG_SECURE_FLASH_ENC_ENABLED is not set 243 | # end of Security features 244 | 245 | # 246 | # Application manager 247 | # 248 | CONFIG_APP_COMPILE_TIME_DATE=y 249 | # CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set 250 | # CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set 251 | # CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set 252 | CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 253 | # end of Application manager 254 | 255 | CONFIG_ESP_ROM_HAS_CRC_LE=y 256 | CONFIG_ESP_ROM_HAS_CRC_BE=y 257 | CONFIG_ESP_ROM_HAS_JPEG_DECODE=y 258 | CONFIG_ESP_ROM_SUPPORT_MULTIPLE_UART=y 259 | CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y 260 | 261 | # 262 | # Serial flasher config 263 | # 264 | # CONFIG_ESPTOOLPY_NO_STUB is not set 265 | # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set 266 | # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set 267 | CONFIG_ESPTOOLPY_FLASHMODE_DIO=y 268 | # CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set 269 | CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y 270 | CONFIG_ESPTOOLPY_FLASHMODE="dio" 271 | # CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set 272 | CONFIG_ESPTOOLPY_FLASHFREQ_40M=y 273 | # CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set 274 | # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set 275 | CONFIG_ESPTOOLPY_FLASHFREQ="40m" 276 | # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set 277 | CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y 278 | # CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set 279 | # CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set 280 | # CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set 281 | # CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set 282 | # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set 283 | # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set 284 | CONFIG_ESPTOOLPY_FLASHSIZE="2MB" 285 | # CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set 286 | CONFIG_ESPTOOLPY_BEFORE_RESET=y 287 | # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set 288 | CONFIG_ESPTOOLPY_BEFORE="default_reset" 289 | CONFIG_ESPTOOLPY_AFTER_RESET=y 290 | # CONFIG_ESPTOOLPY_AFTER_NORESET is not set 291 | CONFIG_ESPTOOLPY_AFTER="hard_reset" 292 | CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 293 | # end of Serial flasher config 294 | 295 | # 296 | # Partition Table 297 | # 298 | CONFIG_PARTITION_TABLE_SINGLE_APP=y 299 | # CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set 300 | # CONFIG_PARTITION_TABLE_TWO_OTA is not set 301 | # CONFIG_PARTITION_TABLE_CUSTOM is not set 302 | CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" 303 | CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" 304 | CONFIG_PARTITION_TABLE_OFFSET=0x8000 305 | CONFIG_PARTITION_TABLE_MD5=y 306 | # end of Partition Table 307 | 308 | # 309 | # Compiler options 310 | # 311 | CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y 312 | # CONFIG_COMPILER_OPTIMIZATION_SIZE is not set 313 | # CONFIG_COMPILER_OPTIMIZATION_PERF is not set 314 | # CONFIG_COMPILER_OPTIMIZATION_NONE is not set 315 | CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y 316 | # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set 317 | # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set 318 | CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y 319 | CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 320 | # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set 321 | CONFIG_COMPILER_HIDE_PATHS_MACROS=y 322 | # CONFIG_COMPILER_CXX_EXCEPTIONS is not set 323 | # CONFIG_COMPILER_CXX_RTTI is not set 324 | CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y 325 | # CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set 326 | # CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set 327 | # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set 328 | # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set 329 | # CONFIG_COMPILER_DUMP_RTL_FILES is not set 330 | # end of Compiler options 331 | 332 | # 333 | # Component config 334 | # 335 | 336 | # 337 | # Application Level Tracing 338 | # 339 | # CONFIG_APPTRACE_DEST_JTAG is not set 340 | CONFIG_APPTRACE_DEST_NONE=y 341 | # CONFIG_APPTRACE_DEST_UART1 is not set 342 | # CONFIG_APPTRACE_DEST_UART2 is not set 343 | CONFIG_APPTRACE_DEST_UART_NONE=y 344 | CONFIG_APPTRACE_UART_TASK_PRIO=1 345 | CONFIG_APPTRACE_LOCK_ENABLE=y 346 | # end of Application Level Tracing 347 | 348 | # 349 | # Bluetooth 350 | # 351 | # CONFIG_BT_ENABLED is not set 352 | # end of Bluetooth 353 | 354 | # 355 | # Driver Configurations 356 | # 357 | 358 | # 359 | # Legacy ADC Configuration 360 | # 361 | CONFIG_ADC_DISABLE_DAC=y 362 | # CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set 363 | 364 | # 365 | # Legacy ADC Calibration Configuration 366 | # 367 | CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y 368 | CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y 369 | CONFIG_ADC_CAL_LUT_ENABLE=y 370 | # CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set 371 | # end of Legacy ADC Calibration Configuration 372 | # end of Legacy ADC Configuration 373 | 374 | # 375 | # SPI Configuration 376 | # 377 | # CONFIG_SPI_MASTER_IN_IRAM is not set 378 | CONFIG_SPI_MASTER_ISR_IN_IRAM=y 379 | # CONFIG_SPI_SLAVE_IN_IRAM is not set 380 | CONFIG_SPI_SLAVE_ISR_IN_IRAM=y 381 | # end of SPI Configuration 382 | 383 | # 384 | # TWAI Configuration 385 | # 386 | # CONFIG_TWAI_ISR_IN_IRAM is not set 387 | # CONFIG_TWAI_ERRATA_FIX_BUS_OFF_REC is not set 388 | # CONFIG_TWAI_ERRATA_FIX_TX_INTR_LOST is not set 389 | # CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID is not set 390 | # CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT is not set 391 | # end of TWAI Configuration 392 | 393 | # 394 | # UART Configuration 395 | # 396 | # CONFIG_UART_ISR_IN_IRAM is not set 397 | # end of UART Configuration 398 | 399 | # 400 | # GPIO Configuration 401 | # 402 | # CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL is not set 403 | # CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set 404 | # end of GPIO Configuration 405 | 406 | # 407 | # Sigma Delta Modulator Configuration 408 | # 409 | # CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set 410 | # CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set 411 | # CONFIG_SDM_ENABLE_DEBUG_LOG is not set 412 | # end of Sigma Delta Modulator Configuration 413 | 414 | # 415 | # GPTimer Configuration 416 | # 417 | # CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set 418 | # CONFIG_GPTIMER_ISR_IRAM_SAFE is not set 419 | # CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set 420 | # CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set 421 | # end of GPTimer Configuration 422 | 423 | # 424 | # PCNT Configuration 425 | # 426 | # CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set 427 | # CONFIG_PCNT_ISR_IRAM_SAFE is not set 428 | # CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set 429 | # CONFIG_PCNT_ENABLE_DEBUG_LOG is not set 430 | # end of PCNT Configuration 431 | 432 | # 433 | # RMT Configuration 434 | # 435 | # CONFIG_RMT_ISR_IRAM_SAFE is not set 436 | # CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set 437 | # CONFIG_RMT_ENABLE_DEBUG_LOG is not set 438 | # end of RMT Configuration 439 | 440 | # 441 | # MCPWM Configuration 442 | # 443 | # CONFIG_MCPWM_ISR_IRAM_SAFE is not set 444 | # CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set 445 | # CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set 446 | # CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set 447 | # end of MCPWM Configuration 448 | 449 | # 450 | # I2S Configuration 451 | # 452 | # CONFIG_I2S_ISR_IRAM_SAFE is not set 453 | # CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set 454 | # CONFIG_I2S_ENABLE_DEBUG_LOG is not set 455 | # end of I2S Configuration 456 | # end of Driver Configurations 457 | 458 | # 459 | # eFuse Bit Manager 460 | # 461 | # CONFIG_EFUSE_CUSTOM_TABLE is not set 462 | # CONFIG_EFUSE_VIRTUAL is not set 463 | # CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set 464 | CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y 465 | # CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set 466 | CONFIG_EFUSE_MAX_BLK_LEN=192 467 | # end of eFuse Bit Manager 468 | 469 | # 470 | # ESP-TLS 471 | # 472 | CONFIG_ESP_TLS_USING_MBEDTLS=y 473 | # CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set 474 | # CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set 475 | # CONFIG_ESP_TLS_SERVER is not set 476 | # CONFIG_ESP_TLS_PSK_VERIFICATION is not set 477 | # CONFIG_ESP_TLS_INSECURE is not set 478 | # end of ESP-TLS 479 | 480 | # 481 | # ADC and ADC Calibration 482 | # 483 | # CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set 484 | # CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set 485 | 486 | # 487 | # ADC Calibration Configurations 488 | # 489 | CONFIG_ADC_CALI_EFUSE_TP_ENABLE=y 490 | CONFIG_ADC_CALI_EFUSE_VREF_ENABLE=y 491 | CONFIG_ADC_CALI_LUT_ENABLE=y 492 | # end of ADC Calibration Configurations 493 | 494 | CONFIG_ADC_DISABLE_DAC_OUTPUT=y 495 | # end of ADC and ADC Calibration 496 | 497 | # 498 | # Common ESP-related 499 | # 500 | CONFIG_ESP_ERR_TO_NAME_LOOKUP=y 501 | # end of Common ESP-related 502 | 503 | # 504 | # Ethernet 505 | # 506 | CONFIG_ETH_ENABLED=y 507 | CONFIG_ETH_USE_ESP32_EMAC=y 508 | CONFIG_ETH_PHY_INTERFACE_RMII=y 509 | CONFIG_ETH_RMII_CLK_INPUT=y 510 | # CONFIG_ETH_RMII_CLK_OUTPUT is not set 511 | CONFIG_ETH_RMII_CLK_IN_GPIO=0 512 | CONFIG_ETH_DMA_BUFFER_SIZE=512 513 | CONFIG_ETH_DMA_RX_BUFFER_NUM=10 514 | CONFIG_ETH_DMA_TX_BUFFER_NUM=10 515 | CONFIG_ETH_USE_SPI_ETHERNET=y 516 | # CONFIG_ETH_SPI_ETHERNET_DM9051 is not set 517 | # CONFIG_ETH_SPI_ETHERNET_W5500 is not set 518 | # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set 519 | # CONFIG_ETH_USE_OPENETH is not set 520 | # CONFIG_ETH_TRANSMIT_MUTEX is not set 521 | # end of Ethernet 522 | 523 | # 524 | # Event Loop Library 525 | # 526 | # CONFIG_ESP_EVENT_LOOP_PROFILING is not set 527 | CONFIG_ESP_EVENT_POST_FROM_ISR=y 528 | CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y 529 | # end of Event Loop Library 530 | 531 | # 532 | # GDB Stub 533 | # 534 | # end of GDB Stub 535 | 536 | # 537 | # ESP HTTP client 538 | # 539 | CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y 540 | # CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set 541 | CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y 542 | # end of ESP HTTP client 543 | 544 | # 545 | # HTTP Server 546 | # 547 | CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 548 | CONFIG_HTTPD_MAX_URI_LEN=512 549 | CONFIG_HTTPD_ERR_RESP_NO_DELAY=y 550 | CONFIG_HTTPD_PURGE_BUF_LEN=32 551 | # CONFIG_HTTPD_LOG_PURGE_DATA is not set 552 | # CONFIG_HTTPD_WS_SUPPORT is not set 553 | # CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set 554 | # end of HTTP Server 555 | 556 | # 557 | # ESP HTTPS OTA 558 | # 559 | # CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set 560 | # CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set 561 | # end of ESP HTTPS OTA 562 | 563 | # 564 | # ESP HTTPS server 565 | # 566 | # CONFIG_ESP_HTTPS_SERVER_ENABLE is not set 567 | # end of ESP HTTPS server 568 | 569 | # 570 | # Hardware Settings 571 | # 572 | 573 | # 574 | # MAC Config 575 | # 576 | CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y 577 | CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y 578 | CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y 579 | CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y 580 | # CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set 581 | CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR=y 582 | CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES=4 583 | # end of MAC Config 584 | 585 | # 586 | # Sleep Config 587 | # 588 | CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y 589 | CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y 590 | # CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set 591 | # CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND is not set 592 | CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 593 | # end of Sleep Config 594 | 595 | # 596 | # RTC Clock Config 597 | # 598 | CONFIG_RTC_CLK_SRC_INT_RC=y 599 | # CONFIG_RTC_CLK_SRC_EXT_CRYS is not set 600 | # CONFIG_RTC_CLK_SRC_EXT_OSC is not set 601 | # CONFIG_RTC_CLK_SRC_INT_8MD256 is not set 602 | CONFIG_RTC_CLK_CAL_CYCLES=1024 603 | # end of RTC Clock Config 604 | 605 | # 606 | # Peripheral Control 607 | # 608 | # CONFIG_PERIPH_CTRL_FUNC_IN_IRAM is not set 609 | # end of Peripheral Control 610 | 611 | # 612 | # MMU Config 613 | # 614 | CONFIG_MMU_PAGE_SIZE_64KB=y 615 | CONFIG_MMU_PAGE_MODE="64KB" 616 | CONFIG_MMU_PAGE_SIZE=0x10000 617 | # end of MMU Config 618 | 619 | CONFIG_ESP32_REV_MIN_0=y 620 | # CONFIG_ESP32_REV_MIN_1 is not set 621 | # CONFIG_ESP32_REV_MIN_2 is not set 622 | # CONFIG_ESP32_REV_MIN_3 is not set 623 | CONFIG_ESP32_REV_MIN=0 624 | 625 | # 626 | # Main XTAL Config 627 | # 628 | # CONFIG_XTAL_FREQ_26 is not set 629 | CONFIG_XTAL_FREQ_40=y 630 | # CONFIG_XTAL_FREQ_AUTO is not set 631 | CONFIG_XTAL_FREQ=40 632 | # end of Main XTAL Config 633 | # end of Hardware Settings 634 | 635 | # 636 | # LCD and Touch Panel 637 | # 638 | 639 | # 640 | # LCD Touch Drivers are maintained in the IDF Component Registry 641 | # 642 | 643 | # 644 | # LCD Peripheral Configuration 645 | # 646 | CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32 647 | # CONFIG_LCD_ENABLE_DEBUG_LOG is not set 648 | # end of LCD Peripheral Configuration 649 | # end of LCD and Touch Panel 650 | 651 | # 652 | # ESP NETIF Adapter 653 | # 654 | CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 655 | CONFIG_ESP_NETIF_TCPIP_LWIP=y 656 | # CONFIG_ESP_NETIF_LOOPBACK is not set 657 | # CONFIG_ESP_NETIF_L2_TAP is not set 658 | # CONFIG_ESP_NETIF_BRIDGE_EN is not set 659 | # end of ESP NETIF Adapter 660 | 661 | # 662 | # PHY 663 | # 664 | CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y 665 | # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set 666 | CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 667 | CONFIG_ESP_PHY_MAX_TX_POWER=20 668 | CONFIG_ESP_PHY_REDUCE_TX_POWER=y 669 | # end of PHY 670 | 671 | # 672 | # Power Management 673 | # 674 | # CONFIG_PM_ENABLE is not set 675 | # end of Power Management 676 | 677 | # 678 | # ESP PSRAM 679 | # 680 | # CONFIG_SPIRAM is not set 681 | # end of ESP PSRAM 682 | 683 | # 684 | # ESP Ringbuf 685 | # 686 | # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set 687 | # CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set 688 | # end of ESP Ringbuf 689 | 690 | # 691 | # ESP System Settings 692 | # 693 | # CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set 694 | # CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 is not set 695 | CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y 696 | CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=240 697 | 698 | # 699 | # Memory 700 | # 701 | # CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set 702 | # end of Memory 703 | 704 | # 705 | # Trace memory 706 | # 707 | # CONFIG_ESP32_TRAX is not set 708 | CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0 709 | # end of Trace memory 710 | 711 | # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set 712 | CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y 713 | # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set 714 | # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set 715 | # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set 716 | 717 | # 718 | # Memory protection 719 | # 720 | # end of Memory protection 721 | 722 | CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 723 | CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 724 | CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 725 | CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y 726 | # CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set 727 | # CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set 728 | CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 729 | CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 730 | CONFIG_ESP_CONSOLE_UART_DEFAULT=y 731 | # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set 732 | # CONFIG_ESP_CONSOLE_NONE is not set 733 | CONFIG_ESP_CONSOLE_UART=y 734 | CONFIG_ESP_CONSOLE_MULTIPLE_UART=y 735 | CONFIG_ESP_CONSOLE_UART_NUM=0 736 | CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 737 | CONFIG_ESP_INT_WDT=y 738 | CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 739 | CONFIG_ESP_INT_WDT_CHECK_CPU1=y 740 | CONFIG_ESP_TASK_WDT=y 741 | # CONFIG_ESP_TASK_WDT_PANIC is not set 742 | CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 743 | CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y 744 | CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y 745 | # CONFIG_ESP_PANIC_HANDLER_IRAM is not set 746 | # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set 747 | CONFIG_ESP_DEBUG_OCDAWARE=y 748 | # CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is not set 749 | CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y 750 | 751 | # 752 | # Brownout Detector 753 | # 754 | CONFIG_ESP_BROWNOUT_DET=y 755 | CONFIG_ESP_BROWNOUT_DET_LVL_SEL_0=y 756 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set 757 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set 758 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set 759 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set 760 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set 761 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set 762 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 is not set 763 | CONFIG_ESP_BROWNOUT_DET_LVL=0 764 | # end of Brownout Detector 765 | 766 | # CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set 767 | CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y 768 | # end of ESP System Settings 769 | 770 | # 771 | # IPC (Inter-Processor Call) 772 | # 773 | CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 774 | CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y 775 | CONFIG_ESP_IPC_ISR_ENABLE=y 776 | # end of IPC (Inter-Processor Call) 777 | 778 | # 779 | # High resolution timer (esp_timer) 780 | # 781 | # CONFIG_ESP_TIMER_PROFILING is not set 782 | CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y 783 | CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y 784 | CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 785 | CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 786 | # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set 787 | CONFIG_ESP_TIMER_IMPL_TG0_LAC=y 788 | # end of High resolution timer (esp_timer) 789 | 790 | # 791 | # Wi-Fi 792 | # 793 | CONFIG_ESP32_WIFI_ENABLED=y 794 | CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 795 | CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 796 | # CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set 797 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y 798 | CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 799 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 800 | # CONFIG_ESP32_WIFI_CSI_ENABLED is not set 801 | CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y 802 | CONFIG_ESP32_WIFI_TX_BA_WIN=6 803 | CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y 804 | CONFIG_ESP32_WIFI_RX_BA_WIN=6 805 | CONFIG_ESP32_WIFI_NVS_ENABLED=y 806 | CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y 807 | # CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set 808 | CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 809 | CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 810 | CONFIG_ESP32_WIFI_IRAM_OPT=y 811 | CONFIG_ESP32_WIFI_RX_IRAM_OPT=y 812 | CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y 813 | CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y 814 | # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set 815 | # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set 816 | # CONFIG_ESP_WIFI_GMAC_SUPPORT is not set 817 | CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y 818 | # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set 819 | # end of Wi-Fi 820 | 821 | # 822 | # Core dump 823 | # 824 | # CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set 825 | # CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set 826 | CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y 827 | # end of Core dump 828 | 829 | # 830 | # FAT Filesystem support 831 | # 832 | CONFIG_FATFS_VOLUME_COUNT=2 833 | # CONFIG_FATFS_SECTOR_512 is not set 834 | # CONFIG_FATFS_SECTOR_1024 is not set 835 | # CONFIG_FATFS_SECTOR_2048 is not set 836 | CONFIG_FATFS_SECTOR_4096=y 837 | CONFIG_FATFS_SECTORS_PER_CLUSTER_1=y 838 | # CONFIG_FATFS_SECTORS_PER_CLUSTER_2 is not set 839 | # CONFIG_FATFS_SECTORS_PER_CLUSTER_4 is not set 840 | # CONFIG_FATFS_SECTORS_PER_CLUSTER_8 is not set 841 | # CONFIG_FATFS_SECTORS_PER_CLUSTER_16 is not set 842 | # CONFIG_FATFS_SECTORS_PER_CLUSTER_32 is not set 843 | # CONFIG_FATFS_SECTORS_PER_CLUSTER_64 is not set 844 | # CONFIG_FATFS_SECTORS_PER_CLUSTER_128 is not set 845 | # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set 846 | CONFIG_FATFS_CODEPAGE_437=y 847 | # CONFIG_FATFS_CODEPAGE_720 is not set 848 | # CONFIG_FATFS_CODEPAGE_737 is not set 849 | # CONFIG_FATFS_CODEPAGE_771 is not set 850 | # CONFIG_FATFS_CODEPAGE_775 is not set 851 | # CONFIG_FATFS_CODEPAGE_850 is not set 852 | # CONFIG_FATFS_CODEPAGE_852 is not set 853 | # CONFIG_FATFS_CODEPAGE_855 is not set 854 | # CONFIG_FATFS_CODEPAGE_857 is not set 855 | # CONFIG_FATFS_CODEPAGE_860 is not set 856 | # CONFIG_FATFS_CODEPAGE_861 is not set 857 | # CONFIG_FATFS_CODEPAGE_862 is not set 858 | # CONFIG_FATFS_CODEPAGE_863 is not set 859 | # CONFIG_FATFS_CODEPAGE_864 is not set 860 | # CONFIG_FATFS_CODEPAGE_865 is not set 861 | # CONFIG_FATFS_CODEPAGE_866 is not set 862 | # CONFIG_FATFS_CODEPAGE_869 is not set 863 | # CONFIG_FATFS_CODEPAGE_932 is not set 864 | # CONFIG_FATFS_CODEPAGE_936 is not set 865 | # CONFIG_FATFS_CODEPAGE_949 is not set 866 | # CONFIG_FATFS_CODEPAGE_950 is not set 867 | CONFIG_FATFS_AUTO_TYPE=y 868 | # CONFIG_FATFS_FAT12 is not set 869 | # CONFIG_FATFS_FAT16 is not set 870 | CONFIG_FATFS_CODEPAGE=437 871 | CONFIG_FATFS_LFN_NONE=y 872 | # CONFIG_FATFS_LFN_HEAP is not set 873 | # CONFIG_FATFS_LFN_STACK is not set 874 | CONFIG_FATFS_FS_LOCK=0 875 | CONFIG_FATFS_TIMEOUT_MS=10000 876 | CONFIG_FATFS_PER_FILE_CACHE=y 877 | # CONFIG_FATFS_USE_FASTSEEK is not set 878 | # end of FAT Filesystem support 879 | 880 | # 881 | # FreeRTOS 882 | # 883 | 884 | # 885 | # Kernel 886 | # 887 | # CONFIG_FREERTOS_SMP is not set 888 | # CONFIG_FREERTOS_UNICORE is not set 889 | CONFIG_FREERTOS_HZ=100 890 | # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set 891 | # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set 892 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y 893 | CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 894 | CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304 895 | # CONFIG_FREERTOS_USE_IDLE_HOOK is not set 896 | # CONFIG_FREERTOS_USE_TICK_HOOK is not set 897 | CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 898 | # CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set 899 | CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 900 | CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 901 | CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 902 | CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 903 | # CONFIG_FREERTOS_USE_TRACE_FACILITY is not set 904 | # CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set 905 | # end of Kernel 906 | 907 | # 908 | # Port 909 | # 910 | CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y 911 | # CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set 912 | # CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set 913 | CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y 914 | CONFIG_FREERTOS_ISR_STACKSIZE=1536 915 | CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y 916 | # CONFIG_FREERTOS_FPU_IN_ISR is not set 917 | CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y 918 | CONFIG_FREERTOS_CORETIMER_0=y 919 | # CONFIG_FREERTOS_CORETIMER_1 is not set 920 | CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y 921 | # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set 922 | # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set 923 | # CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set 924 | CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y 925 | CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y 926 | # end of Port 927 | 928 | CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF 929 | CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y 930 | CONFIG_FREERTOS_DEBUG_OCDAWARE=y 931 | # end of FreeRTOS 932 | 933 | # 934 | # Hardware Abstraction Layer (HAL) and Low Level (LL) 935 | # 936 | CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y 937 | # CONFIG_HAL_ASSERTION_DISABLE is not set 938 | # CONFIG_HAL_ASSERTION_SILENT is not set 939 | # CONFIG_HAL_ASSERTION_ENABLE is not set 940 | CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 941 | # end of Hardware Abstraction Layer (HAL) and Low Level (LL) 942 | 943 | # 944 | # Heap memory debugging 945 | # 946 | CONFIG_HEAP_POISONING_DISABLED=y 947 | # CONFIG_HEAP_POISONING_LIGHT is not set 948 | # CONFIG_HEAP_POISONING_COMPREHENSIVE is not set 949 | CONFIG_HEAP_TRACING_OFF=y 950 | # CONFIG_HEAP_TRACING_STANDALONE is not set 951 | # CONFIG_HEAP_TRACING_TOHOST is not set 952 | # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set 953 | # end of Heap memory debugging 954 | 955 | # 956 | # Log output 957 | # 958 | # CONFIG_LOG_DEFAULT_LEVEL_NONE is not set 959 | # CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set 960 | # CONFIG_LOG_DEFAULT_LEVEL_WARN is not set 961 | CONFIG_LOG_DEFAULT_LEVEL_INFO=y 962 | # CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set 963 | # CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set 964 | CONFIG_LOG_DEFAULT_LEVEL=3 965 | CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y 966 | # CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set 967 | # CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set 968 | CONFIG_LOG_MAXIMUM_LEVEL=3 969 | CONFIG_LOG_COLORS=y 970 | CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y 971 | # CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set 972 | # end of Log output 973 | 974 | # 975 | # LWIP 976 | # 977 | CONFIG_LWIP_LOCAL_HOSTNAME="espressif" 978 | # CONFIG_LWIP_NETIF_API is not set 979 | # CONFIG_LWIP_TCPIP_CORE_LOCKING is not set 980 | CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y 981 | # CONFIG_LWIP_L2_TO_L3_COPY is not set 982 | # CONFIG_LWIP_IRAM_OPTIMIZATION is not set 983 | CONFIG_LWIP_TIMERS_ONDEMAND=y 984 | CONFIG_LWIP_MAX_SOCKETS=10 985 | # CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set 986 | # CONFIG_LWIP_SO_LINGER is not set 987 | CONFIG_LWIP_SO_REUSE=y 988 | CONFIG_LWIP_SO_REUSE_RXTOALL=y 989 | # CONFIG_LWIP_SO_RCVBUF is not set 990 | # CONFIG_LWIP_NETBUF_RECVINFO is not set 991 | CONFIG_LWIP_IP4_FRAG=y 992 | CONFIG_LWIP_IP6_FRAG=y 993 | # CONFIG_LWIP_IP4_REASSEMBLY is not set 994 | # CONFIG_LWIP_IP6_REASSEMBLY is not set 995 | # CONFIG_LWIP_IP_FORWARD is not set 996 | # CONFIG_LWIP_STATS is not set 997 | CONFIG_LWIP_ESP_GRATUITOUS_ARP=y 998 | CONFIG_LWIP_GARP_TMR_INTERVAL=60 999 | CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 1000 | CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y 1001 | # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set 1002 | CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y 1003 | # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set 1004 | CONFIG_LWIP_DHCP_OPTIONS_LEN=68 1005 | CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 1006 | 1007 | # 1008 | # DHCP server 1009 | # 1010 | CONFIG_LWIP_DHCPS=y 1011 | CONFIG_LWIP_DHCPS_LEASE_UNIT=60 1012 | CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 1013 | # end of DHCP server 1014 | 1015 | # CONFIG_LWIP_AUTOIP is not set 1016 | CONFIG_LWIP_IPV6=y 1017 | # CONFIG_LWIP_IPV6_AUTOCONFIG is not set 1018 | CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 1019 | # CONFIG_LWIP_IPV6_FORWARD is not set 1020 | # CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set 1021 | CONFIG_LWIP_NETIF_LOOPBACK=y 1022 | CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 1023 | 1024 | # 1025 | # TCP 1026 | # 1027 | CONFIG_LWIP_MAX_ACTIVE_TCP=16 1028 | CONFIG_LWIP_MAX_LISTENING_TCP=16 1029 | CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y 1030 | CONFIG_LWIP_TCP_MAXRTX=12 1031 | CONFIG_LWIP_TCP_SYNMAXRTX=12 1032 | CONFIG_LWIP_TCP_MSS=1440 1033 | CONFIG_LWIP_TCP_TMR_INTERVAL=250 1034 | CONFIG_LWIP_TCP_MSL=60000 1035 | CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 1036 | CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 1037 | CONFIG_LWIP_TCP_WND_DEFAULT=5744 1038 | CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 1039 | CONFIG_LWIP_TCP_QUEUE_OOSEQ=y 1040 | # CONFIG_LWIP_TCP_SACK_OUT is not set 1041 | CONFIG_LWIP_TCP_OVERSIZE_MSS=y 1042 | # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set 1043 | # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set 1044 | CONFIG_LWIP_TCP_RTO_TIME=1500 1045 | # end of TCP 1046 | 1047 | # 1048 | # UDP 1049 | # 1050 | CONFIG_LWIP_MAX_UDP_PCBS=16 1051 | CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 1052 | # end of UDP 1053 | 1054 | # 1055 | # Checksums 1056 | # 1057 | # CONFIG_LWIP_CHECKSUM_CHECK_IP is not set 1058 | # CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set 1059 | CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y 1060 | # end of Checksums 1061 | 1062 | CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 1063 | CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y 1064 | # CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set 1065 | # CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set 1066 | CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF 1067 | # CONFIG_LWIP_PPP_SUPPORT is not set 1068 | CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 1069 | CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 1070 | # CONFIG_LWIP_SLIP_SUPPORT is not set 1071 | 1072 | # 1073 | # ICMP 1074 | # 1075 | CONFIG_LWIP_ICMP=y 1076 | # CONFIG_LWIP_MULTICAST_PING is not set 1077 | # CONFIG_LWIP_BROADCAST_PING is not set 1078 | # end of ICMP 1079 | 1080 | # 1081 | # LWIP RAW API 1082 | # 1083 | CONFIG_LWIP_MAX_RAW_PCBS=16 1084 | # end of LWIP RAW API 1085 | 1086 | # 1087 | # SNTP 1088 | # 1089 | CONFIG_LWIP_SNTP_MAX_SERVERS=1 1090 | # CONFIG_LWIP_DHCP_GET_NTP_SRV is not set 1091 | CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 1092 | # end of SNTP 1093 | 1094 | CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 1095 | CONFIG_LWIP_ESP_LWIP_ASSERT=y 1096 | 1097 | # 1098 | # Hooks 1099 | # 1100 | # CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set 1101 | CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y 1102 | # CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set 1103 | CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y 1104 | # CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set 1105 | # CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set 1106 | CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y 1107 | # CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set 1108 | # CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set 1109 | CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y 1110 | # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set 1111 | # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set 1112 | CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y 1113 | # CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set 1114 | # CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set 1115 | # end of Hooks 1116 | 1117 | # CONFIG_LWIP_DEBUG is not set 1118 | # end of LWIP 1119 | 1120 | # 1121 | # mbedTLS 1122 | # 1123 | CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y 1124 | # CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set 1125 | # CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set 1126 | CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y 1127 | CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 1128 | CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 1129 | # CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set 1130 | # CONFIG_MBEDTLS_DEBUG is not set 1131 | 1132 | # 1133 | # mbedTLS v3.x related 1134 | # 1135 | # CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set 1136 | # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set 1137 | # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set 1138 | # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set 1139 | CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y 1140 | # end of mbedTLS v3.x related 1141 | 1142 | # 1143 | # Certificate Bundle 1144 | # 1145 | # CONFIG_MBEDTLS_CERTIFICATE_BUNDLE is not set 1146 | # end of Certificate Bundle 1147 | 1148 | # CONFIG_MBEDTLS_ECP_RESTARTABLE is not set 1149 | # CONFIG_MBEDTLS_CMAC_C is not set 1150 | CONFIG_MBEDTLS_HARDWARE_AES=y 1151 | CONFIG_MBEDTLS_HARDWARE_MPI=y 1152 | CONFIG_MBEDTLS_HARDWARE_SHA=y 1153 | CONFIG_MBEDTLS_ROM_MD5=y 1154 | # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set 1155 | # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set 1156 | CONFIG_MBEDTLS_HAVE_TIME=y 1157 | # CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set 1158 | # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set 1159 | CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y 1160 | CONFIG_MBEDTLS_SHA512_C=y 1161 | CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y 1162 | # CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set 1163 | # CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set 1164 | # CONFIG_MBEDTLS_TLS_DISABLED is not set 1165 | CONFIG_MBEDTLS_TLS_SERVER=y 1166 | CONFIG_MBEDTLS_TLS_CLIENT=y 1167 | CONFIG_MBEDTLS_TLS_ENABLED=y 1168 | 1169 | # 1170 | # TLS Key Exchange Methods 1171 | # 1172 | # CONFIG_MBEDTLS_PSK_MODES is not set 1173 | CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y 1174 | CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y 1175 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y 1176 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y 1177 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y 1178 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y 1179 | # end of TLS Key Exchange Methods 1180 | 1181 | CONFIG_MBEDTLS_SSL_RENEGOTIATION=y 1182 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y 1183 | # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set 1184 | # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set 1185 | CONFIG_MBEDTLS_SSL_ALPN=y 1186 | CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y 1187 | CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y 1188 | 1189 | # 1190 | # Symmetric Ciphers 1191 | # 1192 | CONFIG_MBEDTLS_AES_C=y 1193 | # CONFIG_MBEDTLS_CAMELLIA_C is not set 1194 | # CONFIG_MBEDTLS_DES_C is not set 1195 | # CONFIG_MBEDTLS_BLOWFISH_C is not set 1196 | # CONFIG_MBEDTLS_XTEA_C is not set 1197 | CONFIG_MBEDTLS_CCM_C=y 1198 | CONFIG_MBEDTLS_GCM_C=y 1199 | # CONFIG_MBEDTLS_NIST_KW_C is not set 1200 | # end of Symmetric Ciphers 1201 | 1202 | # CONFIG_MBEDTLS_RIPEMD160_C is not set 1203 | 1204 | # 1205 | # Certificates 1206 | # 1207 | CONFIG_MBEDTLS_PEM_PARSE_C=y 1208 | CONFIG_MBEDTLS_PEM_WRITE_C=y 1209 | CONFIG_MBEDTLS_X509_CRL_PARSE_C=y 1210 | CONFIG_MBEDTLS_X509_CSR_PARSE_C=y 1211 | # end of Certificates 1212 | 1213 | CONFIG_MBEDTLS_ECP_C=y 1214 | # CONFIG_MBEDTLS_DHM_C is not set 1215 | CONFIG_MBEDTLS_ECDH_C=y 1216 | CONFIG_MBEDTLS_ECDSA_C=y 1217 | # CONFIG_MBEDTLS_ECJPAKE_C is not set 1218 | CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y 1219 | CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y 1220 | CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y 1221 | CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y 1222 | CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y 1223 | CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y 1224 | CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y 1225 | CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y 1226 | CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y 1227 | CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y 1228 | CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y 1229 | CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y 1230 | CONFIG_MBEDTLS_ECP_NIST_OPTIM=y 1231 | # CONFIG_MBEDTLS_POLY1305_C is not set 1232 | # CONFIG_MBEDTLS_CHACHA20_C is not set 1233 | # CONFIG_MBEDTLS_HKDF_C is not set 1234 | # CONFIG_MBEDTLS_THREADING_C is not set 1235 | # CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set 1236 | # CONFIG_MBEDTLS_SECURITY_RISKS is not set 1237 | # end of mbedTLS 1238 | 1239 | # 1240 | # ESP-MQTT Configurations 1241 | # 1242 | CONFIG_MQTT_PROTOCOL_311=y 1243 | # CONFIG_MQTT_PROTOCOL_5 is not set 1244 | CONFIG_MQTT_TRANSPORT_SSL=y 1245 | CONFIG_MQTT_TRANSPORT_WEBSOCKET=y 1246 | CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y 1247 | # CONFIG_MQTT_MSG_ID_INCREMENTAL is not set 1248 | # CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set 1249 | # CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set 1250 | # CONFIG_MQTT_USE_CUSTOM_CONFIG is not set 1251 | # CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set 1252 | # CONFIG_MQTT_CUSTOM_OUTBOX is not set 1253 | # end of ESP-MQTT Configurations 1254 | 1255 | # 1256 | # Newlib 1257 | # 1258 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y 1259 | # CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set 1260 | # CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set 1261 | # CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set 1262 | # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set 1263 | CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y 1264 | # CONFIG_NEWLIB_NANO_FORMAT is not set 1265 | CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y 1266 | # CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set 1267 | # CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set 1268 | # CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set 1269 | # end of Newlib 1270 | 1271 | # 1272 | # NVS 1273 | # 1274 | # CONFIG_NVS_ASSERT_ERROR_CHECK is not set 1275 | # end of NVS 1276 | 1277 | # 1278 | # OpenThread 1279 | # 1280 | # CONFIG_OPENTHREAD_ENABLED is not set 1281 | # end of OpenThread 1282 | 1283 | # 1284 | # Protocomm 1285 | # 1286 | CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y 1287 | CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y 1288 | CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y 1289 | # end of Protocomm 1290 | 1291 | # 1292 | # PThreads 1293 | # 1294 | CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 1295 | CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 1296 | CONFIG_PTHREAD_STACK_MIN=768 1297 | CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y 1298 | # CONFIG_PTHREAD_DEFAULT_CORE_0 is not set 1299 | # CONFIG_PTHREAD_DEFAULT_CORE_1 is not set 1300 | CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 1301 | CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" 1302 | # end of PThreads 1303 | 1304 | # 1305 | # SPI Flash driver 1306 | # 1307 | # CONFIG_SPI_FLASH_VERIFY_WRITE is not set 1308 | # CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set 1309 | CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y 1310 | CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y 1311 | # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set 1312 | # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set 1313 | # CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set 1314 | # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set 1315 | CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y 1316 | CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 1317 | CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 1318 | CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 1319 | # CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set 1320 | # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set 1321 | # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set 1322 | 1323 | # 1324 | # SPI Flash behavior when brownout 1325 | # 1326 | CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y 1327 | CONFIG_SPI_FLASH_BROWNOUT_RESET=y 1328 | # end of SPI Flash behavior when brownout 1329 | 1330 | # 1331 | # Auto-detect flash chips 1332 | # 1333 | CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y 1334 | CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y 1335 | CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y 1336 | CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y 1337 | # CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP is not set 1338 | # CONFIG_SPI_FLASH_SUPPORT_TH_CHIP is not set 1339 | # end of Auto-detect flash chips 1340 | 1341 | CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y 1342 | # end of SPI Flash driver 1343 | 1344 | # 1345 | # SPIFFS Configuration 1346 | # 1347 | CONFIG_SPIFFS_MAX_PARTITIONS=3 1348 | 1349 | # 1350 | # SPIFFS Cache Configuration 1351 | # 1352 | CONFIG_SPIFFS_CACHE=y 1353 | CONFIG_SPIFFS_CACHE_WR=y 1354 | # CONFIG_SPIFFS_CACHE_STATS is not set 1355 | # end of SPIFFS Cache Configuration 1356 | 1357 | CONFIG_SPIFFS_PAGE_CHECK=y 1358 | CONFIG_SPIFFS_GC_MAX_RUNS=10 1359 | # CONFIG_SPIFFS_GC_STATS is not set 1360 | CONFIG_SPIFFS_PAGE_SIZE=256 1361 | CONFIG_SPIFFS_OBJ_NAME_LEN=32 1362 | # CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set 1363 | CONFIG_SPIFFS_USE_MAGIC=y 1364 | CONFIG_SPIFFS_USE_MAGIC_LENGTH=y 1365 | CONFIG_SPIFFS_META_LENGTH=4 1366 | CONFIG_SPIFFS_USE_MTIME=y 1367 | 1368 | # 1369 | # Debug Configuration 1370 | # 1371 | # CONFIG_SPIFFS_DBG is not set 1372 | # CONFIG_SPIFFS_API_DBG is not set 1373 | # CONFIG_SPIFFS_GC_DBG is not set 1374 | # CONFIG_SPIFFS_CACHE_DBG is not set 1375 | # CONFIG_SPIFFS_CHECK_DBG is not set 1376 | # CONFIG_SPIFFS_TEST_VISUALISATION is not set 1377 | # end of Debug Configuration 1378 | # end of SPIFFS Configuration 1379 | 1380 | # 1381 | # TCP Transport 1382 | # 1383 | 1384 | # 1385 | # Websocket 1386 | # 1387 | CONFIG_WS_TRANSPORT=y 1388 | CONFIG_WS_BUFFER_SIZE=1024 1389 | # CONFIG_WS_DYNAMIC_BUFFER is not set 1390 | # end of Websocket 1391 | # end of TCP Transport 1392 | 1393 | # 1394 | # Ultra Low Power (ULP) Co-processor 1395 | # 1396 | # CONFIG_ULP_COPROC_ENABLED is not set 1397 | # end of Ultra Low Power (ULP) Co-processor 1398 | 1399 | # 1400 | # Unity unit testing library 1401 | # 1402 | CONFIG_UNITY_ENABLE_FLOAT=y 1403 | CONFIG_UNITY_ENABLE_DOUBLE=y 1404 | # CONFIG_UNITY_ENABLE_64BIT is not set 1405 | # CONFIG_UNITY_ENABLE_COLOR is not set 1406 | CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y 1407 | # CONFIG_UNITY_ENABLE_FIXTURE is not set 1408 | # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set 1409 | # end of Unity unit testing library 1410 | 1411 | # 1412 | # Virtual file system 1413 | # 1414 | CONFIG_VFS_SUPPORT_IO=y 1415 | CONFIG_VFS_SUPPORT_DIR=y 1416 | CONFIG_VFS_SUPPORT_SELECT=y 1417 | CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y 1418 | CONFIG_VFS_SUPPORT_TERMIOS=y 1419 | 1420 | # 1421 | # Host File System I/O (Semihosting) 1422 | # 1423 | CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 1424 | # end of Host File System I/O (Semihosting) 1425 | # end of Virtual file system 1426 | 1427 | # 1428 | # Wear Levelling 1429 | # 1430 | # CONFIG_WL_SECTOR_SIZE_512 is not set 1431 | CONFIG_WL_SECTOR_SIZE_4096=y 1432 | CONFIG_WL_SECTOR_SIZE=4096 1433 | # end of Wear Levelling 1434 | 1435 | # 1436 | # Wi-Fi Provisioning Manager 1437 | # 1438 | CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 1439 | CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 1440 | CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y 1441 | # end of Wi-Fi Provisioning Manager 1442 | 1443 | # 1444 | # Supplicant 1445 | # 1446 | CONFIG_WPA_MBEDTLS_CRYPTO=y 1447 | CONFIG_WPA_MBEDTLS_TLS_CLIENT=y 1448 | # CONFIG_WPA_WAPI_PSK is not set 1449 | # CONFIG_WPA_SUITE_B_192 is not set 1450 | # CONFIG_WPA_DEBUG_PRINT is not set 1451 | # CONFIG_WPA_TESTING_OPTIONS is not set 1452 | # CONFIG_WPA_WPS_STRICT is not set 1453 | # CONFIG_WPA_11KV_SUPPORT is not set 1454 | # CONFIG_WPA_MBO_SUPPORT is not set 1455 | # CONFIG_WPA_DPP_SUPPORT is not set 1456 | # CONFIG_WPA_11R_SUPPORT is not set 1457 | # CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set 1458 | # end of Supplicant 1459 | # end of Component config 1460 | 1461 | # Deprecated options for backward compatibility 1462 | # CONFIG_NO_BLOBS is not set 1463 | # CONFIG_ESP32_NO_BLOBS is not set 1464 | # CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set 1465 | # CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set 1466 | # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set 1467 | # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set 1468 | # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set 1469 | CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y 1470 | # CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set 1471 | # CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set 1472 | CONFIG_LOG_BOOTLOADER_LEVEL=3 1473 | # CONFIG_APP_ROLLBACK_ENABLE is not set 1474 | # CONFIG_FLASH_ENCRYPTION_ENABLED is not set 1475 | # CONFIG_FLASHMODE_QIO is not set 1476 | # CONFIG_FLASHMODE_QOUT is not set 1477 | CONFIG_FLASHMODE_DIO=y 1478 | # CONFIG_FLASHMODE_DOUT is not set 1479 | CONFIG_MONITOR_BAUD=115200 1480 | CONFIG_OPTIMIZATION_LEVEL_DEBUG=y 1481 | CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y 1482 | # CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set 1483 | # CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set 1484 | CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y 1485 | # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set 1486 | # CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set 1487 | CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 1488 | # CONFIG_CXX_EXCEPTIONS is not set 1489 | CONFIG_STACK_CHECK_NONE=y 1490 | # CONFIG_STACK_CHECK_NORM is not set 1491 | # CONFIG_STACK_CHECK_STRONG is not set 1492 | # CONFIG_STACK_CHECK_ALL is not set 1493 | # CONFIG_WARN_WRITE_STRINGS is not set 1494 | # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set 1495 | CONFIG_ESP32_APPTRACE_DEST_NONE=y 1496 | CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y 1497 | CONFIG_ADC2_DISABLE_DAC=y 1498 | # CONFIG_MCPWM_ISR_IN_IRAM is not set 1499 | # CONFIG_EVENT_LOOP_PROFILING is not set 1500 | CONFIG_POST_EVENTS_FROM_ISR=y 1501 | CONFIG_POST_EVENTS_FROM_IRAM_ISR=y 1502 | # CONFIG_OTA_ALLOW_HTTP is not set 1503 | # CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set 1504 | CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y 1505 | CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 1506 | CONFIG_ESP_SYSTEM_PD_FLASH=y 1507 | CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 1508 | CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y 1509 | CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y 1510 | # CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set 1511 | # CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set 1512 | # CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set 1513 | # CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set 1514 | # CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set 1515 | # CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set 1516 | CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 1517 | # CONFIG_ESP32_XTAL_FREQ_26 is not set 1518 | CONFIG_ESP32_XTAL_FREQ_40=y 1519 | # CONFIG_ESP32_XTAL_FREQ_AUTO is not set 1520 | CONFIG_ESP32_XTAL_FREQ=40 1521 | CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y 1522 | # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set 1523 | CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 1524 | CONFIG_ESP32_PHY_MAX_TX_POWER=20 1525 | CONFIG_REDUCE_PHY_TX_POWER=y 1526 | CONFIG_ESP32_REDUCE_PHY_TX_POWER=y 1527 | # CONFIG_SPIRAM_SUPPORT is not set 1528 | # CONFIG_ESP32_SPIRAM_SUPPORT is not set 1529 | # CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set 1530 | # CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set 1531 | CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y 1532 | CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 1533 | CONFIG_TRACEMEM_RESERVE_DRAM=0x0 1534 | # CONFIG_ESP32_PANIC_PRINT_HALT is not set 1535 | CONFIG_ESP32_PANIC_PRINT_REBOOT=y 1536 | # CONFIG_ESP32_PANIC_SILENT_REBOOT is not set 1537 | # CONFIG_ESP32_PANIC_GDBSTUB is not set 1538 | CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 1539 | CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 1540 | CONFIG_MAIN_TASK_STACK_SIZE=3584 1541 | CONFIG_CONSOLE_UART_DEFAULT=y 1542 | # CONFIG_CONSOLE_UART_CUSTOM is not set 1543 | # CONFIG_CONSOLE_UART_NONE is not set 1544 | # CONFIG_ESP_CONSOLE_UART_NONE is not set 1545 | CONFIG_CONSOLE_UART=y 1546 | CONFIG_CONSOLE_UART_NUM=0 1547 | CONFIG_CONSOLE_UART_BAUDRATE=115200 1548 | CONFIG_INT_WDT=y 1549 | CONFIG_INT_WDT_TIMEOUT_MS=300 1550 | CONFIG_INT_WDT_CHECK_CPU1=y 1551 | CONFIG_TASK_WDT=y 1552 | # CONFIG_TASK_WDT_PANIC is not set 1553 | CONFIG_TASK_WDT_TIMEOUT_S=5 1554 | CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y 1555 | CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y 1556 | # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set 1557 | CONFIG_ESP32_DEBUG_OCDAWARE=y 1558 | CONFIG_BROWNOUT_DET=y 1559 | CONFIG_ESP32_BROWNOUT_DET=y 1560 | CONFIG_BROWNOUT_DET_LVL_SEL_0=y 1561 | CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0=y 1562 | # CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set 1563 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1 is not set 1564 | # CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set 1565 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2 is not set 1566 | # CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set 1567 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3 is not set 1568 | # CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set 1569 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4 is not set 1570 | # CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set 1571 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 is not set 1572 | # CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set 1573 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 is not set 1574 | # CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set 1575 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 is not set 1576 | CONFIG_BROWNOUT_DET_LVL=0 1577 | CONFIG_ESP32_BROWNOUT_DET_LVL=0 1578 | # CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set 1579 | CONFIG_IPC_TASK_STACK_SIZE=1024 1580 | CONFIG_TIMER_TASK_STACK_SIZE=3584 1581 | # CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set 1582 | # CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set 1583 | CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y 1584 | CONFIG_TIMER_TASK_PRIORITY=1 1585 | CONFIG_TIMER_TASK_STACK_DEPTH=2048 1586 | CONFIG_TIMER_QUEUE_LENGTH=10 1587 | # CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set 1588 | # CONFIG_HAL_ASSERTION_SILIENT is not set 1589 | # CONFIG_L2_TO_L3_COPY is not set 1590 | CONFIG_ESP_GRATUITOUS_ARP=y 1591 | CONFIG_GARP_TMR_INTERVAL=60 1592 | CONFIG_TCPIP_RECVMBOX_SIZE=32 1593 | CONFIG_TCP_MAXRTX=12 1594 | CONFIG_TCP_SYNMAXRTX=12 1595 | CONFIG_TCP_MSS=1440 1596 | CONFIG_TCP_MSL=60000 1597 | CONFIG_TCP_SND_BUF_DEFAULT=5744 1598 | CONFIG_TCP_WND_DEFAULT=5744 1599 | CONFIG_TCP_RECVMBOX_SIZE=6 1600 | CONFIG_TCP_QUEUE_OOSEQ=y 1601 | CONFIG_TCP_OVERSIZE_MSS=y 1602 | # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set 1603 | # CONFIG_TCP_OVERSIZE_DISABLE is not set 1604 | CONFIG_UDP_RECVMBOX_SIZE=6 1605 | CONFIG_TCPIP_TASK_STACK_SIZE=3072 1606 | CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y 1607 | # CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set 1608 | # CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set 1609 | CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF 1610 | # CONFIG_PPP_SUPPORT is not set 1611 | CONFIG_ESP32_TIME_SYSCALL_USE_RTC_HRT=y 1612 | CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y 1613 | # CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set 1614 | # CONFIG_ESP32_TIME_SYSCALL_USE_HRT is not set 1615 | # CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set 1616 | # CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set 1617 | CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 1618 | CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 1619 | CONFIG_ESP32_PTHREAD_STACK_MIN=768 1620 | CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y 1621 | # CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set 1622 | # CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set 1623 | CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 1624 | CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" 1625 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y 1626 | # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set 1627 | # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set 1628 | # CONFIG_ESP32_ULP_COPROC_ENABLED is not set 1629 | CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y 1630 | CONFIG_SUPPORT_TERMIOS=y 1631 | CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 1632 | # End of deprecated options 1633 | -------------------------------------------------------------------------------- /sdkconfig.esp32dev.old: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file. DO NOT EDIT. 3 | # Espressif IoT Development Framework (ESP-IDF) Project Configuration 4 | # 5 | CONFIG_IDF_CMAKE=y 6 | CONFIG_IDF_TARGET_ARCH_XTENSA=y 7 | CONFIG_IDF_TARGET="esp32" 8 | CONFIG_IDF_TARGET_ESP32=y 9 | CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000 10 | 11 | # 12 | # SDK tool configuration 13 | # 14 | CONFIG_SDK_TOOLPREFIX="xtensa-esp32-elf-" 15 | # CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set 16 | # end of SDK tool configuration 17 | 18 | # 19 | # Build type 20 | # 21 | CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y 22 | # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set 23 | CONFIG_APP_BUILD_GENERATE_BINARIES=y 24 | CONFIG_APP_BUILD_BOOTLOADER=y 25 | CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y 26 | # end of Build type 27 | 28 | # 29 | # Application manager 30 | # 31 | CONFIG_APP_COMPILE_TIME_DATE=y 32 | # CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set 33 | # CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set 34 | # CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set 35 | CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 36 | # end of Application manager 37 | 38 | # 39 | # Bootloader config 40 | # 41 | CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 42 | CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y 43 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set 44 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set 45 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set 46 | # CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set 47 | # CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set 48 | # CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set 49 | CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y 50 | # CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set 51 | # CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set 52 | CONFIG_BOOTLOADER_LOG_LEVEL=3 53 | # CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set 54 | CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y 55 | # CONFIG_BOOTLOADER_FACTORY_RESET is not set 56 | # CONFIG_BOOTLOADER_APP_TEST is not set 57 | CONFIG_BOOTLOADER_WDT_ENABLE=y 58 | # CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set 59 | CONFIG_BOOTLOADER_WDT_TIME_MS=9000 60 | # CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set 61 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set 62 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set 63 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set 64 | CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 65 | # CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set 66 | # end of Bootloader config 67 | 68 | # 69 | # Security features 70 | # 71 | # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set 72 | # CONFIG_SECURE_BOOT is not set 73 | # CONFIG_SECURE_FLASH_ENC_ENABLED is not set 74 | # end of Security features 75 | 76 | # 77 | # Serial flasher config 78 | # 79 | CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 80 | # CONFIG_ESPTOOLPY_NO_STUB is not set 81 | # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set 82 | # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set 83 | CONFIG_ESPTOOLPY_FLASHMODE_DIO=y 84 | # CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set 85 | CONFIG_ESPTOOLPY_FLASHMODE="dio" 86 | # CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set 87 | CONFIG_ESPTOOLPY_FLASHFREQ_40M=y 88 | # CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set 89 | # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set 90 | CONFIG_ESPTOOLPY_FLASHFREQ="40m" 91 | # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set 92 | CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y 93 | # CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set 94 | # CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set 95 | # CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set 96 | CONFIG_ESPTOOLPY_FLASHSIZE="2MB" 97 | CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y 98 | CONFIG_ESPTOOLPY_BEFORE_RESET=y 99 | # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set 100 | CONFIG_ESPTOOLPY_BEFORE="default_reset" 101 | CONFIG_ESPTOOLPY_AFTER_RESET=y 102 | # CONFIG_ESPTOOLPY_AFTER_NORESET is not set 103 | CONFIG_ESPTOOLPY_AFTER="hard_reset" 104 | # CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set 105 | # CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set 106 | # CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set 107 | CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y 108 | # CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set 109 | # CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set 110 | # CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set 111 | # CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set 112 | CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 113 | CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 114 | # end of Serial flasher config 115 | 116 | # 117 | # Partition Table 118 | # 119 | CONFIG_PARTITION_TABLE_SINGLE_APP=y 120 | # CONFIG_PARTITION_TABLE_TWO_OTA is not set 121 | # CONFIG_PARTITION_TABLE_CUSTOM is not set 122 | CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" 123 | CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" 124 | CONFIG_PARTITION_TABLE_OFFSET=0x8000 125 | CONFIG_PARTITION_TABLE_MD5=y 126 | # end of Partition Table 127 | 128 | # 129 | # Compiler options 130 | # 131 | CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y 132 | # CONFIG_COMPILER_OPTIMIZATION_SIZE is not set 133 | # CONFIG_COMPILER_OPTIMIZATION_PERF is not set 134 | # CONFIG_COMPILER_OPTIMIZATION_NONE is not set 135 | CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y 136 | # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set 137 | # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set 138 | # CONFIG_COMPILER_CXX_EXCEPTIONS is not set 139 | # CONFIG_COMPILER_CXX_RTTI is not set 140 | CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y 141 | # CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set 142 | # CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set 143 | # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set 144 | # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set 145 | # CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set 146 | # CONFIG_COMPILER_DUMP_RTL_FILES is not set 147 | # end of Compiler options 148 | 149 | # 150 | # Component config 151 | # 152 | 153 | # 154 | # Application Level Tracing 155 | # 156 | # CONFIG_APPTRACE_DEST_TRAX is not set 157 | CONFIG_APPTRACE_DEST_NONE=y 158 | CONFIG_APPTRACE_LOCK_ENABLE=y 159 | # end of Application Level Tracing 160 | 161 | # 162 | # ESP-ASIO 163 | # 164 | # CONFIG_ASIO_SSL_SUPPORT is not set 165 | # end of ESP-ASIO 166 | 167 | # 168 | # Bluetooth 169 | # 170 | # CONFIG_BT_ENABLED is not set 171 | CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 172 | CONFIG_BTDM_CTRL_PCM_ROLE_EFF=0 173 | CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0 174 | CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 175 | CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 176 | CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 177 | CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 178 | CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF=1 179 | CONFIG_BT_CTRL_MODE_EFF=1 180 | CONFIG_BT_CTRL_BLE_MAX_ACT=10 181 | CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=10 182 | CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB=0 183 | CONFIG_BT_CTRL_PINNED_TO_CORE=0 184 | CONFIG_BT_CTRL_HCI_TL=1 185 | CONFIG_BT_CTRL_ADV_DUP_FILT_MAX=30 186 | CONFIG_BT_CTRL_HW_CCA_EFF=0 187 | CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF=0 188 | CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP=y 189 | CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM=100 190 | CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD=20 191 | CONFIG_BT_CTRL_BLE_SCAN_DUPL=y 192 | CONFIG_BT_CTRL_SCAN_DUPL_TYPE=0 193 | CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE=100 194 | CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF=0 195 | CONFIG_BT_CTRL_SLEEP_MODE_EFF=0 196 | CONFIG_BT_CTRL_SLEEP_CLOCK_EFF=0 197 | CONFIG_BT_CTRL_HCI_TL_EFF=1 198 | CONFIG_BT_RESERVE_DRAM=0 199 | # end of Bluetooth 200 | 201 | # 202 | # CoAP Configuration 203 | # 204 | CONFIG_COAP_MBEDTLS_PSK=y 205 | # CONFIG_COAP_MBEDTLS_PKI is not set 206 | # CONFIG_COAP_MBEDTLS_DEBUG is not set 207 | CONFIG_COAP_LOG_DEFAULT_LEVEL=0 208 | # end of CoAP Configuration 209 | 210 | # 211 | # Driver configurations 212 | # 213 | 214 | # 215 | # ADC configuration 216 | # 217 | # CONFIG_ADC_FORCE_XPD_FSM is not set 218 | CONFIG_ADC_DISABLE_DAC=y 219 | # end of ADC configuration 220 | 221 | # 222 | # SPI configuration 223 | # 224 | # CONFIG_SPI_MASTER_IN_IRAM is not set 225 | CONFIG_SPI_MASTER_ISR_IN_IRAM=y 226 | # CONFIG_SPI_SLAVE_IN_IRAM is not set 227 | CONFIG_SPI_SLAVE_ISR_IN_IRAM=y 228 | # end of SPI configuration 229 | 230 | # 231 | # TWAI configuration 232 | # 233 | # CONFIG_TWAI_ISR_IN_IRAM is not set 234 | # CONFIG_TWAI_ERRATA_FIX_BUS_OFF_REC is not set 235 | # CONFIG_TWAI_ERRATA_FIX_TX_INTR_LOST is not set 236 | # CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID is not set 237 | # CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT is not set 238 | # end of TWAI configuration 239 | 240 | # 241 | # UART configuration 242 | # 243 | # CONFIG_UART_ISR_IN_IRAM is not set 244 | # end of UART configuration 245 | 246 | # 247 | # RTCIO configuration 248 | # 249 | # CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC is not set 250 | # end of RTCIO configuration 251 | 252 | # 253 | # GPIO Configuration 254 | # 255 | # CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL is not set 256 | # end of GPIO Configuration 257 | # end of Driver configurations 258 | 259 | # 260 | # eFuse Bit Manager 261 | # 262 | # CONFIG_EFUSE_CUSTOM_TABLE is not set 263 | # CONFIG_EFUSE_VIRTUAL is not set 264 | # CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set 265 | CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y 266 | # CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set 267 | CONFIG_EFUSE_MAX_BLK_LEN=192 268 | # end of eFuse Bit Manager 269 | 270 | # 271 | # ESP-TLS 272 | # 273 | CONFIG_ESP_TLS_USING_MBEDTLS=y 274 | # CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set 275 | # CONFIG_ESP_TLS_SERVER is not set 276 | # CONFIG_ESP_TLS_PSK_VERIFICATION is not set 277 | # CONFIG_ESP_TLS_INSECURE is not set 278 | # end of ESP-TLS 279 | 280 | # 281 | # ESP32-specific 282 | # 283 | CONFIG_ESP32_REV_MIN_0=y 284 | # CONFIG_ESP32_REV_MIN_1 is not set 285 | # CONFIG_ESP32_REV_MIN_2 is not set 286 | # CONFIG_ESP32_REV_MIN_3 is not set 287 | CONFIG_ESP32_REV_MIN=0 288 | CONFIG_ESP32_DPORT_WORKAROUND=y 289 | # CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set 290 | # CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set 291 | CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y 292 | CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 293 | # CONFIG_ESP32_SPIRAM_SUPPORT is not set 294 | # CONFIG_ESP32_TRAX is not set 295 | CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0 296 | # CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set 297 | CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR=y 298 | CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES=4 299 | # CONFIG_ESP32_ULP_COPROC_ENABLED is not set 300 | CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 301 | CONFIG_ESP32_DEBUG_OCDAWARE=y 302 | CONFIG_ESP32_BROWNOUT_DET=y 303 | CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0=y 304 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1 is not set 305 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2 is not set 306 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3 is not set 307 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4 is not set 308 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 is not set 309 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 is not set 310 | # CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 is not set 311 | CONFIG_ESP32_BROWNOUT_DET_LVL=0 312 | CONFIG_ESP32_REDUCE_PHY_TX_POWER=y 313 | CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y 314 | # CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set 315 | # CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set 316 | # CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set 317 | CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y 318 | # CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set 319 | # CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set 320 | # CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set 321 | CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 322 | CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 323 | CONFIG_ESP32_XTAL_FREQ_40=y 324 | # CONFIG_ESP32_XTAL_FREQ_26 is not set 325 | # CONFIG_ESP32_XTAL_FREQ_AUTO is not set 326 | CONFIG_ESP32_XTAL_FREQ=40 327 | # CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set 328 | # CONFIG_ESP32_NO_BLOBS is not set 329 | # CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set 330 | # CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set 331 | CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5 332 | # end of ESP32-specific 333 | 334 | # 335 | # ADC-Calibration 336 | # 337 | CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y 338 | CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y 339 | CONFIG_ADC_CAL_LUT_ENABLE=y 340 | # end of ADC-Calibration 341 | 342 | # 343 | # Common ESP-related 344 | # 345 | CONFIG_ESP_ERR_TO_NAME_LOOKUP=y 346 | CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 347 | CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 348 | CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 349 | CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 350 | CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y 351 | CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 352 | CONFIG_ESP_CONSOLE_UART_DEFAULT=y 353 | # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set 354 | # CONFIG_ESP_CONSOLE_NONE is not set 355 | CONFIG_ESP_CONSOLE_UART=y 356 | CONFIG_ESP_CONSOLE_MULTIPLE_UART=y 357 | CONFIG_ESP_CONSOLE_UART_NUM=0 358 | CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 359 | CONFIG_ESP_INT_WDT=y 360 | CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 361 | CONFIG_ESP_INT_WDT_CHECK_CPU1=y 362 | CONFIG_ESP_TASK_WDT=y 363 | # CONFIG_ESP_TASK_WDT_PANIC is not set 364 | CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 365 | CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y 366 | CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y 367 | # CONFIG_ESP_PANIC_HANDLER_IRAM is not set 368 | CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y 369 | CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y 370 | CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y 371 | CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y 372 | # end of Common ESP-related 373 | 374 | # 375 | # Ethernet 376 | # 377 | CONFIG_ETH_ENABLED=y 378 | CONFIG_ETH_USE_ESP32_EMAC=y 379 | CONFIG_ETH_PHY_INTERFACE_RMII=y 380 | # CONFIG_ETH_PHY_INTERFACE_MII is not set 381 | CONFIG_ETH_RMII_CLK_INPUT=y 382 | # CONFIG_ETH_RMII_CLK_OUTPUT is not set 383 | CONFIG_ETH_RMII_CLK_IN_GPIO=0 384 | CONFIG_ETH_DMA_BUFFER_SIZE=512 385 | CONFIG_ETH_DMA_RX_BUFFER_NUM=10 386 | CONFIG_ETH_DMA_TX_BUFFER_NUM=10 387 | CONFIG_ETH_USE_SPI_ETHERNET=y 388 | # CONFIG_ETH_SPI_ETHERNET_DM9051 is not set 389 | # CONFIG_ETH_SPI_ETHERNET_W5500 is not set 390 | # CONFIG_ETH_USE_OPENETH is not set 391 | # end of Ethernet 392 | 393 | # 394 | # Event Loop Library 395 | # 396 | # CONFIG_ESP_EVENT_LOOP_PROFILING is not set 397 | CONFIG_ESP_EVENT_POST_FROM_ISR=y 398 | CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y 399 | # end of Event Loop Library 400 | 401 | # 402 | # GDB Stub 403 | # 404 | # end of GDB Stub 405 | 406 | # 407 | # ESP HTTP client 408 | # 409 | CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y 410 | # CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set 411 | # end of ESP HTTP client 412 | 413 | # 414 | # HTTP Server 415 | # 416 | CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 417 | CONFIG_HTTPD_MAX_URI_LEN=512 418 | CONFIG_HTTPD_ERR_RESP_NO_DELAY=y 419 | CONFIG_HTTPD_PURGE_BUF_LEN=32 420 | # CONFIG_HTTPD_LOG_PURGE_DATA is not set 421 | # CONFIG_HTTPD_WS_SUPPORT is not set 422 | # end of HTTP Server 423 | 424 | # 425 | # ESP HTTPS OTA 426 | # 427 | # CONFIG_OTA_ALLOW_HTTP is not set 428 | # end of ESP HTTPS OTA 429 | 430 | # 431 | # ESP HTTPS server 432 | # 433 | # CONFIG_ESP_HTTPS_SERVER_ENABLE is not set 434 | # end of ESP HTTPS server 435 | 436 | # 437 | # ESP NETIF Adapter 438 | # 439 | CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 440 | CONFIG_ESP_NETIF_TCPIP_LWIP=y 441 | # CONFIG_ESP_NETIF_LOOPBACK is not set 442 | CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y 443 | # end of ESP NETIF Adapter 444 | 445 | # 446 | # Power Management 447 | # 448 | # CONFIG_PM_ENABLE is not set 449 | # end of Power Management 450 | 451 | # 452 | # ESP System Settings 453 | # 454 | # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set 455 | CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y 456 | # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set 457 | # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set 458 | CONFIG_ESP_SYSTEM_PD_FLASH=y 459 | 460 | # 461 | # Memory protection 462 | # 463 | # end of Memory protection 464 | # end of ESP System Settings 465 | 466 | # 467 | # High resolution timer (esp_timer) 468 | # 469 | # CONFIG_ESP_TIMER_PROFILING is not set 470 | CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y 471 | CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y 472 | CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 473 | # CONFIG_ESP_TIMER_IMPL_FRC2 is not set 474 | CONFIG_ESP_TIMER_IMPL_TG0_LAC=y 475 | # end of High resolution timer (esp_timer) 476 | 477 | # 478 | # Wi-Fi 479 | # 480 | CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 481 | CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 482 | # CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set 483 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y 484 | CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 485 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 486 | # CONFIG_ESP32_WIFI_CSI_ENABLED is not set 487 | CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y 488 | CONFIG_ESP32_WIFI_TX_BA_WIN=6 489 | CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y 490 | CONFIG_ESP32_WIFI_RX_BA_WIN=6 491 | CONFIG_ESP32_WIFI_NVS_ENABLED=y 492 | CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y 493 | # CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set 494 | CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 495 | CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 496 | # CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE is not set 497 | CONFIG_ESP32_WIFI_IRAM_OPT=y 498 | CONFIG_ESP32_WIFI_RX_IRAM_OPT=y 499 | CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y 500 | # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set 501 | # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set 502 | # end of Wi-Fi 503 | 504 | # 505 | # PHY 506 | # 507 | CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y 508 | # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set 509 | CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 510 | CONFIG_ESP32_PHY_MAX_TX_POWER=20 511 | # end of PHY 512 | 513 | # 514 | # Core dump 515 | # 516 | # CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set 517 | # CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set 518 | CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y 519 | # end of Core dump 520 | 521 | # 522 | # FAT Filesystem support 523 | # 524 | # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set 525 | CONFIG_FATFS_CODEPAGE_437=y 526 | # CONFIG_FATFS_CODEPAGE_720 is not set 527 | # CONFIG_FATFS_CODEPAGE_737 is not set 528 | # CONFIG_FATFS_CODEPAGE_771 is not set 529 | # CONFIG_FATFS_CODEPAGE_775 is not set 530 | # CONFIG_FATFS_CODEPAGE_850 is not set 531 | # CONFIG_FATFS_CODEPAGE_852 is not set 532 | # CONFIG_FATFS_CODEPAGE_855 is not set 533 | # CONFIG_FATFS_CODEPAGE_857 is not set 534 | # CONFIG_FATFS_CODEPAGE_860 is not set 535 | # CONFIG_FATFS_CODEPAGE_861 is not set 536 | # CONFIG_FATFS_CODEPAGE_862 is not set 537 | # CONFIG_FATFS_CODEPAGE_863 is not set 538 | # CONFIG_FATFS_CODEPAGE_864 is not set 539 | # CONFIG_FATFS_CODEPAGE_865 is not set 540 | # CONFIG_FATFS_CODEPAGE_866 is not set 541 | # CONFIG_FATFS_CODEPAGE_869 is not set 542 | # CONFIG_FATFS_CODEPAGE_932 is not set 543 | # CONFIG_FATFS_CODEPAGE_936 is not set 544 | # CONFIG_FATFS_CODEPAGE_949 is not set 545 | # CONFIG_FATFS_CODEPAGE_950 is not set 546 | CONFIG_FATFS_CODEPAGE=437 547 | CONFIG_FATFS_LFN_NONE=y 548 | # CONFIG_FATFS_LFN_HEAP is not set 549 | # CONFIG_FATFS_LFN_STACK is not set 550 | CONFIG_FATFS_FS_LOCK=0 551 | CONFIG_FATFS_TIMEOUT_MS=10000 552 | CONFIG_FATFS_PER_FILE_CACHE=y 553 | # CONFIG_FATFS_USE_FASTSEEK is not set 554 | # end of FAT Filesystem support 555 | 556 | # 557 | # Modbus configuration 558 | # 559 | CONFIG_FMB_COMM_MODE_TCP_EN=y 560 | CONFIG_FMB_TCP_PORT_DEFAULT=502 561 | CONFIG_FMB_TCP_PORT_MAX_CONN=5 562 | CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 563 | CONFIG_FMB_COMM_MODE_RTU_EN=y 564 | CONFIG_FMB_COMM_MODE_ASCII_EN=y 565 | CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 566 | CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 567 | CONFIG_FMB_QUEUE_LENGTH=20 568 | CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 569 | CONFIG_FMB_SERIAL_BUF_SIZE=256 570 | CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 571 | CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 572 | CONFIG_FMB_PORT_TASK_PRIO=10 573 | CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y 574 | CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233 575 | CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 576 | CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 577 | CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 578 | CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 579 | CONFIG_FMB_TIMER_PORT_ENABLED=y 580 | CONFIG_FMB_TIMER_GROUP=0 581 | CONFIG_FMB_TIMER_INDEX=0 582 | # CONFIG_FMB_TIMER_ISR_IN_IRAM is not set 583 | # end of Modbus configuration 584 | 585 | # 586 | # FreeRTOS 587 | # 588 | # CONFIG_FREERTOS_UNICORE is not set 589 | CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF 590 | CONFIG_FREERTOS_CORETIMER_0=y 591 | # CONFIG_FREERTOS_CORETIMER_1 is not set 592 | CONFIG_FREERTOS_HZ=100 593 | CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y 594 | # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set 595 | # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set 596 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y 597 | # CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set 598 | CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y 599 | CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 600 | CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y 601 | # CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set 602 | # CONFIG_FREERTOS_ASSERT_DISABLE is not set 603 | CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304 604 | CONFIG_FREERTOS_ISR_STACKSIZE=1536 605 | # CONFIG_FREERTOS_LEGACY_HOOKS is not set 606 | CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 607 | CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y 608 | # CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set 609 | CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 610 | CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 611 | CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 612 | CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 613 | # CONFIG_FREERTOS_USE_TRACE_FACILITY is not set 614 | # CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set 615 | CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y 616 | CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y 617 | # CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set 618 | # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set 619 | CONFIG_FREERTOS_DEBUG_OCDAWARE=y 620 | # CONFIG_FREERTOS_FPU_IN_ISR is not set 621 | # end of FreeRTOS 622 | 623 | # 624 | # Heap memory debugging 625 | # 626 | CONFIG_HEAP_POISONING_DISABLED=y 627 | # CONFIG_HEAP_POISONING_LIGHT is not set 628 | # CONFIG_HEAP_POISONING_COMPREHENSIVE is not set 629 | CONFIG_HEAP_TRACING_OFF=y 630 | # CONFIG_HEAP_TRACING_STANDALONE is not set 631 | # CONFIG_HEAP_TRACING_TOHOST is not set 632 | # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set 633 | # end of Heap memory debugging 634 | 635 | # 636 | # jsmn 637 | # 638 | # CONFIG_JSMN_PARENT_LINKS is not set 639 | # CONFIG_JSMN_STRICT is not set 640 | # end of jsmn 641 | 642 | # 643 | # libsodium 644 | # 645 | # end of libsodium 646 | 647 | # 648 | # Log output 649 | # 650 | # CONFIG_LOG_DEFAULT_LEVEL_NONE is not set 651 | # CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set 652 | # CONFIG_LOG_DEFAULT_LEVEL_WARN is not set 653 | CONFIG_LOG_DEFAULT_LEVEL_INFO=y 654 | # CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set 655 | # CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set 656 | CONFIG_LOG_DEFAULT_LEVEL=3 657 | CONFIG_LOG_COLORS=y 658 | CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y 659 | # CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set 660 | # end of Log output 661 | 662 | # 663 | # LWIP 664 | # 665 | CONFIG_LWIP_LOCAL_HOSTNAME="espressif" 666 | CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y 667 | # CONFIG_LWIP_L2_TO_L3_COPY is not set 668 | # CONFIG_LWIP_IRAM_OPTIMIZATION is not set 669 | CONFIG_LWIP_TIMERS_ONDEMAND=y 670 | CONFIG_LWIP_MAX_SOCKETS=10 671 | # CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set 672 | # CONFIG_LWIP_SO_LINGER is not set 673 | CONFIG_LWIP_SO_REUSE=y 674 | CONFIG_LWIP_SO_REUSE_RXTOALL=y 675 | # CONFIG_LWIP_SO_RCVBUF is not set 676 | # CONFIG_LWIP_NETBUF_RECVINFO is not set 677 | CONFIG_LWIP_IP4_FRAG=y 678 | CONFIG_LWIP_IP6_FRAG=y 679 | # CONFIG_LWIP_IP4_REASSEMBLY is not set 680 | # CONFIG_LWIP_IP6_REASSEMBLY is not set 681 | # CONFIG_LWIP_IP_FORWARD is not set 682 | # CONFIG_LWIP_STATS is not set 683 | # CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set 684 | CONFIG_LWIP_ESP_GRATUITOUS_ARP=y 685 | CONFIG_LWIP_GARP_TMR_INTERVAL=60 686 | CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 687 | CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y 688 | # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set 689 | 690 | # 691 | # DHCP server 692 | # 693 | CONFIG_LWIP_DHCPS_LEASE_UNIT=60 694 | CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 695 | # end of DHCP server 696 | 697 | # CONFIG_LWIP_AUTOIP is not set 698 | CONFIG_LWIP_IPV6=y 699 | # CONFIG_LWIP_IPV6_AUTOCONFIG is not set 700 | CONFIG_LWIP_NETIF_LOOPBACK=y 701 | CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 702 | 703 | # 704 | # TCP 705 | # 706 | CONFIG_LWIP_MAX_ACTIVE_TCP=16 707 | CONFIG_LWIP_MAX_LISTENING_TCP=16 708 | CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y 709 | CONFIG_LWIP_TCP_MAXRTX=12 710 | CONFIG_LWIP_TCP_SYNMAXRTX=12 711 | CONFIG_LWIP_TCP_MSS=1440 712 | CONFIG_LWIP_TCP_TMR_INTERVAL=250 713 | CONFIG_LWIP_TCP_MSL=60000 714 | CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 715 | CONFIG_LWIP_TCP_WND_DEFAULT=5744 716 | CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 717 | CONFIG_LWIP_TCP_QUEUE_OOSEQ=y 718 | # CONFIG_LWIP_TCP_SACK_OUT is not set 719 | # CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set 720 | CONFIG_LWIP_TCP_OVERSIZE_MSS=y 721 | # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set 722 | # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set 723 | CONFIG_LWIP_TCP_RTO_TIME=1500 724 | # end of TCP 725 | 726 | # 727 | # UDP 728 | # 729 | CONFIG_LWIP_MAX_UDP_PCBS=16 730 | CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 731 | # end of UDP 732 | 733 | # 734 | # Checksums 735 | # 736 | # CONFIG_LWIP_CHECKSUM_CHECK_IP is not set 737 | # CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set 738 | CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y 739 | # end of Checksums 740 | 741 | CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 742 | CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y 743 | # CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set 744 | # CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set 745 | CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF 746 | # CONFIG_LWIP_PPP_SUPPORT is not set 747 | CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 748 | CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 749 | # CONFIG_LWIP_SLIP_SUPPORT is not set 750 | 751 | # 752 | # ICMP 753 | # 754 | # CONFIG_LWIP_MULTICAST_PING is not set 755 | # CONFIG_LWIP_BROADCAST_PING is not set 756 | # end of ICMP 757 | 758 | # 759 | # LWIP RAW API 760 | # 761 | CONFIG_LWIP_MAX_RAW_PCBS=16 762 | # end of LWIP RAW API 763 | 764 | # 765 | # SNTP 766 | # 767 | CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 768 | CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 769 | # end of SNTP 770 | 771 | CONFIG_LWIP_ESP_LWIP_ASSERT=y 772 | 773 | # 774 | # Hooks 775 | # 776 | # CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set 777 | CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y 778 | # CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set 779 | CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y 780 | # CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set 781 | # CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set 782 | CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y 783 | # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set 784 | # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set 785 | # end of Hooks 786 | 787 | # CONFIG_LWIP_DEBUG is not set 788 | # end of LWIP 789 | 790 | # 791 | # mbedTLS 792 | # 793 | CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y 794 | # CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set 795 | # CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set 796 | CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y 797 | CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 798 | CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 799 | # CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set 800 | # CONFIG_MBEDTLS_DEBUG is not set 801 | 802 | # 803 | # Certificate Bundle 804 | # 805 | CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y 806 | CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y 807 | # CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set 808 | # CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set 809 | # CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set 810 | # end of Certificate Bundle 811 | 812 | # CONFIG_MBEDTLS_ECP_RESTARTABLE is not set 813 | # CONFIG_MBEDTLS_CMAC_C is not set 814 | CONFIG_MBEDTLS_HARDWARE_AES=y 815 | CONFIG_MBEDTLS_HARDWARE_MPI=y 816 | CONFIG_MBEDTLS_HARDWARE_SHA=y 817 | CONFIG_MBEDTLS_ROM_MD5=y 818 | # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set 819 | # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set 820 | CONFIG_MBEDTLS_HAVE_TIME=y 821 | # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set 822 | CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y 823 | CONFIG_MBEDTLS_SHA512_C=y 824 | CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y 825 | # CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set 826 | # CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set 827 | # CONFIG_MBEDTLS_TLS_DISABLED is not set 828 | CONFIG_MBEDTLS_TLS_SERVER=y 829 | CONFIG_MBEDTLS_TLS_CLIENT=y 830 | CONFIG_MBEDTLS_TLS_ENABLED=y 831 | 832 | # 833 | # TLS Key Exchange Methods 834 | # 835 | # CONFIG_MBEDTLS_PSK_MODES is not set 836 | CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y 837 | CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y 838 | CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y 839 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y 840 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y 841 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y 842 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y 843 | # end of TLS Key Exchange Methods 844 | 845 | CONFIG_MBEDTLS_SSL_RENEGOTIATION=y 846 | # CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set 847 | CONFIG_MBEDTLS_SSL_PROTO_TLS1=y 848 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y 849 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y 850 | # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set 851 | CONFIG_MBEDTLS_SSL_ALPN=y 852 | CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y 853 | CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y 854 | 855 | # 856 | # Symmetric Ciphers 857 | # 858 | CONFIG_MBEDTLS_AES_C=y 859 | # CONFIG_MBEDTLS_CAMELLIA_C is not set 860 | # CONFIG_MBEDTLS_DES_C is not set 861 | CONFIG_MBEDTLS_RC4_DISABLED=y 862 | # CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set 863 | # CONFIG_MBEDTLS_RC4_ENABLED is not set 864 | # CONFIG_MBEDTLS_BLOWFISH_C is not set 865 | # CONFIG_MBEDTLS_XTEA_C is not set 866 | CONFIG_MBEDTLS_CCM_C=y 867 | CONFIG_MBEDTLS_GCM_C=y 868 | # end of Symmetric Ciphers 869 | 870 | # CONFIG_MBEDTLS_RIPEMD160_C is not set 871 | 872 | # 873 | # Certificates 874 | # 875 | CONFIG_MBEDTLS_PEM_PARSE_C=y 876 | CONFIG_MBEDTLS_PEM_WRITE_C=y 877 | CONFIG_MBEDTLS_X509_CRL_PARSE_C=y 878 | CONFIG_MBEDTLS_X509_CSR_PARSE_C=y 879 | # end of Certificates 880 | 881 | CONFIG_MBEDTLS_ECP_C=y 882 | CONFIG_MBEDTLS_ECDH_C=y 883 | CONFIG_MBEDTLS_ECDSA_C=y 884 | # CONFIG_MBEDTLS_ECJPAKE_C is not set 885 | CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y 886 | CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y 887 | CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y 888 | CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y 889 | CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y 890 | CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y 891 | CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y 892 | CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y 893 | CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y 894 | CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y 895 | CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y 896 | CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y 897 | CONFIG_MBEDTLS_ECP_NIST_OPTIM=y 898 | # CONFIG_MBEDTLS_POLY1305_C is not set 899 | # CONFIG_MBEDTLS_CHACHA20_C is not set 900 | # CONFIG_MBEDTLS_HKDF_C is not set 901 | # CONFIG_MBEDTLS_THREADING_C is not set 902 | # CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set 903 | # CONFIG_MBEDTLS_SECURITY_RISKS is not set 904 | # end of mbedTLS 905 | 906 | # 907 | # mDNS 908 | # 909 | CONFIG_MDNS_MAX_SERVICES=10 910 | CONFIG_MDNS_TASK_PRIORITY=1 911 | CONFIG_MDNS_TASK_STACK_SIZE=4096 912 | # CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set 913 | CONFIG_MDNS_TASK_AFFINITY_CPU0=y 914 | # CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set 915 | CONFIG_MDNS_TASK_AFFINITY=0x0 916 | CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 917 | # CONFIG_MDNS_STRICT_MODE is not set 918 | CONFIG_MDNS_TIMER_PERIOD_MS=100 919 | # end of mDNS 920 | 921 | # 922 | # ESP-MQTT Configurations 923 | # 924 | CONFIG_MQTT_PROTOCOL_311=y 925 | CONFIG_MQTT_TRANSPORT_SSL=y 926 | CONFIG_MQTT_TRANSPORT_WEBSOCKET=y 927 | CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y 928 | # CONFIG_MQTT_MSG_ID_INCREMENTAL is not set 929 | # CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set 930 | # CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set 931 | # CONFIG_MQTT_USE_CUSTOM_CONFIG is not set 932 | # CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set 933 | # CONFIG_MQTT_CUSTOM_OUTBOX is not set 934 | # end of ESP-MQTT Configurations 935 | 936 | # 937 | # Newlib 938 | # 939 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y 940 | # CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set 941 | # CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set 942 | # CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set 943 | # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set 944 | CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y 945 | # CONFIG_NEWLIB_NANO_FORMAT is not set 946 | # end of Newlib 947 | 948 | # 949 | # NVS 950 | # 951 | # end of NVS 952 | 953 | # 954 | # OpenSSL 955 | # 956 | # CONFIG_OPENSSL_DEBUG is not set 957 | CONFIG_OPENSSL_ERROR_STACK=y 958 | # CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set 959 | CONFIG_OPENSSL_ASSERT_EXIT=y 960 | # end of OpenSSL 961 | 962 | # 963 | # PThreads 964 | # 965 | CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 966 | CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 967 | CONFIG_PTHREAD_STACK_MIN=768 968 | CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y 969 | # CONFIG_PTHREAD_DEFAULT_CORE_0 is not set 970 | # CONFIG_PTHREAD_DEFAULT_CORE_1 is not set 971 | CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 972 | CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" 973 | # end of PThreads 974 | 975 | # 976 | # SPI Flash driver 977 | # 978 | # CONFIG_SPI_FLASH_VERIFY_WRITE is not set 979 | # CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set 980 | CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y 981 | CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y 982 | # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set 983 | # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set 984 | # CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set 985 | # CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set 986 | # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set 987 | CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y 988 | CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 989 | CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 990 | CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 991 | # CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set 992 | # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set 993 | 994 | # 995 | # Auto-detect flash chips 996 | # 997 | CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y 998 | CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y 999 | CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y 1000 | CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y 1001 | # end of Auto-detect flash chips 1002 | 1003 | CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y 1004 | # end of SPI Flash driver 1005 | 1006 | # 1007 | # SPIFFS Configuration 1008 | # 1009 | CONFIG_SPIFFS_MAX_PARTITIONS=3 1010 | 1011 | # 1012 | # SPIFFS Cache Configuration 1013 | # 1014 | CONFIG_SPIFFS_CACHE=y 1015 | CONFIG_SPIFFS_CACHE_WR=y 1016 | # CONFIG_SPIFFS_CACHE_STATS is not set 1017 | # end of SPIFFS Cache Configuration 1018 | 1019 | CONFIG_SPIFFS_PAGE_CHECK=y 1020 | CONFIG_SPIFFS_GC_MAX_RUNS=10 1021 | # CONFIG_SPIFFS_GC_STATS is not set 1022 | CONFIG_SPIFFS_PAGE_SIZE=256 1023 | CONFIG_SPIFFS_OBJ_NAME_LEN=32 1024 | # CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set 1025 | CONFIG_SPIFFS_USE_MAGIC=y 1026 | CONFIG_SPIFFS_USE_MAGIC_LENGTH=y 1027 | CONFIG_SPIFFS_META_LENGTH=4 1028 | CONFIG_SPIFFS_USE_MTIME=y 1029 | 1030 | # 1031 | # Debug Configuration 1032 | # 1033 | # CONFIG_SPIFFS_DBG is not set 1034 | # CONFIG_SPIFFS_API_DBG is not set 1035 | # CONFIG_SPIFFS_GC_DBG is not set 1036 | # CONFIG_SPIFFS_CACHE_DBG is not set 1037 | # CONFIG_SPIFFS_CHECK_DBG is not set 1038 | # CONFIG_SPIFFS_TEST_VISUALISATION is not set 1039 | # end of Debug Configuration 1040 | # end of SPIFFS Configuration 1041 | 1042 | # 1043 | # TCP Transport 1044 | # 1045 | CONFIG_WS_BUFFER_SIZE=1024 1046 | # end of TCP Transport 1047 | 1048 | # 1049 | # TinyUSB 1050 | # 1051 | # end of TinyUSB 1052 | 1053 | # 1054 | # Unity unit testing library 1055 | # 1056 | CONFIG_UNITY_ENABLE_FLOAT=y 1057 | CONFIG_UNITY_ENABLE_DOUBLE=y 1058 | # CONFIG_UNITY_ENABLE_COLOR is not set 1059 | CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y 1060 | # CONFIG_UNITY_ENABLE_FIXTURE is not set 1061 | # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set 1062 | # end of Unity unit testing library 1063 | 1064 | # 1065 | # Virtual file system 1066 | # 1067 | CONFIG_VFS_SUPPORT_IO=y 1068 | CONFIG_VFS_SUPPORT_DIR=y 1069 | CONFIG_VFS_SUPPORT_SELECT=y 1070 | CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y 1071 | CONFIG_VFS_SUPPORT_TERMIOS=y 1072 | 1073 | # 1074 | # Host File System I/O (Semihosting) 1075 | # 1076 | CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 1077 | CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 1078 | # end of Host File System I/O (Semihosting) 1079 | # end of Virtual file system 1080 | 1081 | # 1082 | # Wear Levelling 1083 | # 1084 | # CONFIG_WL_SECTOR_SIZE_512 is not set 1085 | CONFIG_WL_SECTOR_SIZE_4096=y 1086 | CONFIG_WL_SECTOR_SIZE=4096 1087 | # end of Wear Levelling 1088 | 1089 | # 1090 | # Wi-Fi Provisioning Manager 1091 | # 1092 | CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 1093 | CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 1094 | # end of Wi-Fi Provisioning Manager 1095 | 1096 | # 1097 | # Supplicant 1098 | # 1099 | CONFIG_WPA_MBEDTLS_CRYPTO=y 1100 | # CONFIG_WPA_WAPI_PSK is not set 1101 | # CONFIG_WPA_DEBUG_PRINT is not set 1102 | # CONFIG_WPA_TESTING_OPTIONS is not set 1103 | # CONFIG_WPA_WPS_WARS is not set 1104 | # CONFIG_WPA_11KV_SUPPORT is not set 1105 | # end of Supplicant 1106 | # end of Component config 1107 | 1108 | # 1109 | # Compatibility options 1110 | # 1111 | # CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set 1112 | # end of Compatibility options 1113 | -------------------------------------------------------------------------------- /src/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # This file was automatically generated for projects 2 | # without default 'CMakeLists.txt' file. 3 | 4 | FILE(GLOB_RECURSE app_sources ${CMAKE_SOURCE_DIR}/src/*.*) 5 | 6 | idf_component_register(SRCS ${app_sources}) 7 | -------------------------------------------------------------------------------- /src/config.cpp: -------------------------------------------------------------------------------- 1 | #include "config.h" 2 | 3 | // i2s speaker pins 4 | i2s_pin_config_t i2s_speaker_pins = { 5 | .bck_io_num = I2S_SPEAKER_SERIAL_CLOCK, 6 | .ws_io_num = I2S_SPEAKER_LEFT_RIGHT_CLOCK, 7 | .data_out_num = I2S_SPEAKER_SERIAL_DATA, 8 | .data_in_num = I2S_PIN_NO_CHANGE}; -------------------------------------------------------------------------------- /src/config.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | // comment this out if you want to use the internal DAC 5 | #define USE_I2S 6 | 7 | // speaker settings - if using I2S 8 | #define I2S_SPEAKER_SERIAL_CLOCK GPIO_NUM_19 9 | #define I2S_SPEAKER_LEFT_RIGHT_CLOCK GPIO_NUM_21 10 | #define I2S_SPEAKER_SERIAL_DATA GPIO_NUM_18 11 | #define I2S_SPEAKDER_SD_PIN GPIO_NUM_5 12 | 13 | // volume control - if required 14 | #define VOLUME_CONTROL ADC1_CHANNEL_7 15 | 16 | // button - GPIO 0 is the built in button on most dev boards 17 | #define GPIO_BUTTON GPIO_NUM_0 18 | 19 | // i2s speaker pins definition 20 | extern i2s_pin_config_t i2s_speaker_pins; 21 | -------------------------------------------------------------------------------- /src/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #define MINIMP3_IMPLEMENTATION 9 | #define MINIMP3_ONLY_MP3 10 | #define MINIMP3_NO_STDIO 11 | #include "minimp3.h" 12 | 13 | extern "C" 14 | { 15 | void app_main(); 16 | } 17 | 18 | void wait_for_button_push() 19 | { 20 | while (gpio_get_level(GPIO_BUTTON) == 1) 21 | { 22 | vTaskDelay(pdMS_TO_TICKS(100)); 23 | } 24 | } 25 | 26 | const int BUFFER_SIZE = 1024; 27 | 28 | void play_task(void *param) 29 | { 30 | #ifdef VOLUME_CONTROL 31 | // set up the ADC for reading the volume control 32 | adc1_config_width(ADC_WIDTH_BIT_12); 33 | adc1_config_channel_atten(ADC1_CHANNEL_7, ADC_ATTEN_DB_11); 34 | #endif 35 | // create the output - see config.h for settings 36 | #ifdef USE_I2S 37 | Output *output = new I2SOutput(I2S_NUM_0, i2s_speaker_pins); 38 | #else 39 | Output *output = new DACOutput(); 40 | #endif 41 | #ifdef I2S_SPEAKDER_SD_PIN 42 | // if you I2S amp has a SD pin, you'll need to turn it on 43 | gpio_set_direction(I2S_SPEAKDER_SD_PIN, GPIO_MODE_OUTPUT); 44 | gpio_set_level(I2S_SPEAKDER_SD_PIN, 1); 45 | #endif 46 | // setup the button to trigger playback - see config.h for settings 47 | gpio_set_direction(GPIO_BUTTON, GPIO_MODE_INPUT); 48 | gpio_set_pull_mode(GPIO_BUTTON, GPIO_PULLUP_ONLY); 49 | // create the file system 50 | SPIFFS spiffs("/fs"); 51 | // setup for the mp3 decoded 52 | short *pcm = (short *)malloc(sizeof(short) * MINIMP3_MAX_SAMPLES_PER_FRAME); 53 | uint8_t *input_buf = (uint8_t *)malloc(BUFFER_SIZE); 54 | if (!pcm) 55 | { 56 | ESP_LOGE("main", "Failed to allocate pcm memory"); 57 | } 58 | if (!input_buf) 59 | { 60 | ESP_LOGE("main", "Failed to allocate input_buf memory"); 61 | } 62 | while (true) 63 | { 64 | // wait for the button to be pushed 65 | wait_for_button_push(); 66 | // mp3 decoder state 67 | mp3dec_t mp3d = {}; 68 | mp3dec_init(&mp3d); 69 | mp3dec_frame_info_t info = {}; 70 | // keep track of how much data we have buffered, need to read and decoded 71 | int to_read = BUFFER_SIZE; 72 | int buffered = 0; 73 | int decoded = 0; 74 | bool is_output_started = false; 75 | // this assumes that you have uploaded the mp3 file to the SPIFFS 76 | FILE *fp = fopen("/fs/test.mp3", "r"); 77 | if (!fp) 78 | { 79 | ESP_LOGE("main", "Failed to open file"); 80 | continue; 81 | } 82 | while (1) 83 | { 84 | #ifdef VOLUME_CONTROL 85 | auto adc_value = float(adc1_get_raw(VOLUME_CONTROL)) / 4096.0f; 86 | // make the actual volume match how people hear 87 | // https://ux.stackexchange.com/questions/79672/why-dont-commercial-products-use-logarithmic-volume-controls 88 | output->set_volume(adc_value * adc_value); 89 | #endif 90 | // read in the data that is needed to top up the buffer 91 | size_t n = fread(input_buf + buffered, 1, to_read, fp); 92 | // feed the watchdog 93 | vTaskDelay(pdMS_TO_TICKS(1)); 94 | // ESP_LOGI("main", "Read %d bytes\n", n); 95 | buffered += n; 96 | if (buffered == 0) 97 | { 98 | // we've reached the end of the file and processed all the buffered data 99 | output->stop(); 100 | is_output_started = false; 101 | break; 102 | } 103 | // decode the next frame 104 | int samples = mp3dec_decode_frame(&mp3d, input_buf, buffered, pcm, &info); 105 | // we've processed this may bytes from teh buffered data 106 | buffered -= info.frame_bytes; 107 | // shift the remaining data to the front of the buffer 108 | memmove(input_buf, input_buf + info.frame_bytes, buffered); 109 | // we need to top up the buffer from the file 110 | to_read = info.frame_bytes; 111 | if (samples > 0) 112 | { 113 | // if we haven't started the output yet we can do it now as we now know the sample rate and number of channels 114 | if (!is_output_started) 115 | { 116 | output->start(info.hz); 117 | is_output_started = true; 118 | } 119 | // if we've decoded a frame of mono samples convert it to stereo by duplicating the left channel 120 | // we can do this in place as our samples buffer has enough space 121 | if (info.channels == 1) 122 | { 123 | for (int i = samples - 1; i >= 0; i--) 124 | { 125 | pcm[i * 2] = pcm[i]; 126 | pcm[i * 2 - 1] = pcm[i]; 127 | } 128 | } 129 | // write the decoded samples to the I2S output 130 | output->write(pcm, samples); 131 | // keep track of how many samples we've decoded 132 | decoded += samples; 133 | } 134 | // ESP_LOGI("main", "decoded %d samples\n", decoded); 135 | } 136 | ESP_LOGI("main", "Finished\n"); 137 | fclose(fp); 138 | } 139 | } 140 | 141 | void app_main() 142 | { 143 | xTaskCreatePinnedToCore(play_task, "task", 32768, NULL, 1, NULL, 1); 144 | } -------------------------------------------------------------------------------- /src/minimp3.h: -------------------------------------------------------------------------------- 1 | #ifndef MINIMP3_H 2 | #define MINIMP3_H 3 | /* 4 | https://github.com/lieff/minimp3 5 | To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. 6 | This software is distributed without any warranty. 7 | See . 8 | */ 9 | #include 10 | 11 | #define MINIMP3_MAX_SAMPLES_PER_FRAME (1152 * 2) 12 | 13 | typedef struct 14 | { 15 | int frame_bytes, frame_offset, channels, hz, layer, bitrate_kbps; 16 | } mp3dec_frame_info_t; 17 | 18 | typedef struct 19 | { 20 | float mdct_overlap[2][9 * 32], qmf_state[15 * 2 * 32]; 21 | int reserv, free_format_bytes; 22 | unsigned char header[4], reserv_buf[511]; 23 | } mp3dec_t; 24 | 25 | #ifdef __cplusplus 26 | extern "C" 27 | { 28 | #endif /* __cplusplus */ 29 | 30 | void mp3dec_init(mp3dec_t *dec); 31 | #ifndef MINIMP3_FLOAT_OUTPUT 32 | typedef int16_t mp3d_sample_t; 33 | #else /* MINIMP3_FLOAT_OUTPUT */ 34 | typedef float mp3d_sample_t; 35 | void mp3dec_f32_to_s16(const float *in, int16_t *out, int num_samples); 36 | #endif /* MINIMP3_FLOAT_OUTPUT */ 37 | int mp3dec_decode_frame(mp3dec_t *dec, const uint8_t *mp3, int mp3_bytes, mp3d_sample_t *pcm, mp3dec_frame_info_t *info); 38 | 39 | #ifdef __cplusplus 40 | } 41 | #endif /* __cplusplus */ 42 | 43 | #endif /* MINIMP3_H */ 44 | #if defined(MINIMP3_IMPLEMENTATION) && !defined(_MINIMP3_IMPLEMENTATION_GUARD) 45 | #define _MINIMP3_IMPLEMENTATION_GUARD 46 | 47 | #include 48 | #include 49 | 50 | #define MAX_FREE_FORMAT_FRAME_SIZE 2304 /* more than ISO spec's */ 51 | #ifndef MAX_FRAME_SYNC_MATCHES 52 | #define MAX_FRAME_SYNC_MATCHES 10 53 | #endif /* MAX_FRAME_SYNC_MATCHES */ 54 | 55 | #define MAX_L3_FRAME_PAYLOAD_BYTES MAX_FREE_FORMAT_FRAME_SIZE /* MUST be >= 320000/8/32000*1152 = 1440 */ 56 | 57 | #define MAX_BITRESERVOIR_BYTES 511 58 | #define SHORT_BLOCK_TYPE 2 59 | #define STOP_BLOCK_TYPE 3 60 | #define MODE_MONO 3 61 | #define MODE_JOINT_STEREO 1 62 | #define HDR_SIZE 4 63 | #define HDR_IS_MONO(h) (((h[3]) & 0xC0) == 0xC0) 64 | #define HDR_IS_MS_STEREO(h) (((h[3]) & 0xE0) == 0x60) 65 | #define HDR_IS_FREE_FORMAT(h) (((h[2]) & 0xF0) == 0) 66 | #define HDR_IS_CRC(h) (!((h[1]) & 1)) 67 | #define HDR_TEST_PADDING(h) ((h[2]) & 0x2) 68 | #define HDR_TEST_MPEG1(h) ((h[1]) & 0x8) 69 | #define HDR_TEST_NOT_MPEG25(h) ((h[1]) & 0x10) 70 | #define HDR_TEST_I_STEREO(h) ((h[3]) & 0x10) 71 | #define HDR_TEST_MS_STEREO(h) ((h[3]) & 0x20) 72 | #define HDR_GET_STEREO_MODE(h) (((h[3]) >> 6) & 3) 73 | #define HDR_GET_STEREO_MODE_EXT(h) (((h[3]) >> 4) & 3) 74 | #define HDR_GET_LAYER(h) (((h[1]) >> 1) & 3) 75 | #define HDR_GET_BITRATE(h) ((h[2]) >> 4) 76 | #define HDR_GET_SAMPLE_RATE(h) (((h[2]) >> 2) & 3) 77 | #define HDR_GET_MY_SAMPLE_RATE(h) (HDR_GET_SAMPLE_RATE(h) + (((h[1] >> 3) & 1) + ((h[1] >> 4) & 1)) * 3) 78 | #define HDR_IS_FRAME_576(h) ((h[1] & 14) == 2) 79 | #define HDR_IS_LAYER_1(h) ((h[1] & 6) == 6) 80 | 81 | #define BITS_DEQUANTIZER_OUT -1 82 | #define MAX_SCF (255 + BITS_DEQUANTIZER_OUT * 4 - 210) 83 | #define MAX_SCFI ((MAX_SCF + 3) & ~3) 84 | 85 | #define MINIMP3_MIN(a, b) ((a) > (b) ? (b) : (a)) 86 | #define MINIMP3_MAX(a, b) ((a) < (b) ? (b) : (a)) 87 | 88 | #if !defined(MINIMP3_NO_SIMD) 89 | 90 | #if !defined(MINIMP3_ONLY_SIMD) && (defined(_M_X64) || defined(__x86_64__) || defined(__aarch64__) || defined(_M_ARM64)) 91 | /* x64 always have SSE2, arm64 always have neon, no need for generic code */ 92 | #define MINIMP3_ONLY_SIMD 93 | #endif /* SIMD checks... */ 94 | 95 | #if (defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_X64))) || ((defined(__i386__) || defined(__x86_64__)) && defined(__SSE2__)) 96 | #if defined(_MSC_VER) 97 | #include 98 | #endif /* defined(_MSC_VER) */ 99 | #include 100 | #define HAVE_SSE 1 101 | #define HAVE_SIMD 1 102 | #define VSTORE _mm_storeu_ps 103 | #define VLD _mm_loadu_ps 104 | #define VSET _mm_set1_ps 105 | #define VADD _mm_add_ps 106 | #define VSUB _mm_sub_ps 107 | #define VMUL _mm_mul_ps 108 | #define VMAC(a, x, y) _mm_add_ps(a, _mm_mul_ps(x, y)) 109 | #define VMSB(a, x, y) _mm_sub_ps(a, _mm_mul_ps(x, y)) 110 | #define VMUL_S(x, s) _mm_mul_ps(x, _mm_set1_ps(s)) 111 | #define VREV(x) _mm_shuffle_ps(x, x, _MM_SHUFFLE(0, 1, 2, 3)) 112 | typedef __m128 f4; 113 | #if defined(_MSC_VER) || defined(MINIMP3_ONLY_SIMD) 114 | #define minimp3_cpuid __cpuid 115 | #else /* defined(_MSC_VER) || defined(MINIMP3_ONLY_SIMD) */ 116 | static __inline__ __attribute__((always_inline)) void minimp3_cpuid(int CPUInfo[], const int InfoType) 117 | { 118 | #if defined(__PIC__) 119 | __asm__ __volatile__( 120 | #if defined(__x86_64__) 121 | "push %%rbx\n" 122 | "cpuid\n" 123 | "xchgl %%ebx, %1\n" 124 | "pop %%rbx\n" 125 | #else /* defined(__x86_64__) */ 126 | "xchgl %%ebx, %1\n" 127 | "cpuid\n" 128 | "xchgl %%ebx, %1\n" 129 | #endif /* defined(__x86_64__) */ 130 | : "=a"(CPUInfo[0]), "=r"(CPUInfo[1]), "=c"(CPUInfo[2]), "=d"(CPUInfo[3]) 131 | : "a"(InfoType)); 132 | #else /* defined(__PIC__) */ 133 | __asm__ __volatile__( 134 | "cpuid" 135 | : "=a"(CPUInfo[0]), "=b"(CPUInfo[1]), "=c"(CPUInfo[2]), "=d"(CPUInfo[3]) 136 | : "a"(InfoType)); 137 | #endif /* defined(__PIC__)*/ 138 | } 139 | #endif /* defined(_MSC_VER) || defined(MINIMP3_ONLY_SIMD) */ 140 | static int have_simd(void) 141 | { 142 | #ifdef MINIMP3_ONLY_SIMD 143 | return 1; 144 | #else /* MINIMP3_ONLY_SIMD */ 145 | static int g_have_simd; 146 | int CPUInfo[4]; 147 | #ifdef MINIMP3_TEST 148 | static int g_counter; 149 | if (g_counter++ > 100) 150 | return 0; 151 | #endif /* MINIMP3_TEST */ 152 | if (g_have_simd) 153 | goto end; 154 | minimp3_cpuid(CPUInfo, 0); 155 | g_have_simd = 1; 156 | if (CPUInfo[0] > 0) 157 | { 158 | minimp3_cpuid(CPUInfo, 1); 159 | g_have_simd = (CPUInfo[3] & (1 << 26)) + 1; /* SSE2 */ 160 | } 161 | end: 162 | return g_have_simd - 1; 163 | #endif /* MINIMP3_ONLY_SIMD */ 164 | } 165 | #elif defined(__ARM_NEON) || defined(__aarch64__) || defined(_M_ARM64) 166 | #include 167 | #define HAVE_SSE 0 168 | #define HAVE_SIMD 1 169 | #define VSTORE vst1q_f32 170 | #define VLD vld1q_f32 171 | #define VSET vmovq_n_f32 172 | #define VADD vaddq_f32 173 | #define VSUB vsubq_f32 174 | #define VMUL vmulq_f32 175 | #define VMAC(a, x, y) vmlaq_f32(a, x, y) 176 | #define VMSB(a, x, y) vmlsq_f32(a, x, y) 177 | #define VMUL_S(x, s) vmulq_f32(x, vmovq_n_f32(s)) 178 | #define VREV(x) vcombine_f32(vget_high_f32(vrev64q_f32(x)), vget_low_f32(vrev64q_f32(x))) 179 | typedef float32x4_t f4; 180 | static int have_simd() 181 | { /* TODO: detect neon for !MINIMP3_ONLY_SIMD */ 182 | return 1; 183 | } 184 | #else /* SIMD checks... */ 185 | #define HAVE_SSE 0 186 | #define HAVE_SIMD 0 187 | #ifdef MINIMP3_ONLY_SIMD 188 | #error MINIMP3_ONLY_SIMD used, but SSE/NEON not enabled 189 | #endif /* MINIMP3_ONLY_SIMD */ 190 | #endif /* SIMD checks... */ 191 | #else /* !defined(MINIMP3_NO_SIMD) */ 192 | #define HAVE_SIMD 0 193 | #endif /* !defined(MINIMP3_NO_SIMD) */ 194 | 195 | #if defined(__ARM_ARCH) && (__ARM_ARCH >= 6) && !defined(__aarch64__) && !defined(_M_ARM64) 196 | #define HAVE_ARMV6 1 197 | static __inline__ __attribute__((always_inline)) int32_t minimp3_clip_int16_arm(int32_t a) 198 | { 199 | int32_t x = 0; 200 | __asm__("ssat %0, #16, %1" 201 | : "=r"(x) 202 | : "r"(a)); 203 | return x; 204 | } 205 | #else 206 | #define HAVE_ARMV6 0 207 | #endif 208 | 209 | typedef struct 210 | { 211 | const uint8_t *buf; 212 | int pos, limit; 213 | } bs_t; 214 | 215 | typedef struct 216 | { 217 | float scf[3 * 64]; 218 | uint8_t total_bands, stereo_bands, bitalloc[64], scfcod[64]; 219 | } L12_scale_info; 220 | 221 | typedef struct 222 | { 223 | uint8_t tab_offset, code_tab_width, band_count; 224 | } L12_subband_alloc_t; 225 | 226 | typedef struct 227 | { 228 | const uint8_t *sfbtab; 229 | uint16_t part_23_length, big_values, scalefac_compress; 230 | uint8_t global_gain, block_type, mixed_block_flag, n_long_sfb, n_short_sfb; 231 | uint8_t table_select[3], region_count[3], subblock_gain[3]; 232 | uint8_t preflag, scalefac_scale, count1_table, scfsi; 233 | } L3_gr_info_t; 234 | 235 | typedef struct 236 | { 237 | bs_t bs; 238 | uint8_t maindata[MAX_BITRESERVOIR_BYTES + MAX_L3_FRAME_PAYLOAD_BYTES]; 239 | L3_gr_info_t gr_info[4]; 240 | float grbuf[2][576], scf[40], syn[18 + 15][2 * 32]; 241 | uint8_t ist_pos[2][39]; 242 | } mp3dec_scratch_t; 243 | 244 | static void bs_init(bs_t *bs, const uint8_t *data, int bytes) 245 | { 246 | bs->buf = data; 247 | bs->pos = 0; 248 | bs->limit = bytes * 8; 249 | } 250 | 251 | static uint32_t get_bits(bs_t *bs, int n) 252 | { 253 | uint32_t next, cache = 0, s = bs->pos & 7; 254 | int shl = n + s; 255 | const uint8_t *p = bs->buf + (bs->pos >> 3); 256 | if ((bs->pos += n) > bs->limit) 257 | return 0; 258 | next = *p++ & (255 >> s); 259 | while ((shl -= 8) > 0) 260 | { 261 | cache |= next << shl; 262 | next = *p++; 263 | } 264 | return cache | (next >> -shl); 265 | } 266 | 267 | static int hdr_valid(const uint8_t *h) 268 | { 269 | return h[0] == 0xff && 270 | ((h[1] & 0xF0) == 0xf0 || (h[1] & 0xFE) == 0xe2) && 271 | (HDR_GET_LAYER(h) != 0) && 272 | (HDR_GET_BITRATE(h) != 15) && 273 | (HDR_GET_SAMPLE_RATE(h) != 3); 274 | } 275 | 276 | static int hdr_compare(const uint8_t *h1, const uint8_t *h2) 277 | { 278 | return hdr_valid(h2) && 279 | ((h1[1] ^ h2[1]) & 0xFE) == 0 && 280 | ((h1[2] ^ h2[2]) & 0x0C) == 0 && 281 | !(HDR_IS_FREE_FORMAT(h1) ^ HDR_IS_FREE_FORMAT(h2)); 282 | } 283 | 284 | static unsigned hdr_bitrate_kbps(const uint8_t *h) 285 | { 286 | static const uint8_t halfrate[2][3][15] = { 287 | {{0, 4, 8, 12, 16, 20, 24, 28, 32, 40, 48, 56, 64, 72, 80}, {0, 4, 8, 12, 16, 20, 24, 28, 32, 40, 48, 56, 64, 72, 80}, {0, 16, 24, 28, 32, 40, 48, 56, 64, 72, 80, 88, 96, 112, 128}}, 288 | {{0, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160}, {0, 16, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192}, {0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224}}, 289 | }; 290 | return 2 * halfrate[!!HDR_TEST_MPEG1(h)][HDR_GET_LAYER(h) - 1][HDR_GET_BITRATE(h)]; 291 | } 292 | 293 | static unsigned hdr_sample_rate_hz(const uint8_t *h) 294 | { 295 | static const unsigned g_hz[3] = {44100, 48000, 32000}; 296 | return g_hz[HDR_GET_SAMPLE_RATE(h)] >> (int)!HDR_TEST_MPEG1(h) >> (int)!HDR_TEST_NOT_MPEG25(h); 297 | } 298 | 299 | static unsigned hdr_frame_samples(const uint8_t *h) 300 | { 301 | return HDR_IS_LAYER_1(h) ? 384 : (1152 >> (int)HDR_IS_FRAME_576(h)); 302 | } 303 | 304 | static int hdr_frame_bytes(const uint8_t *h, int free_format_size) 305 | { 306 | int frame_bytes = hdr_frame_samples(h) * hdr_bitrate_kbps(h) * 125 / hdr_sample_rate_hz(h); 307 | if (HDR_IS_LAYER_1(h)) 308 | { 309 | frame_bytes &= ~3; /* slot align */ 310 | } 311 | return frame_bytes ? frame_bytes : free_format_size; 312 | } 313 | 314 | static int hdr_padding(const uint8_t *h) 315 | { 316 | return HDR_TEST_PADDING(h) ? (HDR_IS_LAYER_1(h) ? 4 : 1) : 0; 317 | } 318 | 319 | #ifndef MINIMP3_ONLY_MP3 320 | static const L12_subband_alloc_t *L12_subband_alloc_table(const uint8_t *hdr, L12_scale_info *sci) 321 | { 322 | const L12_subband_alloc_t *alloc; 323 | int mode = HDR_GET_STEREO_MODE(hdr); 324 | int nbands, stereo_bands = (mode == MODE_MONO) ? 0 : (mode == MODE_JOINT_STEREO) ? (HDR_GET_STEREO_MODE_EXT(hdr) << 2) + 4 325 | : 32; 326 | 327 | if (HDR_IS_LAYER_1(hdr)) 328 | { 329 | static const L12_subband_alloc_t g_alloc_L1[] = {{76, 4, 32}}; 330 | alloc = g_alloc_L1; 331 | nbands = 32; 332 | } 333 | else if (!HDR_TEST_MPEG1(hdr)) 334 | { 335 | static const L12_subband_alloc_t g_alloc_L2M2[] = {{60, 4, 4}, {44, 3, 7}, {44, 2, 19}}; 336 | alloc = g_alloc_L2M2; 337 | nbands = 30; 338 | } 339 | else 340 | { 341 | static const L12_subband_alloc_t g_alloc_L2M1[] = {{0, 4, 3}, {16, 4, 8}, {32, 3, 12}, {40, 2, 7}}; 342 | int sample_rate_idx = HDR_GET_SAMPLE_RATE(hdr); 343 | unsigned kbps = hdr_bitrate_kbps(hdr) >> (int)(mode != MODE_MONO); 344 | if (!kbps) /* free-format */ 345 | { 346 | kbps = 192; 347 | } 348 | 349 | alloc = g_alloc_L2M1; 350 | nbands = 27; 351 | if (kbps < 56) 352 | { 353 | static const L12_subband_alloc_t g_alloc_L2M1_lowrate[] = {{44, 4, 2}, {44, 3, 10}}; 354 | alloc = g_alloc_L2M1_lowrate; 355 | nbands = sample_rate_idx == 2 ? 12 : 8; 356 | } 357 | else if (kbps >= 96 && sample_rate_idx != 1) 358 | { 359 | nbands = 30; 360 | } 361 | } 362 | 363 | sci->total_bands = (uint8_t)nbands; 364 | sci->stereo_bands = (uint8_t)MINIMP3_MIN(stereo_bands, nbands); 365 | 366 | return alloc; 367 | } 368 | 369 | static void L12_read_scalefactors(bs_t *bs, uint8_t *pba, uint8_t *scfcod, int bands, float *scf) 370 | { 371 | static const float g_deq_L12[18 * 3] = { 372 | #define DQ(x) 9.53674316e-07f / x, 7.56931807e-07f / x, 6.00777173e-07f / x 373 | DQ(3), DQ(7), DQ(15), DQ(31), DQ(63), DQ(127), DQ(255), DQ(511), DQ(1023), DQ(2047), DQ(4095), DQ(8191), DQ(16383), DQ(32767), DQ(65535), DQ(3), DQ(5), DQ(9)}; 374 | int i, m; 375 | for (i = 0; i < bands; i++) 376 | { 377 | float s = 0; 378 | int ba = *pba++; 379 | int mask = ba ? 4 + ((19 >> scfcod[i]) & 3) : 0; 380 | for (m = 4; m; m >>= 1) 381 | { 382 | if (mask & m) 383 | { 384 | int b = get_bits(bs, 6); 385 | s = g_deq_L12[ba * 3 - 6 + b % 3] * (1 << 21 >> b / 3); 386 | } 387 | *scf++ = s; 388 | } 389 | } 390 | } 391 | 392 | static void L12_read_scale_info(const uint8_t *hdr, bs_t *bs, L12_scale_info *sci) 393 | { 394 | static const uint8_t g_bitalloc_code_tab[] = { 395 | 0, 17, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 396 | 0, 17, 18, 3, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16, 397 | 0, 17, 18, 3, 19, 4, 5, 16, 398 | 0, 17, 18, 16, 399 | 0, 17, 18, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 400 | 0, 17, 18, 3, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 401 | 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 402 | const L12_subband_alloc_t *subband_alloc = L12_subband_alloc_table(hdr, sci); 403 | 404 | int i, k = 0, ba_bits = 0; 405 | const uint8_t *ba_code_tab = g_bitalloc_code_tab; 406 | 407 | for (i = 0; i < sci->total_bands; i++) 408 | { 409 | uint8_t ba; 410 | if (i == k) 411 | { 412 | k += subband_alloc->band_count; 413 | ba_bits = subband_alloc->code_tab_width; 414 | ba_code_tab = g_bitalloc_code_tab + subband_alloc->tab_offset; 415 | subband_alloc++; 416 | } 417 | ba = ba_code_tab[get_bits(bs, ba_bits)]; 418 | sci->bitalloc[2 * i] = ba; 419 | if (i < sci->stereo_bands) 420 | { 421 | ba = ba_code_tab[get_bits(bs, ba_bits)]; 422 | } 423 | sci->bitalloc[2 * i + 1] = sci->stereo_bands ? ba : 0; 424 | } 425 | 426 | for (i = 0; i < 2 * sci->total_bands; i++) 427 | { 428 | sci->scfcod[i] = sci->bitalloc[i] ? HDR_IS_LAYER_1(hdr) ? 2 : get_bits(bs, 2) : 6; 429 | } 430 | 431 | L12_read_scalefactors(bs, sci->bitalloc, sci->scfcod, sci->total_bands * 2, sci->scf); 432 | 433 | for (i = sci->stereo_bands; i < sci->total_bands; i++) 434 | { 435 | sci->bitalloc[2 * i + 1] = 0; 436 | } 437 | } 438 | 439 | static int L12_dequantize_granule(float *grbuf, bs_t *bs, L12_scale_info *sci, int group_size) 440 | { 441 | int i, j, k, choff = 576; 442 | for (j = 0; j < 4; j++) 443 | { 444 | float *dst = grbuf + group_size * j; 445 | for (i = 0; i < 2 * sci->total_bands; i++) 446 | { 447 | int ba = sci->bitalloc[i]; 448 | if (ba != 0) 449 | { 450 | if (ba < 17) 451 | { 452 | int half = (1 << (ba - 1)) - 1; 453 | for (k = 0; k < group_size; k++) 454 | { 455 | dst[k] = (float)((int)get_bits(bs, ba) - half); 456 | } 457 | } 458 | else 459 | { 460 | unsigned mod = (2 << (ba - 17)) + 1; /* 3, 5, 9 */ 461 | unsigned code = get_bits(bs, mod + 2 - (mod >> 3)); /* 5, 7, 10 */ 462 | for (k = 0; k < group_size; k++, code /= mod) 463 | { 464 | dst[k] = (float)((int)(code % mod - mod / 2)); 465 | } 466 | } 467 | } 468 | dst += choff; 469 | choff = 18 - choff; 470 | } 471 | } 472 | return group_size * 4; 473 | } 474 | 475 | static void L12_apply_scf_384(L12_scale_info *sci, const float *scf, float *dst) 476 | { 477 | int i, k; 478 | memcpy(dst + 576 + sci->stereo_bands * 18, dst + sci->stereo_bands * 18, (sci->total_bands - sci->stereo_bands) * 18 * sizeof(float)); 479 | for (i = 0; i < sci->total_bands; i++, dst += 18, scf += 6) 480 | { 481 | for (k = 0; k < 12; k++) 482 | { 483 | dst[k + 0] *= scf[0]; 484 | dst[k + 576] *= scf[3]; 485 | } 486 | } 487 | } 488 | #endif /* MINIMP3_ONLY_MP3 */ 489 | 490 | static int L3_read_side_info(bs_t *bs, L3_gr_info_t *gr, const uint8_t *hdr) 491 | { 492 | static const uint8_t g_scf_long[8][23] = { 493 | {6, 6, 6, 6, 6, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 38, 46, 52, 60, 68, 58, 54, 0}, 494 | {12, 12, 12, 12, 12, 12, 16, 20, 24, 28, 32, 40, 48, 56, 64, 76, 90, 2, 2, 2, 2, 2, 0}, 495 | {6, 6, 6, 6, 6, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 38, 46, 52, 60, 68, 58, 54, 0}, 496 | {6, 6, 6, 6, 6, 6, 8, 10, 12, 14, 16, 18, 22, 26, 32, 38, 46, 54, 62, 70, 76, 36, 0}, 497 | {6, 6, 6, 6, 6, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 38, 46, 52, 60, 68, 58, 54, 0}, 498 | {4, 4, 4, 4, 4, 4, 6, 6, 8, 8, 10, 12, 16, 20, 24, 28, 34, 42, 50, 54, 76, 158, 0}, 499 | {4, 4, 4, 4, 4, 4, 6, 6, 6, 8, 10, 12, 16, 18, 22, 28, 34, 40, 46, 54, 54, 192, 0}, 500 | {4, 4, 4, 4, 4, 4, 6, 6, 8, 10, 12, 16, 20, 24, 30, 38, 46, 56, 68, 84, 102, 26, 0}}; 501 | static const uint8_t g_scf_short[8][40] = { 502 | {4, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 24, 24, 24, 30, 30, 30, 40, 40, 40, 18, 18, 18, 0}, 503 | {8, 8, 8, 8, 8, 8, 8, 8, 8, 12, 12, 12, 16, 16, 16, 20, 20, 20, 24, 24, 24, 28, 28, 28, 36, 36, 36, 2, 2, 2, 2, 2, 2, 2, 2, 2, 26, 26, 26, 0}, 504 | {4, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 6, 6, 6, 6, 8, 8, 8, 10, 10, 10, 14, 14, 14, 18, 18, 18, 26, 26, 26, 32, 32, 32, 42, 42, 42, 18, 18, 18, 0}, 505 | {4, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 24, 24, 24, 32, 32, 32, 44, 44, 44, 12, 12, 12, 0}, 506 | {4, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 24, 24, 24, 30, 30, 30, 40, 40, 40, 18, 18, 18, 0}, 507 | {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 22, 22, 22, 30, 30, 30, 56, 56, 56, 0}, 508 | {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 6, 6, 6, 6, 10, 10, 10, 12, 12, 12, 14, 14, 14, 16, 16, 16, 20, 20, 20, 26, 26, 26, 66, 66, 66, 0}, 509 | {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 6, 8, 8, 8, 12, 12, 12, 16, 16, 16, 20, 20, 20, 26, 26, 26, 34, 34, 34, 42, 42, 42, 12, 12, 12, 0}}; 510 | static const uint8_t g_scf_mixed[8][40] = { 511 | {6, 6, 6, 6, 6, 6, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 24, 24, 24, 30, 30, 30, 40, 40, 40, 18, 18, 18, 0}, 512 | {12, 12, 12, 4, 4, 4, 8, 8, 8, 12, 12, 12, 16, 16, 16, 20, 20, 20, 24, 24, 24, 28, 28, 28, 36, 36, 36, 2, 2, 2, 2, 2, 2, 2, 2, 2, 26, 26, 26, 0}, 513 | {6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 8, 8, 8, 10, 10, 10, 14, 14, 14, 18, 18, 18, 26, 26, 26, 32, 32, 32, 42, 42, 42, 18, 18, 18, 0}, 514 | {6, 6, 6, 6, 6, 6, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 24, 24, 24, 32, 32, 32, 44, 44, 44, 12, 12, 12, 0}, 515 | {6, 6, 6, 6, 6, 6, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 24, 24, 24, 30, 30, 30, 40, 40, 40, 18, 18, 18, 0}, 516 | {4, 4, 4, 4, 4, 4, 6, 6, 4, 4, 4, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 12, 14, 14, 14, 18, 18, 18, 22, 22, 22, 30, 30, 30, 56, 56, 56, 0}, 517 | {4, 4, 4, 4, 4, 4, 6, 6, 4, 4, 4, 6, 6, 6, 6, 6, 6, 10, 10, 10, 12, 12, 12, 14, 14, 14, 16, 16, 16, 20, 20, 20, 26, 26, 26, 66, 66, 66, 0}, 518 | {4, 4, 4, 4, 4, 4, 6, 6, 4, 4, 4, 6, 6, 6, 8, 8, 8, 12, 12, 12, 16, 16, 16, 20, 20, 20, 26, 26, 26, 34, 34, 34, 42, 42, 42, 12, 12, 12, 0}}; 519 | 520 | unsigned tables, scfsi = 0; 521 | int main_data_begin, part_23_sum = 0; 522 | int sr_idx = HDR_GET_MY_SAMPLE_RATE(hdr); 523 | sr_idx -= (sr_idx != 0); 524 | int gr_count = HDR_IS_MONO(hdr) ? 1 : 2; 525 | 526 | if (HDR_TEST_MPEG1(hdr)) 527 | { 528 | gr_count *= 2; 529 | main_data_begin = get_bits(bs, 9); 530 | scfsi = get_bits(bs, 7 + gr_count); 531 | } 532 | else 533 | { 534 | main_data_begin = get_bits(bs, 8 + gr_count) >> gr_count; 535 | } 536 | 537 | do 538 | { 539 | if (HDR_IS_MONO(hdr)) 540 | { 541 | scfsi <<= 4; 542 | } 543 | gr->part_23_length = (uint16_t)get_bits(bs, 12); 544 | part_23_sum += gr->part_23_length; 545 | gr->big_values = (uint16_t)get_bits(bs, 9); 546 | if (gr->big_values > 288) 547 | { 548 | return -1; 549 | } 550 | gr->global_gain = (uint8_t)get_bits(bs, 8); 551 | gr->scalefac_compress = (uint16_t)get_bits(bs, HDR_TEST_MPEG1(hdr) ? 4 : 9); 552 | gr->sfbtab = g_scf_long[sr_idx]; 553 | gr->n_long_sfb = 22; 554 | gr->n_short_sfb = 0; 555 | if (get_bits(bs, 1)) 556 | { 557 | gr->block_type = (uint8_t)get_bits(bs, 2); 558 | if (!gr->block_type) 559 | { 560 | return -1; 561 | } 562 | gr->mixed_block_flag = (uint8_t)get_bits(bs, 1); 563 | gr->region_count[0] = 7; 564 | gr->region_count[1] = 255; 565 | if (gr->block_type == SHORT_BLOCK_TYPE) 566 | { 567 | scfsi &= 0x0F0F; 568 | if (!gr->mixed_block_flag) 569 | { 570 | gr->region_count[0] = 8; 571 | gr->sfbtab = g_scf_short[sr_idx]; 572 | gr->n_long_sfb = 0; 573 | gr->n_short_sfb = 39; 574 | } 575 | else 576 | { 577 | gr->sfbtab = g_scf_mixed[sr_idx]; 578 | gr->n_long_sfb = HDR_TEST_MPEG1(hdr) ? 8 : 6; 579 | gr->n_short_sfb = 30; 580 | } 581 | } 582 | tables = get_bits(bs, 10); 583 | tables <<= 5; 584 | gr->subblock_gain[0] = (uint8_t)get_bits(bs, 3); 585 | gr->subblock_gain[1] = (uint8_t)get_bits(bs, 3); 586 | gr->subblock_gain[2] = (uint8_t)get_bits(bs, 3); 587 | } 588 | else 589 | { 590 | gr->block_type = 0; 591 | gr->mixed_block_flag = 0; 592 | tables = get_bits(bs, 15); 593 | gr->region_count[0] = (uint8_t)get_bits(bs, 4); 594 | gr->region_count[1] = (uint8_t)get_bits(bs, 3); 595 | gr->region_count[2] = 255; 596 | } 597 | gr->table_select[0] = (uint8_t)(tables >> 10); 598 | gr->table_select[1] = (uint8_t)((tables >> 5) & 31); 599 | gr->table_select[2] = (uint8_t)((tables)&31); 600 | gr->preflag = HDR_TEST_MPEG1(hdr) ? get_bits(bs, 1) : (gr->scalefac_compress >= 500); 601 | gr->scalefac_scale = (uint8_t)get_bits(bs, 1); 602 | gr->count1_table = (uint8_t)get_bits(bs, 1); 603 | gr->scfsi = (uint8_t)((scfsi >> 12) & 15); 604 | scfsi <<= 4; 605 | gr++; 606 | } while (--gr_count); 607 | 608 | if (part_23_sum + bs->pos > bs->limit + main_data_begin * 8) 609 | { 610 | return -1; 611 | } 612 | 613 | return main_data_begin; 614 | } 615 | 616 | static void L3_read_scalefactors(uint8_t *scf, uint8_t *ist_pos, const uint8_t *scf_size, const uint8_t *scf_count, bs_t *bitbuf, int scfsi) 617 | { 618 | int i, k; 619 | for (i = 0; i < 4 && scf_count[i]; i++, scfsi *= 2) 620 | { 621 | int cnt = scf_count[i]; 622 | if (scfsi & 8) 623 | { 624 | memcpy(scf, ist_pos, cnt); 625 | } 626 | else 627 | { 628 | int bits = scf_size[i]; 629 | if (!bits) 630 | { 631 | memset(scf, 0, cnt); 632 | memset(ist_pos, 0, cnt); 633 | } 634 | else 635 | { 636 | int max_scf = (scfsi < 0) ? (1 << bits) - 1 : -1; 637 | for (k = 0; k < cnt; k++) 638 | { 639 | int s = get_bits(bitbuf, bits); 640 | ist_pos[k] = (s == max_scf ? -1 : s); 641 | scf[k] = s; 642 | } 643 | } 644 | } 645 | ist_pos += cnt; 646 | scf += cnt; 647 | } 648 | scf[0] = scf[1] = scf[2] = 0; 649 | } 650 | 651 | static float L3_ldexp_q2(float y, int exp_q2) 652 | { 653 | static const float g_expfrac[4] = {9.31322575e-10f, 7.83145814e-10f, 6.58544508e-10f, 5.53767716e-10f}; 654 | int e; 655 | do 656 | { 657 | e = MINIMP3_MIN(30 * 4, exp_q2); 658 | y *= g_expfrac[e & 3] * (1 << 30 >> (e >> 2)); 659 | } while ((exp_q2 -= e) > 0); 660 | return y; 661 | } 662 | 663 | static void L3_decode_scalefactors(const uint8_t *hdr, uint8_t *ist_pos, bs_t *bs, const L3_gr_info_t *gr, float *scf, int ch) 664 | { 665 | static const uint8_t g_scf_partitions[3][28] = { 666 | {6, 5, 5, 5, 6, 5, 5, 5, 6, 5, 7, 3, 11, 10, 0, 0, 7, 7, 7, 0, 6, 6, 6, 3, 8, 8, 5, 0}, 667 | {8, 9, 6, 12, 6, 9, 9, 9, 6, 9, 12, 6, 15, 18, 0, 0, 6, 15, 12, 0, 6, 12, 9, 6, 6, 18, 9, 0}, 668 | {9, 9, 6, 12, 9, 9, 9, 9, 9, 9, 12, 6, 18, 18, 0, 0, 12, 12, 12, 0, 12, 9, 9, 6, 15, 12, 9, 0}}; 669 | const uint8_t *scf_partition = g_scf_partitions[!!gr->n_short_sfb + !gr->n_long_sfb]; 670 | uint8_t scf_size[4], iscf[40]; 671 | int i, scf_shift = gr->scalefac_scale + 1, gain_exp, scfsi = gr->scfsi; 672 | float gain; 673 | 674 | if (HDR_TEST_MPEG1(hdr)) 675 | { 676 | static const uint8_t g_scfc_decode[16] = {0, 1, 2, 3, 12, 5, 6, 7, 9, 10, 11, 13, 14, 15, 18, 19}; 677 | int part = g_scfc_decode[gr->scalefac_compress]; 678 | scf_size[1] = scf_size[0] = (uint8_t)(part >> 2); 679 | scf_size[3] = scf_size[2] = (uint8_t)(part & 3); 680 | } 681 | else 682 | { 683 | static const uint8_t g_mod[6 * 4] = {5, 5, 4, 4, 5, 5, 4, 1, 4, 3, 1, 1, 5, 6, 6, 1, 4, 4, 4, 1, 4, 3, 1, 1}; 684 | int k, modprod, sfc, ist = HDR_TEST_I_STEREO(hdr) && ch; 685 | sfc = gr->scalefac_compress >> ist; 686 | for (k = ist * 3 * 4; sfc >= 0; sfc -= modprod, k += 4) 687 | { 688 | for (modprod = 1, i = 3; i >= 0; i--) 689 | { 690 | scf_size[i] = (uint8_t)(sfc / modprod % g_mod[k + i]); 691 | modprod *= g_mod[k + i]; 692 | } 693 | } 694 | scf_partition += k; 695 | scfsi = -16; 696 | } 697 | L3_read_scalefactors(iscf, ist_pos, scf_size, scf_partition, bs, scfsi); 698 | 699 | if (gr->n_short_sfb) 700 | { 701 | int sh = 3 - scf_shift; 702 | for (i = 0; i < gr->n_short_sfb; i += 3) 703 | { 704 | iscf[gr->n_long_sfb + i + 0] += gr->subblock_gain[0] << sh; 705 | iscf[gr->n_long_sfb + i + 1] += gr->subblock_gain[1] << sh; 706 | iscf[gr->n_long_sfb + i + 2] += gr->subblock_gain[2] << sh; 707 | } 708 | } 709 | else if (gr->preflag) 710 | { 711 | static const uint8_t g_preamp[10] = {1, 1, 1, 1, 2, 2, 3, 3, 3, 2}; 712 | for (i = 0; i < 10; i++) 713 | { 714 | iscf[11 + i] += g_preamp[i]; 715 | } 716 | } 717 | 718 | gain_exp = gr->global_gain + BITS_DEQUANTIZER_OUT * 4 - 210 - (HDR_IS_MS_STEREO(hdr) ? 2 : 0); 719 | gain = L3_ldexp_q2(1 << (MAX_SCFI / 4), MAX_SCFI - gain_exp); 720 | for (i = 0; i < (int)(gr->n_long_sfb + gr->n_short_sfb); i++) 721 | { 722 | scf[i] = L3_ldexp_q2(gain, iscf[i] << scf_shift); 723 | } 724 | } 725 | 726 | static const float g_pow43[129 + 16] = { 727 | 0, -1, -2.519842f, -4.326749f, -6.349604f, -8.549880f, -10.902724f, -13.390518f, -16.000000f, -18.720754f, -21.544347f, -24.463781f, -27.473142f, -30.567351f, -33.741992f, -36.993181f, 728 | 0, 1, 2.519842f, 4.326749f, 6.349604f, 8.549880f, 10.902724f, 13.390518f, 16.000000f, 18.720754f, 21.544347f, 24.463781f, 27.473142f, 30.567351f, 33.741992f, 36.993181f, 40.317474f, 43.711787f, 47.173345f, 50.699631f, 54.288352f, 57.937408f, 61.644865f, 65.408941f, 69.227979f, 73.100443f, 77.024898f, 81.000000f, 85.024491f, 89.097188f, 93.216975f, 97.382800f, 101.593667f, 105.848633f, 110.146801f, 114.487321f, 118.869381f, 123.292209f, 127.755065f, 132.257246f, 136.798076f, 141.376907f, 145.993119f, 150.646117f, 155.335327f, 160.060199f, 164.820202f, 169.614826f, 174.443577f, 179.305980f, 184.201575f, 189.129918f, 194.090580f, 199.083145f, 204.107210f, 209.162385f, 214.248292f, 219.364564f, 224.510845f, 229.686789f, 234.892058f, 240.126328f, 245.389280f, 250.680604f, 256.000000f, 261.347174f, 266.721841f, 272.123723f, 277.552547f, 283.008049f, 288.489971f, 293.998060f, 299.532071f, 305.091761f, 310.676898f, 316.287249f, 321.922592f, 327.582707f, 333.267377f, 338.976394f, 344.709550f, 350.466646f, 356.247482f, 362.051866f, 367.879608f, 373.730522f, 379.604427f, 385.501143f, 391.420496f, 397.362314f, 403.326427f, 409.312672f, 415.320884f, 421.350905f, 427.402579f, 433.475750f, 439.570269f, 445.685987f, 451.822757f, 457.980436f, 464.158883f, 470.357960f, 476.577530f, 482.817459f, 489.077615f, 495.357868f, 501.658090f, 507.978156f, 514.317941f, 520.677324f, 527.056184f, 533.454404f, 539.871867f, 546.308458f, 552.764065f, 559.238575f, 565.731879f, 572.243870f, 578.774440f, 585.323483f, 591.890898f, 598.476581f, 605.080431f, 611.702349f, 618.342238f, 625.000000f, 631.675540f, 638.368763f, 645.079578f}; 729 | 730 | static float L3_pow_43(int x) 731 | { 732 | float frac; 733 | int sign, mult = 256; 734 | 735 | if (x < 129) 736 | { 737 | return g_pow43[16 + x]; 738 | } 739 | 740 | if (x < 1024) 741 | { 742 | mult = 16; 743 | x <<= 3; 744 | } 745 | 746 | sign = 2 * x & 64; 747 | frac = (float)((x & 63) - sign) / ((x & ~63) + sign); 748 | return g_pow43[16 + ((x + sign) >> 6)] * (1.f + frac * ((4.f / 3) + frac * (2.f / 9))) * mult; 749 | } 750 | 751 | static void L3_huffman(float *dst, bs_t *bs, const L3_gr_info_t *gr_info, const float *scf, int layer3gr_limit) 752 | { 753 | static const int16_t tabs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 754 | 785, 785, 785, 785, 784, 784, 784, 784, 513, 513, 513, 513, 513, 513, 513, 513, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 755 | -255, 1313, 1298, 1282, 785, 785, 785, 785, 784, 784, 784, 784, 769, 769, 769, 769, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 290, 288, 756 | -255, 1313, 1298, 1282, 769, 769, 769, 769, 529, 529, 529, 529, 529, 529, 529, 529, 528, 528, 528, 528, 528, 528, 528, 528, 512, 512, 512, 512, 512, 512, 512, 512, 290, 288, 757 | -253, -318, -351, -367, 785, 785, 785, 785, 784, 784, 784, 784, 769, 769, 769, 769, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 819, 818, 547, 547, 275, 275, 275, 275, 561, 560, 515, 546, 289, 274, 288, 258, 758 | -254, -287, 1329, 1299, 1314, 1312, 1057, 1057, 1042, 1042, 1026, 1026, 784, 784, 784, 784, 529, 529, 529, 529, 529, 529, 529, 529, 769, 769, 769, 769, 768, 768, 768, 768, 563, 560, 306, 306, 291, 259, 759 | -252, -413, -477, -542, 1298, -575, 1041, 1041, 784, 784, 784, 784, 769, 769, 769, 769, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, -383, -399, 1107, 1092, 1106, 1061, 849, 849, 789, 789, 1104, 1091, 773, 773, 1076, 1075, 341, 340, 325, 309, 834, 804, 577, 577, 532, 532, 516, 516, 832, 818, 803, 816, 561, 561, 531, 531, 515, 546, 289, 289, 288, 258, 760 | -252, -429, -493, -559, 1057, 1057, 1042, 1042, 529, 529, 529, 529, 529, 529, 529, 529, 784, 784, 784, 784, 769, 769, 769, 769, 512, 512, 512, 512, 512, 512, 512, 512, -382, 1077, -415, 1106, 1061, 1104, 849, 849, 789, 789, 1091, 1076, 1029, 1075, 834, 834, 597, 581, 340, 340, 339, 324, 804, 833, 532, 532, 832, 772, 818, 803, 817, 787, 816, 771, 290, 290, 290, 290, 288, 258, 761 | -253, -349, -414, -447, -463, 1329, 1299, -479, 1314, 1312, 1057, 1057, 1042, 1042, 1026, 1026, 785, 785, 785, 785, 784, 784, 784, 784, 769, 769, 769, 769, 768, 768, 768, 768, -319, 851, 821, -335, 836, 850, 805, 849, 341, 340, 325, 336, 533, 533, 579, 579, 564, 564, 773, 832, 578, 548, 563, 516, 321, 276, 306, 291, 304, 259, 762 | -251, -572, -733, -830, -863, -879, 1041, 1041, 784, 784, 784, 784, 769, 769, 769, 769, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, -511, -527, -543, 1396, 1351, 1381, 1366, 1395, 1335, 1380, -559, 1334, 1138, 1138, 1063, 1063, 1350, 1392, 1031, 1031, 1062, 1062, 1364, 1363, 1120, 1120, 1333, 1348, 881, 881, 881, 881, 375, 374, 359, 373, 343, 358, 341, 325, 791, 791, 1123, 1122, -703, 1105, 1045, -719, 865, 865, 790, 790, 774, 774, 1104, 1029, 338, 293, 323, 308, -799, -815, 833, 788, 772, 818, 803, 816, 322, 292, 307, 320, 561, 531, 515, 546, 289, 274, 288, 258, 763 | -251, -525, -605, -685, -765, -831, -846, 1298, 1057, 1057, 1312, 1282, 785, 785, 785, 785, 784, 784, 784, 784, 769, 769, 769, 769, 512, 512, 512, 512, 512, 512, 512, 512, 1399, 1398, 1383, 1367, 1382, 1396, 1351, -511, 1381, 1366, 1139, 1139, 1079, 1079, 1124, 1124, 1364, 1349, 1363, 1333, 882, 882, 882, 882, 807, 807, 807, 807, 1094, 1094, 1136, 1136, 373, 341, 535, 535, 881, 775, 867, 822, 774, -591, 324, 338, -671, 849, 550, 550, 866, 864, 609, 609, 293, 336, 534, 534, 789, 835, 773, -751, 834, 804, 308, 307, 833, 788, 832, 772, 562, 562, 547, 547, 305, 275, 560, 515, 290, 290, 764 | -252, -397, -477, -557, -622, -653, -719, -735, -750, 1329, 1299, 1314, 1057, 1057, 1042, 1042, 1312, 1282, 1024, 1024, 785, 785, 785, 785, 784, 784, 784, 784, 769, 769, 769, 769, -383, 1127, 1141, 1111, 1126, 1140, 1095, 1110, 869, 869, 883, 883, 1079, 1109, 882, 882, 375, 374, 807, 868, 838, 881, 791, -463, 867, 822, 368, 263, 852, 837, 836, -543, 610, 610, 550, 550, 352, 336, 534, 534, 865, 774, 851, 821, 850, 805, 593, 533, 579, 564, 773, 832, 578, 578, 548, 548, 577, 577, 307, 276, 306, 291, 516, 560, 259, 259, 765 | -250, -2107, -2507, -2764, -2909, -2974, -3007, -3023, 1041, 1041, 1040, 1040, 769, 769, 769, 769, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, -767, -1052, -1213, -1277, -1358, -1405, -1469, -1535, -1550, -1582, -1614, -1647, -1662, -1694, -1726, -1759, -1774, -1807, -1822, -1854, -1886, 1565, -1919, -1935, -1951, -1967, 1731, 1730, 1580, 1717, -1983, 1729, 1564, -1999, 1548, -2015, -2031, 1715, 1595, -2047, 1714, -2063, 1610, -2079, 1609, -2095, 1323, 1323, 1457, 1457, 1307, 1307, 1712, 1547, 1641, 1700, 1699, 1594, 1685, 1625, 1442, 1442, 1322, 1322, -780, -973, -910, 1279, 1278, 1277, 1262, 1276, 1261, 1275, 1215, 1260, 1229, -959, 974, 974, 989, 989, -943, 735, 478, 478, 495, 463, 506, 414, -1039, 1003, 958, 1017, 927, 942, 987, 957, 431, 476, 1272, 1167, 1228, -1183, 1256, -1199, 895, 895, 941, 941, 1242, 1227, 1212, 1135, 1014, 1014, 490, 489, 503, 487, 910, 1013, 985, 925, 863, 894, 970, 955, 1012, 847, -1343, 831, 755, 755, 984, 909, 428, 366, 754, 559, -1391, 752, 486, 457, 924, 997, 698, 698, 983, 893, 740, 740, 908, 877, 739, 739, 667, 667, 953, 938, 497, 287, 271, 271, 683, 606, 590, 712, 726, 574, 302, 302, 738, 736, 481, 286, 526, 725, 605, 711, 636, 724, 696, 651, 589, 681, 666, 710, 364, 467, 573, 695, 466, 466, 301, 465, 379, 379, 709, 604, 665, 679, 316, 316, 634, 633, 436, 436, 464, 269, 424, 394, 452, 332, 438, 363, 347, 408, 393, 448, 331, 422, 362, 407, 392, 421, 346, 406, 391, 376, 375, 359, 1441, 1306, -2367, 1290, -2383, 1337, -2399, -2415, 1426, 1321, -2431, 1411, 1336, -2447, -2463, -2479, 1169, 1169, 1049, 1049, 1424, 1289, 1412, 1352, 1319, -2495, 1154, 1154, 1064, 1064, 1153, 1153, 416, 390, 360, 404, 403, 389, 344, 374, 373, 343, 358, 372, 327, 357, 342, 311, 356, 326, 1395, 1394, 1137, 1137, 1047, 1047, 1365, 1392, 1287, 1379, 1334, 1364, 1349, 1378, 1318, 1363, 792, 792, 792, 792, 1152, 1152, 1032, 1032, 1121, 1121, 1046, 1046, 1120, 1120, 1030, 1030, -2895, 1106, 1061, 1104, 849, 849, 789, 789, 1091, 1076, 1029, 1090, 1060, 1075, 833, 833, 309, 324, 532, 532, 832, 772, 818, 803, 561, 561, 531, 560, 515, 546, 289, 274, 288, 258, 766 | -250, -1179, -1579, -1836, -1996, -2124, -2253, -2333, -2413, -2477, -2542, -2574, -2607, -2622, -2655, 1314, 1313, 1298, 1312, 1282, 785, 785, 785, 785, 1040, 1040, 1025, 1025, 768, 768, 768, 768, -766, -798, -830, -862, -895, -911, -927, -943, -959, -975, -991, -1007, -1023, -1039, -1055, -1070, 1724, 1647, -1103, -1119, 1631, 1767, 1662, 1738, 1708, 1723, -1135, 1780, 1615, 1779, 1599, 1677, 1646, 1778, 1583, -1151, 1777, 1567, 1737, 1692, 1765, 1722, 1707, 1630, 1751, 1661, 1764, 1614, 1736, 1676, 1763, 1750, 1645, 1598, 1721, 1691, 1762, 1706, 1582, 1761, 1566, -1167, 1749, 1629, 767, 766, 751, 765, 494, 494, 735, 764, 719, 749, 734, 763, 447, 447, 748, 718, 477, 506, 431, 491, 446, 476, 461, 505, 415, 430, 475, 445, 504, 399, 460, 489, 414, 503, 383, 474, 429, 459, 502, 502, 746, 752, 488, 398, 501, 473, 413, 472, 486, 271, 480, 270, -1439, -1455, 1357, -1471, -1487, -1503, 1341, 1325, -1519, 1489, 1463, 1403, 1309, -1535, 1372, 1448, 1418, 1476, 1356, 1462, 1387, -1551, 1475, 1340, 1447, 1402, 1386, -1567, 1068, 1068, 1474, 1461, 455, 380, 468, 440, 395, 425, 410, 454, 364, 467, 466, 464, 453, 269, 409, 448, 268, 432, 1371, 1473, 1432, 1417, 1308, 1460, 1355, 1446, 1459, 1431, 1083, 1083, 1401, 1416, 1458, 1445, 1067, 1067, 1370, 1457, 1051, 1051, 1291, 1430, 1385, 1444, 1354, 1415, 1400, 1443, 1082, 1082, 1173, 1113, 1186, 1066, 1185, 1050, -1967, 1158, 1128, 1172, 1097, 1171, 1081, -1983, 1157, 1112, 416, 266, 375, 400, 1170, 1142, 1127, 1065, 793, 793, 1169, 1033, 1156, 1096, 1141, 1111, 1155, 1080, 1126, 1140, 898, 898, 808, 808, 897, 897, 792, 792, 1095, 1152, 1032, 1125, 1110, 1139, 1079, 1124, 882, 807, 838, 881, 853, 791, -2319, 867, 368, 263, 822, 852, 837, 866, 806, 865, -2399, 851, 352, 262, 534, 534, 821, 836, 594, 594, 549, 549, 593, 593, 533, 533, 848, 773, 579, 579, 564, 578, 548, 563, 276, 276, 577, 576, 306, 291, 516, 560, 305, 305, 275, 259, 767 | -251, -892, -2058, -2620, -2828, -2957, -3023, -3039, 1041, 1041, 1040, 1040, 769, 769, 769, 769, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, -511, -527, -543, -559, 1530, -575, -591, 1528, 1527, 1407, 1526, 1391, 1023, 1023, 1023, 1023, 1525, 1375, 1268, 1268, 1103, 1103, 1087, 1087, 1039, 1039, 1523, -604, 815, 815, 815, 815, 510, 495, 509, 479, 508, 463, 507, 447, 431, 505, 415, 399, -734, -782, 1262, -815, 1259, 1244, -831, 1258, 1228, -847, -863, 1196, -879, 1253, 987, 987, 748, -767, 493, 493, 462, 477, 414, 414, 686, 669, 478, 446, 461, 445, 474, 429, 487, 458, 412, 471, 1266, 1264, 1009, 1009, 799, 799, -1019, -1276, -1452, -1581, -1677, -1757, -1821, -1886, -1933, -1997, 1257, 1257, 1483, 1468, 1512, 1422, 1497, 1406, 1467, 1496, 1421, 1510, 1134, 1134, 1225, 1225, 1466, 1451, 1374, 1405, 1252, 1252, 1358, 1480, 1164, 1164, 1251, 1251, 1238, 1238, 1389, 1465, -1407, 1054, 1101, -1423, 1207, -1439, 830, 830, 1248, 1038, 1237, 1117, 1223, 1148, 1236, 1208, 411, 426, 395, 410, 379, 269, 1193, 1222, 1132, 1235, 1221, 1116, 976, 976, 1192, 1162, 1177, 1220, 1131, 1191, 963, 963, -1647, 961, 780, -1663, 558, 558, 994, 993, 437, 408, 393, 407, 829, 978, 813, 797, 947, -1743, 721, 721, 377, 392, 844, 950, 828, 890, 706, 706, 812, 859, 796, 960, 948, 843, 934, 874, 571, 571, -1919, 690, 555, 689, 421, 346, 539, 539, 944, 779, 918, 873, 932, 842, 903, 888, 570, 570, 931, 917, 674, 674, -2575, 1562, -2591, 1609, -2607, 1654, 1322, 1322, 1441, 1441, 1696, 1546, 1683, 1593, 1669, 1624, 1426, 1426, 1321, 1321, 1639, 1680, 1425, 1425, 1305, 1305, 1545, 1668, 1608, 1623, 1667, 1592, 1638, 1666, 1320, 1320, 1652, 1607, 1409, 1409, 1304, 1304, 1288, 1288, 1664, 1637, 1395, 1395, 1335, 1335, 1622, 1636, 1394, 1394, 1319, 1319, 1606, 1621, 1392, 1392, 1137, 1137, 1137, 1137, 345, 390, 360, 375, 404, 373, 1047, -2751, -2767, -2783, 1062, 1121, 1046, -2799, 1077, -2815, 1106, 1061, 789, 789, 1105, 1104, 263, 355, 310, 340, 325, 354, 352, 262, 339, 324, 1091, 1076, 1029, 1090, 1060, 1075, 833, 833, 788, 788, 1088, 1028, 818, 818, 803, 803, 561, 561, 531, 531, 816, 771, 546, 546, 289, 274, 288, 258, 768 | -253, -317, -381, -446, -478, -509, 1279, 1279, -811, -1179, -1451, -1756, -1900, -2028, -2189, -2253, -2333, -2414, -2445, -2511, -2526, 1313, 1298, -2559, 1041, 1041, 1040, 1040, 1025, 1025, 1024, 1024, 1022, 1007, 1021, 991, 1020, 975, 1019, 959, 687, 687, 1018, 1017, 671, 671, 655, 655, 1016, 1015, 639, 639, 758, 758, 623, 623, 757, 607, 756, 591, 755, 575, 754, 559, 543, 543, 1009, 783, -575, -621, -685, -749, 496, -590, 750, 749, 734, 748, 974, 989, 1003, 958, 988, 973, 1002, 942, 987, 957, 972, 1001, 926, 986, 941, 971, 956, 1000, 910, 985, 925, 999, 894, 970, -1071, -1087, -1102, 1390, -1135, 1436, 1509, 1451, 1374, -1151, 1405, 1358, 1480, 1420, -1167, 1507, 1494, 1389, 1342, 1465, 1435, 1450, 1326, 1505, 1310, 1493, 1373, 1479, 1404, 1492, 1464, 1419, 428, 443, 472, 397, 736, 526, 464, 464, 486, 457, 442, 471, 484, 482, 1357, 1449, 1434, 1478, 1388, 1491, 1341, 1490, 1325, 1489, 1463, 1403, 1309, 1477, 1372, 1448, 1418, 1433, 1476, 1356, 1462, 1387, -1439, 1475, 1340, 1447, 1402, 1474, 1324, 1461, 1371, 1473, 269, 448, 1432, 1417, 1308, 1460, -1711, 1459, -1727, 1441, 1099, 1099, 1446, 1386, 1431, 1401, -1743, 1289, 1083, 1083, 1160, 1160, 1458, 1445, 1067, 1067, 1370, 1457, 1307, 1430, 1129, 1129, 1098, 1098, 268, 432, 267, 416, 266, 400, -1887, 1144, 1187, 1082, 1173, 1113, 1186, 1066, 1050, 1158, 1128, 1143, 1172, 1097, 1171, 1081, 420, 391, 1157, 1112, 1170, 1142, 1127, 1065, 1169, 1049, 1156, 1096, 1141, 1111, 1155, 1080, 1126, 1154, 1064, 1153, 1140, 1095, 1048, -2159, 1125, 1110, 1137, -2175, 823, 823, 1139, 1138, 807, 807, 384, 264, 368, 263, 868, 838, 853, 791, 867, 822, 852, 837, 866, 806, 865, 790, -2319, 851, 821, 836, 352, 262, 850, 805, 849, -2399, 533, 533, 835, 820, 336, 261, 578, 548, 563, 577, 532, 532, 832, 772, 562, 562, 547, 547, 305, 275, 560, 515, 290, 290, 288, 258}; 769 | static const uint8_t tab32[] = {130, 162, 193, 209, 44, 28, 76, 140, 9, 9, 9, 9, 9, 9, 9, 9, 190, 254, 222, 238, 126, 94, 157, 157, 109, 61, 173, 205}; 770 | static const uint8_t tab33[] = {252, 236, 220, 204, 188, 172, 156, 140, 124, 108, 92, 76, 60, 44, 28, 12}; 771 | static const int16_t tabindex[2 * 16] = {0, 32, 64, 98, 0, 132, 180, 218, 292, 364, 426, 538, 648, 746, 0, 1126, 1460, 1460, 1460, 1460, 1460, 1460, 1460, 1460, 1842, 1842, 1842, 1842, 1842, 1842, 1842, 1842}; 772 | static const uint8_t g_linbits[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 8, 10, 13, 4, 5, 6, 7, 8, 9, 11, 13}; 773 | 774 | #define PEEK_BITS(n) (bs_cache >> (32 - n)) 775 | #define FLUSH_BITS(n) \ 776 | { \ 777 | bs_cache <<= (n); \ 778 | bs_sh += (n); \ 779 | } 780 | #define CHECK_BITS \ 781 | while (bs_sh >= 0) \ 782 | { \ 783 | bs_cache |= (uint32_t)*bs_next_ptr++ << bs_sh; \ 784 | bs_sh -= 8; \ 785 | } 786 | #define BSPOS ((bs_next_ptr - bs->buf) * 8 - 24 + bs_sh) 787 | 788 | float one = 0.0f; 789 | int ireg = 0, big_val_cnt = gr_info->big_values; 790 | const uint8_t *sfb = gr_info->sfbtab; 791 | const uint8_t *bs_next_ptr = bs->buf + bs->pos / 8; 792 | uint32_t bs_cache = (((bs_next_ptr[0] * 256u + bs_next_ptr[1]) * 256u + bs_next_ptr[2]) * 256u + bs_next_ptr[3]) << (bs->pos & 7); 793 | int pairs_to_decode, np, bs_sh = (bs->pos & 7) - 8; 794 | bs_next_ptr += 4; 795 | 796 | while (big_val_cnt > 0) 797 | { 798 | int tab_num = gr_info->table_select[ireg]; 799 | int sfb_cnt = gr_info->region_count[ireg++]; 800 | const int16_t *codebook = tabs + tabindex[tab_num]; 801 | int linbits = g_linbits[tab_num]; 802 | if (linbits) 803 | { 804 | do 805 | { 806 | np = *sfb++ / 2; 807 | pairs_to_decode = MINIMP3_MIN(big_val_cnt, np); 808 | one = *scf++; 809 | do 810 | { 811 | int j, w = 5; 812 | int leaf = codebook[PEEK_BITS(w)]; 813 | while (leaf < 0) 814 | { 815 | FLUSH_BITS(w); 816 | w = leaf & 7; 817 | leaf = codebook[PEEK_BITS(w) - (leaf >> 3)]; 818 | } 819 | FLUSH_BITS(leaf >> 8); 820 | 821 | for (j = 0; j < 2; j++, dst++, leaf >>= 4) 822 | { 823 | int lsb = leaf & 0x0F; 824 | if (lsb == 15) 825 | { 826 | lsb += PEEK_BITS(linbits); 827 | FLUSH_BITS(linbits); 828 | CHECK_BITS; 829 | *dst = one * L3_pow_43(lsb) * ((int32_t)bs_cache < 0 ? -1 : 1); 830 | } 831 | else 832 | { 833 | *dst = g_pow43[16 + lsb - 16 * (bs_cache >> 31)] * one; 834 | } 835 | FLUSH_BITS(lsb ? 1 : 0); 836 | } 837 | CHECK_BITS; 838 | } while (--pairs_to_decode); 839 | } while ((big_val_cnt -= np) > 0 && --sfb_cnt >= 0); 840 | } 841 | else 842 | { 843 | do 844 | { 845 | np = *sfb++ / 2; 846 | pairs_to_decode = MINIMP3_MIN(big_val_cnt, np); 847 | one = *scf++; 848 | do 849 | { 850 | int j, w = 5; 851 | int leaf = codebook[PEEK_BITS(w)]; 852 | while (leaf < 0) 853 | { 854 | FLUSH_BITS(w); 855 | w = leaf & 7; 856 | leaf = codebook[PEEK_BITS(w) - (leaf >> 3)]; 857 | } 858 | FLUSH_BITS(leaf >> 8); 859 | 860 | for (j = 0; j < 2; j++, dst++, leaf >>= 4) 861 | { 862 | int lsb = leaf & 0x0F; 863 | *dst = g_pow43[16 + lsb - 16 * (bs_cache >> 31)] * one; 864 | FLUSH_BITS(lsb ? 1 : 0); 865 | } 866 | CHECK_BITS; 867 | } while (--pairs_to_decode); 868 | } while ((big_val_cnt -= np) > 0 && --sfb_cnt >= 0); 869 | } 870 | } 871 | 872 | for (np = 1 - big_val_cnt;; dst += 4) 873 | { 874 | const uint8_t *codebook_count1 = (gr_info->count1_table) ? tab33 : tab32; 875 | int leaf = codebook_count1[PEEK_BITS(4)]; 876 | if (!(leaf & 8)) 877 | { 878 | leaf = codebook_count1[(leaf >> 3) + (bs_cache << 4 >> (32 - (leaf & 3)))]; 879 | } 880 | FLUSH_BITS(leaf & 7); 881 | if (BSPOS > layer3gr_limit) 882 | { 883 | break; 884 | } 885 | #define RELOAD_SCALEFACTOR \ 886 | if (!--np) \ 887 | { \ 888 | np = *sfb++ / 2; \ 889 | if (!np) \ 890 | break; \ 891 | one = *scf++; \ 892 | } 893 | #define DEQ_COUNT1(s) \ 894 | if (leaf & (128 >> s)) \ 895 | { \ 896 | dst[s] = ((int32_t)bs_cache < 0) ? -one : one; \ 897 | FLUSH_BITS(1) \ 898 | } 899 | RELOAD_SCALEFACTOR; 900 | DEQ_COUNT1(0); 901 | DEQ_COUNT1(1); 902 | RELOAD_SCALEFACTOR; 903 | DEQ_COUNT1(2); 904 | DEQ_COUNT1(3); 905 | CHECK_BITS; 906 | } 907 | 908 | bs->pos = layer3gr_limit; 909 | } 910 | 911 | static void L3_midside_stereo(float *left, int n) 912 | { 913 | int i = 0; 914 | float *right = left + 576; 915 | #if HAVE_SIMD 916 | if (have_simd()) 917 | { 918 | for (; i < n - 3; i += 4) 919 | { 920 | f4 vl = VLD(left + i); 921 | f4 vr = VLD(right + i); 922 | VSTORE(left + i, VADD(vl, vr)); 923 | VSTORE(right + i, VSUB(vl, vr)); 924 | } 925 | #ifdef __GNUC__ 926 | /* Workaround for spurious -Waggressive-loop-optimizations warning from gcc. 927 | * For more info see: https://github.com/lieff/minimp3/issues/88 928 | */ 929 | if (__builtin_constant_p(n % 4 == 0) && n % 4 == 0) 930 | return; 931 | #endif 932 | } 933 | #endif /* HAVE_SIMD */ 934 | for (; i < n; i++) 935 | { 936 | float a = left[i]; 937 | float b = right[i]; 938 | left[i] = a + b; 939 | right[i] = a - b; 940 | } 941 | } 942 | 943 | static void L3_intensity_stereo_band(float *left, int n, float kl, float kr) 944 | { 945 | int i; 946 | for (i = 0; i < n; i++) 947 | { 948 | left[i + 576] = left[i] * kr; 949 | left[i] = left[i] * kl; 950 | } 951 | } 952 | 953 | static void L3_stereo_top_band(const float *right, const uint8_t *sfb, int nbands, int max_band[3]) 954 | { 955 | int i, k; 956 | 957 | max_band[0] = max_band[1] = max_band[2] = -1; 958 | 959 | for (i = 0; i < nbands; i++) 960 | { 961 | for (k = 0; k < sfb[i]; k += 2) 962 | { 963 | if (right[k] != 0 || right[k + 1] != 0) 964 | { 965 | max_band[i % 3] = i; 966 | break; 967 | } 968 | } 969 | right += sfb[i]; 970 | } 971 | } 972 | 973 | static void L3_stereo_process(float *left, const uint8_t *ist_pos, const uint8_t *sfb, const uint8_t *hdr, int max_band[3], int mpeg2_sh) 974 | { 975 | static const float g_pan[7 * 2] = {0, 1, 0.21132487f, 0.78867513f, 0.36602540f, 0.63397460f, 0.5f, 0.5f, 0.63397460f, 0.36602540f, 0.78867513f, 0.21132487f, 1, 0}; 976 | unsigned i, max_pos = HDR_TEST_MPEG1(hdr) ? 7 : 64; 977 | 978 | for (i = 0; sfb[i]; i++) 979 | { 980 | unsigned ipos = ist_pos[i]; 981 | if ((int)i > max_band[i % 3] && ipos < max_pos) 982 | { 983 | float kl, kr, s = HDR_TEST_MS_STEREO(hdr) ? 1.41421356f : 1; 984 | if (HDR_TEST_MPEG1(hdr)) 985 | { 986 | kl = g_pan[2 * ipos]; 987 | kr = g_pan[2 * ipos + 1]; 988 | } 989 | else 990 | { 991 | kl = 1; 992 | kr = L3_ldexp_q2(1, (ipos + 1) >> 1 << mpeg2_sh); 993 | if (ipos & 1) 994 | { 995 | kl = kr; 996 | kr = 1; 997 | } 998 | } 999 | L3_intensity_stereo_band(left, sfb[i], kl * s, kr * s); 1000 | } 1001 | else if (HDR_TEST_MS_STEREO(hdr)) 1002 | { 1003 | L3_midside_stereo(left, sfb[i]); 1004 | } 1005 | left += sfb[i]; 1006 | } 1007 | } 1008 | 1009 | static void L3_intensity_stereo(float *left, uint8_t *ist_pos, const L3_gr_info_t *gr, const uint8_t *hdr) 1010 | { 1011 | int max_band[3], n_sfb = gr->n_long_sfb + gr->n_short_sfb; 1012 | int i, max_blocks = gr->n_short_sfb ? 3 : 1; 1013 | 1014 | L3_stereo_top_band(left + 576, gr->sfbtab, n_sfb, max_band); 1015 | if (gr->n_long_sfb) 1016 | { 1017 | max_band[0] = max_band[1] = max_band[2] = MINIMP3_MAX(MINIMP3_MAX(max_band[0], max_band[1]), max_band[2]); 1018 | } 1019 | for (i = 0; i < max_blocks; i++) 1020 | { 1021 | int default_pos = HDR_TEST_MPEG1(hdr) ? 3 : 0; 1022 | int itop = n_sfb - max_blocks + i; 1023 | int prev = itop - max_blocks; 1024 | ist_pos[itop] = max_band[i] >= prev ? default_pos : ist_pos[prev]; 1025 | } 1026 | L3_stereo_process(left, ist_pos, gr->sfbtab, hdr, max_band, gr[1].scalefac_compress & 1); 1027 | } 1028 | 1029 | static void L3_reorder(float *grbuf, float *scratch, const uint8_t *sfb) 1030 | { 1031 | int i, len; 1032 | float *src = grbuf, *dst = scratch; 1033 | 1034 | for (; 0 != (len = *sfb); sfb += 3, src += 2 * len) 1035 | { 1036 | for (i = 0; i < len; i++, src++) 1037 | { 1038 | *dst++ = src[0 * len]; 1039 | *dst++ = src[1 * len]; 1040 | *dst++ = src[2 * len]; 1041 | } 1042 | } 1043 | memcpy(grbuf, scratch, (dst - scratch) * sizeof(float)); 1044 | } 1045 | 1046 | static void L3_antialias(float *grbuf, int nbands) 1047 | { 1048 | static const float g_aa[2][8] = { 1049 | {0.85749293f, 0.88174200f, 0.94962865f, 0.98331459f, 0.99551782f, 0.99916056f, 0.99989920f, 0.99999316f}, 1050 | {0.51449576f, 0.47173197f, 0.31337745f, 0.18191320f, 0.09457419f, 0.04096558f, 0.01419856f, 0.00369997f}}; 1051 | 1052 | for (; nbands > 0; nbands--, grbuf += 18) 1053 | { 1054 | int i = 0; 1055 | #if HAVE_SIMD 1056 | if (have_simd()) 1057 | for (; i < 8; i += 4) 1058 | { 1059 | f4 vu = VLD(grbuf + 18 + i); 1060 | f4 vd = VLD(grbuf + 14 - i); 1061 | f4 vc0 = VLD(g_aa[0] + i); 1062 | f4 vc1 = VLD(g_aa[1] + i); 1063 | vd = VREV(vd); 1064 | VSTORE(grbuf + 18 + i, VSUB(VMUL(vu, vc0), VMUL(vd, vc1))); 1065 | vd = VADD(VMUL(vu, vc1), VMUL(vd, vc0)); 1066 | VSTORE(grbuf + 14 - i, VREV(vd)); 1067 | } 1068 | #endif /* HAVE_SIMD */ 1069 | #ifndef MINIMP3_ONLY_SIMD 1070 | for (; i < 8; i++) 1071 | { 1072 | float u = grbuf[18 + i]; 1073 | float d = grbuf[17 - i]; 1074 | grbuf[18 + i] = u * g_aa[0][i] - d * g_aa[1][i]; 1075 | grbuf[17 - i] = u * g_aa[1][i] + d * g_aa[0][i]; 1076 | } 1077 | #endif /* MINIMP3_ONLY_SIMD */ 1078 | } 1079 | } 1080 | 1081 | static void L3_dct3_9(float *y) 1082 | { 1083 | float s0, s1, s2, s3, s4, s5, s6, s7, s8, t0, t2, t4; 1084 | 1085 | s0 = y[0]; 1086 | s2 = y[2]; 1087 | s4 = y[4]; 1088 | s6 = y[6]; 1089 | s8 = y[8]; 1090 | t0 = s0 + s6 * 0.5f; 1091 | s0 -= s6; 1092 | t4 = (s4 + s2) * 0.93969262f; 1093 | t2 = (s8 + s2) * 0.76604444f; 1094 | s6 = (s4 - s8) * 0.17364818f; 1095 | s4 += s8 - s2; 1096 | 1097 | s2 = s0 - s4 * 0.5f; 1098 | y[4] = s4 + s0; 1099 | s8 = t0 - t2 + s6; 1100 | s0 = t0 - t4 + t2; 1101 | s4 = t0 + t4 - s6; 1102 | 1103 | s1 = y[1]; 1104 | s3 = y[3]; 1105 | s5 = y[5]; 1106 | s7 = y[7]; 1107 | 1108 | s3 *= 0.86602540f; 1109 | t0 = (s5 + s1) * 0.98480775f; 1110 | t4 = (s5 - s7) * 0.34202014f; 1111 | t2 = (s1 + s7) * 0.64278761f; 1112 | s1 = (s1 - s5 - s7) * 0.86602540f; 1113 | 1114 | s5 = t0 - s3 - t2; 1115 | s7 = t4 - s3 - t0; 1116 | s3 = t4 + s3 - t2; 1117 | 1118 | y[0] = s4 - s7; 1119 | y[1] = s2 + s1; 1120 | y[2] = s0 - s3; 1121 | y[3] = s8 + s5; 1122 | y[5] = s8 - s5; 1123 | y[6] = s0 + s3; 1124 | y[7] = s2 - s1; 1125 | y[8] = s4 + s7; 1126 | } 1127 | 1128 | static void L3_imdct36(float *grbuf, float *overlap, const float *window, int nbands) 1129 | { 1130 | int i, j; 1131 | static const float g_twid9[18] = { 1132 | 0.73727734f, 0.79335334f, 0.84339145f, 0.88701083f, 0.92387953f, 0.95371695f, 0.97629601f, 0.99144486f, 0.99904822f, 0.67559021f, 0.60876143f, 0.53729961f, 0.46174861f, 0.38268343f, 0.30070580f, 0.21643961f, 0.13052619f, 0.04361938f}; 1133 | 1134 | for (j = 0; j < nbands; j++, grbuf += 18, overlap += 9) 1135 | { 1136 | float co[9], si[9]; 1137 | co[0] = -grbuf[0]; 1138 | si[0] = grbuf[17]; 1139 | for (i = 0; i < 4; i++) 1140 | { 1141 | si[8 - 2 * i] = grbuf[4 * i + 1] - grbuf[4 * i + 2]; 1142 | co[1 + 2 * i] = grbuf[4 * i + 1] + grbuf[4 * i + 2]; 1143 | si[7 - 2 * i] = grbuf[4 * i + 4] - grbuf[4 * i + 3]; 1144 | co[2 + 2 * i] = -(grbuf[4 * i + 3] + grbuf[4 * i + 4]); 1145 | } 1146 | L3_dct3_9(co); 1147 | L3_dct3_9(si); 1148 | 1149 | si[1] = -si[1]; 1150 | si[3] = -si[3]; 1151 | si[5] = -si[5]; 1152 | si[7] = -si[7]; 1153 | 1154 | i = 0; 1155 | 1156 | #if HAVE_SIMD 1157 | if (have_simd()) 1158 | for (; i < 8; i += 4) 1159 | { 1160 | f4 vovl = VLD(overlap + i); 1161 | f4 vc = VLD(co + i); 1162 | f4 vs = VLD(si + i); 1163 | f4 vr0 = VLD(g_twid9 + i); 1164 | f4 vr1 = VLD(g_twid9 + 9 + i); 1165 | f4 vw0 = VLD(window + i); 1166 | f4 vw1 = VLD(window + 9 + i); 1167 | f4 vsum = VADD(VMUL(vc, vr1), VMUL(vs, vr0)); 1168 | VSTORE(overlap + i, VSUB(VMUL(vc, vr0), VMUL(vs, vr1))); 1169 | VSTORE(grbuf + i, VSUB(VMUL(vovl, vw0), VMUL(vsum, vw1))); 1170 | vsum = VADD(VMUL(vovl, vw1), VMUL(vsum, vw0)); 1171 | VSTORE(grbuf + 14 - i, VREV(vsum)); 1172 | } 1173 | #endif /* HAVE_SIMD */ 1174 | for (; i < 9; i++) 1175 | { 1176 | float ovl = overlap[i]; 1177 | float sum = co[i] * g_twid9[9 + i] + si[i] * g_twid9[0 + i]; 1178 | overlap[i] = co[i] * g_twid9[0 + i] - si[i] * g_twid9[9 + i]; 1179 | grbuf[i] = ovl * window[0 + i] - sum * window[9 + i]; 1180 | grbuf[17 - i] = ovl * window[9 + i] + sum * window[0 + i]; 1181 | } 1182 | } 1183 | } 1184 | 1185 | static void L3_idct3(float x0, float x1, float x2, float *dst) 1186 | { 1187 | float m1 = x1 * 0.86602540f; 1188 | float a1 = x0 - x2 * 0.5f; 1189 | dst[1] = x0 + x2; 1190 | dst[0] = a1 + m1; 1191 | dst[2] = a1 - m1; 1192 | } 1193 | 1194 | static void L3_imdct12(float *x, float *dst, float *overlap) 1195 | { 1196 | static const float g_twid3[6] = {0.79335334f, 0.92387953f, 0.99144486f, 0.60876143f, 0.38268343f, 0.13052619f}; 1197 | float co[3], si[3]; 1198 | int i; 1199 | 1200 | L3_idct3(-x[0], x[6] + x[3], x[12] + x[9], co); 1201 | L3_idct3(x[15], x[12] - x[9], x[6] - x[3], si); 1202 | si[1] = -si[1]; 1203 | 1204 | for (i = 0; i < 3; i++) 1205 | { 1206 | float ovl = overlap[i]; 1207 | float sum = co[i] * g_twid3[3 + i] + si[i] * g_twid3[0 + i]; 1208 | overlap[i] = co[i] * g_twid3[0 + i] - si[i] * g_twid3[3 + i]; 1209 | dst[i] = ovl * g_twid3[2 - i] - sum * g_twid3[5 - i]; 1210 | dst[5 - i] = ovl * g_twid3[5 - i] + sum * g_twid3[2 - i]; 1211 | } 1212 | } 1213 | 1214 | static void L3_imdct_short(float *grbuf, float *overlap, int nbands) 1215 | { 1216 | for (; nbands > 0; nbands--, overlap += 9, grbuf += 18) 1217 | { 1218 | float tmp[18]; 1219 | memcpy(tmp, grbuf, sizeof(tmp)); 1220 | memcpy(grbuf, overlap, 6 * sizeof(float)); 1221 | L3_imdct12(tmp, grbuf + 6, overlap + 6); 1222 | L3_imdct12(tmp + 1, grbuf + 12, overlap + 6); 1223 | L3_imdct12(tmp + 2, overlap, overlap + 6); 1224 | } 1225 | } 1226 | 1227 | static void L3_change_sign(float *grbuf) 1228 | { 1229 | int b, i; 1230 | for (b = 0, grbuf += 18; b < 32; b += 2, grbuf += 36) 1231 | for (i = 1; i < 18; i += 2) 1232 | grbuf[i] = -grbuf[i]; 1233 | } 1234 | 1235 | static void L3_imdct_gr(float *grbuf, float *overlap, unsigned block_type, unsigned n_long_bands) 1236 | { 1237 | static const float g_mdct_window[2][18] = { 1238 | {0.99904822f, 0.99144486f, 0.97629601f, 0.95371695f, 0.92387953f, 0.88701083f, 0.84339145f, 0.79335334f, 0.73727734f, 0.04361938f, 0.13052619f, 0.21643961f, 0.30070580f, 0.38268343f, 0.46174861f, 0.53729961f, 0.60876143f, 0.67559021f}, 1239 | {1, 1, 1, 1, 1, 1, 0.99144486f, 0.92387953f, 0.79335334f, 0, 0, 0, 0, 0, 0, 0.13052619f, 0.38268343f, 0.60876143f}}; 1240 | if (n_long_bands) 1241 | { 1242 | L3_imdct36(grbuf, overlap, g_mdct_window[0], n_long_bands); 1243 | grbuf += 18 * n_long_bands; 1244 | overlap += 9 * n_long_bands; 1245 | } 1246 | if (block_type == SHORT_BLOCK_TYPE) 1247 | L3_imdct_short(grbuf, overlap, 32 - n_long_bands); 1248 | else 1249 | L3_imdct36(grbuf, overlap, g_mdct_window[block_type == STOP_BLOCK_TYPE], 32 - n_long_bands); 1250 | } 1251 | 1252 | static void L3_save_reservoir(mp3dec_t *h, mp3dec_scratch_t *s) 1253 | { 1254 | int pos = (s->bs.pos + 7) / 8u; 1255 | int remains = s->bs.limit / 8u - pos; 1256 | if (remains > MAX_BITRESERVOIR_BYTES) 1257 | { 1258 | pos += remains - MAX_BITRESERVOIR_BYTES; 1259 | remains = MAX_BITRESERVOIR_BYTES; 1260 | } 1261 | if (remains > 0) 1262 | { 1263 | memmove(h->reserv_buf, s->maindata + pos, remains); 1264 | } 1265 | h->reserv = remains; 1266 | } 1267 | 1268 | static int L3_restore_reservoir(mp3dec_t *h, bs_t *bs, mp3dec_scratch_t *s, int main_data_begin) 1269 | { 1270 | int frame_bytes = (bs->limit - bs->pos) / 8; 1271 | int bytes_have = MINIMP3_MIN(h->reserv, main_data_begin); 1272 | memcpy(s->maindata, h->reserv_buf + MINIMP3_MAX(0, h->reserv - main_data_begin), MINIMP3_MIN(h->reserv, main_data_begin)); 1273 | memcpy(s->maindata + bytes_have, bs->buf + bs->pos / 8, frame_bytes); 1274 | bs_init(&s->bs, s->maindata, bytes_have + frame_bytes); 1275 | return h->reserv >= main_data_begin; 1276 | } 1277 | 1278 | static void L3_decode(mp3dec_t *h, mp3dec_scratch_t *s, L3_gr_info_t *gr_info, int nch) 1279 | { 1280 | int ch; 1281 | 1282 | for (ch = 0; ch < nch; ch++) 1283 | { 1284 | int layer3gr_limit = s->bs.pos + gr_info[ch].part_23_length; 1285 | L3_decode_scalefactors(h->header, s->ist_pos[ch], &s->bs, gr_info + ch, s->scf, ch); 1286 | L3_huffman(s->grbuf[ch], &s->bs, gr_info + ch, s->scf, layer3gr_limit); 1287 | } 1288 | 1289 | if (HDR_TEST_I_STEREO(h->header)) 1290 | { 1291 | L3_intensity_stereo(s->grbuf[0], s->ist_pos[1], gr_info, h->header); 1292 | } 1293 | else if (HDR_IS_MS_STEREO(h->header)) 1294 | { 1295 | L3_midside_stereo(s->grbuf[0], 576); 1296 | } 1297 | 1298 | for (ch = 0; ch < nch; ch++, gr_info++) 1299 | { 1300 | int aa_bands = 31; 1301 | int n_long_bands = (gr_info->mixed_block_flag ? 2 : 0) << (int)(HDR_GET_MY_SAMPLE_RATE(h->header) == 2); 1302 | 1303 | if (gr_info->n_short_sfb) 1304 | { 1305 | aa_bands = n_long_bands - 1; 1306 | L3_reorder(s->grbuf[ch] + n_long_bands * 18, s->syn[0], gr_info->sfbtab + gr_info->n_long_sfb); 1307 | } 1308 | 1309 | L3_antialias(s->grbuf[ch], aa_bands); 1310 | L3_imdct_gr(s->grbuf[ch], h->mdct_overlap[ch], gr_info->block_type, n_long_bands); 1311 | L3_change_sign(s->grbuf[ch]); 1312 | } 1313 | } 1314 | 1315 | static void mp3d_DCT_II(float *grbuf, int n) 1316 | { 1317 | static const float g_sec[24] = { 1318 | 10.19000816f, 0.50060302f, 0.50241929f, 3.40760851f, 0.50547093f, 0.52249861f, 2.05778098f, 0.51544732f, 0.56694406f, 1.48416460f, 0.53104258f, 0.64682180f, 1.16943991f, 0.55310392f, 0.78815460f, 0.97256821f, 0.58293498f, 1.06067765f, 0.83934963f, 0.62250412f, 1.72244716f, 0.74453628f, 0.67480832f, 5.10114861f}; 1319 | int i, k = 0; 1320 | #if HAVE_SIMD 1321 | if (have_simd()) 1322 | for (; k < n; k += 4) 1323 | { 1324 | f4 t[4][8], *x; 1325 | float *y = grbuf + k; 1326 | 1327 | for (x = t[0], i = 0; i < 8; i++, x++) 1328 | { 1329 | f4 x0 = VLD(&y[i * 18]); 1330 | f4 x1 = VLD(&y[(15 - i) * 18]); 1331 | f4 x2 = VLD(&y[(16 + i) * 18]); 1332 | f4 x3 = VLD(&y[(31 - i) * 18]); 1333 | f4 t0 = VADD(x0, x3); 1334 | f4 t1 = VADD(x1, x2); 1335 | f4 t2 = VMUL_S(VSUB(x1, x2), g_sec[3 * i + 0]); 1336 | f4 t3 = VMUL_S(VSUB(x0, x3), g_sec[3 * i + 1]); 1337 | x[0] = VADD(t0, t1); 1338 | x[8] = VMUL_S(VSUB(t0, t1), g_sec[3 * i + 2]); 1339 | x[16] = VADD(t3, t2); 1340 | x[24] = VMUL_S(VSUB(t3, t2), g_sec[3 * i + 2]); 1341 | } 1342 | for (x = t[0], i = 0; i < 4; i++, x += 8) 1343 | { 1344 | f4 x0 = x[0], x1 = x[1], x2 = x[2], x3 = x[3], x4 = x[4], x5 = x[5], x6 = x[6], x7 = x[7], xt; 1345 | xt = VSUB(x0, x7); 1346 | x0 = VADD(x0, x7); 1347 | x7 = VSUB(x1, x6); 1348 | x1 = VADD(x1, x6); 1349 | x6 = VSUB(x2, x5); 1350 | x2 = VADD(x2, x5); 1351 | x5 = VSUB(x3, x4); 1352 | x3 = VADD(x3, x4); 1353 | x4 = VSUB(x0, x3); 1354 | x0 = VADD(x0, x3); 1355 | x3 = VSUB(x1, x2); 1356 | x1 = VADD(x1, x2); 1357 | x[0] = VADD(x0, x1); 1358 | x[4] = VMUL_S(VSUB(x0, x1), 0.70710677f); 1359 | x5 = VADD(x5, x6); 1360 | x6 = VMUL_S(VADD(x6, x7), 0.70710677f); 1361 | x7 = VADD(x7, xt); 1362 | x3 = VMUL_S(VADD(x3, x4), 0.70710677f); 1363 | x5 = VSUB(x5, VMUL_S(x7, 0.198912367f)); /* rotate by PI/8 */ 1364 | x7 = VADD(x7, VMUL_S(x5, 0.382683432f)); 1365 | x5 = VSUB(x5, VMUL_S(x7, 0.198912367f)); 1366 | x0 = VSUB(xt, x6); 1367 | xt = VADD(xt, x6); 1368 | x[1] = VMUL_S(VADD(xt, x7), 0.50979561f); 1369 | x[2] = VMUL_S(VADD(x4, x3), 0.54119611f); 1370 | x[3] = VMUL_S(VSUB(x0, x5), 0.60134488f); 1371 | x[5] = VMUL_S(VADD(x0, x5), 0.89997619f); 1372 | x[6] = VMUL_S(VSUB(x4, x3), 1.30656302f); 1373 | x[7] = VMUL_S(VSUB(xt, x7), 2.56291556f); 1374 | } 1375 | 1376 | if (k > n - 3) 1377 | { 1378 | #if HAVE_SSE 1379 | #define VSAVE2(i, v) _mm_storel_pi((__m64 *)(void *)&y[i * 18], v) 1380 | #else /* HAVE_SSE */ 1381 | #define VSAVE2(i, v) vst1_f32((float32_t *)&y[i * 18], vget_low_f32(v)) 1382 | #endif /* HAVE_SSE */ 1383 | for (i = 0; i < 7; i++, y += 4 * 18) 1384 | { 1385 | f4 s = VADD(t[3][i], t[3][i + 1]); 1386 | VSAVE2(0, t[0][i]); 1387 | VSAVE2(1, VADD(t[2][i], s)); 1388 | VSAVE2(2, VADD(t[1][i], t[1][i + 1])); 1389 | VSAVE2(3, VADD(t[2][1 + i], s)); 1390 | } 1391 | VSAVE2(0, t[0][7]); 1392 | VSAVE2(1, VADD(t[2][7], t[3][7])); 1393 | VSAVE2(2, t[1][7]); 1394 | VSAVE2(3, t[3][7]); 1395 | } 1396 | else 1397 | { 1398 | #define VSAVE4(i, v) VSTORE(&y[i * 18], v) 1399 | for (i = 0; i < 7; i++, y += 4 * 18) 1400 | { 1401 | f4 s = VADD(t[3][i], t[3][i + 1]); 1402 | VSAVE4(0, t[0][i]); 1403 | VSAVE4(1, VADD(t[2][i], s)); 1404 | VSAVE4(2, VADD(t[1][i], t[1][i + 1])); 1405 | VSAVE4(3, VADD(t[2][1 + i], s)); 1406 | } 1407 | VSAVE4(0, t[0][7]); 1408 | VSAVE4(1, VADD(t[2][7], t[3][7])); 1409 | VSAVE4(2, t[1][7]); 1410 | VSAVE4(3, t[3][7]); 1411 | } 1412 | } 1413 | else 1414 | #endif /* HAVE_SIMD */ 1415 | #ifdef MINIMP3_ONLY_SIMD 1416 | { 1417 | } /* for HAVE_SIMD=1, MINIMP3_ONLY_SIMD=1 case we do not need non-intrinsic "else" branch */ 1418 | #else /* MINIMP3_ONLY_SIMD */ 1419 | for (; k < n; k++) 1420 | { 1421 | float t[4][8], *x, *y = grbuf + k; 1422 | 1423 | for (x = t[0], i = 0; i < 8; i++, x++) 1424 | { 1425 | float x0 = y[i * 18]; 1426 | float x1 = y[(15 - i) * 18]; 1427 | float x2 = y[(16 + i) * 18]; 1428 | float x3 = y[(31 - i) * 18]; 1429 | float t0 = x0 + x3; 1430 | float t1 = x1 + x2; 1431 | float t2 = (x1 - x2) * g_sec[3 * i + 0]; 1432 | float t3 = (x0 - x3) * g_sec[3 * i + 1]; 1433 | x[0] = t0 + t1; 1434 | x[8] = (t0 - t1) * g_sec[3 * i + 2]; 1435 | x[16] = t3 + t2; 1436 | x[24] = (t3 - t2) * g_sec[3 * i + 2]; 1437 | } 1438 | for (x = t[0], i = 0; i < 4; i++, x += 8) 1439 | { 1440 | float x0 = x[0], x1 = x[1], x2 = x[2], x3 = x[3], x4 = x[4], x5 = x[5], x6 = x[6], x7 = x[7], xt; 1441 | xt = x0 - x7; 1442 | x0 += x7; 1443 | x7 = x1 - x6; 1444 | x1 += x6; 1445 | x6 = x2 - x5; 1446 | x2 += x5; 1447 | x5 = x3 - x4; 1448 | x3 += x4; 1449 | x4 = x0 - x3; 1450 | x0 += x3; 1451 | x3 = x1 - x2; 1452 | x1 += x2; 1453 | x[0] = x0 + x1; 1454 | x[4] = (x0 - x1) * 0.70710677f; 1455 | x5 = x5 + x6; 1456 | x6 = (x6 + x7) * 0.70710677f; 1457 | x7 = x7 + xt; 1458 | x3 = (x3 + x4) * 0.70710677f; 1459 | x5 -= x7 * 0.198912367f; /* rotate by PI/8 */ 1460 | x7 += x5 * 0.382683432f; 1461 | x5 -= x7 * 0.198912367f; 1462 | x0 = xt - x6; 1463 | xt += x6; 1464 | x[1] = (xt + x7) * 0.50979561f; 1465 | x[2] = (x4 + x3) * 0.54119611f; 1466 | x[3] = (x0 - x5) * 0.60134488f; 1467 | x[5] = (x0 + x5) * 0.89997619f; 1468 | x[6] = (x4 - x3) * 1.30656302f; 1469 | x[7] = (xt - x7) * 2.56291556f; 1470 | } 1471 | for (i = 0; i < 7; i++, y += 4 * 18) 1472 | { 1473 | y[0 * 18] = t[0][i]; 1474 | y[1 * 18] = t[2][i] + t[3][i] + t[3][i + 1]; 1475 | y[2 * 18] = t[1][i] + t[1][i + 1]; 1476 | y[3 * 18] = t[2][i + 1] + t[3][i] + t[3][i + 1]; 1477 | } 1478 | y[0 * 18] = t[0][7]; 1479 | y[1 * 18] = t[2][7] + t[3][7]; 1480 | y[2 * 18] = t[1][7]; 1481 | y[3 * 18] = t[3][7]; 1482 | } 1483 | #endif /* MINIMP3_ONLY_SIMD */ 1484 | } 1485 | 1486 | #ifndef MINIMP3_FLOAT_OUTPUT 1487 | static int16_t mp3d_scale_pcm(float sample) 1488 | { 1489 | #if HAVE_ARMV6 1490 | int32_t s32 = (int32_t)(sample + .5f); 1491 | s32 -= (s32 < 0); 1492 | int16_t s = (int16_t)minimp3_clip_int16_arm(s32); 1493 | #else 1494 | if (sample >= 32766.5) 1495 | return (int16_t)32767; 1496 | if (sample <= -32767.5) 1497 | return (int16_t)-32768; 1498 | int16_t s = (int16_t)(sample + .5f); 1499 | s -= (s < 0); /* away from zero, to be compliant */ 1500 | #endif 1501 | return s; 1502 | } 1503 | #else /* MINIMP3_FLOAT_OUTPUT */ 1504 | static float mp3d_scale_pcm(float sample) 1505 | { 1506 | return sample * (1.f / 32768.f); 1507 | } 1508 | #endif /* MINIMP3_FLOAT_OUTPUT */ 1509 | 1510 | static void mp3d_synth_pair(mp3d_sample_t *pcm, int nch, const float *z) 1511 | { 1512 | float a; 1513 | a = (z[14 * 64] - z[0]) * 29; 1514 | a += (z[1 * 64] + z[13 * 64]) * 213; 1515 | a += (z[12 * 64] - z[2 * 64]) * 459; 1516 | a += (z[3 * 64] + z[11 * 64]) * 2037; 1517 | a += (z[10 * 64] - z[4 * 64]) * 5153; 1518 | a += (z[5 * 64] + z[9 * 64]) * 6574; 1519 | a += (z[8 * 64] - z[6 * 64]) * 37489; 1520 | a += z[7 * 64] * 75038; 1521 | pcm[0] = mp3d_scale_pcm(a); 1522 | 1523 | z += 2; 1524 | a = z[14 * 64] * 104; 1525 | a += z[12 * 64] * 1567; 1526 | a += z[10 * 64] * 9727; 1527 | a += z[8 * 64] * 64019; 1528 | a += z[6 * 64] * -9975; 1529 | a += z[4 * 64] * -45; 1530 | a += z[2 * 64] * 146; 1531 | a += z[0 * 64] * -5; 1532 | pcm[16 * nch] = mp3d_scale_pcm(a); 1533 | } 1534 | 1535 | static void mp3d_synth(float *xl, mp3d_sample_t *dstl, int nch, float *lins) 1536 | { 1537 | int i; 1538 | float *xr = xl + 576 * (nch - 1); 1539 | mp3d_sample_t *dstr = dstl + (nch - 1); 1540 | 1541 | static const float g_win[] = { 1542 | -1, 26, -31, 208, 218, 401, -519, 2063, 2000, 4788, -5517, 7134, 5959, 35640, -39336, 74992, 1543 | -1, 24, -35, 202, 222, 347, -581, 2080, 1952, 4425, -5879, 7640, 5288, 33791, -41176, 74856, 1544 | -1, 21, -38, 196, 225, 294, -645, 2087, 1893, 4063, -6237, 8092, 4561, 31947, -43006, 74630, 1545 | -1, 19, -41, 190, 227, 244, -711, 2085, 1822, 3705, -6589, 8492, 3776, 30112, -44821, 74313, 1546 | -1, 17, -45, 183, 228, 197, -779, 2075, 1739, 3351, -6935, 8840, 2935, 28289, -46617, 73908, 1547 | -1, 16, -49, 176, 228, 153, -848, 2057, 1644, 3004, -7271, 9139, 2037, 26482, -48390, 73415, 1548 | -2, 14, -53, 169, 227, 111, -919, 2032, 1535, 2663, -7597, 9389, 1082, 24694, -50137, 72835, 1549 | -2, 13, -58, 161, 224, 72, -991, 2001, 1414, 2330, -7910, 9592, 70, 22929, -51853, 72169, 1550 | -2, 11, -63, 154, 221, 36, -1064, 1962, 1280, 2006, -8209, 9750, -998, 21189, -53534, 71420, 1551 | -2, 10, -68, 147, 215, 2, -1137, 1919, 1131, 1692, -8491, 9863, -2122, 19478, -55178, 70590, 1552 | -3, 9, -73, 139, 208, -29, -1210, 1870, 970, 1388, -8755, 9935, -3300, 17799, -56778, 69679, 1553 | -3, 8, -79, 132, 200, -57, -1283, 1817, 794, 1095, -8998, 9966, -4533, 16155, -58333, 68692, 1554 | -4, 7, -85, 125, 189, -83, -1356, 1759, 605, 814, -9219, 9959, -5818, 14548, -59838, 67629, 1555 | -4, 7, -91, 117, 177, -106, -1428, 1698, 402, 545, -9416, 9916, -7154, 12980, -61289, 66494, 1556 | -5, 6, -97, 111, 163, -127, -1498, 1634, 185, 288, -9585, 9838, -8540, 11455, -62684, 65290}; 1557 | float *zlin = lins + 15 * 64; 1558 | const float *w = g_win; 1559 | 1560 | zlin[4 * 15] = xl[18 * 16]; 1561 | zlin[4 * 15 + 1] = xr[18 * 16]; 1562 | zlin[4 * 15 + 2] = xl[0]; 1563 | zlin[4 * 15 + 3] = xr[0]; 1564 | 1565 | zlin[4 * 31] = xl[1 + 18 * 16]; 1566 | zlin[4 * 31 + 1] = xr[1 + 18 * 16]; 1567 | zlin[4 * 31 + 2] = xl[1]; 1568 | zlin[4 * 31 + 3] = xr[1]; 1569 | 1570 | mp3d_synth_pair(dstr, nch, lins + 4 * 15 + 1); 1571 | mp3d_synth_pair(dstr + 32 * nch, nch, lins + 4 * 15 + 64 + 1); 1572 | mp3d_synth_pair(dstl, nch, lins + 4 * 15); 1573 | mp3d_synth_pair(dstl + 32 * nch, nch, lins + 4 * 15 + 64); 1574 | 1575 | #if HAVE_SIMD 1576 | if (have_simd()) 1577 | for (i = 14; i >= 0; i--) 1578 | { 1579 | #define VLOAD(k) \ 1580 | f4 w0 = VSET(*w++); \ 1581 | f4 w1 = VSET(*w++); \ 1582 | f4 vz = VLD(&zlin[4 * i - 64 * k]); \ 1583 | f4 vy = VLD(&zlin[4 * i - 64 * (15 - k)]); 1584 | #define V0(k) \ 1585 | { \ 1586 | VLOAD(k) \ 1587 | b = VADD(VMUL(vz, w1), VMUL(vy, w0)); \ 1588 | a = VSUB(VMUL(vz, w0), VMUL(vy, w1)); \ 1589 | } 1590 | #define V1(k) \ 1591 | { \ 1592 | VLOAD(k) \ 1593 | b = VADD(b, VADD(VMUL(vz, w1), VMUL(vy, w0))); \ 1594 | a = VADD(a, VSUB(VMUL(vz, w0), VMUL(vy, w1))); \ 1595 | } 1596 | #define V2(k) \ 1597 | { \ 1598 | VLOAD(k) \ 1599 | b = VADD(b, VADD(VMUL(vz, w1), VMUL(vy, w0))); \ 1600 | a = VADD(a, VSUB(VMUL(vy, w1), VMUL(vz, w0))); \ 1601 | } 1602 | f4 a, b; 1603 | zlin[4 * i] = xl[18 * (31 - i)]; 1604 | zlin[4 * i + 1] = xr[18 * (31 - i)]; 1605 | zlin[4 * i + 2] = xl[1 + 18 * (31 - i)]; 1606 | zlin[4 * i + 3] = xr[1 + 18 * (31 - i)]; 1607 | zlin[4 * i + 64] = xl[1 + 18 * (1 + i)]; 1608 | zlin[4 * i + 64 + 1] = xr[1 + 18 * (1 + i)]; 1609 | zlin[4 * i - 64 + 2] = xl[18 * (1 + i)]; 1610 | zlin[4 * i - 64 + 3] = xr[18 * (1 + i)]; 1611 | 1612 | V0(0) 1613 | V2(1) V1(2) V2(3) V1(4) V2(5) V1(6) V2(7) 1614 | 1615 | { 1616 | #ifndef MINIMP3_FLOAT_OUTPUT 1617 | #if HAVE_SSE 1618 | static const f4 g_max = {32767.0f, 32767.0f, 32767.0f, 32767.0f}; 1619 | static const f4 g_min = {-32768.0f, -32768.0f, -32768.0f, -32768.0f}; 1620 | __m128i pcm8 = _mm_packs_epi32(_mm_cvtps_epi32(_mm_max_ps(_mm_min_ps(a, g_max), g_min)), 1621 | _mm_cvtps_epi32(_mm_max_ps(_mm_min_ps(b, g_max), g_min))); 1622 | dstr[(15 - i) * nch] = _mm_extract_epi16(pcm8, 1); 1623 | dstr[(17 + i) * nch] = _mm_extract_epi16(pcm8, 5); 1624 | dstl[(15 - i) * nch] = _mm_extract_epi16(pcm8, 0); 1625 | dstl[(17 + i) * nch] = _mm_extract_epi16(pcm8, 4); 1626 | dstr[(47 - i) * nch] = _mm_extract_epi16(pcm8, 3); 1627 | dstr[(49 + i) * nch] = _mm_extract_epi16(pcm8, 7); 1628 | dstl[(47 - i) * nch] = _mm_extract_epi16(pcm8, 2); 1629 | dstl[(49 + i) * nch] = _mm_extract_epi16(pcm8, 6); 1630 | #else /* HAVE_SSE */ 1631 | int16x4_t pcma, pcmb; 1632 | a = VADD(a, VSET(0.5f)); 1633 | b = VADD(b, VSET(0.5f)); 1634 | pcma = vqmovn_s32(vqaddq_s32(vcvtq_s32_f32(a), vreinterpretq_s32_u32(vcltq_f32(a, VSET(0))))); 1635 | pcmb = vqmovn_s32(vqaddq_s32(vcvtq_s32_f32(b), vreinterpretq_s32_u32(vcltq_f32(b, VSET(0))))); 1636 | vst1_lane_s16(dstr + (15 - i) * nch, pcma, 1); 1637 | vst1_lane_s16(dstr + (17 + i) * nch, pcmb, 1); 1638 | vst1_lane_s16(dstl + (15 - i) * nch, pcma, 0); 1639 | vst1_lane_s16(dstl + (17 + i) * nch, pcmb, 0); 1640 | vst1_lane_s16(dstr + (47 - i) * nch, pcma, 3); 1641 | vst1_lane_s16(dstr + (49 + i) * nch, pcmb, 3); 1642 | vst1_lane_s16(dstl + (47 - i) * nch, pcma, 2); 1643 | vst1_lane_s16(dstl + (49 + i) * nch, pcmb, 2); 1644 | #endif /* HAVE_SSE */ 1645 | 1646 | #else /* MINIMP3_FLOAT_OUTPUT */ 1647 | 1648 | static const f4 g_scale = {1.0f / 32768.0f, 1.0f / 32768.0f, 1.0f / 32768.0f, 1.0f / 32768.0f}; 1649 | a = VMUL(a, g_scale); 1650 | b = VMUL(b, g_scale); 1651 | #if HAVE_SSE 1652 | _mm_store_ss(dstr + (15 - i) * nch, _mm_shuffle_ps(a, a, _MM_SHUFFLE(1, 1, 1, 1))); 1653 | _mm_store_ss(dstr + (17 + i) * nch, _mm_shuffle_ps(b, b, _MM_SHUFFLE(1, 1, 1, 1))); 1654 | _mm_store_ss(dstl + (15 - i) * nch, _mm_shuffle_ps(a, a, _MM_SHUFFLE(0, 0, 0, 0))); 1655 | _mm_store_ss(dstl + (17 + i) * nch, _mm_shuffle_ps(b, b, _MM_SHUFFLE(0, 0, 0, 0))); 1656 | _mm_store_ss(dstr + (47 - i) * nch, _mm_shuffle_ps(a, a, _MM_SHUFFLE(3, 3, 3, 3))); 1657 | _mm_store_ss(dstr + (49 + i) * nch, _mm_shuffle_ps(b, b, _MM_SHUFFLE(3, 3, 3, 3))); 1658 | _mm_store_ss(dstl + (47 - i) * nch, _mm_shuffle_ps(a, a, _MM_SHUFFLE(2, 2, 2, 2))); 1659 | _mm_store_ss(dstl + (49 + i) * nch, _mm_shuffle_ps(b, b, _MM_SHUFFLE(2, 2, 2, 2))); 1660 | #else /* HAVE_SSE */ 1661 | vst1q_lane_f32(dstr + (15 - i) * nch, a, 1); 1662 | vst1q_lane_f32(dstr + (17 + i) * nch, b, 1); 1663 | vst1q_lane_f32(dstl + (15 - i) * nch, a, 0); 1664 | vst1q_lane_f32(dstl + (17 + i) * nch, b, 0); 1665 | vst1q_lane_f32(dstr + (47 - i) * nch, a, 3); 1666 | vst1q_lane_f32(dstr + (49 + i) * nch, b, 3); 1667 | vst1q_lane_f32(dstl + (47 - i) * nch, a, 2); 1668 | vst1q_lane_f32(dstl + (49 + i) * nch, b, 2); 1669 | #endif /* HAVE_SSE */ 1670 | #endif /* MINIMP3_FLOAT_OUTPUT */ 1671 | } 1672 | } 1673 | else 1674 | #endif /* HAVE_SIMD */ 1675 | #ifdef MINIMP3_ONLY_SIMD 1676 | { 1677 | } /* for HAVE_SIMD=1, MINIMP3_ONLY_SIMD=1 case we do not need non-intrinsic "else" branch */ 1678 | #else /* MINIMP3_ONLY_SIMD */ 1679 | for (i = 14; i >= 0; i--) 1680 | { 1681 | #define LOAD(k) \ 1682 | float w0 = *w++; \ 1683 | float w1 = *w++; \ 1684 | float *vz = &zlin[4 * i - k * 64]; \ 1685 | float *vy = &zlin[4 * i - (15 - k) * 64]; 1686 | #define S0(k) \ 1687 | { \ 1688 | int j; \ 1689 | LOAD(k); \ 1690 | for (j = 0; j < 4; j++) \ 1691 | b[j] = vz[j] * w1 + vy[j] * w0, a[j] = vz[j] * w0 - vy[j] * w1; \ 1692 | } 1693 | #define S1(k) \ 1694 | { \ 1695 | int j; \ 1696 | LOAD(k); \ 1697 | for (j = 0; j < 4; j++) \ 1698 | b[j] += vz[j] * w1 + vy[j] * w0, a[j] += vz[j] * w0 - vy[j] * w1; \ 1699 | } 1700 | #define S2(k) \ 1701 | { \ 1702 | int j; \ 1703 | LOAD(k); \ 1704 | for (j = 0; j < 4; j++) \ 1705 | b[j] += vz[j] * w1 + vy[j] * w0, a[j] += vy[j] * w1 - vz[j] * w0; \ 1706 | } 1707 | float a[4], b[4]; 1708 | 1709 | zlin[4 * i] = xl[18 * (31 - i)]; 1710 | zlin[4 * i + 1] = xr[18 * (31 - i)]; 1711 | zlin[4 * i + 2] = xl[1 + 18 * (31 - i)]; 1712 | zlin[4 * i + 3] = xr[1 + 18 * (31 - i)]; 1713 | zlin[4 * (i + 16)] = xl[1 + 18 * (1 + i)]; 1714 | zlin[4 * (i + 16) + 1] = xr[1 + 18 * (1 + i)]; 1715 | zlin[4 * (i - 16) + 2] = xl[18 * (1 + i)]; 1716 | zlin[4 * (i - 16) + 3] = xr[18 * (1 + i)]; 1717 | 1718 | S0(0) 1719 | S2(1) S1(2) S2(3) S1(4) S2(5) S1(6) S2(7) 1720 | 1721 | dstr[(15 - i) * nch] = mp3d_scale_pcm(a[1]); 1722 | dstr[(17 + i) * nch] = mp3d_scale_pcm(b[1]); 1723 | dstl[(15 - i) * nch] = mp3d_scale_pcm(a[0]); 1724 | dstl[(17 + i) * nch] = mp3d_scale_pcm(b[0]); 1725 | dstr[(47 - i) * nch] = mp3d_scale_pcm(a[3]); 1726 | dstr[(49 + i) * nch] = mp3d_scale_pcm(b[3]); 1727 | dstl[(47 - i) * nch] = mp3d_scale_pcm(a[2]); 1728 | dstl[(49 + i) * nch] = mp3d_scale_pcm(b[2]); 1729 | } 1730 | #endif /* MINIMP3_ONLY_SIMD */ 1731 | } 1732 | 1733 | static void mp3d_synth_granule(float *qmf_state, float *grbuf, int nbands, int nch, mp3d_sample_t *pcm, float *lins) 1734 | { 1735 | int i; 1736 | for (i = 0; i < nch; i++) 1737 | { 1738 | mp3d_DCT_II(grbuf + 576 * i, nbands); 1739 | } 1740 | 1741 | memcpy(lins, qmf_state, sizeof(float) * 15 * 64); 1742 | 1743 | for (i = 0; i < nbands; i += 2) 1744 | { 1745 | mp3d_synth(grbuf + i, pcm + 32 * nch * i, nch, lins + i * 64); 1746 | } 1747 | #ifndef MINIMP3_NONSTANDARD_BUT_LOGICAL 1748 | if (nch == 1) 1749 | { 1750 | for (i = 0; i < 15 * 64; i += 2) 1751 | { 1752 | qmf_state[i] = lins[nbands * 64 + i]; 1753 | } 1754 | } 1755 | else 1756 | #endif /* MINIMP3_NONSTANDARD_BUT_LOGICAL */ 1757 | { 1758 | memcpy(qmf_state, lins + nbands * 64, sizeof(float) * 15 * 64); 1759 | } 1760 | } 1761 | 1762 | static int mp3d_match_frame(const uint8_t *hdr, int mp3_bytes, int frame_bytes) 1763 | { 1764 | int i, nmatch; 1765 | for (i = 0, nmatch = 0; nmatch < MAX_FRAME_SYNC_MATCHES; nmatch++) 1766 | { 1767 | i += hdr_frame_bytes(hdr + i, frame_bytes) + hdr_padding(hdr + i); 1768 | if (i + HDR_SIZE > mp3_bytes) 1769 | return nmatch > 0; 1770 | if (!hdr_compare(hdr, hdr + i)) 1771 | return 0; 1772 | } 1773 | return 1; 1774 | } 1775 | 1776 | static int mp3d_find_frame(const uint8_t *mp3, int mp3_bytes, int *free_format_bytes, int *ptr_frame_bytes) 1777 | { 1778 | int i, k; 1779 | for (i = 0; i < mp3_bytes - HDR_SIZE; i++, mp3++) 1780 | { 1781 | if (hdr_valid(mp3)) 1782 | { 1783 | int frame_bytes = hdr_frame_bytes(mp3, *free_format_bytes); 1784 | int frame_and_padding = frame_bytes + hdr_padding(mp3); 1785 | 1786 | for (k = HDR_SIZE; !frame_bytes && k < MAX_FREE_FORMAT_FRAME_SIZE && i + 2 * k < mp3_bytes - HDR_SIZE; k++) 1787 | { 1788 | if (hdr_compare(mp3, mp3 + k)) 1789 | { 1790 | int fb = k - hdr_padding(mp3); 1791 | int nextfb = fb + hdr_padding(mp3 + k); 1792 | if (i + k + nextfb + HDR_SIZE > mp3_bytes || !hdr_compare(mp3, mp3 + k + nextfb)) 1793 | continue; 1794 | frame_and_padding = k; 1795 | frame_bytes = fb; 1796 | *free_format_bytes = fb; 1797 | } 1798 | } 1799 | if ((frame_bytes && i + frame_and_padding <= mp3_bytes && 1800 | mp3d_match_frame(mp3, mp3_bytes - i, frame_bytes)) || 1801 | (!i && frame_and_padding == mp3_bytes)) 1802 | { 1803 | *ptr_frame_bytes = frame_and_padding; 1804 | return i; 1805 | } 1806 | *free_format_bytes = 0; 1807 | } 1808 | } 1809 | *ptr_frame_bytes = 0; 1810 | return mp3_bytes; 1811 | } 1812 | 1813 | void mp3dec_init(mp3dec_t *dec) 1814 | { 1815 | dec->header[0] = 0; 1816 | } 1817 | 1818 | int mp3dec_decode_frame(mp3dec_t *dec, const uint8_t *mp3, int mp3_bytes, mp3d_sample_t *pcm, mp3dec_frame_info_t *info) 1819 | { 1820 | int i = 0, igr, frame_size = 0, success = 1; 1821 | const uint8_t *hdr; 1822 | bs_t bs_frame[1]; 1823 | mp3dec_scratch_t scratch; 1824 | 1825 | if (mp3_bytes > 4 && dec->header[0] == 0xff && hdr_compare(dec->header, mp3)) 1826 | { 1827 | frame_size = hdr_frame_bytes(mp3, dec->free_format_bytes) + hdr_padding(mp3); 1828 | if (frame_size != mp3_bytes && (frame_size + HDR_SIZE > mp3_bytes || !hdr_compare(mp3, mp3 + frame_size))) 1829 | { 1830 | frame_size = 0; 1831 | } 1832 | } 1833 | if (!frame_size) 1834 | { 1835 | memset(dec, 0, sizeof(mp3dec_t)); 1836 | i = mp3d_find_frame(mp3, mp3_bytes, &dec->free_format_bytes, &frame_size); 1837 | if (!frame_size || i + frame_size > mp3_bytes) 1838 | { 1839 | info->frame_bytes = i; 1840 | return 0; 1841 | } 1842 | } 1843 | 1844 | hdr = mp3 + i; 1845 | memcpy(dec->header, hdr, HDR_SIZE); 1846 | info->frame_bytes = i + frame_size; 1847 | info->frame_offset = i; 1848 | info->channels = HDR_IS_MONO(hdr) ? 1 : 2; 1849 | info->hz = hdr_sample_rate_hz(hdr); 1850 | info->layer = 4 - HDR_GET_LAYER(hdr); 1851 | info->bitrate_kbps = hdr_bitrate_kbps(hdr); 1852 | 1853 | if (!pcm) 1854 | { 1855 | return hdr_frame_samples(hdr); 1856 | } 1857 | 1858 | bs_init(bs_frame, hdr + HDR_SIZE, frame_size - HDR_SIZE); 1859 | if (HDR_IS_CRC(hdr)) 1860 | { 1861 | get_bits(bs_frame, 16); 1862 | } 1863 | 1864 | if (info->layer == 3) 1865 | { 1866 | int main_data_begin = L3_read_side_info(bs_frame, scratch.gr_info, hdr); 1867 | if (main_data_begin < 0 || bs_frame->pos > bs_frame->limit) 1868 | { 1869 | mp3dec_init(dec); 1870 | return 0; 1871 | } 1872 | success = L3_restore_reservoir(dec, bs_frame, &scratch, main_data_begin); 1873 | if (success) 1874 | { 1875 | for (igr = 0; igr < (HDR_TEST_MPEG1(hdr) ? 2 : 1); igr++, pcm += 576 * info->channels) 1876 | { 1877 | memset(scratch.grbuf[0], 0, 576 * 2 * sizeof(float)); 1878 | L3_decode(dec, &scratch, scratch.gr_info + igr * info->channels, info->channels); 1879 | mp3d_synth_granule(dec->qmf_state, scratch.grbuf[0], 18, info->channels, pcm, scratch.syn[0]); 1880 | } 1881 | } 1882 | L3_save_reservoir(dec, &scratch); 1883 | } 1884 | else 1885 | { 1886 | #ifdef MINIMP3_ONLY_MP3 1887 | return 0; 1888 | #else /* MINIMP3_ONLY_MP3 */ 1889 | L12_scale_info sci[1]; 1890 | L12_read_scale_info(hdr, bs_frame, sci); 1891 | 1892 | memset(scratch.grbuf[0], 0, 576 * 2 * sizeof(float)); 1893 | for (i = 0, igr = 0; igr < 3; igr++) 1894 | { 1895 | if (12 == (i += L12_dequantize_granule(scratch.grbuf[0] + i, bs_frame, sci, info->layer | 1))) 1896 | { 1897 | i = 0; 1898 | L12_apply_scf_384(sci, sci->scf + igr, scratch.grbuf[0]); 1899 | mp3d_synth_granule(dec->qmf_state, scratch.grbuf[0], 12, info->channels, pcm, scratch.syn[0]); 1900 | memset(scratch.grbuf[0], 0, 576 * 2 * sizeof(float)); 1901 | pcm += 384 * info->channels; 1902 | } 1903 | if (bs_frame->pos > bs_frame->limit) 1904 | { 1905 | mp3dec_init(dec); 1906 | return 0; 1907 | } 1908 | } 1909 | #endif /* MINIMP3_ONLY_MP3 */ 1910 | } 1911 | return success * hdr_frame_samples(dec->header); 1912 | } 1913 | 1914 | #ifdef MINIMP3_FLOAT_OUTPUT 1915 | void mp3dec_f32_to_s16(const float *in, int16_t *out, int num_samples) 1916 | { 1917 | int i = 0; 1918 | #if HAVE_SIMD 1919 | int aligned_count = num_samples & ~7; 1920 | for (; i < aligned_count; i += 8) 1921 | { 1922 | static const f4 g_scale = {32768.0f, 32768.0f, 32768.0f, 32768.0f}; 1923 | f4 a = VMUL(VLD(&in[i]), g_scale); 1924 | f4 b = VMUL(VLD(&in[i + 4]), g_scale); 1925 | #if HAVE_SSE 1926 | static const f4 g_max = {32767.0f, 32767.0f, 32767.0f, 32767.0f}; 1927 | static const f4 g_min = {-32768.0f, -32768.0f, -32768.0f, -32768.0f}; 1928 | __m128i pcm8 = _mm_packs_epi32(_mm_cvtps_epi32(_mm_max_ps(_mm_min_ps(a, g_max), g_min)), 1929 | _mm_cvtps_epi32(_mm_max_ps(_mm_min_ps(b, g_max), g_min))); 1930 | out[i] = _mm_extract_epi16(pcm8, 0); 1931 | out[i + 1] = _mm_extract_epi16(pcm8, 1); 1932 | out[i + 2] = _mm_extract_epi16(pcm8, 2); 1933 | out[i + 3] = _mm_extract_epi16(pcm8, 3); 1934 | out[i + 4] = _mm_extract_epi16(pcm8, 4); 1935 | out[i + 5] = _mm_extract_epi16(pcm8, 5); 1936 | out[i + 6] = _mm_extract_epi16(pcm8, 6); 1937 | out[i + 7] = _mm_extract_epi16(pcm8, 7); 1938 | #else /* HAVE_SSE */ 1939 | int16x4_t pcma, pcmb; 1940 | a = VADD(a, VSET(0.5f)); 1941 | b = VADD(b, VSET(0.5f)); 1942 | pcma = vqmovn_s32(vqaddq_s32(vcvtq_s32_f32(a), vreinterpretq_s32_u32(vcltq_f32(a, VSET(0))))); 1943 | pcmb = vqmovn_s32(vqaddq_s32(vcvtq_s32_f32(b), vreinterpretq_s32_u32(vcltq_f32(b, VSET(0))))); 1944 | vst1_lane_s16(out + i, pcma, 0); 1945 | vst1_lane_s16(out + i + 1, pcma, 1); 1946 | vst1_lane_s16(out + i + 2, pcma, 2); 1947 | vst1_lane_s16(out + i + 3, pcma, 3); 1948 | vst1_lane_s16(out + i + 4, pcmb, 0); 1949 | vst1_lane_s16(out + i + 5, pcmb, 1); 1950 | vst1_lane_s16(out + i + 6, pcmb, 2); 1951 | vst1_lane_s16(out + i + 7, pcmb, 3); 1952 | #endif /* HAVE_SSE */ 1953 | } 1954 | #endif /* HAVE_SIMD */ 1955 | for (; i < num_samples; i++) 1956 | { 1957 | float sample = in[i] * 32768.0f; 1958 | if (sample >= 32766.5) 1959 | out[i] = (int16_t)32767; 1960 | else if (sample <= -32767.5) 1961 | out[i] = (int16_t)-32768; 1962 | else 1963 | { 1964 | int16_t s = (int16_t)(sample + .5f); 1965 | s -= (s < 0); /* away from zero, to be compliant */ 1966 | out[i] = s; 1967 | } 1968 | } 1969 | } 1970 | #endif /* MINIMP3_FLOAT_OUTPUT */ 1971 | #endif /* MINIMP3_IMPLEMENTATION && !_MINIMP3_IMPLEMENTATION_GUARD */ -------------------------------------------------------------------------------- /test/README: -------------------------------------------------------------------------------- 1 | 2 | This directory is intended for PlatformIO Unit Testing and project tests. 3 | 4 | Unit Testing is a software testing method by which individual units of 5 | source code, sets of one or more MCU program modules together with associated 6 | control data, usage procedures, and operating procedures, are tested to 7 | determine whether they are fit for use. Unit testing finds problems early 8 | in the development cycle. 9 | 10 | More information about PlatformIO Unit Testing: 11 | - https://docs.platformio.org/page/plus/unit-testing.html 12 | --------------------------------------------------------------------------------