├── Arduino ├── NHD_LCD │ └── NHD_LCD.ino ├── InProgress │ ├── LowPower │ │ ├── nbproject │ │ │ ├── private │ │ │ │ ├── config.properties │ │ │ │ ├── private.properties │ │ │ │ └── private.xml │ │ │ ├── genfiles.properties │ │ │ ├── project.xml │ │ │ └── project.properties │ │ ├── build │ │ │ └── classes │ │ │ │ ├── .netbeans_automatic_build │ │ │ │ ├── .netbeans_update_resources │ │ │ │ └── lowpower │ │ │ │ ├── LowPower.class │ │ │ │ ├── LowPower$SerialReader.class │ │ │ │ └── LowPower$SerialWriter.class │ │ ├── manifest.mf │ │ ├── build.xml │ │ └── src │ │ │ └── lowpower │ │ │ └── LowPower.java │ ├── ClientLowPower │ │ ├── build │ │ │ └── classes │ │ │ │ ├── .netbeans_automatic_build │ │ │ │ ├── .netbeans_update_resources │ │ │ │ └── clientlowpower │ │ │ │ ├── ClientLowPower.class │ │ │ │ ├── ClientLowPower$SerialReader.class │ │ │ │ └── ClientLowPower$SerialWriter.class │ │ ├── nbproject │ │ │ ├── private │ │ │ │ ├── config.properties │ │ │ │ └── private.properties │ │ │ ├── genfiles.properties │ │ │ ├── project.xml │ │ │ └── project.properties │ │ ├── manifest.mf │ │ ├── build.xml │ │ └── src │ │ │ └── clientlowpower │ │ │ └── ClientLowPower.java │ ├── CppApplication_1 │ │ ├── build │ │ │ └── Debug │ │ │ │ └── GNU-Linux-x86 │ │ │ │ ├── main.o.d │ │ │ │ └── main.o │ │ ├── nbproject │ │ │ ├── private │ │ │ │ ├── Makefile-variables.mk │ │ │ │ ├── private.xml │ │ │ │ ├── launcher.properties │ │ │ │ └── configurations.xml │ │ │ ├── project.xml │ │ │ ├── Makefile-variables.mk │ │ │ ├── Package-Debug.bash │ │ │ ├── Package-Release.bash │ │ │ ├── Makefile-Debug.mk │ │ │ ├── Makefile-Release.mk │ │ │ ├── configurations.xml │ │ │ └── Makefile-impl.mk │ │ ├── .dep.inc │ │ ├── dist │ │ │ └── Debug │ │ │ │ └── GNU-Linux-x86 │ │ │ │ └── cppapplication_1 │ │ ├── main.cpp │ │ └── Makefile │ ├── Sample1.so │ ├── Sample1.class │ ├── com.py │ ├── Sample1.java │ ├── Sample1.c │ ├── Sample1.h │ ├── Sample1.cpp │ └── GUI.py ├── MMA8452Q │ └── MMA8452Q.ino └── VCNL4000 │ └── VCNL4000.ino ├── OLD ├── I2C │ ├── test │ │ ├── vsim.wlf │ │ ├── modelsim_work │ │ │ ├── testbech │ │ │ │ ├── _primary.vhd │ │ │ │ ├── _primary.dat │ │ │ │ └── _primary.dbs │ │ │ ├── testbench │ │ │ │ ├── _primary.vhd │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ └── verilog.asm64 │ │ │ ├── testbench1 │ │ │ │ ├── _primary.vhd │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ └── verilog.asm64 │ │ │ ├── _temp │ │ │ │ ├── vlogBF5Oqc │ │ │ │ ├── vlogY7YoFA │ │ │ │ ├── vlogrUtiCy │ │ │ │ └── vlogscIE6H │ │ │ ├── test │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── verilog.asm64 │ │ │ │ └── _primary.vhd │ │ │ ├── test1 │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── verilog.asm64 │ │ │ │ └── _primary.vhd │ │ │ └── _info │ │ ├── test.v │ │ ├── test1.v │ │ ├── modelsim.ini │ │ └── transcript │ ├── .slave_testbench.v.swp │ ├── I2C_testbench.v │ └── modelsim.ini └── revise_I2C │ └── .master.v.swp ├── rfid-verilog ├── README ├── tag │ ├── divby2.v │ ├── counter10.v │ ├── epc.v │ ├── txsettings.v │ ├── sevenseg.v │ ├── txclkdivide.v │ ├── uid.v │ ├── read.v │ ├── rng.v │ ├── preamble.v │ ├── crc16.v │ ├── cmdparser.v │ ├── toptest.v │ ├── sequencer.v │ ├── rx.v │ ├── tx.v │ └── top.v └── reader │ ├── rfid_reader_rx.v │ ├── rfid_reader_tx.v │ └── rfid_reader.v ├── Memory ├── clock_tb.v ├── clock.v ├── test_memory.v ├── memory.v └── slave.v ├── README.md ├── I2C ├── I2C_tb.v ├── modelsim.ini └── slave.v ├── clock.v └── FIFO ├── test_FIFO.v ├── modelsim.ini └── FIFO.v /Arduino/NHD_LCD/NHD_LCD.ino: -------------------------------------------------------------------------------- 1 | Place Holder 2 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/nbproject/private/config.properties: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/build/classes/.netbeans_automatic_build: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/build/classes/.netbeans_update_resources: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/build/classes/.netbeans_automatic_build: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/nbproject/private/config.properties: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/build/classes/.netbeans_update_resources: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /OLD/I2C/test/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/OLD/I2C/test/vsim.wlf -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/build/Debug/GNU-Linux-x86/main.o.d: -------------------------------------------------------------------------------- 1 | build/Debug/GNU-Linux-x86/main.o: main.cpp 2 | -------------------------------------------------------------------------------- /Arduino/InProgress/Sample1.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/Arduino/InProgress/Sample1.so -------------------------------------------------------------------------------- /OLD/I2C/.slave_testbench.v.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/OLD/I2C/.slave_testbench.v.swp -------------------------------------------------------------------------------- /OLD/revise_I2C/.master.v.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/OLD/revise_I2C/.master.v.swp -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/manifest.mf: -------------------------------------------------------------------------------- 1 | Manifest-Version: 1.0 2 | X-COMMENT: Main-Class will be added automatically by build 3 | 4 | -------------------------------------------------------------------------------- /Arduino/InProgress/Sample1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/Arduino/InProgress/Sample1.class -------------------------------------------------------------------------------- /Arduino/InProgress/com.py: -------------------------------------------------------------------------------- 1 | import serial 2 | 3 | ser = serial.Serial('/dev/ttyACM0',9600) 4 | while True: 5 | print ser.readline() 6 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/manifest.mf: -------------------------------------------------------------------------------- 1 | Manifest-Version: 1.0 2 | X-COMMENT: Main-Class will be added automatically by build 3 | 4 | -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/testbech/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity testbech is 4 | end testbech; 5 | -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/testbench/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity testbench is 4 | end testbench; 5 | -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/testbench1/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity testbench1 is 4 | end testbench1; 5 | -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/_temp/vlogBF5Oqc: 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/OLD/I2C/test/modelsim_work/testbench1/_primary.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/OLD/I2C/test/modelsim_work/testbench1/_primary.dat -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/testbench1/_primary.dbs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/OLD/I2C/test/modelsim_work/testbench1/_primary.dbs -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/testbench1/verilog.asm64: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/OLD/I2C/test/modelsim_work/testbench1/verilog.asm64 -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/private/Makefile-variables.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated - do not edit! 3 | # 4 | # NOCDDL 5 | # 6 | # Debug configuration 7 | # Release configuration 8 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/build/classes/lowpower/LowPower.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/Arduino/InProgress/LowPower/build/classes/lowpower/LowPower.class -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/.dep.inc: -------------------------------------------------------------------------------- 1 | # This code depends on make tool being used 2 | DEPFILES=$(wildcard $(addsuffix .d, ${OBJECTFILES})) 3 | ifneq (${DEPFILES},) 4 | include ${DEPFILES} 5 | endif 6 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/build/Debug/GNU-Linux-x86/main.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/Arduino/InProgress/CppApplication_1/build/Debug/GNU-Linux-x86/main.o -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/dist/Debug/GNU-Linux-x86/cppapplication_1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/Arduino/InProgress/CppApplication_1/dist/Debug/GNU-Linux-x86/cppapplication_1 -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/build/classes/lowpower/LowPower$SerialReader.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/Arduino/InProgress/LowPower/build/classes/lowpower/LowPower$SerialReader.class -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/build/classes/lowpower/LowPower$SerialWriter.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/audiocircuit/NCSU-Low-Power-RFID/HEAD/Arduino/InProgress/LowPower/build/classes/lowpower/LowPower$SerialWriter.class -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/build/classes/clientlowpower/ClientLowPower.class: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity test is 4 | port( 5 | clk : in vl_logic; 6 | sda : in vl_logic; 7 | \out\ : out vl_logic 8 | ); 9 | end test; 10 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/private/private.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1 5 | 0 6 | 7 | 8 | -------------------------------------------------------------------------------- /rfid-verilog/README: -------------------------------------------------------------------------------- 1 | Copyright 2010 University of Washington 2 | License: http://creativecommons.org/licenses/by/3.0/ 3 | 4 | Original author: Dan Yeager, University of Washington 5 | 6 | This code is split into two separate branches: 7 | - master: every READ command causes a sample. 8 | - fifo: the ADC interface has a FIFO. 9 | 10 | TODO: merge master and fifo branches and use Verilog `ifdef <...> `endif to 11 | select between versions at compile time. 12 | -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/test1/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity test1 is 4 | port( 5 | clk : in vl_logic; 6 | reset : in vl_logic; 7 | enabled : in vl_logic; 8 | \in\ : in vl_logic; 9 | Start : in vl_logic; 10 | Stop : in vl_logic; 11 | sda : out vl_logic 12 | ); 13 | end test1; 14 | -------------------------------------------------------------------------------- /rfid-verilog/tag/divby2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // Divide by 2 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | module divby2 (in, reset, out); 9 | output out; 10 | input in, reset; 11 | 12 | reg out; 13 | 14 | always @ (posedge in or posedge reset) begin 15 | if (reset) begin 16 | out <= 0; 17 | end else begin 18 | out <= ~out; 19 | end 20 | end 21 | 22 | endmodule 23 | 24 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/nbproject/genfiles.properties: -------------------------------------------------------------------------------- 1 | build.xml.data.CRC32=5c2c2fb8 2 | build.xml.script.CRC32=abd0552f 3 | build.xml.stylesheet.CRC32=8064a381@1.68.1.46 4 | # This file is used by a NetBeans-based IDE to track changes in generated files such as build-impl.xml. 5 | # Do not edit this file. You may delete it but then the IDE will never regenerate such files for you. 6 | nbproject/build-impl.xml.data.CRC32=5c2c2fb8 7 | nbproject/build-impl.xml.script.CRC32=15048094 8 | nbproject/build-impl.xml.stylesheet.CRC32=5a01deb7@1.68.1.46 9 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/nbproject/private/private.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | file:/home/deathmonkey/Desktop/low_power/LowPower/src/lowpower/LowPower.java 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/nbproject/genfiles.properties: -------------------------------------------------------------------------------- 1 | build.xml.data.CRC32=47a4d4f2 2 | build.xml.script.CRC32=e6ae8004 3 | build.xml.stylesheet.CRC32=8064a381@1.68.1.46 4 | # This file is used by a NetBeans-based IDE to track changes in generated files such as build-impl.xml. 5 | # Do not edit this file. You may delete it but then the IDE will never regenerate such files for you. 6 | nbproject/build-impl.xml.data.CRC32=47a4d4f2 7 | nbproject/build-impl.xml.script.CRC32=e5618be8 8 | nbproject/build-impl.xml.stylesheet.CRC32=5a01deb7@1.68.1.46 9 | -------------------------------------------------------------------------------- /Memory/clock_tb.v: -------------------------------------------------------------------------------- 1 | module clock_test(); 2 | 3 | reg clk; 4 | reg reset; 5 | reg enabled; 6 | wire clk_out; 7 | wire clk_offset; 8 | 9 | clock_divider u1 (clk, reset, enabled, clk_out, clk_offset); 10 | 11 | always 12 | begin 13 | #5 clk <= !clk; 14 | end 15 | 16 | initial 17 | begin 18 | clk = 0; 19 | reset = 0; 20 | enabled = 0; 21 | #20000 22 | reset = 1; 23 | enabled = 1; 24 | #6000000; 25 | $finish; 26 | end 27 | 28 | endmodule -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/main.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * File: main.cpp 3 | * Author: deathmonkey 4 | * 5 | * Created on December 19, 2013, 1:57 PM 6 | */ 7 | 8 | #include 9 | #include 10 | using namespace std; 11 | 12 | /* 13 | * 14 | */ 15 | void dosomething(int *array); 16 | 17 | int main(int argc, char** argv) { 18 | 19 | int array[2] = {0, 0}; 20 | dosomething(array); 21 | printf("%d, %d", array[0], array[1]); 22 | return 0; 23 | } 24 | 25 | void dosomething(int *array) 26 | { 27 | array[0] = 56; 28 | array[1] = 78; 29 | } 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/nbproject/project.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | org.netbeans.modules.java.j2seproject 4 | 5 | 6 | LowPower 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/nbproject/project.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | org.netbeans.modules.java.j2seproject 4 | 5 | 6 | ClientLowPower 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /rfid-verilog/tag/counter10.v: -------------------------------------------------------------------------------- 1 | 2 | // Copyright 2010 University of Washington 3 | // License: http://creativecommons.org/licenses/by/3.0/ 4 | 5 | 6 | 7 | module counter10 (clk, reset, enable, count, overflow); 8 | output [9:0] count; 9 | output overflow; 10 | input clk, reset, enable; 11 | 12 | reg [9:0] count; 13 | 14 | wire [9:0] next_count; 15 | assign next_count = count + 10'd1; 16 | 17 | wire overflow; 18 | assign overflow = (count > 750); 19 | 20 | always @ (posedge clk or posedge reset) begin 21 | if (reset) begin 22 | count <= 0; 23 | end else if (enable & ~overflow) begin 24 | count <= next_count; 25 | end 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /OLD/I2C/test/test.v: -------------------------------------------------------------------------------- 1 | module test( 2 | input wire clk, 3 | input sda, 4 | output reg out 5 | ); 6 | 7 | always@( posedge sda ) 8 | begin 9 | if( clk == 1) 10 | begin 11 | out <= 1'b1; 12 | end 13 | else 14 | begin 15 | out <= 1'b0; 16 | end 17 | end 18 | 19 | endmodule 20 | 21 | 22 | module testbench(); 23 | 24 | reg clk, sda; 25 | wire out; 26 | 27 | test u1 (clk, sda, out); 28 | 29 | always 30 | begin 31 | #5 clk = ~clk; 32 | end 33 | 34 | initial 35 | begin 36 | clk = 0; 37 | sda = 1; 38 | #40 39 | sda = 0; 40 | #22 41 | sda = 1; 42 | #4 43 | sda = 0; 44 | #2 45 | sda = 1; 46 | #400 47 | 48 | 49 | $finish; 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | NCSU-Low-Power-RFID 2 | =================== 3 | 4 | Joshua Stevens 5 | Burton Younts 6 | Scott Johnson 7 | 8 | 9 | Verilog code for a low power RFID chip that will communicate with I2C sensors. 10 | 11 | We are using Modelsim to compile:
12 | "add cadence2010"
13 | "ncverilog filename.v"
14 | 15 | How to run Quartus:
16 | "add quartus111"
17 | "quartus &" MUST Be running X-win32 for this step
18 | 19 | 20 | Set up Modelsim in EOS:
21 | "add modelsim10.0c"
22 | "setenv MODELSIM modelsim.ini"
23 | 24 | Compile Verilog and Run Simulation:
25 | "vlog *.v"
26 | "vsim -novopt testbench_name.v"
27 | Inside vsim program: "log -r *"
28 | "run -all"
29 | 30 | **NOTE: to rerun in vsim: "vlog *.v"
31 | "restart -f"
32 | "run -all"
33 | -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim_work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K3 3 | 13 4 | cModel Technology 5 | Z0 d/afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test 6 | vtest 7 | Vo?JdDS^bhNDkH=PaehG5o0 8 | r1 9 | 31 10 | IZ2E8[m`8Uo]QZ9h2VBC_40 11 | Z1 w1388188357 12 | Z2 8test.v 13 | Z3 Ftest.v 14 | L0 1 15 | Z4 OL;L;6.3d;37 16 | !s85 0 17 | vtest1 18 | Vg?>YYP0f^eW4nd3I:knBl0 19 | r1 20 | !s85 0 21 | 31 22 | I[YNkh:WKbcHd`j@]8lfkg0 23 | Z5 w1388200037 24 | Z6 8test1.v 25 | Z7 Ftest1.v 26 | L0 1 27 | R4 28 | vtestbech 29 | IemkcIeB1mK_@[kL=keaXI0 30 | VWjgOD4j[`XTT0@Qc86ld<3 31 | w1388188038 32 | R2 33 | R3 34 | L0 22 35 | R4 36 | r1 37 | 31 38 | !s85 0 39 | vtestbench 40 | VhGfW:390DM[oDMzegDH9`2 41 | r1 42 | 31 43 | Ia75a20N0n=_@XUdm1j`7P1 44 | R1 45 | R2 46 | R3 47 | L0 22 48 | R4 49 | !s85 0 50 | vtestbench1 51 | VJ_5hzZ`<<1]AMHlCiT^[g1 52 | r1 53 | 31 54 | IjU^kRK`9iAHk9>L[8S^@83 55 | R5 56 | R6 57 | R7 58 | L0 61 59 | R4 60 | !s85 0 61 | -------------------------------------------------------------------------------- /Arduino/InProgress/Sample1.java: -------------------------------------------------------------------------------- 1 | public class Sample1 2 | { 3 | public native int intMethod(int n); 4 | public native boolean booleanMethod(boolean bool); 5 | public native String stringMethod(String text); 6 | public native int intArrayMethod(int [] intArrray); 7 | 8 | public static void main(String[] args) 9 | { 10 | System.loadLibrary("Sampe1"); 11 | 12 | Sample1 sample = new Sample1(); 13 | int square = sample.intMethod(5); 14 | boolean bool = sample.booleanMethod(true); 15 | String text = sample.stringMethod("Java"); 16 | int sum = sample.intArrayMethod( 17 | new int[]{1,2,3,4,5} ); 18 | 19 | System.out.println("intMethod: " + square); 20 | System.out.println("booleanMethod: " + bool); 21 | System.out.println("stringMethod: " + text); 22 | System.out.println("intArrayMethod: " + sum); 23 | 24 | } 25 | 26 | 27 | } 28 | -------------------------------------------------------------------------------- /Arduino/InProgress/Sample1.c: -------------------------------------------------------------------------------- 1 | 2 | #include "sm 3 | 4 | #ifndef _Included_Sample1 5 | #define _Included_Sample1 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | /* 10 | * Class: Sample1 11 | * Method: intMethod 12 | * Signature: (I)I 13 | */ 14 | JNIEXPORT jint JNICALL Java_Sample1_intMethod 15 | (JNIEnv *, jobject, jint); 16 | 17 | /* 18 | * Class: Sample1 19 | * Method: booleanMethod 20 | * Signature: (Z)Z 21 | */ 22 | JNIEXPORT jboolean JNICALL Java_Sample1_booleanMethod 23 | (JNIEnv *, jobject, jboolean); 24 | 25 | /* 26 | * Class: Sample1 27 | * Method: stringMethod 28 | * Signature: (Ljava/lang/String;)Ljava/lang/String; 29 | */ 30 | JNIEXPORT jstring JNICALL Java_Sample1_stringMethod 31 | (JNIEnv *, jobject, jstring); 32 | 33 | /* 34 | * Class: Sample1 35 | * Method: intArrayMethod 36 | * Signature: ([I)I 37 | */ 38 | JNIEXPORT jint JNICALL Java_Sample1_intArrayMethod 39 | (JNIEnv *, jobject, jintArray); 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | #endif 45 | -------------------------------------------------------------------------------- /I2C/I2C_tb.v: -------------------------------------------------------------------------------- 1 | module test(); 2 | reg reset_n; 3 | reg clk; 4 | reg en; 5 | reg start; 6 | reg stop; 7 | reg mode; 8 | reg [6:0] address; 9 | reg [7:0] regist; 10 | reg [7:0] mess; 11 | tri1 sda; 12 | tri1 scl; 13 | wire [7:0]data_out; 14 | 15 | master master_test (reset_n, clk, en, start, stop, mode, 16 | address, regist, sda, scl, data_out); 17 | 18 | slave slave_test (reset_n, en, address, mess, scl, sda); 19 | 20 | always 21 | #5 clk <= ~clk; 22 | 23 | initial 24 | begin 25 | clk = 1; 26 | en = 0; 27 | reset_n = 1; 28 | start = 0; 29 | stop = 0; 30 | mode = 1; 31 | address = 7'b1110000; 32 | regist = 8'b11110000; 33 | mess = 8'b00001111; 34 | #20 35 | reset_n = 0; 36 | #20 37 | reset_n = 1; 38 | #20 39 | en = 1; 40 | #20 41 | start = 1; 42 | #400 43 | start = 0; 44 | stop = 1; 45 | #100 46 | $finish; 47 | end 48 | 49 | endmodule 50 | 51 | -------------------------------------------------------------------------------- /rfid-verilog/tag/epc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // EPC: generate tag response to an ACK. 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // 2 byte PC: 0x30, 0x00 9 | // 12 byte EPC: 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 10 | 11 | module epc(reset, epcclk, epcbitout, epcdone); 12 | input reset, epcclk; 13 | output epcbitout, epcdone; 14 | 15 | wire [111:0] epc; 16 | assign epc = 112'h3000aabbccddeeff012345678910; 17 | 18 | reg [6:0] bitoutcounter; 19 | assign epcbitout = epc[bitoutcounter]; 20 | assign epcdone = (bitoutcounter == 0); 21 | reg initialized; 22 | 23 | always @ (posedge epcclk or posedge reset) begin 24 | if (reset) begin 25 | bitoutcounter <= 0; 26 | initialized <= 0; 27 | end else if (!initialized) begin 28 | bitoutcounter <= 111; 29 | initialized <= 1; 30 | end else if (!epcdone) begin 31 | bitoutcounter <= bitoutcounter - 7'd1; 32 | end else begin 33 | end // ~reset 34 | end // always 35 | 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /rfid-verilog/tag/txsettings.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // Transmit settings 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // This stores tx settings 9 | // Settings are refreshed from a query command 10 | 11 | module txsettings(reset, trcal_in, m_in, dr_in, trext_in, querycomplete, 12 | trcal_out, m_out, dr_out, trext_out); 13 | 14 | input reset, dr_in, trext_in, querycomplete; 15 | input [9:0] trcal_in; 16 | input [1:0] m_in; 17 | 18 | output dr_out, trext_out; 19 | output [9:0] trcal_out; 20 | output [1:0] m_out; 21 | 22 | reg dr_out, trext_out; 23 | reg [9:0] trcal_out; 24 | reg [1:0] m_out; 25 | 26 | 27 | always @ (posedge querycomplete or posedge reset) begin 28 | if (reset) begin 29 | dr_out <= 0; 30 | trext_out <= 0; 31 | trcal_out <= 0; 32 | m_out <= 0; 33 | end else begin 34 | dr_out <= dr_in; 35 | trext_out <= trext_in; 36 | trcal_out <= trcal_in; 37 | m_out <= m_in; 38 | end 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /Arduino/InProgress/Sample1.h: -------------------------------------------------------------------------------- 1 | /* DO NOT EDIT THIS FILE - it is machine generated */ 2 | #include 3 | /* Header for class Sample1 */ 4 | 5 | #ifndef _Included_Sample1 6 | #define _Included_Sample1 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | /* 11 | * Class: Sample1 12 | * Method: intMethod 13 | * Signature: (I)I 14 | */ 15 | JNIEXPORT jint JNICALL Java_Sample1_intMethod 16 | (JNIEnv *, jobject, jint); 17 | 18 | /* 19 | * Class: Sample1 20 | * Method: booleanMethod 21 | * Signature: (Z)Z 22 | */ 23 | JNIEXPORT jboolean JNICALL Java_Sample1_booleanMethod 24 | (JNIEnv *, jobject, jboolean); 25 | 26 | /* 27 | * Class: Sample1 28 | * Method: stringMethod 29 | * Signature: (Ljava/lang/String;)Ljava/lang/String; 30 | */ 31 | JNIEXPORT jstring JNICALL Java_Sample1_stringMethod 32 | (JNIEnv *, jobject, jstring); 33 | 34 | /* 35 | * Class: Sample1 36 | * Method: intArrayMethod 37 | * Signature: ([I)I 38 | */ 39 | JNIEXPORT jint JNICALL Java_Sample1_intArrayMethod 40 | (JNIEnv *, jobject, jintArray); 41 | 42 | #ifdef __cplusplus 43 | } 44 | #endif 45 | #endif 46 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/project.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | org.netbeans.modules.cnd.makeproject 4 | 5 | 6 | CppApplication_1 7 | 8 | cpp 9 | 10 | 11 | 12 | 13 | 14 | Debug 15 | 1 16 | 17 | 18 | Release 19 | 1 20 | 21 | 22 | UTF-8 23 | 24 | false 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /Arduino/InProgress/Sample1.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include "Sample1.h" 3 | #include 4 | 5 | JNIEXPORT jint JNICALL Java_Sample1_intMethod 6 | (JNIEnv * env, jobject obj, jint num) 7 | { 8 | return num * num; 9 | 10 | } 11 | 12 | JNIEXPORT jboolean JNICALL Java_Sample1_booleanMethod 13 | (JNIEnv * env, jobject obj, jboolean boolean) 14 | { 15 | return !boolean; 16 | } 17 | 18 | JNIEXPORT jstring JNICALL Java_Sample1_stringMethod 19 | (JNIEnv *env, jobject obj, jstring string) 20 | { 21 | const char *str = env->GetStringUTFChars(string, 0); 22 | char cap[128]; 23 | strcpy(cap, str); 24 | env->ReleaseStringUTFChars(string, str); 25 | return env->NewStringUTF(cap); 26 | 27 | } 28 | 29 | JNIEXPORT jint JNICALL Java_Sample1_intArrayMethod 30 | (JNIEnv *env, jobject obj, jintArray array) 31 | { 32 | int i, sum = 0; 33 | jsize len = env->GetArrayLength(array); 34 | jint *body = env->GetIntArrayElements(array, 0); 35 | for(i=0;iReleaseIntArrayElements(array, body, 0); 40 | return sum; 41 | 42 | } 43 | 44 | 45 | int main(){return 0;} 46 | -------------------------------------------------------------------------------- /Arduino/InProgress/GUI.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: iso-8859-1 -*- 3 | 4 | try: 5 | import wx 6 | except ImportError: 7 | raise ImportError,"The wxPython module is required to run this program" 8 | 9 | class simpleapp_wx(wx.Frame): 10 | def __init__(self,parent,id,title): 11 | wx.Frame.__init__(self,parent,id,title) 12 | self.parent = parent 13 | self.initialize() 14 | 15 | def initialize(self): 16 | sizer = wx.GridBagSizer() 17 | 18 | self.entry = wx.TextCtrl(self,-1,value=u"Enter text here.") 19 | sizer.Add(self.entry,(0,0),(1,1),wx.EXPAND) 20 | 21 | buttonOne = wx.Button(self,-1,label="Click me !") 22 | sizer.Add(buttonOne, (0,1)) 23 | 24 | self.label = wx.StaticText(self,-1,label=u'Hello !') 25 | self.label.SetBackgroundColour(wx.BLUE) 26 | self.label.SetForegroundColour(wx.WHITE) 27 | sizer.Add( self.label, (1,0),(1,2), wx.EXPAND ) 28 | 29 | self.SetSizerAndFit(sizer) 30 | self.Show(True) 31 | 32 | if __name__ == "__main__": 33 | app = wx.App() 34 | frame = simpleapp_wx(None,-1,'my application') 35 | app.MainLoop() 36 | 37 | -------------------------------------------------------------------------------- /clock.v: -------------------------------------------------------------------------------- 1 | module clock_divider( 2 | input wire clk, 3 | input wire reset, 4 | input wire enabled, 5 | output reg refresh_clk, 6 | output reg sys_clk 7 | ); 8 | 9 | reg [8:0] counter1; 10 | reg [8:0] counter2; 11 | reg [8:0] clk_divid; 12 | 13 | always@(posedge clk or negedge reset) 14 | begin 15 | if( ~reset ) 16 | begin 17 | refresh_clk <= 1; 18 | sys_clk <= 0; 19 | counter1 <= 0; 20 | counter2 <= 63; 21 | clk_divid <= 127; 22 | end 23 | else if( enabled ) 24 | begin 25 | clk_divid <= clk_divid; 26 | if( counter1 < clk_divid ) 27 | begin 28 | counter1 <= counter1 + 1; 29 | refresh_clk <= refresh_clk; 30 | end 31 | else 32 | begin 33 | refresh_clk <= !refresh_clk; 34 | counter1 <= 0; 35 | end 36 | if( counter2 < clk_divid ) 37 | begin 38 | counter2 <= counter2 + 1; 39 | sys_clk <= sys_clk; 40 | end 41 | else 42 | begin 43 | sys_clk <= !sys_clk; 44 | counter2 <= 0; 45 | end 46 | end 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /Memory/clock.v: -------------------------------------------------------------------------------- 1 | module clock_divider( 2 | input wire clk, 3 | input wire reset, 4 | input wire enabled, 5 | output reg refresh_clk, 6 | output reg sys_clk 7 | ); 8 | 9 | reg [8:0] counter1; 10 | reg [8:0] counter2; 11 | reg [8:0] clk_divid; 12 | 13 | always@(posedge clk or negedge reset) 14 | begin 15 | if( ~reset ) 16 | begin 17 | refresh_clk <= 1; 18 | sys_clk <= 0; 19 | counter1 <= 0; 20 | counter2 <= 63; 21 | clk_divid <= 100; 22 | end 23 | else if( enabled ) 24 | begin 25 | clk_divid <= clk_divid; 26 | if( counter1 < clk_divid ) 27 | begin 28 | counter1 <= counter1 + 1; 29 | refresh_clk <= refresh_clk; 30 | end 31 | else 32 | begin 33 | refresh_clk <= !refresh_clk; 34 | counter1 <= 0; 35 | end 36 | if( counter2 < clk_divid ) 37 | begin 38 | counter2 <= counter2 + 1; 39 | sys_clk <= sys_clk; 40 | end 41 | else 42 | begin 43 | sys_clk <= !sys_clk; 44 | counter2 <= 0; 45 | end 46 | end 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /OLD/I2C/I2C_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module I2C_testbench(); 4 | reg [6:0] address; 5 | reg [7:0] register; 6 | reg clk; 7 | wire sys_clk; 8 | wire refresh_clk; 9 | reg mode; 10 | reg en; 11 | reg reset; 12 | reg Start; 13 | reg Stop; 14 | reg repeat_start; 15 | wire [7:0] out; 16 | tri1 sda; 17 | tri1 scl; 18 | wire ack; 19 | 20 | wire sda_master, sda_slave; 21 | reg sda_master_reg, sda_slave_reg; 22 | reg[7:0] measurement; 23 | 24 | master u1 (address, register, refresh_clk, sys_clk, mode, en, reset, Start, Stop, repeat_start, out, ack, sda, scl); 25 | slave u2 (address, measurement, en, reset, scl, sda); 26 | clock_divider u3 (clk, reset, en, refresh_clk, sys_clk); 27 | 28 | always 29 | begin 30 | #5 clk = ~clk; 31 | end 32 | 33 | initial 34 | begin 35 | address = 7'b1110001; 36 | register = 8'b11111111; 37 | measurement = 8'b11110000; 38 | clk = 1; 39 | mode = 1; 40 | en = 0; 41 | Stop = 0; 42 | Start = 0; 43 | reset = 1; 44 | repeat_start = 0; 45 | #1000 46 | reset = 0; 47 | #2000 48 | reset = 1; 49 | en = 1; 50 | #5000 51 | Start = 1; 52 | #100000 53 | Stop = 1; 54 | #30000 55 | $finish; 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /FIFO/test_FIFO.v: -------------------------------------------------------------------------------- 1 | module test_FIFO(); 2 | reg reset_n; 3 | reg en; 4 | reg r_clk; 5 | reg w_clk; 6 | reg read; 7 | reg write; 8 | reg [7:0] data_in; 9 | wire [7:0] data_out; 10 | wire empty; 11 | wire full; 12 | 13 | 14 | FIFO fifo ( 15 | reset_n, 16 | en, 17 | r_clk, 18 | w_clk, 19 | read, 20 | write, 21 | data_in, 22 | data_out, 23 | empty, 24 | full 25 | ); 26 | 27 | always 28 | begin 29 | #5 30 | r_clk <= ~r_clk; 31 | w_clk <= ~w_clk; 32 | end 33 | 34 | initial 35 | begin 36 | reset_n =1; 37 | en = 1; 38 | r_clk = 1; 39 | w_clk = 1; 40 | read = 0; 41 | write = 0; 42 | data_in = 1; 43 | #20 44 | reset_n = 0; 45 | #20 46 | reset_n = 1; 47 | #15 48 | read = 1; 49 | write = 1; 50 | repeat(20) 51 | begin 52 | #10 53 | data_in = data_in + 2; 54 | end 55 | write = 0; 56 | #20 57 | read = 0; 58 | data_in = data_in -1; 59 | #50 60 | write = 1; 61 | repeat(20) 62 | begin 63 | #10 64 | data_in = data_in -1; 65 | end 66 | #10 67 | write = 0; 68 | #20 69 | read = 1; 70 | #300 71 | 72 | 73 | $finish; 74 | end 75 | 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/Makefile-variables.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated - do not edit! 3 | # 4 | # NOCDDL 5 | # 6 | CND_BASEDIR=`pwd` 7 | CND_BUILDDIR=build 8 | CND_DISTDIR=dist 9 | # Debug configuration 10 | CND_PLATFORM_Debug=GNU-Linux-x86 11 | CND_ARTIFACT_DIR_Debug=dist/Debug/GNU-Linux-x86 12 | CND_ARTIFACT_NAME_Debug=cppapplication_1 13 | CND_ARTIFACT_PATH_Debug=dist/Debug/GNU-Linux-x86/cppapplication_1 14 | CND_PACKAGE_DIR_Debug=dist/Debug/GNU-Linux-x86/package 15 | CND_PACKAGE_NAME_Debug=cppapplication1.tar 16 | CND_PACKAGE_PATH_Debug=dist/Debug/GNU-Linux-x86/package/cppapplication1.tar 17 | # Release configuration 18 | CND_PLATFORM_Release=GNU-Linux-x86 19 | CND_ARTIFACT_DIR_Release=dist/Release/GNU-Linux-x86 20 | CND_ARTIFACT_NAME_Release=cppapplication_1 21 | CND_ARTIFACT_PATH_Release=dist/Release/GNU-Linux-x86/cppapplication_1 22 | CND_PACKAGE_DIR_Release=dist/Release/GNU-Linux-x86/package 23 | CND_PACKAGE_NAME_Release=cppapplication1.tar 24 | CND_PACKAGE_PATH_Release=dist/Release/GNU-Linux-x86/package/cppapplication1.tar 25 | # 26 | # include compiler specific variables 27 | # 28 | # dmake command 29 | ROOT:sh = test -f nbproject/private/Makefile-variables.mk || \ 30 | (mkdir -p nbproject/private && touch nbproject/private/Makefile-variables.mk) 31 | # 32 | # gmake command 33 | .PHONY: $(shell test -f nbproject/private/Makefile-variables.mk || (mkdir -p nbproject/private && touch nbproject/private/Makefile-variables.mk)) 34 | # 35 | include nbproject/private/Makefile-variables.mk 36 | -------------------------------------------------------------------------------- /rfid-verilog/tag/sevenseg.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // http://www.lti-systems.com/verilog_03.html 4 | 5 | // altera seven seg is logic low. 6 | 7 | module sevenseg(displayout,inputbcd); 8 | 9 | output [6:0] displayout; 10 | input [3:0] inputbcd; 11 | 12 | reg [6:0] displayout; //latch the outputs 13 | 14 | 15 | parameter bit0 = 7'b0000001; 16 | parameter bit1 = 7'b0000010; 17 | parameter bit2 = 7'b0000100; 18 | parameter bit3 = 7'b0001000; 19 | parameter bit4 = 7'b0010000; 20 | parameter bit5 = 7'b0100000; 21 | parameter bit6 = 7'b1000000; 22 | 23 | parameter zero = ~(bit0 | bit1 | bit2 | bit3 | bit4 | bit5); 24 | parameter one = ~(bit1 | bit2); 25 | parameter two = ~(bit0 | bit1 | bit3 | bit4 | bit6); 26 | parameter three = ~(bit0 | bit1 | bit2 | bit3 | bit6); 27 | parameter four = ~(bit1 | bit2 | bit5 | bit6); 28 | parameter five = ~(bit0 | bit2 | bit3 | bit5 | bit6); 29 | parameter six = ~(bit0 | bit2 | bit3 | bit4 | bit5 | bit6); 30 | parameter seven = ~(bit0 | bit1 | bit2); 31 | parameter eight = ~(bit0 | bit1 | bit2 | bit3 | bit4 | bit5 | bit6); 32 | parameter nine = ~(bit0 | bit1 | bit2 | bit5 | bit6); 33 | parameter blank = ~(7'd0); 34 | 35 | always @ (inputbcd) 36 | 37 | case (inputbcd) 38 | 0: displayout = zero; 39 | 1: displayout = one; 40 | 2: displayout = two; 41 | 3: displayout = three; 42 | 4: displayout = four; 43 | 5: displayout = five; 44 | 6: displayout = six; 45 | 7: displayout = seven; 46 | 8: displayout = eight; 47 | 9: displayout = nine; 48 | 49 | default: displayout = blank; 50 | endcase 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /rfid-verilog/tag/txclkdivide.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // Tx Clock Divide 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // dr == 0 => 8 9 | // dr == 1 => 64/3 10 | 11 | // txclk = oscclk / ((dr) ? ((13+trcal+trcal+trcal)>>7) : (4+trcal)>>4)) 12 | 13 | // static offsets of 13 and 4 center the rounding error on 0% 14 | 15 | // tx only uses positive edges, so we don't need to be symmetric 16 | // this allows arbitrary divide ratios. 17 | 18 | module txclkdivide(reset, oscclk, trcal, dr, txclk); 19 | input reset, oscclk, dr; 20 | input [9:0] trcal; // max: 1023 21 | output txclk; 22 | reg txclk; 23 | reg [6:0] counter; 24 | 25 | // trcal3 = 3 * trcal 26 | wire [10:0] trcal2; 27 | assign trcal2[10:1] = trcal; 28 | assign trcal2[0] = 1'b0; 29 | wire [11:0] trcal3; 30 | assign trcal3 = trcal2 + trcal; 31 | 32 | wire [11:0] dr1numerator; 33 | assign dr1numerator = (11'd75+trcal3); // max: 12 bits 34 | wire [11:0] dr0numerator; 35 | assign dr0numerator = (11'd4+trcal); // max: 11 bits 36 | 37 | wire [6:0] tempdivider; 38 | assign tempdivider = dr ? ({1'b0, dr1numerator[11:7]}) : (dr0numerator[9:4]); // max dr0 = 64, dr1 = 24 -> 7 bits. 39 | wire [6:0] divider; 40 | assign divider = (tempdivider >= 7'd2) ? tempdivider : 7'd2; 41 | 42 | always @ (posedge oscclk or posedge reset) begin 43 | if (reset) begin 44 | txclk = 0; 45 | counter = 0; 46 | end else if (counter >= (divider-1)) begin 47 | txclk = 1; 48 | counter = 0; 49 | end else if (counter == ((divider-1) >> 1)) begin 50 | counter = counter + 7'd1; 51 | txclk = 0; 52 | end else begin 53 | counter = counter + 7'd1; 54 | end // ~reset 55 | end // always 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/Package-Debug.bash: -------------------------------------------------------------------------------- 1 | #!/bin/bash -x 2 | 3 | # 4 | # Generated - do not edit! 5 | # 6 | 7 | # Macros 8 | TOP=`pwd` 9 | CND_PLATFORM=GNU-Linux-x86 10 | CND_CONF=Debug 11 | CND_DISTDIR=dist 12 | CND_BUILDDIR=build 13 | CND_DLIB_EXT=so 14 | NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging 15 | TMPDIRNAME=tmp-packaging 16 | OUTPUT_PATH=${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 17 | OUTPUT_BASENAME=cppapplication_1 18 | PACKAGE_TOP_DIR=cppapplication1/ 19 | 20 | # Functions 21 | function checkReturnCode 22 | { 23 | rc=$? 24 | if [ $rc != 0 ] 25 | then 26 | exit $rc 27 | fi 28 | } 29 | function makeDirectory 30 | # $1 directory path 31 | # $2 permission (optional) 32 | { 33 | mkdir -p "$1" 34 | checkReturnCode 35 | if [ "$2" != "" ] 36 | then 37 | chmod $2 "$1" 38 | checkReturnCode 39 | fi 40 | } 41 | function copyFileToTmpDir 42 | # $1 from-file path 43 | # $2 to-file path 44 | # $3 permission 45 | { 46 | cp "$1" "$2" 47 | checkReturnCode 48 | if [ "$3" != "" ] 49 | then 50 | chmod $3 "$2" 51 | checkReturnCode 52 | fi 53 | } 54 | 55 | # Setup 56 | cd "${TOP}" 57 | mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package 58 | rm -rf ${NBTMPDIR} 59 | mkdir -p ${NBTMPDIR} 60 | 61 | # Copy files and create directories and links 62 | cd "${TOP}" 63 | makeDirectory "${NBTMPDIR}/cppapplication1/bin" 64 | copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 65 | 66 | 67 | # Generate tar file 68 | cd "${TOP}" 69 | rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/cppapplication1.tar 70 | cd ${NBTMPDIR} 71 | tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/cppapplication1.tar * 72 | checkReturnCode 73 | 74 | # Cleanup 75 | cd "${TOP}" 76 | rm -rf ${NBTMPDIR} 77 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/Package-Release.bash: -------------------------------------------------------------------------------- 1 | #!/bin/bash -x 2 | 3 | # 4 | # Generated - do not edit! 5 | # 6 | 7 | # Macros 8 | TOP=`pwd` 9 | CND_PLATFORM=GNU-Linux-x86 10 | CND_CONF=Release 11 | CND_DISTDIR=dist 12 | CND_BUILDDIR=build 13 | CND_DLIB_EXT=so 14 | NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging 15 | TMPDIRNAME=tmp-packaging 16 | OUTPUT_PATH=${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 17 | OUTPUT_BASENAME=cppapplication_1 18 | PACKAGE_TOP_DIR=cppapplication1/ 19 | 20 | # Functions 21 | function checkReturnCode 22 | { 23 | rc=$? 24 | if [ $rc != 0 ] 25 | then 26 | exit $rc 27 | fi 28 | } 29 | function makeDirectory 30 | # $1 directory path 31 | # $2 permission (optional) 32 | { 33 | mkdir -p "$1" 34 | checkReturnCode 35 | if [ "$2" != "" ] 36 | then 37 | chmod $2 "$1" 38 | checkReturnCode 39 | fi 40 | } 41 | function copyFileToTmpDir 42 | # $1 from-file path 43 | # $2 to-file path 44 | # $3 permission 45 | { 46 | cp "$1" "$2" 47 | checkReturnCode 48 | if [ "$3" != "" ] 49 | then 50 | chmod $3 "$2" 51 | checkReturnCode 52 | fi 53 | } 54 | 55 | # Setup 56 | cd "${TOP}" 57 | mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package 58 | rm -rf ${NBTMPDIR} 59 | mkdir -p ${NBTMPDIR} 60 | 61 | # Copy files and create directories and links 62 | cd "${TOP}" 63 | makeDirectory "${NBTMPDIR}/cppapplication1/bin" 64 | copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 65 | 66 | 67 | # Generate tar file 68 | cd "${TOP}" 69 | rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/cppapplication1.tar 70 | cd ${NBTMPDIR} 71 | tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/cppapplication1.tar * 72 | checkReturnCode 73 | 74 | # Cleanup 75 | cd "${TOP}" 76 | rm -rf ${NBTMPDIR} 77 | -------------------------------------------------------------------------------- /rfid-verilog/tag/uid.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // UID: EPC ID from Ying's Unique ID Generator 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // readbitclk, readbitout, readbitdone talk to tx module to send bits out 9 | 10 | // uid_byte_in, uid_addr_out talk to Ying's id generator. 11 | 12 | module uid(reset, uidbitclk, uidbitout, uidbitdone, 13 | uid_byte_in, uid_addr_out, uid_clk_out); 14 | 15 | input reset, uidbitclk; 16 | output uidbitout, uidbitdone, uid_clk_out; 17 | input [7:0] uid_byte_in; 18 | output [3:0] uid_addr_out; 19 | 20 | wire [15:0] preamble; 21 | assign preamble = 16'h3000; 22 | 23 | reg [3:0] bitoutcounter; 24 | reg [3:0] uid_addr_out; 25 | reg initialized; 26 | reg preambledone; 27 | 28 | assign uidbitout = (!preambledone) ? preamble[bitoutcounter] : uid_byte_in[bitoutcounter[2:0]]; 29 | assign uidbitdone = (bitoutcounter == 4'd0 && uid_addr_out == 11); 30 | 31 | assign uid_clk_out = ~uidbitclk; 32 | 33 | always @ (posedge uidbitclk or posedge reset) begin 34 | if (reset) begin 35 | bitoutcounter <= 4'd0; 36 | initialized <= 0; 37 | preambledone <= 0; 38 | uid_addr_out <= 4'd0; 39 | end else if (!initialized) begin 40 | initialized <= 1; 41 | bitoutcounter <= 4'd15; 42 | end else if (!preambledone) begin 43 | if (bitoutcounter == 0) begin 44 | preambledone <= 1; 45 | bitoutcounter <= 4'd7; 46 | end else begin 47 | bitoutcounter <= bitoutcounter - 4'd1; 48 | end 49 | end else if (!uidbitdone) begin 50 | if (bitoutcounter == 0) begin 51 | uid_addr_out <= uid_addr_out + 4'd1; 52 | bitoutcounter <= 4'd7; 53 | end else begin 54 | bitoutcounter <= bitoutcounter - 4'd1; 55 | end 56 | end else begin 57 | end // ~reset 58 | end // always 59 | 60 | endmodule 61 | 62 | -------------------------------------------------------------------------------- /rfid-verilog/tag/read.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // READ: Tag response to a 'read' command. 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // readbit* = talking to tx module 9 | 10 | // read_sample_* = talking to external source (adc or msp430) 11 | // which supplies sample data to be transmitted. 12 | 13 | // handle = current handle from random number generator 14 | 15 | module read(reset, readbitclk, readbitout, readbitdone, 16 | read_sample_ctl, read_sample_clk, read_sample_datain, 17 | handle); 18 | input reset, readbitclk; 19 | output readbitout, readbitdone; 20 | input read_sample_datain; 21 | output read_sample_ctl, read_sample_clk; 22 | input [15:0] handle; 23 | 24 | wire [32:0] packet; 25 | assign packet[32] = 1'b0; 26 | assign packet[31:16] = 16'h0000; 27 | assign packet[15:0] = handle[15:0]; 28 | 29 | reg [5:0] bitoutcounter; 30 | reg read_sample_ctl; 31 | 32 | wire read_sample_clk, readbitout, readbitdone; 33 | 34 | assign read_sample_clk = readbitclk & (bitoutcounter > 15); 35 | assign readbitout = (bitoutcounter!=32 && bitoutcounter>15) ? read_sample_datain : packet[bitoutcounter]; 36 | assign readbitdone = (bitoutcounter == 0); 37 | reg initialized; 38 | 39 | always @ (posedge readbitclk or posedge reset) begin 40 | if (reset) begin 41 | bitoutcounter <= 0; 42 | initialized <= 0; 43 | read_sample_ctl <= 0; 44 | end else if (!initialized) begin 45 | initialized <= 1; 46 | read_sample_ctl <= 1; 47 | bitoutcounter <= 32; 48 | end else if (!readbitdone) begin 49 | bitoutcounter <= bitoutcounter - 4'd1; 50 | if (bitoutcounter >= 15) read_sample_ctl <= 1; 51 | else read_sample_ctl <= 0; 52 | end else begin 53 | read_sample_ctl<= 0; 54 | end // ~reset 55 | end // always 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /Arduino/MMA8452Q/MMA8452Q.ino: -------------------------------------------------------------------------------- 1 | #include "Wire.h" 2 | #define MMA8452QAdress 0x1C 3 | #define MMA8452QRegister0 0x00 4 | #define MMA8452QRegister1 0x01 5 | #define MMA8452QRegister2 0x02 6 | #define MMA8452QRegister3 0x03 7 | #define MMA8452QRegister4 0x04 8 | #define MMA8452QRegister5 0x05 9 | #define MMA8452QRegister6 0x06 10 | #define MMA8452QRegister7 0x07 11 | #define MMA8452QRegister8 0x08 12 | #define MMA8452QRegister9 0x09 13 | #define MMA8452QRegister10 0x0A 14 | #define MMA8452QRegisterCTRL_REG1 0x28 15 | 16 | 17 | void setup() 18 | { 19 | Serial.begin(9600); 20 | Wire.begin(); 21 | MMA8452QSetup(); 22 | 23 | } 24 | 25 | void MMA8452QSetup() 26 | { 27 | MMA8452Qwrite(MMA8452QRegisterCTRL_REG1, 0x01); 28 | } 29 | 30 | void MMA8452Qwrite(byte address, byte value) 31 | { 32 | Wire.beginTransmission(MMA8452QAdress); 33 | Wire.write(address); 34 | Wire.write(value); 35 | Wire.endTransmission(); 36 | } 37 | 38 | 39 | void loop() 40 | { 41 | byte xHigh, xLow, yHigh, yLow, zHigh, zLow; 42 | unsigned int xResult, yResult, zResult; 43 | while(true) 44 | { 45 | MMA8452QRead(&xHigh, &xLow, &yHigh, &yLow, &zHigh, &zLow); 46 | xResult = (int)(xHigh << 4) + (int)(xLow >> 4); 47 | yResult = (int)(yHigh << 4) + (int)(yLow >> 4); 48 | zResult = (int)(zHigh << 4) + (int)(zLow >> 4); 49 | Serial.print(xResult); 50 | Serial.print(", "); 51 | Serial.print(yResult); 52 | Serial.print(", "); 53 | Serial.print(zResult); 54 | Serial.println(""); 55 | delay(10); 56 | } 57 | } 58 | 59 | void MMA8452QRead(byte *xHigh, byte *xLow, byte *yHigh, byte *yLow, byte *zHigh, byte *zLow) 60 | { 61 | Wire.beginTransmission(MMA8452QAdress); 62 | Wire.write(MMA8452QRegister1); 63 | Wire.endTransmission(); 64 | Wire.requestFrom(MMA8452QAdress,6); 65 | *xHigh = Wire.read(); 66 | *xLow = Wire.read(); 67 | *yHigh = Wire.read(); 68 | *yLow = Wire.read(); 69 | *zHigh = Wire.read(); 70 | *zLow = Wire.read(); 71 | } 72 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/Makefile-Debug.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated Makefile - do not edit! 3 | # 4 | # Edit the Makefile in the project folder instead (../Makefile). Each target 5 | # has a -pre and a -post target defined where you can add customized code. 6 | # 7 | # This makefile implements configuration specific macros and targets. 8 | 9 | 10 | # Environment 11 | MKDIR=mkdir 12 | CP=cp 13 | GREP=grep 14 | NM=nm 15 | CCADMIN=CCadmin 16 | RANLIB=ranlib 17 | CC=gcc 18 | CCC=g++ 19 | CXX=g++ 20 | FC=gfortran 21 | AS=as 22 | 23 | # Macros 24 | CND_PLATFORM=GNU-Linux-x86 25 | CND_DLIB_EXT=so 26 | CND_CONF=Debug 27 | CND_DISTDIR=dist 28 | CND_BUILDDIR=build 29 | 30 | # Include project Makefile 31 | include Makefile 32 | 33 | # Object Directory 34 | OBJECTDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM} 35 | 36 | # Object Files 37 | OBJECTFILES= \ 38 | ${OBJECTDIR}/main.o 39 | 40 | 41 | # C Compiler Flags 42 | CFLAGS= 43 | 44 | # CC Compiler Flags 45 | CCFLAGS= 46 | CXXFLAGS= 47 | 48 | # Fortran Compiler Flags 49 | FFLAGS= 50 | 51 | # Assembler Flags 52 | ASFLAGS= 53 | 54 | # Link Libraries and Options 55 | LDLIBSOPTIONS= 56 | 57 | # Build Targets 58 | .build-conf: ${BUILD_SUBPROJECTS} 59 | "${MAKE}" -f nbproject/Makefile-${CND_CONF}.mk ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 60 | 61 | ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1: ${OBJECTFILES} 62 | ${MKDIR} -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM} 63 | ${LINK.cc} -o ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 ${OBJECTFILES} ${LDLIBSOPTIONS} 64 | 65 | ${OBJECTDIR}/main.o: main.cpp 66 | ${MKDIR} -p ${OBJECTDIR} 67 | ${RM} "$@.d" 68 | $(COMPILE.cc) -g -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/main.o main.cpp 69 | 70 | # Subprojects 71 | .build-subprojects: 72 | 73 | # Clean Targets 74 | .clean-conf: ${CLEAN_SUBPROJECTS} 75 | ${RM} -r ${CND_BUILDDIR}/${CND_CONF} 76 | ${RM} ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 77 | 78 | # Subprojects 79 | .clean-subprojects: 80 | 81 | # Enable dependency checking 82 | .dep.inc: .depcheck-impl 83 | 84 | include .dep.inc 85 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/Makefile-Release.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated Makefile - do not edit! 3 | # 4 | # Edit the Makefile in the project folder instead (../Makefile). Each target 5 | # has a -pre and a -post target defined where you can add customized code. 6 | # 7 | # This makefile implements configuration specific macros and targets. 8 | 9 | 10 | # Environment 11 | MKDIR=mkdir 12 | CP=cp 13 | GREP=grep 14 | NM=nm 15 | CCADMIN=CCadmin 16 | RANLIB=ranlib 17 | CC=gcc 18 | CCC=g++ 19 | CXX=g++ 20 | FC=gfortran 21 | AS=as 22 | 23 | # Macros 24 | CND_PLATFORM=GNU-Linux-x86 25 | CND_DLIB_EXT=so 26 | CND_CONF=Release 27 | CND_DISTDIR=dist 28 | CND_BUILDDIR=build 29 | 30 | # Include project Makefile 31 | include Makefile 32 | 33 | # Object Directory 34 | OBJECTDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM} 35 | 36 | # Object Files 37 | OBJECTFILES= \ 38 | ${OBJECTDIR}/main.o 39 | 40 | 41 | # C Compiler Flags 42 | CFLAGS= 43 | 44 | # CC Compiler Flags 45 | CCFLAGS= 46 | CXXFLAGS= 47 | 48 | # Fortran Compiler Flags 49 | FFLAGS= 50 | 51 | # Assembler Flags 52 | ASFLAGS= 53 | 54 | # Link Libraries and Options 55 | LDLIBSOPTIONS= 56 | 57 | # Build Targets 58 | .build-conf: ${BUILD_SUBPROJECTS} 59 | "${MAKE}" -f nbproject/Makefile-${CND_CONF}.mk ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 60 | 61 | ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1: ${OBJECTFILES} 62 | ${MKDIR} -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM} 63 | ${LINK.cc} -o ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 ${OBJECTFILES} ${LDLIBSOPTIONS} 64 | 65 | ${OBJECTDIR}/main.o: main.cpp 66 | ${MKDIR} -p ${OBJECTDIR} 67 | ${RM} "$@.d" 68 | $(COMPILE.cc) -O2 -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/main.o main.cpp 69 | 70 | # Subprojects 71 | .build-subprojects: 72 | 73 | # Clean Targets 74 | .clean-conf: ${CLEAN_SUBPROJECTS} 75 | ${RM} -r ${CND_BUILDDIR}/${CND_CONF} 76 | ${RM} ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/cppapplication_1 77 | 78 | # Subprojects 79 | .clean-subprojects: 80 | 81 | # Enable dependency checking 82 | .dep.inc: .depcheck-impl 83 | 84 | include .dep.inc 85 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/private/launcher.properties: -------------------------------------------------------------------------------- 1 | # Launchers File syntax: 2 | # 3 | # [Must-have property line] 4 | # launcher1.runCommand= 5 | # [Optional extra properties] 6 | # launcher1.displayName= 7 | # launcher1.buildCommand= 8 | # launcher1.runDir= 9 | # launcher1.symbolFiles= 10 | # launcher1.env.= 11 | # (If this value is quoted with ` it is handled as a native command which execution result will become the value) 12 | # [Common launcher properties] 13 | # common.runDir= 14 | # (This value is overwritten by a launcher specific runDir value if the latter exists) 15 | # common.env.= 16 | # (Environment variables from common launcher are merged with launcher specific variables) 17 | # common.symbolFiles= 18 | # (This value is overwritten by a launcher specific symbolFiles value if the latter exists) 19 | # 20 | # In runDir, symbolFiles and env fields you can use these macroses: 21 | # ${PROJECT_DIR} - project directory absolute path 22 | # ${OUTPUT_PATH} - linker output path (relative to project directory path) 23 | # ${OUTPUT_BASENAME}- linker output filename 24 | # ${TESTDIR} - test files directory (relative to project directory path) 25 | # ${OBJECTDIR} - object files directory (relative to project directory path) 26 | # ${CND_DISTDIR} - distribution directory (relative to project directory path) 27 | # ${CND_BUILDDIR} - build directory (relative to project directory path) 28 | # ${CND_PLATFORM} - platform name 29 | # ${CND_CONF} - configuration name 30 | # ${CND_DLIB_EXT} - dynamic library extension 31 | # 32 | # All the project launchers must be listed in the file! 33 | # 34 | # launcher1.runCommand=... 35 | # launcher2.runCommand=... 36 | # ... 37 | # common.runDir=... 38 | # common.env.KEY=VALUE 39 | 40 | # launcher1.runCommand= -------------------------------------------------------------------------------- /rfid-verilog/tag/rng.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // RNG: generate tag response to query, query_rep, req_rn 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // RNG reuses the crc algorithm 9 | // The input is the lsb of the counter 10 | // at each incoming bit from the reader. 11 | 12 | // The RNG only changes when rngbitinclk is clocked. 13 | // The clock should only be enabled for query,queryadj 14 | // and req_rn (after passing handlecheck match) 15 | 16 | module rng(reset, rnreset, rngbitin, rngbitinclk, rngbitoutclk, rngbitout, rngdone, handle); 17 | input reset, rnreset, rngbitoutclk; 18 | input rngbitin, rngbitinclk; 19 | output rngbitout, rngdone; 20 | output [15:0] handle; 21 | 22 | reg [15:0] rn; 23 | reg [3:0] bitoutcounter; 24 | 25 | /* 26 | // test setup for checking functionality. 27 | wire [15:0] fixedrn; 28 | assign fixedrn = 16'h0001; 29 | assign handle[15:0] = fixedrn[15:0]; 30 | assign rngbitout = fixedrn[bitoutcounter]; 31 | */ 32 | 33 | // real setup 34 | assign handle[15:0] = rn[15:0]; 35 | assign rngbitout = rn[bitoutcounter]; 36 | 37 | assign rngdone = (bitoutcounter == 0); 38 | reg initialized; 39 | 40 | always @ (posedge rngbitoutclk or posedge reset) begin 41 | if (reset) begin 42 | bitoutcounter <= 0; 43 | initialized <= 0; 44 | end else if (!initialized) begin 45 | initialized <= 1; 46 | bitoutcounter <= 15; 47 | end else if (!rngdone) begin 48 | bitoutcounter <= bitoutcounter - 4'd1; 49 | end else begin 50 | end // ~reset 51 | end // always 52 | 53 | always @ (posedge rngbitinclk or posedge rnreset) begin 54 | if (rnreset) begin 55 | rn <= 16'h0000; 56 | end else begin 57 | rn[0] <= rngbitin ^ rn[15]; 58 | rn[1] <= rn[0]; 59 | rn[2] <= rn[1]; 60 | rn[3] <= rn[2]; 61 | rn[4] <= rn[3]; 62 | rn[5] <= rn[4] ^ rngbitin ^ rn[15]; 63 | rn[6] <= rn[5]; 64 | rn[7] <= rn[6]; 65 | rn[8] <= rn[7]; 66 | rn[9] <= rn[8]; 67 | rn[10] <= rn[9]; 68 | rn[11] <= rn[10]; 69 | rn[12] <= rn[11] ^ rngbitin ^ rn[15]; 70 | rn[13] <= rn[12]; 71 | rn[14] <= rn[13]; 72 | rn[15] <= rn[14]; 73 | end // ~reset. 74 | end // always 75 | 76 | 77 | endmodule 78 | 79 | -------------------------------------------------------------------------------- /OLD/I2C/test/test1.v: -------------------------------------------------------------------------------- 1 | module test1( 2 | input wire clk, 3 | input wire reset, 4 | input wire enabled, 5 | input wire in, 6 | input wire Start, 7 | input wire Stop, 8 | output wire sda 9 | ); 10 | 11 | reg start, done, data; 12 | 13 | always@( negedge Start or reset ) 14 | begin 15 | if(~reset) 16 | begin 17 | start <= 1'b0; 18 | end 19 | else 20 | begin 21 | if( enabled == 1 ) 22 | begin 23 | start <= 1'b1; 24 | end 25 | else 26 | begin 27 | start <= 1'b0; 28 | end 29 | end 30 | end 31 | 32 | always@( posedge Stop or reset ) 33 | begin 34 | if(~reset) 35 | begin 36 | done <= 1'b0; 37 | end 38 | else 39 | begin 40 | if( enabled == 1 ) 41 | begin 42 | done <= 1'b1; 43 | end 44 | else 45 | begin 46 | done <= 1'b0; 47 | end 48 | end 49 | end 50 | 51 | always@( posedge clk ) 52 | begin 53 | data <= in; 54 | end 55 | 56 | assign sda = ( enabled == 1 ) ? ( start == 1) ? (done== 0) ? data : 1'bz : 1'bz : 1'bz; 57 | 58 | endmodule 59 | 60 | 61 | module testbench1(); 62 | 63 | reg reset, clk, enable, in, Start, Stop; 64 | wire sda; 65 | 66 | test1 u1 ( clk, reset, enable, in, Start, Stop, sda ); 67 | 68 | always 69 | begin 70 | #5 clk = ~clk; 71 | end 72 | 73 | initial 74 | begin 75 | reset = 0; 76 | clk = 1; 77 | enable = 0; 78 | in = 0; 79 | Start = 0; 80 | Stop = 0; 81 | #20 82 | reset = 1; 83 | #40 84 | Start = 1; 85 | #20; 86 | Start = 0; 87 | #20 88 | enable = 1; 89 | #20 90 | enable = 0; 91 | #20 92 | enable = 1; 93 | Start = 1; 94 | #20 95 | Start = 0; 96 | in = 0; 97 | #20 98 | in = 1; 99 | #10 100 | in = 0; 101 | #10 102 | in = 1; 103 | #10 104 | in = 0; 105 | #10 106 | in = 1; 107 | #10 108 | in = 0; 109 | #10 110 | in = 1; 111 | #10 112 | in = 0; 113 | #10 114 | in = 1; 115 | Stop = 1; 116 | #2 117 | Stop = 0; 118 | #50 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | $finish; 127 | end 128 | 129 | endmodule 130 | -------------------------------------------------------------------------------- /Memory/test_memory.v: -------------------------------------------------------------------------------- 1 | //`timescale 1ns/1ps 2 | 3 | module write_to_memory_testbench(); 4 | 5 | wire [6:0] slave_address; // 7 bit alave address 6 | wire [7:0] byte_to_be_writen; // 8 bit value for write 7 | wire I2C_mode; // use to select between read and write 8 | wire I2C_start; 9 | wire I2C_stop; 10 | wire I2C_repeat_start; 11 | wire [7:0] I2C_data_out; 12 | wire ack; 13 | tri1 sda; 14 | tri1 scl; 15 | wire [7:0] FIFO_data_out; 16 | wire FIFO_empty; 17 | wire FIFO_read; 18 | wire full; 19 | wire I2C_en; // used to enable the memory write to memory 20 | wire reset_I2C; // used to reset the I2C machine 21 | wire refresh_clk; 22 | wire sys_clk; 23 | 24 | reg clk; 25 | reg write; 26 | reg reset; 27 | reg run; 28 | reg [11:0] number_of_bytes; 29 | reg [2:0] memory_number; 30 | reg [14:0] memory_address; 31 | reg [7:0] data_in; 32 | reg [7:0] measurement; 33 | reg en; 34 | 35 | 36 | 37 | master u1 (slave_address, byte_to_be_writen, refresh_clk, sys_clk, 38 | I2C_mode, I2C_en, reset_I2C, I2C_start, I2C_stop, 39 | I2C_repeat_start, I2C_data_out, ack, sda, scl); 40 | 41 | I2C_write_to_memory u2 (sys_clk, reset, run, number_of_bytes, 42 | memory_address, FIFO_data_out, empty, ack, memory_number, 43 | FIFO_read, slave_address, byte_to_be_writen, I2C_mode, 44 | I2C_en, reset_I2C, I2C_start, I2C_stop, I2C_repeat_start, 45 | sda); 46 | 47 | FIFO_four u3 (sys_clk, reset, write, FIFO_read, data_in, 48 | FIFO_data_out, full, FIFO_empty); 49 | 50 | clock_divider u4 (clk, reset, en, refresh_clk, sys_clk); 51 | 52 | slave u5 (slave_address, measurement, en, reset, scl, sda); 53 | 54 | always 55 | begin 56 | #5 clk <= ~clk; 57 | end 58 | 59 | 60 | initial 61 | begin 62 | 63 | clk = 1; 64 | reset = 1; 65 | en = 1; 66 | write = 0; 67 | #200 68 | reset = 0; 69 | run = 0; 70 | number_of_bytes = 5; 71 | memory_address = 0; 72 | memory_number = 2; 73 | data_in = 0; 74 | #4000 75 | reset = 1; 76 | #1400 77 | while( !full ) 78 | begin 79 | #1000 80 | write = 1; 81 | #1000 82 | write = 0; 83 | data_in = data_in + 3; 84 | end 85 | write = 0; 86 | run = 1; 87 | #30000 88 | 89 | $finish; 90 | end 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/configurations.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 11 | 12 | 15 | main.cpp 16 | 17 | 21 | 22 | 26 | Makefile 27 | 28 | 29 | Makefile 30 | 31 | 32 | 33 | default 34 | true 35 | false 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | default 45 | true 46 | false 47 | 48 | 49 | 50 | 5 51 | 52 | 53 | 5 54 | 55 | 56 | 5 57 | 58 | 59 | 5 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | -------------------------------------------------------------------------------- /Arduino/VCNL4000/VCNL4000.ino: -------------------------------------------------------------------------------- 1 | #include "Wire.h" 2 | #define VCNL4000Adress 0x13 3 | #define VCNL4000Register0 0x80 4 | #define VCNL4000Register1 0x81 5 | #define VCNL4000Register2 0x82 6 | #define VCNL4000Register3 0x803 7 | #define VCNL4000Register4 0x84 8 | #define VCNL4000Register5 0x85 9 | #define VCNL4000Register6 0x86 10 | #define VCNL4000Register7 0x87 11 | #define VCNL4000Register8 0x88 12 | #define VCNL4000Register9 0x89 13 | #define VCNL4000Register10 0x8A 14 | 15 | 16 | void setup() 17 | { 18 | byte value = 0; 19 | Serial.begin(9600); 20 | Wire.begin(); 21 | delay(1000); 22 | VCNL4000Setup(); 23 | Wire.beginTransmission(VCNL4000Adress); 24 | Wire.write(VCNL4000Register0); 25 | Wire.endTransmission(); 26 | Wire.requestFrom(VCNL4000Adress,1); 27 | value = Wire.read(); 28 | Serial.print("setup: "); 29 | Serial.println(value,1); 30 | Wire.beginTransmission(VCNL4000Adress); 31 | Wire.write(VCNL4000Register3); 32 | Wire.endTransmission(); 33 | Wire.requestFrom(VCNL4000Adress,1); 34 | value = Wire.read(); 35 | Serial.print("setup: "); 36 | Serial.println(value,1); 37 | Wire.beginTransmission(VCNL4000Adress); 38 | Wire.write(VCNL4000Register4); 39 | Wire.endTransmission(); 40 | Wire.requestFrom(VCNL4000Adress,1); 41 | value = Wire.read(); 42 | Serial.print("setup: "); 43 | Serial.println(value,1); 44 | 45 | } 46 | 47 | void loop() 48 | { 49 | byte LightHigh, LightLow, ProximtyHigh, ProximtyLow; 50 | 51 | while(true) 52 | { 53 | byte results[2] = {0, 0}; 54 | unsigned int light, proximty; 55 | VCNL4000Read(results, 2, VCNL4000Register5); 56 | light = ((int)results[1] << 8) + (int)results[0]; 57 | Serial.print(light); 58 | Serial.print(", "); 59 | Serial.println(""); 60 | delay(20); 61 | 62 | } 63 | 64 | } 65 | 66 | void VCNL4000Setup() 67 | { 68 | VCNL4000Write(VCNL4000Register4,0x8d); 69 | } 70 | 71 | void VCNL4000Write(byte registerAddress,byte data) 72 | { 73 | byte value = 0x00; 74 | Wire.beginTransmission(VCNL4000Adress); 75 | Wire.write(registerAddress); 76 | Wire.write(data); 77 | Wire.endTransmission(); 78 | Wire.beginTransmission(VCNL4000Adress); 79 | Wire.write(registerAddress); 80 | Wire.endTransmission(); 81 | Wire.requestFrom(VCNL4000Adress,1); 82 | value = Wire.read(); 83 | Serial.print("setup: "); 84 | Serial.println(value,1); 85 | } 86 | 87 | void VCNL4000Read(byte *results, int len, byte Register) 88 | { 89 | int n; 90 | Wire.beginTransmission(VCNL4000Adress); 91 | Wire.write(Register); 92 | Wire.endTransmission(); 93 | Wire.requestFrom(VCNL4000Adress,len); 94 | for(n = 0; n < len; n++) 95 | { 96 | results[n] = Wire.read(); 97 | } 98 | } 99 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/private/configurations.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | Makefile 4 | 5 | 6 | 7 | localhost 8 | 2 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | gdb 24 | 25 | 26 | 27 | "${OUTPUT_PATH}" 28 | 29 | "${OUTPUT_PATH}" 30 | 31 | true 32 | 0 33 | 0 34 | 35 | 36 | 37 | 38 | 39 | 40 | localhost 41 | 2 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | gdb 57 | 58 | 59 | 60 | "${OUTPUT_PATH}" 61 | 62 | "${OUTPUT_PATH}" 63 | 64 | true 65 | 0 66 | 0 67 | 68 | 69 | 70 | 71 | 72 | 73 | -------------------------------------------------------------------------------- /rfid-verilog/tag/preamble.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // PREAMBLE 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // PREAMBLE module sends out the EPC Class 1 Gen 2 preamble 9 | // based on the miller encoding 'm' and subcarrier duration 'trext' 10 | 11 | module preamble(reset, clk, m, trext, out, violation, done); 12 | input clk, reset, trext; 13 | input [1:0] m; 14 | output out, violation, done; 15 | 16 | reg out, done, violation; 17 | 18 | reg [5:0] clkcount; 19 | wire [5:0] bitcount, next_count; 20 | assign bitcount = (trext == 6'd1) ? (clkcount) : (clkcount + 6'd12); 21 | 22 | // don't wrap counter around to 0 -> stick at max count. 23 | assign next_count = (bitcount > 6'd25) ? (clkcount) : (clkcount + 6'd1); 24 | 25 | always @ (posedge clk or posedge reset) begin 26 | if (reset) begin 27 | clkcount <= 0; 28 | done <= 0; 29 | out <= 0; 30 | violation <= 0; 31 | 32 | end else begin 33 | if (m > 0) begin // miller 34 | if (bitcount == 0) begin 35 | out <= 0; 36 | violation <= 0; 37 | end else if (bitcount == 12 & ~trext) begin 38 | out <= 0; 39 | violation <= 0; 40 | end else if (bitcount <= 16) begin 41 | out <= 0; 42 | violation <= 1; 43 | end else if (bitcount == 17) begin 44 | out <= 1; 45 | violation <= 0; 46 | end else if (bitcount == 18) begin 47 | out <= 0; 48 | violation <= 0; 49 | end else if (bitcount == 19) begin 50 | out <= 1; 51 | violation <= 0; 52 | end else if (bitcount == 20) begin 53 | out <= 1; 54 | violation <= 0; 55 | end else if (bitcount == 21) begin 56 | out <= 1; 57 | violation <= 0; 58 | done <= 1; 59 | end 60 | 61 | end else begin // fm 0 62 | if (bitcount <= 11) begin 63 | out <= 0; 64 | violation <= 0; 65 | end else if (bitcount == 12) begin 66 | out <= 1; 67 | violation <= 0; 68 | end else if (bitcount == 13) begin 69 | out <= 0; 70 | violation <= 0; 71 | end else if (bitcount == 14) begin 72 | out <= 1; 73 | violation <= 0; 74 | end else if (bitcount == 15) begin 75 | out <= 0; 76 | violation <= 0; 77 | end else if (bitcount == 16) begin 78 | out <= 0; 79 | violation <= 1; 80 | end else if (bitcount == 17) begin 81 | out <= 1; 82 | violation <= 0; 83 | done <= 1; 84 | end 85 | 86 | end // m > 0 87 | 88 | clkcount <= next_count; 89 | end // ~reset 90 | end // always @ clk 91 | endmodule 92 | 93 | -------------------------------------------------------------------------------- /rfid-verilog/tag/crc16.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // CRC16 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // 2 direction module. 9 | // inclk, inbit generate crc 10 | // outclk, outbit read out crc. 11 | 12 | module crc16(reset, crcinclk, crcbitin, crcoutclk, crcbitout, crcdone); 13 | input reset, crcinclk, crcbitin, crcoutclk; 14 | output crcbitout, crcdone; 15 | 16 | reg [15:0] crc; 17 | 18 | /* 19 | // working code 20 | reg [3:0] bitoutcounter; 21 | wire crcdone; 22 | assign crcbitout = ~crc[~bitoutcounter]; 23 | //assign crcbitout = 0; 24 | assign crcdone = (bitoutcounter == 15); 25 | 26 | always @ (posedge crcoutclk or posedge reset) begin 27 | if (reset) begin 28 | bitoutcounter <= 0; 29 | end else if (!crcdone) begin 30 | bitoutcounter <= bitoutcounter + 4'd1; 31 | end // ~reset 32 | end // always 33 | 34 | 35 | always @ (posedge crcinclk or posedge reset) begin 36 | if (reset) begin 37 | crc <= 'hFFFF; 38 | end else begin 39 | crc[0] <= crcbitin ^ crc[15]; 40 | crc[1] <= crc[0]; 41 | crc[2] <= crc[1]; 42 | crc[3] <= crc[2]; 43 | crc[4] <= crc[3]; 44 | crc[5] <= crc[4] ^ crcbitin ^ crc[15]; 45 | crc[6] <= crc[5]; 46 | crc[7] <= crc[6]; 47 | crc[8] <= crc[7]; 48 | crc[9] <= crc[8]; 49 | crc[10] <= crc[9]; 50 | crc[11] <= crc[10]; 51 | crc[12] <= crc[11] ^ crcbitin ^ crc[15]; 52 | crc[13] <= crc[12]; 53 | crc[14] <= crc[13]; 54 | crc[15] <= crc[14]; 55 | end // ~reset 56 | end // always 57 | */ 58 | 59 | 60 | 61 | reg [3:0] bitoutcounter; 62 | wire crcdone; 63 | assign crcbitout = crc[~bitoutcounter]; 64 | //assign crcbitout = 0; 65 | assign crcdone = (bitoutcounter == 15); 66 | 67 | always @ (posedge crcoutclk or posedge reset) begin 68 | if (reset) begin 69 | bitoutcounter <= 0; 70 | end else if (!crcdone) begin 71 | bitoutcounter <= bitoutcounter + 4'd1; 72 | end // ~reset 73 | end // always 74 | 75 | 76 | always @ (posedge crcinclk or posedge reset) begin 77 | if (reset) begin 78 | crc <= 'h0000; 79 | end else begin 80 | crc[0] <= ~(crcbitin ^ ~crc[15]); 81 | crc[1] <= crc[0]; 82 | crc[2] <= crc[1]; 83 | crc[3] <= crc[2]; 84 | crc[4] <= crc[3]; 85 | crc[5] <= ~(~crc[4] ^ crcbitin ^ ~crc[15]); 86 | crc[6] <= crc[5]; 87 | crc[7] <= crc[6]; 88 | crc[8] <= crc[7]; 89 | crc[9] <= crc[8]; 90 | crc[10] <= crc[9]; 91 | crc[11] <= crc[10]; 92 | crc[12] <= ~(~crc[11] ^ crcbitin ^ ~crc[15]); 93 | crc[13] <= crc[12]; 94 | crc[14] <= crc[13]; 95 | crc[15] <= crc[14]; 96 | end // ~reset 97 | end // always 98 | 99 | endmodule 100 | 101 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/nbproject/project.properties: -------------------------------------------------------------------------------- 1 | annotation.processing.enabled=true 2 | annotation.processing.enabled.in.editor=false 3 | annotation.processing.processors.list= 4 | annotation.processing.run.all.processors=true 5 | annotation.processing.source.output=${build.generated.sources.dir}/ap-source-output 6 | application.title=LowPower 7 | application.vendor=deathmonkey 8 | build.classes.dir=${build.dir}/classes 9 | build.classes.excludes=**/*.java,**/*.form 10 | # This directory is removed when the project is cleaned: 11 | build.dir=build 12 | build.generated.dir=${build.dir}/generated 13 | build.generated.sources.dir=${build.dir}/generated-sources 14 | # Only compile against the classpath explicitly listed here: 15 | build.sysclasspath=ignore 16 | build.test.classes.dir=${build.dir}/test/classes 17 | build.test.results.dir=${build.dir}/test/results 18 | # Uncomment to specify the preferred debugger connection transport: 19 | #debug.transport=dt_socket 20 | debug.classpath=\ 21 | ${run.classpath} 22 | debug.test.classpath=\ 23 | ${run.test.classpath} 24 | # Files in build.classes.dir which should be excluded from distribution jar 25 | dist.archive.excludes= 26 | # This directory is removed when the project is cleaned: 27 | dist.dir=dist 28 | dist.jar=${dist.dir}/LowPower.jar 29 | dist.javadoc.dir=${dist.dir}/javadoc 30 | endorsed.classpath= 31 | excludes= 32 | file.reference.RXTXcomm-2.2pre2.jar=/usr/share/java/RXTXcomm-2.2pre2.jar 33 | file.reference.RXTXcomm.jar=/usr/share/java/RXTXcomm.jar 34 | includes=** 35 | jar.compress=false 36 | javac.classpath=\ 37 | ${file.reference.RXTXcomm-2.2pre2.jar}:\ 38 | ${file.reference.RXTXcomm.jar} 39 | # Space-separated list of extra javac options 40 | javac.compilerargs= 41 | javac.deprecation=false 42 | javac.processorpath=\ 43 | ${javac.classpath} 44 | javac.source=1.7 45 | javac.target=1.7 46 | javac.test.classpath=\ 47 | ${javac.classpath}:\ 48 | ${build.classes.dir} 49 | javac.test.processorpath=\ 50 | ${javac.test.classpath} 51 | javadoc.additionalparam= 52 | javadoc.author=false 53 | javadoc.encoding=${source.encoding} 54 | javadoc.noindex=false 55 | javadoc.nonavbar=false 56 | javadoc.notree=false 57 | javadoc.private=false 58 | javadoc.splitindex=true 59 | javadoc.use=true 60 | javadoc.version=false 61 | javadoc.windowtitle= 62 | main.class=lowpower.LowPower 63 | manifest.file=manifest.mf 64 | meta.inf.dir=${src.dir}/META-INF 65 | mkdist.disabled=false 66 | platform.active=default_platform 67 | run.classpath=\ 68 | ${javac.classpath}:\ 69 | ${build.classes.dir} 70 | # Space-separated list of JVM arguments used when running the project. 71 | # You may also define separate properties like run-sys-prop.name=value instead of -Dname=value. 72 | # To set system properties for unit tests define test-sys-prop.name=value: 73 | run.jvmargs= 74 | run.test.classpath=\ 75 | ${javac.test.classpath}:\ 76 | ${build.test.classes.dir} 77 | source.encoding=UTF-8 78 | src.dir=src 79 | test.src.dir=test 80 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/nbproject/project.properties: -------------------------------------------------------------------------------- 1 | annotation.processing.enabled=true 2 | annotation.processing.enabled.in.editor=false 3 | annotation.processing.processors.list= 4 | annotation.processing.run.all.processors=true 5 | annotation.processing.source.output=${build.generated.sources.dir}/ap-source-output 6 | application.title=ClientLowPower 7 | application.vendor=deathmonkey 8 | build.classes.dir=${build.dir}/classes 9 | build.classes.excludes=**/*.java,**/*.form 10 | # This directory is removed when the project is cleaned: 11 | build.dir=build 12 | build.generated.dir=${build.dir}/generated 13 | build.generated.sources.dir=${build.dir}/generated-sources 14 | # Only compile against the classpath explicitly listed here: 15 | build.sysclasspath=ignore 16 | build.test.classes.dir=${build.dir}/test/classes 17 | build.test.results.dir=${build.dir}/test/results 18 | # Uncomment to specify the preferred debugger connection transport: 19 | #debug.transport=dt_socket 20 | debug.classpath=\ 21 | ${run.classpath} 22 | debug.test.classpath=\ 23 | ${run.test.classpath} 24 | # Files in build.classes.dir which should be excluded from distribution jar 25 | dist.archive.excludes= 26 | # This directory is removed when the project is cleaned: 27 | dist.dir=dist 28 | dist.jar=${dist.dir}/ClientLowPower.jar 29 | dist.javadoc.dir=${dist.dir}/javadoc 30 | endorsed.classpath= 31 | excludes= 32 | file.reference.RXTXcomm-2.2pre2.jar=/usr/share/java/RXTXcomm-2.2pre2.jar 33 | file.reference.RXTXcomm.jar=/usr/share/java/RXTXcomm.jar 34 | includes=** 35 | jar.compress=false 36 | javac.classpath=\ 37 | ${file.reference.RXTXcomm-2.2pre2.jar}:\ 38 | ${file.reference.RXTXcomm.jar} 39 | # Space-separated list of extra javac options 40 | javac.compilerargs= 41 | javac.deprecation=false 42 | javac.processorpath=\ 43 | ${javac.classpath} 44 | javac.source=1.7 45 | javac.target=1.7 46 | javac.test.classpath=\ 47 | ${javac.classpath}:\ 48 | ${build.classes.dir} 49 | javac.test.processorpath=\ 50 | ${javac.test.classpath} 51 | javadoc.additionalparam= 52 | javadoc.author=false 53 | javadoc.encoding=${source.encoding} 54 | javadoc.noindex=false 55 | javadoc.nonavbar=false 56 | javadoc.notree=false 57 | javadoc.private=false 58 | javadoc.splitindex=true 59 | javadoc.use=true 60 | javadoc.version=false 61 | javadoc.windowtitle= 62 | main.class=clientlowpower.ClientLowPower 63 | manifest.file=manifest.mf 64 | meta.inf.dir=${src.dir}/META-INF 65 | mkdist.disabled=false 66 | platform.active=default_platform 67 | run.classpath=\ 68 | ${javac.classpath}:\ 69 | ${build.classes.dir} 70 | # Space-separated list of JVM arguments used when running the project. 71 | # You may also define separate properties like run-sys-prop.name=value instead of -Dname=value. 72 | # To set system properties for unit tests define test-sys-prop.name=value: 73 | run.jvmargs= 74 | run.test.classpath=\ 75 | ${javac.test.classpath}:\ 76 | ${build.test.classes.dir} 77 | source.encoding=UTF-8 78 | src.dir=src 79 | test.src.dir=test 80 | -------------------------------------------------------------------------------- /FIFO/modelsim.ini: -------------------------------------------------------------------------------- 1 | [Library] 2 | work = ./modelsim_work 3 | 4 | others =${MODEL_TECH}/../modelsim.ini 5 | 6 | [vcom] 7 | ; Turn of case sensitivity 8 | ObjectsCaseSensitive = 0 9 | 10 | ; Echo the VHDL source line with the error message (default is 0) 11 | ; Show_Source = 1 12 | 13 | ; Turn off various categories of compiler warnings (default is 1) 14 | ; Show_Warning1 = 0 15 | ; Show_Warning2 = 0 16 | ; Show_Warning3 = 0 17 | ; Show_Warning4 = 0 18 | ; Show_Warning5 = 0 19 | 20 | ; Turn off IEEE std_logic_1164 package optimization (default is 1) 21 | ; Optimize_1164 = 0 22 | 23 | ; Turn on VHDL1993 as the default (default is 0) 24 | VHDL93 = 1 25 | 26 | ; Turn on the -explicit option (default is 0) 27 | Explicit = 1 28 | ; Turn on the synthesis check to find sensitivity list problems (default is 0) 29 | ;CheckSynthesis = 1 30 | 31 | NoDebug = 0 32 | CheckSynthesis = 0 33 | NoVitalCheck = 0 34 | Optimize_1164 = 1 35 | NoVital = 0 36 | Quiet = 0 37 | Show_source = 0 38 | Show_Warning1 = 1 39 | Show_Warning2 = 1 40 | Show_Warning3 = 1 41 | Show_Warning4 = 1 42 | Show_Warning5 = 1 43 | [vsim] 44 | main_window_pos = 25 25 528 264 45 | ; Default run length 46 | RunLength = 100 47 | 48 | ; Iterations that can be run without advancing simulation time 49 | IterationLimit = 5000 50 | 51 | ; Simulator resolution 52 | Resolution = ns 53 | 54 | ; Stop the simulator after an assertion message 55 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 56 | BreakOnAssertion = 3 57 | 58 | ; List Translation 59 | ; Map an enumerated value to 0, 1, or Z. Default is 'X'; 60 | List0 = '0' FALSE 'L' 61 | List1 = '1' TRUE 'H' 62 | ListZ = 'Z' 63 | 64 | ; Default Force Kind 65 | ; Choices are freeze, drive, or deposit 66 | ; DefaultForceKind = freeze 67 | 68 | ; Force Translation 69 | ; Map 1s and 0s to the enumerated value 70 | Force0 = '0' FALSE 71 | Force1 = '1' TRUE 72 | 73 | ; Default radix for all windows and commands... 74 | ; 0 = symbolic, 2 = binary, 8 = octal, 10 = decimal, 16 = hex 75 | DefaultRadix = 16 76 | 77 | ; This controls the number of characters of a signal name 78 | ; shown in the waveform window. The default value or a 79 | ; value of zero tells VSIM to display the full name. 80 | WaveSignalNameWidth = 25 81 | 82 | ; VSIM Startup command 83 | ; Startup = do startup.do 84 | 85 | ; Save the command window contents to this file 86 | TranscriptFile = transcript 87 | 88 | ; Disable assertion messages 89 | ; ignoreNote = 1 90 | ignoreWarning = 1 91 | ; ignoreError = 1 92 | ; ignoreFailure = 1 93 | 94 | ; If zero, open files when elaborated 95 | ; else open files on first read or write 96 | ; DelayFileOpen = 0 97 | 98 | ; Set tabwidth for the source window (default is 4) 99 | ; TabWidth = 8 100 | 101 | ; window positions 102 | structure_window_pos = 265 1 257 434 103 | signal_window_pos = 265 258 272 327 104 | process_window_pos = 699 1 257 198 105 | variable_window_pos = 592 258 272 305 106 | source_window_pos = 1 529 622 305 107 | list_window_pos = 673 529 622 224 108 | wave_window_pos = 306 529 622 367 109 | 110 | ; List of object libraries to search for C interface 111 | ForeignLibs = /usr/lib/libc.a 112 | 113 | [lmc] 114 | ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software 115 | ;libsm = $MODEL_TECH/libsm.sl 116 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 117 | libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 118 | [vlog] 119 | Quiet = 0 120 | Show_source = 0 121 | NoDebug = 0 122 | Hazard = 0 123 | UpCase = 0 124 | -------------------------------------------------------------------------------- /I2C/modelsim.ini: -------------------------------------------------------------------------------- 1 | [Library] 2 | work = ./modelsim_work 3 | 4 | others =${MODEL_TECH}/../modelsim.ini 5 | 6 | [vcom] 7 | ; Turn of case sensitivity 8 | ObjectsCaseSensitive = 0 9 | 10 | ; Echo the VHDL source line with the error message (default is 0) 11 | ; Show_Source = 1 12 | 13 | ; Turn off various categories of compiler warnings (default is 1) 14 | ; Show_Warning1 = 0 15 | ; Show_Warning2 = 0 16 | ; Show_Warning3 = 0 17 | ; Show_Warning4 = 0 18 | ; Show_Warning5 = 0 19 | 20 | ; Turn off IEEE std_logic_1164 package optimization (default is 1) 21 | ; Optimize_1164 = 0 22 | 23 | ; Turn on VHDL1993 as the default (default is 0) 24 | VHDL93 = 1 25 | 26 | ; Turn on the -explicit option (default is 0) 27 | Explicit = 1 28 | ; Turn on the synthesis check to find sensitivity list problems (default is 0) 29 | ;CheckSynthesis = 1 30 | 31 | NoDebug = 0 32 | CheckSynthesis = 0 33 | NoVitalCheck = 0 34 | Optimize_1164 = 1 35 | NoVital = 0 36 | Quiet = 0 37 | Show_source = 0 38 | Show_Warning1 = 1 39 | Show_Warning2 = 1 40 | Show_Warning3 = 1 41 | Show_Warning4 = 1 42 | Show_Warning5 = 1 43 | [vsim] 44 | main_window_pos = 25 25 528 264 45 | ; Default run length 46 | RunLength = 100 47 | 48 | ; Iterations that can be run without advancing simulation time 49 | IterationLimit = 5000 50 | 51 | ; Simulator resolution 52 | Resolution = ns 53 | 54 | ; Stop the simulator after an assertion message 55 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 56 | BreakOnAssertion = 3 57 | 58 | ; List Translation 59 | ; Map an enumerated value to 0, 1, or Z. Default is 'X'; 60 | List0 = '0' FALSE 'L' 61 | List1 = '1' TRUE 'H' 62 | ListZ = 'Z' 63 | 64 | ; Default Force Kind 65 | ; Choices are freeze, drive, or deposit 66 | ; DefaultForceKind = freeze 67 | 68 | ; Force Translation 69 | ; Map 1s and 0s to the enumerated value 70 | Force0 = '0' FALSE 71 | Force1 = '1' TRUE 72 | 73 | ; Default radix for all windows and commands... 74 | ; 0 = symbolic, 2 = binary, 8 = octal, 10 = decimal, 16 = hex 75 | DefaultRadix = 16 76 | 77 | ; This controls the number of characters of a signal name 78 | ; shown in the waveform window. The default value or a 79 | ; value of zero tells VSIM to display the full name. 80 | WaveSignalNameWidth = 25 81 | 82 | ; VSIM Startup command 83 | ; Startup = do startup.do 84 | 85 | ; Save the command window contents to this file 86 | TranscriptFile = transcript 87 | 88 | ; Disable assertion messages 89 | ; ignoreNote = 1 90 | ignoreWarning = 1 91 | ; ignoreError = 1 92 | ; ignoreFailure = 1 93 | 94 | ; If zero, open files when elaborated 95 | ; else open files on first read or write 96 | ; DelayFileOpen = 0 97 | 98 | ; Set tabwidth for the source window (default is 4) 99 | ; TabWidth = 8 100 | 101 | ; window positions 102 | structure_window_pos = 265 1 257 434 103 | signal_window_pos = 265 258 272 327 104 | process_window_pos = 699 1 257 198 105 | variable_window_pos = 592 258 272 305 106 | source_window_pos = 1 529 622 305 107 | list_window_pos = 673 529 622 224 108 | wave_window_pos = 306 529 622 367 109 | 110 | ; List of object libraries to search for C interface 111 | ForeignLibs = /usr/lib/libc.a 112 | 113 | [lmc] 114 | ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software 115 | ;libsm = $MODEL_TECH/libsm.sl 116 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 117 | libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 118 | [vlog] 119 | Quiet = 0 120 | Show_source = 0 121 | NoDebug = 0 122 | Hazard = 0 123 | UpCase = 0 124 | -------------------------------------------------------------------------------- /OLD/I2C/modelsim.ini: -------------------------------------------------------------------------------- 1 | [Library] 2 | work = ./modelsim_work 3 | 4 | others =${MODEL_TECH}/../modelsim.ini 5 | 6 | [vcom] 7 | ; Turn of case sensitivity 8 | ObjectsCaseSensitive = 0 9 | 10 | ; Echo the VHDL source line with the error message (default is 0) 11 | ; Show_Source = 1 12 | 13 | ; Turn off various categories of compiler warnings (default is 1) 14 | ; Show_Warning1 = 0 15 | ; Show_Warning2 = 0 16 | ; Show_Warning3 = 0 17 | ; Show_Warning4 = 0 18 | ; Show_Warning5 = 0 19 | 20 | ; Turn off IEEE std_logic_1164 package optimization (default is 1) 21 | ; Optimize_1164 = 0 22 | 23 | ; Turn on VHDL1993 as the default (default is 0) 24 | VHDL93 = 1 25 | 26 | ; Turn on the -explicit option (default is 0) 27 | Explicit = 1 28 | ; Turn on the synthesis check to find sensitivity list problems (default is 0) 29 | ;CheckSynthesis = 1 30 | 31 | NoDebug = 0 32 | CheckSynthesis = 0 33 | NoVitalCheck = 0 34 | Optimize_1164 = 1 35 | NoVital = 0 36 | Quiet = 0 37 | Show_source = 0 38 | Show_Warning1 = 1 39 | Show_Warning2 = 1 40 | Show_Warning3 = 1 41 | Show_Warning4 = 1 42 | Show_Warning5 = 1 43 | [vsim] 44 | main_window_pos = 25 25 528 264 45 | ; Default run length 46 | RunLength = 100 47 | 48 | ; Iterations that can be run without advancing simulation time 49 | IterationLimit = 5000 50 | 51 | ; Simulator resolution 52 | Resolution = ns 53 | 54 | ; Stop the simulator after an assertion message 55 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 56 | BreakOnAssertion = 3 57 | 58 | ; List Translation 59 | ; Map an enumerated value to 0, 1, or Z. Default is 'X'; 60 | List0 = '0' FALSE 'L' 61 | List1 = '1' TRUE 'H' 62 | ListZ = 'Z' 63 | 64 | ; Default Force Kind 65 | ; Choices are freeze, drive, or deposit 66 | ; DefaultForceKind = freeze 67 | 68 | ; Force Translation 69 | ; Map 1s and 0s to the enumerated value 70 | Force0 = '0' FALSE 71 | Force1 = '1' TRUE 72 | 73 | ; Default radix for all windows and commands... 74 | ; 0 = symbolic, 2 = binary, 8 = octal, 10 = decimal, 16 = hex 75 | DefaultRadix = 16 76 | 77 | ; This controls the number of characters of a signal name 78 | ; shown in the waveform window. The default value or a 79 | ; value of zero tells VSIM to display the full name. 80 | WaveSignalNameWidth = 25 81 | 82 | ; VSIM Startup command 83 | ; Startup = do startup.do 84 | 85 | ; Save the command window contents to this file 86 | TranscriptFile = transcript 87 | 88 | ; Disable assertion messages 89 | ; ignoreNote = 1 90 | ignoreWarning = 1 91 | ; ignoreError = 1 92 | ; ignoreFailure = 1 93 | 94 | ; If zero, open files when elaborated 95 | ; else open files on first read or write 96 | ; DelayFileOpen = 0 97 | 98 | ; Set tabwidth for the source window (default is 4) 99 | ; TabWidth = 8 100 | 101 | ; window positions 102 | structure_window_pos = 265 1 257 434 103 | signal_window_pos = 265 258 272 327 104 | process_window_pos = 699 1 257 198 105 | variable_window_pos = 592 258 272 305 106 | source_window_pos = 1 529 622 305 107 | list_window_pos = 673 529 622 224 108 | wave_window_pos = 306 529 622 367 109 | 110 | ; List of object libraries to search for C interface 111 | ForeignLibs = /usr/lib/libc.a 112 | 113 | [lmc] 114 | ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software 115 | ;libsm = $MODEL_TECH/libsm.sl 116 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 117 | libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 118 | [vlog] 119 | Quiet = 0 120 | Show_source = 0 121 | NoDebug = 0 122 | Hazard = 0 123 | UpCase = 0 124 | -------------------------------------------------------------------------------- /OLD/I2C/test/modelsim.ini: -------------------------------------------------------------------------------- 1 | [Library] 2 | work = ./modelsim_work 3 | 4 | others =${MODEL_TECH}/../modelsim.ini 5 | 6 | [vcom] 7 | ; Turn of case sensitivity 8 | ObjectsCaseSensitive = 0 9 | 10 | ; Echo the VHDL source line with the error message (default is 0) 11 | ; Show_Source = 1 12 | 13 | ; Turn off various categories of compiler warnings (default is 1) 14 | ; Show_Warning1 = 0 15 | ; Show_Warning2 = 0 16 | ; Show_Warning3 = 0 17 | ; Show_Warning4 = 0 18 | ; Show_Warning5 = 0 19 | 20 | ; Turn off IEEE std_logic_1164 package optimization (default is 1) 21 | ; Optimize_1164 = 0 22 | 23 | ; Turn on VHDL1993 as the default (default is 0) 24 | VHDL93 = 1 25 | 26 | ; Turn on the -explicit option (default is 0) 27 | Explicit = 1 28 | ; Turn on the synthesis check to find sensitivity list problems (default is 0) 29 | ;CheckSynthesis = 1 30 | 31 | NoDebug = 0 32 | CheckSynthesis = 0 33 | NoVitalCheck = 0 34 | Optimize_1164 = 1 35 | NoVital = 0 36 | Quiet = 0 37 | Show_source = 0 38 | Show_Warning1 = 1 39 | Show_Warning2 = 1 40 | Show_Warning3 = 1 41 | Show_Warning4 = 1 42 | Show_Warning5 = 1 43 | [vsim] 44 | main_window_pos = 25 25 528 264 45 | ; Default run length 46 | RunLength = 100 47 | 48 | ; Iterations that can be run without advancing simulation time 49 | IterationLimit = 5000 50 | 51 | ; Simulator resolution 52 | Resolution = ns 53 | 54 | ; Stop the simulator after an assertion message 55 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 56 | BreakOnAssertion = 3 57 | 58 | ; List Translation 59 | ; Map an enumerated value to 0, 1, or Z. Default is 'X'; 60 | List0 = '0' FALSE 'L' 61 | List1 = '1' TRUE 'H' 62 | ListZ = 'Z' 63 | 64 | ; Default Force Kind 65 | ; Choices are freeze, drive, or deposit 66 | ; DefaultForceKind = freeze 67 | 68 | ; Force Translation 69 | ; Map 1s and 0s to the enumerated value 70 | Force0 = '0' FALSE 71 | Force1 = '1' TRUE 72 | 73 | ; Default radix for all windows and commands... 74 | ; 0 = symbolic, 2 = binary, 8 = octal, 10 = decimal, 16 = hex 75 | DefaultRadix = 16 76 | 77 | ; This controls the number of characters of a signal name 78 | ; shown in the waveform window. The default value or a 79 | ; value of zero tells VSIM to display the full name. 80 | WaveSignalNameWidth = 25 81 | 82 | ; VSIM Startup command 83 | ; Startup = do startup.do 84 | 85 | ; Save the command window contents to this file 86 | TranscriptFile = transcript 87 | 88 | ; Disable assertion messages 89 | ; ignoreNote = 1 90 | ignoreWarning = 1 91 | ; ignoreError = 1 92 | ; ignoreFailure = 1 93 | 94 | ; If zero, open files when elaborated 95 | ; else open files on first read or write 96 | ; DelayFileOpen = 0 97 | 98 | ; Set tabwidth for the source window (default is 4) 99 | ; TabWidth = 8 100 | 101 | ; window positions 102 | structure_window_pos = 265 1 257 434 103 | signal_window_pos = 265 258 272 327 104 | process_window_pos = 699 1 257 198 105 | variable_window_pos = 592 258 272 305 106 | source_window_pos = 1 529 622 305 107 | list_window_pos = 673 529 622 224 108 | wave_window_pos = 306 529 622 367 109 | 110 | ; List of object libraries to search for C interface 111 | ForeignLibs = /usr/lib/libc.a 112 | 113 | [lmc] 114 | ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software 115 | ;libsm = $MODEL_TECH/libsm.sl 116 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 117 | libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 118 | [vlog] 119 | Quiet = 0 120 | Show_source = 0 121 | NoDebug = 0 122 | Hazard = 0 123 | UpCase = 0 124 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/build.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Builds, tests, and runs the project LowPower. 12 | 13 | 73 | 74 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/build.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Builds, tests, and runs the project ClientLowPower. 12 | 13 | 73 | 74 | -------------------------------------------------------------------------------- /rfid-verilog/tag/cmdparser.v: -------------------------------------------------------------------------------- 1 | 2 | // Command Parser: Parses reader command and signals packet completion. 3 | // Copyright 2010 University of Washington 4 | // License: http://creativecommons.org/licenses/by/3.0/ 5 | // 2008 Dan Yeager and Oliver C. 6 | 7 | // This module also parses the query tx settings. 8 | // This should be moved to packetparse eventually. 9 | // (possibly along with the cmd parsing) 10 | 11 | module cmdparser (reset, bitin, bitclk, cmd_out, packet_complete_out, cmd_complete, 12 | m, trext, dr); 13 | 14 | input reset, bitin, bitclk; 15 | output packet_complete_out, cmd_complete; 16 | output [8:0] cmd_out; 17 | output [1:0] m; 18 | output trext, dr; 19 | 20 | reg packet_complete_out; 21 | wire [8:0] cmd_out; 22 | wire packet_complete, cmd_complete; 23 | reg [7:0] cmd; 24 | wire [7:0] new_cmd; 25 | reg [5:0] count; 26 | reg [1:0] m; 27 | reg trext, dr; // modulation settings from query 28 | 29 | always @ (posedge bitclk or posedge reset) begin 30 | if(reset) begin 31 | count <= 0; 32 | cmd <= 0; 33 | m <= 0; 34 | dr <= 0; 35 | trext <= 0; 36 | packet_complete_out <= 0; 37 | end else begin 38 | cmd <= new_cmd; 39 | count <= count + 6'd1; 40 | packet_complete_out <= packet_complete; // clear up glitching? 41 | 42 | if(cmd_out[2] && count == 4) dr <= bitin; 43 | if(cmd_out[2] && count == 5) m[1] <= bitin; 44 | if(cmd_out[2] && count == 6) m[0] <= bitin; 45 | if(cmd_out[2] && count == 7) trext <= bitin; 46 | end 47 | end 48 | 49 | 50 | assign cmd_complete = (cmd_out > 0); 51 | 52 | // we are gating this signal, so update it 1 count early 53 | // causing the complete to occur on the last bit pos edge. 54 | assign packet_complete = ((cmd_out[0] && count >= 3 ) || // QueryRep 55 | (cmd_out[1] && count >= 17) || // Ack 56 | (cmd_out[2] && count >= 21) || // Query 57 | (cmd_out[3] && count >= 8 ) || // QueryAdj 58 | (cmd_out[4] && count >= 44) || // Select 59 | (cmd_out[5] && count >= 7 ) || // Nack 60 | (cmd_out[6] && count >= 39) || // ReqRN 61 | (cmd_out[7] && count >= 57) || // Read 62 | (cmd_out[8] && count >= 58)); // Write 63 | 64 | 65 | assign cmd_out[0] = (count >= 2 && ~cmd[0] && ~cmd[1]); // QueryRep 66 | assign cmd_out[1] = (count >= 2 && ~cmd[0] && cmd[1]); // Ack 67 | assign cmd_out[2] = (count >= 4 && cmd[0] && ~cmd[1] && ~cmd[2] && ~cmd[3]); // query 68 | assign cmd_out[3] = (count >= 4 && cmd[0] && ~cmd[1] && ~cmd[2] && cmd[3]); // QueryAdj 69 | assign cmd_out[4] = (count >= 4 && cmd[0] && ~cmd[1] && cmd[2] && ~cmd[3]); // Select 70 | assign cmd_out[5] = (count >= 8 && cmd[0] && cmd[1] && ~cmd[6] && ~cmd[7]); //Nack 71 | assign cmd_out[6] = (count >= 8 && cmd[0] && cmd[1] && ~cmd[6] && cmd[7]); // RegRN 72 | assign cmd_out[7] = (count >= 8 && cmd[0] && cmd[1] && cmd[6] && ~cmd[7]); // Read 73 | assign cmd_out[8] = (count >= 8 && cmd[0] && cmd[1] && cmd[6] && cmd[7]); // Write 74 | 75 | assign new_cmd[0] = (count==0) ? bitin : cmd[0]; 76 | assign new_cmd[1] = (count==1) ? bitin : cmd[1]; 77 | assign new_cmd[2] = (count==2 && !cmd_complete) ? bitin : cmd[2]; 78 | assign new_cmd[3] = (count==3 && !cmd_complete) ? bitin : cmd[3]; 79 | assign new_cmd[4] = (count==4 && !cmd_complete) ? bitin : cmd[4]; 80 | assign new_cmd[5] = (count==5 && !cmd_complete) ? bitin : cmd[5]; 81 | assign new_cmd[6] = (count==6 && !cmd_complete) ? bitin : cmd[6]; 82 | assign new_cmd[7] = (count==7 && !cmd_complete) ? bitin : cmd[7]; 83 | 84 | 85 | endmodule 86 | 87 | 88 | 89 | -------------------------------------------------------------------------------- /Arduino/InProgress/LowPower/src/lowpower/LowPower.java: -------------------------------------------------------------------------------- 1 | /* 2 | * To change this license header, choose License Headers in Project Properties. 3 | * To change this template file, choose Tools | Templates 4 | * and open the template in the editor. 5 | */ 6 | package lowpower; 7 | 8 | import gnu.io.CommPort; 9 | import gnu.io.CommPortIdentifier; 10 | import gnu.io.NoSuchPortException; 11 | import gnu.io.PortInUseException; 12 | import gnu.io.SerialPort; 13 | import gnu.io.UnsupportedCommOperationException; 14 | 15 | import java.io.IOException; 16 | import java.io.InputStream; 17 | import java.io.OutputStream; 18 | 19 | /** 20 | * 21 | * @author deathmonkey 22 | */ 23 | public class LowPower { 24 | 25 | public LowPower() { 26 | super(); 27 | } 28 | 29 | void connect(String portName) throws NoSuchPortException, PortInUseException, UnsupportedCommOperationException, IOException 30 | { 31 | CommPortIdentifier portIdentifier = CommPortIdentifier.getPortIdentifier(portName); 32 | System.out.println("portIdentifier: " + portIdentifier.toString()); 33 | if (portIdentifier.isCurrentlyOwned()) 34 | { 35 | System.out.println("Error: Port is currently in use"); 36 | } 37 | else 38 | { 39 | CommPort commPort = portIdentifier.open(this.getClass().getName(), 2000); 40 | System.out.println("comPort: "+ commPort.toString()); 41 | if (commPort instanceof SerialPort) 42 | { 43 | SerialPort serialPort = (SerialPort) commPort; 44 | System.out.println("serialPort: " + serialPort.getName()); 45 | serialPort.setSerialPortParams(9600, SerialPort.DATABITS_8, SerialPort.STOPBITS_1, SerialPort.PARITY_NONE); 46 | 47 | InputStream in = serialPort.getInputStream(); 48 | OutputStream out = serialPort.getOutputStream(); 49 | 50 | (new Thread(new SerialReader(in))).start(); 51 | (new Thread(new SerialWriter(out))).start(); 52 | 53 | } else { 54 | System.out.println("Error: Only serial ports are handled"); 55 | } 56 | } 57 | 58 | } 59 | 60 | private static class SerialReader implements Runnable { 61 | 62 | InputStream in; 63 | 64 | public SerialReader(InputStream in) { 65 | this.in = in; 66 | } 67 | 68 | @Override 69 | public void run() { 70 | byte[] buffer = new byte[1024]; 71 | int len = -1; 72 | try { 73 | while ((len = this.in.read(buffer)) > -1) { 74 | System.out.print(new String(buffer, 0, len)); 75 | } 76 | } catch (IOException e) { 77 | e.printStackTrace(); 78 | } 79 | 80 | } 81 | } 82 | 83 | private static class SerialWriter implements Runnable { 84 | 85 | OutputStream out; 86 | 87 | public SerialWriter(OutputStream out) { 88 | this.out = out; 89 | } 90 | 91 | @Override 92 | public void run() { 93 | try { 94 | int c = 0; 95 | while ((c = System.in.read()) > -1) { 96 | this.out.write(c); 97 | } 98 | } catch (IOException e) { 99 | e.printStackTrace(); 100 | } 101 | } 102 | } 103 | 104 | /** 105 | * @param args the command line arguments 106 | */ 107 | public static void main(String[] args) { 108 | // TODO code application logic here 109 | try 110 | { 111 | (new LowPower()).connect("/dev/ttyACM0"); 112 | } 113 | catch( Exception e) 114 | { 115 | e.printStackTrace(); 116 | } 117 | } 118 | } 119 | -------------------------------------------------------------------------------- /rfid-verilog/tag/toptest.v: -------------------------------------------------------------------------------- 1 | 2 | // FGPA Test of TOP functional block. 3 | // Copyright 2010 University of Washington 4 | // License: http://creativecommons.org/licenses/by/3.0/ 5 | // 2008 Dan Yeager 6 | 7 | // Maps FPGA IO onto RFID tag (top.v) 8 | 9 | module toptest(LEDR, LEDG, GPIO_0, KEY, SW, EXT_CLOCK, 10 | HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7); 11 | input [3:0] KEY; 12 | inout [35:0] GPIO_0; 13 | output [17:0] LEDR; 14 | output [8:0] LEDG; 15 | input EXT_CLOCK; 16 | input [17:0] SW; 17 | output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7; 18 | 19 | // basic tag IO 20 | wire clk, reset, demodin, modout; 21 | 22 | 23 | // Functionality control 24 | wire use_uid, use_q, comm_enable; 25 | 26 | // read data connections 27 | wire adc_sample_ctl, adc_sample_clk, adc_sample_datain; 28 | wire msp_sample_ctl, msp_sample_clk, msp_sample_datain; 29 | 30 | // write data connections 31 | wire writedataout, writedataclk; 32 | 33 | // EPC ID source 34 | wire [7:0] uid_byte_in; 35 | wire [3:0] uid_addr_out; 36 | wire uid_clk_out; 37 | 38 | // debugging connections 39 | wire debug_clk, debug_out; 40 | 41 | assign debug_clk = SW[5]; 42 | 43 | assign GPIO_0[35:3] = 33'bZ; 44 | 45 | // Basic tag connections 46 | assign clk = EXT_CLOCK; 47 | assign reset = ~KEY[1]; 48 | assign demodin = GPIO_0[3]; 49 | 50 | assign use_q = SW[4]; 51 | assign comm_enable = SW[3]; 52 | assign use_uid = SW[2]; 53 | assign uid_byte_in = SW[17:10]; 54 | 55 | // adc connections 56 | assign msp_sample_datain = SW[1]; 57 | assign adc_sample_datain = SW[0]; 58 | 59 | /* 60 | // for debugging purposes: hold on to packet type after rx reset. 61 | reg [8:0] rx_packet_reg; 62 | wire [8:0] rx_packet; 63 | always @ (posedge cmd_complete or posedge reset) begin 64 | if (reset) rx_packet_reg <= 0; 65 | else rx_packet_reg <= rx_packet; 66 | end 67 | 68 | wire [1:0] readwritebank; 69 | wire [7:0] readwriteptr; 70 | wire [7:0] readwords; 71 | reg [1:0] readwritebank_reg; 72 | reg [7:0] readwriteptr_reg; 73 | reg [7:0] readwords_reg; 74 | always @ (posedge packet_complete or posedge reset) begin 75 | if (reset) begin 76 | readwritebank_reg <= 0; 77 | readwriteptr_reg <= 0; 78 | readwords_reg <= 0; 79 | end else if (rx_packet_reg[7] | rx_packet_reg[8]) begin 80 | readwritebank_reg <= readwritebank; 81 | readwriteptr_reg <= readwriteptr; 82 | readwords_reg <= readwords; 83 | end 84 | end 85 | */ 86 | 87 | // red LED debugging connections 88 | assign LEDR[17] = reset; // assign reset to LED for sanity check. 89 | assign LEDR[16] = 0; 90 | assign LEDR[15] = 0; 91 | assign LEDR[14] = 0; 92 | assign LEDR[13] = 0; 93 | assign LEDR[12] = 0; 94 | assign LEDR[11] = 0; 95 | assign LEDR[10:4] = 0; 96 | assign LEDR[3] = 0; 97 | assign LEDR[2] = 0; 98 | assign LEDR[1:0] = 0; 99 | 100 | assign LEDG[8:0] = 0; 101 | 102 | assign GPIO_0[2] = modout; 103 | assign GPIO_0[1] = debug_clk; 104 | assign GPIO_0[0] = debug_out; 105 | /* 106 | sevenseg U_SEG0 (HEX0,readwritebank_reg); 107 | sevenseg U_SEG1 (HEX1,readwriteptr_reg); 108 | sevenseg U_SEG2 (HEX2,readwords_reg); 109 | sevenseg U_SEG3 (HEX3,4'd3); 110 | sevenseg U_SEG4 (HEX4,slotcounter[3:0]); 111 | sevenseg U_SEG5 (HEX5,slotcounter[7:4]); 112 | sevenseg U_SEG6 (HEX6,slotcounter[11:8]); 113 | sevenseg U_SEG7 (HEX7,{1'b0,slotcounter[14:12]}); 114 | */ 115 | 116 | top U_TOP (reset, clk, demodin, modout, // regular IO 117 | adc_sample_ctl, adc_sample_clk, adc_sample_datain, // adc connections 118 | msp_sample_ctl, msp_sample_clk, msp_sample_datain, // msp430 connections 119 | uid_byte_in, uid_addr_out, uid_clk_out, 120 | writedataout, writedataclk, 121 | use_uid, use_q, comm_enable, 122 | debug_clk, debug_out); 123 | 124 | endmodule 125 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # There exist several targets which are by default empty and which can be 3 | # used for execution of your targets. These targets are usually executed 4 | # before and after some main targets. They are: 5 | # 6 | # .build-pre: called before 'build' target 7 | # .build-post: called after 'build' target 8 | # .clean-pre: called before 'clean' target 9 | # .clean-post: called after 'clean' target 10 | # .clobber-pre: called before 'clobber' target 11 | # .clobber-post: called after 'clobber' target 12 | # .all-pre: called before 'all' target 13 | # .all-post: called after 'all' target 14 | # .help-pre: called before 'help' target 15 | # .help-post: called after 'help' target 16 | # 17 | # Targets beginning with '.' are not intended to be called on their own. 18 | # 19 | # Main targets can be executed directly, and they are: 20 | # 21 | # build build a specific configuration 22 | # clean remove built files from a configuration 23 | # clobber remove all built files 24 | # all build all configurations 25 | # help print help mesage 26 | # 27 | # Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and 28 | # .help-impl are implemented in nbproject/makefile-impl.mk. 29 | # 30 | # Available make variables: 31 | # 32 | # CND_BASEDIR base directory for relative paths 33 | # CND_DISTDIR default top distribution directory (build artifacts) 34 | # CND_BUILDDIR default top build directory (object files, ...) 35 | # CONF name of current configuration 36 | # CND_PLATFORM_${CONF} platform name (current configuration) 37 | # CND_ARTIFACT_DIR_${CONF} directory of build artifact (current configuration) 38 | # CND_ARTIFACT_NAME_${CONF} name of build artifact (current configuration) 39 | # CND_ARTIFACT_PATH_${CONF} path to build artifact (current configuration) 40 | # CND_PACKAGE_DIR_${CONF} directory of package (current configuration) 41 | # CND_PACKAGE_NAME_${CONF} name of package (current configuration) 42 | # CND_PACKAGE_PATH_${CONF} path to package (current configuration) 43 | # 44 | # NOCDDL 45 | 46 | 47 | # Environment 48 | MKDIR=mkdir 49 | CP=cp 50 | CCADMIN=CCadmin 51 | 52 | 53 | # build 54 | build: .build-post 55 | 56 | .build-pre: 57 | # Add your pre 'build' code here... 58 | 59 | .build-post: .build-impl 60 | # Add your post 'build' code here... 61 | 62 | 63 | # clean 64 | clean: .clean-post 65 | 66 | .clean-pre: 67 | # Add your pre 'clean' code here... 68 | 69 | .clean-post: .clean-impl 70 | # Add your post 'clean' code here... 71 | 72 | 73 | # clobber 74 | clobber: .clobber-post 75 | 76 | .clobber-pre: 77 | # Add your pre 'clobber' code here... 78 | 79 | .clobber-post: .clobber-impl 80 | # Add your post 'clobber' code here... 81 | 82 | 83 | # all 84 | all: .all-post 85 | 86 | .all-pre: 87 | # Add your pre 'all' code here... 88 | 89 | .all-post: .all-impl 90 | # Add your post 'all' code here... 91 | 92 | 93 | # build tests 94 | build-tests: .build-tests-post 95 | 96 | .build-tests-pre: 97 | # Add your pre 'build-tests' code here... 98 | 99 | .build-tests-post: .build-tests-impl 100 | # Add your post 'build-tests' code here... 101 | 102 | 103 | # run tests 104 | test: .test-post 105 | 106 | .test-pre: build-tests 107 | # Add your pre 'test' code here... 108 | 109 | .test-post: .test-impl 110 | # Add your post 'test' code here... 111 | 112 | 113 | # help 114 | help: .help-post 115 | 116 | .help-pre: 117 | # Add your pre 'help' code here... 118 | 119 | .help-post: .help-impl 120 | # Add your post 'help' code here... 121 | 122 | 123 | 124 | # include project implementation makefile 125 | include nbproject/Makefile-impl.mk 126 | 127 | # include project make variables 128 | include nbproject/Makefile-variables.mk 129 | -------------------------------------------------------------------------------- /rfid-verilog/tag/sequencer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // SEQUENCER: Top level TX module. 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // Connects the TX module to its appropriate clock sources 9 | // 0. !reset 10 | // 1. Preamble is clocked until it's done flag is raised. 11 | // 2. Data is clocked until it's done flag is raised. 12 | // 3. If "docrc" input, CRC module is clocked until it's done flag is raised. 13 | // 4. Dummy "1" bit is clocked out and !txenable signal is sent to TX module. 14 | 15 | module sequencer (reset, rtcal_expired, oscclk, m, dr, docrc, trext, trcal, 16 | databitsrc, datadone, dataclk, modout, txsetupdone, txdone); 17 | 18 | input reset, rtcal_expired, trext, dr, docrc, databitsrc, datadone, oscclk; 19 | input [9:0] trcal; 20 | input [1:0] m; 21 | output dataclk, modout, txsetupdone, txdone; 22 | 23 | reg done; 24 | reg tx_stop; 25 | wire txsetupdone, txdone; 26 | 27 | // module connections 28 | wire txclk, txbitclk; 29 | wire violation; 30 | wire crcdone, preambledone; // datadone is an input 31 | wire crcinclk, crcbitin; 32 | wire txbitsrc, crcbitsrc, preamblebitsrc; // databitsrc is an input 33 | 34 | wire crcoutclk, preambleclk, dataclk; 35 | 36 | // MODULES! :) 37 | txclkdivide U_DIV (reset, oscclk, trcal, dr, txclk); 38 | tx U_TX0 (reset, rtcal_expired, tx_stop, 39 | txclk, txbitsrc, violation, m, 40 | modout, txbitclk, txsetupdone, txdone); 41 | preamble U_PRE (reset, preambleclk, m, trext, preamblebitsrc, violation, preambledone); 42 | crc16 U_CRC (reset, crcinclk, crcbitin, crcoutclk, crcbitsrc, crcdone); 43 | 44 | // state machine variables 45 | reg [1:0] state; 46 | parameter STATE_PRE = 2'd0; 47 | parameter STATE_DATA = 2'd1; 48 | parameter STATE_CRC = 2'd2; 49 | parameter STATE_END = 2'd3; 50 | 51 | // mux the bit source for the tx module 52 | wire [3:0] bitsrc; 53 | assign bitsrc[0] = preamblebitsrc; 54 | assign bitsrc[1] = databitsrc; 55 | assign bitsrc[2] = crcbitsrc; 56 | assign bitsrc[3] = 1; 57 | assign txbitsrc = bitsrc[state]; 58 | 59 | reg bit_transition; 60 | 61 | // crc gets the data bits too 62 | assign crcbitin = databitsrc; 63 | assign crcinclk = txbitclk & (state == STATE_DATA) & docrc; 64 | 65 | // send the tx module bit clock to the appropriate module 66 | // Note: Preamble and Data clocks overlap at handoffs 67 | // because these modules need 1 clock for setup. 68 | assign preambleclk = txbitclk && (state == STATE_PRE) && (!done); 69 | assign dataclk = txbitclk && (state == STATE_DATA ||(state == STATE_PRE && bit_transition && !done)); 70 | assign crcoutclk = txbitclk && (state == STATE_CRC); // crc doesn't need extra pre data clk edge. 71 | 72 | always @ (negedge txbitclk or posedge reset) begin 73 | if (reset) begin 74 | state <= 0; 75 | done <= 0; 76 | bit_transition <= 0; 77 | tx_stop <= 0; 78 | 79 | end else if (done) begin 80 | // don't do anything after we are done 81 | // wait for controller to reset us. 82 | end else if (state == STATE_PRE) begin 83 | if (bit_transition) begin 84 | state <= STATE_DATA; 85 | bit_transition <= 0; 86 | end else if (preambledone) begin 87 | bit_transition <= 1; 88 | end 89 | 90 | end else if (state == STATE_DATA) begin 91 | if (bit_transition) begin 92 | if (datadone && docrc) state <= STATE_CRC; 93 | else if (datadone) state <= STATE_END; 94 | bit_transition <= 0; 95 | end else if (datadone) begin 96 | bit_transition <= 1; 97 | end 98 | 99 | end else if (state == STATE_CRC) begin 100 | if (bit_transition) begin 101 | state <= STATE_END; 102 | bit_transition <= 0; 103 | end else if (crcdone) begin 104 | bit_transition <= 1; 105 | end 106 | 107 | end else if (state == STATE_END) begin 108 | if (txdone) begin 109 | state <= STATE_PRE; 110 | done <= 1; 111 | end else begin 112 | tx_stop <= 1; 113 | end 114 | end // no else required because states are exhaustive 115 | 116 | end 117 | 118 | 119 | endmodule 120 | -------------------------------------------------------------------------------- /rfid-verilog/tag/rx.v: -------------------------------------------------------------------------------- 1 | 2 | // RX 3 | // Copyright 2010 University of Washington 4 | // License: http://creativecommons.org/licenses/by/3.0/ 5 | // 2008 Dan Yeager 6 | 7 | // RX module converts EPC Class 1 Gen 2 time domain protocol 8 | // to a serial binary data stream 9 | // Sample bitout on bitclk positive edges. 10 | 11 | // TR cal measurement provided for TX clock calibration. 12 | // RT cal for debugging purposes and possibly adjustment 13 | // of oscillator frequency if necessary. 14 | 15 | module rx (reset, clk, demodin, bitout, bitclk, rx_overflow_reset, trcal, rngbitout); 16 | 17 | input reset, clk, demodin; 18 | output bitout, bitclk, rx_overflow_reset, rngbitout; 19 | output [9:0] trcal; 20 | 21 | reg bitout, bitclk, rngbitout; 22 | reg [9:0] trcal, rtcal; 23 | 24 | // States 25 | parameter STATE_DELIMITER = 5'd0; 26 | parameter STATE_DATA0 = 5'd1; 27 | parameter STATE_RTCAL = 5'd2; 28 | parameter STATE_TRCAL = 5'd4; 29 | parameter STATE_BITS = 5'd8; 30 | reg [4:0] commstate; 31 | 32 | parameter STATE_WAIT_DEMOD_LOW = 4'd0; 33 | parameter STATE_WAIT_DEMOD_HIGH = 4'd1; 34 | parameter STATE_EVAL_BIT = 4'd2; 35 | parameter STATE_RESET_COUNTER = 4'd4; 36 | reg [3:0] evalstate; 37 | 38 | wire[9:0] count; 39 | wire clkb; 40 | assign clkb = ~clk; 41 | reg counterreset, counterenable; 42 | wire overflow; 43 | wire counter_reset_in; 44 | assign counter_reset_in = counterreset|reset; 45 | counter10 counter (clkb, counter_reset_in, counterenable, count, overflow); 46 | assign rx_overflow_reset = overflow | ((commstate == STATE_BITS) && (count > rtcal)); 47 | 48 | always @ (posedge clk or posedge reset) begin 49 | 50 | if( reset ) begin 51 | bitout <= 0; 52 | bitclk <= 0; 53 | rtcal <= 10'd0; 54 | trcal <= 10'd0; 55 | rngbitout <= 0; 56 | counterreset <= 0; 57 | counterenable <= 0; 58 | commstate <= STATE_DELIMITER; 59 | evalstate <= STATE_WAIT_DEMOD_LOW; 60 | 61 | // process normal operation 62 | end else begin 63 | 64 | if(evalstate == STATE_WAIT_DEMOD_LOW) begin 65 | if (demodin == 0) begin 66 | evalstate <= STATE_WAIT_DEMOD_HIGH; 67 | if(commstate != STATE_DELIMITER) counterenable <= 1; 68 | else counterenable <= 0; 69 | counterreset <= 0; 70 | end 71 | 72 | end else if(evalstate == STATE_WAIT_DEMOD_HIGH) begin 73 | if (demodin == 1) begin 74 | evalstate <= STATE_EVAL_BIT; 75 | counterenable <= 1; 76 | counterreset <= 0; 77 | end 78 | 79 | end else if(evalstate == STATE_EVAL_BIT) begin 80 | counterreset <= 1; 81 | evalstate <= STATE_RESET_COUNTER; 82 | bitclk <= 0; 83 | rngbitout <= count[0]; 84 | 85 | case(commstate) 86 | STATE_DELIMITER: begin 87 | commstate <= STATE_DATA0; 88 | end 89 | STATE_DATA0: begin 90 | commstate <= STATE_RTCAL; 91 | end 92 | STATE_RTCAL: begin 93 | rtcal <= count; 94 | commstate <= STATE_TRCAL; 95 | end 96 | STATE_TRCAL: begin 97 | if(count > rtcal) begin 98 | trcal <= count; 99 | end else if(count[8:0] > rtcal[9:1]) begin // divide rtcal by 2 100 | bitout <= 1; 101 | commstate <= STATE_BITS; 102 | end else begin 103 | bitout <= 0; 104 | commstate <= STATE_BITS; 105 | end 106 | end 107 | STATE_BITS: begin 108 | if(count[8:0] > rtcal[9:1]) begin // data 1 (divide rtcal by 2) 109 | bitout <= 1; 110 | end else begin // data 0 111 | bitout <= 0; 112 | end 113 | end 114 | default: begin 115 | counterreset <= 0; 116 | commstate <= 0; 117 | end 118 | endcase // case(mode) 119 | 120 | 121 | end else if(evalstate == STATE_RESET_COUNTER) begin 122 | if(commstate == STATE_BITS) begin 123 | bitclk <= 1; 124 | end 125 | counterreset <= 0; 126 | evalstate <= STATE_WAIT_DEMOD_LOW; 127 | 128 | end else begin // unknown state, reset. 129 | evalstate <= 0; 130 | end 131 | end // ~reset 132 | end // always @ clk 133 | 134 | endmodule // 135 | 136 | -------------------------------------------------------------------------------- /rfid-verilog/reader/rfid_reader_rx.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module rfid_reader_rx ( 4 | // basic connections 5 | reset, clk, tag_backscatter, 6 | // logistics 7 | rx_done, rx_timeout, 8 | // modulation infomation 9 | miller, trext, divide_ratio, 10 | // timing information 11 | rtcal_counts, trcal_counts, tari_counts, 12 | // received data 13 | rx_data, rx_dataidx 14 | ); 15 | 16 | input reset, clk, tag_backscatter; 17 | output rx_done, rx_timeout; 18 | 19 | input [2:0] miller; 20 | input trext; 21 | input divide_ratio; 22 | 23 | input [15:0] tari_counts; 24 | input [15:0] rtcal_counts; 25 | input [15:0] trcal_counts; 26 | 27 | output [1023:0] rx_data; 28 | output [9:0] rx_dataidx; 29 | 30 | reg [1023:0] rx_data; 31 | reg [9:0] rx_dataidx; 32 | 33 | reg rx_done; 34 | 35 | // clock and recovery 36 | reg [15:0] rx_period; 37 | reg [15:0] rx_counter; 38 | 39 | // timeout detector 40 | assign rx_timeout = (rx_counter > rtcal_counts<<2); 41 | 42 | // modulator edge detector -> clock generator for bit slicer 43 | reg previousbit; 44 | reg edgeclk; 45 | reg [15:0] count; 46 | always @ (posedge clk or posedge reset) begin 47 | if (reset) begin 48 | previousbit <= 0; 49 | edgeclk <= 0; 50 | count <= 0; 51 | rx_counter <= 0; 52 | end else begin 53 | if (tag_backscatter != previousbit) begin 54 | edgeclk <= 1; 55 | previousbit <= tag_backscatter; 56 | count <= 0; 57 | end else begin 58 | edgeclk <= 0; 59 | count <= count + 1; 60 | rx_counter <= count + 1; 61 | end 62 | end 63 | end 64 | 65 | reg [4:0] rx_state; 66 | parameter STATE_CLK_UP = 0; 67 | parameter STATE_CLK_DN = 1; 68 | parameter STATE_PREAMBLE = 2; 69 | parameter STATE_DATA1 = 3; 70 | parameter STATE_DATA2 = 4; 71 | parameter STATE_DATA3 = 5; 72 | parameter STATE_DATA4 = 6; 73 | parameter STATE_DATA5 = 7; 74 | parameter STATE_DATA6 = 8; 75 | parameter STATE_DATA7 = 9; 76 | parameter STATE_DATA8 = 10; 77 | 78 | 79 | 80 | wire isfm0, ism2, ism4, ism8; 81 | assign isfm0 = (miller == 0); 82 | assign ism2 = (miller == 1); 83 | assign ism4 = (miller == 2); 84 | assign ism8 = (miller == 3); 85 | 86 | wire count_lessthan_period; 87 | assign count_lessthan_period = (rx_counter <= rx_period); 88 | 89 | wire fm0_preamble_done; 90 | assign fm0_preamble_done = (rx_dataidx >= 5); 91 | 92 | wire [15:0] rx_counter_by2; 93 | assign rx_counter_by2 = rx_counter >> 1; 94 | 95 | // bit slicer / parser 96 | always @ (posedge edgeclk or posedge reset) begin 97 | if (reset) begin 98 | rx_state <= 0; 99 | rx_dataidx <= 0; 100 | rx_data <= 0; 101 | end else begin 102 | 103 | case(rx_state) 104 | STATE_CLK_UP: begin 105 | rx_state <= STATE_CLK_DN; 106 | rx_dataidx <= 0; 107 | rx_data <= 0; 108 | end 109 | 110 | STATE_CLK_DN: begin 111 | if(isfm0 & ~trext) rx_period <= rx_counter_by2; 112 | else rx_period <= rx_counter; 113 | rx_state <= STATE_PREAMBLE; 114 | end 115 | 116 | STATE_PREAMBLE: begin 117 | if(isfm0) begin 118 | if( fm0_preamble_done ) begin 119 | rx_state <= STATE_DATA1; 120 | rx_dataidx <= 0; 121 | end else begin 122 | rx_dataidx <= rx_dataidx + 1; 123 | end 124 | end 125 | end 126 | 127 | STATE_DATA1: begin 128 | if(isfm0) begin 129 | // data 0 130 | if( count_lessthan_period ) begin 131 | rx_state <= STATE_DATA2; 132 | rx_data[rx_dataidx] <= 0; 133 | rx_dataidx <= rx_dataidx + 1; 134 | // data 1 135 | end else begin 136 | rx_data[rx_dataidx] <= 1; 137 | rx_dataidx <= rx_dataidx + 1; 138 | end 139 | end else begin // todo: 140 | // data 0 141 | if( count_lessthan_period ) begin 142 | rx_state <= STATE_DATA2; 143 | rx_data[rx_dataidx] <= 0; 144 | rx_dataidx <= rx_dataidx + 1; 145 | // data 1 146 | end else begin 147 | rx_data[rx_dataidx] <= 1; 148 | rx_dataidx <= rx_dataidx + 1; 149 | end 150 | end 151 | end 152 | STATE_DATA2: begin 153 | if(isfm0) begin 154 | rx_state <= STATE_DATA1; 155 | end else begin 156 | rx_state <= STATE_DATA1; // todo: 157 | end 158 | end 159 | 160 | default begin 161 | rx_state <= 0; 162 | end 163 | endcase 164 | 165 | end 166 | end 167 | 168 | 169 | 170 | endmodule 171 | 172 | -------------------------------------------------------------------------------- /Arduino/InProgress/CppApplication_1/nbproject/Makefile-impl.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated Makefile - do not edit! 3 | # 4 | # Edit the Makefile in the project folder instead (../Makefile). Each target 5 | # has a pre- and a post- target defined where you can add customization code. 6 | # 7 | # This makefile implements macros and targets common to all configurations. 8 | # 9 | # NOCDDL 10 | 11 | 12 | # Building and Cleaning subprojects are done by default, but can be controlled with the SUB 13 | # macro. If SUB=no, subprojects will not be built or cleaned. The following macro 14 | # statements set BUILD_SUB-CONF and CLEAN_SUB-CONF to .build-reqprojects-conf 15 | # and .clean-reqprojects-conf unless SUB has the value 'no' 16 | SUB_no=NO 17 | SUBPROJECTS=${SUB_${SUB}} 18 | BUILD_SUBPROJECTS_=.build-subprojects 19 | BUILD_SUBPROJECTS_NO= 20 | BUILD_SUBPROJECTS=${BUILD_SUBPROJECTS_${SUBPROJECTS}} 21 | CLEAN_SUBPROJECTS_=.clean-subprojects 22 | CLEAN_SUBPROJECTS_NO= 23 | CLEAN_SUBPROJECTS=${CLEAN_SUBPROJECTS_${SUBPROJECTS}} 24 | 25 | 26 | # Project Name 27 | PROJECTNAME=CppApplication_1 28 | 29 | # Active Configuration 30 | DEFAULTCONF=Debug 31 | CONF=${DEFAULTCONF} 32 | 33 | # All Configurations 34 | ALLCONFS=Debug Release 35 | 36 | 37 | # build 38 | .build-impl: .build-pre .validate-impl .depcheck-impl 39 | @#echo "=> Running $@... Configuration=$(CONF)" 40 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .build-conf 41 | 42 | 43 | # clean 44 | .clean-impl: .clean-pre .validate-impl .depcheck-impl 45 | @#echo "=> Running $@... Configuration=$(CONF)" 46 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .clean-conf 47 | 48 | 49 | # clobber 50 | .clobber-impl: .clobber-pre .depcheck-impl 51 | @#echo "=> Running $@..." 52 | for CONF in ${ALLCONFS}; \ 53 | do \ 54 | "${MAKE}" -f nbproject/Makefile-$${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .clean-conf; \ 55 | done 56 | 57 | # all 58 | .all-impl: .all-pre .depcheck-impl 59 | @#echo "=> Running $@..." 60 | for CONF in ${ALLCONFS}; \ 61 | do \ 62 | "${MAKE}" -f nbproject/Makefile-$${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .build-conf; \ 63 | done 64 | 65 | # build tests 66 | .build-tests-impl: .build-impl .build-tests-pre 67 | @#echo "=> Running $@... Configuration=$(CONF)" 68 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .build-tests-conf 69 | 70 | # run tests 71 | .test-impl: .build-tests-impl .test-pre 72 | @#echo "=> Running $@... Configuration=$(CONF)" 73 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .test-conf 74 | 75 | # dependency checking support 76 | .depcheck-impl: 77 | @echo "# This code depends on make tool being used" >.dep.inc 78 | @if [ -n "${MAKE_VERSION}" ]; then \ 79 | echo "DEPFILES=\$$(wildcard \$$(addsuffix .d, \$${OBJECTFILES}))" >>.dep.inc; \ 80 | echo "ifneq (\$${DEPFILES},)" >>.dep.inc; \ 81 | echo "include \$${DEPFILES}" >>.dep.inc; \ 82 | echo "endif" >>.dep.inc; \ 83 | else \ 84 | echo ".KEEP_STATE:" >>.dep.inc; \ 85 | echo ".KEEP_STATE_FILE:.make.state.\$${CONF}" >>.dep.inc; \ 86 | fi 87 | 88 | # configuration validation 89 | .validate-impl: 90 | @if [ ! -f nbproject/Makefile-${CONF}.mk ]; \ 91 | then \ 92 | echo ""; \ 93 | echo "Error: can not find the makefile for configuration '${CONF}' in project ${PROJECTNAME}"; \ 94 | echo "See 'make help' for details."; \ 95 | echo "Current directory: " `pwd`; \ 96 | echo ""; \ 97 | fi 98 | @if [ ! -f nbproject/Makefile-${CONF}.mk ]; \ 99 | then \ 100 | exit 1; \ 101 | fi 102 | 103 | 104 | # help 105 | .help-impl: .help-pre 106 | @echo "This makefile supports the following configurations:" 107 | @echo " ${ALLCONFS}" 108 | @echo "" 109 | @echo "and the following targets:" 110 | @echo " build (default target)" 111 | @echo " clean" 112 | @echo " clobber" 113 | @echo " all" 114 | @echo " help" 115 | @echo "" 116 | @echo "Makefile Usage:" 117 | @echo " make [CONF=] [SUB=no] build" 118 | @echo " make [CONF=] [SUB=no] clean" 119 | @echo " make [SUB=no] clobber" 120 | @echo " make [SUB=no] all" 121 | @echo " make help" 122 | @echo "" 123 | @echo "Target 'build' will build a specific configuration and, unless 'SUB=no'," 124 | @echo " also build subprojects." 125 | @echo "Target 'clean' will clean a specific configuration and, unless 'SUB=no'," 126 | @echo " also clean subprojects." 127 | @echo "Target 'clobber' will remove all built files from all configurations and," 128 | @echo " unless 'SUB=no', also from subprojects." 129 | @echo "Target 'all' will will build all configurations and, unless 'SUB=no'," 130 | @echo " also build subprojects." 131 | @echo "Target 'help' prints this message." 132 | @echo "" 133 | 134 | -------------------------------------------------------------------------------- /Memory/memory.v: -------------------------------------------------------------------------------- 1 | module I2C_write_to_memory( 2 | input wire clk, 3 | input wire reset, 4 | input wire run, 5 | input wire [11:0] number_of_bytes, 6 | input wire [14:0] memory_address, 7 | input wire [7:0] data_in, 8 | input wire empty, 9 | input wire ack, 10 | input wire [2:0] memory_number, 11 | output reg read, 12 | output reg [6:0] address, 13 | output reg [7:0] register, 14 | output reg mode, 15 | output reg I2C_en, 16 | output reg reset_I2C, 17 | output reg Start, 18 | output reg Stop, 19 | output reg repeat_start, 20 | input wire sda 21 | ); 22 | 23 | reg [3:0] state; 24 | reg [11:0] counter; 25 | 26 | 27 | always@(posedge clk or negedge reset) 28 | begin 29 | if( !reset ) 30 | begin 31 | state <= 0; 32 | read <= 0; 33 | address <= 7'b0; 34 | register <= 8'b0; 35 | mode <= 0; 36 | I2C_en <= 0; 37 | reset_I2C <= 0; 38 | Start <= 0; 39 | Stop <= 0; 40 | repeat_start <= 0; 41 | counter <= 0; 42 | end 43 | else 44 | begin 45 | case( state ) 46 | 0: // initial state 47 | begin 48 | if( run ) // if run is not enabled 49 | begin 50 | state <= 1; 51 | read <= 0; 52 | address <= 7'b0; 53 | register <= 8'b0; 54 | mode <= 0; 55 | I2C_en <= 1; // Enable the I2C module 56 | reset_I2C <= 0; // reset the I2C module 57 | Start <= 0; 58 | Stop <= 0; 59 | repeat_start <= 0; 60 | counter <= 0; 61 | end 62 | else 63 | begin 64 | state <= 0; 65 | read <= 0; 66 | address <= 7'b0; 67 | register <= 8'b0; 68 | mode <= 0; 69 | I2C_en <= 0; 70 | reset_I2C <= 1; 71 | Start <= 0; 72 | Stop <= 0; 73 | repeat_start <= 0; 74 | counter <= 0; 75 | end 76 | end 77 | 1: 78 | begin 79 | state <= 2; 80 | read <= 0; 81 | address <= {4'b1010, memory_number}; // set memory address; 82 | register <= 8'b0; 83 | mode <= 0; 84 | I2C_en <= 1; 85 | reset_I2C <= 1; // Done with I2c reset 86 | Start <= 1; // Start the I2C module 87 | Stop <= 0; 88 | repeat_start <= 0; 89 | counter <= 0; 90 | end 91 | 2: 92 | begin 93 | if(counter < 8) 94 | begin 95 | state <= 2; 96 | read <= 0; 97 | address <= {4'b1010, memory_number}; // set memory address; 98 | register <= 8'b0; 99 | mode <= 0; 100 | I2C_en <= 1; 101 | reset_I2C <= 1; // Done with I2c reset 102 | Start <= 0; // Start the I2C module 103 | Stop <= 0; 104 | repeat_start <= 0; 105 | counter <= counter + 1; 106 | end 107 | else 108 | begin 109 | state <= 3; 110 | read <= 0; 111 | address <= 0; 112 | register <= 8'b0; 113 | mode <= 0; 114 | I2C_en <= 1; 115 | reset_I2C <= 1; // Done with I2c reset 116 | Start <= 0; // Start the I2C module 117 | Stop <= 0; 118 | repeat_start <= 0; 119 | counter <= 0; 120 | end 121 | end 122 | 3: 123 | begin 124 | state <= 3; 125 | read <= 0; 126 | address <= 8'b0; // set memory address; 127 | register <= 8'b0; 128 | mode <= 0; 129 | I2C_en <= 1; 130 | reset_I2C <= 1; // Done with I2c reset 131 | Start <= 1; // Start the I2C module 132 | Stop <= 0; 133 | repeat_start <= 0; 134 | counter <= 0; 135 | end 136 | endcase 137 | end 138 | end 139 | 140 | endmodule 141 | 142 | 143 | 144 | -------------------------------------------------------------------------------- /rfid-verilog/reader/rfid_reader_tx.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // rigidly assume clock = 10mhz. 4 | 5 | module rfid_reader_tx ( 6 | // basic setup connections 7 | reset, clk, reader_modulation, 8 | // control signals 9 | tx_done, tx_running, tx_go, send_trcal, 10 | // timing information 11 | delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts, 12 | // payload information 13 | tx_packet_length, tx_packet_data 14 | ); 15 | 16 | input reset, clk, send_trcal, tx_go; 17 | output reader_modulation; 18 | output tx_done, tx_running; 19 | 20 | input [15:0] delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts; 21 | 22 | input [6:0] tx_packet_length; 23 | input [127:0] tx_packet_data; 24 | 25 | reg [2:0] tx_state; 26 | parameter STATE_IDLE = 3'd0; 27 | parameter STATE_DELIM = 3'd2; 28 | parameter STATE_DATA0 = 3'd3; 29 | parameter STATE_RTCAL = 3'd4; 30 | parameter STATE_TRCAL = 3'd5; 31 | parameter STATE_DATA = 3'd6; 32 | parameter STATE_WAIT_FOR_RX = 3'd7; 33 | 34 | reg modout; 35 | assign reader_modulation = modout; 36 | 37 | reg [15:0] count; 38 | reg [6:0] current_tx_bit; 39 | 40 | reg tx_done, tx_running; 41 | 42 | wire current_bit, data0_bit_end, data0_bit_transition, data1_bit_end, data1_bit_transition, bit_transition, bit_end; 43 | wire [15:0] data0_end_count, data1_end_count, data0_tran_count, data1_tran_count; 44 | assign current_bit = tx_packet_data[current_tx_bit]; 45 | assign data0_end_count = tari_counts+pw_counts; 46 | assign data1_end_count = tari_counts+tari_counts+pw_counts; 47 | assign data0_tran_count = tari_counts; 48 | assign data1_tran_count = tari_counts+tari_counts; 49 | assign data0_bit_end = (count >= data0_end_count); 50 | assign data0_bit_transition = (count >= data0_tran_count); 51 | assign data1_bit_end = (count >= data1_end_count); 52 | assign data1_bit_transition = (count >= data1_tran_count); 53 | assign bit_transition = data1_bit_transition | (!current_bit & data0_bit_transition); 54 | assign bit_end = data1_bit_end | (!current_bit & data0_bit_end); 55 | 56 | wire rtcal_end, rtcal_transition, trcal_end, trcal_transition; 57 | wire [15:0] rtcal_end_count, trcal_end_count; 58 | 59 | assign rtcal_end_count = rtcal_counts+pw_counts; 60 | assign trcal_end_count = trcal_counts+pw_counts; 61 | assign rtcal_end = (count >= rtcal_end_count); 62 | assign rtcal_transition = (count >= rtcal_counts); 63 | assign trcal_end = (count >= trcal_end_count); 64 | assign trcal_transition = (count >= trcal_counts); 65 | 66 | always @ (posedge clk or posedge reset) begin 67 | if (reset) begin 68 | tx_state <= 0; 69 | modout <= 0; 70 | count <= 0; 71 | current_tx_bit <= 0; 72 | tx_done <= 0; 73 | tx_running <= 0; 74 | 75 | end else begin 76 | case(tx_state) 77 | STATE_IDLE: begin 78 | tx_done <= 0; 79 | if(tx_go) begin 80 | tx_state <= STATE_DELIM; 81 | count <= 1; 82 | tx_running <= 1; 83 | modout <= 0; 84 | current_tx_bit <= tx_packet_length - 1; 85 | end else begin 86 | tx_running <= 0; 87 | modout <= 1; 88 | end 89 | end 90 | 91 | STATE_DELIM: begin 92 | if( count >= delim_counts ) begin 93 | modout <= 1; 94 | count <= 1; 95 | tx_state <= STATE_DATA0; 96 | end else begin 97 | count <= count + 1; 98 | end 99 | end 100 | 101 | STATE_DATA0: begin 102 | if( data0_bit_end ) begin 103 | tx_state <= STATE_RTCAL; 104 | count <= 1; 105 | modout <= 1; 106 | end else if ( data0_bit_transition ) begin 107 | modout <= 0; 108 | count <= count + 1; 109 | end else begin 110 | count <= count + 1; 111 | end 112 | end 113 | 114 | STATE_RTCAL: begin 115 | if( rtcal_end ) begin 116 | if (send_trcal) tx_state <= STATE_TRCAL; 117 | else tx_state <= STATE_DATA; 118 | count <= 1; 119 | modout <= 1; 120 | end else if( rtcal_transition ) begin 121 | modout <= 0; 122 | count <= count + 1; 123 | end else begin 124 | count <= count + 1; 125 | end 126 | end 127 | 128 | STATE_TRCAL: begin 129 | if( trcal_end ) begin 130 | tx_state <= STATE_DATA; 131 | count <= 1; 132 | modout <= 1; 133 | end else if( trcal_transition ) begin 134 | modout <= 0; 135 | count <= count + 1; 136 | end else begin 137 | count <= count + 1; 138 | end 139 | end 140 | 141 | STATE_DATA: begin 142 | if (bit_end) begin 143 | count <= 1; 144 | modout <= 1; 145 | 146 | if (current_tx_bit == 0) begin 147 | tx_state <= STATE_WAIT_FOR_RX; 148 | tx_done <= 1; 149 | end else begin 150 | current_tx_bit <= current_tx_bit - 1; 151 | end 152 | 153 | end else if (bit_transition) begin 154 | modout <= 0; 155 | count <= count + 1; 156 | end else begin 157 | count <= count + 1; 158 | end 159 | end 160 | 161 | STATE_WAIT_FOR_RX: begin 162 | modout <= 1; 163 | if(!tx_go) tx_state <= 0; 164 | end 165 | 166 | default: begin 167 | tx_state <= 0; 168 | end 169 | endcase 170 | end 171 | end 172 | 173 | endmodule 174 | -------------------------------------------------------------------------------- /FIFO/FIFO.v: -------------------------------------------------------------------------------- 1 | module FIFO( 2 | input wire reset_n, 3 | input wire en, 4 | input wire r_clk, 5 | input wire w_clk, 6 | input wire read, 7 | input wire write, 8 | input wire [7:0] data_in, 9 | output reg [7:0] data_out, 10 | output wire empty, 11 | output wire full 12 | ); 13 | 14 | reg [3:0] write_pointer; 15 | reg [3:0] read_pointer; 16 | reg [7:0] memory [0:7]; 17 | reg [7:0] data; 18 | 19 | assign full = ((read_pointer[3] != write_pointer[3]) && 20 | (read_pointer[2:0] == write_pointer[2:0])) ? 1 : 0; 21 | assign empty = (read_pointer == write_pointer) ? 1 : 0; 22 | 23 | always@(posedge w_clk or negedge reset_n) 24 | begin 25 | if( !reset_n ) 26 | begin 27 | write_pointer <= 0; 28 | data <= 8'bz; 29 | end 30 | else 31 | begin 32 | if( write && en && !full ) 33 | begin 34 | if((write_pointer +1) < 16) 35 | begin 36 | write_pointer <= write_pointer + 1; 37 | data <= data_in; 38 | end 39 | else 40 | begin 41 | write_pointer <= 0; 42 | data <= data_in; 43 | end 44 | end 45 | else 46 | begin 47 | write_pointer <= write_pointer; 48 | data <= data; 49 | end 50 | end 51 | end 52 | 53 | always@(write_pointer or negedge reset_n) 54 | begin 55 | if(!reset_n) 56 | begin 57 | memory[0] <= 0; 58 | memory[1] <= 0; 59 | memory[2] <= 0; 60 | memory[3] <= 0; 61 | memory[4] <= 0; 62 | memory[5] <= 0; 63 | memory[6] <= 0; 64 | memory[7] <= 0; 65 | end 66 | else 67 | begin 68 | case(write_pointer[2:0]) 69 | 0: 70 | begin 71 | memory[0] <= memory[0]; 72 | memory[1] <= memory[1]; 73 | memory[2] <= memory[2]; 74 | memory[3] <= memory[3]; 75 | memory[4] <= memory[4]; 76 | memory[5] <= memory[5]; 77 | memory[6] <= memory[6]; 78 | memory[7] <= data; 79 | end 80 | 1: 81 | begin 82 | memory[0] <= data; 83 | memory[1] <= memory[1]; 84 | memory[2] <= memory[2]; 85 | memory[3] <= memory[3]; 86 | memory[4] <= memory[4]; 87 | memory[5] <= memory[5]; 88 | memory[6] <= memory[6]; 89 | memory[7] <= memory[7]; 90 | end 91 | 2: 92 | begin 93 | memory[0] <= memory[0]; 94 | memory[1] <= data; 95 | memory[2] <= memory[2]; 96 | memory[3] <= memory[3]; 97 | memory[4] <= memory[4]; 98 | memory[5] <= memory[5]; 99 | memory[6] <= memory[6]; 100 | memory[7] <= memory[7]; 101 | end 102 | 3: 103 | begin 104 | memory[0] <= memory[0]; 105 | memory[1] <= memory[1]; 106 | memory[2] <= data; 107 | memory[3] <= memory[3]; 108 | memory[4] <= memory[4]; 109 | memory[5] <= memory[5]; 110 | memory[6] <= memory[6]; 111 | memory[7] <= memory[7]; 112 | end 113 | 4: 114 | begin 115 | memory[0] <= memory[0]; 116 | memory[1] <= memory[1]; 117 | memory[2] <= memory[2]; 118 | memory[3] <= data; 119 | memory[4] <= memory[4]; 120 | memory[5] <= memory[5]; 121 | memory[6] <= memory[6]; 122 | memory[7] <= memory[7]; 123 | end 124 | 5: 125 | begin 126 | memory[0] <= memory[0]; 127 | memory[1] <= memory[1]; 128 | memory[2] <= memory[2]; 129 | memory[3] <= memory[3]; 130 | memory[4] <= data; 131 | memory[5] <= memory[5]; 132 | memory[6] <= memory[6]; 133 | memory[7] <= memory[7]; 134 | end 135 | 6: 136 | begin 137 | memory[0] <= memory[0]; 138 | memory[1] <= memory[1]; 139 | memory[2] <= memory[2]; 140 | memory[3] <= memory[3]; 141 | memory[4] <= memory[4]; 142 | memory[5] <= data; 143 | memory[6] <= memory[6]; 144 | memory[7] <= memory[7]; 145 | end 146 | 7: 147 | begin 148 | memory[0] <= memory[0]; 149 | memory[1] <= memory[1]; 150 | memory[2] <= memory[2]; 151 | memory[3] <= memory[3]; 152 | memory[4] <= memory[4]; 153 | memory[5] <= memory[5]; 154 | memory[6] <= data; 155 | memory[7] <= memory[7]; 156 | end 157 | endcase 158 | end 159 | end 160 | 161 | always@(negedge r_clk or negedge reset_n) 162 | begin 163 | if(!reset_n) 164 | begin 165 | read_pointer <= 0; 166 | end 167 | else 168 | begin 169 | if(en) 170 | begin 171 | if( read && !empty ) 172 | begin 173 | if((read_pointer + 1) < 16) 174 | begin 175 | read_pointer <= read_pointer + 1; 176 | end 177 | else 178 | begin 179 | read_pointer <= 0; 180 | end 181 | end 182 | else 183 | begin 184 | read_pointer <= read_pointer; 185 | end 186 | end 187 | else 188 | begin 189 | read_pointer <= 0; 190 | end 191 | end 192 | end 193 | 194 | 195 | always@(read_pointer) 196 | begin 197 | if(!reset_n) 198 | begin 199 | data_out <= 8'bz; 200 | end 201 | else 202 | begin 203 | if(read_pointer[2:0] == 0) 204 | begin 205 | data_out <= memory[7]; 206 | end 207 | else 208 | begin 209 | data_out <= memory[read_pointer[2:0] - 1]; 210 | end 211 | end 212 | end 213 | endmodule 214 | -------------------------------------------------------------------------------- /rfid-verilog/tag/tx.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | // TX 4 | // Copyright 2010 University of Washington 5 | // License: http://creativecommons.org/licenses/by/3.0/ 6 | // 2008 Dan Yeager 7 | 8 | // TX module converts a binary serial data stream to 9 | // a time domain EPC Class 1 Gen 2 modulated waveform. 10 | // This is intended to connect to the tag modulator. 11 | // The clkin should correspond to 2x the link frequency "LF" 12 | // as described in the EPC specification. 13 | // Violation is driven by the preamble module to facilitate 14 | // the modulation rule violations in the preamble. 15 | // This module generates a clock for the modules which 16 | // are to supply data. 17 | 18 | // setupdone tells the controller that we have received the 19 | // count > rtcal signal ("rtcal_expired") so it can turn off the rx module 20 | 21 | // txdoneout tells the sequencer that we are totally done sending bits 22 | // and it can turn off the tx module safely without corrupting the transmission 23 | 24 | // rtcal_expired: we need to wait for MAX(trcal, 10*Tpri) to transmit. 25 | 26 | // txstopin: this is for stopping gracefully. Sequencer sends us a signal to stop 27 | // and we should stop after our current bit is finished and then set the txdoneout flag high 28 | // so the sequencer knows we are done. 29 | 30 | // bitinclk and bitin are the preamble, data and crc, serialized by the sequencer. 31 | 32 | // m sets the miller modulation, and violationin is used by the preamble to generate 33 | // the protocol violations as per the epc spec. 34 | 35 | // bitout goes to the modulator. 36 | 37 | module tx (reset, rtcal_expired, txstopin, 38 | clkin, bitin, violationin, m, 39 | bitout, bitinclk, setupdone, txdoneout); 40 | 41 | input reset, rtcal_expired, txstopin, clkin, bitin, violationin; 42 | input [1:0] m; 43 | output bitout, bitinclk, setupdone, txdoneout; 44 | reg bitout; 45 | wire bitinclk; 46 | 47 | // after rtcal_expired and 10 Tpri, setupdone = 1 and regular operation commences 48 | // txstop gets clocked in with bits, but we wait until bit is finished to shut off modout. 49 | reg setupdone, txstop, txdone, txdoneout; 50 | 51 | reg bitoutenable; 52 | 53 | reg currentbit, previousbit, phaseinvert; 54 | reg currentviolation; 55 | 56 | wire millerphaseinvert; 57 | assign millerphaseinvert = phaseinvert ^ (setupdone & !(currentbit | previousbit) & !currentviolation); 58 | 59 | wire nextphaseinvert; 60 | assign nextphaseinvert = phaseinvert ^ (currentbit & setupdone); 61 | 62 | reg clkphase; 63 | wire evalclk, evalclkby2; 64 | wire [3:0] clocks; 65 | 66 | wire tempbit, bitgenclk, nextbitout; 67 | assign bitgenclk = ~clocks[0]; 68 | assign tempbit = (bitgenclk ^ phaseinvert) & setupdone & !txdone; 69 | assign nextbitout = (m == 0) ? (tempbit & !currentviolation) : tempbit; // fm0 violation opportunity 70 | 71 | wire divreset; 72 | assign divreset = reset | !setupdone; 73 | 74 | divby2 U_DIV1 (clkin , divreset, clocks[0]); 75 | divby2 U_DIV2 (clkin , divreset, clocks[1]); 76 | divby2 U_DIV3 (clocks[1], divreset, clocks[2]); 77 | divby2 U_DIV4 (clocks[2], divreset, clocks[3]); 78 | 79 | // Bits are evaluated every eval clock 80 | assign evalclk = clocks[m] & setupdone; 81 | 82 | // fm0 clocks data at the output frequency: 83 | // so dataclk = eval clk. 84 | // miller clocks data at half the evalclk 85 | // in order to evaluate both possible phase inversions. 86 | divby2 U_DIV5 (evalclk, reset, evalclkby2); 87 | reg bitinclkoverride; // to clock first bit from preamble module during setup. 88 | assign bitinclk = ((m == 0) ? evalclk : evalclkby2) | bitinclkoverride; 89 | 90 | // We don't want glitches on the tempbit output, so it is gated 91 | // with a FF. However, the FF causes the freq. to divide by 2 92 | // so the FF is clocked with clkin and the tempbit waveform 93 | // is generated with clkin/2 for FM0 and M2 (M2 get divided via 94 | // the state machine variable clkphase). 95 | // Subsequent Miller schemes are again divided by 2. 96 | always @ (posedge clkin or posedge reset) begin 97 | if (reset) begin 98 | bitout <= 0; 99 | end else begin 100 | bitout <= nextbitout & bitoutenable; 101 | end 102 | end 103 | 104 | // start up circuit 105 | // we should wait 10 subcarrier periods before tx start 106 | // also, rtcal_expired must be high before tx start. 107 | // clkin is 2x the subcarrier frequency 108 | reg [5:0] subcarriers; 109 | always @ (posedge clkin or posedge reset) begin 110 | if (reset) begin 111 | subcarriers <= 0; 112 | bitinclkoverride <= 0; 113 | txdone <= 0; 114 | txdoneout <= 0; 115 | setupdone <= 0; 116 | 117 | end else if (subcarriers < 8) begin 118 | subcarriers <= subcarriers + 6'd1; 119 | bitinclkoverride <= 1; 120 | 121 | end else if (subcarriers < 17) begin 122 | subcarriers <= subcarriers + 6'd1; 123 | bitinclkoverride <= 0; 124 | 125 | end else if (subcarriers == 17) begin // start tx 126 | if (rtcal_expired) begin 127 | subcarriers <= subcarriers + 6'd1; 128 | setupdone <= 1; 129 | end 130 | 131 | end else if (txstop & !txdone & (m==0)) begin // end tx 132 | txdone <= 1; 133 | subcarriers <= subcarriers + 6'd1; 134 | 135 | end else if (txstop & !txdone & (m==1) & (subcarriers >= 19)) begin 136 | txdone <= 1; 137 | subcarriers <= subcarriers + 6'd1; 138 | 139 | end else if (txstop & !txdone & (m==2) & (subcarriers >= 21)) begin 140 | txdone <= 1; 141 | subcarriers <= subcarriers + 6'd1; 142 | 143 | end else if (txstop & !txdone & (m==3) & (subcarriers >= 25)) begin 144 | txdone <= 1; 145 | subcarriers <= subcarriers + 6'd1; 146 | 147 | end else if (txstop & (subcarriers==6'b111111)) begin // overflow 148 | txdone <= 1; 149 | txdoneout <= 1; 150 | 151 | end else if (txdone) begin // 152 | txdoneout <= 1; 153 | 154 | end else if (txstop) begin // 155 | subcarriers <= subcarriers + 6'd1; 156 | end 157 | end 158 | 159 | always @ (posedge evalclk or posedge reset) begin 160 | if (reset) begin 161 | previousbit <= 0; 162 | currentbit <= 0; 163 | phaseinvert <= 0; 164 | clkphase <= 0; 165 | currentviolation <= 0; 166 | txstop <= 0; 167 | bitoutenable <= 0; 168 | 169 | end else begin 170 | 171 | if (clkphase == 0 | m == 0) begin 172 | clkphase <= 1; 173 | phaseinvert <= nextphaseinvert; 174 | currentbit <= bitin; 175 | previousbit <= currentbit; 176 | currentviolation <= violationin; 177 | txstop <= txstopin; 178 | 179 | if(m==0) bitoutenable <= 1; 180 | 181 | end else begin 182 | clkphase <= 0; 183 | phaseinvert <= millerphaseinvert; 184 | bitoutenable <= 1; 185 | end 186 | 187 | end 188 | end 189 | 190 | endmodule -------------------------------------------------------------------------------- /rfid-verilog/reader/rfid_reader.v: -------------------------------------------------------------------------------- 1 | 2 | // RFID Reader for testing epc class 1 gen 2 tags. 3 | 4 | 5 | // rigidly assume clock = 7.812mhz. (this makes our divide ratios work out nicely) 6 | // for an 8mhz crystal, we are off by about 2% 7 | 8 | `timescale 1ns/1ns 9 | 10 | module rfid_reader ( 11 | // basic setup connections 12 | reset, clk, tag_backscatter, reader_modulation 13 | ); 14 | 15 | input reset, clk, tag_backscatter; 16 | output reader_modulation; 17 | 18 | // Packets (valid tx_cmd values) 19 | parameter QUERYREP = 0; 20 | parameter ACK = 1; 21 | parameter QUERY = 2; 22 | parameter QUERYADJ = 3; 23 | parameter SELECT = 4; 24 | parameter NACK = 5; 25 | parameter REQRN = 6; 26 | parameter READ = 7; 27 | parameter WRITE = 8; 28 | parameter KILL = 9; 29 | parameter LOCK = 10; 30 | parameter ACCESS = 11; 31 | parameter BLOCKWRITE = 12; 32 | parameter BLOCKERASE = 13; 33 | 34 | // Query parameters 35 | parameter DR = 1'd0; // 0 = 8, 1 = 64/3 36 | parameter M = 2'd0; // 0 to 3 37 | parameter TREXT = 1'd0; // 0 or 1 38 | parameter SEL = 2'd0; // 0 or 1 39 | parameter SESSION = 2'd0; // 0 or 1 40 | parameter TARGET = 1'd0; // 0 or 1 41 | parameter Q = 4'd2; // 0 to 15 42 | 43 | // TX Timing info 44 | parameter DELIM = 16'd15000; // delimiter = 15us 45 | parameter PW = 16'd1000; // 46 | parameter TARI = 16'd6250; // 47 | parameter RTCAL = 16'd18750; // 2.5*TARIRTCAL 49 | 50 | wire [2:0] miller; 51 | assign miller = M; 52 | wire trext; 53 | assign trext = TREXT; 54 | wire divide_ratio; 55 | assign divide_ratio = DR; 56 | wire [15:0] tari_ns; 57 | assign tari_ns = TARI; 58 | wire [15:0] trcal_ns; 59 | assign trcal_ns = TRCAL; 60 | 61 | wire [2:0] q_adj; 62 | assign q_adj = 0; 63 | wire [3:0] slot_q; 64 | assign slot_q = Q; 65 | wire [1:0] session; 66 | assign session = SESSION; 67 | wire [1:0] select; 68 | assign select = SEL; 69 | wire target; 70 | assign target = TARGET; 71 | 72 | reg [3:0] send_packet_type; 73 | reg start_tx; 74 | 75 | reg [15:0] tx_handle; 76 | wire [15:0] rx_handle; 77 | 78 | wire reader_done, rx_timeout, rx_packet_complete, reader_running; 79 | 80 | rfid_reader_packet_rxtx UREADER ( 81 | // basic setup connections 82 | reset, clk, tag_backscatter, reader_modulation, 83 | // modulation settings 84 | miller, trext, divide_ratio, tari_ns, trcal_ns, 85 | // tag state settings 86 | slot_q, q_adj, session, target, select, 87 | // command to send, posedge send trigger 88 | send_packet_type, start_tx, reader_done, rx_timeout, rx_packet_complete, reader_running, 89 | // tx payload info 90 | tx_handle, 91 | // rx payload info 92 | rx_handle 93 | ); 94 | 95 | 96 | // divide time periods by 128 ns via shift right 7 to get clock cycles 97 | parameter CLK_EXP = 7; 98 | 99 | wire [15:0] startup_counts; 100 | assign startup_counts = 16'd50000 >> CLK_EXP; 101 | 102 | 103 | reg [5:0] reader_state; 104 | parameter STATE_INIT = 0; 105 | parameter STATE_QUERY = 1; 106 | parameter STATE_QUERYREP = 2; 107 | parameter STATE_ACK = 3; 108 | parameter STATE_REQRN = 4; 109 | parameter STATE_READ = 5; 110 | parameter STATE_REQMASK = 6; 111 | parameter STATE_WRITE = 7; 112 | 113 | reg started; 114 | reg [15:0] counter; 115 | 116 | always @ (posedge clk or posedge reset) begin 117 | if (reset) begin 118 | reader_state <= 0; 119 | started <= 0; 120 | tx_handle <= 0; 121 | start_tx <= 0; 122 | counter <= 0; 123 | send_packet_type <= 0; 124 | end else begin 125 | case(reader_state) 126 | STATE_INIT: begin 127 | if (!started) begin 128 | counter <= 0; 129 | started <= 1; 130 | end else begin 131 | if (counter >= startup_counts) begin 132 | reader_state <= STATE_QUERY; 133 | started <= 0; 134 | end else begin 135 | counter <= counter + 1; 136 | end 137 | end 138 | end 139 | 140 | STATE_QUERY: begin 141 | send_packet_type <= QUERY; 142 | 143 | if (!started && reader_running) begin 144 | start_tx <= 0; 145 | started <= 1; 146 | end else if (!started && !reader_running) begin 147 | start_tx <= 1; 148 | end else if (started && reader_done && rx_packet_complete) begin 149 | tx_handle <= rx_handle; 150 | reader_state <= STATE_ACK; 151 | started <= 0; 152 | end else if (started && reader_done && !rx_packet_complete) begin 153 | reader_state <= STATE_QUERYREP; 154 | started <= 0; 155 | end 156 | end 157 | 158 | STATE_QUERYREP: begin 159 | send_packet_type <= QUERYREP; 160 | 161 | if (!started && reader_running) begin 162 | start_tx <= 0; 163 | started <= 1; 164 | end else if (!started && !reader_running) begin 165 | start_tx <= 1; 166 | end else if (started && reader_done && rx_packet_complete) begin 167 | tx_handle <= rx_handle; 168 | reader_state <= STATE_ACK; 169 | started <= 0; 170 | end else if (started && reader_done && !rx_packet_complete) begin 171 | reader_state <= STATE_QUERYREP; 172 | started <= 0; 173 | end 174 | end 175 | 176 | STATE_ACK: begin 177 | send_packet_type <= ACK; 178 | 179 | if (!started && reader_running) begin 180 | start_tx <= 0; 181 | started <= 1; 182 | end else if (!started && !reader_running) begin 183 | start_tx <= 1; 184 | end else if (started && reader_done && rx_packet_complete) begin 185 | tx_handle <= rx_handle; 186 | reader_state <= STATE_REQRN; 187 | started <= 0; 188 | end else if (started && reader_done && !rx_packet_complete) begin 189 | reader_state <= STATE_QUERY; 190 | started <= 0; 191 | end 192 | end 193 | 194 | STATE_REQRN: begin 195 | send_packet_type <= REQRN; 196 | 197 | if (!started && reader_running) begin 198 | start_tx <= 0; 199 | started <= 1; 200 | end else if (!started && !reader_running) begin 201 | start_tx <= 1; 202 | end else if (started && reader_done && rx_packet_complete) begin 203 | tx_handle <= rx_handle; 204 | reader_state <= STATE_READ; 205 | started <= 0; 206 | end else if (started && reader_done && !rx_packet_complete) begin 207 | reader_state <= STATE_QUERY; 208 | started <= 0; 209 | end 210 | end 211 | 212 | STATE_READ: begin 213 | send_packet_type <= READ; 214 | 215 | if (!started && reader_running) begin 216 | start_tx <= 0; 217 | started <= 1; 218 | end else if (!started && !reader_running) begin 219 | start_tx <= 1; 220 | end else if (started && reader_done && rx_packet_complete) begin 221 | tx_handle <= rx_handle; 222 | reader_state <= STATE_QUERY; 223 | started <= 0; 224 | end else if (started && reader_done && !rx_packet_complete) begin 225 | reader_state <= STATE_QUERY; 226 | started <= 0; 227 | end 228 | end 229 | 230 | default: begin 231 | reader_state <= 0; 232 | end 233 | endcase 234 | end 235 | end 236 | 237 | 238 | endmodule 239 | -------------------------------------------------------------------------------- /I2C/slave.v: -------------------------------------------------------------------------------- 1 | module slave( 2 | input wire reset_n, 3 | input wire en, 4 | input wire [6:0] my_addr, 5 | input wire [7:0] measurement, 6 | input wire scl, 7 | inout wire sda 8 | ); 9 | 10 | reg stop; 11 | reg start; 12 | reg mode; 13 | reg [7:0] data_in; 14 | reg [6:0] address; 15 | reg [2:0] slave_state; 16 | reg [4:0] slave_counter; 17 | reg sda_out; 18 | reg sda_en; 19 | reg sda_in; 20 | 21 | parameter WAIT = 0; 22 | parameter ADDRESS = 1; 23 | parameter MODE = 2; 24 | parameter ADDRESS_ACK = 3; 25 | parameter WRITE_DATA = 4; 26 | parameter READ_DATA = 5; 27 | parameter WRITE_ACK = 6; 28 | parameter READ_ACK = 7; 29 | 30 | 31 | assign sda = (sda_en) ? ( sda_out ) ? 1'bz : 1'b0 : 1'bz; 32 | 33 | always@(negedge sda or negedge reset_n) 34 | begin 35 | if(!reset_n) 36 | begin 37 | start <= 0; 38 | end 39 | else 40 | begin 41 | if( scl ) 42 | begin 43 | start <= 1; 44 | end 45 | else 46 | begin 47 | start <= 0; 48 | end 49 | end 50 | end 51 | 52 | always@(posedge sda or negedge reset_n) 53 | begin 54 | if(!reset_n) 55 | begin 56 | stop <= 0; 57 | end 58 | else 59 | begin 60 | if( scl ) 61 | begin 62 | stop <= 1; 63 | end 64 | else 65 | begin 66 | stop <= 0; 67 | end 68 | end 69 | end 70 | 71 | 72 | always@(posedge scl or negedge reset_n) 73 | begin 74 | sda_in <= sda; 75 | end 76 | 77 | always@( sda_in or slave_state or slave_counter or negedge reset_n) 78 | begin 79 | if( !reset_n ) 80 | begin 81 | sda_en <= 0; 82 | sda_out <= 0; 83 | address <= 7'b0; 84 | data_in <= 8'b0; 85 | mode <= 0; 86 | end 87 | else 88 | begin 89 | case(slave_state) 90 | WAIT: 91 | begin 92 | sda_en <= 0; 93 | sda_out <= 0; 94 | address <= {address, sda_in}; 95 | data_in <= 8'b0; 96 | mode <= 0; 97 | end 98 | ADDRESS: 99 | begin 100 | sda_en <= 0; 101 | sda_out <= 0; 102 | address <= {address, sda_in}; 103 | data_in <= 8'b0; 104 | mode <= 0; 105 | end 106 | MODE: 107 | begin 108 | sda_en <= 0; 109 | sda_out <= 0; 110 | address <= address; 111 | data_in <= 8'b0; 112 | mode <= sda; 113 | end 114 | ADDRESS_ACK: 115 | begin 116 | sda_en <= 1; 117 | sda_out <= 0; 118 | address <= address; 119 | data_in <= 8'b0; 120 | mode <= mode; 121 | end 122 | WRITE_DATA: 123 | begin 124 | sda_en <= 1; 125 | sda_out <= measurement[7 - slave_counter]; 126 | address <= 7'b0; 127 | data_in <= 8'b0; 128 | mode <= mode; 129 | end 130 | WRITE_ACK: 131 | begin 132 | sda_en <= 0; 133 | sda_out <= 0; 134 | address <= address; 135 | data_in <= 8'b0; 136 | mode <= mode; 137 | end 138 | READ_DATA: 139 | begin 140 | sda_en <= 0; 141 | sda_out <= 0; 142 | address <= address; 143 | data_in <= {data_in, sda_in}; 144 | mode <= mode; 145 | end 146 | READ_ACK: 147 | begin 148 | sda_en <= 1; 149 | sda_out <= 0; 150 | address <= address; 151 | data_in <= data_in; 152 | mode <= mode; 153 | end 154 | endcase 155 | end 156 | end 157 | 158 | 159 | always@(negedge scl or negedge reset_n) 160 | begin 161 | if( !reset_n ) 162 | begin 163 | slave_state = WAIT; 164 | slave_counter = 0; 165 | end 166 | else 167 | begin 168 | case(slave_state) 169 | WAIT: 170 | begin 171 | if( start && en ) 172 | begin 173 | slave_state <= ADDRESS; 174 | slave_counter <= 4'b0; 175 | end 176 | else 177 | begin 178 | slave_state <= WAIT; 179 | slave_counter <= 4'b0; 180 | end 181 | end 182 | ADDRESS: 183 | begin 184 | if(slave_counter < 6) 185 | begin 186 | slave_state <= ADDRESS; 187 | slave_counter <= slave_counter + 1'b1; 188 | end 189 | else 190 | begin 191 | slave_state <= MODE; 192 | slave_counter <= 0; 193 | end 194 | end 195 | MODE: 196 | begin 197 | slave_state <= ADDRESS_ACK; 198 | slave_counter <= 0; 199 | end 200 | ADDRESS_ACK: 201 | begin 202 | if((address == my_addr) || ( stop )) 203 | begin 204 | if( mode ) 205 | begin 206 | slave_state <= WRITE_DATA; 207 | slave_counter <= 0; 208 | end 209 | else 210 | slave_state <= READ_DATA; 211 | slave_counter <= 0; 212 | end 213 | else 214 | begin 215 | slave_state <= WAIT; 216 | slave_counter <= 0; 217 | end 218 | end 219 | WRITE_DATA: 220 | begin 221 | if(slave_counter < 7) 222 | begin 223 | slave_state <= WRITE_DATA; 224 | slave_counter <= slave_counter + 1'b1; 225 | end 226 | else 227 | begin 228 | slave_state <= WRITE_ACK; 229 | slave_counter <= 0; 230 | end 231 | end 232 | WRITE_ACK: 233 | begin 234 | if( sda_in || stop ) 235 | begin 236 | slave_state <= WAIT; 237 | slave_counter = 0; 238 | end 239 | else 240 | begin 241 | slave_state <= WRITE_DATA; 242 | slave_counter <= 0; 243 | end 244 | end 245 | READ_DATA: 246 | begin 247 | if(slave_counter < 7) 248 | begin 249 | slave_state <= READ_DATA; 250 | slave_counter <= slave_counter + 1; 251 | end 252 | else 253 | begin 254 | slave_state <= READ_ACK; 255 | slave_counter <= 0; 256 | end 257 | end 258 | READ_ACK: 259 | begin 260 | if( stop ) 261 | begin 262 | slave_state <= WAIT; 263 | slave_counter <= 0; 264 | end 265 | else 266 | begin 267 | slave_state <= READ_DATA; 268 | slave_counter <= 0; 269 | end 270 | end 271 | endcase 272 | end 273 | end 274 | endmodule 275 | -------------------------------------------------------------------------------- /rfid-verilog/tag/top.v: -------------------------------------------------------------------------------- 1 | 2 | // Top level which connects all the top-level functional blocks. 3 | // Copyright 2010 University of Washington 4 | // License: http://creativecommons.org/licenses/by/3.0/ 5 | // 2008 Dan Yeager 6 | 7 | // The controller chooses if and what packet is sent. 8 | 9 | // RX converts RFID protocol into a serial data stream 10 | // and provides TRCAL, the tx clock divider calibration 11 | // and the lsb of the counter as a random number stream. 12 | 13 | // CMDPARSE and PACKETPARSE decode the serial bit stream 14 | // and help the controller make decisions. 15 | 16 | // TX converts a serial bit stream to RFID protocol. 17 | // It is wrapped in a SEQUENCER which provides the proper 18 | // clock to TX and sequences the preamble, DATA and crc in time. 19 | 20 | // The controller connects one of 4 DATA sources to the sequencer. 21 | // Options are RNG (random number), EPC (ID), READ (response to READ packet) 22 | // and WRITE (response to WRITE packet). 23 | 24 | module top(reset, clk, demodin, modout, // regular IO 25 | adc_sample_ctl, adc_sample_clk, adc_sample_datain, // adc connections 26 | msp_sample_ctl, msp_sample_clk, msp_sample_datain, // msp430 connections 27 | uid_byte_in, uid_addr_out, uid_clk_out, 28 | writedataout, writedataclk, 29 | use_uid, use_q, comm_enable, 30 | debug_clk, debug_out); 31 | 32 | // Regular IO 33 | // Oscillator input, master reset, demodulator input 34 | input reset, clk, demodin; 35 | 36 | // Modulator output 37 | output modout; 38 | 39 | // Functionality control 40 | input use_uid, use_q, comm_enable; 41 | 42 | // EPC ID source 43 | input [7:0] uid_byte_in; 44 | output [3:0] uid_addr_out; 45 | output uid_clk_out; 46 | 47 | // ADC connections 48 | input adc_sample_datain; 49 | output adc_sample_clk, adc_sample_ctl; 50 | 51 | // MSP430 connections 52 | input msp_sample_datain; 53 | output msp_sample_clk, msp_sample_ctl; 54 | output writedataout, writedataclk; 55 | 56 | // Debugging IO 57 | input debug_clk; 58 | output debug_out; 59 | 60 | // CONTROLLER module connections 61 | wire rx_en, tx_en, docrc; 62 | wire [15:0] currentrn; // current rn 63 | wire [15:0] currenthandle; // current handle 64 | 65 | // RX module connections 66 | wire rx_reset, rxtop_reset, bitclk, bitout; 67 | wire rx_overflow; 68 | 69 | // PACKET PARSE module connections 70 | wire handlematch; 71 | wire [1:0] readwritebank; 72 | wire [7:0] readwriteptr; 73 | wire [7:0] readwords; 74 | wire writedataout, writedataclk; 75 | wire [3:0] rx_q; 76 | wire [2:0] rx_updn; 77 | 78 | // CMDPARSE module connections 79 | wire packet_complete, cmd_complete; 80 | wire [8:0] rx_cmd; 81 | 82 | // TX module connections 83 | wire tx_reset, txsetupdone, tx_done; 84 | 85 | // TX settings module wires 86 | wire dr_in, dr_out; 87 | wire trext_in, trext_out; 88 | wire [1:0] m_in, m_out; 89 | wire [9:0] trcal_in, trcal_out; 90 | 91 | // Signal to tx settings module to store TR modulation settings. 92 | parameter QUERY = 9'b000000100; 93 | wire query_complete; 94 | assign query_complete = packet_complete && (rx_cmd==QUERY); 95 | 96 | // RNG connections 97 | wire rngbitin, rngbitinclk; 98 | // Signal to RNG to clock in new bits for query, queryadj, reqrn 99 | assign rngbitinclk = bitclk & (rx_cmd[2] | rx_cmd[3] | (rx_cmd[6] & handlematch)); 100 | 101 | // TX module connections 102 | wire txbitclk, txbitsrc, txdatadone; 103 | 104 | // RX and TX module reset signals 105 | assign tx_reset = reset | !tx_en; 106 | assign rx_reset = reset | !rx_en; 107 | assign rxtop_reset = reset | !rx_en; 108 | 109 | // mux control for transmit data source 110 | wire [1:0] bitsrcselect; 111 | parameter BITSRC_RNG = 0; 112 | parameter BITSRC_EPC = 1; 113 | parameter BITSRC_READ = 2; 114 | parameter BITSRC_UID = 3; 115 | 116 | // mux the bit source for the tx module 117 | wire [3:0] bitsrc; 118 | wire rngbitsrc, epcbitsrc, readbitsrc, uidbitsrc; 119 | assign bitsrc[0] = rngbitsrc; 120 | assign bitsrc[1] = epcbitsrc; 121 | assign bitsrc[2] = readbitsrc; 122 | assign bitsrc[3] = uidbitsrc; 123 | assign txbitsrc = bitsrc[bitsrcselect]; 124 | 125 | // mux control for data source done flag 126 | wire [3:0] datadone; 127 | wire rngdatadone, epcdatadone, readdatadone, uiddatadone; 128 | assign datadone[0] = rngdatadone; 129 | assign datadone[1] = epcdatadone; 130 | assign datadone[2] = readdatadone; 131 | assign datadone[3] = uiddatadone; 132 | assign txdatadone = datadone[bitsrcselect]; 133 | 134 | // mux control for tx data clock 135 | wire rngbitclk, epcbitclk, readbitclk, uidbitclk; 136 | assign rngbitclk = (bitsrcselect == BITSRC_RNG ) ? txbitclk : 1'b0; 137 | assign epcbitclk = (bitsrcselect == BITSRC_EPC ) ? txbitclk : 1'b0; 138 | assign readbitclk = (bitsrcselect == BITSRC_READ) ? txbitclk : 1'b0; 139 | assign uidbitclk = (bitsrcselect == BITSRC_UID ) ? txbitclk : 1'b0; 140 | 141 | // MUX connection from READ to MSP or ADC 142 | wire readfrommsp; 143 | wire readfromadc = !readfrommsp; 144 | wire read_sample_ctl, read_sample_clk, read_sample_datain; 145 | 146 | // ADC connections 147 | assign adc_sample_ctl = read_sample_ctl & readfromadc; 148 | assign adc_sample_clk = read_sample_clk & readfromadc; 149 | 150 | // MSP430 connections 151 | assign msp_sample_ctl = read_sample_ctl & readfrommsp; 152 | assign msp_sample_clk = read_sample_clk & readfrommsp; 153 | 154 | assign read_sample_datain = readfromadc ? adc_sample_datain : msp_sample_datain; 155 | 156 | // Serial debug interface for viewing registers: 157 | reg [3:0] debug_address; 158 | reg debug_out; 159 | always @ (posedge debug_clk or posedge reset) begin 160 | if(reset) begin 161 | debug_address <= 4'd0; 162 | end else begin 163 | debug_address <= debug_address + 4'd1; 164 | end 165 | end 166 | always @ (debug_address) begin 167 | case(debug_address) 168 | 0: debug_out = packet_complete; 169 | 1: debug_out = cmd_complete; 170 | 2: debug_out = handlematch; 171 | 3: debug_out = docrc; 172 | 4: debug_out = rx_en; 173 | 5: debug_out = tx_en; 174 | 6: debug_out = bitout; 175 | 7: debug_out = bitclk; 176 | 8: debug_out = rngbitin; 177 | 9: debug_out = rx_overflow; 178 | 10: debug_out = tx_done; 179 | 11: debug_out = txsetupdone; 180 | 12: debug_out = 1'b0; 181 | 13: debug_out = 1'b1; 182 | 14: debug_out = 1'b0; 183 | 15: debug_out = 1'b1; 184 | default: debug_out = 1'b0; 185 | endcase 186 | end 187 | 188 | // MODULES! :) 189 | 190 | controller U_CTL (reset, clk, rx_overflow, rx_cmd, currentrn, currenthandle, 191 | packet_complete, txsetupdone, tx_done, 192 | rx_en, tx_en, docrc, handlematch, 193 | bitsrcselect, readfrommsp, readwriteptr, rx_q, rx_updn, 194 | use_uid, use_q, comm_enable); 195 | 196 | txsettings U_SET (reset, trcal_in, m_in, dr_in, trext_in, query_complete, 197 | trcal_out, m_out, dr_out, trext_out); 198 | 199 | rx U_RX (rx_reset, clk, demodin, bitout, bitclk, rx_overflow, trcal_in, rngbitin); 200 | cmdparser U_CMD (rxtop_reset, bitout, bitclk, rx_cmd, packet_complete, cmd_complete, 201 | m_in, trext_in, dr_in); 202 | 203 | packetparse U_PRSE (rx_reset, bitout, bitclk, rx_cmd, rx_q, rx_updn, 204 | currenthandle, currentrn, handlematch, 205 | readwritebank, readwriteptr, readwords, 206 | writedataout, writedataclk ); 207 | 208 | rng U_RNG (tx_reset, reset, rngbitin, rngbitinclk, rngbitclk, rngbitsrc, rngdatadone, currentrn); 209 | epc U_EPC (tx_reset, epcbitclk, epcbitsrc, epcdatadone); 210 | read U_READ (tx_reset, readbitclk, readbitsrc, readdatadone, 211 | read_sample_ctl, read_sample_clk, read_sample_datain, 212 | currenthandle); 213 | uid U_UID (tx_reset, uidbitclk, uidbitsrc, uiddatadone, 214 | uid_byte_in, uid_addr_out, uid_clk_out); 215 | 216 | sequencer U_SEQ (tx_reset, rx_overflow, clk, m_out, dr_out, docrc, trext_out, 217 | trcal_out, txbitsrc, txdatadone, txbitclk, modout, txsetupdone, tx_done); 218 | 219 | endmodule 220 | -------------------------------------------------------------------------------- /Arduino/InProgress/ClientLowPower/src/clientlowpower/ClientLowPower.java: -------------------------------------------------------------------------------- 1 | /* 2 | * To change this license header, choose License Headers in Project Properties. 3 | * To change this template file, choose Tools | Templates 4 | * and open the template in the editor. 5 | */ 6 | 7 | package clientlowpower; 8 | 9 | 10 | import gnu.io.CommPort; 11 | import gnu.io.CommPortIdentifier; 12 | import gnu.io.NoSuchPortException; 13 | import gnu.io.PortInUseException; 14 | import gnu.io.SerialPort; 15 | import gnu.io.UnsupportedCommOperationException; 16 | import java.awt.FlowLayout; 17 | import java.awt.event.ActionEvent; 18 | import java.awt.event.ActionListener; 19 | import java.io.File; 20 | 21 | import java.io.IOException; 22 | import java.io.InputStream; 23 | import java.io.OutputStream; 24 | import javax.swing.JButton; 25 | 26 | import javax.swing.JFrame; 27 | import javax.swing.JLabel; 28 | import javax.swing.JPanel; 29 | import javax.swing.JTextArea; 30 | import javax.swing.JTextField; 31 | /** 32 | * 33 | * @author deathmonkey 34 | */ 35 | public class ClientLowPower implements ActionListener 36 | { 37 | JFrame gui = new JFrame("Low Power Client"); 38 | JPanel guiPanel = new JPanel(); 39 | 40 | JButton powerState = new JButton("Power On"); 41 | JButton serialConnected = new JButton("Open Serial Line"); 42 | JButton sensorOne = new JButton("Sensor One"); 43 | JButton sensorTwo = new JButton("Sensor Two"); 44 | JButton sensorThree = new JButton("Sensor Three"); 45 | 46 | JLabel serialConnectedLabel = new JLabel("Not Connected"); 47 | JLabel powerStateLabel = new JLabel(" Powered Off "); 48 | JLabel sensorOneLabel = new JLabel("Sensor One Not Calibrated"); 49 | JLabel sensorTwoLabel = new JLabel("Sensor Two Not Calibrated"); 50 | JLabel sensorThreeLabel = new JLabel("Sensor Three Not Calibrated"); 51 | 52 | JTextField errorField = new JTextField(15); 53 | JTextField sensorOneField = new JTextField(15); 54 | JTextField sensorTwoField = new JTextField(15); 55 | JTextField sensorThreeField = new JTextField(15); 56 | 57 | JLabel sensorOneLabelField = new JLabel("Sensor One"); 58 | JLabel sensorTwoLabelField = new JLabel("Sensor Two"); 59 | JLabel sensorThreeLabelField = new JLabel("Sensor Three"); 60 | 61 | FlowLayout layout = new FlowLayout(); 62 | 63 | File sensorOneFile = new File("SensorOne.txt"); 64 | File sensorTwoFile = new File("SensorTwo.txt"); 65 | File sensotThreeFile = new File("SensorThree.txt"); 66 | 67 | public ClientLowPower() 68 | { 69 | gui.setSize(210, 500); 70 | guiPanel.add(serialConnectedLabel); 71 | guiPanel.add(serialConnected); 72 | guiPanel.add(powerStateLabel); 73 | guiPanel.add(powerState); 74 | guiPanel.add(sensorOneLabel); 75 | guiPanel.add(sensorOne); 76 | guiPanel.add(sensorTwoLabel); 77 | guiPanel.add(sensorTwo); 78 | guiPanel.add(sensorThreeLabel); 79 | guiPanel.add(sensorThree); 80 | guiPanel.add(new JLabel(" Error ")); 81 | guiPanel.add(errorField); 82 | guiPanel.add(sensorOneLabelField); 83 | guiPanel.add(sensorOneField); 84 | guiPanel.add(sensorTwoLabelField); 85 | guiPanel.add(sensorTwoField); 86 | guiPanel.add(sensorThreeLabelField); 87 | guiPanel.add(sensorThreeField); 88 | errorField.setText("No Error"); 89 | gui.add(guiPanel); 90 | gui.setVisible(true); 91 | gui.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE); 92 | 93 | powerState.addActionListener(this); 94 | serialConnected.addActionListener(this); 95 | sensorOne.addActionListener(this); 96 | sensorTwo.addActionListener(this); 97 | sensorThree.addActionListener(this); 98 | } 99 | 100 | /** 101 | * @param args the command line arguments 102 | */ 103 | public static void main(String[] args) 104 | { 105 | // TODO code application logic here 106 | new ClientLowPower(); 107 | 108 | } 109 | 110 | @Override 111 | public void actionPerformed(ActionEvent e) 112 | { 113 | if(e.getSource() == powerState) 114 | { 115 | powerStateLabel.setText(" Power On "); 116 | 117 | 118 | } 119 | else if(e.getSource() == serialConnected) 120 | { 121 | try 122 | { 123 | CommPortIdentifier portIdentifier = CommPortIdentifier.getPortIdentifier("/dev/ttyACM0"); 124 | System.out.println("portIdentifier: " + portIdentifier.toString()); 125 | if (portIdentifier.isCurrentlyOwned()) 126 | { 127 | System.out.println("Error: Port is currently in use"); 128 | } 129 | else 130 | { 131 | CommPort commPort = portIdentifier.open(this.getClass().getName(), 2000); 132 | System.out.println("comPort: "+ commPort.toString()); 133 | if (commPort instanceof SerialPort) 134 | { 135 | SerialPort serialPort = (SerialPort) commPort; 136 | System.out.println("serialPort: " + serialPort.getName()); 137 | serialPort.setSerialPortParams(9600, SerialPort.DATABITS_8, SerialPort.STOPBITS_1, SerialPort.PARITY_NONE); 138 | 139 | InputStream in = serialPort.getInputStream(); 140 | OutputStream out = serialPort.getOutputStream(); 141 | 142 | (new Thread(new SerialReader(in))).start(); 143 | (new Thread(new SerialWriter(out))).start(); 144 | serialConnectedLabel.setText(" Connected "); 145 | 146 | } 147 | else 148 | { 149 | System.out.println("Error: Only serial ports are handled"); 150 | } 151 | } 152 | } 153 | catch(NoSuchPortException exception) 154 | { 155 | exception.printStackTrace(); 156 | } 157 | catch (PortInUseException exception) 158 | { 159 | exception.printStackTrace(); 160 | } 161 | catch (UnsupportedCommOperationException exception) 162 | { 163 | exception.printStackTrace(); 164 | } 165 | catch (IOException exception) 166 | { 167 | exception.printStackTrace(); 168 | } 169 | serialConnectedLabel.setText(" Connected "); 170 | } 171 | else if(e.getSource() == sensorOne) 172 | { 173 | sensorOneLabel.setText("Sensor One Calibrated"); 174 | } 175 | else if(e.getSource() == sensorTwo) 176 | { 177 | sensorTwoLabel.setText("Sensor Two Calibrated"); 178 | } 179 | else if(e.getSource() == sensorThree) 180 | { 181 | sensorThreeLabel.setText("Sensor Three Calibrated"); 182 | } 183 | } 184 | 185 | 186 | private static class SerialWriter implements Runnable 187 | { 188 | public OutputStream out; 189 | public String string = null; 190 | public boolean writeState; 191 | 192 | public SerialWriter(OutputStream out) 193 | { 194 | this.out = out; 195 | writeState = false; 196 | } 197 | 198 | @Override 199 | public void run() 200 | { 201 | try 202 | { 203 | while(!writeState); 204 | int c = 0; 205 | while ((c = System.in.read()) > -1) 206 | { 207 | while(!writeState); 208 | this.out.write(Byte.parseByte(string)); 209 | writeState = false; 210 | } 211 | } 212 | catch (IOException e) 213 | { 214 | e.printStackTrace(); 215 | } 216 | } 217 | } 218 | 219 | 220 | private static class SerialReader implements Runnable 221 | { 222 | 223 | InputStream in; 224 | 225 | public SerialReader(InputStream in) 226 | { 227 | this.in = in; 228 | } 229 | 230 | @Override 231 | public void run() 232 | { 233 | byte[] buffer = new byte[1024]; 234 | int len = -1; 235 | try 236 | { 237 | while ((len = this.in.read(buffer)) > -1) 238 | { 239 | System.out.print(new String(buffer, 0, len)); 240 | 241 | } 242 | } 243 | catch (IOException e) 244 | { 245 | e.printStackTrace(); 246 | } 247 | 248 | } 249 | } 250 | 251 | 252 | } 253 | -------------------------------------------------------------------------------- /OLD/I2C/test/transcript: -------------------------------------------------------------------------------- 1 | # // ModelSim SE-64 6.3d Nov 26 2007 Linux 2.6.32-431.1.2.el6.x86_64 2 | # // 3 | # // Copyright 1991-2007 Mentor Graphics Corporation 4 | # // All Rights Reserved. 5 | # // 6 | # // THIS WORK CONTAINS TRADE SECRET AND 7 | # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY 8 | # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS 9 | # // AND IS SUBJECT TO LICENSE TERMS. 10 | # // 11 | # vsim -novopt testbench1 12 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 13 | # Loading work.testbench1 14 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 15 | # Loading work.test1 16 | add wave sim:/testbench1/u1/* 17 | log -r * 18 | run -all 19 | # ** Note: $finish : test1.v(139) 20 | # Time: 274 ns Iteration: 0 Instance: /testbench1 21 | # 1 22 | # Break in Module testbench1 at test1.v line 139 23 | vlog test1.v 24 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 25 | # -- Compiling module test1 26 | # -- Compiling module testbench1 27 | # 28 | # Top level modules: 29 | # testbench1 30 | restart 31 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 32 | # Loading work.testbench1 33 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 34 | # Loading work.test1 35 | run -all 36 | # ** Note: $finish : test1.v(117) 37 | # Time: 274 ns Iteration: 0 Instance: /testbench1 38 | # 1 39 | # Break in Module testbench1 at test1.v line 117 40 | vlog test1.v 41 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 42 | # -- Compiling module test1 43 | # -- Compiling module testbench1 44 | # 45 | # Top level modules: 46 | # testbench1 47 | restart -f 48 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 49 | # Loading work.testbench1 50 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 51 | # Loading work.test1 52 | run -all 53 | # ** Note: $finish : test1.v(110) 54 | # Time: 274 ns Iteration: 0 Instance: /testbench1 55 | # 1 56 | # Break in Module testbench1 at test1.v line 110 57 | vlog test1.v 58 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 59 | # -- Compiling module test1 60 | # -- Compiling module testbench1 61 | # 62 | # Top level modules: 63 | # testbench1 64 | restart -f 65 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 66 | # Loading work.testbench1 67 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 68 | # Loading work.test1 69 | run -all 70 | # ** Note: $finish : test1.v(110) 71 | # Time: 274 ns Iteration: 0 Instance: /testbench1 72 | # 1 73 | # Break in Module testbench1 at test1.v line 110 74 | restart -f 75 | vlog test1.v 76 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 77 | # -- Compiling module test1 78 | # -- Compiling module testbench1 79 | # 80 | # Top level modules: 81 | # testbench1 82 | run -all 83 | # ** Note: $finish : test1.v(110) 84 | # Time: 274 ns Iteration: 0 Instance: /testbench1 85 | # 1 86 | # Break in Module testbench1 at test1.v line 110 87 | vlog test1.v 88 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 89 | # -- Compiling module test1 90 | # ** Error: test1.v(33): Register is illegal in left-hand side of continuous assignment 91 | # -- Compiling module testbench1 92 | # /ncsu/modelsim63/linux_x86_64/vlog failed. 93 | vlog test1.v 94 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 95 | # -- Compiling module test1 96 | # ** Error: test1.v(33): Register is illegal in left-hand side of continuous assignment 97 | # -- Compiling module testbench1 98 | # /ncsu/modelsim63/linux_x86_64/vlog failed. 99 | vlog test1.v 100 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 101 | # -- Compiling module test1 102 | # -- Compiling module testbench1 103 | # 104 | # Top level modules: 105 | # testbench1 106 | restart -f 107 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 108 | # Loading work.testbench1 109 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 110 | # Loading work.test1 111 | run -all 112 | # ** Note: $finish : test1.v(108) 113 | # Time: 274 ns Iteration: 0 Instance: /testbench1 114 | # 1 115 | # Break in Module testbench1 at test1.v line 108 116 | vlog test1.v 117 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 118 | # -- Compiling module test1 119 | # -- Compiling module testbench1 120 | # 121 | # Top level modules: 122 | # testbench1 123 | restart -f 124 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 125 | # Loading work.testbench1 126 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 127 | # Loading work.test1 128 | run -all 129 | # ** Note: $finish : test1.v(112) 130 | # Time: 274 ns Iteration: 0 Instance: /testbench1 131 | # 1 132 | # Break in Module testbench1 at test1.v line 112 133 | vlog test1.v 134 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 135 | # -- Compiling module test1 136 | # -- Compiling module testbench1 137 | # 138 | # Top level modules: 139 | # testbench1 140 | restart -f 141 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 142 | # Loading work.testbench1 143 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 144 | # Loading work.test1 145 | run -all 146 | # ** Note: $finish : test1.v(112) 147 | # Time: 274 ns Iteration: 0 Instance: /testbench1 148 | # 1 149 | # Break in Module testbench1 at test1.v line 112 150 | vlog test1.v 151 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 152 | # -- Compiling module test1 153 | # -- Compiling module testbench1 154 | # 155 | # Top level modules: 156 | # testbench1 157 | restart -f 158 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 159 | # Loading work.testbench1 160 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 161 | # Loading work.test1 162 | run -all 163 | # ** Note: $finish : test1.v(129) 164 | # Time: 274 ns Iteration: 0 Instance: /testbench1 165 | # 1 166 | # Break in Module testbench1 at test1.v line 129 167 | vlog test1.v 168 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 169 | # -- Compiling module test1 170 | # -- Compiling module testbench1 171 | # 172 | # Top level modules: 173 | # testbench1 174 | restart -f 175 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 176 | # Loading work.testbench1 177 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 178 | # Loading work.test1 179 | run -all 180 | # ** Note: $finish : test1.v(116) 181 | # Time: 274 ns Iteration: 0 Instance: /testbench1 182 | # 1 183 | # Break in Module testbench1 at test1.v line 116 184 | vlog test1.v 185 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 186 | # -- Compiling module test1 187 | # -- Compiling module testbench1 188 | # 189 | # Top level modules: 190 | # testbench1 191 | restart -f 192 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 193 | # Loading work.testbench1 194 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 195 | # Loading work.test1 196 | run -all 197 | # ** Note: $finish : test1.v(129) 198 | # Time: 274 ns Iteration: 0 Instance: /testbench1 199 | # 1 200 | # Break in Module testbench1 at test1.v line 129 201 | vlog test1.v 202 | # Model Technology ModelSim SE-64 vlog 6.3d Compiler 2007.11 Nov 26 2007 203 | # -- Compiling module test1 204 | # -- Compiling module testbench1 205 | # 206 | # Top level modules: 207 | # testbench1 208 | restart -f 209 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.testbench1 210 | # Loading work.testbench1 211 | # Refreshing /afs/unity.ncsu.edu/users/j/jasteve4/Documents/NCSU-Low-Power-RFID/testing/I2C/test/modelsim_work.test1 212 | # Loading work.test1 213 | run -all 214 | # ** Note: $finish : test1.v(126) 215 | # Time: 312 ns Iteration: 0 Instance: /testbench1 216 | # 1 217 | # Break in Module testbench1 at test1.v line 126 218 | -------------------------------------------------------------------------------- /Memory/slave.v: -------------------------------------------------------------------------------- 1 | module slave( 2 | input wire [6:0] my_addr, 3 | input wire [7:0] measurement, 4 | input wire en, 5 | input wire reset, 6 | input wire scl, 7 | inout wire sda 8 | ); 9 | 10 | reg stop, start, mode; 11 | reg [7:0] input_buffer; 12 | reg [6:0] input_address; 13 | reg [2:0] state; 14 | reg [4:0] counter; 15 | reg sda_output, sda_out; 16 | reg sda_enable, sda_en; 17 | 18 | assign #(1) sda = (sda_enable) ? ( sda_output ) ? 1'bz : 1'b0 : 1'bz; 19 | assign sda_in = sda; 20 | 21 | 22 | always@( negedge scl or negedge reset ) 23 | begin 24 | if( !reset ) 25 | begin 26 | sda_enable <= 0; 27 | sda_output <= 0; 28 | end 29 | else 30 | begin 31 | sda_enable <= sda_en; 32 | sda_output <= sda_out; 33 | end 34 | end 35 | 36 | always@( negedge sda ) 37 | begin 38 | if( scl ) 39 | begin 40 | start <= 1; 41 | end 42 | else 43 | begin 44 | start <= 0; 45 | end 46 | end 47 | 48 | 49 | always@( posedge sda ) 50 | begin 51 | if( scl ) 52 | begin 53 | stop <= 1; 54 | end 55 | else 56 | begin 57 | stop <= 0; 58 | end 59 | end 60 | 61 | always@(posedge scl or negedge reset) 62 | begin 63 | if( ~reset ) 64 | begin 65 | state <= 0; 66 | input_address <= 0; 67 | counter <= 0; 68 | mode <= 0; 69 | input_buffer <= 0; 70 | sda_en <= 0; 71 | sda_out <= 0; 72 | end 73 | else 74 | begin 75 | case( state ) 76 | 0: 77 | begin 78 | if( start && en ) 79 | begin 80 | state <=1; 81 | input_address <= {input_address, sda}; 82 | counter <= 1; 83 | mode <= 0; 84 | input_buffer <= 0; 85 | sda_en <= 0; 86 | sda_out <= 0; 87 | end 88 | else 89 | begin 90 | state <= 0; 91 | input_address <= 0; 92 | counter <= 0; 93 | mode <= 0; 94 | input_buffer <= 0; 95 | sda_en <= 0; 96 | sda_out <= 0; 97 | end 98 | end 99 | 1: 100 | begin 101 | if(counter < 7 ) 102 | begin 103 | state <= 1; 104 | input_address <= {input_address, sda}; 105 | counter <= counter +1; 106 | mode <= 0; 107 | input_buffer <= 0; 108 | sda_en <= 0; 109 | sda_out <= 0; 110 | end 111 | else 112 | begin 113 | if(input_address == my_addr) 114 | begin 115 | if( sda ) 116 | begin 117 | state <= 2; 118 | input_address <= 0; 119 | counter <= 0; 120 | mode <= sda; 121 | input_buffer <= 0; 122 | sda_en <= 1; 123 | sda_out <= 0; 124 | end 125 | else 126 | begin 127 | state <= 5; 128 | input_address <= 0; 129 | counter <= 0; 130 | mode <= sda; 131 | input_buffer <= 0; 132 | sda_en <= 1; 133 | sda_out <= 0; 134 | end 135 | end 136 | else 137 | begin 138 | state <= 0; 139 | input_address <= 0; 140 | counter <= 0; 141 | mode <= 0; 142 | input_buffer <= 0; 143 | sda_en <= 0; 144 | sda_out <= 0; 145 | end 146 | end 147 | end 148 | 2: 149 | begin 150 | if( !stop ) 151 | begin 152 | if( counter < 8 ) 153 | begin 154 | state <= 2; 155 | input_address <= 0; 156 | counter <= counter + 1; 157 | mode <= 0; 158 | input_buffer <= 0; 159 | sda_en <= 1; 160 | sda_out <= measurement[7 - counter]; 161 | end 162 | else 163 | begin 164 | state <= 4; 165 | input_address <= 0; 166 | counter <= 0; 167 | mode <= 0; 168 | input_buffer <= 0; 169 | sda_en <= 0; 170 | sda_out <= 0; 171 | end 172 | end 173 | else 174 | begin 175 | state <= 0; 176 | input_address <= 0; 177 | counter <= 0; 178 | mode <= 0; 179 | input_buffer <= 0; 180 | sda_en <= 0; 181 | sda_out <= 0; 182 | end 183 | end 184 | 3: 185 | begin 186 | if( !stop ) 187 | begin 188 | if( counter < 7 ) 189 | begin 190 | state <= 3; 191 | input_address <= 0; 192 | counter <= counter + 1; 193 | mode <= 0; 194 | input_buffer <= {input_buffer, sda}; 195 | sda_en <= 0; 196 | sda_out <= 0; 197 | end 198 | else if(counter == 7) 199 | begin 200 | state <= 3; 201 | input_address <= 0; 202 | counter <= counter +1; 203 | mode <= 0; 204 | input_buffer <= {input_buffer,sda}; 205 | sda_en <= 0; 206 | sda_out <= 0; 207 | end 208 | else 209 | begin 210 | state <= 3; 211 | input_address <= 0; 212 | counter <= 0; 213 | mode <= 0; 214 | input_buffer <= {input_buffer,sda}; 215 | sda_en <= 1; 216 | sda_out <= 0; 217 | end 218 | end 219 | else 220 | begin 221 | state <= 0; 222 | input_address <= 0; 223 | counter <= 0; 224 | mode <= 0; 225 | input_buffer <= 0; 226 | sda_en <= 0; 227 | sda_out <= 0; 228 | end 229 | end 230 | 4: 231 | begin 232 | if( sda ) 233 | begin 234 | state <= 0; 235 | input_address <= 0; 236 | counter <= 0; 237 | mode <= 0; 238 | input_buffer <= 0; 239 | sda_en <= 0; 240 | sda_out <= 0; 241 | end 242 | else 243 | begin 244 | state <= 2; 245 | input_address <= 0; 246 | counter <= counter + 1; 247 | mode <= mode; 248 | input_buffer <= 0; 249 | sda_en <= 1; 250 | sda_out <= measurement[7 - counter]; 251 | end 252 | end 253 | 5: 254 | begin 255 | state <= 3; 256 | input_address <= 0; 257 | counter <= 0; 258 | mode <= mode; 259 | input_buffer <= 0; 260 | sda_en <= 0; 261 | sda_out <= 0; 262 | end 263 | endcase 264 | end 265 | end 266 | endmodule 267 | --------------------------------------------------------------------------------