├── .gitignore ├── Fall 2023 ├── Final_Pic.png ├── Labs │ ├── Lab 4 │ │ ├── Implementation │ │ │ ├── .lso │ │ │ ├── Implementation.gise │ │ │ ├── Implementation.xise │ │ │ ├── ParityGenerator.bgn │ │ │ ├── ParityGenerator.bit │ │ │ ├── ParityGenerator.bld │ │ │ ├── ParityGenerator.cmd_log │ │ │ ├── ParityGenerator.drc │ │ │ ├── ParityGenerator.lso │ │ │ ├── ParityGenerator.ncd │ │ │ ├── ParityGenerator.ngc │ │ │ ├── ParityGenerator.ngd │ │ │ ├── ParityGenerator.ngr │ │ │ ├── ParityGenerator.par │ │ │ ├── ParityGenerator.pcf │ │ │ ├── ParityGenerator.prj │ │ │ ├── ParityGenerator.stx │ │ │ ├── ParityGenerator.syr │ │ │ ├── ParityGenerator.twr │ │ │ ├── ParityGenerator.twx │ │ │ ├── ParityGenerator.ucf │ │ │ ├── ParityGenerator.unroutes │ │ │ ├── ParityGenerator.ut │ │ │ ├── ParityGenerator.v │ │ │ ├── ParityGenerator.xst │ │ │ ├── ParityGenerator_bitgen.xwbt │ │ │ ├── ParityGenerator_envsettings.html │ │ │ ├── ParityGenerator_guide.ncd │ │ │ ├── ParityGenerator_map.map │ │ │ ├── ParityGenerator_map.mrp │ │ │ ├── ParityGenerator_map.ncd │ │ │ ├── ParityGenerator_map.ngm │ │ │ ├── ParityGenerator_pad.csv │ │ │ ├── ParityGenerator_pad.txt │ │ │ ├── ParityGenerator_summary.html │ │ │ ├── ParityGenerator_xst.xrpt │ │ │ ├── SOP_ParityGenerator.bgn │ │ │ ├── SOP_ParityGenerator.bit │ │ │ ├── SOP_ParityGenerator.bld │ │ │ ├── SOP_ParityGenerator.cmd_log │ │ │ ├── SOP_ParityGenerator.drc │ │ │ ├── SOP_ParityGenerator.lso │ │ │ ├── SOP_ParityGenerator.ncd │ │ │ ├── SOP_ParityGenerator.ngc │ │ │ ├── SOP_ParityGenerator.ngd │ │ │ ├── SOP_ParityGenerator.ngr │ │ │ ├── SOP_ParityGenerator.pad │ │ │ ├── SOP_ParityGenerator.par │ │ │ ├── SOP_ParityGenerator.pcf │ │ │ ├── SOP_ParityGenerator.prj │ │ │ ├── SOP_ParityGenerator.ptwx │ │ │ ├── SOP_ParityGenerator.stx │ │ │ ├── SOP_ParityGenerator.syr │ │ │ ├── SOP_ParityGenerator.twr │ │ │ ├── SOP_ParityGenerator.twx │ │ │ ├── SOP_ParityGenerator.unroutes │ │ │ ├── SOP_ParityGenerator.ut │ │ │ ├── SOP_ParityGenerator.v │ │ │ ├── SOP_ParityGenerator.xpi │ │ │ ├── SOP_ParityGenerator.xst │ │ │ ├── SOP_ParityGenerator_bitgen.xwbt │ │ │ ├── SOP_ParityGenerator_envsettings.html │ │ │ ├── SOP_ParityGenerator_guide.ncd │ │ │ ├── SOP_ParityGenerator_map.map │ │ │ ├── SOP_ParityGenerator_map.mrp │ │ │ ├── SOP_ParityGenerator_map.ncd │ │ │ ├── SOP_ParityGenerator_map.ngm │ │ │ ├── SOP_ParityGenerator_map.xrpt │ │ │ ├── SOP_ParityGenerator_ngdbuild.xrpt │ │ │ ├── SOP_ParityGenerator_pad.csv │ │ │ ├── SOP_ParityGenerator_pad.txt │ │ │ ├── SOP_ParityGenerator_par.xrpt │ │ │ ├── SOP_ParityGenerator_summary.html │ │ │ ├── SOP_ParityGenerator_summary.xml │ │ │ ├── SOP_ParityGenerator_usage.xml │ │ │ ├── SOP_ParityGenerator_xst.xrpt │ │ │ ├── _impact.cmd │ │ │ ├── _impact.log │ │ │ ├── _ngo │ │ │ │ └── netlist.lst │ │ │ ├── _xmsgs │ │ │ │ ├── bitgen.xmsgs │ │ │ │ ├── map.xmsgs │ │ │ │ ├── ngdbuild.xmsgs │ │ │ │ ├── par.xmsgs │ │ │ │ ├── pn_parser.xmsgs │ │ │ │ ├── trce.xmsgs │ │ │ │ └── xst.xmsgs │ │ │ ├── iseconfig │ │ │ │ ├── Implementation.projectmgr │ │ │ │ └── ParityGenerator.xreport │ │ │ ├── pa.fromHdl.tcl │ │ │ ├── pa.fromNetlist.tcl │ │ │ ├── planAhead.ngc2edif.log │ │ │ ├── planAhead_pid16534.debug │ │ │ ├── planAhead_pid17016.debug │ │ │ ├── planAhead_pid18719.debug │ │ │ ├── planAhead_pid19013.debug │ │ │ ├── planAhead_run_1 │ │ │ │ ├── planAhead.jou │ │ │ │ ├── planAhead.log │ │ │ │ └── planAhead_run.log │ │ │ ├── planAhead_run_2 │ │ │ │ ├── Implementation.data │ │ │ │ │ ├── constrs_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ ├── sim_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ ├── sources_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── Implementation.ppr │ │ │ │ ├── planAhead.jou │ │ │ │ ├── planAhead.log │ │ │ │ └── planAhead_run.log │ │ │ ├── planAhead_run_3 │ │ │ │ ├── Implementation.data │ │ │ │ │ ├── cache │ │ │ │ │ │ └── SOP_ParityGenerator_ngc_9ab4f5bc.edif │ │ │ │ │ ├── constrs_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ ├── runs │ │ │ │ │ │ ├── impl_1.psg │ │ │ │ │ │ └── runs.xml │ │ │ │ │ ├── sim_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ ├── sources_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── Implementation.ppr │ │ │ │ ├── planAhead.jou │ │ │ │ ├── planAhead.log │ │ │ │ └── planAhead_run.log │ │ │ ├── planAhead_run_4 │ │ │ │ ├── Implementation.data │ │ │ │ │ ├── cache │ │ │ │ │ │ └── SOP_ParityGenerator_ngc_9ab4f5bc.edif │ │ │ │ │ ├── constrs_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ ├── runs │ │ │ │ │ │ ├── impl_1.psg │ │ │ │ │ │ └── runs.xml │ │ │ │ │ ├── sim_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ ├── sources_1 │ │ │ │ │ │ └── fileset.xml │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── Implementation.ppr │ │ │ │ ├── planAhead.jou │ │ │ │ ├── planAhead.log │ │ │ │ └── planAhead_run.log │ │ │ ├── usage_statistics_webtalk.html │ │ │ ├── webtalk.log │ │ │ ├── webtalk_pn.xml │ │ │ ├── xlnx_auto_0_xdb │ │ │ │ └── cst.xbcd │ │ │ └── xst │ │ │ │ └── work │ │ │ │ ├── hdllib.ref │ │ │ │ ├── vlg1C │ │ │ │ └── _parity_generator.bin │ │ │ │ └── vlg65 │ │ │ │ └── _s_o_p___parity_generator.bin │ │ └── ParityBit │ │ │ ├── .lso │ │ │ ├── ParityBit.gise │ │ │ ├── ParityBit.xise │ │ │ ├── ParityGenerator.cmd_log │ │ │ ├── ParityGenerator.prj │ │ │ ├── ParityGenerator.spl │ │ │ ├── ParityGenerator.stx │ │ │ ├── ParityGenerator.sym │ │ │ ├── ParityGenerator.tfi │ │ │ ├── ParityGenerator.v │ │ │ ├── ParityGenerator.xst │ │ │ ├── ParityGenerator_TB.cmd_log │ │ │ ├── ParityGenerator_TB.lso │ │ │ ├── ParityGenerator_TB.prj │ │ │ ├── ParityGenerator_TB.syr │ │ │ ├── ParityGenerator_TB.v │ │ │ ├── ParityGenerator_TB.xst │ │ │ ├── ParityGenerator_TB_envsettings.html │ │ │ ├── ParityGenerator_TB_isim_beh.exe │ │ │ ├── ParityGenerator_TB_isim_beh1.wdb │ │ │ ├── ParityGenerator_TB_stx_beh.prj │ │ │ ├── ParityGenerator_TB_summary.html │ │ │ ├── ParityGenerator_TB_xst.xrpt │ │ │ ├── SOP_ParityGenerator.prj │ │ │ ├── SOP_ParityGenerator.stx │ │ │ ├── SOP_ParityGenerator.v │ │ │ ├── SOP_ParityGenerator.xst │ │ │ ├── SOP_ParityGenerator_TB.v │ │ │ ├── SOP_ParityGenerator_TB_beh.prj │ │ │ ├── SOP_ParityGenerator_TB_isim_beh.exe │ │ │ ├── SOP_ParityGenerator_TB_isim_beh.wdb │ │ │ ├── SOP_ParityGenerator_TB_isim_beh1.wdb │ │ │ ├── SOP_ParityGenerator_TB_stx_beh.prj │ │ │ ├── SOP_ParityGenerator_isim_beh.exe │ │ │ ├── SOP_ParityGenerator_stx_beh.prj │ │ │ ├── _xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ └── xst.xmsgs │ │ │ ├── fuse.log │ │ │ ├── fuse.xmsgs │ │ │ ├── fuseRelaunch.cmd │ │ │ ├── iseconfig │ │ │ ├── ParityBit.projectmgr │ │ │ └── ParityGenerator_TB.xreport │ │ │ ├── isim.cmd │ │ │ ├── isim.log │ │ │ ├── isim │ │ │ ├── ParityGenerator_TB_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy1.dbg │ │ │ │ ├── ParityGenerator_TB_isim_beh.exe │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId1.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── ParityGenerator_TB_isim_beh.exe_main.c │ │ │ │ │ ├── ParityGenerator_TB_isim_beh.exe_main.lin64.o │ │ │ │ │ ├── m_07618084400293480704_4247149254.c │ │ │ │ │ ├── m_07618084400293480704_4247149254.didat │ │ │ │ │ ├── m_07618084400293480704_4247149254.lin64.o │ │ │ │ │ ├── m_08596763247464291979_1315026168.c │ │ │ │ │ ├── m_08596763247464291979_1315026168.didat │ │ │ │ │ ├── m_08596763247464291979_1315026168.lin64.o │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ └── m_16541823861846354283_2073120511.lin64.o │ │ │ ├── SOP_ParityGenerator_TB_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── ISimEngine-DesignHierarchy1.dbg │ │ │ │ ├── SOP_ParityGenerator_TB_isim_beh.exe │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── netId1.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── SOP_ParityGenerator_TB_isim_beh.exe_main.c │ │ │ │ │ ├── SOP_ParityGenerator_TB_isim_beh.exe_main.lin64.o │ │ │ │ │ ├── m_07618084400293480704_0663302490.c │ │ │ │ │ ├── m_07618084400293480704_0663302490.didat │ │ │ │ │ ├── m_07618084400293480704_0663302490.lin64.o │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ ├── m_16788694261097279505_0397876370.c │ │ │ │ │ ├── m_16788694261097279505_0397876370.didat │ │ │ │ │ └── m_16788694261097279505_0397876370.lin64.o │ │ │ ├── SOP_ParityGenerator_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── SOP_ParityGenerator_isim_beh.exe │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── SOP_ParityGenerator_isim_beh.exe_main.c │ │ │ │ │ ├── SOP_ParityGenerator_isim_beh.exe_main.lin64.o │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ ├── m_16788694261097279505_0397876370.c │ │ │ │ │ ├── m_16788694261097279505_0397876370.didat │ │ │ │ │ └── m_16788694261097279505_0397876370.lin64.o │ │ │ ├── isim_usage_statistics.html │ │ │ ├── lockfile │ │ │ ├── lockfile1 │ │ │ ├── pn_info │ │ │ ├── temp │ │ │ │ ├── @parity@generator.sdb │ │ │ │ ├── @parity@generator_@t@b.sdb │ │ │ │ ├── @s@o@p_@parity@generator.sdb │ │ │ │ ├── @s@o@p_@parity@generator_@t@b.sdb │ │ │ │ └── glbl.sdb │ │ │ └── work │ │ │ │ ├── @s@o@p_@parity@generator.sdb │ │ │ │ ├── @s@o@p_@parity@generator_@t@b.sdb │ │ │ │ └── glbl.sdb │ │ │ ├── webtalk_pn.xml │ │ │ ├── xilinxsim.ini │ │ │ └── xst │ │ │ └── work │ │ │ ├── hdllib.ref │ │ │ ├── vlg1C │ │ │ └── _parity_generator.bin │ │ │ ├── vlg59 │ │ │ └── _parity_generator___t_b.bin │ │ │ └── vlg65 │ │ │ └── _s_o_p___parity_generator.bin │ ├── Lab 5 │ │ ├── .lso │ │ ├── Decoder4x16 and function │ │ │ ├── .lso │ │ │ ├── _xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── decoder2x4.v │ │ │ ├── decoder4x16.prj │ │ │ ├── decoder4x16.stx │ │ │ ├── decoder4x16.v │ │ │ ├── decoder4x16.xst │ │ │ ├── decoder4x16_summary.html │ │ │ ├── function.v │ │ │ ├── function_with_dec4x16.prj │ │ │ ├── function_with_dec4x16.stx │ │ │ ├── function_with_dec4x16.v │ │ │ ├── function_with_dec4x16.xst │ │ │ ├── function_with_dec4x16_summary.html │ │ │ ├── fuse.log │ │ │ ├── fuse.xmsgs │ │ │ ├── fuseRelaunch.cmd │ │ │ ├── iseconfig │ │ │ │ ├── decoder4x16.xreport │ │ │ │ └── test.projectmgr │ │ │ ├── isim.cmd │ │ │ ├── isim.log │ │ │ ├── isim │ │ │ │ ├── isim_usage_statistics.html │ │ │ │ ├── lockfile │ │ │ │ ├── lockfile1 │ │ │ │ ├── pn_info │ │ │ │ ├── tb_decoder4x16_isim_beh.exe.sim │ │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ │ ├── isimcrash.log │ │ │ │ │ ├── isimkernel.log │ │ │ │ │ ├── netId.dat │ │ │ │ │ ├── tb_decoder4x16_isim_beh.exe │ │ │ │ │ ├── tmp_save │ │ │ │ │ │ └── _1 │ │ │ │ │ └── work │ │ │ │ │ │ ├── m_04729211710942299136_0274277177.c │ │ │ │ │ │ ├── m_04729211710942299136_0274277177.didat │ │ │ │ │ │ ├── m_04729211710942299136_0274277177.lin64.o │ │ │ │ │ │ ├── m_07162495332256470469_0727738315.c │ │ │ │ │ │ ├── m_07162495332256470469_0727738315.didat │ │ │ │ │ │ ├── m_07162495332256470469_0727738315.lin64.o │ │ │ │ │ │ ├── m_14477175212511074496_0410812591.c │ │ │ │ │ │ ├── m_14477175212511074496_0410812591.didat │ │ │ │ │ │ ├── m_14477175212511074496_0410812591.lin64.o │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ │ ├── tb_decoder4x16_isim_beh.exe_main.c │ │ │ │ │ │ └── tb_decoder4x16_isim_beh.exe_main.lin64.o │ │ │ │ ├── tb_function_with_dec4x16_isim_beh.exe.sim │ │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ │ ├── isimcrash.log │ │ │ │ │ ├── isimkernel.log │ │ │ │ │ ├── netId.dat │ │ │ │ │ ├── tb_function_with_dec4x16_isim_beh.exe │ │ │ │ │ ├── tmp_save │ │ │ │ │ │ └── _1 │ │ │ │ │ └── work │ │ │ │ │ │ ├── m_01580942110610943994_0062759626.c │ │ │ │ │ │ ├── m_01580942110610943994_0062759626.didat │ │ │ │ │ │ ├── m_01580942110610943994_0062759626.lin64.o │ │ │ │ │ │ ├── m_04729211710942299136_0274277177.c │ │ │ │ │ │ ├── m_04729211710942299136_0274277177.didat │ │ │ │ │ │ ├── m_04729211710942299136_0274277177.lin64.o │ │ │ │ │ │ ├── m_14477175212511074496_0410812591.c │ │ │ │ │ │ ├── m_14477175212511074496_0410812591.didat │ │ │ │ │ │ ├── m_14477175212511074496_0410812591.lin64.o │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ │ ├── m_17352977803267689174_4091618986.c │ │ │ │ │ │ ├── m_17352977803267689174_4091618986.didat │ │ │ │ │ │ ├── m_17352977803267689174_4091618986.lin64.o │ │ │ │ │ │ ├── tb_function_with_dec4x16_isim_beh.exe_main.c │ │ │ │ │ │ └── tb_function_with_dec4x16_isim_beh.exe_main.lin64.o │ │ │ │ └── work │ │ │ │ │ ├── decoder2x4.sdb │ │ │ │ │ ├── decoder4x16.sdb │ │ │ │ │ ├── function_with_dec4x16.sdb │ │ │ │ │ ├── glbl.sdb │ │ │ │ │ └── tb_function_with_dec4x16.sdb │ │ │ ├── tb_decoder4x16.v │ │ │ ├── tb_decoder4x16_beh.prj │ │ │ ├── tb_decoder4x16_isim_beh.exe │ │ │ ├── tb_decoder4x16_isim_beh.wdb │ │ │ ├── tb_decoder4x16_isim_beh1.wdb │ │ │ ├── tb_function_with_dec4x16.v │ │ │ ├── tb_function_with_dec4x16_beh.prj │ │ │ ├── tb_function_with_dec4x16_isim_beh.exe │ │ │ ├── tb_function_with_dec4x16_isim_beh.wdb │ │ │ ├── tb_function_with_dec4x16_isim_beh1.wdb │ │ │ ├── test.gise │ │ │ ├── test.xise │ │ │ ├── xilinxsim.ini │ │ │ └── xst │ │ │ │ └── work │ │ │ │ ├── hdllib.ref │ │ │ │ ├── vlg29 │ │ │ │ └── decoder4x16.bin │ │ │ │ ├── vlg5B │ │ │ │ └── function__with__dec4x16.bin │ │ │ │ └── vlg68 │ │ │ │ └── decoder2x4.bin │ │ ├── Lab5.gise │ │ ├── Lab5.xise │ │ ├── _impact.cmd │ │ ├── _impact.log │ │ ├── _ngo │ │ │ └── netlist.lst │ │ ├── _xmsgs │ │ │ ├── bitgen.xmsgs │ │ │ ├── map.xmsgs │ │ │ ├── ngdbuild.xmsgs │ │ │ ├── par.xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ ├── trce.xmsgs │ │ │ └── xst.xmsgs │ │ ├── decoder2x4.bgn │ │ ├── decoder2x4.bit │ │ ├── decoder2x4.bld │ │ ├── decoder2x4.cmd_log │ │ ├── decoder2x4.drc │ │ ├── decoder2x4.lso │ │ ├── decoder2x4.ncd │ │ ├── decoder2x4.ngc │ │ ├── decoder2x4.ngd │ │ ├── decoder2x4.ngr │ │ ├── decoder2x4.pad │ │ ├── decoder2x4.par │ │ ├── decoder2x4.pcf │ │ ├── decoder2x4.prj │ │ ├── decoder2x4.ptwx │ │ ├── decoder2x4.stx │ │ ├── decoder2x4.syr │ │ ├── decoder2x4.twr │ │ ├── decoder2x4.twx │ │ ├── decoder2x4.ucf │ │ ├── decoder2x4.unroutes │ │ ├── decoder2x4.ut │ │ ├── decoder2x4.v │ │ ├── decoder2x4.xpi │ │ ├── decoder2x4.xst │ │ ├── decoder2x4_bitgen.xwbt │ │ ├── decoder2x4_envsettings.html │ │ ├── decoder2x4_guide.ncd │ │ ├── decoder2x4_isim_beh.exe │ │ ├── decoder2x4_map.map │ │ ├── decoder2x4_map.mrp │ │ ├── decoder2x4_map.ncd │ │ ├── decoder2x4_map.ngm │ │ ├── decoder2x4_map.xrpt │ │ ├── decoder2x4_pad.csv │ │ ├── decoder2x4_pad.txt │ │ ├── decoder2x4_par.xrpt │ │ ├── decoder2x4_stx_beh.prj │ │ ├── decoder2x4_summary.html │ │ ├── decoder2x4_summary.xml │ │ ├── decoder2x4_usage.xml │ │ ├── decoder2x4_xst.xrpt │ │ ├── decoder4x16.prj │ │ ├── decoder4x16.stx │ │ ├── decoder4x16.v │ │ ├── decoder4x16.xst │ │ ├── decoder4x16_isim_beh.exe │ │ ├── decoder4x16_stx_beh.prj │ │ ├── decoder4x16_summary.html │ │ ├── function_with_dec4x16.bld │ │ ├── function_with_dec4x16.cmd_log │ │ ├── function_with_dec4x16.lso │ │ ├── function_with_dec4x16.ncd │ │ ├── function_with_dec4x16.ngc │ │ ├── function_with_dec4x16.ngd │ │ ├── function_with_dec4x16.ngr │ │ ├── function_with_dec4x16.par │ │ ├── function_with_dec4x16.pcf │ │ ├── function_with_dec4x16.prj │ │ ├── function_with_dec4x16.stx │ │ ├── function_with_dec4x16.syr │ │ ├── function_with_dec4x16.twr │ │ ├── function_with_dec4x16.twx │ │ ├── function_with_dec4x16.unroutes │ │ ├── function_with_dec4x16.v │ │ ├── function_with_dec4x16.xst │ │ ├── function_with_dec4x16_beh.prj │ │ ├── function_with_dec4x16_envsettings.html │ │ ├── function_with_dec4x16_guide.ncd │ │ ├── function_with_dec4x16_map.map │ │ ├── function_with_dec4x16_map.mrp │ │ ├── function_with_dec4x16_map.ncd │ │ ├── function_with_dec4x16_map.ngm │ │ ├── function_with_dec4x16_pad.csv │ │ ├── function_with_dec4x16_pad.txt │ │ ├── function_with_dec4x16_summary.html │ │ ├── function_with_dec4x16_xst.xrpt │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── iseconfig │ │ │ ├── Lab5.projectmgr │ │ │ ├── decoder2x4.xreport │ │ │ ├── decoder4x16.xreport │ │ │ └── function_with_dec4x16.xreport │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ │ ├── isim_usage_statistics.html │ │ │ ├── lockfile │ │ │ ├── lockfile1 │ │ │ ├── lockfile2 │ │ │ ├── pn_info │ │ │ ├── tb_decoder4x16_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy1.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId1.dat │ │ │ │ ├── tb_decoder4x16_isim_beh.exe │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── m_04729211710942299136_0274277177.c │ │ │ │ │ ├── m_04729211710942299136_0274277177.didat │ │ │ │ │ ├── m_04729211710942299136_0274277177.lin64.o │ │ │ │ │ ├── m_07162495332256470469_0727738315.c │ │ │ │ │ ├── m_07162495332256470469_0727738315.didat │ │ │ │ │ ├── m_07162495332256470469_0727738315.lin64.o │ │ │ │ │ ├── m_14477175212511074496_0410812591.c │ │ │ │ │ ├── m_14477175212511074496_0410812591.didat │ │ │ │ │ ├── m_14477175212511074496_0410812591.lin64.o │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ ├── tb_decoder4x16_isim_beh.exe_main.c │ │ │ │ │ └── tb_decoder4x16_isim_beh.exe_main.lin64.o │ │ │ ├── tb_function_with_dec4x16_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy2.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId2.dat │ │ │ │ ├── tb_function_with_dec4x16_isim_beh.exe │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── m_01580942110610943994_0062759626.c │ │ │ │ │ ├── m_01580942110610943994_0062759626.didat │ │ │ │ │ ├── m_01580942110610943994_0062759626.lin64.o │ │ │ │ │ ├── m_04729211710942299136_0274277177.c │ │ │ │ │ ├── m_04729211710942299136_0274277177.didat │ │ │ │ │ ├── m_04729211710942299136_0274277177.lin64.o │ │ │ │ │ ├── m_14477175212511074496_0410812591.c │ │ │ │ │ ├── m_14477175212511074496_0410812591.didat │ │ │ │ │ ├── m_14477175212511074496_0410812591.lin64.o │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ ├── m_17352977803267689174_4091618986.c │ │ │ │ │ ├── m_17352977803267689174_4091618986.didat │ │ │ │ │ ├── m_17352977803267689174_4091618986.lin64.o │ │ │ │ │ ├── tb_function_with_dec4x16_isim_beh.exe_main.c │ │ │ │ │ └── tb_function_with_dec4x16_isim_beh.exe_main.lin64.o │ │ │ └── work │ │ │ │ ├── decoder2x4.sdb │ │ │ │ ├── decoder4x16.sdb │ │ │ │ ├── function_with_dec4x16.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ └── tb_function_with_dec4x16.sdb │ │ ├── mux4x1.bgn │ │ ├── mux4x1.bit │ │ ├── mux4x1.bld │ │ ├── mux4x1.cmd_log │ │ ├── mux4x1.drc │ │ ├── mux4x1.lso │ │ ├── mux4x1.ncd │ │ ├── mux4x1.ngc │ │ ├── mux4x1.ngd │ │ ├── mux4x1.ngr │ │ ├── mux4x1.pad │ │ ├── mux4x1.par │ │ ├── mux4x1.pcf │ │ ├── mux4x1.prj │ │ ├── mux4x1.ptwx │ │ ├── mux4x1.stx │ │ ├── mux4x1.syr │ │ ├── mux4x1.twr │ │ ├── mux4x1.twx │ │ ├── mux4x1.ucf │ │ ├── mux4x1.unroutes │ │ ├── mux4x1.ut │ │ ├── mux4x1.v │ │ ├── mux4x1.xpi │ │ ├── mux4x1.xst │ │ ├── mux4x1_bitgen.xwbt │ │ ├── mux4x1_envsettings.html │ │ ├── mux4x1_guide.ncd │ │ ├── mux4x1_map.map │ │ ├── mux4x1_map.mrp │ │ ├── mux4x1_map.ncd │ │ ├── mux4x1_map.ngm │ │ ├── mux4x1_map.xrpt │ │ ├── mux4x1_ngdbuild.xrpt │ │ ├── mux4x1_pad.csv │ │ ├── mux4x1_pad.txt │ │ ├── mux4x1_par.xrpt │ │ ├── mux4x1_summary.html │ │ ├── mux4x1_summary.xml │ │ ├── mux4x1_usage.xml │ │ ├── mux4x1_xst.xrpt │ │ ├── pEncoder4x2.bld │ │ ├── pEncoder4x2.cmd_log │ │ ├── pEncoder4x2.lso │ │ ├── pEncoder4x2.ncd │ │ ├── pEncoder4x2.ngc │ │ ├── pEncoder4x2.ngd │ │ ├── pEncoder4x2.ngr │ │ ├── pEncoder4x2.pad │ │ ├── pEncoder4x2.par │ │ ├── pEncoder4x2.pcf │ │ ├── pEncoder4x2.prj │ │ ├── pEncoder4x2.ptwx │ │ ├── pEncoder4x2.stx │ │ ├── pEncoder4x2.syr │ │ ├── pEncoder4x2.twr │ │ ├── pEncoder4x2.twx │ │ ├── pEncoder4x2.ucf │ │ ├── pEncoder4x2.unroutes │ │ ├── pEncoder4x2.v │ │ ├── pEncoder4x2.xpi │ │ ├── pEncoder4x2.xst │ │ ├── pEncoder4x2_envsettings.html │ │ ├── pEncoder4x2_guide.ncd │ │ ├── pEncoder4x2_map.map │ │ ├── pEncoder4x2_map.mrp │ │ ├── pEncoder4x2_map.ncd │ │ ├── pEncoder4x2_map.ngm │ │ ├── pEncoder4x2_map.xrpt │ │ ├── pEncoder4x2_ngdbuild.xrpt │ │ ├── pEncoder4x2_pad.csv │ │ ├── pEncoder4x2_pad.txt │ │ ├── pEncoder4x2_par.xrpt │ │ ├── pEncoder4x2_summary.html │ │ ├── pEncoder4x2_summary.xml │ │ ├── pEncoder4x2_usage.xml │ │ ├── pEncoder4x2_xst.xrpt │ │ ├── pa.fromNetlist.tcl │ │ ├── planAhead.ngc2edif.log │ │ ├── planAhead_pid35227.debug │ │ ├── planAhead_pid35629.debug │ │ ├── planAhead_pid35988.debug │ │ ├── planAhead_pid36969.debug │ │ ├── planAhead_pid37227.debug │ │ ├── planAhead_run_1 │ │ │ ├── Lab5.data │ │ │ │ ├── cache │ │ │ │ │ └── decoder2x4_ngc_67dcf532.edif │ │ │ │ ├── constrs_1 │ │ │ │ │ ├── designprops.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── usercols.xml │ │ │ │ ├── runs │ │ │ │ │ ├── impl_1.psg │ │ │ │ │ └── runs.xml │ │ │ │ ├── sim_1 │ │ │ │ │ └── fileset.xml │ │ │ │ ├── sources_1 │ │ │ │ │ ├── chipscope.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── ports.xml │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ ├── project.wpc │ │ │ │ │ └── webtalk_pa.xml │ │ │ ├── Lab5.ppr │ │ │ ├── planAhead.jou │ │ │ ├── planAhead.log │ │ │ └── planAhead_run.log │ │ ├── planAhead_run_2 │ │ │ ├── Lab5.data │ │ │ │ ├── cache │ │ │ │ │ └── decoder2x4_ngc_67dcf532.edif │ │ │ │ ├── constrs_1 │ │ │ │ │ ├── designprops.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── usercols.xml │ │ │ │ ├── runs │ │ │ │ │ ├── impl_1.psg │ │ │ │ │ └── runs.xml │ │ │ │ ├── sim_1 │ │ │ │ │ └── fileset.xml │ │ │ │ ├── sources_1 │ │ │ │ │ ├── chipscope.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── ports.xml │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ ├── project.wpc │ │ │ │ │ └── webtalk_pa.xml │ │ │ ├── Lab5.ppr │ │ │ ├── planAhead.jou │ │ │ ├── planAhead.log │ │ │ └── planAhead_run.log │ │ ├── planAhead_run_3 │ │ │ ├── Lab5.data │ │ │ │ ├── cache │ │ │ │ │ └── decoder2x4_ngc_67dcf532.edif │ │ │ │ ├── constrs_1 │ │ │ │ │ ├── designprops.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── usercols.xml │ │ │ │ ├── runs │ │ │ │ │ ├── impl_1.psg │ │ │ │ │ └── runs.xml │ │ │ │ ├── sim_1 │ │ │ │ │ └── fileset.xml │ │ │ │ ├── sources_1 │ │ │ │ │ ├── chipscope.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── ports.xml │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ ├── project.wpc │ │ │ │ │ └── webtalk_pa.xml │ │ │ ├── Lab5.ppr │ │ │ ├── planAhead.jou │ │ │ ├── planAhead.log │ │ │ └── planAhead_run.log │ │ ├── planAhead_run_4 │ │ │ ├── Lab5.data │ │ │ │ ├── cache │ │ │ │ │ └── mux4x1_ngc_67dcf532.edif │ │ │ │ ├── constrs_1 │ │ │ │ │ ├── designprops.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── usercols.xml │ │ │ │ ├── runs │ │ │ │ │ ├── impl_1.psg │ │ │ │ │ └── runs.xml │ │ │ │ ├── sim_1 │ │ │ │ │ └── fileset.xml │ │ │ │ ├── sources_1 │ │ │ │ │ ├── chipscope.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── ports.xml │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ ├── project.wpc │ │ │ │ │ └── webtalk_pa.xml │ │ │ ├── Lab5.ppr │ │ │ ├── planAhead.jou │ │ │ ├── planAhead.log │ │ │ └── planAhead_run.log │ │ ├── planAhead_run_5 │ │ │ ├── Lab5.data │ │ │ │ ├── cache │ │ │ │ │ └── mux4x1_ngc_67dcf532.edif │ │ │ │ ├── constrs_1 │ │ │ │ │ ├── designprops.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── usercols.xml │ │ │ │ ├── runs │ │ │ │ │ ├── impl_1.psg │ │ │ │ │ └── runs.xml │ │ │ │ ├── sim_1 │ │ │ │ │ └── fileset.xml │ │ │ │ ├── sources_1 │ │ │ │ │ ├── chipscope.xml │ │ │ │ │ ├── fileset.xml │ │ │ │ │ └── ports.xml │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ ├── project.wpc │ │ │ │ │ └── webtalk_pa.xml │ │ │ ├── Lab5.ppr │ │ │ ├── planAhead.jou │ │ │ ├── planAhead.log │ │ │ └── planAhead_run.log │ │ ├── tb_decoder2x4.v │ │ ├── tb_decoder2x4_isim_beh.exe │ │ ├── tb_decoder2x4_stx_beh.prj │ │ ├── tb_decoder4x16_isim_beh.exe │ │ ├── tb_decoder4x16_isim_beh1.wdb │ │ ├── tb_function_with_dec4x16.v │ │ ├── tb_function_with_dec4x16_beh.prj │ │ ├── tb_function_with_dec4x16_isim_beh.exe │ │ ├── tb_function_with_dec4x16_isim_beh.wdb │ │ ├── tb_function_with_dec4x16_isim_beh2.wdb │ │ ├── tb_mux4x1.v │ │ ├── tb_mux4x1_isim_beh.exe │ │ ├── tb_mux4x1_stx_beh.prj │ │ ├── tb_pEncoder4x2.v │ │ ├── tb_pEncoder4x2_isim_beh.exe │ │ ├── tb_pEncoder4x2_isim_beh.wdb │ │ ├── tb_pEncoder4x2_isim_beh1.wdb │ │ ├── tb_pEncoder4x2_stx_beh.prj │ │ ├── usage_statistics_webtalk.html │ │ ├── webtalk.log │ │ ├── webtalk_pn.xml │ │ ├── xilinxsim.ini │ │ ├── xlnx_auto_0_xdb │ │ │ └── cst.xbcd │ │ └── xst │ │ │ └── work │ │ │ ├── hdllib.ref │ │ │ ├── vlg36 │ │ │ └── p_encoder4x2.bin │ │ │ ├── vlg5B │ │ │ └── function__with__dec4x16.bin │ │ │ ├── vlg68 │ │ │ └── decoder2x4.bin │ │ │ └── vlg6B │ │ │ └── mux4x1.bin │ ├── Lab 6 │ │ └── comparator │ │ │ ├── .lso │ │ │ ├── ThreeBitComparator.cmd_log │ │ │ ├── ThreeBitComparator.lso │ │ │ ├── ThreeBitComparator.ngr │ │ │ ├── ThreeBitComparator.prj │ │ │ ├── ThreeBitComparator.stx │ │ │ ├── ThreeBitComparator.syr │ │ │ ├── ThreeBitComparator.xst │ │ │ ├── ThreeBitComparator_envsettings.html │ │ │ ├── ThreeBitComparator_summary.html │ │ │ ├── ThreeBitComparator_xst.xrpt │ │ │ ├── _xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ └── xst.xmsgs │ │ │ ├── comp3.cmd_log │ │ │ ├── comp3.lso │ │ │ ├── comp3.ngr │ │ │ ├── comp3.prj │ │ │ ├── comp3.stx │ │ │ ├── comp3.syr │ │ │ ├── comp3.v │ │ │ ├── comp3.xst │ │ │ ├── comp3_envsettings.html │ │ │ ├── comp3_summary.html │ │ │ ├── comp3_xst.xrpt │ │ │ ├── comp_summary.html │ │ │ ├── comparator.gise │ │ │ ├── comparator.xise │ │ │ ├── comparator3.prj │ │ │ ├── comparator3.stx │ │ │ ├── comparator3.xst │ │ │ ├── comparator3_summary.html │ │ │ ├── fuse.log │ │ │ ├── fuse.xmsgs │ │ │ ├── fuseRelaunch.cmd │ │ │ ├── iseconfig │ │ │ ├── comp3.xreport │ │ │ └── comparator.projectmgr │ │ │ ├── isim.cmd │ │ │ ├── isim.log │ │ │ ├── isim │ │ │ ├── isim_usage_statistics.html │ │ │ ├── lockfile │ │ │ ├── pn_info │ │ │ ├── tb_comp3_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tb_comp3_isim_beh.exe │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── m_04449556141025364874_2000275818.c │ │ │ │ │ ├── m_04449556141025364874_2000275818.didat │ │ │ │ │ ├── m_04449556141025364874_2000275818.lin64.o │ │ │ │ │ ├── m_13053431338902791555_2782340395.c │ │ │ │ │ ├── m_13053431338902791555_2782340395.didat │ │ │ │ │ ├── m_13053431338902791555_2782340395.lin64.o │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ ├── tb_comp3_isim_beh.exe_main.c │ │ │ │ │ └── tb_comp3_isim_beh.exe_main.lin64.o │ │ │ ├── temp │ │ │ │ ├── comp3.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ └── tb_comp3.sdb │ │ │ └── work │ │ │ │ ├── comp3.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ └── tb_comp3.sdb │ │ │ ├── tb_comp3.v │ │ │ ├── tb_comp3_beh.prj │ │ │ ├── tb_comp3_isim_beh.exe │ │ │ ├── tb_comp3_isim_beh.wdb │ │ │ ├── tb_comp3_stx_beh.prj │ │ │ ├── three_bit_comparator_gl_summary.html │ │ │ ├── webtalk_pn.xml │ │ │ ├── xilinxsim.ini │ │ │ └── xst │ │ │ └── work │ │ │ ├── hdllib.ref │ │ │ ├── vlg33 │ │ │ └── _three_bit_comparator.bin │ │ │ ├── vlg4F │ │ │ └── comparator3.bin │ │ │ └── vlg6E │ │ │ └── comp3.bin │ ├── Lab 7 │ │ ├── add_sub.v │ │ ├── add_sub │ │ │ ├── _xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── add_sub.gise │ │ │ ├── add_sub.xise │ │ │ ├── fuse.log │ │ │ ├── fuse.xmsgs │ │ │ ├── fuseRelaunch.cmd │ │ │ ├── iseconfig │ │ │ │ ├── add_sub.projectmgr │ │ │ │ └── tb_adder_subtractor_4bit.xreport │ │ │ ├── isim.cmd │ │ │ ├── isim.log │ │ │ ├── isim │ │ │ │ ├── isim_usage_statistics.html │ │ │ │ ├── lockfile │ │ │ │ ├── pn_info │ │ │ │ ├── tb_adder_subtractor_4bit_delay_isim_beh.exe.sim │ │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ │ ├── isimcrash.log │ │ │ │ │ ├── isimkernel.log │ │ │ │ │ ├── netId.dat │ │ │ │ │ ├── tb_adder_subtractor_4bit_delay_isim_beh.exe │ │ │ │ │ ├── tmp_save │ │ │ │ │ │ └── _1 │ │ │ │ │ └── work │ │ │ │ │ │ ├── m_02223542811341278160_3890714917.c │ │ │ │ │ │ ├── m_02223542811341278160_3890714917.didat │ │ │ │ │ │ ├── m_02223542811341278160_3890714917.lin64.o │ │ │ │ │ │ ├── m_03707478635005068086_0014183270.c │ │ │ │ │ │ ├── m_03707478635005068086_0014183270.didat │ │ │ │ │ │ ├── m_03707478635005068086_0014183270.lin64.o │ │ │ │ │ │ ├── m_12245597318307620160_2950233121.c │ │ │ │ │ │ ├── m_12245597318307620160_2950233121.didat │ │ │ │ │ │ ├── m_12245597318307620160_2950233121.lin64.o │ │ │ │ │ │ ├── m_16079455487785753509_2412540121.c │ │ │ │ │ │ ├── m_16079455487785753509_2412540121.didat │ │ │ │ │ │ ├── m_16079455487785753509_2412540121.lin64.o │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ │ ├── tb_adder_subtractor_4bit_delay_isim_beh.exe_main.c │ │ │ │ │ │ └── tb_adder_subtractor_4bit_delay_isim_beh.exe_main.lin64.o │ │ │ │ ├── tb_adder_subtractor_4bit_isim_beh.exe.sim │ │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ │ ├── isimcrash.log │ │ │ │ │ ├── isimkernel.log │ │ │ │ │ ├── netId.dat │ │ │ │ │ ├── tb_adder_subtractor_4bit_isim_beh.exe │ │ │ │ │ ├── tmp_save │ │ │ │ │ │ └── _1 │ │ │ │ │ └── work │ │ │ │ │ │ ├── m_01350452300803916280_1877273954.c │ │ │ │ │ │ ├── m_01350452300803916280_1877273954.didat │ │ │ │ │ │ ├── m_01350452300803916280_1877273954.lin64.o │ │ │ │ │ │ ├── m_02223542811341278160_3890714917.c │ │ │ │ │ │ ├── m_02223542811341278160_3890714917.didat │ │ │ │ │ │ ├── m_02223542811341278160_3890714917.lin64.o │ │ │ │ │ │ ├── m_02871897007744701030_0597467428.c │ │ │ │ │ │ ├── m_02871897007744701030_0597467428.didat │ │ │ │ │ │ ├── m_02871897007744701030_0597467428.lin64.o │ │ │ │ │ │ ├── m_03707478635005068086_0014183270.c │ │ │ │ │ │ ├── m_03707478635005068086_0014183270.didat │ │ │ │ │ │ ├── m_03707478635005068086_0014183270.lin64.o │ │ │ │ │ │ ├── m_08941714888441564966_2679662850.c │ │ │ │ │ │ ├── m_08941714888441564966_2679662850.didat │ │ │ │ │ │ ├── m_08941714888441564966_2679662850.lin64.o │ │ │ │ │ │ ├── m_12245597318307620160_2950233121.c │ │ │ │ │ │ ├── m_12245597318307620160_2950233121.didat │ │ │ │ │ │ ├── m_12245597318307620160_2950233121.lin64.o │ │ │ │ │ │ ├── m_14723061407210558642_3190593924.c │ │ │ │ │ │ ├── m_14723061407210558642_3190593924.didat │ │ │ │ │ │ ├── m_14723061407210558642_3190593924.lin64.o │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ │ ├── tb_adder_subtractor_4bit_isim_beh.exe_main.c │ │ │ │ │ │ └── tb_adder_subtractor_4bit_isim_beh.exe_main.lin64.o │ │ │ │ ├── temp │ │ │ │ │ ├── add_sub.sdb │ │ │ │ │ ├── add_sub_delay.sdb │ │ │ │ │ ├── adder_subtractor_4bit.sdb │ │ │ │ │ ├── adder_subtractor_4bit_delay.sdb │ │ │ │ │ ├── full_adder.sdb │ │ │ │ │ ├── full_adder_delay.sdb │ │ │ │ │ ├── glbl.sdb │ │ │ │ │ ├── tb_adder_subtractor_4bit.sdb │ │ │ │ │ └── tb_adder_subtractor_4bit_delay.sdb │ │ │ │ └── work │ │ │ │ │ ├── add_sub_delay.sdb │ │ │ │ │ ├── adder_subtractor_4bit_delay.sdb │ │ │ │ │ ├── full_adder_delay.sdb │ │ │ │ │ ├── glbl.sdb │ │ │ │ │ └── tb_adder_subtractor_4bit_delay.sdb │ │ │ ├── tb_adder_subtractor_4bit_delay_beh.prj │ │ │ ├── tb_adder_subtractor_4bit_delay_isim_beh.exe │ │ │ ├── tb_adder_subtractor_4bit_delay_isim_beh.wdb │ │ │ ├── tb_adder_subtractor_4bit_delay_stx_beh.prj │ │ │ ├── tb_adder_subtractor_4bit_isim_beh.exe │ │ │ ├── tb_adder_subtractor_4bit_stx_beh.prj │ │ │ ├── tb_adder_subtractor_4bit_summary.html │ │ │ └── xilinxsim.ini │ │ ├── add_sub_delay.v │ │ ├── adder_subtractor_4bit.v │ │ ├── adder_subtractor_4bit_delay.v │ │ ├── full_adder.v │ │ ├── full_adder_delay.v │ │ ├── tb_adder_subtractor_4bit.v │ │ └── tb_adder_subtractor_4bit_delay.v │ ├── Lab 8 │ │ ├── ALU │ │ │ ├── ALU.gise │ │ │ ├── ALU.xise │ │ │ ├── _xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── alu_stx_beh.prj │ │ │ ├── fuse.log │ │ │ ├── fuse.xmsgs │ │ │ ├── fuseRelaunch.cmd │ │ │ ├── iseconfig │ │ │ │ ├── ALU.projectmgr │ │ │ │ └── tb_alu.xreport │ │ │ ├── isim.cmd │ │ │ ├── isim.log │ │ │ ├── isim │ │ │ │ ├── isim_usage_statistics.html │ │ │ │ ├── lockfile │ │ │ │ ├── pn_info │ │ │ │ ├── tb_alu_isim_beh.exe.sim │ │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ │ ├── isimcrash.log │ │ │ │ │ ├── isimkernel.log │ │ │ │ │ ├── netId.dat │ │ │ │ │ ├── tb_alu_isim_beh.exe │ │ │ │ │ ├── tmp_save │ │ │ │ │ │ └── _1 │ │ │ │ │ └── work │ │ │ │ │ │ ├── m_03920280463730855008_2725559894.c │ │ │ │ │ │ ├── m_03920280463730855008_2725559894.didat │ │ │ │ │ │ ├── m_03920280463730855008_2725559894.lin64.o │ │ │ │ │ │ ├── m_13803829186070922956_0637143749.c │ │ │ │ │ │ ├── m_13803829186070922956_0637143749.didat │ │ │ │ │ │ ├── m_13803829186070922956_0637143749.lin64.o │ │ │ │ │ │ ├── m_15463909857099405132_2521077532.c │ │ │ │ │ │ ├── m_15463909857099405132_2521077532.didat │ │ │ │ │ │ ├── m_15463909857099405132_2521077532.lin64.o │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ │ │ ├── tb_alu_isim_beh.exe_main.c │ │ │ │ │ │ └── tb_alu_isim_beh.exe_main.lin64.o │ │ │ │ ├── temp │ │ │ │ │ ├── alu.sdb │ │ │ │ │ ├── glbl.sdb │ │ │ │ │ ├── multiplexer4x4.sdb │ │ │ │ │ └── tb_alu.sdb │ │ │ │ └── work │ │ │ │ │ ├── alu.sdb │ │ │ │ │ ├── glbl.sdb │ │ │ │ │ ├── multiplexer4x4.sdb │ │ │ │ │ └── tb_alu.sdb │ │ │ ├── tb_alu_beh.prj │ │ │ ├── tb_alu_isim_beh.exe │ │ │ ├── tb_alu_isim_beh.wdb │ │ │ ├── tb_alu_stx_beh.prj │ │ │ ├── tb_alu_summary.html │ │ │ └── xilinxsim.ini │ │ ├── alu.v │ │ ├── multiplexer4x4.v │ │ └── tb_alu.v │ └── Lab 9 │ │ └── Sequential_Circuit │ │ ├── .lso │ │ ├── JKFF.bmm │ │ ├── JKFF.prj │ │ ├── JKFF.stx │ │ ├── JKFF.v │ │ ├── JKFF.xst │ │ ├── JKFF_summary.html │ │ ├── JKFlipFlop.prj │ │ ├── JKFlipFlop.stx │ │ ├── JKFlipFlop.xst │ │ ├── JKFlipFlop_summary.html │ │ ├── Sequential_Circuit.gise │ │ ├── Sequential_Circuit.xise │ │ ├── _xmsgs │ │ └── pn_parser.xmsgs │ │ ├── counter.prj │ │ ├── counter.stx │ │ ├── counter.v │ │ ├── counter.xst │ │ ├── counter_beh.prj │ │ ├── counter_stx_beh.prj │ │ ├── counter_summary.html │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── iseconfig │ │ ├── JKFF.xreport │ │ ├── Sequential_Circuit.projectmgr │ │ └── counter.xreport │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ ├── isim_usage_statistics.html │ │ ├── lockfile │ │ ├── pn_info │ │ ├── tb_counter_isim_beh.exe.sim │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── isimcrash.log │ │ │ ├── isimkernel.log │ │ │ ├── netId.dat │ │ │ ├── tb_counter_isim_beh.exe │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ └── work │ │ │ │ ├── m_01250171221410507948_1050165513.c │ │ │ │ ├── m_01250171221410507948_1050165513.didat │ │ │ │ ├── m_01250171221410507948_1050165513.lin64.o │ │ │ │ ├── m_02641065694070196638_1247655525.c │ │ │ │ ├── m_02641065694070196638_1247655525.didat │ │ │ │ ├── m_02641065694070196638_1247655525.lin64.o │ │ │ │ ├── m_12708656695966495901_2582214024.c │ │ │ │ ├── m_12708656695966495901_2582214024.didat │ │ │ │ ├── m_12708656695966495901_2582214024.lin64.o │ │ │ │ ├── m_16541823861846354283_2073120511.c │ │ │ │ ├── m_16541823861846354283_2073120511.didat │ │ │ │ ├── m_16541823861846354283_2073120511.lin64.o │ │ │ │ ├── tb_counter_isim_beh.exe_main.c │ │ │ │ └── tb_counter_isim_beh.exe_main.lin64.o │ │ ├── temp │ │ │ ├── @j@k@f@f.sdb │ │ │ ├── counter.sdb │ │ │ ├── glbl.sdb │ │ │ └── tb_counter.sdb │ │ └── work │ │ │ ├── @j@k@f@f.sdb │ │ │ ├── counter.sdb │ │ │ ├── glbl.sdb │ │ │ └── tb_counter.sdb │ │ ├── tb_JKFF_isim_beh.exe │ │ ├── tb_JKFF_stx_beh.prj │ │ ├── tb_JKFlipFlop.v │ │ ├── tb_JKFlipFlop_isim_beh.exe │ │ ├── tb_JKFlipFlop_stx_beh.prj │ │ ├── tb_counter.v │ │ ├── tb_counter_beh.prj │ │ ├── tb_counter_isim_beh.exe │ │ ├── tb_counter_isim_beh.wdb │ │ ├── tb_counter_new.v │ │ ├── tb_counter_new_stx_beh.prj │ │ ├── tb_counter_stx_beh.prj │ │ ├── xilinxsim.ini │ │ └── xst │ │ └── work │ │ ├── hdllib.ref │ │ ├── vlg10 │ │ └── counter.bin │ │ ├── vlg19 │ │ └── _j_k_f_f.bin │ │ └── vlg39 │ │ └── _j_k_flip_flop.bin ├── README.md ├── Slides │ ├── 01_intro.ppt │ ├── 02_binary.pptx │ ├── 02_boolean algebra.ppt │ ├── 03_verilog.ppt │ ├── 04_karnaugh.ppt │ ├── 05_delay.ppt │ ├── 06_decoder.ppt │ ├── 07_mux.ppt │ ├── 08_numbers1.ppt │ ├── 09_arithmetic1.ppt │ ├── 10_verilog.pptx │ ├── 11_numbers2.ppt │ ├── 12_arithmetic2.ppt │ ├── 13_verilog.ppt │ ├── 14_FF.ppt │ ├── 15_analysis.ppt │ ├── 16_seq design_1.ppt │ ├── 17_verilog-C.pptx │ ├── 18_seq design_2.ppt │ ├── 19_registers_counters.ppt │ └── 20_hazard.ppt ├── Template │ ├── Latex │ │ ├── cover-page.aux │ │ ├── cover-page.tex │ │ ├── fonts │ │ │ └── XB Kayhan Pook.ttf │ │ ├── images │ │ │ ├── aut-fa.png │ │ │ └── aut-fa2.png │ │ ├── info.aux │ │ ├── info.tex │ │ ├── main.aux │ │ ├── main.log │ │ ├── main.pdf │ │ ├── main.synctex.gz │ │ └── main.tex │ └── Word │ │ └── Lab_Template.docx ├── User Manual │ └── LogicLabManual.1402.pdf └── Verilog │ ├── 03_verilog.ppt │ ├── 10_verilog.ppt │ ├── 13_verilog.ppt │ ├── 17_verilog.pptx │ └── Verilog VS VHDL.ppt ├── LICENCE ├── Projects ├── 2020Fall │ ├── .gitignore │ ├── Module01 │ │ ├── AdderSubtractor32bit.v │ │ ├── Multiplier16x16.v │ │ ├── Multiplier8x8.v │ │ ├── TemperatureCalculator.v │ │ └── TemperatureCalculatorUtils.v │ ├── Module02 │ │ ├── GasDetectorSensor.v │ │ └── GasEngineUtils.v │ ├── Module03 │ │ ├── CoolHeatSystem.v │ │ ├── CoolHeatSystemUtils.v │ │ ├── FanSpeed.v │ │ └── ModePower.v │ ├── Module04 │ │ ├── ActiveLamps.v │ │ ├── LampState.v │ │ ├── LightingSystem.v │ │ ├── LightingSystemUtils.v │ │ └── WindowShadeDegree.v │ ├── Module05 │ │ ├── DFlop.v │ │ ├── LightDance.v │ │ └── LightDanceUtils.v │ ├── Module06 │ │ ├── MemoryUnit.v │ │ └── MemoryUnitUtils.v │ ├── Module07 │ │ ├── ControlUnit.v │ │ ├── ControlUnitUtils.v │ │ └── PassCheckUnit.v │ ├── ModuleSmartHomeSystem │ │ └── SmartHomeSystem.v │ └── README.md ├── 2023Fall │ ├── Logic-Project-Fall2023.pdf │ ├── README.md │ ├── Sample.pptx │ └── Testbench.pptx ├── 2023Spring │ ├── 99-1-LogicDesignFinalProject99001.pdf │ └── README.md ├── 2024Fall │ ├── Logic_Lab_final_project_fall2024-V3.pdf │ └── README.md ├── 2024Spring │ └── phase_0_1 │ │ ├── .pdf │ │ ├── Logic-Project-Spring2024.pdf │ │ └── main │ │ ├── Fonts │ │ ├── IRNazanin.ttf │ │ ├── IRNazaninBold.ttf │ │ ├── IRNazaninIrani.ttf │ │ ├── Lalezar-Regular.ttf │ │ ├── LiberationSerif-Bold.ttf │ │ ├── LiberationSerif-BoldItalic.ttf │ │ ├── LiberationSerif-Italic.ttf │ │ ├── LiberationSerif-Regular.ttf │ │ ├── XB Zar bold.ttf │ │ └── XB Zar.ttf │ │ ├── IRNazanin.ttf │ │ ├── IRNazaninBold.ttf │ │ ├── IRNazaninIrani.ttf │ │ ├── Lalezar-Regular.ttf │ │ ├── LiberationSerif-Bold.ttf │ │ ├── LiberationSerif-BoldItalic.ttf │ │ ├── LiberationSerif-Italic.ttf │ │ ├── LiberationSerif-Regular.ttf │ │ ├── Logo │ │ ├── aut-fa2.png │ │ └── ce-fa.png │ │ ├── PHASE3.aux │ │ ├── PHASE3.log │ │ ├── PHASE3.out │ │ ├── PHASE3.pdf │ │ ├── PHASE3.synctex.gz │ │ ├── PHASE3.tex │ │ ├── PHASE3.toc │ │ ├── XB Zar bold.ttf │ │ ├── XB Zar.ttf │ │ ├── images │ │ ├── Admin │ │ │ ├── admin.ipe │ │ │ └── admin.pdf │ │ ├── User │ │ │ ├── user.ipe │ │ │ ├── user.ipe.autosave.ipe │ │ │ └── user.pdf │ │ ├── admin.pdf │ │ ├── img1.png │ │ ├── img2.JPG │ │ ├── keypad.png │ │ ├── lcd.jpg │ │ └── user.pdf │ │ └── tex.bib └── 2025Spring │ └── Logic_Lab_final_project_Spring2025-(Final).pdf ├── README.md ├── Slides ├── 03_verilog.ppt ├── 09_arithmetic1.ppt ├── 10_verilog.ppt ├── 12_arithmetic2.ppt ├── 13_verilog.ppt ├── 14_FF.pptx ├── 15_analysis.pptx ├── 16_seq design1.pptx ├── 17_verilog.pptx ├── 18_seq design2.pptx ├── 19_registers_counters.pptx └── Verilog VS VHDL.ppt ├── assignment-04 ├── README.md ├── paritiy3_gen.v ├── paritiy3_gen_sop.v ├── raw │ └── xnor3.svg └── tb_paritiy3_gen.v ├── assignment-05 ├── README.md ├── decoder2x4.v ├── decoder4x16.v ├── encoder4x2.v ├── function4x1.v ├── multiplexer4x1.v ├── raw │ └── components.svg ├── tb_decoder2x4.v ├── tb_encoder4x2.v ├── tb_function4x1.v └── tb_multiplexer4x1.v ├── assignment-06 ├── README.md ├── comparator3.v ├── comparator8.v ├── raw │ └── comparator3.svg ├── tb_comparator3.v └── tb_comparator8.v ├── assignment-07 ├── README.md ├── adder_subtractor_4bit.v ├── adder_subtractor_4bit_delay.v ├── addsub.v ├── addsub_delay.v ├── full_adder.v ├── full_adder_delay.v ├── raw │ ├── addersubtractor.svg │ └── addsub.svg └── tb_adder_subtractor_4bit.v ├── assignment-08 ├── README.md ├── alu.v ├── multiplexer4x4.v ├── raw │ └── alu.png └── tb_alu.v ├── assignment-09 ├── README.md ├── dflop_negedge.v ├── raw │ ├── sequential.png │ └── sequential_wave.png ├── seq_circuit.v └── tb_seq_circuit.v ├── assignment-10 ├── README.md ├── fsm.v ├── register.v ├── system.v └── tb_system.v ├── examples └── learnfirstlogic │ ├── mylogic.ucf │ ├── mylogic.v │ └── tb_mylogic.v ├── who-had-logic-lab-ta.md └── who-know-logic-lab.md /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | /manual/LogicLabManual.pdf 3 | /tutorials/ 4 | /final-project/ 5 | a.out -------------------------------------------------------------------------------- /Fall 2023/Final_Pic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Final_Pic.png -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.bit -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.drc: -------------------------------------------------------------------------------- 1 | Release 14.7 Drc P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Nov 4 17:54:58 2023 5 | 6 | drc -z ParityGenerator.ncd ParityGenerator.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.prj: -------------------------------------------------------------------------------- 1 | verilog work "ParityGenerator.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.7 - par P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Nov 4 17:54:48 2023 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ParityGenerator(input [2:0] data, output parity); 4 | wire xnor1, xnor2, xnor3; 5 | 6 | assign xnor1 = data[0] ^ data[1]; 7 | assign xnor2 = xnor1 ^ data[2]; 8 | assign xnor3 = xnor2 ^ 1'b1; 9 | 10 | assign parity = xnor3; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/home/reza/Desktop/Implementation/xst/projnav.tmp" 2 | set -xsthdpdir "/home/reza/Desktop/Implementation/xst" 3 | elaborate 4 | -ifn ParityGenerator.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/ParityGenerator_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/reza/Desktop/Implementation/ParityGenerator.ncd 3 | OUTFILE=/home/reza/Desktop/Implementation/ParityGenerator.bit 4 | FAMILY=Spartan3 5 | PART=xc3s400-5pq208 6 | WORKINGDIR=/home/reza/Desktop/Implementation 7 | LICENSE=WebPack 8 | USER_INFO=__0_0_0 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.bit -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.drc: -------------------------------------------------------------------------------- 1 | Release 14.7 Drc P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Nov 4 18:44:05 2023 5 | 6 | drc -z SOP_ParityGenerator.ncd SOP_ParityGenerator.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.prj: -------------------------------------------------------------------------------- 1 | verilog work "SOP_ParityGenerator.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.stx -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.7 - par P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Nov 4 18:43:58 2023 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SOP_ParityGenerator(input [2:0] data, output parity); 4 | 5 | assign parity = data[0] & data[1] & ~data[2] | 6 | data[0] & ~data[1] & data[2] | 7 | ~data[0] & data[1] & data[2] | 8 | ~data[0] & ~data[1] & ~data[2]; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/SOP_ParityGenerator_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/reza/Desktop/Implementation/SOP_ParityGenerator.ncd 3 | OUTFILE=/home/reza/Desktop/Implementation/SOP_ParityGenerator.bit 4 | FAMILY=Spartan3 5 | PART=xc3s400-5pq208 6 | WORKINGDIR=/home/reza/Desktop/Implementation 7 | LICENSE=WebPack 8 | USER_INFO=__0_0_0 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | /home/reza/Desktop/Implementation/SOP_ParityGenerator.ngc 1699110494 2 | OK 3 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/planAhead_run_2/Implementation.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/planAhead_run_3/Implementation.data/runs/runs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/planAhead_run_3/Implementation.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/planAhead_run_3/Implementation.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/planAhead_run_4/Implementation.data/runs/runs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/planAhead_run_4/Implementation.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/planAhead_run_4/Implementation.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/Implementation/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO ParityGenerator NULL ParityGenerator.v vlg1C/_parity_generator.bin 1699107192 2 | MO SOP_ParityGenerator NULL SOP_ParityGenerator.v vlg65/_s_o_p___parity_generator.bin 1699110491 3 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/xst/work/vlg1C/_parity_generator.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/Implementation/xst/work/vlg1C/_parity_generator.bin -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/Implementation/xst/work/vlg65/_s_o_p___parity_generator.bin: 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parity 5 | [BiDir] 6 | [ATTRIBUTES] 7 | VeriModel ParityGenerator 8 | 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator.tfi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | // Instantiate the module 5 | ParityGenerator instance_name ( 6 | .data(data), 7 | .parity(parity) 8 | ); 9 | 10 | 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ParityGenerator(input [2:0] data, output parity); 4 | wire xnor1, xnor2, xnor3; 5 | 6 | assign xnor1 = data[0] ^ data[1]; 7 | assign xnor2 = xnor1 ^ data[2]; 8 | assign xnor3 = xnor2 ^ 1'b1; 9 | 10 | assign parity = xnor3; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/home/reza/Desktop/ParityBit/xst/projnav.tmp" 2 | set -xsthdpdir "/home/reza/Desktop/ParityBit/xst" 3 | elaborate 4 | -ifn ParityGenerator.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "/home/reza/Desktop/ParityBit/ParityGenerator_TB.xst" -ofn "/home/reza/Desktop/ParityBit/ParityGenerator_TB.syr" 2 | xst -intstyle ise -ifn "/home/reza/Desktop/ParityBit/ParityGenerator_TB.xst" -ofn "/home/reza/Desktop/ParityBit/ParityGenerator_TB.syr" 3 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB.prj: -------------------------------------------------------------------------------- 1 | verilog work "ParityGenerator.v" 2 | verilog work "ParityGenerator_TB.v" 3 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB_isim_beh1.wdb -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/ParityGenerator_TB_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "ParityGenerator.v" 2 | verilog isim_temp "ParityGenerator_TB.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/SOP_ParityGenerator.prj: -------------------------------------------------------------------------------- 1 | verilog work "SOP_ParityGenerator.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/SOP_ParityGenerator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SOP_ParityGenerator(input [2:0] data, output parity); 4 | 5 | assign parity = data[0] & data[1] & ~data[2] | 6 | data[0] & ~data[1] & data[2] | 7 | ~data[0] & data[1] & data[2] | 8 | ~data[0] & ~data[1] & ~data[2]; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/SOP_ParityGenerator.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/home/reza/Desktop/ParityBit/xst/projnav.tmp" 2 | set -xsthdpdir "/home/reza/Desktop/ParityBit/xst" 3 | elaborate 4 | -ifn SOP_ParityGenerator.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/SOP_ParityGenerator_TB_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "SOP_ParityGenerator.v" 2 | verilog work "SOP_ParityGenerator_TB.v" 3 | verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/SOP_ParityGenerator_TB_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 4/ParityBit/SOP_ParityGenerator_TB_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 4/ParityBit/SOP_ParityGenerator_TB_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 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2023/Labs/Lab 5/Decoder4x16 and function/decoder4x16.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/home/reza/Desktop/test/xst/projnav.tmp" 2 | set -xsthdpdir "/home/reza/Desktop/test/xst" 3 | elaborate 4 | -ifn decoder4x16.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/Decoder4x16 and function/function_with_dec4x16.prj: -------------------------------------------------------------------------------- 1 | verilog work "decoder2x4.v" 2 | verilog work "decoder4x16.v" 3 | verilog work "function_with_dec4x16.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/Decoder4x16 and function/function_with_dec4x16.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/home/reza/Desktop/test/xst/projnav.tmp" 2 | set -xsthdpdir "/home/reza/Desktop/test/xst" 3 | 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All rights reserved. 3 | 4 | Sat Nov 11 17:35:15 2023 5 | 6 | drc -z decoder2x4.ncd decoder2x4.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4.prj: -------------------------------------------------------------------------------- 1 | verilog work "decoder2x4.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/decoder2x4.stx -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4.ucf: -------------------------------------------------------------------------------- 1 | NET "sel[1]" LOC = P182; 2 | NET "sel[0]" LOC = P183; 3 | NET "w_in[0]" LOC = P171; 4 | NET "w_in[1]" LOC = P169; 5 | NET "w_in[2]" LOC = P168; 6 | NET "w_in[3]" LOC = P167; 7 | NET "y" LOC = P42; 8 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.7 - par P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Nov 11 17:35:10 2023 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module decoder2x4( output [3:0] D, 4 | input [1:0] I, 5 | input en); 6 | 7 | //wire I_not[1:0]; 8 | //not n1(I_not[0], I[0]); 9 | //not n2(I_not[1], in[1]); 10 | 11 | // output b a 12 | and D0( D[0], ~en, ~I[1], ~I[0] ); 13 | and D1( D[2], ~en, I[1], ~I[0] ); 14 | and D2( D[1], ~en, ~I[1], I[0] ); 15 | and D3( D[3], ~en, I[1], I[0] ); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5/decoder2x4.ncd 3 | OUTFILE=/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5/decoder2x4.bit 4 | FAMILY=Spartan3 5 | PART=xc3s400-5pq208 6 | WORKINGDIR=/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5 7 | LICENSE=WebPack 8 | USER_INFO=__0_0_0 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/decoder2x4_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder2x4_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "decoder2x4.v" 2 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 3 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder4x16.prj: -------------------------------------------------------------------------------- 1 | verilog work "decoder2x4.v" 2 | verilog work "decoder4x16.v" 3 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder4x16.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5/xst/projnav.tmp" 2 | set -xsthdpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5/xst" 3 | elaborate 4 | -ifn decoder4x16.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder4x16_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/decoder4x16_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/decoder4x16_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "decoder2x4.v" 2 | verilog isim_temp "Decoder4x16 and function/decoder4x16.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/function_with_dec4x16.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/function_with_dec4x16.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map P.20131013 on Fri Nov 10 20:01:11 2023 3 | //! ************************************************************************** 4 | 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/function_with_dec4x16.prj: -------------------------------------------------------------------------------- 1 | verilog work "decoder2x4.v" 2 | verilog work "decoder4x16.v" 3 | verilog work "function_with_dec4x16.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/function_with_dec4x16.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/function_with_dec4x16.stx -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/function_with_dec4x16.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.7 - par P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Fri Nov 10 20:01:14 2023 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/function_with_dec4x16_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "decoder2x4.v" 2 | verilog work "decoder4x16.v" 3 | verilog work "Decoder4x16 and function/function_with_dec4x16.v" 4 | verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib 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All rights reserved. 3 | 4 | Sat Nov 11 17:57:31 2023 5 | 6 | drc -z mux4x1.ncd mux4x1.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1.prj: -------------------------------------------------------------------------------- 1 | verilog work "mux4x1.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/mux4x1.stx -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1.ucf: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Generated physical constraints 3 | 4 | NET "y" LOC = P42; 5 | NET "w_in[0]" LOC = P171; 6 | NET "w_in[1]" LOC = P169; 7 | NET "w_in[2]" LOC = P168; 8 | NET "w_in[3]" LOC = P167; 9 | NET "sel[1]" LOC = P182; 10 | NET "sel[0]" LOC = P183; 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.7 - par P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Nov 11 17:57:28 2023 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module mux4x1( output y, 5 | input [3:0] w_in, 6 | input [1:0] sel ); 7 | 8 | 9 | wire [3:0] a; 10 | 11 | and a0(a[0], w_in[0], ~sel[0], ~sel[1]); 12 | and a1(a[1], w_in[1], sel[0], ~sel[1]); 13 | and a2(a[2], w_in[2], ~sel[0], sel[1]); 14 | and a3(a[3], w_in[3], sel[0], sel[1]); 15 | 16 | or out(y, a[0], a[1], a[2], a[3]); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/mux4x1_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5/mux4x1.ncd 3 | OUTFILE=/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5/mux4x1.bit 4 | FAMILY=Spartan3 5 | PART=xc3s400-5pq208 6 | WORKINGDIR=/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab5 7 | LICENSE=WebPack 8 | USER_INFO=__0_0_0 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map P.20131013 on Sat Nov 11 18:08:38 2023 3 | //! ************************************************************************** 4 | 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.prj: -------------------------------------------------------------------------------- 1 | verilog work "pEncoder4x2.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/pEncoder4x2.stx -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/pEncoder4x2.ucf -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.7 - par P.20131013 (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Nov 11 18:08:42 2023 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module pEncoder4x2( output [1:0] Q_out, 4 | output v, 5 | input [3:0] D_in ); 6 | 7 | 8 | wire x; 9 | 10 | and a(x, ~D_in[2], D_in[1]); 11 | or b(Q_out[0], x, D_in[3]); 12 | 13 | or c(Q_out[1], D_in[2], D_in[3]); 14 | 15 | or d(v, D_in[0], D_in[1], Q_out[1]); 16 | 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/pEncoder4x2.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 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70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:32:00:00 3 | eof:1506592605 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_1/Lab5.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_2/Lab5.data/constrs_1/designprops.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_2/Lab5.data/constrs_1/usercols.xml: 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1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_3/Lab5.data/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00 3 | eof:3611541694 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_3/Lab5.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_4/Lab5.data/constrs_1/designprops.xml: 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5/planAhead_run_4/Lab5.data/sources_1/chipscope.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_4/Lab5.data/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00 3 | eof:3611541694 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_4/Lab5.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_5/Lab5.data/constrs_1/designprops.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_5/Lab5.data/constrs_1/usercols.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_5/Lab5.data/runs/runs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_5/Lab5.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_5/Lab5.data/sources_1/chipscope.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_5/Lab5.data/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00 3 | eof:3611541694 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/planAhead_run_5/Lab5.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_decoder2x4_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/tb_decoder2x4_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_decoder2x4_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "decoder2x4.v" 2 | verilog isim_temp "tb_decoder2x4.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_decoder4x16_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/tb_decoder4x16_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_decoder4x16_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/tb_decoder4x16_isim_beh1.wdb -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_function_with_dec4x16_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "decoder2x4.v" 2 | verilog work "decoder4x16.v" 3 | verilog work "function_with_dec4x16.v" 4 | verilog work "Decoder4x16 and function/tb_function_with_dec4x16.v" 5 | verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_function_with_dec4x16_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/tb_function_with_dec4x16_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_function_with_dec4x16_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/tb_function_with_dec4x16_isim_beh.wdb -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_function_with_dec4x16_isim_beh2.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/tb_function_with_dec4x16_isim_beh2.wdb -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_mux4x1_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/tb_mux4x1_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_mux4x1_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "mux4x1.v" 2 | verilog isim_temp "tb_mux4x1.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_pEncoder4x2_isim_beh.exe: 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-------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/tb_pEncoder4x2_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "pEncoder4x2.v" 2 | verilog isim_temp "tb_pEncoder4x2.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO pEncoder4x2 NULL pEncoder4x2.v vlg36/p_encoder4x2.bin 1699713539 2 | MO decoder2x4 NULL decoder2x4.v vlg68/decoder2x4.bin 1699715433 3 | MO function_with_dec4x16 NULL function_with_dec4x16.v vlg5B/function__with__dec4x16.bin 1699633864 4 | MO decoder4x16 NULL decoder4x16.v vlg29/decoder4x16.bin 1699633864 5 | MO mux4x1 NULL mux4x1.v vlg6B/mux4x1.bin 1699712501 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/xst/work/vlg36/p_encoder4x2.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/xst/work/vlg36/p_encoder4x2.bin -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/xst/work/vlg5B/function__with__dec4x16.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/xst/work/vlg5B/function__with__dec4x16.bin -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/xst/work/vlg68/decoder2x4.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/xst/work/vlg68/decoder2x4.bin -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 5/xst/work/vlg6B/mux4x1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 5/xst/work/vlg6B/mux4x1.bin -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/ThreeBitComparator.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/ThreeBitComparator.xst" -ofn "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/ThreeBitComparator.syr" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/ThreeBitComparator.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/ThreeBitComparator.prj: -------------------------------------------------------------------------------- 1 | verilog work "comp3.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/ThreeBitComparator.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/xst/projnav.tmp" 2 | set -xsthdpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/xst" 3 | elaborate 4 | -ifn ThreeBitComparator.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/comp3.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/comp3.xst" -ofn "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/comp3.syr" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/comp3.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/comp3.prj: -------------------------------------------------------------------------------- 1 | verilog work "comp3.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/comp3.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/xst/projnav.tmp" 2 | set -xsthdpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/xst" 3 | elaborate 4 | -ifn comp3.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/comparator3.prj: -------------------------------------------------------------------------------- 1 | verilog work "comp3.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/comparator3.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/xst/projnav.tmp" 2 | set -xsthdpdir "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/xst" 3 | elaborate 4 | -ifn comparator3.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/tb_comp3_isim_beh.exe" -prj "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 6/comparator/tb_comp3_beh.prj" "work.tb_comp3" "work.glbl" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/isim/lockfile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 6/comparator/isim/lockfile -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/isim/tb_comp3_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 6/comparator/isim/tb_comp3_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/isim/tb_comp3_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 6/comparator/isim/tb_comp3_isim_beh.exe.sim/isimcrash.log -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/isim/tb_comp3_isim_beh.exe.sim/netId.dat: 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https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 6/comparator/tb_comp3_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/tb_comp3_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 6/comparator/tb_comp3_isim_beh.wdb -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/tb_comp3_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "comp3.v" 2 | verilog isim_temp "tb_comp3.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | isim_temp=isim/temp 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO ThreeBitComparator NULL comp3.v vlg33/_three_bit_comparator.bin 1700400612 2 | MO comparator3 NULL comp3.v vlg4F/comparator3.bin 1700404266 3 | MO comp3 NULL comp3.v vlg6E/comp3.bin 1700404373 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 6/comparator/xst/work/vlg33/_three_bit_comparator.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 6/comparator/xst/work/vlg33/_three_bit_comparator.bin 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module add_sub ( 4 | input a , 5 | input b , 6 | input cin , 7 | input sel , 8 | output sum , 9 | output cout 10 | ); 11 | wire new_b; 12 | assign new_b = b ^ sel; 13 | full_adder FA(a, new_b, cin, sum, cout); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 7/add_sub/tb_adder_subtractor_4bit_delay_isim_beh.exe" -prj "/media/reza/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 7/add_sub/tb_adder_subtractor_4bit_delay_beh.prj" "work.tb_adder_subtractor_4bit_delay" "work.glbl" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/isim/lockfile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 7/add_sub/isim/lockfile -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | 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7/add_sub/isim/work/tb_adder_subtractor_4bit_delay.sdb -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/tb_adder_subtractor_4bit_delay_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "../full_adder_delay.v" 2 | verilog work "../add_sub_delay.v" 3 | verilog work "../adder_subtractor_4bit_delay.v" 4 | verilog work "../tb_adder_subtractor_4bit_delay.v" 5 | verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/tb_adder_subtractor_4bit_delay_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 7/add_sub/tb_adder_subtractor_4bit_delay_isim_beh.exe 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"/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 9 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/add_sub_delay.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/1 ns 2 | 3 | module add_sub_delay ( 4 | input a , 5 | input b , 6 | input cin , 7 | input sel , 8 | output sum , 9 | output cout 10 | ); 11 | 12 | wire xor_out_1; 13 | xor #10 xor_1(xor_out_1, b, sel); 14 | full_adder_delay FAD(a, xor_out_1, cin, sum, cout); 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 7/full_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/1 ns 2 | 3 | module full_adder ( 4 | input a , 5 | input b , 6 | input ci , 7 | output s , 8 | output co 9 | ); 10 | 11 | assign s = a ^ b ^ ci; 12 | assign co = (a & b) | (ci & (a | b)); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 8/ALU/alu_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "../multiplexer4x4.v" 2 | verilog isim_temp "../alu.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 8/ALU/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 8/ALU/fuseRelaunch.cmd: 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https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 8/ALU/tb_alu_isim_beh.exe -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 8/ALU/tb_alu_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 8/ALU/tb_alu_isim_beh.wdb -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 8/ALU/tb_alu_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "../multiplexer4x4.v" 2 | verilog isim_temp "../alu.v" 3 | verilog isim_temp "../tb_alu.v" 4 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 5 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 8/ALU/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 8/multiplexer4x4.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/1 ns 2 | 3 | module multiplexer4x4 ( 4 | input [3:0] w3 , 5 | input [3:0] w2 , 6 | input [3:0] w1 , 7 | input [3:0] w0 , 8 | input [1:0] sel , 9 | output [3:0] y ); 10 | 11 | reg [3:0] y_1; 12 | always @(sel, w0, w1, w2, w3) 13 | case(sel) 14 | 2'b00: y_1 = w0; 15 | 2'b01: y_1 = w1; 16 | 2'b10: y_1 = w2; 17 | 2'b11: y_1 = w3; 18 | endcase 19 | assign y = y_1; 20 | endmodule 21 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/JKFF.bmm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 9/Sequential_Circuit/JKFF.bmm -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/JKFF.prj: -------------------------------------------------------------------------------- 1 | verilog work "JKFF.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/JKFF.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/xst/projnav.tmp" 2 | set -xsthdpdir "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/xst" 3 | elaborate 4 | -ifn JKFF.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/JKFlipFlop.prj: -------------------------------------------------------------------------------- 1 | verilog work "JKFF.v" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/JKFlipFlop.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/xst/projnav.tmp" 2 | set -xsthdpdir "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/xst" 3 | elaborate 4 | -ifn JKFlipFlop.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/counter.prj: -------------------------------------------------------------------------------- 1 | verilog work "JKFF.v" 2 | verilog work "counter.v" 3 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/counter.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/xst/projnav.tmp" 2 | set -xsthdpdir "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/xst" 3 | elaborate 4 | -ifn counter.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/counter_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "JKFF.v" 2 | verilog work "counter.v" 3 | verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/counter_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "JKFF.v" 2 | verilog isim_temp "counter.v" 3 | verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/tb_counter_isim_beh.exe" -prj "/mnt/9636D17436D15639/University/Ta/Logic Circuit Lab/Fall 2023/Labs/Lab 9/Sequential_Circuit/tb_counter_beh.prj" "work.tb_counter" "work.glbl" 2 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/isim/lockfile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aut-ce/CE202-LC-Lab-Manual/563defea6e27dadb80d9442f6e2d07b5bcadbb69/Fall 2023/Labs/Lab 9/Sequential_Circuit/isim/lockfile -------------------------------------------------------------------------------- /Fall 2023/Labs/Lab 9/Sequential_Circuit/isim/pn_info: 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| ### Submission Sources 18 | * Source files (Grading Sources) 19 | * Waveform of testbeches that covers all signals in `testbench.png` diagram 20 | -------------------------------------------------------------------------------- /examples/learnfirstlogic/mylogic.ucf: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Generated physical constraints 3 | NET "A" LOC = W13; 4 | NET "B" LOC = P15; 5 | NET "C" LOC = G15; 6 | NET "x" LOC = M14; 7 | NET "y" LOC = M15; 8 | # PlanAhead Generated IO constraints 9 | 10 | NET "A" IOSTANDARD = LVCMOS33; 11 | NET "B" IOSTANDARD = LVCMOS33; 12 | NET "C" IOSTANDARD = LVCMOS33; 13 | NET "x" IOSTANDARD = LVCMOS33; 14 | NET "y" IOSTANDARD = LVCMOS33; 15 | -------------------------------------------------------------------------------- /examples/learnfirstlogic/mylogic.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | 5 | 6 | module mylogic( 7 | input A, 8 | input B, 9 | input C, 10 | output x, 11 | output y 12 | ); 13 | wire e; 14 | 15 | and g1(e,A,B); 16 | not g2(y, C); 17 | or g3(x,e,y); 18 | 19 | endmodule 20 | --------------------------------------------------------------------------------