├── README.md ├── doc ├── Assembly.md ├── BIOS.md ├── BOM.md ├── Compiling.md ├── FPGA_CPU_interface.md ├── Issues.md ├── PCB.md ├── README.md └── USB.md ├── fpga_pin_test ├── README.md ├── top.qpf ├── top.qsf ├── top.v ├── uart.v └── vdu.v ├── pcb ├── Gerber.zip ├── ep4f23_286_r2.lay6 ├── ep4f23_286_r2_2.lay6 ├── ep4f23_286_v2.pcb └── ep4f23_286_v2_m1.pcb ├── pictures ├── 1.png ├── 2.png ├── 3.png ├── 4.png ├── board.jpg ├── bottom.gif ├── cpu.png ├── pcad.jpg ├── sch1.png ├── top.gif ├── usb_nak.png └── usb_osc.jpg ├── sch └── README.md └── src ├── BIOS.qip ├── BIOS.v ├── BIOS_bb.v ├── Font.qip ├── Font.v ├── Font_bb.v ├── Main.qsf ├── Main.qws ├── Main.v ├── Main86.qsf ├── PIC.v ├── PIT.v ├── PLL1.ppf ├── PLL1.qip ├── PLL1.v ├── PLL1_bb.v ├── PLLJ_PLLSPE_INFO.txt ├── PS2.v ├── Palette.qip ├── Palette.v ├── Palette_bb.v ├── SDRAM.v ├── SPI.v ├── SRAM.v ├── UART_tx.v ├── USB_LS_HID.v ├── USB_LS_PHY.v ├── VGA.v ├── VGARegs.qip ├── VGARegs.v ├── VGARegs_bb.v ├── ep4r86.qpf ├── keyboard.mif ├── keyboard.qip ├── keyboard.v ├── keyboard_bb.v └── vgafont.mif /README.md: -------------------------------------------------------------------------------- 1 | # fpga286r2 2 | 80286 Retro computer board with FPGA 3 | 4 | ### Tested software 5 | * MSDOS 3.3 / 4.0 / 6.22 6 | * Windows 2.0 in CGA mode 7 | 8 | ### Some tested games 9 | * Some old CGA games 10 | * Prince of Persia (CGA and VGA mode) 11 | 12 | ## New USB host controller is almost done! 13 | 14 | Currently only keyboards are supported, only 1 button press at a time is possible. 15 | This is enough for work with some apps, but not enough for games. 16 | 17 | I tried to keep the design as simple as possible - only 2 files (about 300 lines each) with 2 FSMs, total about 420 LEs. 18 | These FSMs make it easy to add new USB commands or to work with additional device's endpoints. 19 | 20 | To test it: 21 | * Connect your keyboard to an upper USB (only low-speed and no hubs/radio, sorry!). 22 | * Start the DOS or 16-bit Minix and try some commands like "cd" or "dir" ("ls"). 23 | * Connect headphones to audio jack. 24 | * Every time you push buttons on a keyboard you'll hear bleeps - thus the controller 25 | lets you know that a device's report has been received. Each key will have unique sound frequency which depends on a key's scancode. 26 | 27 | "ACK" response on "GET DESCRIPTOR" command: 28 | 29 | ![top](pictures/usb_osc.jpg) 30 | 31 | "NAK" response: 32 | 33 | ![top](pictures/usb_nak.png) 34 | 35 | ## BIOS 36 | Please use this compact BIOS: 37 | 38 | https://github.com/b-dmitry1/BIOS 39 | 40 | ## PCB 41 | P-CAD 2006, Sprint Layout 6, and prepared for manufacturing Gerber files could be found in a "pcb" directory. 42 | 43 | Technology: 44 | * 4-layer PCB. 45 | * 100x100 mm size. 46 | * 0.2 mm min hole. 47 | * 0.46 mm min via diameter. 48 | * 0.127 mm min track. 49 | 50 | It is safe to increase hole size to 0.3 mm, via to 0.63mm, and track width to 0.15 mm. 51 | 52 | All the electronic components including FPGA (EP4CE15F23C8N) and CPU (80c286) could be found on AliExpress. 53 | 54 | FPGA pin test is included. Check the fpga_pin_test project. 55 | 56 | ![top](pictures/board.jpg) 57 | 58 | Top view: 59 | 60 | ![top](pictures/top.gif) 61 | 62 | Bottom view: 63 | 64 | ![bottom](pictures/bottom.gif) 65 | 66 | Simplified schematic diagram: 67 | 68 | ![top](pictures/sch1.png) 69 | 70 | ## Compiling on Windows 71 | 72 | Please use Altera Quartus II 13.0sp1 to compile the project. 73 | 74 | ## Using disk images 75 | Please use disk images from my e86r project: 76 | 77 | https://github.com/b-dmitry1/e86r 78 | 79 | Just write a FreeDos or an empty image to a SD card, mount it and add your files using File Explorer. 80 | 81 | ## Docs and manuals 82 | 83 | * Electrical schematic diagram is in "sch" directory. 84 | * Please check the "doc" directory. 85 | 86 | ## Disclaimer 87 | The project is provided "as is" without any warranty. Use at your own risk. 88 | -------------------------------------------------------------------------------- /doc/Assembly.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/doc/Assembly.md -------------------------------------------------------------------------------- /doc/BIOS.md: -------------------------------------------------------------------------------- 1 | # BIOS 2 | Please use this compact BIOS: 3 | 4 | https://github.com/b-dmitry1/BIOS 5 | 6 | -------------------------------------------------------------------------------- /doc/BOM.md: -------------------------------------------------------------------------------- 1 | # BOM 2 | 3 | * 1 x Altera EP4CE15F23C8N 4 | * 1 x 80286 CPU (PLCC-68) 12+ MHz 5 | * 1 x PLCC-68 socket 6 | * 1 x VGA 15 pin connector 7 | * 1 x USB double-port connector 8 | * 1 x SD-CARD connector 9 | * 1 x AUDIO 3.5 mm 10 | * 1 x POWER 2EDG-5.08 connector 11 | * 2 x buttons (90 degree) 12 | * 1 x IDC FC-10 connector 13 | * 1 x IDC FC-34 connector if you need floppy drive interface 14 | * 1 x 50 MHz 4 pin active crystal oscillator 15 | * 1 x W9825G6JH-6 or compatible 32-megabyte SDRAM 16 | * 1 x IS61LV25616AL-8 or compatible 512-kilobyte SRAM 17 | * 1 x W25Q64FVSIQ SOIC-8 Serial EEPROM or compatible 18 | * 1 x AMS1117-3.3 19 | * 1 x AMS1117-2.5 20 | * 1 x AMS1117-1.2 21 | * 3 x LEDs 3 mm 22 | * 16 x IP4220CZ6 or compatible 23 | * 1 x 74HC04 or 74HC14 24 | * 1 x 100 uF 10 V capacitor 25 | * 6 x 10 uF 10 V capacitor 26 | * 1 x 0.5 A recoverable fuse 27 | * 1 x bucket of 0.1 uF 0603 high-quality ceramic capacitors 28 | * 6 x 0.1 uF 1206 capacitors 29 | * 1 x 0.01 uF 0603 capacitor 30 | * 62 x 1K 0603 resistors 31 | * 9 x 10K 0603 resistors 32 | * 8 x 47R 1206 resistors 33 | * 2 x 150R 1206 resistors 34 | * 4 x 510R 0603 resistors 35 | * 3 x 2K 0603 resistors 36 | * 4 x 33R 0603 resistors 37 | * 4 x 15K 0603 resistors 38 | * 3 x 470R 1206 resistors 39 | * 2 x 300R 0603 resistors 40 | 41 | Some component's values can be safely changed if you want to. For example, you can use 33R instead of 47R, and 470R instead of 300R resistors to minimize BOM. 42 | 43 | Before ordering the PCB please measure all the sockets and connectors you plan to use here and edit the PCB's design file! 44 | 45 | Please note that some 286 CPUs like old Intel, AMD, and Siemens requires additional 0.047 uF 12 V ceramic capacitor to be connected between pin 52 and GND. 46 | If you have such CPU don't forget to add this one! 47 | -------------------------------------------------------------------------------- /doc/Compiling.md: -------------------------------------------------------------------------------- 1 | # Compiling on Windows 2 | 3 | Please use Altera Quartus II 13.0sp1 to compile the project. 4 | 5 | Just clone this repo, go to "src" directory, open the project file, compile and program it. 6 | 7 | -------------------------------------------------------------------------------- /doc/FPGA_CPU_interface.md: -------------------------------------------------------------------------------- 1 | # The FPGA - CPU interface 2 | 3 | 80286 CPU have 5 main transaction types: Memory Read, Memory Write, I/O Read, I/O Write, and an Interrupt Acknowledge. 4 | Each cycle is identified by combination of signals S0, S1, M/IO, COD/INTA appearing on the CPU's buses. 5 | 6 | When S0 and/or S1 goes low it is safe to fetch address and transaction type. 7 | 8 | ### Memory read 9 | 10 | Appearing when the CPU is requesting code or reading memory. Identified by S0 = 1, S1 = 0, M/IO = 1. 11 | 12 | We need to redirect a "read" command to RAM controller or ROM BIOS. When done, we'll send the result to the CPU's data bus. 13 | 14 | ### Memory write 15 | 16 | Appearing when the CPU is writing to a memory. Identified by S0 = 0, S1 = 1, M/IO = 1. 17 | 18 | We need to wait until S0 goes high and redirect a value from the CPU's data bus and a "write" command to RAM controller. 19 | 20 | ### I/O read 21 | 22 | Appearing when the CPU is reading data from an external device. Identified by S0 = 1, S1 = 0, M/IO = 0. 23 | 24 | We need to redirect a "read" command to a selected device. When done, we'll send the result to the CPU's data bus. 25 | 26 | If the CPU is trying to read from a non-existing device it is better to return all one's like an original PC does. 27 | 28 | ### I/O write 29 | 30 | Appearing when the CPU is writing to an external device. Identified by S0 = 0, S1 = 1, M/IO = 0. 31 | 32 | We need to wait until S0 goes high and redirect a value from the CPU's data bus and a "write" command to a selected device. 33 | 34 | ### Interrupt Acknowledge 35 | 36 | Appearing when the CPU acknowledges an interrupt. Identified by S0 = 0, S1 = 0, M/IO = 0, COD/INTA = 0. 37 | 38 | We need to ask an interrupt controller what interrupt number is requested and send it to the CPU's data bus. 39 | 40 | The CPU (for some reason) is performing this cycle twice. Ok, we'll repeat the number one more time. 41 | 42 | ### Ready signal 43 | 44 | Some devices like SDRAM or SPI bus controller are working much slower than the CPU so we need to "extend" read/write cycles. 45 | 46 | If the requested device cannot execute command immediately - it indicates "not ready" state by pulling CPU's "ready" signal to an inactive state. 47 | The CPU can wait for the tranaction to end indefinitely. The "ready" signal should be synchronized to the CPU's clock. 48 | 49 | A small program in the "Main.v" file performs all this actions. 50 | 51 | ### System reset 52 | 53 | On power-up or by user's request (push the button) the CPU's reset procedure is performed. 54 | The CPU will do it's own initialization routines for about 50 clock cycles, and we should keep the clock running for this period. 55 | 56 | After that, the CPU will fill its instruction queue by performing 4 x 16 bit reads from address 0xFFFFF0. This address is a mirror for 0x0FFFF0 where the system BIOS lives. 57 | A very first command usually located in this address in the BIOS is a long jump to a BIOS's entry point, but you can place there any command you want - the CPU will execute it in an usual way. 58 | -------------------------------------------------------------------------------- /doc/Issues.md: -------------------------------------------------------------------------------- 1 | # Known issues 2 | * USB support is in progress. Working USB module could be found in my "V188" project. 3 | * No return from protected mode due to absence of 70h port emulation. 4 | * VGA virtual resolution (panning) calculation may be wrong for some games. 5 | * VGA palette errors 6 | 7 | -------------------------------------------------------------------------------- /doc/PCB.md: -------------------------------------------------------------------------------- 1 | # PCB 2 | P-CAD 2006, Sprint Layout 6, and prepared for manufacturing Gerber files could be found in a "pcb" directory. 3 | 4 | The board was designed to support 3 different CPUs: 5 | * Zilog Z80 6 | * 8086 7 | * 80286 8 | 9 | The CPUs are not pin-compatible so there are some jumpers near to the CPU that routing power/signals: 10 | * Jumpers marked by "Z" should be shorted if the CPU is Z80. 11 | * Jumpers marked by "0" should be shorted if the CPU is 8086. 12 | * Not marked jumpers should be shorted if the CPU is Z80 and there is no "Z" jumper on an opposite side (for 3-position jumpers). 13 | * Not marked jumpers should be shorted if the CPU is 8086 and there is no "0" jumper on an opposite side (for 3-position jumpers). 14 | * Not marked jumpers should be shorted if the CPU is 80286. 15 | 16 | ### Technology 17 | * 4-layer PCB. 18 | * 100x100 mm size. 19 | * 0.2 mm min hole. 20 | * 0.46 mm min via diameter. 21 | * 0.127 mm min track. 22 | 23 | I have paid only $7 for 5 PCBs on jlcpcb.com. 24 | It is safe to increase hole size to 0.3 mm, via to 0.63mm, and track width to 0.15 mm. 25 | 26 | All the electronic components including FPGA (EP4CE15F23C8N) and CPU (80c286) could be found on AliExpress. 27 | 28 | ![top](../pictures/board.jpg) 29 | 30 | Top view: 31 | 32 | ![top](../pictures/top.jpg) 33 | 34 | Bottom view: 35 | 36 | ![bottom](../pictures/bottom.jpg) 37 | 38 | Please note that the PCB should be slightly corrected to make it work with a 286 CPU. 39 | There are 2 modifications: 40 | * 1 track should be cut at the location indicated by the yellow cross. 41 | * 1 wire should be added as shown in yellow. 42 | 43 | If you want to use Z80 or 8086 CPU please re-route tracks on DIP40 pins 27 and 28. They are connected there by mistake. 44 | The FPGA-CPU bridge located in the "Main.v" file also should be changed to provide support of this CPUs. 45 | They are incompatible so is not interchangeable! 46 | 47 | ![pcad](../pictures/pcad.jpg) 48 | -------------------------------------------------------------------------------- /doc/README.md: -------------------------------------------------------------------------------- 1 | # Documentation 2 | 3 | Please select the documentation file you need. 4 | 5 | -------------------------------------------------------------------------------- /doc/USB.md: -------------------------------------------------------------------------------- 1 | # USB host 2 | 3 | * Fully automatic LS USB host controller. 4 | * Configurable delays. 5 | * Automatic ACK on DATA0 and DATA1. 6 | * Automatic reset and re-init on STALL and on connection loss. 7 | * Automatic HID device initialization. 8 | * Automatic periodic report requests. 9 | 10 | If you want to use it in your project: 11 | * Copy USB_LS_PHY.v and USB_LS_HID.v files. 12 | * Provide 50 MHz clock and reset (active 0) signals. 13 | * Connect USB d-/d+ signals. 14 | * Add your code to USB_LS_HID.v to parse your device's reports the way you need it. 15 | -------------------------------------------------------------------------------- /fpga_pin_test/README.md: -------------------------------------------------------------------------------- 1 | # fpga286r2 pin test 2 | 3 | This test is designed to check the quality of FPGA pins connection. 4 | 5 | Test procedure: 6 | * After soldering the board do not install the CPU and do not connect SD-card, USB and a floppy drive. 7 | * Powerup the board, write this test program to FPGA, then use a LED with a series 1 KOhm resistor connected to +3.3V to test all the interfaces. 8 | * Touch CPU, SRAM, SDRAM, USB, SD-card, Expansion and floppy drive interface pins. The LED should blink on all the output and bidirectional pins. Use precautions to avoid damaging the device with electrostatic discharge. 9 | * Test the VGA interface: you will see a moving RGB stripes (4096 different colors). 10 | * Test 3.5 mm audio connector with headphones: you'll hear a loud beeps. 11 | * Test the UART: connect USB type-A cable, open a Terminal program, set the port to 115200 baud rate, 8 data bits, 1 stop bit, no parity, no flow control. You will see a "Test" text message. 12 | -------------------------------------------------------------------------------- /fpga_pin_test/top.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 12:44:23 January 13, 2024 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "12:44:23 January 13, 2024" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "top" 31 | -------------------------------------------------------------------------------- /fpga_pin_test/top.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 00:12:21 January 02, 2023 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Main_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV E" 40 | set_global_assignment -name DEVICE EP4CE15F23C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY top 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:12:21 JANUARY 02, 2023" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 49 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 50 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 51 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 52 | set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V 53 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 54 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 55 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 56 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 57 | 58 | set_location_assignment PIN_G1 -to clk 59 | set_location_assignment PIN_T1 -to reset_n 60 | 61 | set_location_assignment PIN_B3 -to vga_vsync 62 | set_location_assignment PIN_A3 -to vga_hsync 63 | set_location_assignment PIN_B4 -to vga_r[4] 64 | set_location_assignment PIN_A4 -to vga_r[5] 65 | set_location_assignment PIN_B5 -to vga_r[6] 66 | set_location_assignment PIN_A5 -to vga_r[7] 67 | set_location_assignment PIN_B6 -to vga_g[4] 68 | set_location_assignment PIN_A6 -to vga_g[5] 69 | set_location_assignment PIN_B7 -to vga_g[6] 70 | set_location_assignment PIN_A7 -to vga_g[7] 71 | set_location_assignment PIN_B8 -to vga_b[4] 72 | set_location_assignment PIN_A8 -to vga_b[5] 73 | set_location_assignment PIN_B9 -to vga_b[6] 74 | set_location_assignment PIN_A9 -to vga_b[7] 75 | 76 | set_location_assignment PIN_B10 -to usb1_p 77 | set_location_assignment PIN_A10 -to usb1_m 78 | set_location_assignment PIN_E11 -to usb2_p 79 | set_location_assignment PIN_A13 -to usb2_m 80 | 81 | set_location_assignment PIN_B13 -to sd_cs_n 82 | set_location_assignment PIN_A14 -to sd_mosi 83 | set_location_assignment PIN_B14 -to sd_sck 84 | set_location_assignment PIN_A15 -to sd_miso 85 | 86 | set_location_assignment PIN_B15 -to audio_left 87 | set_location_assignment PIN_A16 -to audio_right 88 | 89 | set_location_assignment PIN_AB20 -to cpu_d[0] 90 | set_location_assignment PIN_M19 -to cpu_d[1] 91 | set_location_assignment PIN_P22 -to cpu_d[2] 92 | set_location_assignment PIN_M20 -to cpu_d[3] 93 | set_location_assignment PIN_J22 -to cpu_d[4] 94 | set_location_assignment PIN_F22 -to cpu_d[5] 95 | set_location_assignment PIN_F20 -to cpu_d[6] 96 | set_location_assignment PIN_D21 -to cpu_d[7] 97 | set_location_assignment PIN_AA18 -to cpu_d[8] 98 | set_location_assignment PIN_K18 -to cpu_d[9] 99 | set_location_assignment PIN_B16 -to cpu_d[10] 100 | set_location_assignment PIN_A17 -to cpu_d[11] 101 | set_location_assignment PIN_B17 -to cpu_d[12] 102 | set_location_assignment PIN_B18 -to cpu_d[13] 103 | set_location_assignment PIN_A19 -to cpu_d[14] 104 | set_location_assignment PIN_A18 -to cpu_d[15] 105 | set_location_assignment PIN_B19 -to cpu_intr 106 | set_location_assignment PIN_B20 -to cpu_clk_n 107 | set_location_assignment PIN_C17 -to cpu_nmi_n 108 | set_location_assignment PIN_B21 -to cpu_bhe_n 109 | set_location_assignment PIN_B22 -to cpu_error_n 110 | set_location_assignment PIN_C20 -to cpu_ready 111 | set_location_assignment PIN_C21 -to cpu_inta_n 112 | set_location_assignment PIN_C22 -to cpu_mio 113 | set_location_assignment PIN_D22 -to cpu_hold 114 | set_location_assignment PIN_E21 -to cpu_hlda 115 | set_location_assignment PIN_E22 -to cpu_s1_n 116 | set_location_assignment PIN_F21 -to cpu_s0_n 117 | set_location_assignment PIN_AA19 -to cpu_reset 118 | set_location_assignment PIN_AB19 -to cpu_a[0] 119 | set_location_assignment PIN_J18 -to cpu_a[1] 120 | set_location_assignment PIN_K17 -to cpu_a[2] 121 | set_location_assignment PIN_AB18 -to cpu_a[3] 122 | set_location_assignment PIN_W22 -to cpu_a[4] 123 | set_location_assignment PIN_AA20 -to cpu_a[5] 124 | set_location_assignment PIN_T18 -to cpu_a[6] 125 | set_location_assignment PIN_W21 -to cpu_a[7] 126 | set_location_assignment PIN_Y22 -to cpu_a[8] 127 | set_location_assignment PIN_AA21 -to cpu_a[9] 128 | set_location_assignment PIN_V22 -to cpu_a[10] 129 | set_location_assignment PIN_Y21 -to cpu_a[11] 130 | set_location_assignment PIN_U21 -to cpu_a[12] 131 | set_location_assignment PIN_V21 -to cpu_a[13] 132 | set_location_assignment PIN_U22 -to cpu_a[14] 133 | set_location_assignment PIN_N20 -to cpu_a[15] 134 | set_location_assignment PIN_P21 -to cpu_a[16] 135 | set_location_assignment PIN_M22 -to cpu_a[17] 136 | set_location_assignment PIN_M21 -to cpu_a[18] 137 | set_location_assignment PIN_K21 -to cpu_a[19] 138 | set_location_assignment PIN_L21 -to cpu_a[20] 139 | set_location_assignment PIN_H22 -to cpu_a[21] 140 | set_location_assignment PIN_J21 -to cpu_a[22] 141 | set_location_assignment PIN_H21 -to cpu_a[23] 142 | 143 | set_location_assignment PIN_R18 -to intf_irq_n 144 | 145 | set_location_assignment PIN_R20 -to uart_rxd 146 | set_location_assignment PIN_R19 -to uart_txd 147 | 148 | set_location_assignment PIN_N17 -to fdd_change_n 149 | set_location_assignment PIN_P17 -to fdd_rdata 150 | set_location_assignment PIN_N18 -to fdd_trk0_n 151 | set_location_assignment PIN_N19 -to fdd_index_n 152 | set_location_assignment PIN_H20 -to fdd_motor_n 153 | set_location_assignment PIN_H19 -to fdd_drvsel_n 154 | set_location_assignment PIN_F19 -to fdd_dir_n 155 | set_location_assignment PIN_D17 -to fdd_step_n 156 | set_location_assignment PIN_D19 -to fdd_wdata 157 | set_location_assignment PIN_D20 -to fdd_wgate_n 158 | set_location_assignment PIN_C19 -to fdd_head_n 159 | 160 | set_location_assignment PIN_AA17 -to sdram_dqm[0] 161 | set_location_assignment PIN_AB17 -to sdram_d[7] 162 | set_location_assignment PIN_AA16 -to sdram_d[6] 163 | set_location_assignment PIN_AB16 -to sdram_d[5] 164 | set_location_assignment PIN_AA15 -to sdram_d[4] 165 | set_location_assignment PIN_AB15 -to sdram_d[3] 166 | set_location_assignment PIN_AA14 -to sdram_d[2] 167 | set_location_assignment PIN_AB14 -to sdram_d[1] 168 | set_location_assignment PIN_AA13 -to sdram_d[0] 169 | set_location_assignment PIN_AB13 -to sdram_d[15] 170 | set_location_assignment PIN_V11 -to sdram_d[14] 171 | set_location_assignment PIN_AB10 -to sdram_d[13] 172 | set_location_assignment PIN_AA10 -to sdram_d[12] 173 | set_location_assignment PIN_AB9 -to sdram_d[11] 174 | set_location_assignment PIN_AA9 -to sdram_d[10] 175 | set_location_assignment PIN_AB8 -to sdram_a[4] 176 | set_location_assignment PIN_AA8 -to sdram_a[5] 177 | set_location_assignment PIN_AB7 -to sdram_a[6] 178 | set_location_assignment PIN_AA7 -to sdram_a[7] 179 | set_location_assignment PIN_AB5 -to sdram_a[8] 180 | set_location_assignment PIN_AA5 -to sdram_a[9] 181 | set_location_assignment PIN_AB4 -to sdram_a[11] 182 | set_location_assignment PIN_AA4 -to sdram_a[12] 183 | set_location_assignment PIN_AB3 -to sdram_cke 184 | set_location_assignment PIN_AA3 -to sdram_clk 185 | set_location_assignment PIN_Y3 -to sdram_d[9] 186 | set_location_assignment PIN_Y4 -to sdram_d[8] 187 | set_location_assignment PIN_V3 -to sdram_dqm[1] 188 | set_location_assignment PIN_V10 -to sdram_we_n 189 | set_location_assignment PIN_Y10 -to sdram_cas_n 190 | set_location_assignment PIN_T11 -to sdram_ras_n 191 | set_location_assignment PIN_T12 -to sdram_cs_n 192 | set_location_assignment PIN_T14 -to sdram_ba[0] 193 | set_location_assignment PIN_W14 -to sdram_ba[1] 194 | set_location_assignment PIN_W15 -to sdram_a[3] 195 | set_location_assignment PIN_W17 -to sdram_a[2] 196 | set_location_assignment PIN_Y17 -to sdram_a[1] 197 | set_location_assignment PIN_W19 -to sdram_a[0] 198 | set_location_assignment PIN_W20 -to sdram_a[10] 199 | 200 | set_location_assignment PIN_Y2 -to vram_a[10] 201 | set_location_assignment PIN_Y1 -to vram_a[11] 202 | set_location_assignment PIN_W2 -to vram_a[12] 203 | set_location_assignment PIN_W1 -to vram_a[13] 204 | set_location_assignment PIN_V2 -to vram_a[14] 205 | set_location_assignment PIN_V1 -to vram_d[8] 206 | set_location_assignment PIN_U2 -to vram_d[9] 207 | set_location_assignment PIN_U1 -to vram_d[12] 208 | set_location_assignment PIN_T3 -to vram_d[13] 209 | set_location_assignment PIN_R2 -to vram_d[14] 210 | set_location_assignment PIN_R1 -to vram_d[15] 211 | set_location_assignment PIN_P3 -to vram_dqm[0] 212 | set_location_assignment PIN_P1 -to vram_dqm[1] 213 | set_location_assignment PIN_P2 -to vram_oe_n 214 | set_location_assignment PIN_N1 -to vram_a[15] 215 | set_location_assignment PIN_N2 -to vram_a[16] 216 | set_location_assignment PIN_M1 -to vram_a[17] 217 | set_location_assignment PIN_M2 -to vram_we_n 218 | set_location_assignment PIN_J1 -to vram_d[7] 219 | set_location_assignment PIN_J2 -to vram_d[6] 220 | set_location_assignment PIN_H1 -to vram_d[5] 221 | set_location_assignment PIN_H2 -to vram_d[4] 222 | set_location_assignment PIN_F1 -to vram_d[3] 223 | set_location_assignment PIN_F2 -to vram_d[2] 224 | set_location_assignment PIN_E1 -to vram_d[1] 225 | set_location_assignment PIN_D2 -to vram_d[0] 226 | set_location_assignment PIN_C1 -to vram_cs_n 227 | set_location_assignment PIN_C2 -to vram_a[4] 228 | set_location_assignment PIN_B1 -to vram_a[3] 229 | set_location_assignment PIN_B2 -to vram_a[2] 230 | set_location_assignment PIN_G3 -to vram_a[1] 231 | set_location_assignment PIN_J3 -to vram_a[0] 232 | set_location_assignment PIN_V5 -to vram_d[10] 233 | set_location_assignment PIN_P6 -to vram_d[11] 234 | set_location_assignment PIN_N6 -to vram_a[9] 235 | set_location_assignment PIN_N5 -to vram_a[8] 236 | set_location_assignment PIN_M6 -to vram_a[7] 237 | set_location_assignment PIN_L6 -to vram_a[6] 238 | set_location_assignment PIN_M4 -to vram_a[5] 239 | 240 | set_location_assignment PIN_V4 -to intf[6] 241 | set_location_assignment PIN_Y6 -to intf[7] 242 | set_location_assignment PIN_W6 -to intf[8] 243 | set_location_assignment PIN_V6 -to intf[9] 244 | set_location_assignment PIN_W7 -to intf[10] 245 | set_location_assignment PIN_V7 -to intf[11] 246 | set_location_assignment PIN_U7 -to intf[12] 247 | set_location_assignment PIN_V8 -to intf[13] 248 | set_location_assignment PIN_V9 -to intf[14] 249 | set_location_assignment PIN_T16 -to intf[15] 250 | set_location_assignment PIN_U19 -to intf[16] 251 | set_location_assignment PIN_U20 -to intf[17] 252 | set_location_assignment PIN_R21 -to intf[18] 253 | set_location_assignment PIN_R22 -to intf[19] 254 | 255 | 256 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 257 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 258 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 259 | 260 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb1_m 261 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb1_p 262 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb2_m 263 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb2_p 264 | 265 | 266 | set_global_assignment -name VERILOG_FILE vdu.v 267 | set_global_assignment -name VERILOG_FILE uart.v 268 | set_global_assignment -name VERILOG_FILE top.v 269 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /fpga_pin_test/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input wire clk, 4 | input wire reset_n, 5 | 6 | output wire vga_vsync, 7 | output wire vga_hsync, 8 | output wire [7:0] vga_r, 9 | output wire [7:0] vga_g, 10 | output wire [7:0] vga_b, 11 | 12 | output wire [15:0] cpu_d, 13 | output wire [23:0] cpu_a, 14 | 15 | output wire cpu_bhe_n, 16 | output wire cpu_s0_n, 17 | output wire cpu_s1_n, 18 | output wire cpu_inta_n, 19 | output wire cpu_mio, 20 | 21 | output wire cpu_intr, 22 | output wire cpu_clk_n, 23 | output wire cpu_nmi_n, 24 | 25 | output wire cpu_error_n, 26 | 27 | output wire cpu_hold, 28 | output wire cpu_hlda, 29 | output wire cpu_reset, 30 | output wire cpu_ready, 31 | 32 | output wire sd_cs_n, 33 | input wire sd_miso, 34 | output wire sd_mosi, 35 | output wire sd_sck, 36 | 37 | output wire usb1_p, 38 | output wire usb1_m, 39 | output wire usb2_p, 40 | output wire usb2_m, 41 | 42 | input wire uart_rxd, 43 | output wire uart_txd, 44 | 45 | output wire audio_left, 46 | output wire audio_right, 47 | 48 | input wire fdd_change_n, 49 | input wire fdd_trk0_n, 50 | input wire fdd_index_n, 51 | output wire fdd_motor_n, 52 | output wire fdd_drvsel_n, 53 | output wire fdd_dir_n, 54 | output wire fdd_step_n, 55 | output wire fdd_wdata, 56 | output wire fdd_wgate_n, 57 | output wire fdd_head_n, 58 | 59 | output wire [12:0] sdram_a, 60 | output wire [15:0] sdram_d, 61 | output wire [1:0] sdram_dqm, 62 | output wire [1:0] sdram_ba, 63 | output wire sdram_clk, 64 | output wire sdram_cke, 65 | output wire sdram_cs_n, 66 | output wire sdram_we_n, 67 | output wire sdram_cas_n, 68 | output wire sdram_ras_n, 69 | 70 | output wire [17:0] vram_a, 71 | output wire [15:0] vram_d, 72 | output wire [1:0] vram_dqm, 73 | output wire vram_cs_n, 74 | output wire vram_we_n, 75 | output wire vram_oe_n, 76 | 77 | output wire intf_irq_n, 78 | output wire [19:6] intf 79 | ); 80 | 81 | ////////////////////////////////////////////////////////////////////////////// 82 | // VGA controller 83 | ////////////////////////////////////////////////////////////////////////////// 84 | 85 | vdu i_vdu 86 | ( 87 | .clk (clk), 88 | 89 | .hsync (vga_hsync), 90 | .vsync (vga_vsync), 91 | .red (vga_r), 92 | .green (vga_g), 93 | .blue (vga_b) 94 | ); 95 | 96 | ////////////////////////////////////////////////////////////////////////////// 97 | // UART 98 | ////////////////////////////////////////////////////////////////////////////// 99 | 100 | reg [7:0] uart_symbol; 101 | 102 | always @* 103 | begin 104 | case (delay[25:23]) 105 | 3'd0: uart_symbol <= 8'h54; 106 | 3'd1: uart_symbol <= 8'h65; 107 | 3'd2: uart_symbol <= 8'h73; 108 | 3'd3: uart_symbol <= 8'h74; 109 | 3'd4: uart_symbol <= 8'h0D; 110 | 3'd5: uart_symbol <= 8'h0A; 111 | default: uart_symbol <= 8'h20; 112 | endcase 113 | end 114 | 115 | uart i_uart 116 | ( 117 | .clk (clk), 118 | .addr (3'd0), 119 | .din ({24'h0, uart_symbol}), 120 | .lane (4'b1111), 121 | .wr (1'b1), 122 | .valid (delay[22:0] == 23'h10000), 123 | .txd (uart_txd) 124 | ); 125 | 126 | reg [25:0] delay; 127 | reg [7:0] shift; 128 | 129 | assign cpu_d = ~{2{shift}}; 130 | assign cpu_a = ~{3{shift}}; 131 | 132 | assign cpu_bhe_n = ~shift[0]; 133 | assign cpu_s0_n = ~shift[1]; 134 | assign cpu_s1_n = ~shift[2]; 135 | assign cpu_inta_n = ~shift[3]; 136 | assign cpu_mio = ~shift[4]; 137 | 138 | assign cpu_intr = ~shift[5]; 139 | assign cpu_clk_n = ~shift[6]; 140 | assign cpu_nmi_n = ~shift[7]; 141 | 142 | assign cpu_error_n = ~shift[0]; 143 | assign cpu_hold = ~shift[1]; 144 | assign cpu_hlda = ~shift[2]; 145 | assign cpu_reset = ~shift[3]; 146 | assign cpu_ready = ~shift[4]; 147 | 148 | assign sd_cs_n = ~shift[5]; 149 | assign sd_mosi = ~shift[6]; 150 | assign sd_sck = ~shift[7]; 151 | 152 | assign usb1_p = ~shift[0]; 153 | assign usb1_m = ~shift[1]; 154 | assign usb2_p = ~shift[2]; 155 | assign usb2_m = ~shift[3]; 156 | 157 | assign fdd_motor_n = ~shift[4]; 158 | assign fdd_drvsel_n = ~shift[5]; 159 | assign fdd_dir_n = ~shift[6]; 160 | assign fdd_step_n = ~shift[7]; 161 | assign fdd_wdata = ~shift[0]; 162 | assign fdd_wgate_n = ~shift[1]; 163 | assign fdd_head_n = ~shift[2]; 164 | 165 | assign sdram_a = ~{shift[0], shift[7:4], shift}; 166 | assign sdram_d = ~{2{shift}}; 167 | assign sdram_dqm = ~shift[1:0]; 168 | assign sdram_ba = ~shift[3:2]; 169 | assign sdram_clk = ~shift[4]; 170 | assign sdram_cke = ~shift[5]; 171 | assign sdram_cs_n = ~shift[6]; 172 | assign sdram_we_n = ~shift[7]; 173 | assign sdram_cas_n = ~shift[0]; 174 | assign sdram_ras_n = ~shift[1]; 175 | 176 | assign vram_a = ~{shift[3:2], shift, shift}; 177 | assign vram_d = ~{2{shift}}; 178 | assign vram_dqm = ~shift[5:4]; 179 | assign vram_cs_n = ~shift[6]; 180 | assign vram_we_n = ~shift[7]; 181 | assign vram_oe_n = ~shift[0]; 182 | 183 | assign intf_irq_n = ~shift[1]; 184 | assign intf = ~{shift[7:2], shift}; 185 | 186 | assign audio_left = delay[16] & (&delay[24:23]) & ~delay[25]; 187 | assign audio_right = delay[16] & (&delay[25:23]); 188 | 189 | always @(posedge clk or negedge reset_n) 190 | begin 191 | if (~reset_n) 192 | begin 193 | delay <= 26'd0; 194 | shift <= 8'd1; 195 | end 196 | else 197 | begin 198 | delay <= delay + 1'd1; 199 | 200 | if (&delay[19:0]) 201 | begin 202 | if (|shift) 203 | shift <= {shift[6:0], shift[7]}; 204 | else 205 | shift <= 8'h01; 206 | end 207 | end 208 | end 209 | 210 | endmodule 211 | -------------------------------------------------------------------------------- /fpga_pin_test/uart.v: -------------------------------------------------------------------------------- 1 | module uart 2 | ( 3 | input wire clk, 4 | 5 | input wire [ 2:0] addr, 6 | input wire [31:0] din, 7 | output reg [31:0] dout, 8 | input wire [ 3:0] lane, 9 | input wire wr, 10 | input wire valid, 11 | 12 | output reg txd 13 | ); 14 | 15 | localparam 16 | BIT_TIME = 12'd433; 17 | 18 | localparam 19 | S_IDLE = 2'd0, 20 | S_TRANSMIT = 2'd1; 21 | 22 | reg [11:0] tdiv; 23 | reg [1:0] tstate; 24 | reg [9:0] tdata; 25 | 26 | reg [31:0] regs1; 27 | reg [31:0] regs2; 28 | 29 | always @(posedge clk) 30 | begin 31 | tdiv <= 32 | tstate == S_IDLE ? 12'd0 : 33 | tdiv == BIT_TIME ? 12'd0 : 34 | tdiv + 1'd1; 35 | 36 | txd <= 37 | tstate == S_IDLE ? 1'b1 : 38 | tdata[0]; 39 | 40 | if (addr[2]) 41 | dout <= tstate == S_IDLE ? 32'h6000 : 32'h0; 42 | else 43 | dout <= 32'd0; 44 | 45 | case (tstate) 46 | S_IDLE: 47 | begin 48 | if (valid && wr && ~addr[2] && lane[0]) 49 | begin 50 | tdata <= {1'b1, din[7:0], 1'b0}; 51 | tstate <= S_TRANSMIT; 52 | end 53 | end 54 | S_TRANSMIT: 55 | begin 56 | if (tdiv == BIT_TIME) 57 | begin 58 | tdata <= {1'b0, tdata[9:1]}; 59 | if (tdata == 10'd1) 60 | tstate <= S_IDLE; 61 | end 62 | end 63 | endcase 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /fpga_pin_test/vdu.v: -------------------------------------------------------------------------------- 1 | module vdu 2 | ( 3 | input wire clk, 4 | 5 | output wire hsync, 6 | output wire vsync, 7 | output reg [ 7:0] red, 8 | output reg [ 7:0] green, 9 | output reg [ 7:0] blue 10 | ); 11 | 12 | assign hsync = ~((hcounter >= 10'd664) && (hcounter < 10'd760)); 13 | assign vsync = ~((vcounter >= 10'd490) && (vcounter < 10'd492)); 14 | 15 | reg pixel_div; 16 | 17 | reg [9:0] hcounter; 18 | reg [9:0] vcounter; 19 | 20 | reg [7:0] frame; 21 | 22 | always @(posedge clk) 23 | begin 24 | pixel_div <= ~pixel_div; 25 | 26 | if (hcounter < 10'd640 && vcounter < 10'd480) 27 | begin 28 | red <= hcounter[7:0] + frame; 29 | green <= vcounter[7:0] + hcounter[8:1]; 30 | blue <= vcounter[7:0]; 31 | end 32 | else 33 | begin 34 | red <= 8'd0; 35 | green <= 8'd0; 36 | blue <= 8'd0; 37 | end 38 | 39 | if (pixel_div) 40 | begin 41 | if (hcounter == 10'd799) 42 | begin 43 | hcounter <= 10'd0; 44 | if (vcounter == 10'd524) 45 | begin 46 | vcounter <= 10'd0; 47 | frame <= frame + 1'd1; 48 | end 49 | else 50 | begin 51 | vcounter <= vcounter + 10'd1; 52 | end 53 | end 54 | else 55 | hcounter <= hcounter + 10'd1; 56 | end 57 | end 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /pcb/Gerber.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pcb/Gerber.zip -------------------------------------------------------------------------------- /pcb/ep4f23_286_r2.lay6: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pcb/ep4f23_286_r2.lay6 -------------------------------------------------------------------------------- /pcb/ep4f23_286_r2_2.lay6: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pcb/ep4f23_286_r2_2.lay6 -------------------------------------------------------------------------------- /pcb/ep4f23_286_v2.pcb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pcb/ep4f23_286_v2.pcb -------------------------------------------------------------------------------- /pcb/ep4f23_286_v2_m1.pcb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pcb/ep4f23_286_v2_m1.pcb -------------------------------------------------------------------------------- /pictures/1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/1.png -------------------------------------------------------------------------------- /pictures/2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/2.png -------------------------------------------------------------------------------- /pictures/3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/3.png -------------------------------------------------------------------------------- /pictures/4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/4.png -------------------------------------------------------------------------------- /pictures/board.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/board.jpg -------------------------------------------------------------------------------- /pictures/bottom.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/bottom.gif -------------------------------------------------------------------------------- /pictures/cpu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/cpu.png -------------------------------------------------------------------------------- /pictures/pcad.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/pcad.jpg -------------------------------------------------------------------------------- /pictures/sch1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/sch1.png -------------------------------------------------------------------------------- /pictures/top.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/top.gif -------------------------------------------------------------------------------- /pictures/usb_nak.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/usb_nak.png -------------------------------------------------------------------------------- /pictures/usb_osc.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/b-dmitry1/fpga286r2/b6cb590470f955086b90ae315f543ab52f73c1fa/pictures/usb_osc.jpg -------------------------------------------------------------------------------- /sch/README.md: -------------------------------------------------------------------------------- 1 | 2 | ![cpu](/pictures/1.png) 3 | 4 | ![overshoot](/pictures/2.png) 5 | 6 | ![interfaces](/pictures/3.png) 7 | 8 | ![ram](/pictures/4.png) 9 | -------------------------------------------------------------------------------- /src/BIOS.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "BIOS.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "BIOS_bb.v"] 5 | -------------------------------------------------------------------------------- /src/BIOS.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: BIOS.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module BIOS ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [11:0] address; 45 | input clock; 46 | output [15:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [15:0] sub_wire0; 56 | wire [15:0] q = sub_wire0[15:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({16{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | altsyncram_component.init_file = "C:/nasm/bios.mif", 87 | altsyncram_component.intended_device_family = "Cyclone IV E", 88 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 89 | altsyncram_component.lpm_type = "altsyncram", 90 | altsyncram_component.numwords_a = 4096, 91 | altsyncram_component.operation_mode = "ROM", 92 | altsyncram_component.outdata_aclr_a = "NONE", 93 | altsyncram_component.outdata_reg_a = "CLOCK0", 94 | altsyncram_component.widthad_a = 12, 95 | altsyncram_component.width_a = 16, 96 | altsyncram_component.width_byteena_a = 1; 97 | 98 | 99 | endmodule 100 | 101 | // ============================================================ 102 | // CNX file retrieval info 103 | // ============================================================ 104 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 105 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 108 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 110 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 111 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 114 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 115 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 116 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 117 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 118 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 119 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 120 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 121 | // Retrieval info: PRIVATE: MIFfilename STRING "C:/nasm/bios.mif" 122 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 123 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 124 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 125 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 126 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 127 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 128 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 129 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 130 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 131 | // Retrieval info: PRIVATE: rden NUMERIC "0" 132 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 133 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 134 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: INIT_FILE STRING "C:/nasm/bios.mif" 137 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 138 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 139 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 140 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 141 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 142 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 144 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 145 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 146 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 147 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 148 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 149 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 150 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 151 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 152 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 153 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.v TRUE 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.inc FALSE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.cmp FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.bsf FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_inst.v FALSE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_bb.v TRUE 159 | // Retrieval info: LIB_FILE: altera_mf 160 | -------------------------------------------------------------------------------- /src/BIOS_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: BIOS.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module BIOS ( 35 | address, 36 | clock, 37 | q); 38 | 39 | input [11:0] address; 40 | input clock; 41 | output [15:0] q; 42 | `ifndef ALTERA_RESERVED_QIS 43 | // synopsys translate_off 44 | `endif 45 | tri1 clock; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_on 48 | `endif 49 | 50 | endmodule 51 | 52 | // ============================================================ 53 | // CNX file retrieval info 54 | // ============================================================ 55 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 56 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 59 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 61 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 62 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 65 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 66 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 67 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 68 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 69 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 70 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 71 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 72 | // Retrieval info: PRIVATE: MIFfilename STRING "C:/nasm/bios.mif" 73 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 74 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 75 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 76 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 77 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 78 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 79 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 80 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 81 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 82 | // Retrieval info: PRIVATE: rden NUMERIC "0" 83 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 84 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 85 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: INIT_FILE STRING "C:/nasm/bios.mif" 88 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 90 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 91 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 92 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 93 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 94 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 95 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 96 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 97 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 98 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 99 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 100 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 101 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 102 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 103 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.v TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.inc FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.cmp FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS.bsf FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_inst.v FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_bb.v TRUE 110 | // Retrieval info: LIB_FILE: altera_mf 111 | -------------------------------------------------------------------------------- /src/Font.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Font.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Font_bb.v"] 5 | -------------------------------------------------------------------------------- /src/Font.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: Font.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module Font ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [11:0] address; 45 | input clock; 46 | output [7:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [7:0] sub_wire0; 56 | wire [7:0] q = sub_wire0[7:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({8{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | altsyncram_component.init_file = "vgafont.mif", 87 | altsyncram_component.intended_device_family = "Cyclone IV E", 88 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 89 | altsyncram_component.lpm_type = "altsyncram", 90 | altsyncram_component.numwords_a = 4096, 91 | altsyncram_component.operation_mode = "ROM", 92 | altsyncram_component.outdata_aclr_a = "NONE", 93 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 94 | altsyncram_component.widthad_a = 12, 95 | altsyncram_component.width_a = 8, 96 | altsyncram_component.width_byteena_a = 1; 97 | 98 | 99 | endmodule 100 | 101 | // ============================================================ 102 | // CNX file retrieval info 103 | // ============================================================ 104 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 105 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 108 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 110 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 111 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 114 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 115 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 116 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 117 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 118 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 119 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 120 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 121 | // Retrieval info: PRIVATE: MIFfilename STRING "vgafont.mif" 122 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 123 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 124 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 125 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 126 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 127 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 128 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 129 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 130 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 131 | // Retrieval info: PRIVATE: rden NUMERIC "0" 132 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 133 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 134 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: INIT_FILE STRING "vgafont.mif" 137 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 138 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 139 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 140 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 141 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 142 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 144 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 145 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 146 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 147 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 148 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 149 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 150 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 151 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 152 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 153 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.v TRUE 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.inc FALSE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.cmp FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.bsf FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font_inst.v FALSE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font_bb.v TRUE 159 | // Retrieval info: LIB_FILE: altera_mf 160 | -------------------------------------------------------------------------------- /src/Font_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: Font.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module Font ( 35 | address, 36 | clock, 37 | q); 38 | 39 | input [11:0] address; 40 | input clock; 41 | output [7:0] q; 42 | `ifndef ALTERA_RESERVED_QIS 43 | // synopsys translate_off 44 | `endif 45 | tri1 clock; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_on 48 | `endif 49 | 50 | endmodule 51 | 52 | // ============================================================ 53 | // CNX file retrieval info 54 | // ============================================================ 55 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 56 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 59 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 61 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 62 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 65 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 66 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 67 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 68 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 69 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 70 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 71 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 72 | // Retrieval info: PRIVATE: MIFfilename STRING "vgafont.mif" 73 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 74 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 75 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 76 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 77 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 78 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 79 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 80 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 81 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 82 | // Retrieval info: PRIVATE: rden NUMERIC "0" 83 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 84 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 85 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: INIT_FILE STRING "vgafont.mif" 88 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 90 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 91 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 92 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 93 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 94 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 95 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 96 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 97 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 98 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 99 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 100 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 101 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 102 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 103 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.v TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.inc FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.cmp FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font.bsf FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font_inst.v FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL Font_bb.v TRUE 110 | // Retrieval info: LIB_FILE: altera_mf 111 | -------------------------------------------------------------------------------- /src/Main.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 00:12:21 January 02, 2023 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Main_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV E" 40 | set_global_assignment -name DEVICE EP4CE15F23C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY Main 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:12:21 JANUARY 02, 2023" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 49 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 50 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 51 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 52 | set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V 53 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 54 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 55 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 56 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 57 | 58 | set_location_assignment PIN_G1 -to clk 59 | set_location_assignment PIN_T1 -to reset_n 60 | 61 | set_location_assignment PIN_B3 -to vga_vsync 62 | set_location_assignment PIN_A3 -to vga_hsync 63 | set_location_assignment PIN_B4 -to vga_r[4] 64 | set_location_assignment PIN_A4 -to vga_r[5] 65 | set_location_assignment PIN_B5 -to vga_r[6] 66 | set_location_assignment PIN_A5 -to vga_r[7] 67 | set_location_assignment PIN_B6 -to vga_g[4] 68 | set_location_assignment PIN_A6 -to vga_g[5] 69 | set_location_assignment PIN_B7 -to vga_g[6] 70 | set_location_assignment PIN_A7 -to vga_g[7] 71 | set_location_assignment PIN_B8 -to vga_b[4] 72 | set_location_assignment PIN_A8 -to vga_b[5] 73 | set_location_assignment PIN_B9 -to vga_b[6] 74 | set_location_assignment PIN_A9 -to vga_b[7] 75 | 76 | set_location_assignment PIN_B10 -to usb1_p 77 | set_location_assignment PIN_A10 -to usb1_m 78 | set_location_assignment PIN_E11 -to usb2_p 79 | set_location_assignment PIN_A13 -to usb2_m 80 | 81 | set_location_assignment PIN_B13 -to sd_cs_n 82 | set_location_assignment PIN_A14 -to sd_mosi 83 | set_location_assignment PIN_B14 -to sd_sck 84 | set_location_assignment PIN_A15 -to sd_miso 85 | 86 | set_location_assignment PIN_B15 -to audio_left 87 | set_location_assignment PIN_A16 -to audio_right 88 | 89 | set_location_assignment PIN_AB20 -to cpu_d[0] 90 | set_location_assignment PIN_M19 -to cpu_d[1] 91 | set_location_assignment PIN_P22 -to cpu_d[2] 92 | set_location_assignment PIN_M20 -to cpu_d[3] 93 | set_location_assignment PIN_J22 -to cpu_d[4] 94 | set_location_assignment PIN_F22 -to cpu_d[5] 95 | set_location_assignment PIN_F20 -to cpu_d[6] 96 | set_location_assignment PIN_D21 -to cpu_d[7] 97 | set_location_assignment PIN_AA18 -to cpu_d[8] 98 | set_location_assignment PIN_K18 -to cpu_d[9] 99 | set_location_assignment PIN_B16 -to cpu_d[10] 100 | set_location_assignment PIN_A17 -to cpu_d[11] 101 | set_location_assignment PIN_B17 -to cpu_d[12] 102 | set_location_assignment PIN_B18 -to cpu_d[13] 103 | set_location_assignment PIN_A19 -to cpu_d[14] 104 | set_location_assignment PIN_A18 -to cpu_d[15] 105 | set_location_assignment PIN_B19 -to cpu_intr 106 | set_location_assignment PIN_B20 -to cpu_clk_n 107 | set_location_assignment PIN_C17 -to cpu_nmi_n 108 | set_location_assignment PIN_B21 -to cpu_bhe_n 109 | set_location_assignment PIN_B22 -to cpu_error_n 110 | set_location_assignment PIN_C20 -to cpu_ready 111 | set_location_assignment PIN_C21 -to cpu_inta_n 112 | set_location_assignment PIN_C22 -to cpu_mio 113 | set_location_assignment PIN_D22 -to cpu_hold 114 | set_location_assignment PIN_E21 -to cpu_hlda 115 | set_location_assignment PIN_E22 -to cpu_s1_n 116 | set_location_assignment PIN_F21 -to cpu_s0_n 117 | set_location_assignment PIN_AA19 -to cpu_reset 118 | set_location_assignment PIN_AB19 -to cpu_a[0] 119 | set_location_assignment PIN_J18 -to cpu_a[1] 120 | set_location_assignment PIN_K17 -to cpu_a[2] 121 | set_location_assignment PIN_AB18 -to cpu_a[3] 122 | set_location_assignment PIN_W22 -to cpu_a[4] 123 | set_location_assignment PIN_AA20 -to cpu_a[5] 124 | set_location_assignment PIN_T18 -to cpu_a[6] 125 | set_location_assignment PIN_W21 -to cpu_a[7] 126 | set_location_assignment PIN_Y22 -to cpu_a[8] 127 | set_location_assignment PIN_AA21 -to cpu_a[9] 128 | set_location_assignment PIN_V22 -to cpu_a[10] 129 | set_location_assignment PIN_Y21 -to cpu_a[11] 130 | set_location_assignment PIN_U21 -to cpu_a[12] 131 | set_location_assignment PIN_V21 -to cpu_a[13] 132 | set_location_assignment PIN_U22 -to cpu_a[14] 133 | set_location_assignment PIN_N20 -to cpu_a[15] 134 | set_location_assignment PIN_P21 -to cpu_a[16] 135 | set_location_assignment PIN_M22 -to cpu_a[17] 136 | set_location_assignment PIN_M21 -to cpu_a[18] 137 | set_location_assignment PIN_K21 -to cpu_a[19] 138 | set_location_assignment PIN_L21 -to cpu_a[20] 139 | set_location_assignment PIN_H22 -to cpu_a[21] 140 | set_location_assignment PIN_J21 -to cpu_a[22] 141 | set_location_assignment PIN_H21 -to cpu_a[23] 142 | 143 | set_location_assignment PIN_R18 -to intf_irq_n 144 | 145 | set_location_assignment PIN_R20 -to uart_rxd 146 | set_location_assignment PIN_R19 -to uart_txd 147 | 148 | set_location_assignment PIN_N17 -to fdd_change_n 149 | set_location_assignment PIN_P17 -to fdd_rdata 150 | set_location_assignment PIN_N18 -to fdd_trk0_n 151 | set_location_assignment PIN_N19 -to fdd_index_n 152 | set_location_assignment PIN_H20 -to fdd_motor_n 153 | set_location_assignment PIN_H19 -to fdd_drvsel_n 154 | set_location_assignment PIN_F19 -to fdd_dir_n 155 | set_location_assignment PIN_D17 -to fdd_step_n 156 | set_location_assignment PIN_D19 -to fdd_wdata 157 | set_location_assignment PIN_D20 -to fdd_wgate_n 158 | set_location_assignment PIN_C19 -to fdd_head_n 159 | 160 | set_location_assignment PIN_AA17 -to sdram_dqm[0] 161 | set_location_assignment PIN_AB17 -to sdram_d[7] 162 | set_location_assignment PIN_AA16 -to sdram_d[6] 163 | set_location_assignment PIN_AB16 -to sdram_d[5] 164 | set_location_assignment PIN_AA15 -to sdram_d[4] 165 | set_location_assignment PIN_AB15 -to sdram_d[3] 166 | set_location_assignment PIN_AA14 -to sdram_d[2] 167 | set_location_assignment PIN_AB14 -to sdram_d[1] 168 | set_location_assignment PIN_AA13 -to sdram_d[0] 169 | set_location_assignment PIN_AB13 -to sdram_d[15] 170 | set_location_assignment PIN_V11 -to sdram_d[14] 171 | set_location_assignment PIN_AB10 -to sdram_d[13] 172 | set_location_assignment PIN_AA10 -to sdram_d[12] 173 | set_location_assignment PIN_AB9 -to sdram_d[11] 174 | set_location_assignment PIN_AA9 -to sdram_d[10] 175 | set_location_assignment PIN_AB8 -to sdram_a[4] 176 | set_location_assignment PIN_AA8 -to sdram_a[5] 177 | set_location_assignment PIN_AB7 -to sdram_a[6] 178 | set_location_assignment PIN_AA7 -to sdram_a[7] 179 | set_location_assignment PIN_AB5 -to sdram_a[8] 180 | set_location_assignment PIN_AA5 -to sdram_a[9] 181 | set_location_assignment PIN_AB4 -to sdram_a[11] 182 | set_location_assignment PIN_AA4 -to sdram_a[12] 183 | set_location_assignment PIN_AB3 -to sdram_cke 184 | set_location_assignment PIN_AA3 -to sdram_clk 185 | set_location_assignment PIN_Y3 -to sdram_d[9] 186 | set_location_assignment PIN_Y4 -to sdram_d[8] 187 | set_location_assignment PIN_V3 -to sdram_dqm[1] 188 | set_location_assignment PIN_V10 -to sdram_we_n 189 | set_location_assignment PIN_Y10 -to sdram_cas_n 190 | set_location_assignment PIN_T11 -to sdram_ras_n 191 | set_location_assignment PIN_T12 -to sdram_cs_n 192 | set_location_assignment PIN_T14 -to sdram_ba[0] 193 | set_location_assignment PIN_W14 -to sdram_ba[1] 194 | set_location_assignment PIN_W15 -to sdram_a[3] 195 | set_location_assignment PIN_W17 -to sdram_a[2] 196 | set_location_assignment PIN_Y17 -to sdram_a[1] 197 | set_location_assignment PIN_W19 -to sdram_a[0] 198 | set_location_assignment PIN_W20 -to sdram_a[10] 199 | 200 | set_location_assignment PIN_Y2 -to vram_a[10] 201 | set_location_assignment PIN_Y1 -to vram_a[11] 202 | set_location_assignment PIN_W2 -to vram_a[12] 203 | set_location_assignment PIN_W1 -to vram_a[13] 204 | set_location_assignment PIN_V2 -to vram_a[14] 205 | set_location_assignment PIN_V1 -to vram_d[8] 206 | set_location_assignment PIN_U2 -to vram_d[9] 207 | set_location_assignment PIN_U1 -to vram_d[12] 208 | set_location_assignment PIN_T3 -to vram_d[13] 209 | set_location_assignment PIN_R2 -to vram_d[14] 210 | set_location_assignment PIN_R1 -to vram_d[15] 211 | set_location_assignment PIN_P3 -to vram_dqm[0] 212 | set_location_assignment PIN_P1 -to vram_dqm[1] 213 | set_location_assignment PIN_P2 -to vram_oe_n 214 | set_location_assignment PIN_N1 -to vram_a[15] 215 | set_location_assignment PIN_N2 -to vram_a[16] 216 | set_location_assignment PIN_M1 -to vram_a[17] 217 | set_location_assignment PIN_M2 -to vram_we_n 218 | set_location_assignment PIN_J1 -to vram_d[7] 219 | set_location_assignment PIN_J2 -to vram_d[6] 220 | set_location_assignment PIN_H1 -to vram_d[5] 221 | set_location_assignment PIN_H2 -to vram_d[4] 222 | set_location_assignment PIN_F1 -to vram_d[3] 223 | set_location_assignment PIN_F2 -to vram_d[2] 224 | set_location_assignment PIN_E1 -to vram_d[1] 225 | set_location_assignment PIN_D2 -to vram_d[0] 226 | set_location_assignment PIN_C1 -to vram_cs_n 227 | set_location_assignment PIN_C2 -to vram_a[4] 228 | set_location_assignment PIN_B1 -to vram_a[3] 229 | set_location_assignment PIN_B2 -to vram_a[2] 230 | set_location_assignment PIN_G3 -to vram_a[1] 231 | set_location_assignment PIN_J3 -to vram_a[0] 232 | set_location_assignment PIN_V5 -to vram_d[10] 233 | set_location_assignment PIN_P6 -to vram_d[11] 234 | set_location_assignment PIN_N6 -to vram_a[9] 235 | set_location_assignment PIN_N5 -to vram_a[8] 236 | set_location_assignment PIN_M6 -to vram_a[7] 237 | set_location_assignment PIN_L6 -to vram_a[6] 238 | set_location_assignment PIN_M4 -to vram_a[5] 239 | 240 | set_location_assignment PIN_V4 -to intf[6] 241 | set_location_assignment PIN_Y6 -to intf[7] 242 | set_location_assignment PIN_W6 -to intf[8] 243 | set_location_assignment PIN_V6 -to intf[9] 244 | set_location_assignment PIN_W7 -to intf[10] 245 | set_location_assignment PIN_V7 -to intf[11] 246 | set_location_assignment PIN_U7 -to intf[12] 247 | set_location_assignment PIN_V8 -to intf[13] 248 | set_location_assignment PIN_V9 -to intf[14] 249 | set_location_assignment PIN_T16 -to intf[15] 250 | set_location_assignment PIN_U19 -to intf[16] 251 | set_location_assignment PIN_U20 -to intf[17] 252 | set_location_assignment PIN_R21 -to intf[18] 253 | set_location_assignment PIN_R22 -to intf[19] 254 | 255 | 256 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 257 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 258 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 259 | 260 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb1_m 261 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb1_p 262 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb2_m 263 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb2_p 264 | set_global_assignment -name VERILOG_FILE PIC.v 265 | set_global_assignment -name VERILOG_FILE PIT.v 266 | set_global_assignment -name VERILOG_FILE SPI.v 267 | set_global_assignment -name VERILOG_FILE SDRAM.v 268 | set_global_assignment -name VERILOG_FILE PLL1.v 269 | set_global_assignment -name VERILOG_FILE BIOS.v 270 | set_global_assignment -name VERILOG_FILE VGARegs.v 271 | set_global_assignment -name VERILOG_FILE VGA.v 272 | set_global_assignment -name VERILOG_FILE Font.v 273 | set_global_assignment -name VERILOG_FILE SRAM.v 274 | set_global_assignment -name VERILOG_FILE Main.v 275 | set_global_assignment -name VERILOG_FILE UART_tx.v 276 | set_global_assignment -name VERILOG_FILE USB_LS_PHY.v 277 | set_global_assignment -name VERILOG_FILE USB_LS_HID.v 278 | set_global_assignment -name VERILOG_FILE PS2.v 279 | set_global_assignment -name QIP_FILE keyboard.qip 280 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /src/Main.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /src/Main.v: -------------------------------------------------------------------------------- 1 | module Main( 2 | input wire clk, 3 | input wire reset_n, 4 | 5 | output wire vga_vsync, 6 | output wire vga_hsync, 7 | output wire [7:4] vga_r, 8 | output wire [7:4] vga_g, 9 | output wire [7:4] vga_b, 10 | 11 | inout reg [15:0] cpu_d, 12 | input wire [23:0] cpu_a, 13 | 14 | input wire cpu_bhe_n, 15 | input wire cpu_s0_n, 16 | input wire cpu_s1_n, 17 | input wire cpu_inta_n, 18 | input wire cpu_mio, 19 | 20 | output wire cpu_intr, 21 | output reg cpu_clk_n, 22 | output wire cpu_nmi_n, 23 | 24 | input wire cpu_error_n, 25 | 26 | output wire cpu_hold, 27 | input wire cpu_hlda, 28 | output reg cpu_reset, 29 | output reg cpu_ready, 30 | 31 | output wire sd_cs_n, 32 | input wire sd_miso, 33 | output wire sd_mosi, 34 | output wire sd_sck, 35 | 36 | inout wire usb1_p, 37 | inout wire usb1_m, 38 | inout wire usb2_p, 39 | inout wire usb2_m, 40 | 41 | input wire uart_rxd, 42 | output wire uart_txd, 43 | 44 | output wire audio_left, 45 | output wire audio_right, 46 | 47 | input wire fdd_change_n, 48 | input wire fdd_wprot_n, 49 | input wire fdd_trk0_n, 50 | input wire fdd_index_n, 51 | output wire fdd_motor_n, 52 | output wire fdd_drvsel_n, 53 | output wire fdd_dir_n, 54 | output wire fdd_step_n, 55 | output wire fdd_wdata, 56 | output wire fdd_wgate_n, 57 | output wire fdd_head_n, 58 | 59 | output wire [12:0] sdram_a, 60 | inout wire [15:0] sdram_d, 61 | output wire [1:0] sdram_dqm, 62 | output wire [1:0] sdram_ba, 63 | output wire sdram_clk, 64 | output wire sdram_cke, 65 | output wire sdram_cs_n, 66 | output wire sdram_we_n, 67 | output wire sdram_cas_n, 68 | output wire sdram_ras_n, 69 | 70 | output wire [17:0] vram_a, 71 | inout wire [15:0] vram_d, 72 | output wire [1:0] vram_dqm, 73 | output wire vram_cs_n, 74 | output wire vram_we_n, 75 | output wire vram_oe_n, 76 | 77 | output reg intf_irq_n, 78 | inout reg [19:6] intf 79 | ); 80 | 81 | assign cpu_nmi_n = 1'b1; 82 | assign cpu_hold = 1'b0; 83 | 84 | wire empty_txd; 85 | 86 | always @(posedge clk) 87 | begin 88 | intf_irq_n <= 1'bZ; 89 | intf[19:6] <= 14'bZZZZZZZZZZZZZZ; 90 | end 91 | 92 | 93 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 94 | // USB to virtual PS/2 converter 95 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 96 | wire [7:0] ps2_iodout; 97 | wire cpu_rdin_ps2; 98 | reg cpu_rdout_ps2; 99 | wire cpu_wrin_ps2; 100 | reg cpu_wrout_ps2; 101 | 102 | PS2 ps2( 103 | .clk(clk), 104 | .reset_n(reset_n), 105 | 106 | .led(audio_left), 107 | 108 | .dm(usb2_m), 109 | .dp(usb2_p), 110 | 111 | .port(addr_8bit), 112 | .dout(ps2_iodout), 113 | .din(data_8bit), 114 | .cpu_iordin(cpu_rdout_ps2), 115 | .cpu_iordout(cpu_rdin_ps2), 116 | .cpu_iowrin(cpu_wrout_ps2), 117 | .cpu_iowrout(cpu_wrin_ps2), 118 | 119 | .irq1(irq[1]) 120 | ); 121 | 122 | 123 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 124 | // UART 125 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 126 | reg [7:0] uart_tx_data; 127 | reg cpu_wrout_dbg; 128 | wire uart_tx_in; 129 | wire dbg_ready = cpu_wrout_dbg == uart_tx_in; 130 | wire empty_txd2; 131 | UART_tx uart_tx( 132 | .clk(clk), 133 | .data(data_8bit), 134 | .send_in(cpu_wrout_dbg), 135 | .send_out(uart_tx_in), 136 | .txd(uart_txd) 137 | ); 138 | 139 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 140 | // PLL 141 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 142 | wire clk250; 143 | wire clk_sdram; 144 | wire clk_sram; 145 | wire clk2; 146 | wire clk48; 147 | PLL1 pll1(.inclk0(clk), .c0(clk_sdram), .c1(clk250), .c2(clk_sram), .c3(clk2), .c4(clk48)); 148 | 149 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 150 | // SDRAM 151 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 152 | wire [15:0] cpu_dout_sdram; 153 | reg [15:0] cpu_din_sdram; 154 | wire cpu_rdin_sdram; 155 | reg cpu_rdout_sdram; 156 | wire cpu_wrin_sdram; 157 | reg cpu_wrout_sdram; 158 | wire sdram_cpu_addr_hit; 159 | wire sdram_ready; 160 | 161 | SDRAM sdram(.clk(clk), .clk1(clk_sdram), .reset_n(reset_n), .ready(sdram_ready), 162 | .cpu_addr(c_a), .cpu_bhe_n(c_bhe_n), .cpu_din(c_d), .cpu_dout(cpu_dout_sdram), .cpu_addr_hit(sdram_cpu_addr_hit), 163 | .cpu_rdin(cpu_rdout_sdram), .cpu_rdout(cpu_rdin_sdram), .cpu_wrin(cpu_wrout_sdram), .cpu_wrout(cpu_wrin_sdram), 164 | 165 | .a(sdram_a), .ba(sdram_ba), .d(sdram_d), .ras_n(sdram_ras_n), .cas_n(sdram_cas_n), .we_n(sdram_we_n), .cs_n(sdram_cs_n), 166 | .sclk(sdram_clk), .scke(sdram_cke), .dqm(sdram_dqm)); 167 | 168 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 169 | // SRAM 170 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 171 | wire [15:0] cpu_dout_sram; 172 | reg [15:0] cpu_din_sram; 173 | wire cpu_rdin_sram; 174 | reg cpu_rdout_sram; 175 | wire cpu_wrin_sram; 176 | reg cpu_wrout_sram; 177 | wire sram_ready; 178 | 179 | wire [23:0] gpu_addr; 180 | wire [31:0] gpu_din; 181 | wire [31:0] gpu_dout; 182 | wire gpu_rdin; 183 | wire gpu_rdout; 184 | wire gpu_wrin; 185 | wire gpu_wrout; 186 | 187 | SRAM sram(.clk(clk), 188 | .cpu_addr(c_a), .cpu_bhe_n(c_bhe_n), .cpu_din(c_d), .cpu_dout(cpu_dout_sram), .ready(sram_ready), 189 | .cpu_rdin(cpu_rdout_sram), .cpu_rdout(cpu_rdin_sram), .cpu_wrin(cpu_wrout_sram), .cpu_wrout(cpu_wrin_sram), 190 | .gpu_addr(gpu_addr), .gpu_din(gpu_din), .gpu_dout(gpu_dout), 191 | .gpu_rdin(gpu_rdin), .gpu_rdout(gpu_rdout), .gpu_wrin(gpu_wrin), .gpu_wrout(gpu_wrout), 192 | .video_addr(video_addr), .video_dout(video_din), 193 | .a(vram_a), .d(vram_d), .we_n(vram_we_n), .cs_n(vram_cs_n), .oe_n(vram_oe_n), 194 | .lb_n(vram_dqm[0]), .ub_n(vram_dqm[1])); 195 | 196 | 197 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 198 | // VGA 199 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 200 | wire [23:0] video_addr; 201 | wire [63:0] video_din; 202 | wire [7:0] video_red; 203 | wire [7:0] video_green; 204 | wire [7:0] video_blue; 205 | assign vga_r = video_red[7:4]; 206 | assign vga_g = video_green[7:4]; 207 | assign vga_b = video_blue[7:4]; 208 | wire [7:0] vga_iodout; 209 | wire [15:0] vga_dout; 210 | wire vga_ready; 211 | wire vga_planar; 212 | 213 | wire cpu_rdin_vga; 214 | reg cpu_rdout_vga; 215 | wire cpu_wrin_vga; 216 | reg cpu_wrout_vga; 217 | 218 | VGA vga(.clk(clk), .reset_n(reset_n), .ready(vga_ready), 219 | //.a(ca), .din(cdout), .dout(vga_dout), .mrdin(cmrdout), .mwrin(cmwrout), 220 | .port(addr_8bit[7:0]), .iodin(data_8bit), .iodout(vga_iodout), 221 | .iordin(cpu_rdout_vga), 222 | .iordout(cpu_rdin_vga), 223 | .iowrin(cpu_wrout_vga), 224 | .iowrout(cpu_wrin_vga), 225 | 226 | .hsync(vga_hsync), .vsync(vga_vsync), 227 | .red(video_red), .green(video_green), .blue(video_blue), 228 | .video_addr(video_addr), 229 | 230 | .video_din(video_din), 231 | 232 | .gpu_addr(gpu_addr), 233 | .gpu_din(gpu_dout), 234 | .gpu_dout(gpu_din), 235 | .gpu_rdin(gpu_rdout), 236 | .gpu_rdout(gpu_rdin), 237 | .gpu_wrin(gpu_wrout), 238 | .gpu_wrout(gpu_wrin), 239 | 240 | .planar(vga_planar) 241 | 242 | // ,.hdmi_rp(hdmi_rp), .hdmi_rm(hdmi_rm), .hdmi_gp(hdmi_gp), .hdmi_gm(hdmi_gm), .hdmi_bp(hdmi_bp), .hdmi_bm(hdmi_bm), .hdmi_cp(hdmi_cp), .hdmi_cm(hdmi_cm) 243 | ); 244 | 245 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 246 | // SPI 247 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 248 | wire [7:0] spi_iodout; 249 | wire spi_ready; 250 | wire cpu_rdin_spi; 251 | reg cpu_rdout_spi; 252 | wire cpu_wrin_spi; 253 | reg cpu_wrout_spi; 254 | SPI spi( 255 | .clk(clk), 256 | 257 | .addr(addr_8bit), 258 | .din(data_8bit), 259 | .dout(spi_iodout), 260 | 261 | .cpu_iordin(cpu_rdout_spi), 262 | .cpu_iordout(cpu_rdin_spi), 263 | .cpu_iowrin(cpu_wrout_spi), 264 | .cpu_iowrout(cpu_wrin_spi), 265 | 266 | .ready(spi_ready), 267 | 268 | .cs_n(sd_cs_n), 269 | .miso(sd_miso), 270 | .mosi(sd_mosi), 271 | .sck(sd_sck) 272 | ); 273 | 274 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 275 | // PIT 276 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 277 | wire t1out, t2out; 278 | wire [7:0] pit_iodout; 279 | wire cpu_rdin_pit; 280 | reg cpu_rdout_pit; 281 | wire cpu_wrin_pit; 282 | reg cpu_wrout_pit; 283 | PIT pit( 284 | .clk(clk), 285 | .reset_n(reset_n), 286 | 287 | .port(addr_8bit), 288 | .din(data_8bit), 289 | .dout(pit_iodout), 290 | 291 | .cpu_iordin(cpu_rdout_pit), 292 | .cpu_iordout(cpu_rdin_pit), 293 | .cpu_iowrin(cpu_wrout_pit), 294 | .cpu_iowrout(cpu_wrin_pit), 295 | 296 | .irq0(irq[0]), 297 | .t1out(t1out), 298 | .t2out(t2out) 299 | ); 300 | 301 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 302 | // PIC 303 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 304 | wire [7:0] pic_iodout; 305 | wire cpu_rdin_pic; 306 | reg cpu_rdout_pic; 307 | wire cpu_wrin_pic; 308 | reg cpu_wrout_pic; 309 | wire [7:0] irq_vector; 310 | wire [7:0] irq; 311 | PIC pic( 312 | .clk(clk), 313 | .reset_n(reset_n), 314 | 315 | .port(addr_8bit), 316 | .din(data_8bit), 317 | .dout(pic_iodout), 318 | 319 | .cpu_iordin(cpu_rdout_pic), 320 | .cpu_iordout(cpu_rdin_pic), 321 | .cpu_iowrin(cpu_wrout_pic), 322 | .cpu_iowrout(cpu_wrin_pic), 323 | 324 | .inta(inta), 325 | 326 | .irq_vector(irq_vector), 327 | .intr(cpu_intr), 328 | 329 | .irq0(irq[0]), 330 | .irq1(irq[1]) 331 | ); 332 | 333 | 334 | reg [23:0] div; 335 | reg run; 336 | 337 | // assign cpu_reset = ~run; 338 | 339 | always @(posedge clk or negedge reset_n) 340 | begin 341 | if (~reset_n) 342 | begin 343 | div <= 24'd0; 344 | run <= 1'b0; 345 | end 346 | else 347 | begin 348 | div <= div + 24'd1; 349 | if (div[23]) 350 | run <= 1'b1; 351 | end 352 | end 353 | 354 | 355 | 356 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 357 | // BIOS 358 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 359 | wire [15:0] bios_out; 360 | BIOS bios( 361 | .clock(clk), 362 | .address(c_a[12:1]), 363 | .q(bios_out) 364 | ); 365 | 366 | 367 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 368 | // 16 bit to 8 bit bridge 369 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 370 | 371 | task send_io_request; 372 | if (spi_write) cpu_wrout_spi <= ~cpu_wrout_spi; 373 | if (spi_read) cpu_rdout_spi <= ~cpu_rdout_spi; 374 | if (pit_write) cpu_wrout_pit <= ~cpu_wrout_pit; 375 | if (pit_read) cpu_rdout_pit <= ~cpu_rdout_pit; 376 | if (pic_write) cpu_wrout_pic <= ~cpu_wrout_pic; 377 | if (pic_read) cpu_rdout_pic <= ~cpu_rdout_pic; 378 | if (vga_write) cpu_wrout_vga <= ~cpu_wrout_vga; 379 | if (vga_read) cpu_rdout_vga <= ~cpu_rdout_vga; 380 | if (dbg_write) cpu_wrout_dbg <= ~cpu_wrout_dbg; 381 | if (ps2_write) cpu_wrout_ps2 <= ~cpu_wrout_ps2; 382 | if (ps2_read) cpu_rdout_ps2 <= ~cpu_rdout_ps2; 383 | endtask 384 | 385 | 386 | reg [23:0] addr_8bit; 387 | reg [7:0] data_8bit; 388 | reg [15:0] result_16bit; 389 | reg cycle_phase0; 390 | reg cycle_phase1; 391 | 392 | task process_bridge; 393 | if (io_ready) 394 | begin 395 | if (cycle_phase0) 396 | begin 397 | // Cycle 0 is done -> store lower 8 bit from i/o device's output, 398 | // send higher 8 bit, and advance to a next address 399 | addr_8bit[0] <= 1'b1; 400 | data_8bit <= c_d[15:8]; 401 | 402 | cycle_phase0 <= 1'b0; 403 | result_16bit[7:0] <= io_dout; 404 | 405 | if (cycle_phase1) 406 | send_io_request; 407 | end 408 | else if (cycle_phase1) 409 | begin 410 | cycle_phase1 <= 1'b0; 411 | result_16bit[15:8] <= io_dout; 412 | end 413 | end 414 | endtask 415 | 416 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 417 | // CPU 418 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 419 | reg [1:0] c_s; 420 | 421 | reg [23:0] c_a; 422 | reg c_bhe_n; 423 | reg [15:0] c_d; 424 | 425 | always @(posedge clk) 426 | begin 427 | cpu_d <= 428 | bios_read ? bios_out : 429 | vram_read ? cpu_dout_sram : 430 | ram_read ? cpu_dout_sdram : 431 | spi_read ? result_16bit : 432 | pit_read ? result_16bit : 433 | pic_read ? result_16bit : 434 | vga_read ? result_16bit : 435 | ps2_read ? result_16bit : 436 | inta ? irq_vector : 437 | 16'hZZZZ; 438 | end 439 | 440 | wire [7:0] io_dout = 441 | vga_read ? vga_iodout : 442 | pic_read ? pic_iodout : 443 | pit_read ? pit_iodout : 444 | ps2_read ? ps2_iodout : 445 | spi_iodout; 446 | 447 | always @(posedge div[0]) 448 | begin 449 | cpu_clk_n <= ~cpu_clk_n; 450 | end 451 | 452 | always @(posedge cpu_clk_n) 453 | begin 454 | cpu_reset <= ~run; 455 | end 456 | 457 | // BIOS: 0F0000-0FFFFF, FF0000-FFFFFF 458 | wire bios_area = (&cpu_a[19:16]) && (cpu_a[23:20] == 4'hF || cpu_a[23:20] == 4'h0); 459 | // Video RAM: 0A0000-0BFFFF 460 | wire vram_area = cpu_a[23:17] == 7'b0000101; 461 | // RAM: all but BIOS and Video RAM 462 | wire ram_area = !vram_area; 463 | 464 | // SPI: I/O 0B0-0B2 465 | wire spi_area = cpu_a[11:2] == 10'b0000101100; 466 | // PIT: I/O 040-043 467 | wire pit_area = cpu_a[11:2] == 10'b0000010000; 468 | // PIC: I/O 020-021 469 | wire pic_area = cpu_a[11:1] == 11'b00000010000; 470 | // VGA: I/O 3B0-3DF 471 | wire vga_area = (cpu_a[11:7] == 5'b00111) || (cpu_a[11:0] == 12'h0BE); 472 | // DEBUG UART: I/O 0BC 473 | wire dbg_area = cpu_a[11:0] == 12'hBC; 474 | // PS/2: I/O 060-064 475 | wire ps2_area = cpu_a[11:3] == 9'b000001100; 476 | 477 | // Decoded commands and areas 478 | reg bios_read; 479 | reg vram_read; 480 | reg vram_write; 481 | reg ram_read; 482 | reg ram_write; 483 | reg inta; 484 | 485 | reg spi_read; 486 | reg spi_write; 487 | reg pit_read; 488 | reg pit_write; 489 | reg pic_read; 490 | reg pic_write; 491 | reg vga_read; 492 | reg vga_write; 493 | reg dbg_write; 494 | reg ps2_read; 495 | reg ps2_write; 496 | 497 | reg io_read; 498 | reg io_write; 499 | 500 | // CPU cycle status 501 | wire [3:0] cpu_cmd = {cpu_inta_n, cpu_mio, cpu_s1_n, cpu_s0_n}; 502 | wire mem_read_cycle = cpu_cmd[2:0] == 3'b101; 503 | wire mem_write_cycle = cpu_cmd[2:0] == 3'b110; 504 | wire io_read_cycle = cpu_cmd[2:0] == 3'b001; 505 | wire io_write_cycle = cpu_cmd[2:0] == 3'b010; 506 | wire inta_cycle = cpu_cmd[3:0] == 4'b0000; 507 | 508 | wire io_ready = spi_ready && vga_ready && dbg_ready; 509 | 510 | always @(negedge cpu_clk_n) 511 | begin 512 | cpu_ready <= sdram_ready && sram_ready && io_ready && (!cycle_phase0) && (!cycle_phase1); 513 | 514 | c_s <= {cpu_s1_n, cpu_s0_n}; 515 | 516 | if ((cpu_s1_n == 1'b0) || (cpu_s0_n == 1'b0)) 517 | begin 518 | // The address is now available 519 | c_a <= cpu_a; 520 | c_bhe_n <= cpu_bhe_n; 521 | 522 | addr_8bit <= cpu_a; 523 | 524 | // Decode CPU address and command 525 | bios_read <= bios_area & mem_read_cycle; 526 | vram_read <= vram_area & mem_read_cycle; 527 | vram_write <= vram_area & mem_write_cycle; 528 | ram_read <= ram_area & mem_read_cycle; 529 | ram_write <= ram_area & mem_write_cycle; 530 | inta <= inta_cycle; 531 | 532 | spi_read <= spi_area & io_read_cycle; 533 | spi_write <= spi_area & io_write_cycle; 534 | pit_read <= pit_area & io_read_cycle; 535 | pit_write <= pit_area & io_write_cycle; 536 | pic_read <= pic_area & io_read_cycle; 537 | pic_write <= pic_area & io_write_cycle; 538 | vga_read <= vga_area & io_read_cycle; 539 | vga_write <= vga_area & io_write_cycle; 540 | dbg_write <= dbg_area & io_write_cycle; 541 | ps2_read <= ps2_area & io_read_cycle; 542 | ps2_write <= ps2_area & io_write_cycle; 543 | 544 | io_read <= io_read_cycle; 545 | io_write <= io_write_cycle; 546 | end 547 | else if ((c_s[1] == 1'b0) || (c_s[0] == 1'b0)) 548 | begin 549 | c_d <= cpu_d; 550 | 551 | data_8bit <= addr_8bit[0] ? cpu_d[15:8] : cpu_d[7:0]; 552 | 553 | if (io_read || io_write) 554 | begin 555 | cycle_phase0 <= c_a[0] == 1'b0; 556 | cycle_phase1 <= cpu_bhe_n == 1'b0; 557 | end 558 | 559 | // Execute CPU's command 560 | 561 | if (vram_read) cpu_rdout_sram <= ~cpu_rdout_sram; 562 | if (vram_write) cpu_wrout_sram <= ~cpu_wrout_sram; 563 | if (ram_read) cpu_rdout_sdram <= ~cpu_rdout_sdram; 564 | if (ram_write) cpu_wrout_sdram <= ~cpu_wrout_sdram; 565 | 566 | send_io_request; 567 | end 568 | 569 | process_bridge; 570 | end 571 | 572 | endmodule 573 | -------------------------------------------------------------------------------- /src/Main86.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 00:12:21 January 02, 2023 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Main_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV E" 40 | set_global_assignment -name DEVICE EP4CE15F23C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY Main 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:12:21 JANUARY 02, 2023" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 49 | set_global_assignment -name VERILOG_FILE Main.v 50 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 51 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 52 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 53 | set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V 54 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 55 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 56 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 57 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 58 | set_location_assignment PIN_G1 -to clk 59 | set_location_assignment PIN_T1 -to reset_n 60 | set_location_assignment PIN_B3 -to vga_vsync 61 | set_location_assignment PIN_A3 -to vga_hsync 62 | set_location_assignment PIN_B4 -to vga_r[4] 63 | set_location_assignment PIN_A4 -to vga_r[5] 64 | set_location_assignment PIN_B5 -to vga_r[6] 65 | set_location_assignment PIN_A5 -to vga_r[7] 66 | set_location_assignment PIN_B6 -to vga_g[4] 67 | set_location_assignment PIN_A6 -to vga_g[5] 68 | set_location_assignment PIN_B7 -to vga_g[6] 69 | set_location_assignment PIN_A7 -to vga_g[7] 70 | set_location_assignment PIN_B8 -to vga_b[4] 71 | set_location_assignment PIN_A8 -to vga_b[5] 72 | set_location_assignment PIN_B9 -to vga_b[6] 73 | set_location_assignment PIN_A9 -to vga_b[7] 74 | set_location_assignment PIN_B10 -to usb1_p 75 | set_location_assignment PIN_A10 -to usb1_m 76 | set_location_assignment PIN_E11 -to usb2_p 77 | set_location_assignment PIN_A13 -to usb2_m 78 | set_location_assignment PIN_B13 -to sd_cs_n 79 | set_location_assignment PIN_A14 -to sd_mosi 80 | set_location_assignment PIN_B14 -to sd_sck 81 | set_location_assignment PIN_A15 -to sd_miso 82 | set_location_assignment PIN_B15 -to audio_left 83 | set_location_assignment PIN_A16 -to audio_right 84 | set_location_assignment PIN_B16 -to cpu_d10 85 | set_location_assignment PIN_A17 -to cpu_d11 86 | set_location_assignment PIN_B17 -to cpu_d12 87 | set_location_assignment PIN_A18 -to cpu_d15 88 | set_location_assignment PIN_B18 -to cpu_d13 89 | set_location_assignment PIN_A19 -to cpu_d14_ad15_a9 90 | set_location_assignment PIN_B19 -to cpu_intr_a16_a8 91 | set_location_assignment PIN_A20 -to cpu_x_a17_a7 92 | set_location_assignment PIN_B20 -to cpu_clk 93 | set_location_assignment PIN_C17 -to cpu_nmi 94 | set_location_assignment PIN_B21 -to cpu_bhe_x_a11 95 | set_location_assignment PIN_B22 -to cpu_error_a18_a6 96 | set_location_assignment PIN_C21 -to cpu_inta_ad14_a12 97 | set_location_assignment PIN_C22 -to cpu_mio_ad13_a13 98 | 99 | set_location_assignment PIN_D21 -to cpu_d7_a19_a5 100 | set_location_assignment PIN_D22 -to cpu_hold_ad12_a14 101 | set_location_assignment PIN_E21 -to cpu_hlda_ad11_a15 102 | set_location_assignment PIN_E22 -to cpu_s1_ad10_x 103 | set_location_assignment PIN_F21 -to cpu_s0_ad9_d4 104 | set_location_assignment PIN_F22 -to cpu_d5_x_a3 105 | set_location_assignment PIN_F20 -to cpu_d6_bhe_a4 106 | set_location_assignment PIN_H21 -to cpu_a23 107 | set_location_assignment PIN_H22 -to cpu_a21_ad7_d5 108 | set_location_assignment PIN_J21 -to cpu_a22_ad8_d3 109 | set_location_assignment PIN_J22 -to cpu_d4_rd_a2 110 | set_location_assignment PIN_K21 -to cpu_a19_ad6_d6 111 | set_location_assignment PIN_L21 -to cpu_a20 112 | set_location_assignment PIN_M20 -to cpu_d3_hold_a1 113 | set_location_assignment PIN_M22 -to cpu_a17_ad5_x 114 | set_location_assignment PIN_M21 -to cpu_a18 115 | 116 | set_location_assignment PIN_N20 -to cpu_a15_ad4_d2 117 | set_location_assignment PIN_P22 -to cpu_d2_hlda_a0 118 | set_location_assignment PIN_P21 -to cpu_a16 119 | set_location_assignment PIN_T18 -to cpu_a6 120 | set_location_assignment PIN_U22 -to cpu_a14 121 | set_location_assignment PIN_U21 -to cpu_a12 122 | set_location_assignment PIN_V22 -to cpu_a10 123 | set_location_assignment PIN_V21 -to cpu_a13 124 | set_location_assignment PIN_W22 -to cpu_a4 125 | set_location_assignment PIN_W21 -to cpu_a7 126 | set_location_assignment PIN_Y22 -to cpu_a8_ad3_d7 127 | set_location_assignment PIN_Y21 -to cpu_a11_reset_rd 128 | set_location_assignment PIN_AA21 -to cpu_a9_ad2_d0 129 | set_location_assignment PIN_AA20 -to cpu_a5_ad1_d1 130 | set_location_assignment PIN_AB20 -to cpu_d8_den_reset 131 | set_location_assignment PIN_AA19 -to cpu_reset_ad0_int 132 | set_location_assignment PIN_AB19 -to cpu_d9_ale_busrq 133 | set_location_assignment PIN_AA18 -to cpu_a0_inta_wait 134 | set_location_assignment PIN_AB18 -to cpu_a3_intr_halt 135 | 136 | set_location_assignment PIN_J18 -to cpu_a1_x_mreq 137 | set_location_assignment PIN_K18 -to cpu_d0_readymio_wrrfsh 138 | set_location_assignment PIN_K17 -to cpu_a2_x_iorq 139 | set_location_assignment PIN_M19 -to cpu_d1_wr_x 140 | 141 | set_location_assignment PIN_N17 -to flop_change_n 142 | set_location_assignment PIN_P17 -to flop_wprot_n 143 | set_location_assignment PIN_N18 -to flop_trk0_n 144 | set_location_assignment PIN_N19 -to flop_index_n 145 | 146 | set_location_assignment PIN_R18 -to intf_irq 147 | 148 | set_location_assignment PIN_R20 -to uart_rxd 149 | set_location_assignment PIN_R19 -to uart_txd 150 | -------------------------------------------------------------------------------- /src/PIC.v: -------------------------------------------------------------------------------- 1 | module PIC( 2 | input wire clk, 3 | input wire reset_n, 4 | 5 | input wire [11:0] port, 6 | input wire [15:0] din, 7 | output reg [15:0] dout, 8 | 9 | input wire cpu_iordin, 10 | output reg cpu_iordout, 11 | input wire cpu_iowrin, 12 | output reg cpu_iowrout, 13 | 14 | input wire inta, 15 | 16 | output reg [7:0] irq_vector, 17 | output wire intr, 18 | 19 | input wire irq0, 20 | input wire irq1 21 | ); 22 | 23 | // Здесь IRQ0 срабатывает по фронту, а IRQ1 по высокому уровню 24 | 25 | reg irq0_toggle; 26 | 27 | reg irq_enable; 28 | 29 | wire irq = |irq_vector; 30 | 31 | assign intr = irq & irq_enable; 32 | 33 | wire iord = cpu_iordout ^ cpu_iordin; 34 | wire iowr = cpu_iowrout ^ cpu_iowrin; 35 | 36 | wire cs_20h = port == 12'h020; 37 | 38 | always @(posedge clk) 39 | begin 40 | cpu_iordout <= cpu_iordin; 41 | cpu_iowrout <= cpu_iowrin; 42 | 43 | irq_enable <= (~reset_n) | inta ? 1'b0 : iowr && cs_20h ? 1'b1 : irq_enable; 44 | 45 | irq_vector <= (~reset_n) || (iowr && cs_20h) ? 8'd0 : 46 | |irq_vector ? irq_vector : irq0 ^ irq0_toggle ? 8'd8 : irq1 ? 8'd9 : 8'd0; 47 | 48 | irq0_toggle <= (irq0 ^ irq0_toggle) && (irq_vector == 8'd8) ? ~irq0_toggle : irq0_toggle; 49 | 50 | dout <= 16'hFFFF; 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /src/PIT.v: -------------------------------------------------------------------------------- 1 | module PIT( 2 | input wire clk, 3 | input wire reset_n, 4 | 5 | input wire [11:0] port, 6 | input wire [7:0] din, 7 | output reg [7:0] dout, 8 | input wire cpu_iordin, 9 | output reg cpu_iordout, 10 | input wire cpu_iowrin, 11 | output reg cpu_iowrout, 12 | 13 | output reg irq0, 14 | 15 | output reg t1out, 16 | output reg t2out 17 | ); 18 | 19 | localparam 20 | PRESCALER = 7'd42; 21 | 22 | reg cs_40h; 23 | reg cs_41h; 24 | reg cs_42h; 25 | reg cs_43h; 26 | 27 | reg [6:0] div; 28 | 29 | 30 | reg [6:0] control1; 31 | reg [6:0] control2; 32 | reg [6:0] control3; 33 | reg [15:0] preset1; 34 | reg [15:0] preset2; 35 | reg [15:0] preset3; 36 | reg [15:0] value1; 37 | reg [15:0] value2; 38 | reg [15:0] value3; 39 | reg [15:0] latch1; 40 | reg [15:0] latch2; 41 | reg [15:0] latch3; 42 | 43 | wire iord = cpu_iordout ^ cpu_iordin; 44 | wire iowr = cpu_iowrout ^ cpu_iowrin; 45 | 46 | 47 | always @(negedge clk) 48 | begin 49 | cs_40h <= port == 12'h040; 50 | cs_41h <= port == 12'h041; 51 | cs_42h <= port == 12'h042; 52 | cs_43h <= port == 12'h043; 53 | end 54 | 55 | always @(posedge clk) 56 | begin 57 | cpu_iordout <= cpu_iordin; 58 | cpu_iowrout <= cpu_iowrin; 59 | 60 | control1 <= ~reset_n ? 7'd0 : iowr && cs_43h && (din[7:6] == 2'd0) ? {1'b0, din[5:0]} : 61 | (iowr || iord) && cs_40h && (~(control1[5] ^ control1[4])) ? {~control1[6], control1[5:0]} : control1; 62 | control2 <= ~reset_n ? 7'd0 : iowr && cs_43h && (din[7:6] == 2'd1) ? {1'b0, din[5:0]} : 63 | (iowr || iord) && cs_41h && (~(control2[5] ^ control2[4])) ? {~control2[6], control2[5:0]} : control2; 64 | control3 <= ~reset_n ? 7'd0 : iowr && cs_43h && (din[7:6] == 2'd2) ? {1'b0, din[5:0]} : 65 | (iowr || iord) && cs_42h && (~(control3[5] ^ control3[4])) ? {~control3[6], control3[5:0]} : control3; 66 | 67 | preset1 <= ~reset_n ? 16'hFFFF : iowr && cs_40h && (&control1[5:4]) ? {control1[6] ? din : preset1[15:8], ~control1[6] ? din : preset1[7:0]} : 68 | iowr && cs_40h && (^control1[5:4]) ? {control1[5] ? din : preset1[15:8], control1[4] ? din : preset1[7:0]} : preset1; 69 | preset2 <= ~reset_n ? 16'h0012 : iowr && cs_41h && (&control2[5:4]) ? {control2[6] ? din : preset2[15:8], ~control2[6] ? din : preset2[7:0]} : 70 | iowr && cs_41h && (^control2[5:4]) ? {control2[5] ? din : preset2[15:8], control2[4] ? din : preset2[7:0]} : preset2; 71 | preset3 <= ~reset_n ? 16'hFFFF : iowr && cs_42h && (&control3[5:4]) ? {control3[6] ? din : preset3[15:8], ~control3[6] ? din : preset3[7:0]} : 72 | iowr && cs_42h && (^control3[5:4]) ? {control3[5] ? din : preset3[15:8], control3[4] ? din : preset3[7:0]} : preset3; 73 | 74 | value1 <= div == PRESCALER ? (|value1 ? value1 - 16'd1 : (|preset1 ? preset1 : 16'hFFFF)) : value1; 75 | value2 <= div == PRESCALER ? (|value2 ? value2 - 16'd1 : (|preset2 ? preset2 : 16'hFFFF)) : value2; 76 | value3 <= div == PRESCALER ? (|value3 ? value3 - 16'd1 : (|(preset3 >> 1) ? preset3 : 16'hFFFF)) : value3; 77 | 78 | div <= div == PRESCALER ? 7'd0 : div + 7'd1; 79 | 80 | irq0 <= (div == PRESCALER) && (value1 == 16'd0) ? ~irq0 : irq0; 81 | 82 | t1out <= (div == PRESCALER) && (value2 == 16'd0) ? ~t1out : t1out; 83 | 84 | t2out <= (div == PRESCALER) && (value3 == 16'd0) ? ~t2out : t2out; 85 | 86 | dout <= 87 | cs_40h && ((~control1[5]) || (control1[5] & (~control1[6]))) ? value1[7:0] : 88 | cs_40h && (((~control1[4]) && control1[5]) || (control1[5] & (control1[6]))) ? value1[15:8] : 89 | cs_41h && ((~control2[5]) || (control2[5] & (~control2[6]))) ? value2[7:0] : 90 | cs_41h && (((~control2[4]) && control2[5]) || (control2[5] & (control2[6]))) ? value2[15:8] : 91 | cs_42h && ((~control3[5]) || (control3[5] & (~control3[6]))) ? value3[7:0] : 92 | cs_42h && (((~control3[4]) && control3[5]) || (control3[5] & (control3[6]))) ? value3[15:8] : 93 | 8'hFF; 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /src/PLL1.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /src/PLL1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL1.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL1_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL1.ppf"] 6 | -------------------------------------------------------------------------------- /src/PLL1_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: PLL1.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module PLL1 ( 35 | inclk0, 36 | c0, 37 | c1, 38 | c2, 39 | c3, 40 | c4); 41 | 42 | input inclk0; 43 | output c0; 44 | output c1; 45 | output c2; 46 | output c3; 47 | output c4; 48 | 49 | endmodule 50 | 51 | // ============================================================ 52 | // CNX file retrieval info 53 | // ============================================================ 54 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 55 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 56 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 57 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 58 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 59 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 60 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 61 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 62 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 63 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 64 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 65 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 66 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 67 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 68 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 69 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" 70 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 71 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 72 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 73 | // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "2" 74 | // Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "333" 75 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 76 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 77 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 78 | // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" 79 | // Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" 80 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" 81 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000" 82 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000" 83 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000" 84 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "1.501502" 85 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 86 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 87 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 88 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 89 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 90 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 91 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 92 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 93 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 94 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 95 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 96 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 97 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 98 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 99 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 100 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 101 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 102 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 103 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 104 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 105 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 106 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" 107 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" 108 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" 109 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 110 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 111 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 112 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 113 | // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" 114 | // Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" 115 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 116 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5" 117 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" 118 | // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" 119 | // Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "10" 120 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 121 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" 122 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000" 123 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "75.00000000" 124 | // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000" 125 | // Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "3.00000000" 126 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" 127 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" 128 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" 129 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" 130 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" 131 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 132 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 133 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 134 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" 135 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" 136 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 137 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 138 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "8.00000000" 139 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 140 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" 141 | // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-2.00000000" 142 | // Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" 143 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 144 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" 145 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" 146 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns" 147 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns" 148 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps" 149 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 150 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 151 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 152 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 153 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 154 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 155 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 156 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 157 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 158 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 159 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL1.mif" 160 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 161 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 162 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 163 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 164 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 165 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 166 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 167 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 168 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 169 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 170 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 171 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 172 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 173 | // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" 174 | // Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" 175 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 176 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 177 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 178 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 179 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 180 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 181 | // Retrieval info: PRIVATE: USE_CLK3 STRING "1" 182 | // Retrieval info: PRIVATE: USE_CLK4 STRING "1" 183 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 184 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 185 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 186 | // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" 187 | // Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" 188 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 189 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 190 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 191 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 192 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 193 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 194 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" 195 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "8000" 196 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" 197 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 198 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" 199 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 200 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" 201 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 202 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" 203 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" 204 | // Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2" 205 | // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" 206 | // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" 207 | // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-2000" 208 | // Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "333" 209 | // Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" 210 | // Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "10" 211 | // Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" 212 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 213 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 214 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 215 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 216 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 217 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 218 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 219 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 220 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 221 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 222 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 223 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 224 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 225 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 226 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 227 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 228 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 229 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 230 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 231 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 232 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 233 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 234 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 235 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 236 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 237 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 238 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 239 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 240 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 241 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 242 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 243 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 244 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 245 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 246 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" 247 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" 248 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 249 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 250 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 251 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 252 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 253 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 254 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 255 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 256 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 257 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 258 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 259 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 260 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 261 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 262 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 263 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 264 | // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" 265 | // Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" 266 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 267 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 268 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 269 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 270 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 271 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 272 | // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 273 | // Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 274 | // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.v TRUE 275 | // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.ppf TRUE 276 | // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.inc FALSE 277 | // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.cmp FALSE 278 | // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.bsf FALSE 279 | // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_inst.v FALSE 280 | // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_bb.v TRUE 281 | // Retrieval info: LIB_FILE: altera_mf 282 | // Retrieval info: CBX_MODULE_PREFIX: ON 283 | -------------------------------------------------------------------------------- /src/PLLJ_PLLSPE_INFO.txt: -------------------------------------------------------------------------------- 1 | PLL_Name PLL1:pll1|altpll:altpll_component|PLL1_altpll:auto_generated|pll1 2 | PLLJITTER 35 3 | PLLSPEmax 84 4 | PLLSPEmin -53 5 | 6 | -------------------------------------------------------------------------------- /src/PS2.v: -------------------------------------------------------------------------------- 1 | module PS2( 2 | input wire clk, 3 | input wire reset_n, 4 | 5 | output reg led, 6 | 7 | inout wire dm, 8 | inout wire dp, 9 | 10 | input wire [11:0] port, 11 | output reg [7:0] dout, 12 | input wire [7:0] din, 13 | input wire cpu_iordin, 14 | output reg cpu_iordout, 15 | input wire cpu_iowrin, 16 | output reg cpu_iowrout, 17 | 18 | output reg [7:0] keycode, 19 | output reg irq1 20 | ); 21 | 22 | wire noled; 23 | wire [7:0] shift; 24 | wire [7:0] keycode1; 25 | wire [7:0] keycode2; 26 | wire [7:0] keycode3; 27 | reg [7:0] prev_shift; 28 | reg [7:0] prev_keycode1; 29 | reg [7:0] prev_keycode2; 30 | reg [7:0] prev_keycode3; 31 | USB_LS_HID ls_hid( 32 | .clk(clk), 33 | .reset_n(reset_n), 34 | 35 | .led(noled), 36 | 37 | .shift(shift), 38 | .keycode1(keycode1), 39 | .keycode2(keycode2), 40 | .keycode3(keycode3), 41 | 42 | .dm(dm), 43 | .dp(dp) 44 | ); 45 | 46 | wire iord = cpu_iordout ^ cpu_iordin; 47 | wire iowr = cpu_iowrout ^ cpu_iowrin; 48 | 49 | reg cs_60h; 50 | reg cs_61h; 51 | 52 | reg [24:0] div; 53 | 54 | reg [19:0] div2; 55 | 56 | wire [7:0] code1; 57 | keyboard rom 58 | ( 59 | .clock(~clk), 60 | .address(keycode1 | prev_keycode1), 61 | .q(code1) 62 | ); 63 | 64 | always @(negedge clk) 65 | begin 66 | cs_60h <= port == 12'h060; 67 | cs_61h <= port == 12'h061; 68 | end 69 | 70 | reg press1; 71 | reg release1; 72 | 73 | always @(posedge clk) 74 | begin 75 | cpu_iordout <= cpu_iordin; 76 | cpu_iowrout <= cpu_iowrin; 77 | 78 | dout <= keycode; 79 | 80 | //led <= noled; 81 | 82 | if (div2[19:12] == keycode1) 83 | begin 84 | div2 <= 20'd0; 85 | led <= ~led; 86 | end 87 | else 88 | begin 89 | div2 <= div2 + 1'd1; 90 | end 91 | 92 | // irq1 <= div < 7'd30; 93 | 94 | if (cs_61h && iowr) 95 | begin 96 | irq1 <= 1'b0; 97 | end 98 | 99 | div <= div[24] ? 25'd0 : div + 1'd1; 100 | 101 | prev_shift <= shift; 102 | prev_keycode1 <= keycode1; 103 | prev_keycode2 <= keycode2; 104 | prev_keycode3 <= keycode3; 105 | 106 | press1 <= prev_keycode1 == 8'd0 && keycode1 != 8'd0; 107 | release1 <= prev_keycode1 != 8'd0 && keycode1 == 8'd0; 108 | 109 | if (press1) 110 | begin 111 | keycode <= code1; 112 | if (|code1) 113 | irq1 <= 1'b1; 114 | end 115 | else if (release1) 116 | begin 117 | keycode <= code1 | 8'h80; 118 | if (code1) 119 | irq1 <= 1'b1; 120 | end 121 | end 122 | 123 | endmodule 124 | -------------------------------------------------------------------------------- /src/Palette.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Palette.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Palette_bb.v"] 5 | -------------------------------------------------------------------------------- /src/Palette.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: Palette.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module Palette ( 40 | address_a, 41 | address_b, 42 | clock, 43 | data_a, 44 | data_b, 45 | wren_a, 46 | wren_b, 47 | q_a, 48 | q_b); 49 | 50 | input [7:0] address_a; 51 | input [7:0] address_b; 52 | input clock; 53 | input [17:0] data_a; 54 | input [17:0] data_b; 55 | input wren_a; 56 | input wren_b; 57 | output [17:0] q_a; 58 | output [17:0] q_b; 59 | `ifndef ALTERA_RESERVED_QIS 60 | // synopsys translate_off 61 | `endif 62 | tri1 clock; 63 | tri0 wren_a; 64 | tri0 wren_b; 65 | `ifndef ALTERA_RESERVED_QIS 66 | // synopsys translate_on 67 | `endif 68 | 69 | wire [17:0] sub_wire0; 70 | wire [17:0] sub_wire1; 71 | wire [17:0] q_a = sub_wire0[17:0]; 72 | wire [17:0] q_b = sub_wire1[17:0]; 73 | 74 | altsyncram altsyncram_component ( 75 | .clock0 (clock), 76 | .wren_a (wren_a), 77 | .address_b (address_b), 78 | .data_b (data_b), 79 | .wren_b (wren_b), 80 | .address_a (address_a), 81 | .data_a (data_a), 82 | .q_a (sub_wire0), 83 | .q_b (sub_wire1), 84 | .aclr0 (1'b0), 85 | .aclr1 (1'b0), 86 | .addressstall_a (1'b0), 87 | .addressstall_b (1'b0), 88 | .byteena_a (1'b1), 89 | .byteena_b (1'b1), 90 | .clock1 (1'b1), 91 | .clocken0 (1'b1), 92 | .clocken1 (1'b1), 93 | .clocken2 (1'b1), 94 | .clocken3 (1'b1), 95 | .eccstatus (), 96 | .rden_a (1'b1), 97 | .rden_b (1'b1)); 98 | defparam 99 | altsyncram_component.address_reg_b = "CLOCK0", 100 | altsyncram_component.clock_enable_input_a = "BYPASS", 101 | altsyncram_component.clock_enable_input_b = "BYPASS", 102 | altsyncram_component.clock_enable_output_a = "BYPASS", 103 | altsyncram_component.clock_enable_output_b = "BYPASS", 104 | altsyncram_component.indata_reg_b = "CLOCK0", 105 | altsyncram_component.intended_device_family = "Cyclone IV E", 106 | altsyncram_component.lpm_type = "altsyncram", 107 | altsyncram_component.numwords_a = 256, 108 | altsyncram_component.numwords_b = 256, 109 | altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", 110 | altsyncram_component.outdata_aclr_a = "NONE", 111 | altsyncram_component.outdata_aclr_b = "NONE", 112 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 113 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 114 | altsyncram_component.power_up_uninitialized = "FALSE", 115 | altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", 116 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 117 | altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", 118 | altsyncram_component.widthad_a = 8, 119 | altsyncram_component.widthad_b = 8, 120 | altsyncram_component.width_a = 18, 121 | altsyncram_component.width_b = 18, 122 | altsyncram_component.width_byteena_a = 1, 123 | altsyncram_component.width_byteena_b = 1, 124 | altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; 125 | 126 | 127 | endmodule 128 | 129 | // ============================================================ 130 | // CNX file retrieval info 131 | // ============================================================ 132 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 133 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 134 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 135 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 136 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 137 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 138 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" 139 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 140 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 141 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 142 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 143 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 144 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 145 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 146 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 147 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 148 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 149 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 150 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 151 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 152 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 153 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 154 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 155 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 156 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 157 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 158 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 159 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 160 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 161 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 162 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "4608" 163 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 164 | // Retrieval info: PRIVATE: MIFfilename STRING "" 165 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 166 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 167 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 168 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 169 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 170 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 171 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 172 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 173 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 174 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 175 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 176 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 177 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 178 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 179 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 180 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 181 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 182 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18" 183 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18" 184 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18" 185 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18" 186 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 187 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 188 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 189 | // Retrieval info: PRIVATE: enable NUMERIC "0" 190 | // Retrieval info: PRIVATE: rden NUMERIC "0" 191 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 192 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 193 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 194 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 195 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 196 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 197 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 198 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 199 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 200 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 201 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" 202 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 203 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 204 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 205 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 206 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 207 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 208 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 209 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 210 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 211 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 212 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" 213 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" 214 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "18" 215 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 216 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 217 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 218 | // Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]" 219 | // Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]" 220 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 221 | // Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]" 222 | // Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]" 223 | // Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]" 224 | // Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]" 225 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 226 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 227 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 228 | // Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 229 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 230 | // Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0 231 | // Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0 232 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 233 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 234 | // Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0 235 | // Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0 236 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.v TRUE 237 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.inc FALSE 238 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.cmp FALSE 239 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.bsf FALSE 240 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette_inst.v FALSE 241 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette_bb.v TRUE 242 | // Retrieval info: LIB_FILE: altera_mf 243 | -------------------------------------------------------------------------------- /src/Palette_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: Palette.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module Palette ( 35 | address_a, 36 | address_b, 37 | clock, 38 | data_a, 39 | data_b, 40 | wren_a, 41 | wren_b, 42 | q_a, 43 | q_b); 44 | 45 | input [7:0] address_a; 46 | input [7:0] address_b; 47 | input clock; 48 | input [17:0] data_a; 49 | input [17:0] data_b; 50 | input wren_a; 51 | input wren_b; 52 | output [17:0] q_a; 53 | output [17:0] q_b; 54 | `ifndef ALTERA_RESERVED_QIS 55 | // synopsys translate_off 56 | `endif 57 | tri1 clock; 58 | tri0 wren_a; 59 | tri0 wren_b; 60 | `ifndef ALTERA_RESERVED_QIS 61 | // synopsys translate_on 62 | `endif 63 | 64 | endmodule 65 | 66 | // ============================================================ 67 | // CNX file retrieval info 68 | // ============================================================ 69 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 70 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 71 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 72 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 73 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 74 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 75 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" 76 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 77 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 78 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 79 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 80 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 81 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 82 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 83 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 84 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 85 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 86 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 87 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 88 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 90 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 91 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 92 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 93 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 94 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 95 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 96 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 97 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 98 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 99 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "4608" 100 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 101 | // Retrieval info: PRIVATE: MIFfilename STRING "" 102 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 103 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 104 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 105 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 106 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 107 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 108 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 109 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 110 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 111 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 112 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 113 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 114 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 115 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 116 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 117 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 118 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 119 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18" 120 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18" 121 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18" 122 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18" 123 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 124 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 125 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 126 | // Retrieval info: PRIVATE: enable NUMERIC "0" 127 | // Retrieval info: PRIVATE: rden NUMERIC "0" 128 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 129 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 130 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 131 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 132 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 133 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 134 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 135 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 136 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 137 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 138 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" 139 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 140 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 141 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 142 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 144 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 145 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 146 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 147 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 148 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 149 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" 150 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" 151 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "18" 152 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 153 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 154 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 155 | // Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]" 156 | // Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]" 157 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 158 | // Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]" 159 | // Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]" 160 | // Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]" 161 | // Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]" 162 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 163 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 164 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 165 | // Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 166 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 167 | // Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0 168 | // Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0 169 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 170 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 171 | // Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0 172 | // Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.v TRUE 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.inc FALSE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.cmp FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette.bsf FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette_inst.v FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL Palette_bb.v TRUE 179 | // Retrieval info: LIB_FILE: altera_mf 180 | -------------------------------------------------------------------------------- /src/SDRAM.v: -------------------------------------------------------------------------------- 1 | module SDRAM( 2 | input wire clk, 3 | input wire clk1, 4 | input wire reset_n, 5 | 6 | output wire ready, 7 | output wire cpu_addr_hit, 8 | 9 | input wire [23:0] cpu_addr, 10 | input wire cpu_bhe_n, 11 | input wire [15:0] cpu_din, 12 | output wire [15:0] cpu_dout, 13 | input wire cpu_rdin, 14 | output reg cpu_rdout, 15 | input wire cpu_wrin, 16 | output reg cpu_wrout, 17 | 18 | output reg [12:0] a, 19 | output reg [1:0] ba, 20 | output reg [1:0] dqm, 21 | inout wire [15:0] d, 22 | output wire ras_n, 23 | output wire cas_n, 24 | output wire we_n, 25 | output wire cs_n, 26 | output wire sclk, 27 | output reg scke 28 | ); 29 | 30 | assign d = 31 | state == S_WRITE_CPU ? cpu_din : 32 | 16'hZZZZ; 33 | 34 | reg [23:2] cpu_data_addr; 35 | reg [31:0] cpu_data; 36 | reg cpu_data_valid; 37 | 38 | assign cpu_dout = 39 | cpu_addr[1] == 1'b0 ? cpu_data[15:0] : 40 | cpu_data[31:16]; 41 | 42 | assign cpu_addr_hit = (cpu_data_addr == cpu_addr[23:2]) && cpu_data_valid; 43 | 44 | reg [19:0] start; 45 | reg start1, start2, start3; 46 | always @(posedge clk or negedge reset_n) 47 | begin 48 | if (~reset_n) 49 | start <= 20'd0; 50 | else 51 | start <= start[19] ? start : start + 20'd1; 52 | end 53 | always @(posedge clk) 54 | begin 55 | start3 = start[19]; 56 | start2 = |start[19:18]; 57 | start1 = |start[19:17]; 58 | end 59 | 60 | localparam S_START = 0; 61 | localparam S_IDLE = 1; 62 | localparam S_PRECHARGE = 2; 63 | localparam S_LOADMODE = 3; 64 | localparam S_READ_CPU = 4; 65 | localparam S_READ_CPU_1 = 5; 66 | localparam S_READ_CPU_2 = 6; 67 | localparam S_READ_CPU_3 = 7; 68 | localparam S_WRITE_CPU = 8; 69 | localparam S_WRITE_CPU_1 = 9; 70 | localparam S_WRITE_CPU_2 = 10; 71 | localparam S_REFRESH = 11; 72 | localparam S_REFRESH_1 = 12; 73 | localparam S_REFRESH_2 = 13; 74 | localparam S_REFRESH_3 = 14; 75 | localparam S_REFRESH_DONE = 15; 76 | 77 | // SRCW 78 | localparam NOP = 4'b0000; 79 | localparam PRECHARGE = 4'b1101; 80 | localparam REFRESH = 4'b1110; 81 | localparam LOADMODE = 4'b1111; 82 | localparam ACTIVE = 4'b1100; 83 | localparam READ = 4'b1010; 84 | localparam WRITE = 4'b1011; 85 | 86 | reg [4:0] state; 87 | 88 | reg [9:0] refresh; 89 | 90 | reg [3:0] cmd; 91 | 92 | assign sclk = clk1; 93 | 94 | assign cs_n = ~cmd[3]; 95 | assign ras_n = ~cmd[2]; 96 | assign cas_n = ~cmd[1]; 97 | assign we_n = ~cmd[0]; 98 | 99 | reg [13:0] row; 100 | reg row_active; 101 | 102 | assign ready = (cpu_rdin == cpu_rdout) && (cpu_wrin == cpu_wrout); 103 | 104 | always @(posedge clk) 105 | begin 106 | scke <= start1; 107 | 108 | refresh <= state == S_REFRESH ? 10'd0 : refresh + 10'd1; 109 | end 110 | 111 | always @(posedge clk or negedge reset_n) 112 | begin 113 | if (~reset_n) 114 | begin 115 | state <= S_START; 116 | end 117 | else 118 | begin 119 | case (state) 120 | S_START: 121 | begin 122 | cmd <= NOP; 123 | ba <= 2'b00; 124 | if (start2) 125 | state <= S_IDLE; 126 | cpu_data_valid <= 1'b0; 127 | row_active <= 1'b0; 128 | end 129 | S_IDLE: 130 | begin 131 | if (~start3) 132 | begin 133 | end 134 | else if (refresh[8]) 135 | begin 136 | cmd <= PRECHARGE; 137 | a <= 13'h400; 138 | ba <= 2'b00; 139 | row_active <= 1'b0; 140 | state <= S_REFRESH; 141 | end 142 | else if (cpu_rdin ^ cpu_rdout) 143 | begin 144 | dqm <= 2'b00; 145 | if (row_active) 146 | begin 147 | if (row == cpu_addr[23:10]) 148 | begin 149 | state <= S_READ_CPU; 150 | end 151 | else 152 | begin 153 | cmd <= PRECHARGE; 154 | a <= 13'h400; 155 | ba <= 2'b00; 156 | row_active <= 1'b0; 157 | end 158 | end 159 | else 160 | begin 161 | cmd <= ACTIVE; 162 | a <= cpu_addr[21:10]; 163 | ba <= cpu_addr[23:22]; 164 | row <= cpu_addr[23:10]; 165 | row_active <= 1'b1; 166 | state <= S_READ_CPU; 167 | end 168 | end 169 | else if (cpu_wrin ^ cpu_wrout) 170 | begin 171 | dqm[0] <= cpu_addr[0]; 172 | dqm[1] <= cpu_bhe_n; 173 | if (row_active) 174 | begin 175 | if (row == cpu_addr[23:10]) 176 | begin 177 | state <= S_WRITE_CPU; 178 | end 179 | else 180 | begin 181 | cmd <= PRECHARGE; 182 | a <= 13'h400; 183 | ba <= 2'b00; 184 | row_active <= 1'b0; 185 | end 186 | end 187 | else 188 | begin 189 | cmd <= ACTIVE; 190 | a <= cpu_addr[21:10]; 191 | ba <= cpu_addr[23:22]; 192 | row <= cpu_addr[23:10]; 193 | row_active <= 1'b1; 194 | state <= S_WRITE_CPU; 195 | end 196 | end 197 | end 198 | S_REFRESH: 199 | begin 200 | cmd <= REFRESH; 201 | state <= S_REFRESH_1; 202 | end 203 | S_REFRESH_1: 204 | begin 205 | cmd <= NOP; 206 | state <= S_REFRESH_2; 207 | end 208 | S_REFRESH_2: 209 | state <= S_REFRESH_3; 210 | S_REFRESH_3: 211 | state <= S_REFRESH_DONE; 212 | S_REFRESH_DONE: 213 | begin 214 | cmd <= LOADMODE; 215 | a <= 13'h220; 216 | ba <= 2'b00; 217 | state <= S_LOADMODE; 218 | end 219 | S_LOADMODE: 220 | begin 221 | cmd <= NOP; 222 | state <= S_IDLE; 223 | end 224 | S_READ_CPU: 225 | begin 226 | cmd <= READ; 227 | a <= {4'b00, cpu_addr[9:2], 1'b0}; 228 | ba <= cpu_addr[23:22]; 229 | state <= S_READ_CPU_1; 230 | end 231 | S_READ_CPU_1: 232 | begin 233 | a <= {4'b00, cpu_addr[9:2], 1'b1}; 234 | state <= S_READ_CPU_2; 235 | end 236 | S_READ_CPU_2: 237 | begin 238 | cmd <= NOP; 239 | cpu_data[15:0] <= d[15:0]; 240 | state <= S_READ_CPU_3; 241 | end 242 | S_READ_CPU_3: 243 | begin 244 | cpu_data_addr <= cpu_addr[23:2]; 245 | cpu_data[31:16] <= d[15:0]; 246 | cpu_data_valid <= 1'b1; 247 | cpu_rdout <= ~cpu_rdout; 248 | state <= S_IDLE; 249 | end 250 | S_WRITE_CPU: 251 | begin 252 | if (cpu_addr[23:2] == cpu_data_addr) 253 | begin 254 | cpu_data[7:0] <= (cpu_addr[1] == 1'b0) && (cpu_addr[0] == 1'b0) ? cpu_din[7:0] : cpu_data[7:0]; 255 | cpu_data[15:8] <= (cpu_addr[1] == 1'b0) && (cpu_bhe_n == 1'b0) ? cpu_din[15:8] : cpu_data[15:8]; 256 | cpu_data[23:16] <= (cpu_addr[1] == 1'b1) && (cpu_addr[0] == 1'b0) ? cpu_din[7:0] : cpu_data[23:16]; 257 | cpu_data[31:24] <= (cpu_addr[1] == 1'b1) && (cpu_bhe_n == 1'b0) ? cpu_din[15:8] : cpu_data[31:24]; 258 | end 259 | cmd <= WRITE; 260 | a <= {4'b00, cpu_addr[9:1]}; 261 | state <= S_WRITE_CPU_1; 262 | end 263 | S_WRITE_CPU_1: 264 | begin 265 | cmd <= NOP; 266 | dqm <= 2'b00; 267 | cpu_wrout <= ~cpu_wrout; 268 | state <= S_IDLE; 269 | end 270 | default: 271 | state <= S_START; 272 | endcase 273 | end 274 | end 275 | 276 | endmodule 277 | -------------------------------------------------------------------------------- /src/SPI.v: -------------------------------------------------------------------------------- 1 | module SPI( 2 | input wire clk, 3 | 4 | input wire [11:0] addr, 5 | input wire [7:0] din, 6 | output wire [7:0] dout, 7 | input wire cpu_iordin, 8 | output reg cpu_iordout, 9 | input wire cpu_iowrin, 10 | output reg cpu_iowrout, 11 | 12 | output reg ready, 13 | 14 | output wire cs_n, 15 | input wire miso, 16 | output wire mosi, 17 | output wire sck 18 | ); 19 | 20 | reg cs; 21 | 22 | reg [7:0] div; 23 | reg [7:0] preset; 24 | 25 | reg [7:0] sin; 26 | reg [7:0] sout; 27 | reg [3:0] bits; 28 | 29 | reg [15:0] shift; 30 | 31 | assign cs_n = ~cs; 32 | assign sck = shift[1] | shift[3] | shift[5] | shift[7] | shift[9] | shift[11] | shift[13] | shift[15]; 33 | assign mosi = sout[7]; 34 | 35 | assign dout = sin; 36 | 37 | wire iord = cpu_iordout ^ cpu_iordin; 38 | wire iowr = cpu_iowrout ^ cpu_iowrin; 39 | 40 | always @(posedge clk) 41 | begin 42 | ready <= ~|shift; 43 | 44 | cpu_iordout <= cpu_iordin; 45 | cpu_iowrout <= cpu_iowrin; 46 | 47 | if (iowr && (addr[11:0] == 12'h0B0)) // 0xB0 48 | cs <= din[0]; 49 | 50 | if (iowr && (addr[11:0] == 12'h0B1)) // 0xB1 51 | preset <= din; 52 | 53 | if (iowr && (addr[11:0] == 12'h0B2)) // 0xB2 54 | begin 55 | sout <= din; 56 | shift <= 16'd1; 57 | div <= 8'd0; 58 | end 59 | 60 | if (|shift) 61 | begin 62 | if (div == preset) 63 | begin 64 | div <= 8'd0; 65 | 66 | shift <= {shift[14:0], 1'b0}; 67 | 68 | if (sck) 69 | begin 70 | sin <= {sin[6:0], miso}; 71 | sout <= {sout[6:0], 1'b0}; 72 | end 73 | end 74 | else 75 | div <= div + 8'd1; 76 | end 77 | end 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /src/SRAM.v: -------------------------------------------------------------------------------- 1 | module SRAM( 2 | input wire clk, 3 | 4 | output wire ready, 5 | 6 | input wire [23:0] cpu_addr, 7 | input wire cpu_bhe_n, 8 | input wire [15:0] cpu_din, 9 | output reg [15:0] cpu_dout, 10 | input wire cpu_rdin, 11 | output reg cpu_rdout, 12 | input wire cpu_wrin, 13 | output reg cpu_wrout, 14 | 15 | input wire [23:0] gpu_addr, 16 | input wire [31:0] gpu_din, 17 | output reg [31:0] gpu_dout, 18 | input wire gpu_rdin, 19 | output reg gpu_rdout, 20 | input wire gpu_wrin, 21 | output reg gpu_wrout, 22 | 23 | input wire [23:0] video_addr, 24 | output reg [63:0] video_dout, 25 | 26 | output reg [17:0] a, 27 | inout reg [15:0] d, 28 | output wire cs_n, 29 | output wire we_n, 30 | output wire oe_n, 31 | output reg lb_n, 32 | output reg ub_n 33 | ); 34 | 35 | parameter S_IDLE = 1 << 0; 36 | parameter S_READ_CPU = 1 << 1; 37 | parameter S_WRITE_CPU = 1 << 2; 38 | parameter S_WRITE_CPU_1 = 1 << 3; 39 | parameter S_READ_GPU_0 = 1 << 5; 40 | parameter S_READ_GPU_1 = 1 << 6; 41 | parameter S_READ_GPU_2 = 1 << 7; 42 | parameter S_WRITE_GPU_0 = 1 << 8; 43 | parameter S_WRITE_GPU_1 = 1 << 9; 44 | parameter S_READ_VIDEO_0 = 1 << 10; 45 | parameter S_READ_VIDEO_1 = 1 << 11; 46 | parameter S_READ_VIDEO_2 = 1 << 12; 47 | parameter S_READ_VIDEO_3 = 1 << 13; 48 | parameter S_READ_VIDEO_4 = 1 << 14; 49 | 50 | reg [14:0] state; 51 | 52 | reg [18:3] cur_video_addr; 53 | 54 | reg cs; 55 | reg oe; 56 | reg we; 57 | 58 | assign ready = ~((cpu_rdin ^ cpu_rdout) | (cpu_wrin ^ cpu_wrout)); 59 | 60 | assign oe_n = ~oe; 61 | assign we_n = ~we; 62 | assign cs_n = ~cs; 63 | 64 | reg video_needs_data; 65 | 66 | always @(posedge clk) 67 | begin 68 | video_needs_data <= video_addr[18:3] != cur_video_addr; 69 | end 70 | 71 | reg delay; 72 | 73 | always @(posedge clk) 74 | begin 75 | delay <= 1'b1;//(cpu_wrin ^ cpu_wrout) || (cpu_rdin ^ cpu_rdout); 76 | case (state) 77 | S_IDLE: 78 | if (video_needs_data) 79 | begin 80 | a <= {video_addr[18:3], 2'b00}; 81 | d <= 16'hZZZZ; 82 | cs <= 1'b1; 83 | oe <= 1'b1; 84 | we <= 1'b0; 85 | lb_n <= 1'b0; 86 | ub_n <= 1'b0; 87 | state <= S_READ_VIDEO_0; 88 | end 89 | //else if (gpu_wrin ^ gpu_wrout) 90 | //state <= S_WRITE_GPU_0; 91 | //else if (gpu_rdin ^ gpu_rdout) 92 | //state <= S_READ_GPU_0; 93 | else if ((cpu_wrin ^ cpu_wrout) && delay) 94 | begin 95 | a <= cpu_addr[18:1]; 96 | d <= cpu_din; 97 | cs <= 1'b0; 98 | oe <= 1'b0; 99 | we <= 1'b1; 100 | lb_n <= cpu_addr[0]; 101 | ub_n <= cpu_bhe_n; 102 | state <= S_WRITE_CPU; 103 | end 104 | else if ((cpu_rdin ^ cpu_rdout) && delay) 105 | begin 106 | a <= cpu_addr[18:1]; 107 | d <= 16'hZZZZ; 108 | cs <= 1'b1; 109 | oe <= 1'b1; 110 | we <= 1'b0; 111 | lb_n <= 1'b0; 112 | ub_n <= 1'b0; 113 | state <= S_READ_CPU; 114 | end 115 | S_READ_CPU: 116 | begin 117 | cpu_rdout <= ~cpu_rdout; 118 | cpu_dout <= d; 119 | cs <= 1'b0; 120 | oe <= 1'b0; 121 | state <= S_IDLE; 122 | end 123 | S_WRITE_CPU: 124 | begin 125 | cs <= 1'b1; 126 | state <= S_WRITE_CPU_1; 127 | end 128 | S_WRITE_CPU_1: 129 | begin 130 | cpu_wrout <= ~cpu_wrout; 131 | d <= 16'hZZZZ; 132 | cs <= 1'b0; 133 | we <= 1'b0; 134 | state <= S_IDLE; 135 | end 136 | S_READ_GPU_0: 137 | state <= S_READ_GPU_1; 138 | S_READ_GPU_1: 139 | state <= S_READ_GPU_2; 140 | S_READ_GPU_2: 141 | state <= S_IDLE; 142 | S_WRITE_GPU_0: 143 | state <= S_WRITE_GPU_1; 144 | S_WRITE_GPU_1: 145 | state <= S_IDLE; 146 | S_READ_VIDEO_0: 147 | begin 148 | a <= {video_addr[18:3], 2'b01}; 149 | video_dout[15:0] <= d; 150 | state <= S_READ_VIDEO_1; 151 | end 152 | S_READ_VIDEO_1: 153 | begin 154 | a <= {video_addr[18:3], 2'b10}; 155 | video_dout[31:16] <= d; 156 | state <= S_READ_VIDEO_2; 157 | end 158 | S_READ_VIDEO_2: 159 | begin 160 | a <= {video_addr[18:3], 2'b11}; 161 | video_dout[47:32] <= d; 162 | state <= S_READ_VIDEO_3; 163 | end 164 | S_READ_VIDEO_3: 165 | begin 166 | cur_video_addr <= video_addr[18:3]; 167 | video_dout[63:48] <= d; 168 | cs <= 1'b0; 169 | oe <= 1'b0; 170 | state <= S_IDLE; 171 | end 172 | default: 173 | state <= S_IDLE; 174 | endcase 175 | end 176 | 177 | endmodule 178 | -------------------------------------------------------------------------------- /src/UART_tx.v: -------------------------------------------------------------------------------- 1 | module UART_tx( 2 | input wire clk, 3 | 4 | input wire [7:0] data, 5 | 6 | input wire send_in, 7 | output reg send_out, 8 | 9 | output reg txd 10 | ); 11 | 12 | localparam 13 | PRESCALER = 9'd433; 14 | 15 | reg [8:0] div; 16 | reg tx_clk; 17 | 18 | reg [3:0] bitn; 19 | reg [7:0] buffer; 20 | 21 | always @(posedge clk) 22 | begin 23 | div <= div == PRESCALER ? 9'd0 : div + 1'd1; 24 | tx_clk <= div == PRESCALER; 25 | end 26 | 27 | always @(posedge tx_clk) 28 | begin 29 | if (bitn == 4'd0) 30 | begin 31 | if (send_in != send_out) 32 | begin 33 | bitn <= bitn + 1'd1; 34 | buffer <= data; 35 | send_out <= ~send_out; 36 | txd <= 1'b0; 37 | end 38 | else 39 | begin 40 | txd <= 1'b1; 41 | end 42 | end 43 | else 44 | begin 45 | if (bitn <= 4'd8) 46 | begin 47 | buffer <= {1'b0, buffer[7:1]}; 48 | bitn <= bitn + 1'd1; 49 | txd <= buffer[0]; 50 | end 51 | else 52 | begin 53 | bitn <= 4'd0; 54 | txd <= 1'b1; 55 | end 56 | end 57 | end 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /src/USB_LS_HID.v: -------------------------------------------------------------------------------- 1 | module USB_LS_HID( 2 | input wire clk, 3 | input wire reset_n, 4 | 5 | output reg led, 6 | 7 | inout wire dm, 8 | inout wire dp, 9 | 10 | output reg [7:0] shift, 11 | output reg [7:0] keycode1, 12 | output reg [7:0] keycode2, 13 | output reg [7:0] keycode3, 14 | output reg irq_flip_out, 15 | input wire irq_flip_in, 16 | 17 | input wire keycode_next_flip 18 | ); 19 | 20 | wire connected; 21 | wire frame_in; 22 | reg frame_out; 23 | 24 | wire send_in; 25 | reg send_out; 26 | reg [31:0] send_ctrl; 27 | reg [5:0] send_ctrl_size; 28 | reg [95:0] send_data; 29 | reg [6:0] send_data_size; 30 | 31 | wire recv_in; 32 | reg recv_out; 33 | wire [95:0] recv_data; 34 | 35 | wire phy_led; 36 | wire [7:0] last_received_packet_type; 37 | 38 | wire [7:0] byte2; 39 | wire [7:0] byte3; 40 | wire [7:0] byte4; 41 | wire [7:0] byte5; 42 | wire [7:0] byte6; 43 | wire [7:0] byte7; 44 | USB_LS_PHY phy( 45 | .clk(clk), 46 | .reset_n(reset_n), 47 | 48 | .dm(dm), 49 | .dp(dp), 50 | 51 | .led(phy_led), 52 | 53 | .connected(connected), 54 | 55 | .frame_out(frame_in), 56 | 57 | .send_in(send_out), 58 | .send_out(send_in), 59 | .send_data(send_data), 60 | .send_data_size(send_data_size), 61 | .send_ctrl(send_ctrl), 62 | .send_ctrl_size(send_ctrl_size), 63 | 64 | .recv_out(recv_in), 65 | .recv_data(recv_data), 66 | .last_received_packet_type(last_received_packet_type), 67 | .byte2(byte2), 68 | .byte3(byte3), 69 | .byte4(byte4), 70 | .byte5(byte5), 71 | .byte6(byte6), 72 | .byte7(byte7) 73 | ); 74 | 75 | localparam 76 | R_ACK = 8'hD2, 77 | R_NAK = 8'h5A, 78 | R_STALL = 8'h1E, 79 | R_DATA0 = 8'hC3, 80 | R_DATA1 = 8'h4B; 81 | 82 | localparam 83 | CMD_SETUP0 = 32'h10002D80, 84 | CMD_SET_ADDRESS = 96'h25EB0000_00000001_0500C380, 85 | CMD_SETUP1 = 32'hE8012D80, 86 | CMD_SET_CONF = 96'h25270000_00000001_0900C380, 87 | CMD_READ0 = 32'h10006980, 88 | CMD_READ01 = 32'hA0806980, 89 | CMD_READ10 = 32'hE8016980, 90 | CMD_READ1 = 32'h58816980, 91 | CMD_GET_DESCR = 96'hF4E00012_00000100_0680C380, 92 | CMD_NONE = 96'h0, 93 | CMD_ACK = 16'hD280; 94 | 95 | localparam 96 | SZ_SETUP0 = 6'd32, 97 | SZ_SET_ADDRESS = 7'd96, 98 | SZ_SETUP1 = 6'd32, 99 | SZ_SET_CONF = 7'd96, 100 | SZ_READ0 = 6'd32, 101 | SZ_READ10 = 6'd32, 102 | SZ_READ1 = 6'd32, 103 | SZ_NONE = 7'd0, 104 | SZ_ACK = 6'd16; 105 | 106 | localparam 107 | S_NO_ADDRESS = 4'd0, 108 | S_NO_ADDRESS_READ = 4'd5, 109 | S_NO_STATUS_READ = 4'd10, 110 | S_NO_CONF = 4'd6, 111 | S_NO_CONF_READ = 4'd7, 112 | S_READY = 4'd8, 113 | S_NO_DESCR = 4'd4, 114 | S_NO_DESCR_READ1 = 4'd1, 115 | S_NO_DESCR_READ2 = 4'd2, 116 | S_NO_DESCR_READ3 = 4'd3; 117 | 118 | reg [3:0] state; 119 | 120 | reg [7:0] last2; 121 | reg [7:0] last3; 122 | reg [7:0] last4; 123 | reg [7:0] last5; 124 | 125 | reg [9:0] counter; 126 | 127 | reg [3:0] packet; 128 | 129 | always @(posedge clk or negedge reset_n) 130 | begin 131 | if (~reset_n) 132 | begin 133 | state <= S_NO_ADDRESS; 134 | end 135 | else 136 | begin 137 | if (!connected) 138 | begin 139 | state <= S_NO_ADDRESS; 140 | end 141 | else if (frame_in != frame_out) 142 | begin 143 | frame_out <= ~frame_out; 144 | //if (state != S_READY && counter[9]) 145 | //begin 146 | // state <= S_NO_ADDRESS; 147 | //end 148 | //else 149 | 150 | // if (state == S_READY) led <= ~led; 151 | 152 | begin 153 | counter <= counter + 1'd1; 154 | case (state) 155 | S_NO_DESCR: 156 | begin 157 | send_out <= ~send_out; 158 | send_ctrl <= CMD_SETUP0; 159 | send_ctrl_size <= SZ_SETUP0; 160 | send_data <= CMD_GET_DESCR; 161 | send_data_size <= SZ_SET_CONF; 162 | end 163 | S_NO_DESCR_READ1, S_NO_DESCR_READ2, S_NO_DESCR_READ3: 164 | begin 165 | send_out <= ~send_out; 166 | send_ctrl <= CMD_READ0; 167 | send_ctrl_size <= SZ_READ0; 168 | send_data <= CMD_NONE; 169 | send_data_size <= SZ_NONE; 170 | end 171 | S_NO_ADDRESS: 172 | begin 173 | send_out <= ~send_out; 174 | send_ctrl <= CMD_SETUP0; 175 | send_ctrl_size <= SZ_SETUP0; 176 | send_data <= CMD_SET_ADDRESS; 177 | send_data_size <= SZ_SET_ADDRESS; 178 | end 179 | S_NO_ADDRESS_READ: 180 | begin 181 | send_out <= ~send_out; 182 | send_ctrl <= CMD_READ0; 183 | send_ctrl_size <= SZ_READ0; 184 | send_data <= CMD_NONE; 185 | send_data_size <= SZ_NONE; 186 | end 187 | S_NO_STATUS_READ: 188 | begin 189 | send_out <= ~send_out; 190 | send_ctrl <= CMD_READ1; 191 | send_ctrl_size <= SZ_READ1; 192 | send_data <= CMD_NONE; 193 | send_data_size <= SZ_NONE; 194 | end 195 | S_NO_CONF: 196 | begin 197 | send_out <= ~send_out; 198 | send_ctrl <= CMD_SETUP1; 199 | send_ctrl_size <= SZ_SETUP1; 200 | send_data <= CMD_SET_CONF; 201 | send_data_size <= SZ_SET_CONF; 202 | end 203 | S_NO_CONF_READ: 204 | begin 205 | send_out <= ~send_out; 206 | send_ctrl <= CMD_READ10; 207 | send_ctrl_size <= SZ_READ10; 208 | send_data <= CMD_NONE; 209 | send_data_size <= SZ_NONE; 210 | end 211 | S_READY: 212 | begin 213 | packet <= packet + 1'd1; 214 | //if (packet == 4'd8) 215 | begin 216 | send_out <= ~send_out; 217 | send_ctrl <= CMD_READ1; 218 | send_ctrl_size <= SZ_READ1; 219 | send_data <= CMD_NONE; 220 | send_data_size <= SZ_NONE; 221 | end 222 | end 223 | endcase 224 | end 225 | end 226 | 227 | if (recv_in != recv_out) 228 | begin 229 | recv_out <= ~recv_out; 230 | if (last_received_packet_type == R_ACK) 231 | begin 232 | counter <= 10'd0; 233 | case (state) 234 | S_NO_ADDRESS: 235 | begin 236 | state <= S_NO_ADDRESS_READ; 237 | end 238 | S_NO_DESCR: 239 | begin 240 | state <= S_NO_DESCR_READ1; 241 | end 242 | S_NO_CONF: 243 | begin 244 | state <= S_READY;//S_NO_CONF_READ; 245 | end 246 | endcase 247 | end 248 | if (last_received_packet_type == R_NAK) 249 | begin 250 | counter <= 10'd0; 251 | case (state) 252 | S_READY: 253 | begin 254 | //led <= ~led; 255 | end 256 | endcase 257 | end 258 | else if (last_received_packet_type == R_DATA0 || last_received_packet_type == R_DATA1) 259 | begin 260 | counter <= 10'd0; 261 | led <= ~led; 262 | case (state) 263 | S_NO_ADDRESS_READ: 264 | begin 265 | state <= S_NO_CONF; 266 | end 267 | S_NO_STATUS_READ: 268 | begin 269 | state <= S_NO_CONF; 270 | end 271 | S_NO_DESCR_READ1: 272 | begin 273 | state <= S_NO_DESCR_READ2; 274 | end 275 | S_NO_DESCR_READ2: 276 | begin 277 | state <= S_NO_DESCR_READ3; 278 | end 279 | S_NO_DESCR_READ3: 280 | begin 281 | state <= S_NO_ADDRESS; 282 | end 283 | S_NO_CONF_READ: 284 | begin 285 | state <= S_READY; 286 | end 287 | S_READY: 288 | begin 289 | led <= ~led; 290 | last2 <= byte2; 291 | last3 <= byte3; 292 | last4 <= byte4; 293 | last5 <= byte5; 294 | 295 | shift <= byte2; 296 | 297 | keycode1 <= byte4; 298 | keycode2 <= byte5; 299 | keycode3 <= byte6; 300 | end 301 | endcase 302 | end 303 | end 304 | end 305 | end 306 | 307 | endmodule 308 | -------------------------------------------------------------------------------- /src/USB_LS_PHY.v: -------------------------------------------------------------------------------- 1 | module USB_LS_PHY( 2 | input wire clk, 3 | input wire reset_n, 4 | 5 | inout reg dm, 6 | inout reg dp, 7 | 8 | output reg led, 9 | 10 | output reg connected, 11 | 12 | output reg frame_out, 13 | 14 | input wire send_in, 15 | output reg send_out, 16 | input wire [31:0] send_ctrl, 17 | input wire [5:0] send_ctrl_size, 18 | input wire [95:0] send_data, 19 | input wire [6:0] send_data_size, 20 | 21 | output reg recv_out, 22 | output reg [95:0] recv_data, 23 | output reg [6:0] recv_size, 24 | output reg [7:0] last_received_packet_type, 25 | 26 | output reg [7:0] byte2, 27 | output reg [7:0] byte3, 28 | output reg [7:0] byte4, 29 | output reg [7:0] byte5, 30 | output reg [7:0] byte6, 31 | output reg [7:0] byte7 32 | ); 33 | 34 | localparam 35 | S_NODEVICE = 4'd0, 36 | S_DEBOUNCE = 4'd1, 37 | S_RESET = 4'd2, 38 | S_IDLE = 4'd3, 39 | S_SEND = 4'd4, 40 | S_START0 = 4'd5, 41 | S_START1 = 4'd6, 42 | S_START2 = 4'd7, 43 | S_STOP0 = 4'd8, 44 | S_STOP1 = 4'd9, 45 | S_STOP2 = 4'd10, 46 | S_RECEIVE_SYNC = 4'd11, 47 | S_RECEIVE = 4'd12; 48 | 49 | localparam 50 | R_ACK = 8'hD2, 51 | R_NAK = 8'h5A, 52 | R_STALL = 8'h1E, 53 | R_DATA0 = 8'hC3, 54 | R_DATA1 = 8'h4B; 55 | 56 | reg [3:0] state; 57 | reg send_data_after_ctrl; 58 | 59 | reg [19:0] timer; 60 | reg timer_exp; 61 | 62 | reg [3:0] phase; 63 | reg [3:0] errors; 64 | reg [2:0] ones; 65 | 66 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 67 | // Packet data 68 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 69 | reg [95:0] data; 70 | reg flip; 71 | reg [6:0] bits; 72 | reg [7:0] response_timeout; 73 | 74 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 75 | // Bit and frame timer 76 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 77 | reg [15:0] frame_timer; 78 | reg frame, prev_frame; 79 | reg [5:0] div33; 80 | reg bit_clk; 81 | reg fast; 82 | reg dmi; 83 | reg dpi; 84 | always @(negedge bit_clk) 85 | begin 86 | timer_exp <= timer == 20'd0; 87 | dmi <= dm; 88 | dpi <= dp; 89 | end 90 | 91 | always @(posedge clk or negedge reset_n) 92 | begin 93 | if (~reset_n) 94 | begin 95 | state <= S_NODEVICE; 96 | dm <= 1'bZ; 97 | dp <= 1'bZ; 98 | connected <= 1'b0; 99 | end 100 | else 101 | begin 102 | // Variable bit clock 103 | if (fast) 104 | begin 105 | // Waiting response - sample faster to synchronize with the device 106 | div33 <= div33 == 6'd7 ? 6'd0 : div33 + 1'd1; 107 | end 108 | else 109 | begin 110 | div33 <= div33 == 6'd32 ? 6'd0 : div33 + 1'd1; 111 | end 112 | bit_clk <= div33 == 6'd6; 113 | 114 | frame_timer <= frame_timer == 16'd49999 ? 16'd0 : frame_timer + 1'd1; 115 | frame <= frame_timer == 16'd49999 ? frame + 1'd1 : frame; 116 | 117 | if (bit_clk) 118 | begin 119 | timer <= timer == 20'd0 ? timer : timer - 1'd1; 120 | 121 | if (timer_exp) 122 | begin 123 | case (state) 124 | S_NODEVICE: 125 | begin 126 | connected <= 1'b0; 127 | dm <= 1'bZ; 128 | dp <= 1'bZ; 129 | errors <= 4'd0; 130 | if ({dmi, dpi} == 2'b10) 131 | begin 132 | state <= S_DEBOUNCE; 133 | end 134 | // Check 2 times per second 135 | timer <= 20'd750000; 136 | end 137 | S_DEBOUNCE: 138 | begin 139 | dm <= 1'b0; 140 | dp <= 1'b0; 141 | state <= S_RESET; 142 | // 20 ms reset 143 | timer <= 20'd30000; 144 | send_out <= send_in; 145 | end 146 | S_RESET: 147 | begin 148 | dm <= 1'bZ; 149 | dp <= 1'bZ; 150 | state <= S_IDLE; 151 | timer <= 20'd100; 152 | end 153 | S_START0: 154 | begin 155 | dm <= 1'b0; 156 | dp <= 1'b0; 157 | state <= S_START1; 158 | end 159 | S_START1: 160 | begin 161 | dm <= 1'b0; 162 | dp <= 1'b0; 163 | state <= S_START2; 164 | end 165 | S_START2: 166 | begin 167 | dm <= 1'b1; 168 | dp <= 1'b0; 169 | timer <= 20'd7; 170 | frame_out <= ~frame_out; 171 | ones <= 3'd0; 172 | 173 | if (send_in != send_out) 174 | begin 175 | data <= send_ctrl; 176 | bits <= send_ctrl_size; 177 | state <= S_SEND; 178 | send_data_after_ctrl <= send_data_size != 7'd0; 179 | end 180 | else 181 | begin 182 | state <= S_IDLE; 183 | end 184 | end 185 | S_SEND: 186 | begin 187 | if (ones == 3'd6) 188 | begin 189 | flip <= ~flip; 190 | dm <= flip; 191 | dp <= ~flip; 192 | ones <= 3'd0; 193 | end 194 | else if (|bits) 195 | begin 196 | bits <= bits - 1'd1; 197 | 198 | if (data[0]) 199 | begin 200 | ones <= ones + 1'd1; 201 | end 202 | else 203 | begin 204 | flip <= ~flip; 205 | dm <= flip; 206 | dp <= ~flip; 207 | ones <= 3'd0; 208 | end 209 | 210 | data <= {1'b0, data[95:1]}; 211 | end 212 | else 213 | begin 214 | dm <= 1'b0; 215 | dp <= 1'b0; 216 | state <= S_STOP0; 217 | end 218 | end 219 | S_STOP0: 220 | begin 221 | dm <= 1'b0; 222 | dp <= 1'b0; 223 | state <= S_STOP1; 224 | end 225 | S_STOP1: 226 | begin 227 | dm <= 1'b1; 228 | dp <= 1'b0; 229 | state <= S_STOP2; 230 | end 231 | S_STOP2: 232 | begin 233 | dm <= 1'bZ; 234 | dp <= 1'bZ; 235 | flip <= 1'b0; 236 | ones <= 3'd0; 237 | send_out <= ~send_out; 238 | send_data_after_ctrl <= 1'b0; 239 | if (send_data_after_ctrl) 240 | begin 241 | data <= send_data; 242 | bits <= send_data_size; 243 | state <= S_SEND; 244 | timer <= 20'd0; 245 | end 246 | else 247 | begin 248 | fast <= 1'b1; 249 | state <= S_IDLE; 250 | end 251 | end 252 | S_RECEIVE_SYNC: 253 | begin 254 | dm <= 1'bZ; 255 | dp <= 1'bZ; 256 | flip <= 1'b1; 257 | fast <= 1'b0; 258 | ones <= 3'd0; 259 | state <= S_RECEIVE; 260 | end 261 | S_RECEIVE: 262 | begin 263 | response_timeout <= response_timeout + 1'd1; 264 | if ((&response_timeout) || (bits >= 7'd120)) 265 | begin 266 | state <= S_IDLE; 267 | end 268 | else if ({dmi, dpi} == 2'b00) 269 | begin 270 | recv_data <= data; 271 | recv_size <= bits; 272 | recv_out <= ~recv_out; 273 | flip <= 1'b0; 274 | ones <= 3'd0; 275 | 276 | if (last_received_packet_type == R_STALL) 277 | begin 278 | // Something goes wrong. Let's re-initialize the device 279 | state <= S_NODEVICE; 280 | end 281 | else if (last_received_packet_type == R_DATA0 || last_received_packet_type == R_DATA1) 282 | begin 283 | led <= ~led; 284 | data <= 16'hD280; 285 | bits <= 6'd16; 286 | state <= S_SEND; 287 | timer <= 20'd3; 288 | end 289 | else 290 | begin 291 | state <= S_IDLE; 292 | end 293 | end 294 | else 295 | begin 296 | if (ones == 3'd6) 297 | begin 298 | ones <= 3'd0; 299 | end 300 | else if (dmi == flip) 301 | begin 302 | data <= {1'b1, data[95:1]}; 303 | bits <= bits + 1'd1; 304 | if (bits <= 7'd16) 305 | last_received_packet_type <= {1'b1, last_received_packet_type[7:1]}; 306 | if (bits <= 7'd24) 307 | byte2 <= {1'b1, byte2[7:1]}; 308 | if (bits <= 7'd32) 309 | byte3 <= {1'b1, byte3[7:1]}; 310 | if (bits <= 7'd40) 311 | byte4 <= {1'b1, byte4[7:1]}; 312 | if (bits <= 7'd48) 313 | byte5 <= {1'b1, byte5[7:1]}; 314 | if (bits <= 7'd56) 315 | byte6 <= {1'b1, byte6[7:1]}; 316 | if (bits <= 7'd64) 317 | byte7 <= {1'b1, byte7[7:1]}; 318 | ones <= ones + 1'd1; 319 | end 320 | else 321 | begin 322 | data <= {1'b0, data[95:1]}; 323 | bits <= bits + 1'd1; 324 | if (bits <= 7'd16) 325 | last_received_packet_type <= {1'b0, last_received_packet_type[7:1]}; 326 | if (bits <= 7'd24) 327 | byte2 <= {1'b0, byte2[7:1]}; 328 | if (bits <= 7'd32) 329 | byte3 <= {1'b0, byte3[7:1]}; 330 | if (bits <= 7'd40) 331 | byte4 <= {1'b0, byte4[7:1]}; 332 | if (bits <= 7'd48) 333 | byte5 <= {1'b0, byte5[7:1]}; 334 | if (bits <= 7'd56) 335 | byte6 <= {1'b0, byte6[7:1]}; 336 | if (bits <= 7'd64) 337 | byte7 <= {1'b0, byte7[7:1]}; 338 | ones <= 3'd0; 339 | end 340 | flip <= dmi; 341 | end 342 | end 343 | S_IDLE: 344 | begin 345 | // Usually, we're listening here at 4x frequency to find a start bit 346 | connected <= 1'b1; 347 | response_timeout <= 8'd0; 348 | ones <= 3'd0; 349 | 350 | if ({dmi, dpi} == 2'b00) 351 | begin 352 | errors <= errors + 1'd1; 353 | if (&errors) 354 | state <= S_NODEVICE; 355 | end 356 | else 357 | begin 358 | errors <= 4'd0; 359 | end 360 | 361 | if (frame != prev_frame) 362 | begin 363 | prev_frame <= frame; 364 | fast <= 1'b0; 365 | state <= S_START0; 366 | end 367 | else if ({dmi, dpi} == 2'b01) 368 | begin 369 | bits <= 7'd0; 370 | state <= S_RECEIVE_SYNC; 371 | end 372 | 373 | flip <= 1'b0; 374 | dm <= 1'bZ; 375 | dp <= 1'bZ; 376 | end 377 | 378 | default: 379 | state <= S_NODEVICE; 380 | endcase 381 | end 382 | end 383 | end 384 | end 385 | 386 | endmodule 387 | -------------------------------------------------------------------------------- /src/VGARegs.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "VGARegs.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "VGARegs_bb.v"] 5 | -------------------------------------------------------------------------------- /src/VGARegs.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: VGARegs.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module VGARegs ( 40 | address_a, 41 | address_b, 42 | clock, 43 | data_a, 44 | data_b, 45 | wren_a, 46 | wren_b, 47 | q_a, 48 | q_b); 49 | 50 | input [8:0] address_a; 51 | input [8:0] address_b; 52 | input clock; 53 | input [17:0] data_a; 54 | input [17:0] data_b; 55 | input wren_a; 56 | input wren_b; 57 | output [17:0] q_a; 58 | output [17:0] q_b; 59 | `ifndef ALTERA_RESERVED_QIS 60 | // synopsys translate_off 61 | `endif 62 | tri1 clock; 63 | tri0 wren_a; 64 | tri0 wren_b; 65 | `ifndef ALTERA_RESERVED_QIS 66 | // synopsys translate_on 67 | `endif 68 | 69 | wire [17:0] sub_wire0; 70 | wire [17:0] sub_wire1; 71 | wire [17:0] q_a = sub_wire0[17:0]; 72 | wire [17:0] q_b = sub_wire1[17:0]; 73 | 74 | altsyncram altsyncram_component ( 75 | .clock0 (clock), 76 | .wren_a (wren_a), 77 | .address_b (address_b), 78 | .data_b (data_b), 79 | .wren_b (wren_b), 80 | .address_a (address_a), 81 | .data_a (data_a), 82 | .q_a (sub_wire0), 83 | .q_b (sub_wire1), 84 | .aclr0 (1'b0), 85 | .aclr1 (1'b0), 86 | .addressstall_a (1'b0), 87 | .addressstall_b (1'b0), 88 | .byteena_a (1'b1), 89 | .byteena_b (1'b1), 90 | .clock1 (1'b1), 91 | .clocken0 (1'b1), 92 | .clocken1 (1'b1), 93 | .clocken2 (1'b1), 94 | .clocken3 (1'b1), 95 | .eccstatus (), 96 | .rden_a (1'b1), 97 | .rden_b (1'b1)); 98 | defparam 99 | altsyncram_component.address_reg_b = "CLOCK0", 100 | altsyncram_component.clock_enable_input_a = "BYPASS", 101 | altsyncram_component.clock_enable_input_b = "BYPASS", 102 | altsyncram_component.clock_enable_output_a = "BYPASS", 103 | altsyncram_component.clock_enable_output_b = "BYPASS", 104 | altsyncram_component.indata_reg_b = "CLOCK0", 105 | altsyncram_component.intended_device_family = "Cyclone IV E", 106 | altsyncram_component.lpm_type = "altsyncram", 107 | altsyncram_component.numwords_a = 512, 108 | altsyncram_component.numwords_b = 512, 109 | altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", 110 | altsyncram_component.outdata_aclr_a = "NONE", 111 | altsyncram_component.outdata_aclr_b = "NONE", 112 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 113 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 114 | altsyncram_component.power_up_uninitialized = "FALSE", 115 | altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", 116 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 117 | altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", 118 | altsyncram_component.widthad_a = 9, 119 | altsyncram_component.widthad_b = 9, 120 | altsyncram_component.width_a = 18, 121 | altsyncram_component.width_b = 18, 122 | altsyncram_component.width_byteena_a = 1, 123 | altsyncram_component.width_byteena_b = 1, 124 | altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; 125 | 126 | 127 | endmodule 128 | 129 | // ============================================================ 130 | // CNX file retrieval info 131 | // ============================================================ 132 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 133 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 134 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 135 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 136 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 137 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 138 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" 139 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 140 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 141 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 142 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 143 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 144 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 145 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 146 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 147 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 148 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 149 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 150 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 151 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 152 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 153 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 154 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 155 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 156 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 157 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 158 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 159 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 160 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 161 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 162 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216" 163 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 164 | // Retrieval info: PRIVATE: MIFfilename STRING "" 165 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 166 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 167 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 168 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 169 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 170 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 171 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 172 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 173 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 174 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 175 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 176 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 177 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 178 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 179 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 180 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 181 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 182 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18" 183 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18" 184 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18" 185 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18" 186 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 187 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 188 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 189 | // Retrieval info: PRIVATE: enable NUMERIC "0" 190 | // Retrieval info: PRIVATE: rden NUMERIC "0" 191 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 192 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 193 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 194 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 195 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 196 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 197 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 198 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 199 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 200 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" 201 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512" 202 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 203 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 204 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 205 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 206 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 207 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 208 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 209 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 210 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 211 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" 212 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9" 213 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" 214 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "18" 215 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 216 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 217 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 218 | // Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]" 219 | // Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]" 220 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 221 | // Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]" 222 | // Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]" 223 | // Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]" 224 | // Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]" 225 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 226 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 227 | // Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0 228 | // Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0 229 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 230 | // Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0 231 | // Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0 232 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 233 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 234 | // Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0 235 | // Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0 236 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.v TRUE 237 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.inc FALSE 238 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.cmp FALSE 239 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.bsf FALSE 240 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs_inst.v FALSE 241 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs_bb.v TRUE 242 | // Retrieval info: LIB_FILE: altera_mf 243 | -------------------------------------------------------------------------------- /src/VGARegs_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: VGARegs.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module VGARegs ( 35 | address_a, 36 | address_b, 37 | clock, 38 | data_a, 39 | data_b, 40 | wren_a, 41 | wren_b, 42 | q_a, 43 | q_b); 44 | 45 | input [8:0] address_a; 46 | input [8:0] address_b; 47 | input clock; 48 | input [17:0] data_a; 49 | input [17:0] data_b; 50 | input wren_a; 51 | input wren_b; 52 | output [17:0] q_a; 53 | output [17:0] q_b; 54 | `ifndef ALTERA_RESERVED_QIS 55 | // synopsys translate_off 56 | `endif 57 | tri1 clock; 58 | tri0 wren_a; 59 | tri0 wren_b; 60 | `ifndef ALTERA_RESERVED_QIS 61 | // synopsys translate_on 62 | `endif 63 | 64 | endmodule 65 | 66 | // ============================================================ 67 | // CNX file retrieval info 68 | // ============================================================ 69 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 70 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 71 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 72 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 73 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 74 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 75 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" 76 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 77 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 78 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 79 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 80 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 81 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 82 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 83 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 84 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 85 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 86 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 87 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 88 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 90 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 91 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 92 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 93 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 94 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 95 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 96 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 97 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 98 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 99 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216" 100 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 101 | // Retrieval info: PRIVATE: MIFfilename STRING "" 102 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 103 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 104 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 105 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 106 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 107 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 108 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 109 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 110 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 111 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 112 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 113 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 114 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 115 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 116 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 117 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 118 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 119 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18" 120 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18" 121 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18" 122 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18" 123 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 124 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 125 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 126 | // Retrieval info: PRIVATE: enable NUMERIC "0" 127 | // Retrieval info: PRIVATE: rden NUMERIC "0" 128 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 129 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 130 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 131 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 132 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 133 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 134 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 135 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 136 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 137 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" 138 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512" 139 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 140 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 141 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 142 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 144 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 145 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 146 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 147 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 148 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" 149 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9" 150 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" 151 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "18" 152 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 153 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 154 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 155 | // Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]" 156 | // Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]" 157 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 158 | // Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]" 159 | // Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]" 160 | // Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]" 161 | // Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]" 162 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 163 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 164 | // Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0 165 | // Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0 166 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 167 | // Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0 168 | // Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0 169 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 170 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 171 | // Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0 172 | // Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.v TRUE 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.inc FALSE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.cmp FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs.bsf FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs_inst.v FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL VGARegs_bb.v TRUE 179 | // Retrieval info: LIB_FILE: altera_mf 180 | -------------------------------------------------------------------------------- /src/ep4r86.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 00:12:21 January 02, 2023 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "00:12:21 January 02, 2023" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "Main" 31 | -------------------------------------------------------------------------------- /src/keyboard.mif: -------------------------------------------------------------------------------- 1 | WIDTH = 8; 2 | DEPTH = 100; 3 | 4 | ADDRESS_RADIX = HEX; 5 | DATA_RADIX = HEX; 6 | CONTENT BEGIN 7 | 0000 : 00; 8 | 0001 : 00; 9 | 0002 : 00; 10 | 0003 : 00; 11 | 0004 : 1E; 12 | 0005 : 30; 13 | 0006 : 2E; 14 | 0007 : 20; 15 | 0008 : 12; 16 | 0009 : 21; 17 | 000A : 22; 18 | 000B : 23; 19 | 000C : 17; 20 | 000D : 24; 21 | 000E : 25; 22 | 000F : 26; 23 | 0010 : 32; 24 | 0011 : 31; 25 | 0012 : 18; 26 | 0013 : 19; 27 | 0014 : 10; 28 | 0015 : 13; 29 | 0016 : 1F; 30 | 0017 : 14; 31 | 0018 : 16; 32 | 0019 : 2F; 33 | 001A : 11; 34 | 001B : 2D; 35 | 001C : 15; 36 | 001D : 2C; 37 | 001E : 02; 38 | 001F : 03; 39 | 0020 : 04; 40 | 0021 : 05; 41 | 0022 : 06; 42 | 0023 : 07; 43 | 0024 : 08; 44 | 0025 : 09; 45 | 0026 : 0A; 46 | 0027 : 0B; 47 | 0028 : 1C; 48 | 0029 : 01; 49 | 002A : 0E; 50 | 002B : 0F; 51 | 002C : 39; 52 | 002D : 0C; 53 | 002E : 0D; 54 | 002F : 1A; 55 | 0030 : 1B; 56 | 0031 : 2B; 57 | 0032 : 00; 58 | 0033 : 27; 59 | 0034 : 28; 60 | 0035 : 29; 61 | 0036 : 33; 62 | 0037 : 34; 63 | 0038 : 35; 64 | 0039 : 3A; 65 | 003A : 3B; 66 | 003B : 3C; 67 | 003C : 3D; 68 | 003D : 3E; 69 | 003E : 3F; 70 | 003F : 40; 71 | 0040 : 41; 72 | 0041 : 42; 73 | 0042 : 43; 74 | 0043 : 44; 75 | 0044 : 57; 76 | 0045 : 58; 77 | 0046 : 00; 78 | 0047 : 46; 79 | 0048 : 00; 80 | 0049 : 52; 81 | 004A : 47; 82 | 004B : 49; 83 | 004C : 53; 84 | 004D : 4F; 85 | 004E : 51; 86 | 004F : 4D; 87 | 0050 : 4B; 88 | 0051 : 50; 89 | 0052 : 48; 90 | 0053 : 45; 91 | 0054 : 35; 92 | 0055 : 37; 93 | 0056 : 4A; 94 | 0057 : 4E; 95 | 0058 : 1C; 96 | 0059 : 4F; 97 | 005A : 50; 98 | 005B : 51; 99 | 005C : 4B; 100 | 005D : 4C; 101 | 005E : 4D; 102 | 005F : 47; 103 | 0060 : 48; 104 | 0061 : 49; 105 | 0062 : 52; 106 | 0063 : 53; 107 | END 108 | -------------------------------------------------------------------------------- /src/keyboard.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "keyboard.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "keyboard_bb.v"] 5 | -------------------------------------------------------------------------------- /src/keyboard.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: keyboard.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module keyboard ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [7:0] address; 45 | input clock; 46 | output [7:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [7:0] sub_wire0; 56 | wire [7:0] q = sub_wire0[7:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({8{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | altsyncram_component.init_file = "keyboard.mif", 87 | altsyncram_component.intended_device_family = "Cyclone IV E", 88 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 89 | altsyncram_component.lpm_type = "altsyncram", 90 | altsyncram_component.numwords_a = 256, 91 | altsyncram_component.operation_mode = "ROM", 92 | altsyncram_component.outdata_aclr_a = "NONE", 93 | altsyncram_component.outdata_reg_a = "CLOCK0", 94 | altsyncram_component.widthad_a = 8, 95 | altsyncram_component.width_a = 8, 96 | altsyncram_component.width_byteena_a = 1; 97 | 98 | 99 | endmodule 100 | 101 | // ============================================================ 102 | // CNX file retrieval info 103 | // ============================================================ 104 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 105 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 108 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 110 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 111 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 114 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 115 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 116 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 117 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 118 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 119 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 120 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 121 | // Retrieval info: PRIVATE: MIFfilename STRING "../keyboard.mif" 122 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 123 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 124 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 125 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 126 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 127 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 128 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 129 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 130 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 131 | // Retrieval info: PRIVATE: rden NUMERIC "0" 132 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 133 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 134 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: INIT_FILE STRING "../keyboard.mif" 137 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 138 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 139 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 140 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 141 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 142 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 144 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 145 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 146 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 147 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 148 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 149 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 150 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 151 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 152 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 153 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.v TRUE 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.inc FALSE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.cmp FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.bsf FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard_inst.v FALSE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard_bb.v TRUE 159 | // Retrieval info: LIB_FILE: altera_mf 160 | -------------------------------------------------------------------------------- /src/keyboard_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: keyboard.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module keyboard ( 35 | address, 36 | clock, 37 | q); 38 | 39 | input [7:0] address; 40 | input clock; 41 | output [7:0] q; 42 | `ifndef ALTERA_RESERVED_QIS 43 | // synopsys translate_off 44 | `endif 45 | tri1 clock; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_on 48 | `endif 49 | 50 | endmodule 51 | 52 | // ============================================================ 53 | // CNX file retrieval info 54 | // ============================================================ 55 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 56 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 59 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 61 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 62 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 65 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 66 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 67 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 68 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 69 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 70 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 71 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 72 | // Retrieval info: PRIVATE: MIFfilename STRING "../keyboard.mif" 73 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 74 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 75 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 76 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 77 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 78 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 79 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 80 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 81 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 82 | // Retrieval info: PRIVATE: rden NUMERIC "0" 83 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 84 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 85 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: INIT_FILE STRING "../keyboard.mif" 88 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 90 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 91 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 92 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 93 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 94 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 95 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 96 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 97 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 98 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 99 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 100 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 101 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 102 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 103 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.v TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.inc FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.cmp FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard.bsf FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard_inst.v FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL keyboard_bb.v TRUE 110 | // Retrieval info: LIB_FILE: altera_mf 111 | --------------------------------------------------------------------------------