├── README.md ├── dft ├── cons │ └── cons.tcl ├── output │ ├── UART.def │ ├── UART.svf │ ├── UART_mapped.ddc │ ├── UART_mapped.sdc │ ├── UART_mapped.sdf │ └── UART_mapped.v ├── reports │ ├── area.rpt │ ├── constraints.rpt │ ├── hold.rpt │ ├── power.rpt │ ├── qor.rpt │ └── setup.rpt └── script │ └── dft_script.tcl ├── fm ├── post_DFT │ ├── fm_reports │ │ ├── aborted_points.rpt │ │ ├── failing_points.rpt │ │ ├── passing_points.rpt │ │ └── unverified_points.rpt │ ├── fm_script.tcl │ └── formality_svf │ │ └── svf.txt └── post_synthesis │ ├── fm_reports │ ├── aborted_points.rpt │ ├── failing_points.rpt │ ├── passing_points.rpt │ └── unverified_points.rpt │ ├── fm_script.tcl │ └── formality_svf │ ├── d1 │ └── netlists │ │ └── S1 │ │ └── J1 │ │ └── dw-1 │ │ ├── data_sampling_DP_OP_13J1_124_7424_J1_0.b │ │ ├── deserializer_DATA_WIDTH8_DP_OP_3J1_126_2816_J1_0.b │ │ ├── edge_bit_counter_DP_OP_10J1_125_9618_J1_0.b │ │ ├── uart_rx_fsm_DATA_WIDTH8_DP_OP_29J1_122_2437_J1_0.b │ │ └── uart_rx_fsm_DATA_WIDTH8_DP_OP_30J1_123_2437_J1_0.b │ └── svf.txt ├── pnr ├── output │ ├── UART.def │ ├── UART.gds │ ├── UART.lef │ ├── UART.lvs.v │ ├── UART.tlef │ └── UART.v ├── pnr.tcl ├── reports │ ├── CTS │ │ ├── check_legality.rpt │ │ ├── latency.rpt │ │ ├── local_skew.rpt │ │ ├── report_clock_qor.rpt │ │ ├── report_constraints_max_capacitance.rpt │ │ ├── report_constraints_max_transition.rpt │ │ └── report_qor.rpt │ ├── Placement │ │ ├── check_legality.rpt │ │ ├── report_congestion.rpt │ │ ├── report_qor.summary.rpt │ │ ├── report_timing.data.rpt │ │ ├── report_timing.full.rpt │ │ └── report_utilization.rpt │ ├── Powerplanning │ │ ├── check_pg_connectivity.rpt │ │ ├── check_pg_drc.rpt │ │ ├── check_pg_missing_vias.rpt │ │ ├── report_qor.summary.rpt │ │ └── report_timing.rpt │ └── Routing │ │ ├── check_legality.rpt │ │ ├── check_lvs.rpt │ │ ├── check_routes.rpt │ │ ├── report_constraints_max_capacitance.rpt │ │ ├── report_constraints_max_transition.rpt │ │ ├── report_qor.rpt │ │ └── report_timing.rpt └── scripts │ ├── ndr.tcl │ └── power_network.tcl ├── rtl ├── UART_RX │ ├── UART_RX.v │ ├── data_sampling.v │ ├── deserializer.v │ ├── edge_bit_counter.v │ ├── par_chk.v │ ├── stp_chk.v │ ├── strt_chk.v │ └── uart_rx_fsm.v ├── UART_TOP │ └── UART.v ├── UART_TOP_DFT │ ├── UART.v │ └── mux2X1.v └── UART_TX │ ├── Serializer.v │ ├── UART_TX.v │ ├── mux.v │ ├── mux.v~ │ ├── parity_calc.v │ └── uart_tx_fsm.v ├── sim ├── UART_RX │ ├── Test_cases │ │ ├── Test1.png │ │ ├── Test2.png │ │ ├── Test3.png │ │ ├── Test4.png │ │ ├── Test5.png │ │ ├── Test6.png │ │ ├── Test7.png │ │ ├── Test8.png │ │ └── Test9.png │ └── UART_RX_TB.v └── UART_TX │ ├── Test_cases │ ├── Test1.png │ ├── Test2.png │ └── Test3.png │ └── UART_TX_TB.v └── syn ├── cons └── cons.tcl ├── output ├── UART.svf ├── UART_mapped.ddc ├── UART_mapped.sdc ├── UART_mapped.sdf └── UART_mapped.v ├── reports ├── area.rpt ├── constraints.rpt ├── hold.rpt ├── power.rpt ├── qor.rpt └── setup.rpt └── script └── syn_script.tcl /README.md: -------------------------------------------------------------------------------- 1 | # Design-and-ASIC-Implementation-of-UART 2 | This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II 3 | 4 | UART stands for universal asynchronous receiver / transmitter and defines a protocol, or set of rules, for exchanging serial data between two devices. UART is very simple and only uses two wires between transmitter and receiver to transmit and receive in both directions. so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in VCS, synthesized in Design Compiler, and extracted in ICC II in SAED 32 nm CMOS cell library. 5 | 6 | ## Introduction 7 | The first step of the ASIC Design flow is the register transfer level (RTL) design, where the high-level architectural description is transformed into a digital representation using VerilogL. This involves designing and implementing the behavior and connections of individual digital components. 8 | 9 | UART can be divided into sending module and receiving module according to functions. It is worth noting that in order to take into account the accuracy and efficiency of information transmission, the sending module and the receiving module have different methods of confirming information. 10 | 11 | During the transmission, the transmitter transmits the parallel data by converting it into a serial data stream and includes „start bit‟ and „stop bit‟ 12 | 13 | During the receiving operation, the receiver receives the serial bit data stream and converts it into parallel data by rejecting the „start bit‟ and „stop bit‟ 14 | 15 | ### UART Data Frame 16 | UART frame contain start and stop bits, and optional parity bit. 17 |

18 | ![Picture1](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/1b63e52d-1c66-4f15-8897-520179add408) 19 | 20 | - Start bit: Because UART is asynchronous, the transmitter needs to signal that data bits are coming. This is accomplished by using the start bit. The start bit is a transition from the idle high state to a low state, and immediately followed by user data bits. 21 | - Stop bit: After the data bits are finished, the stop bit indicates the end of user data. The stop bit is a transition back to the high state. 22 | - Data bits: The data bits are the user data or “useful” bits and come immediately after the start bit. 7 or 8 bits is most common. These data bits are usually transmitted with the least significant bit first. 23 | - Parity bit: A UART frame can also contain an optional parity bit that can be used for error detection. The value of the parity bit depends on the type of parity being used (even or odd) 24 | 25 | ## Timing and Synchronization 26 | It is possible for a phase delay to occur during the frame's passage through the system until it reaches the UART_RX, so we will need to use higher clock frequency to oversampling the data.UART_RX support oversampling by 8, 16, 32. data_sampling block in UART_RX will take 3 samples in the middle of clock period to ensure sampl the correct value. 27 |

28 | For example: Oversampling by 8 means that the clock speed of UART_RX is 8 times the speed of UART_TX 29 | ![oversampling](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/e499402c-bcff-40ee-8666-e7fefb5ab2ea) 30 | 31 | ## UART clock 32 | the transmitter and receiver do not share a common clock signal. in this repository I used two clock UART_CLK_TX for transmitter module and UART_CLK_RX for receiver module and used the baud rate 115200 and prescale (division factor) = 32 : 33 |

34 | baud rate = 115200 bits/sec = 112.5 KHz 35 |

36 | UART_CLK_TX = 112.5 KHz 37 |

38 | UART_CLK_RX =115200 * 32 = 3.515 MHz 39 |

40 | 41 | ## Simulation using VCS 42 | ### UART_RX simulation 43 | ![Test7](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/58055bd7-a6f3-4ce0-8e29-c399697ca906) 44 |

45 | ### UART_TX simulation 46 | ![Test2](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/807dc089-16ea-4de2-90c2-414951b9ce5a) 47 | 48 | ## Synthesized View of UART chip (post DFT) 49 | ![Synthesized View of UART chip](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/67561cf1-9c6b-4ec3-921d-660c68a194a0) 50 | 51 | ## Synthesized view of UART connections (post DFT) 52 | ![Synthesized View of UART connections](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/97f61794-663f-4914-b1d0-1a316f23f953) 53 | 54 | ## Powerplanning layout 55 | ![power network](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/9e0838d5-ebe0-4ddd-88fc-d4bb8dd8ff21) 56 | 57 | ## Placement layout 58 | turn off visibility of the P/G mesh to better see the placement 59 | ![placement](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/28c4d26a-a31c-43b6-a293-b246a22d4544) 60 | 61 | ## Clock Tree 62 | ![Clock tree](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/dec10d49-432f-4898-8d33-c9bbafd011e7) 63 | 64 | ## Scan Chain 65 | ![Scan chain](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/66d34d08-5bbe-464b-bc1d-3e1b4680cc71) 66 | 67 | ## Routing layout 68 | ![Routing](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/6dfff8a5-b3ac-4c8e-8bc3-9ffb82900cef) 69 | 70 | ## IR drop 71 | to do analyze_power_plan I use set_virtual_pad at nets VDD and VSS 72 | ![Voltage drop](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/1e6ed2c4-8a42-4103-9484-a6ee2ad4e558) 73 | 74 | ## Congestion map 75 | ![congestion map](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/401dd473-3581-4afe-a3d6-7c93fcff14b2) 76 | 77 | 78 | ## Contributing 79 | Contributions to this project are welcome. If you find any issues or have suggestions for improvements, please feel free to submit a pull request or open an issue in the repository. 80 | -------------------------------------------------------------------------------- /dft/cons/cons.tcl: -------------------------------------------------------------------------------- 1 | 2 | # Constraints 3 | # ---------------------------------------------------------------------------- 4 | # 5 | # 1. Master Clock Definitions 6 | # 7 | # 2. Clock Uncertainties 8 | # 9 | # 3. set input/output delay on ports 10 | # 11 | # 4. Driving cells 12 | # 13 | # 5. Output load 14 | 15 | 16 | #################################################################################### 17 | ######################################################### 18 | #### Section 1 : Clock Definition #### 19 | ######################################################### 20 | #################################################################################### 21 | # 1. Master Clock Definitions 22 | # 2. Clock Uncertainties 23 | # 3. Clock Transitions 24 | #################################################################################### 25 | 26 | #baud rate =115200 bits/sec = 112.5 KHz 27 | 28 | # UART_CLK_TX = 112.5 KHz 29 | set CLK1_NAME UART_CLK_TX 30 | set CLK1_PER 8680.5 31 | 32 | # UART_CLK_RX =115200 * 32= 3.515 MHz 33 | set CLK2_NAME UART_CLK_RX 34 | set CLK2_PER 271.316 35 | 36 | #SCAN_CLK (10 MHZ) 37 | set CLK3_NAME SCAN_CLK 38 | set CLK3_PER 100 39 | 40 | set CLK_SETUP_SKEW 0.25 41 | set CLK_HOLD_SKEW 0.1 42 | set CLK_TRA 0.1 43 | 44 | 45 | create_clock -name $CLK1_NAME -period $CLK1_PER -waveform "0 [expr $CLK1_PER/2]" [get_ports TX_CLK] 46 | set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK1_NAME] 47 | set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK1_NAME] 48 | 49 | create_clock -name $CLK2_NAME -period $CLK2_PER -waveform "0 [expr $CLK2_PER/2]" [get_ports RX_CLK] 50 | set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK2_NAME] 51 | set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK2_NAME] 52 | 53 | # Scan clocks 54 | create_clock -name $CLK3_NAME -period $CLK3_PER -waveform "0 [expr $CLK3_PER/2]" [get_ports scan_clk] 55 | set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK3_NAME] 56 | set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK3_NAME] 57 | 58 | set_clock_transition -rise $CLK_TRA [get_clocks $CLK1_NAME] 59 | set_clock_transition -rise $CLK_TRA [get_clocks $CLK2_NAME] 60 | 61 | # Don’t optimize logic crossing clock domains 62 | set_false_path -from [get_clocks $CLK1_NAME] -to [get_clocks $CLK2_NAME] 63 | set_false_path -from [get_clocks $CLK2_NAME] -to [get_clocks $CLK1_NAME] 64 | 65 | #################################################################################### 66 | ######################################################### 67 | #### Section 2 : Clocks Relationship #### 68 | ######################################################### 69 | #################################################################################### 70 | 71 | set_clock_groups -asynchronous -group [get_clocks {UART_CLK_TX UART_CLK_RX}] \ 72 | -group [get_clocks SCAN_CLK] 73 | #################################################################################### 74 | ######################################################### 75 | #### Section 2 : set input/output delay on ports #### 76 | ######################################################### 77 | #################################################################################### 78 | 79 | set in_delay [expr 0.3*$CLK2_PER] 80 | set out_delay [expr 0.3*$CLK2_PER] 81 | 82 | #Constrain Input Paths 83 | set_input_delay $in_delay -clock $CLK2_NAME [remove_from_collection [all_inputs] [get_ports {scan_clk TX_CLK RX_CLK RST}]] 84 | 85 | 86 | #Constrain Output Paths 87 | set_output_delay $out_delay -clock $CLK2_NAME [all_outputs] 88 | 89 | #################################################################################### 90 | ######################################################### 91 | #### Section 4 : Driving cells #### 92 | ######################################################### 93 | #################################################################################### 94 | 95 | set_driving_cell -no_design_rule -max -lib_cell NBUFFX4_RVT [remove_from_collection [all_inputs] [get_ports {scan_clk TX_CLK RX_CLK}]] 96 | 97 | #################################################################################### 98 | ######################################################### 99 | #### Section 5 : Output load #### 100 | ######################################################### 101 | #################################################################################### 102 | 103 | set_load -max [expr {2 * [load_of saed32rvt_ss0p75v125c/NBUFFX4_RVT/A]}] [all_outputs] 104 | 105 | #################################################################################### 106 | ######################################################### 107 | #### Section 6 : min and max library #### 108 | ######################################################### 109 | #################################################################################### 110 | 111 | set_min_library saed32rvt_ss0p75v125c.db -min_version saed32rvt_ff1p16vn40c.db 112 | 113 | #################################################################################### 114 | ######################################################### 115 | #### Section 7 : wireload Model #### 116 | ######################################################### 117 | #################################################################################### 118 | 119 | set auto_wire_load_selection area_reselect 120 | set_wire_load_mode enclosed 121 | set_wire_load_selection_group predcaps 122 | 123 | #################################################################################### 124 | ######################################################### 125 | #### Section 8 : set_case_analysis #### 126 | ######################################################### 127 | #################################################################################### 128 | 129 | set_case_analysis 1 [get_port test_mode] 130 | -------------------------------------------------------------------------------- /dft/output/UART.def: -------------------------------------------------------------------------------- 1 | VERSION 5.5 ; 2 | NAMESCASESENSITIVE ON ; 3 | DIVIDERCHAR "/" ; 4 | BUSBITCHARS "[]" ; 5 | DESIGN UART ; 6 | 7 | SCANCHAINS 1 ; 8 | 9 | - 1 10 | + START PIN SI 11 | + FLOATING U0_UART_RX/U0_data_sampling/Samples_reg_0_ ( IN SI ) ( OUT QN ) 12 | U0_UART_RX/U0_data_sampling/Samples_reg_1_ ( IN SI ) ( OUT QN ) 13 | U0_UART_RX/U0_data_sampling/Samples_reg_2_ ( IN SI ) ( OUT QN ) 14 | U0_UART_RX/U0_data_sampling/sampled_bit_reg ( IN SI ) ( OUT QN ) 15 | U0_UART_RX/U0_deserializer/P_DATA_reg_0_ ( IN SI ) ( OUT QN ) 16 | U0_UART_RX/U0_deserializer/P_DATA_reg_1_ ( IN SI ) ( OUT QN ) 17 | U0_UART_RX/U0_deserializer/P_DATA_reg_2_ ( IN SI ) ( OUT QN ) 18 | U0_UART_RX/U0_deserializer/P_DATA_reg_3_ ( IN SI ) ( OUT QN ) 19 | U0_UART_RX/U0_deserializer/P_DATA_reg_4_ ( IN SI ) ( OUT QN ) 20 | U0_UART_RX/U0_deserializer/P_DATA_reg_5_ ( IN SI ) ( OUT QN ) 21 | U0_UART_RX/U0_deserializer/P_DATA_reg_6_ ( IN SI ) ( OUT QN ) 22 | U0_UART_RX/U0_deserializer/P_DATA_reg_7_ ( IN SI ) ( OUT QN ) 23 | U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ ( IN SI ) ( OUT QN ) 24 | U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ ( IN SI ) ( OUT QN ) 25 | U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ ( IN SI ) ( OUT QN ) 26 | U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ ( IN SI ) ( OUT QN ) 27 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ ( IN SI ) ( OUT QN ) 28 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ ( IN SI ) ( OUT QN ) 29 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ ( IN SI ) ( OUT QN ) 30 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ ( IN SI ) ( OUT QN ) 31 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ ( IN SI ) ( OUT QN ) 32 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ ( IN SI ) ( OUT QN ) 33 | U0_UART_RX/U0_par_chk/par_err_reg ( IN SI ) ( OUT QN ) 34 | U0_UART_RX/U0_stp_chk/stp_err_reg ( IN SI ) ( OUT Q ) 35 | U0_UART_RX/U0_strt_chk/strt_glitch_reg ( IN SI ) ( OUT QN ) 36 | U0_UART_RX/U0_uart_fsm/current_state_reg_0_ ( IN SI ) ( OUT Q ) 37 | U0_UART_RX/U0_uart_fsm/current_state_reg_1_ ( IN SI ) ( OUT QN ) 38 | U0_UART_RX/U0_uart_fsm/current_state_reg_2_ ( IN SI ) ( OUT QN ) 39 | U0_UART_TX/U0_Serializer/DATA_V_reg_0_ ( IN SI ) ( OUT QN ) 40 | U0_UART_TX/U0_Serializer/DATA_V_reg_1_ ( IN SI ) ( OUT QN ) 41 | U0_UART_TX/U0_Serializer/DATA_V_reg_2_ ( IN SI ) ( OUT QN ) 42 | U0_UART_TX/U0_Serializer/DATA_V_reg_3_ ( IN SI ) ( OUT QN ) 43 | U0_UART_TX/U0_Serializer/DATA_V_reg_4_ ( IN SI ) ( OUT QN ) 44 | U0_UART_TX/U0_Serializer/DATA_V_reg_5_ ( IN SI ) ( OUT QN ) 45 | U0_UART_TX/U0_Serializer/DATA_V_reg_6_ ( IN SI ) ( OUT QN ) 46 | U0_UART_TX/U0_Serializer/DATA_V_reg_7_ ( IN SI ) ( OUT QN ) 47 | U0_UART_TX/U0_Serializer/ser_count_reg_0_ ( IN SI ) ( OUT QN ) 48 | U0_UART_TX/U0_Serializer/ser_count_reg_1_ ( IN SI ) ( OUT QN ) 49 | U0_UART_TX/U0_Serializer/ser_count_reg_2_ ( IN SI ) ( OUT QN ) 50 | U0_UART_TX/U0_fsm/busy_reg ( IN SI ) ( OUT QN ) 51 | U0_UART_TX/U0_fsm/current_state_reg_0_ ( IN SI ) ( OUT QN ) 52 | U0_UART_TX/U0_fsm/current_state_reg_1_ ( IN SI ) ( OUT QN ) 53 | U0_UART_TX/U0_fsm/current_state_reg_2_ ( IN SI ) ( OUT Q ) 54 | U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ ( IN SI ) ( OUT Q ) 55 | U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ ( IN SI ) ( OUT QN ) 56 | U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ ( IN SI ) ( OUT Q ) 57 | U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ ( IN SI ) ( OUT QN ) 58 | U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ ( IN SI ) ( OUT Q ) 59 | U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ ( IN SI ) ( OUT Q ) 60 | U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ ( IN SI ) ( OUT Q ) 61 | U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ ( IN SI ) ( OUT Q ) 62 | U0_UART_TX/U0_parity_calc/parity_reg ( IN SI ) ( OUT QN ) 63 | U0_UART_TX/U0_mux/OUT_reg ( IN SI ) ( OUT Q ) 64 | + PARTITION scan_clk_30_30 65 | + STOP PIN SO ; 66 | 67 | END SCANCHAINS 68 | 69 | END DESIGN 70 | -------------------------------------------------------------------------------- /dft/output/UART.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/dft/output/UART.svf -------------------------------------------------------------------------------- /dft/output/UART_mapped.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/dft/output/UART_mapped.ddc -------------------------------------------------------------------------------- /dft/output/UART_mapped.sdc: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | 3 | # Created by write_sdc on Thu Apr 18 17:18:50 2024 4 | 5 | ################################################################### 6 | set sdc_version 2.1 7 | 8 | set_units -time ns -resistance MOhm -capacitance fF -voltage V -current uA 9 | set_wire_load_mode enclosed 10 | set_wire_load_selection_group predcaps 11 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports RST] 12 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports RX_IN_S] 13 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[7]}] 14 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[6]}] 15 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[5]}] 16 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[4]}] 17 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[3]}] 18 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[2]}] 19 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[1]}] 20 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[0]}] 21 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports TX_IN_V] 22 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[5]}] 23 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[4]}] 24 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[3]}] 25 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[2]}] 26 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[1]}] 27 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[0]}] 28 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports parity_enable] 29 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports parity_type] 30 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports SI] 31 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports SE] 32 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports scan_rst] 33 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports test_mode] 34 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[7]}] 35 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[6]}] 36 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[5]}] 37 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[4]}] 38 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[3]}] 39 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[2]}] 40 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[1]}] 41 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[0]}] 42 | set_load -pin_load 1.18475 [get_ports RX_OUT_V] 43 | set_load -pin_load 1.18475 [get_ports TX_OUT_S] 44 | set_load -pin_load 1.18475 [get_ports TX_OUT_V] 45 | set_load -pin_load 1.18475 [get_ports parity_error] 46 | set_load -pin_load 1.18475 [get_ports framing_error] 47 | set_load -pin_load 1.18475 [get_ports SO] 48 | set_case_analysis 1 [get_ports test_mode] 49 | create_clock [get_ports TX_CLK] -name UART_CLK_TX -period 8680.5 -waveform {0 4340.25} 50 | set_clock_uncertainty -setup 0.25 [get_clocks UART_CLK_TX] 51 | set_clock_uncertainty -hold 0.1 [get_clocks UART_CLK_TX] 52 | set_clock_transition -min -rise 0.1 [get_clocks UART_CLK_TX] 53 | set_clock_transition -max -rise 0.1 [get_clocks UART_CLK_TX] 54 | create_clock [get_ports RX_CLK] -name UART_CLK_RX -period 271.316 -waveform {0 135.658} 55 | set_clock_uncertainty -setup 0.25 [get_clocks UART_CLK_RX] 56 | set_clock_uncertainty -hold 0.1 [get_clocks UART_CLK_RX] 57 | set_clock_transition -min -rise 0.1 [get_clocks UART_CLK_RX] 58 | set_clock_transition -max -rise 0.1 [get_clocks UART_CLK_RX] 59 | create_clock [get_ports scan_clk] -name SCAN_CLK -period 100 -waveform {0 50} 60 | set_clock_uncertainty -setup 0.25 [get_clocks SCAN_CLK] 61 | set_clock_uncertainty -hold 0.1 [get_clocks SCAN_CLK] 62 | group_path -name INOUT -from [list [get_ports RST] [get_ports TX_CLK] [get_ports RX_CLK] [get_ports RX_IN_S] [get_ports {TX_IN_P[7]}] [get_ports {TX_IN_P[6]}] [get_ports {TX_IN_P[5]}] [get_ports {TX_IN_P[4]}] [get_ports {TX_IN_P[3]}] [get_ports {TX_IN_P[2]}] [get_ports {TX_IN_P[1]}] [get_ports {TX_IN_P[0]}] [get_ports TX_IN_V] [get_ports {Prescale[5]}] [get_ports {Prescale[4]}] [get_ports {Prescale[3]}] [get_ports {Prescale[2]}] [get_ports {Prescale[1]}] [get_ports {Prescale[0]}] [get_ports parity_enable] [get_ports parity_type] [get_ports SI] [get_ports SE] [get_ports scan_clk] [get_ports scan_rst] [get_ports test_mode]] -to [list [get_ports {RX_OUT_P[7]}] [get_ports {RX_OUT_P[6]}] [get_ports {RX_OUT_P[5]}] [get_ports {RX_OUT_P[4]}] [get_ports {RX_OUT_P[3]}] [get_ports {RX_OUT_P[2]}] [get_ports {RX_OUT_P[1]}] [get_ports {RX_OUT_P[0]}] [get_ports RX_OUT_V] [get_ports TX_OUT_S] [get_ports TX_OUT_V] [get_ports parity_error] [get_ports framing_error] [get_ports SO]] 63 | group_path -name INREG -from [list [get_ports RST] [get_ports TX_CLK] [get_ports RX_CLK] [get_ports RX_IN_S] [get_ports {TX_IN_P[7]}] [get_ports {TX_IN_P[6]}] [get_ports {TX_IN_P[5]}] [get_ports {TX_IN_P[4]}] [get_ports {TX_IN_P[3]}] [get_ports {TX_IN_P[2]}] [get_ports {TX_IN_P[1]}] [get_ports {TX_IN_P[0]}] [get_ports TX_IN_V] [get_ports {Prescale[5]}] [get_ports {Prescale[4]}] [get_ports {Prescale[3]}] [get_ports {Prescale[2]}] [get_ports {Prescale[1]}] [get_ports {Prescale[0]}] [get_ports parity_enable] [get_ports parity_type] [get_ports SI] [get_ports SE] [get_ports scan_clk] [get_ports scan_rst] [get_ports test_mode]] 64 | group_path -name REGOUT -to [list [get_ports {RX_OUT_P[7]}] [get_ports {RX_OUT_P[6]}] [get_ports {RX_OUT_P[5]}] [get_ports {RX_OUT_P[4]}] [get_ports {RX_OUT_P[3]}] [get_ports {RX_OUT_P[2]}] [get_ports {RX_OUT_P[1]}] [get_ports {RX_OUT_P[0]}] [get_ports RX_OUT_V] [get_ports TX_OUT_S] [get_ports TX_OUT_V] [get_ports parity_error] [get_ports framing_error] [get_ports SO]] 65 | set_false_path -from [get_clocks UART_CLK_TX] -to [get_clocks UART_CLK_RX] 66 | set_false_path -from [get_clocks UART_CLK_RX] -to [get_clocks UART_CLK_TX] 67 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports RX_IN_S] 68 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[7]}] 69 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[6]}] 70 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[5]}] 71 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[4]}] 72 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[3]}] 73 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[2]}] 74 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[1]}] 75 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[0]}] 76 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports TX_IN_V] 77 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[5]}] 78 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[4]}] 79 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[3]}] 80 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[2]}] 81 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[1]}] 82 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[0]}] 83 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports parity_enable] 84 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports parity_type] 85 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports SI] 86 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports SE] 87 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports scan_rst] 88 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports test_mode] 89 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[7]}] 90 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[6]}] 91 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[5]}] 92 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[4]}] 93 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[3]}] 94 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[2]}] 95 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[1]}] 96 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[0]}] 97 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports RX_OUT_V] 98 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports TX_OUT_S] 99 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports TX_OUT_V] 100 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports parity_error] 101 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports framing_error] 102 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports SO] 103 | set_clock_groups -asynchronous -name UART_CLK_TX_1 -group [list [get_clocks UART_CLK_TX] [get_clocks UART_CLK_RX]] -group [get_clocks SCAN_CLK] 104 | -------------------------------------------------------------------------------- /dft/reports/area.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : area 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Thu Apr 18 17:18:50 2024 7 | **************************************** 8 | 9 | Library(s) Used: 10 | 11 | saed32rvt_ss0p75v125c (File: /home/ICer/Projects/UART/ref/std_cells/saed32rvt_ss0p75v125c.db) 12 | 13 | Number of ports: 287 14 | Number of nets: 683 15 | Number of cells: 368 16 | Number of combinational cells: 297 17 | Number of sequential cells: 55 18 | Number of macros/black boxes: 0 19 | Number of buf/inv: 55 20 | Number of references: 6 21 | 22 | Combinational area: 792.675138 23 | Buf/Inv area: 81.834369 24 | Noncombinational area: 484.906764 25 | Macro/Black Box area: 0.000000 26 | Net Interconnect area: 228.919691 27 | 28 | Total cell area: 1277.581902 29 | Total area: 1506.501594 30 | 31 | Hierarchical area distribution 32 | ------------------------------ 33 | 34 | Global cell area Local cell area 35 | ------------------ --------------------------- 36 | Hierarchical cell Absolute Percent Combi- Noncombi- Black- 37 | Total Total national national boxes Design 38 | -------------------------------- --------- ------- -------- --------- ------ ------------------------------- 39 | UART 1277.5819 100.0 10.6740 0.0000 0.0000 UART 40 | U0_UART_RX 873.4929 68.4 2.5414 0.0000 0.0000 UART_RX_test_1 41 | U0_UART_RX/U0_data_sampling 209.4147 16.4 172.8179 36.5967 0.0000 data_sampling_test_1 42 | U0_UART_RX/U0_deserializer 158.8400 12.4 85.6465 73.1935 0.0000 deserializer_DATA_WIDTH8_test_1 43 | U0_UART_RX/U0_edge_bit_counter 219.3263 17.2 127.8344 91.4918 0.0000 edge_bit_counter_test_1 44 | U0_UART_RX/U0_par_chk 44.2211 3.5 35.0719 9.1492 0.0000 par_chk_DATA_WIDTH8_test_1 45 | U0_UART_RX/U0_stp_chk 13.4696 1.1 4.3204 9.1492 0.0000 stp_chk_test_1 46 | U0_UART_RX/U0_strt_chk 12.9613 1.0 3.8122 9.1492 0.0000 strt_chk_test_1 47 | U0_UART_RX/U0_uart_fsm 212.7185 16.7 185.2710 27.4476 0.0000 uart_rx_fsm_DATA_WIDTH8_test_1 48 | U0_UART_TX 382.9950 30.0 2.5414 0.0000 0.0000 UART_TX_DATA_WIDTH8_test_1 49 | U0_UART_TX/U0_Serializer 153.5030 12.0 52.8620 100.6410 0.0000 Serializer_WIDTH8_test_1 50 | U0_UART_TX/U0_fsm 70.1437 5.5 33.5470 36.5967 0.0000 uart_tx_fsm_test_1 51 | U0_UART_TX/U0_mux 19.3149 1.5 10.1658 9.1492 0.0000 mux_test_1 52 | U0_UART_TX/U0_parity_calc 137.4919 10.8 55.1492 82.3427 0.0000 parity_calc_WIDTH8_test_1 53 | U0_mux2X1 3.5580 0.3 3.5580 0.0000 0.0000 mux2X1_0 54 | U1_mux2X1 3.5580 0.3 3.5580 0.0000 0.0000 mux2X1_2 55 | U2_mux2X1 3.3039 0.3 3.3039 0.0000 0.0000 mux2X1_1 56 | -------------------------------- --------- ------- -------- --------- ------ ------------------------------- 57 | Total 792.6751 484.9068 0.0000 58 | 59 | 1 60 | -------------------------------------------------------------------------------- /dft/reports/constraints.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : constraint 4 | -all_violators 5 | Design : UART 6 | Version: O-2018.06-SP1 7 | Date : Thu Apr 18 17:18:51 2024 8 | **************************************** 9 | 10 | 11 | min_delay/hold ('SCAN_CLK' group) 12 | 13 | Required Actual 14 | Endpoint Path Delay Path Delay Slack 15 | ----------------------------------------------------------------- 16 | U0_UART_RX/U0_data_sampling/sampled_bit_reg/SI 17 | 0.08 0.04 f -0.04 (VIOLATED) 18 | U0_UART_RX/U0_deserializer/P_DATA_reg_0_/SI 19 | 0.08 0.04 f -0.04 (VIOLATED) 20 | U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/SI 21 | 0.08 0.04 f -0.04 (VIOLATED) 22 | U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/SI 23 | 0.08 0.04 f -0.04 (VIOLATED) 24 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/SI 25 | 0.08 0.04 f -0.04 (VIOLATED) 26 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/SI 27 | 0.08 0.04 f -0.04 (VIOLATED) 28 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/SI 29 | 0.08 0.04 f -0.04 (VIOLATED) 30 | U0_UART_RX/U0_par_chk/par_err_reg/SI 31 | 0.08 0.04 f -0.04 (VIOLATED) 32 | U0_UART_RX/U0_stp_chk/stp_err_reg/SI 33 | 0.08 0.04 f -0.04 (VIOLATED) 34 | U0_UART_RX/U0_uart_fsm/current_state_reg_0_/SI 35 | 0.08 0.04 f -0.04 (VIOLATED) 36 | U0_UART_TX/U0_mux/OUT_reg/SI 37 | 0.08 0.04 f -0.04 (VIOLATED) 38 | U0_UART_RX/U0_deserializer/P_DATA_reg_1_/SI 39 | 0.08 0.04 f -0.04 (VIOLATED) 40 | U0_UART_RX/U0_deserializer/P_DATA_reg_2_/SI 41 | 0.08 0.04 f -0.04 (VIOLATED) 42 | U0_UART_RX/U0_deserializer/P_DATA_reg_3_/SI 43 | 0.08 0.04 f -0.04 (VIOLATED) 44 | U0_UART_RX/U0_deserializer/P_DATA_reg_4_/SI 45 | 0.08 0.04 f -0.04 (VIOLATED) 46 | U0_UART_RX/U0_deserializer/P_DATA_reg_5_/SI 47 | 0.08 0.04 f -0.04 (VIOLATED) 48 | U0_UART_RX/U0_deserializer/P_DATA_reg_6_/SI 49 | 0.08 0.04 f -0.04 (VIOLATED) 50 | U0_UART_RX/U0_deserializer/P_DATA_reg_7_/SI 51 | 0.08 0.04 f -0.04 (VIOLATED) 52 | U0_UART_TX/U0_Serializer/DATA_V_reg_1_/SI 53 | 0.08 0.04 f -0.04 (VIOLATED) 54 | U0_UART_TX/U0_Serializer/DATA_V_reg_2_/SI 55 | 0.08 0.04 f -0.04 (VIOLATED) 56 | U0_UART_TX/U0_Serializer/DATA_V_reg_3_/SI 57 | 0.08 0.04 f -0.04 (VIOLATED) 58 | U0_UART_TX/U0_Serializer/DATA_V_reg_4_/SI 59 | 0.08 0.04 f -0.04 (VIOLATED) 60 | U0_UART_TX/U0_Serializer/DATA_V_reg_5_/SI 61 | 0.08 0.04 f -0.04 (VIOLATED) 62 | U0_UART_TX/U0_Serializer/DATA_V_reg_6_/SI 63 | 0.08 0.04 f -0.04 (VIOLATED) 64 | U0_UART_TX/U0_Serializer/DATA_V_reg_7_/SI 65 | 0.08 0.04 f -0.04 (VIOLATED) 66 | U0_UART_TX/U0_Serializer/ser_count_reg_0_/SI 67 | 0.08 0.04 f -0.04 (VIOLATED) 68 | U0_UART_TX/U0_fsm/current_state_reg_0_/SI 69 | 0.08 0.04 f -0.04 (VIOLATED) 70 | U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/SI 71 | 0.08 0.04 f -0.04 (VIOLATED) 72 | U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/SI 73 | 0.08 0.04 f -0.04 (VIOLATED) 74 | U0_UART_RX/U0_data_sampling/Samples_reg_1_/SI 75 | 0.08 0.07 f -0.01 (VIOLATED) 76 | U0_UART_RX/U0_uart_fsm/current_state_reg_2_/SI 77 | 0.08 0.07 f -0.01 (VIOLATED) 78 | U0_UART_RX/U0_data_sampling/Samples_reg_2_/SI 79 | 0.08 0.07 f -0.01 (VIOLATED) 80 | U0_UART_TX/U0_fsm/busy_reg/SI 81 | 0.08 0.07 f -0.01 (VIOLATED) 82 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/SI 83 | 0.08 0.07 f -0.01 (VIOLATED) 84 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/SI 85 | 0.08 0.07 f -0.01 (VIOLATED) 86 | U0_UART_RX/U0_stp_chk/stp_err_reg/D 87 | 0.08 0.07 r -0.01 (VIOLATED) 88 | U0_UART_TX/U0_Serializer/ser_count_reg_1_/SI 89 | 0.08 0.08 f 0.00 (VIOLATED: increase significant digits) 90 | 91 | 92 | 1 93 | -------------------------------------------------------------------------------- /dft/reports/power.rpt: -------------------------------------------------------------------------------- 1 | Loading db file '/home/ICer/Projects/UART/ref/std_cells/saed32rvt_ss0p75v125c.db' 2 | Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) 3 | Warning: Design has unannotated primary inputs. (PWR-414) 4 | Warning: Design has unannotated sequential cell outputs. (PWR-415) 5 | 6 | **************************************** 7 | Report : power 8 | -hier 9 | -analysis_effort low 10 | Design : UART 11 | Version: O-2018.06-SP1 12 | Date : Thu Apr 18 17:18:51 2024 13 | **************************************** 14 | 15 | 16 | Library(s) Used: 17 | 18 | saed32rvt_ss0p75v125c (File: /home/ICer/Projects/UART/ref/std_cells/saed32rvt_ss0p75v125c.db) 19 | 20 | 21 | Operating Conditions: ss0p75v125c Library: saed32rvt_ss0p75v125c 22 | Wire Load Model Mode: enclosed 23 | 24 | Design Wire Load Model Library 25 | ------------------------------------------------ 26 | UART 8000 saed32rvt_ss0p75v125c 27 | mux2X1_0 ForQA saed32rvt_ss0p75v125c 28 | mux2X1_1 ForQA saed32rvt_ss0p75v125c 29 | UART_TX_DATA_WIDTH8_test_1 30 | 8000 saed32rvt_ss0p75v125c 31 | UART_RX_test_1 8000 saed32rvt_ss0p75v125c 32 | uart_tx_fsm_test_1 ForQA saed32rvt_ss0p75v125c 33 | Serializer_WIDTH8_test_1 34 | ForQA saed32rvt_ss0p75v125c 35 | mux_test_1 ForQA saed32rvt_ss0p75v125c 36 | parity_calc_WIDTH8_test_1 37 | ForQA saed32rvt_ss0p75v125c 38 | uart_rx_fsm_DATA_WIDTH8_test_1 39 | 8000 saed32rvt_ss0p75v125c 40 | edge_bit_counter_test_1 41 | 8000 saed32rvt_ss0p75v125c 42 | data_sampling_test_1 8000 saed32rvt_ss0p75v125c 43 | deserializer_DATA_WIDTH8_test_1 44 | ForQA saed32rvt_ss0p75v125c 45 | strt_chk_test_1 ForQA saed32rvt_ss0p75v125c 46 | par_chk_DATA_WIDTH8_test_1 47 | ForQA saed32rvt_ss0p75v125c 48 | stp_chk_test_1 ForQA saed32rvt_ss0p75v125c 49 | mux2X1_2 ForQA saed32rvt_ss0p75v125c 50 | 51 | 52 | Global Operating Voltage = 0.75 53 | Power-specific unit information : 54 | Voltage Units = 1V 55 | Capacitance Units = 1.000000ff 56 | Time Units = 1ns 57 | Dynamic Power Units = 1uW (derived from V,C,T units) 58 | Leakage Power Units = 1pW 59 | 60 | 61 | -------------------------------------------------------------------------------- 62 | Switch Int Leak Total 63 | Hierarchy Power Power Power Power % 64 | -------------------------------------------------------------------------------- 65 | UART 0.486 6.635 2.19e+07 28.989 100.0 66 | U0_UART_RX (UART_RX_test_1) 0.169 3.191 1.37e+07 17.046 58.8 67 | U0_stp_chk (stp_chk_test_1) 2.03e-03 0.119 2.76e+05 0.397 1.4 68 | U0_par_chk (par_chk_DATA_WIDTH8_test_1) 69 | 4.03e-03 0.137 8.41e+05 0.982 3.4 70 | U0_strt_chk (strt_chk_test_1) 1.78e-03 0.116 2.35e+05 0.353 1.2 71 | U0_deserializer (deserializer_DATA_WIDTH8_test_1) 72 | 2.52e-02 0.703 2.61e+06 3.342 11.5 73 | U0_data_sampling (data_sampling_test_1) 74 | 3.48e-02 0.385 2.99e+06 3.414 11.8 75 | U0_edge_bit_counter (edge_bit_counter_test_1) 76 | 5.96e-02 1.312 3.84e+06 5.213 18.0 77 | U0_uart_fsm (uart_rx_fsm_DATA_WIDTH8_test_1) 78 | 3.22e-02 0.418 2.76e+06 3.207 11.1 79 | U0_UART_TX (UART_TX_DATA_WIDTH8_test_1) 80 | 0.102 3.353 7.02e+06 10.477 36.1 81 | U0_parity_calc (parity_calc_WIDTH8_test_1) 82 | 2.79e-02 1.171 2.57e+06 3.771 13.0 83 | U0_mux (mux_test_1) 6.89e-03 0.163 3.36e+05 0.506 1.7 84 | U0_Serializer (Serializer_WIDTH8_test_1) 85 | 3.57e-02 1.450 2.71e+06 4.199 14.5 86 | U0_fsm (uart_tx_fsm_test_1) 2.36e-02 0.567 1.27e+06 1.863 6.4 87 | U2_mux2X1 (mux2X1_1) 4.27e-04 9.30e-04 4.08e+04 4.22e-02 0.1 88 | U1_mux2X1 (mux2X1_2) 0.101 2.47e-02 6.92e+04 0.195 0.7 89 | U0_mux2X1 (mux2X1_0) 0.113 2.49e-02 6.92e+04 0.207 0.7 90 | 1 91 | -------------------------------------------------------------------------------- /dft/reports/qor.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : qor 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Thu Apr 18 17:18:51 2024 7 | **************************************** 8 | 9 | 10 | Timing Path Group 'SCAN_CLK' 11 | ----------------------------------- 12 | Levels of Logic: 8.00 13 | Critical Path Length: 1.96 14 | Critical Path Slack: 97.48 15 | Critical Path Clk Period: 100.00 16 | Total Negative Slack: 0.00 17 | No. of Violating Paths: 0.00 18 | Worst Hold Violation: -0.04 19 | Total Hold Violation: -1.26 20 | No. of Hold Violations: 37.00 21 | ----------------------------------- 22 | 23 | 24 | Cell Count 25 | ----------------------------------- 26 | Hierarchical Cell Count: 16 27 | Hierarchical Port Count: 247 28 | Leaf Cell Count: 350 29 | Buf/Inv Cell Count: 55 30 | Buf Cell Count: 3 31 | Inv Cell Count: 52 32 | CT Buf/Inv Cell Count: 0 33 | Combinational Cell Count: 297 34 | Sequential Cell Count: 53 35 | Macro Count: 0 36 | ----------------------------------- 37 | 38 | 39 | Area 40 | ----------------------------------- 41 | Combinational Area: 792.675138 42 | Noncombinational Area: 484.906764 43 | Buf/Inv Area: 81.834369 44 | Total Buffer Area: 15.76 45 | Total Inverter Area: 66.08 46 | Macro/Black Box Area: 0.000000 47 | Net Area: 228.919691 48 | ----------------------------------- 49 | Cell Area: 1277.581902 50 | Design Area: 1506.501594 51 | 52 | 53 | Design Rules 54 | ----------------------------------- 55 | Total Number of Nets: 437 56 | Nets With Violations: 0 57 | Max Trans Violations: 0 58 | Max Cap Violations: 0 59 | ----------------------------------- 60 | 61 | 62 | Hostname: IC_EDA 63 | 64 | Compile CPU Statistics 65 | ----------------------------------------- 66 | Resource Sharing: 0.00 67 | Logic Optimization: 0.02 68 | Mapping Optimization: 0.26 69 | ----------------------------------------- 70 | Overall Compile Time: 2.77 71 | Overall Compile Wall Clock Time: 3.27 72 | 73 | -------------------------------------------------------------------- 74 | 75 | Design WNS: 0.00 TNS: 0.00 Number of Violating Paths: 0 76 | 77 | 78 | Design (Hold) WNS: 0.04 TNS: 1.26 Number of Violating Paths: 37 79 | 80 | -------------------------------------------------------------------- 81 | 82 | 83 | 1 84 | -------------------------------------------------------------------------------- /dft/script/dft_script.tcl: -------------------------------------------------------------------------------- 1 | ########################### Define Top Module ############################ 2 | 3 | set top_module UART 4 | 5 | ########################### Define SVF File ############################ 6 | set_svf $top_module.svf 7 | 8 | ##################### Define Working Library Directory ###################### 9 | 10 | define_design_lib work -path ./work 11 | 12 | ################## Design Compiler Library Files #setup ###################### 13 | 14 | puts "###########################################" 15 | puts "# #setting Design Libraries #" 16 | puts "###########################################" 17 | 18 | #Add the path of the libraries to the search_path variable 19 | lappend search_path /home/ICer/Projects/UART/ref/std_cells 20 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TX 21 | lappend search_path /home/ICer/Projects/UART/rtl/UART_RX 22 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TOP_DFT 23 | 24 | set SSLIB "saed32rvt_ss0p75v125c.db" 25 | 26 | ## Standard Cell libraries 27 | set target_library [list $SSLIB] 28 | 29 | ## Standard Cell & Hard Macros libraries 30 | set link_library [list * $SSLIB] 31 | 32 | ######################## Reading RTL Files ################################# 33 | 34 | puts "###########################################" 35 | puts "# Reading RTL Files #" 36 | puts "###########################################" 37 | 38 | set file_format verilog 39 | 40 | analyze -format $file_format { mux.v \ 41 | parity_calc.v \ 42 | Serializer.v \ 43 | uart_tx_fsm.v \ 44 | UART_TX.v \ 45 | data_sampling.v \ 46 | deserializer.v \ 47 | edge_bit_counter.v \ 48 | par_chk.v \ 49 | stp_chk.v \ 50 | strt_chk.v \ 51 | uart_rx_fsm.v \ 52 | UART_RX.v \ 53 | mux2X1.v \ 54 | UART.v } 55 | 56 | 57 | elaborate -lib work UART 58 | 59 | 60 | ###################### Defining toplevel ################################### 61 | 62 | current_design $top_module 63 | 64 | #################### Liniking All The Design Parts ######################### 65 | puts "###############################################" 66 | puts "######## Liniking All The Design Parts ########" 67 | puts "###############################################" 68 | 69 | link 70 | 71 | #################### Liniking All The Design Parts ######################### 72 | puts "###############################################" 73 | puts "######## checking design consistency ##########" 74 | puts "###############################################" 75 | 76 | check_design 77 | 78 | ############################### Path groups ################################ 79 | puts "###############################################" 80 | puts "################ Path groups ##################" 81 | puts "###############################################" 82 | 83 | group_path -name INREG -from [all_inputs] 84 | group_path -name REGOUT -to [all_outputs] 85 | group_path -name INOUT -from [all_inputs] -to [all_outputs] 86 | 87 | #################### Define Design Constraints ######################### 88 | puts "###############################################" 89 | puts "############ Design Constraints #### ##########" 90 | puts "###############################################" 91 | 92 | source -echo ./cons.tcl 93 | 94 | #################### Archirecture Scan Chains ######################### 95 | puts "###############################################" 96 | puts "############ Configure scan chains ############" 97 | puts "###############################################" 98 | 99 | set_scan_configuration -clock_mixing no_mix -style multiplexed_flip_flop -replace true -max_length 100 100 | 101 | ###################### Mapping and optimization ######################## 102 | puts "###############################################" 103 | puts "######## Preventing Multiple Port Nets ########" 104 | puts "###############################################" 105 | 106 | set case_analysis_with_logic_constants true 107 | 108 | set_fix_multiple_port_nets -all 109 | 110 | ###################### Mapping and optimization ######################## 111 | puts "###############################################" 112 | puts "########## Mapping & Optimization #############" 113 | puts "###############################################" 114 | 115 | compile -scan 116 | 117 | set_svf -off 118 | 119 | ################################################################### 120 | # Setting Test Timing Variables 121 | ################################################################### 122 | 123 | # Preclock Measure Protocol (default protocol) 124 | set test_default_period 100 125 | set test_default_delay 0 126 | set test_default_bidir_delay 0 127 | set test_default_strobe 20 128 | set test_default_strobe_width 0 129 | 130 | ########################## Define DFT Signals ########################## 131 | 132 | set_dft_signal -port [get_ports scan_clk] -type ScanClock -view existing_dft -timing {30 60} 133 | set_dft_signal -port [get_ports scan_rst] -type Reset -view existing_dft -active_state 0 134 | set_dft_signal -port [get_ports test_mode] -type Constant -view existing_dft -active_state 1 135 | set_dft_signal -port [get_ports test_mode] -type TestMode -view spec -active_state 1 136 | set_dft_signal -port [get_ports SE] -type ScanEnable -view spec -active_state 1 -usage scan 137 | set_dft_signal -port [get_ports SI] -type ScanDataIn -view spec 138 | set_dft_signal -port [get_ports SO] -type ScanDataOut -view spec 139 | 140 | ############################# Create Test Protocol ##################### 141 | 142 | create_test_protocol 143 | 144 | ###################### Pre-DFT Design Rule Checking #################### 145 | 146 | dft_drc -verbose 147 | 148 | ############################# Preview DFT ############################## 149 | 150 | preview_dft -show scan_summary 151 | 152 | ############################# Insert DFT ############################### 153 | 154 | insert_dft 155 | 156 | ######################## Optimize Logic post DFT ####################### 157 | 158 | compile -scan -incremental 159 | 160 | ###################### Design Rule Checking post DFT ################### 161 | 162 | dft_drc -verbose -coverage_estimate 163 | 164 | ############################################################################# 165 | # Write out Design after initial compile 166 | ############################################################################# 167 | puts "###############################################" 168 | puts "########## Remove Special Characters ##########" 169 | puts "###############################################" 170 | 171 | set verilogout_equation false 172 | 173 | change_names -rule verilog -hierarchy 174 | 175 | write_file -format verilog -hierarchy -output UART_mapped.v 176 | write_file -format ddc -hierarchy -output UART_mapped.ddc 177 | write_sdc -nosplit UART_mapped.sdc 178 | write_sdf UART_mapped.sdf 179 | 180 | # Generates SCANDEF scan chain information for performing scan chain reordering in the physical implementation flow. 181 | write_scan_def 182 | check_scan_def 183 | ################# reporting ####################### 184 | 185 | report_area -hierarchy > reports/area.rpt 186 | report_power -hierarchy > reports/power.rpt 187 | report_timing -max_paths 100 -delay_type min > reports/hold.rpt 188 | report_timing -max_paths 100 -delay_type max > reports/setup.rpt 189 | report_constraint -all_violators > reports/constraints.rpt 190 | report_qor > reports/qor.rpt 191 | 192 | ################# starting graphical user interface ####################### 193 | 194 | gui_start 195 | 196 | 197 | -------------------------------------------------------------------------------- /fm/post_DFT/fm_reports/aborted_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : aborted_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 16:39:22 2024 8 | ************************************************** 9 | 10 | No aborted compare points. 11 | 12 | 1 13 | -------------------------------------------------------------------------------- /fm/post_DFT/fm_reports/failing_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : failing_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 16:39:22 2024 8 | ************************************************** 9 | 10 | No failing compare points. 11 | 12 | 1 13 | -------------------------------------------------------------------------------- /fm/post_DFT/fm_reports/passing_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : passing_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 16:39:22 2024 8 | ************************************************** 9 | 10 | 66 Passing compare points: 11 | 12 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg[0] 13 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg_0_ 14 | 15 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg[1] 16 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg_1_ 17 | 18 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg[2] 19 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg_2_ 20 | 21 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/sampled_bit_reg 22 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/sampled_bit_reg 23 | 24 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[0] 25 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_0_ 26 | 27 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[1] 28 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_1_ 29 | 30 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[2] 31 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_2_ 32 | 33 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[3] 34 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_3_ 35 | 36 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[4] 37 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_4_ 38 | 39 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[5] 40 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_5_ 41 | 42 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[6] 43 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_6_ 44 | 45 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[7] 46 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_7_ 47 | 48 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[0] 49 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ 50 | 51 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[1] 52 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ 53 | 54 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[2] 55 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ 56 | 57 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[3] 58 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ 59 | 60 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[0] 61 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ 62 | 63 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[1] 64 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ 65 | 66 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[2] 67 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ 68 | 69 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[3] 70 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ 71 | 72 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[4] 73 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ 74 | 75 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[5] 76 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ 77 | 78 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_par_chk/par_err_reg 79 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_par_chk/par_err_reg 80 | 81 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_stp_chk/stp_err_reg 82 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_stp_chk/stp_err_reg 83 | 84 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_strt_chk/strt_glitch_reg 85 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_strt_chk/strt_glitch_reg 86 | 87 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg[0] 88 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg_0_ 89 | 90 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg[1] 91 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg_1_ 92 | 93 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg[2] 94 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg_2_ 95 | 96 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[0] 97 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_0_ 98 | 99 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[1] 100 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_1_ 101 | 102 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[2] 103 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_2_ 104 | 105 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[3] 106 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_3_ 107 | 108 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[4] 109 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_4_ 110 | 111 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[5] 112 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_5_ 113 | 114 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[6] 115 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_6_ 116 | 117 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[7] 118 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_7_ 119 | 120 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg[0] 121 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg_0_ 122 | 123 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg[1] 124 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg_1_ 125 | 126 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg[2] 127 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg_2_ 128 | 129 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/busy_reg 130 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/busy_reg 131 | 132 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg[0] 133 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg_0_ 134 | 135 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg[1] 136 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg_1_ 137 | 138 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg[2] 139 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg_2_ 140 | 141 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_mux/OUT_reg 142 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_mux/OUT_reg 143 | 144 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[0] 145 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ 146 | 147 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[1] 148 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ 149 | 150 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[2] 151 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ 152 | 153 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[3] 154 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ 155 | 156 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[4] 157 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ 158 | 159 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[5] 160 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ 161 | 162 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[6] 163 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ 164 | 165 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[7] 166 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ 167 | 168 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/parity_reg 169 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/parity_reg 170 | 171 | Ref Port Ref:/WORK/UART/RX_OUT_P[0] 172 | Impl Port Imp:/WORK/UART/RX_OUT_P[0] 173 | 174 | Ref Port Ref:/WORK/UART/RX_OUT_P[1] 175 | Impl Port Imp:/WORK/UART/RX_OUT_P[1] 176 | 177 | Ref Port Ref:/WORK/UART/RX_OUT_P[2] 178 | Impl Port Imp:/WORK/UART/RX_OUT_P[2] 179 | 180 | Ref Port Ref:/WORK/UART/RX_OUT_P[3] 181 | Impl Port Imp:/WORK/UART/RX_OUT_P[3] 182 | 183 | Ref Port Ref:/WORK/UART/RX_OUT_P[4] 184 | Impl Port Imp:/WORK/UART/RX_OUT_P[4] 185 | 186 | Ref Port Ref:/WORK/UART/RX_OUT_P[5] 187 | Impl Port Imp:/WORK/UART/RX_OUT_P[5] 188 | 189 | Ref Port Ref:/WORK/UART/RX_OUT_P[6] 190 | Impl Port Imp:/WORK/UART/RX_OUT_P[6] 191 | 192 | Ref Port Ref:/WORK/UART/RX_OUT_P[7] 193 | Impl Port Imp:/WORK/UART/RX_OUT_P[7] 194 | 195 | Ref Port Ref:/WORK/UART/RX_OUT_V 196 | Impl Port Imp:/WORK/UART/RX_OUT_V 197 | 198 | Ref Port Ref:/WORK/UART/TX_OUT_S 199 | Impl Port Imp:/WORK/UART/TX_OUT_S 200 | 201 | Ref Port Ref:/WORK/UART/TX_OUT_V 202 | Impl Port Imp:/WORK/UART/TX_OUT_V 203 | 204 | Ref Port Ref:/WORK/UART/framing_error 205 | Impl Port Imp:/WORK/UART/framing_error 206 | 207 | Ref Port Ref:/WORK/UART/parity_error 208 | Impl Port Imp:/WORK/UART/parity_error 209 | 210 | [BBNet: multiply-driven net 211 | BBPin: black-box pin 212 | Cut: cut-point 213 | DFF: non-constant DFF register 214 | DFF0: constant 0 DFF register 215 | DFF1: constant 1 DFF register 216 | DFFX: constant X DFF register 217 | DFF0X: constrained 0X DFF register 218 | DFF1X: constrained 1X DFF register 219 | LAT: non-constant latch register 220 | LAT0: constant 0 latch register 221 | LAT1: constant 1 latch register 222 | LATX: constant X latch register 223 | LAT0X: constrained 0X latch register 224 | LAT1X: constrained 1X latch register 225 | LATCG: clock-gating latch register 226 | TLA: transparent latch register 227 | TLA0X: transparent constrained 0X latch register 228 | TLA1X: transparent constrained 1X latch register 229 | Loop: cycle break point 230 | Port: primary (top-level) port 231 | Und: undriven signal cut-point 232 | Unk: unknown signal cut-point] 233 | 234 | 1 235 | -------------------------------------------------------------------------------- /fm/post_DFT/fm_reports/unverified_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : unverified_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 16:39:22 2024 8 | ************************************************** 9 | 10 | No unverified compare points. 11 | 12 | 1 13 | -------------------------------------------------------------------------------- /fm/post_DFT/fm_script.tcl: -------------------------------------------------------------------------------- 1 | 2 | ############################ Search PATH ################################ 3 | 4 | lappend search_path /home/ICer/Projects/UART/ref/std_cells 5 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TX 6 | lappend search_path /home/ICer/Projects/UART/rtl/UART_RX 7 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TOP_DFT 8 | 9 | 10 | ########################### Define Top Module ############################ 11 | 12 | set system_top UART 13 | 14 | ################################################################### 15 | ############################ Guidance ############################# 16 | ################################################################### 17 | 18 | # Synopsys setup variable 19 | set synopsys_auto_setup true 20 | 21 | # Formality Setup File 22 | set_svf "/home/ICer/Projects/UART/dft/UART.svf" 23 | 24 | 25 | ####################### Read Reference tech libs ######################## 26 | 27 | set SSLIB "saed32rvt_ss0p75v125c.db" 28 | 29 | read_db -container Ref [list $SSLIB] 30 | 31 | ################################################################### 32 | ###################### Reference Container ######################## 33 | ################################################################### 34 | 35 | 36 | read_verilog -container Ref "{mux.v \ 37 | parity_calc.v \ 38 | Serializer.v \ 39 | uart_tx_fsm.v \ 40 | UART_TX.v \ 41 | data_sampling.v \ 42 | deserializer.v \ 43 | edge_bit_counter.v \ 44 | par_chk.v \ 45 | stp_chk.v \ 46 | strt_chk.v \ 47 | uart_rx_fsm.v \ 48 | UART_RX.v \ 49 | mux2X1.v \ 50 | UART.v }" 51 | 52 | 53 | # set the top Reference Design 54 | set_reference_design $system_top 55 | 56 | set_top $system_top 57 | 58 | ################################################################### 59 | #################### Implementation Container ##################### 60 | ################################################################### 61 | 62 | read_db -container Imp [list $SSLIB] 63 | 64 | 65 | # Read Implementation Design Files 66 | read_verilog -netlist -container Imp "/home/ICer/Projects/UART/dft/UART_mapped.v" 67 | 68 | 69 | # set the top Implementation Design 70 | set_implementation_design $system_top 71 | 72 | set_top $system_top 73 | 74 | ########################## Don't verify ########################### 75 | 76 | # do not verify scan in & scan out ports as a compare point as it is existed only after synthesis and not existed in the RTL 77 | 78 | #scan in 79 | set_dont_verify_points -type port Ref:/WORK/*/SI 80 | set_dont_verify_points -type port Imp:/WORK/*/SI 81 | 82 | #scan_out 83 | set_dont_verify_points -type port Ref:/WORK/*/SO 84 | set_dont_verify_points -type port Imp:/WORK/*/SO 85 | 86 | 87 | ############################### constants ##################################### 88 | 89 | # all atpg enable (test_mode, scan_enable) are zero during formal compare 90 | 91 | #test_mode 92 | set_constant Ref:/WORK/*/test_mode 0 93 | set_constant Imp:/WORK/*/test_mode 0 94 | 95 | #scan_enable 96 | set_constant Ref:/WORK/*/SE 0 97 | set_constant Imp:/WORK/*/SE 0 98 | 99 | 100 | ###################### Matching Compare points #################### 101 | 102 | match 103 | 104 | ######################### Run Verification ######################## 105 | 106 | set successful [verify] 107 | if {!$successful} { 108 | diagnose 109 | analyze_points -failing 110 | } 111 | 112 | ########################### Reporting ############################# 113 | report_passing_points > "fm_reports/passing_points.rpt" 114 | report_failing_points > "fm_reports/failing_points.rpt" 115 | report_aborted_points > "fm_reports/aborted_points.rpt" 116 | report_unverified_points > "fm_reports/unverified_points.rpt" 117 | 118 | 119 | start_gui 120 | 121 | -------------------------------------------------------------------------------- /fm/post_synthesis/fm_reports/aborted_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : aborted_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 13:45:39 2024 8 | ************************************************** 9 | 10 | No aborted compare points. 11 | 12 | 1 13 | -------------------------------------------------------------------------------- /fm/post_synthesis/fm_reports/failing_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : failing_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 13:45:39 2024 8 | ************************************************** 9 | 10 | No failing compare points. 11 | 12 | 1 13 | -------------------------------------------------------------------------------- /fm/post_synthesis/fm_reports/passing_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : passing_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 13:45:39 2024 8 | ************************************************** 9 | 10 | 66 Passing compare points: 11 | 12 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg[0] 13 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg_0_ 14 | 15 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg[1] 16 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg_1_ 17 | 18 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg[2] 19 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/Samples_reg_2_ 20 | 21 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_data_sampling/sampled_bit_reg 22 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_data_sampling/sampled_bit_reg 23 | 24 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[0] 25 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_0_ 26 | 27 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[1] 28 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_1_ 29 | 30 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[2] 31 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_2_ 32 | 33 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[3] 34 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_3_ 35 | 36 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[4] 37 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_4_ 38 | 39 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[5] 40 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_5_ 41 | 42 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[6] 43 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_6_ 44 | 45 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg[7] 46 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_deserializer/P_DATA_reg_7_ 47 | 48 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[0] 49 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ 50 | 51 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[1] 52 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ 53 | 54 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[2] 55 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ 56 | 57 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg[3] 58 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ 59 | 60 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[0] 61 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ 62 | 63 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[1] 64 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ 65 | 66 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[2] 67 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ 68 | 69 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[3] 70 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ 71 | 72 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[4] 73 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ 74 | 75 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg[5] 76 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ 77 | 78 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_par_chk/par_err_reg 79 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_par_chk/par_err_reg 80 | 81 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_stp_chk/stp_err_reg 82 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_stp_chk/stp_err_reg 83 | 84 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_strt_chk/strt_glitch_reg 85 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_strt_chk/strt_glitch_reg 86 | 87 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg[0] 88 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg_0_ 89 | 90 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg[1] 91 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg_1_ 92 | 93 | Ref DFF Ref:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg[2] 94 | Impl DFF Imp:/WORK/UART/U0_UART_RX/U0_uart_fsm/current_state_reg_2_ 95 | 96 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[0] 97 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_0_ 98 | 99 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[1] 100 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_1_ 101 | 102 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[2] 103 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_2_ 104 | 105 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[3] 106 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_3_ 107 | 108 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[4] 109 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_4_ 110 | 111 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[5] 112 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_5_ 113 | 114 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[6] 115 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_6_ 116 | 117 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg[7] 118 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/DATA_V_reg_7_ 119 | 120 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg[0] 121 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg_0_ 122 | 123 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg[1] 124 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg_1_ 125 | 126 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg[2] 127 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_Serializer/ser_count_reg_2_ 128 | 129 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/busy_reg 130 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/busy_reg 131 | 132 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg[0] 133 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg_0_ 134 | 135 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg[1] 136 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg_1_ 137 | 138 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg[2] 139 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_fsm/current_state_reg_2_ 140 | 141 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_mux/OUT_reg 142 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_mux/OUT_reg 143 | 144 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[0] 145 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ 146 | 147 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[1] 148 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ 149 | 150 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[2] 151 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ 152 | 153 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[3] 154 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ 155 | 156 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[4] 157 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ 158 | 159 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[5] 160 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ 161 | 162 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[6] 163 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ 164 | 165 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg[7] 166 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ 167 | 168 | Ref DFF Ref:/WORK/UART/U0_UART_TX/U0_parity_calc/parity_reg 169 | Impl DFF Imp:/WORK/UART/U0_UART_TX/U0_parity_calc/parity_reg 170 | 171 | Ref Port Ref:/WORK/UART/RX_OUT_P[0] 172 | Impl Port Imp:/WORK/UART/RX_OUT_P[0] 173 | 174 | Ref Port Ref:/WORK/UART/RX_OUT_P[1] 175 | Impl Port Imp:/WORK/UART/RX_OUT_P[1] 176 | 177 | Ref Port Ref:/WORK/UART/RX_OUT_P[2] 178 | Impl Port Imp:/WORK/UART/RX_OUT_P[2] 179 | 180 | Ref Port Ref:/WORK/UART/RX_OUT_P[3] 181 | Impl Port Imp:/WORK/UART/RX_OUT_P[3] 182 | 183 | Ref Port Ref:/WORK/UART/RX_OUT_P[4] 184 | Impl Port Imp:/WORK/UART/RX_OUT_P[4] 185 | 186 | Ref Port Ref:/WORK/UART/RX_OUT_P[5] 187 | Impl Port Imp:/WORK/UART/RX_OUT_P[5] 188 | 189 | Ref Port Ref:/WORK/UART/RX_OUT_P[6] 190 | Impl Port Imp:/WORK/UART/RX_OUT_P[6] 191 | 192 | Ref Port Ref:/WORK/UART/RX_OUT_P[7] 193 | Impl Port Imp:/WORK/UART/RX_OUT_P[7] 194 | 195 | Ref Port Ref:/WORK/UART/RX_OUT_V 196 | Impl Port Imp:/WORK/UART/RX_OUT_V 197 | 198 | Ref Port Ref:/WORK/UART/TX_OUT_S 199 | Impl Port Imp:/WORK/UART/TX_OUT_S 200 | 201 | Ref Port Ref:/WORK/UART/TX_OUT_V 202 | Impl Port Imp:/WORK/UART/TX_OUT_V 203 | 204 | Ref Port Ref:/WORK/UART/framing_error 205 | Impl Port Imp:/WORK/UART/framing_error 206 | 207 | Ref Port Ref:/WORK/UART/parity_error 208 | Impl Port Imp:/WORK/UART/parity_error 209 | 210 | [BBNet: multiply-driven net 211 | BBPin: black-box pin 212 | Cut: cut-point 213 | DFF: non-constant DFF register 214 | DFF0: constant 0 DFF register 215 | DFF1: constant 1 DFF register 216 | DFFX: constant X DFF register 217 | DFF0X: constrained 0X DFF register 218 | DFF1X: constrained 1X DFF register 219 | LAT: non-constant latch register 220 | LAT0: constant 0 latch register 221 | LAT1: constant 1 latch register 222 | LATX: constant X latch register 223 | LAT0X: constrained 0X latch register 224 | LAT1X: constrained 1X latch register 225 | LATCG: clock-gating latch register 226 | TLA: transparent latch register 227 | TLA0X: transparent constrained 0X latch register 228 | TLA1X: transparent constrained 1X latch register 229 | Loop: cycle break point 230 | Port: primary (top-level) port 231 | Und: undriven signal cut-point 232 | Unk: unknown signal cut-point] 233 | 234 | 1 235 | -------------------------------------------------------------------------------- /fm/post_synthesis/fm_reports/unverified_points.rpt: -------------------------------------------------------------------------------- 1 | ************************************************** 2 | Report : unverified_points 3 | 4 | Reference : Ref:/WORK/UART 5 | Implementation : Imp:/WORK/UART 6 | Version : O-2018.06-SP1 7 | Date : Thu Apr 18 13:45:39 2024 8 | ************************************************** 9 | 10 | No unverified compare points. 11 | 12 | 1 13 | -------------------------------------------------------------------------------- /fm/post_synthesis/fm_script.tcl: -------------------------------------------------------------------------------- 1 | 2 | ############################ Search PATH ################################ 3 | 4 | lappend search_path /home/ICer/Projects/UART/ref/std_cells 5 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TX 6 | lappend search_path /home/ICer/Projects/UART/rtl/UART_RX 7 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TOP 8 | 9 | 10 | ########################### Define Top Module ############################ 11 | 12 | set system_top UART 13 | 14 | ################################################################### 15 | ############################ Guidance ############################# 16 | ################################################################### 17 | 18 | # Synopsys setup variable 19 | set synopsys_auto_setup true 20 | 21 | # Formality Setup File 22 | set_svf "/home/ICer/Projects/UART/syn/UART.svf" 23 | 24 | 25 | ####################### Read Reference tech libs ######################## 26 | 27 | set SSLIB "saed32rvt_ss0p75v125c.db" 28 | 29 | read_db -container Ref [list $SSLIB] 30 | 31 | ################################################################### 32 | ###################### Reference Container ######################## 33 | ################################################################### 34 | 35 | 36 | read_verilog -container Ref "{mux.v \ 37 | parity_calc.v \ 38 | Serializer.v \ 39 | uart_tx_fsm.v \ 40 | UART_TX.v \ 41 | data_sampling.v \ 42 | deserializer.v \ 43 | edge_bit_counter.v \ 44 | par_chk.v \ 45 | stp_chk.v \ 46 | strt_chk.v \ 47 | uart_rx_fsm.v \ 48 | UART_RX.v \ 49 | UART.v }" 50 | 51 | 52 | # set the top Reference Design 53 | set_reference_design $system_top 54 | 55 | set_top -auto 56 | 57 | ################################################################### 58 | #################### Implementation Container ##################### 59 | ################################################################### 60 | 61 | read_db -container Imp [list $SSLIB] 62 | 63 | 64 | # Read Implementation Design Files 65 | read_verilog -netlist -container Imp "/home/ICer/Projects/UART/syn/UART_mapped.v" 66 | 67 | 68 | # set the top Implementation Design 69 | set_implementation_design $system_top 70 | 71 | set_top $system_top 72 | 73 | 74 | ###################### Matching Compare points #################### 75 | 76 | match 77 | 78 | ######################### Run Verification ######################## 79 | 80 | set successful [verify] 81 | if {!$successful} { 82 | diagnose 83 | analyze_points -failing 84 | } 85 | 86 | ########################### Reporting ############################# 87 | report_passing_points > "fm_reports/passing_points.rpt" 88 | report_failing_points > "fm_reports/failing_points.rpt" 89 | report_aborted_points > "fm_reports/aborted_points.rpt" 90 | report_unverified_points > "fm_reports/unverified_points.rpt" 91 | 92 | 93 | start_gui 94 | 95 | -------------------------------------------------------------------------------- /fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/data_sampling_DP_OP_13J1_124_7424_J1_0.b: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/data_sampling_DP_OP_13J1_124_7424_J1_0.b -------------------------------------------------------------------------------- /fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/deserializer_DATA_WIDTH8_DP_OP_3J1_126_2816_J1_0.b: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/deserializer_DATA_WIDTH8_DP_OP_3J1_126_2816_J1_0.b -------------------------------------------------------------------------------- /fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/edge_bit_counter_DP_OP_10J1_125_9618_J1_0.b: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/edge_bit_counter_DP_OP_10J1_125_9618_J1_0.b -------------------------------------------------------------------------------- /fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/uart_rx_fsm_DATA_WIDTH8_DP_OP_29J1_122_2437_J1_0.b: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/uart_rx_fsm_DATA_WIDTH8_DP_OP_29J1_122_2437_J1_0.b -------------------------------------------------------------------------------- /fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/uart_rx_fsm_DATA_WIDTH8_DP_OP_30J1_123_2437_J1_0.b: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/fm/post_synthesis/formality_svf/d1/netlists/S1/J1/dw-1/uart_rx_fsm_DATA_WIDTH8_DP_OP_30J1_123_2437_J1_0.b -------------------------------------------------------------------------------- /pnr/output/UART.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/pnr/output/UART.gds -------------------------------------------------------------------------------- /pnr/reports/CTS/check_legality.rpt: -------------------------------------------------------------------------------- 1 | 2 | ************************ 3 | 4 | running check_legality 5 | 6 | Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 7 | Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 8 | PDC app_options settings ========= 9 | place.legalize.enable_prerouted_net_check: 1 10 | place.legalize.num_tracks_for_access_check: 1 11 | place.legalize.use_eol_spacing_for_access_check: 0 12 | place.legalize.allow_touch_track_for_access_check: 1 13 | place.legalize.reduce_conservatism_in_eol_check: 0 14 | place.legalize.preroute_shape_merge_distance: 0.0 15 | place.legalize.enable_non_preferred_direction_span_check: 0 16 | 17 | Layer M1: cached 0 shapes out of 40 total shapes. 18 | Layer M2: cached 0 shapes out of 85 total shapes. 19 | Cached 252 vias out of 1162 total vias. 20 | 21 | check_legality for block design UART ... 22 | Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 23 | Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 24 | Design has no advanced rules 25 | Checking legality 26 | Checking cell legality: 27 | 0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% 28 | Sorting rows. 29 | Checking spacing rule legality. 30 | 0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% 31 | Checking packing rule legality. 32 | 33 | 34 | **************************************** 35 | Report : Legality 36 | **************************************** 37 | 38 | VIOLATIONS BY CATEGORY: 39 | MOVABLE APP-FIXED USER-FIXED DESCRIPTION 40 | 0 0 0 Two objects overlap. 41 | 0 0 0 A cell violates a pnet. 42 | 0 0 0 A cell is illegal at a site. 43 | 0 0 0 A cell is not aligned with a site. 44 | 0 0 0 A cell has an illegal orientation. 45 | 0 0 0 A cell spacing rule is violated. 46 | 0 0 0 A layer rule is violated. 47 | 0 0 0 A cell is in the wrong region. 48 | 0 0 0 Two cells violate cts margins. 49 | 0 0 0 Two cells violate coloring. 50 | 51 | 0 0 0 TOTAL 52 | 53 | TOTAL 0 Violations. 54 | 55 | VIOLATIONS BY SUBCATEGORY: 56 | MOVABLE APP-FIXED USER-FIXED DESCRIPTION 57 | 58 | 0 0 0 Two objects overlap. 59 | 0 0 0 Two cells overlap. 60 | 0 0 0 Two cells have overlapping keepout margins. 61 | 0 0 0 A cell overlaps a blockage. 62 | 0 0 0 A cell keepout margin overlaps a blockage. 63 | 64 | 0 0 0 A cell violates a pnet. 65 | 66 | 0 0 0 A cell is illegal at a site. 67 | 0 0 0 A cell violates pin-track alignment rules. 68 | 0 0 0 A cell is illegal at a site. 69 | 0 0 0 A cell violates legal index rule. 70 | 0 0 0 A cell has the wrong variant for its location. 71 | 72 | 0 0 0 A cell is not aligned with a site. 73 | 0 0 0 A cell is not aligned with the base site. 74 | 0 0 0 A cell is not aligned with an overlaid site. 75 | 76 | 0 0 0 A cell has an illegal orientation. 77 | 78 | 0 0 0 A cell spacing rule is violated. 79 | 0 0 0 A spacing rule is violated in a row. 80 | 0 0 0 A spacing rule is violated between adjacent rows. 81 | 0 0 0 A cell violates vertical abutment rule. 82 | 0 0 0 A cell violates metal spacing rule. 83 | 84 | 0 0 0 A layer rule is violated. 85 | 0 0 0 A layer VTH rule is violated. 86 | 0 0 0 A layer OD rule is violated. 87 | 0 0 0 A layer OD max-width rule is violated. 88 | 0 0 0 A layer ALL_OD corner rule is violated. 89 | 0 0 0 A layer max-vertical-length rule is violated. 90 | 0 0 0 A layer TPO rule is violated. 91 | 0 0 0 Filler cell insertion cannot satisfy layer rules. 92 | 93 | 0 0 0 A cell is in the wrong region. 94 | 0 0 0 A cell is outside its hard bound. 95 | 0 0 0 A cell is in the wrong voltage area. 96 | 0 0 0 A cell violates an exclusive movebound. 97 | 98 | 0 0 0 Two cells violate cts margins. 99 | 100 | 0 0 0 Two cells violate coloring. 101 | 102 | 103 | check_legality for block design UART succeeded! 104 | 105 | 106 | check_legality succeeded. 107 | 108 | ************************** 109 | 110 | 1 111 | -------------------------------------------------------------------------------- /pnr/reports/CTS/latency.rpt: -------------------------------------------------------------------------------- 1 | Warning: Use -per_clock_root option along with -type latency option to split the reporting of a clock to per clock root, so that the clock trees associated with different root pins are reported separately 2 | Info: Initializing timer in CLOCK_SYN_MODE 3 | **************************************** 4 | Report : clock qor 5 | -type latency 6 | -clocks SCAN_CLK 7 | UART_CLK_RX 8 | UART_CLK_TX 9 | Design : UART 10 | Version: O-2018.06-SP1 11 | Date : Sun Apr 28 19:25:11 2024 12 | **************************************** 13 | 14 | Attributes 15 | =========== 16 | M Master Clock 17 | G Generated Clock 18 | & Internal Generated Clock 19 | U User Defined Skew Group 20 | D Default Skew Group 21 | * Generated Clock Balanced Separately 22 | 23 | ============================================== 24 | ==== Latency Reporting for Corner default ==== 25 | ============================================== 26 | 27 | =================================================== Summary Table for Corner default =================================================== 28 | Clock / Attrs Sinks Target Global Target Max Min Median Latency Boundary 29 | Skew Group Skew Skew Latency Latency Latency Latency Std Dev Skew 30 | ---------------------------------------------------------------------------------------------------------------------------------------- 31 | ### Mode: default, Scenario: default 32 | SCAN_CLK M,D 53 10.00 0.02 -- 0.33 0.31 0.33 0.01 -- 33 | ---------------------------------------------------------------------------------------------------------------------------------------- 34 | All Clocks 53 0.05 0.02 -- 0.33 0.31 -- -- -- 35 | 36 | 37 | & = Offset derived from max_clock_tree_path / min_clock_tree_path 38 | r = latency reported is for a rising edge triggered event at the sink 39 | f = latency reported is for a falling edge triggered event at the sink 40 | 41 | 42 | Showing 5 largest and 5 smallest datapoints per clock / skew group (L=largest, S=smallest) 43 | ========================================== Details Table for Corner default ========================================== 44 | Clock / Sink Launch Capture Late Early 45 | Skew Group Name Latency Latency Offset Offset 46 | ---------------------------------------------------------------------------------------------------------------------- 47 | ### Mode: default, Scenario: default 48 | SCAN_CLK 49 | L U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK 50 | 0.33 r 0.33 r -- -- 51 | L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK 52 | 0.33 r 0.33 r -- -- 53 | L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK 54 | 0.33 r 0.33 r -- -- 55 | L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK 56 | 0.33 r 0.33 r -- -- 57 | L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK 58 | 0.33 r 0.33 r -- -- 59 | S U0_UART_TX/U0_fsm/current_state_reg_1_/CLK 60 | 0.31 r 0.31 r -- -- 61 | S U0_UART_TX/U0_fsm/current_state_reg_0_/CLK 62 | 0.31 r 0.31 r -- -- 63 | S U0_UART_TX/U0_parity_calc/parity_reg/CLK 64 | 0.31 r 0.31 r -- -- 65 | S U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK 66 | 0.31 r 0.31 r -- -- 67 | S U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK 68 | 0.31 r 0.31 r -- -- 69 | 70 | 71 | 1 72 | -------------------------------------------------------------------------------- /pnr/reports/CTS/report_clock_qor.rpt: -------------------------------------------------------------------------------- 1 | Info: Initializing timer in CLOCK_SYN_MODE 2 | Information: The stitching and editing of coupling caps is turned OFF for design 'UART.dlib:UART.design'. (TIM-125) 3 | Information: The RC mode used is CTO(RDE) for design 'UART'. (NEX-022) 4 | Information: Update timing completed net estimation for all the timing graph nets (TIM-111) 5 | Information: Net estimation statistics: timing graph nets = 441, routed nets = 5, across physical hierarchy nets = 0, parasitics cached nets = 5, delay annotated nets = 0, parasitics annotated nets = 0, multi-voltage nets = 0. (TIM-112) 6 | Warning: The scenario default has max transition DRC fixing disabled using the set_scenario_status command. High DRC count may be expected. 7 | Warning: The scenario default has max capacitance DRC fixing disabled using the set_scenario_status command. High DRC count may be expected. 8 | **************************************** 9 | Report : clock qor 10 | -type summary 11 | Design : UART 12 | Version: O-2018.06-SP1 13 | Date : Sun Apr 28 19:25:11 2024 14 | **************************************** 15 | 16 | Attributes 17 | =========== 18 | M Master Clock 19 | G Generated Clock 20 | & Internal Generated Clock 21 | U User Defined Skew Group 22 | D Default Skew Group 23 | * Generated Clock Balanced Separately 24 | 25 | ============================================== 26 | ==== Summary Reporting for Corner default ==== 27 | ============================================== 28 | 29 | ================================================= Summary Table for Corner default ================================================= 30 | Clock / Attrs Sinks Levels Clock Clock Clock Max Global Trans DRC Cap DRC 31 | Skew Group Repeater Repeater Stdcell Latency Skew Count Count 32 | Count Area Area 33 | ------------------------------------------------------------------------------------------------------------------------------------ 34 | ### Mode: default, Scenario: default 35 | SCAN_CLK M,D 53 2 0 0.00 7.12 0.33 0.02 0 0 36 | UART_CLK_TX M,D 0 0 0 0.00 0.00 -- -- 0 0 37 | UART_CLK_RX M,D 0 0 0 0.00 0.00 -- -- 0 0 38 | ------------------------------------------------------------------------------------------------------------------------------------ 39 | All Clocks 53 2 0 0.00 7.12 0.33 0.02 0 0 40 | 41 | 42 | 1 43 | -------------------------------------------------------------------------------- /pnr/reports/CTS/report_constraints_max_capacitance.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : constraint 3 | -verbose 4 | -all_violators 5 | -max_capacitance 6 | Design : UART 7 | Version: O-2018.06-SP1 8 | Date : Sat Apr 27 15:21:16 2024 9 | **************************************** 10 | 11 | 12 | 13 | 14 | Total number of violation(s): 0 15 | 1 16 | **************************************** 17 | Report : constraint 18 | -verbose 19 | -all_violators 20 | -max_capacitance 21 | Design : UART 22 | Version: O-2018.06-SP1 23 | Date : Sat Apr 27 16:41:56 2024 24 | **************************************** 25 | 26 | 27 | 28 | 29 | Total number of violation(s): 0 30 | 1 31 | **************************************** 32 | Report : constraint 33 | -verbose 34 | -all_violators 35 | -max_capacitance 36 | Design : UART 37 | Version: O-2018.06-SP1 38 | Date : Sun Apr 28 19:11:53 2024 39 | **************************************** 40 | 41 | 42 | 43 | 44 | Total number of violation(s): 0 45 | 1 46 | **************************************** 47 | Report : constraint 48 | -verbose 49 | -all_violators 50 | -max_capacitance 51 | Design : UART 52 | Version: O-2018.06-SP1 53 | Date : Sun Apr 28 19:25:11 2024 54 | **************************************** 55 | 56 | 57 | 58 | 59 | Total number of violation(s): 0 60 | 1 61 | -------------------------------------------------------------------------------- /pnr/reports/CTS/report_constraints_max_transition.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : constraint 3 | -verbose 4 | -all_violators 5 | -max_transition 6 | Design : UART 7 | Version: O-2018.06-SP1 8 | Date : Sun Apr 28 19:25:11 2024 9 | **************************************** 10 | 11 | 12 | 13 | Information: The stitching and editing of coupling caps is turned OFF for design 'UART.dlib:UART.design'. (TIM-125) 14 | Information: Update timing completed net estimation for all the timing graph nets (TIM-111) 15 | Information: Net estimation statistics: timing graph nets = 441, routed nets = 5, across physical hierarchy nets = 0, parasitics cached nets = 9, delay annotated nets = 0, parasitics annotated nets = 0, multi-voltage nets = 0. (TIM-112) 16 | 17 | Total number of violation(s): 0 18 | 1 19 | -------------------------------------------------------------------------------- /pnr/reports/CTS/report_qor.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : qor 3 | -summary 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Sun Apr 28 19:25:11 2024 7 | **************************************** 8 | Information: Timer using 'CRPR'. (TIM-050) 9 | 10 | Timing 11 | --------------------------------------------------------------------------- 12 | Context WNS TNS NVE 13 | --------------------------------------------------------------------------- 14 | Design (Setup) 97.23 0.00 0 15 | 16 | Design (Hold) 0.30 0.00 0 17 | --------------------------------------------------------------------------- 18 | 19 | Miscellaneous 20 | --------------------------------------------------------------------------- 21 | Cell Area (netlist): 1283.68 22 | Cell Area (netlist and physical only): 1283.68 23 | Nets with DRC Violations: 0 24 | 1 25 | -------------------------------------------------------------------------------- /pnr/reports/Placement/check_legality.rpt: -------------------------------------------------------------------------------- 1 | 2 | ************************ 3 | 4 | running check_legality 5 | 6 | Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 7 | Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 8 | PDC app_options settings ========= 9 | place.legalize.enable_prerouted_net_check: 1 10 | place.legalize.num_tracks_for_access_check: 1 11 | place.legalize.use_eol_spacing_for_access_check: 0 12 | place.legalize.allow_touch_track_for_access_check: 1 13 | place.legalize.reduce_conservatism_in_eol_check: 0 14 | place.legalize.preroute_shape_merge_distance: 0.0 15 | place.legalize.enable_non_preferred_direction_span_check: 0 16 | 17 | Layer M1: cached 0 shapes out of 28 total shapes. 18 | Layer M2: cached 0 shapes out of 0 total shapes. 19 | Cached 252 vias out of 960 total vias. 20 | 21 | check_legality for block design UART ... 22 | Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 23 | Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 24 | Design has no advanced rules 25 | Checking legality 26 | Checking cell legality: 27 | 0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% 28 | Sorting rows. 29 | Checking spacing rule legality. 30 | 0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% 31 | Checking packing rule legality. 32 | 33 | 34 | **************************************** 35 | Report : Legality 36 | **************************************** 37 | 38 | VIOLATIONS BY CATEGORY: 39 | MOVABLE APP-FIXED USER-FIXED DESCRIPTION 40 | 0 0 0 Two objects overlap. 41 | 0 0 0 A cell violates a pnet. 42 | 0 0 0 A cell is illegal at a site. 43 | 0 0 0 A cell is not aligned with a site. 44 | 0 0 0 A cell has an illegal orientation. 45 | 0 0 0 A cell spacing rule is violated. 46 | 0 0 0 A layer rule is violated. 47 | 0 0 0 A cell is in the wrong region. 48 | 0 0 0 Two cells violate cts margins. 49 | 0 0 0 Two cells violate coloring. 50 | 51 | 0 0 0 TOTAL 52 | 53 | TOTAL 0 Violations. 54 | 55 | VIOLATIONS BY SUBCATEGORY: 56 | MOVABLE APP-FIXED USER-FIXED DESCRIPTION 57 | 58 | 0 0 0 Two objects overlap. 59 | 0 0 0 Two cells overlap. 60 | 0 0 0 Two cells have overlapping keepout margins. 61 | 0 0 0 A cell overlaps a blockage. 62 | 0 0 0 A cell keepout margin overlaps a blockage. 63 | 64 | 0 0 0 A cell violates a pnet. 65 | 66 | 0 0 0 A cell is illegal at a site. 67 | 0 0 0 A cell violates pin-track alignment rules. 68 | 0 0 0 A cell is illegal at a site. 69 | 0 0 0 A cell violates legal index rule. 70 | 0 0 0 A cell has the wrong variant for its location. 71 | 72 | 0 0 0 A cell is not aligned with a site. 73 | 0 0 0 A cell is not aligned with the base site. 74 | 0 0 0 A cell is not aligned with an overlaid site. 75 | 76 | 0 0 0 A cell has an illegal orientation. 77 | 78 | 0 0 0 A cell spacing rule is violated. 79 | 0 0 0 A spacing rule is violated in a row. 80 | 0 0 0 A spacing rule is violated between adjacent rows. 81 | 0 0 0 A cell violates vertical abutment rule. 82 | 0 0 0 A cell violates metal spacing rule. 83 | 84 | 0 0 0 A layer rule is violated. 85 | 0 0 0 A layer VTH rule is violated. 86 | 0 0 0 A layer OD rule is violated. 87 | 0 0 0 A layer OD max-width rule is violated. 88 | 0 0 0 A layer ALL_OD corner rule is violated. 89 | 0 0 0 A layer max-vertical-length rule is violated. 90 | 0 0 0 A layer TPO rule is violated. 91 | 0 0 0 Filler cell insertion cannot satisfy layer rules. 92 | 93 | 0 0 0 A cell is in the wrong region. 94 | 0 0 0 A cell is outside its hard bound. 95 | 0 0 0 A cell is in the wrong voltage area. 96 | 0 0 0 A cell violates an exclusive movebound. 97 | 98 | 0 0 0 Two cells violate cts margins. 99 | 100 | 0 0 0 Two cells violate coloring. 101 | 102 | 103 | check_legality for block design UART succeeded! 104 | 105 | 106 | check_legality succeeded. 107 | 108 | ************************** 109 | 110 | 1 111 | -------------------------------------------------------------------------------- /pnr/reports/Placement/report_congestion.rpt: -------------------------------------------------------------------------------- 1 | Warning: Layer MRDL does not have a preferred direction, skipped. 2 | **************************************** 3 | Report : congestion 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Sun Apr 28 19:24:39 2024 7 | **************************************** 8 | 9 | Layer | overflow | # GRCs has 10 | Name | total | max | overflow (%) | max overflow 11 | --------------------------------------------------------------- 12 | Both Dirs | 5 | 1 | 5 ( 0.92%) | 5 13 | H routing | 5 | 1 | 5 ( 1.84%) | 5 14 | V routing | 0 | 0 | 0 ( 0.00%) | 0 15 | 16 | 1 17 | -------------------------------------------------------------------------------- /pnr/reports/Placement/report_qor.summary.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : qor 3 | -summary 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Sun Apr 28 19:24:38 2024 7 | **************************************** 8 | 9 | Timing 10 | --------------------------------------------------------------------------- 11 | Context WNS TNS NVE 12 | --------------------------------------------------------------------------- 13 | Design (Setup) 97.23 0.00 0 14 | 15 | Design (Hold) 0.20 0.00 0 16 | --------------------------------------------------------------------------- 17 | 18 | Miscellaneous 19 | --------------------------------------------------------------------------- 20 | Cell Area (netlist): 1279.62 21 | Cell Area (netlist and physical only): 1279.62 22 | Nets with DRC Violations: 0 23 | 1 24 | -------------------------------------------------------------------------------- /pnr/reports/Placement/report_utilization.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : report_utilization 3 | Design : UART 4 | Version: O-2018.06-SP1 5 | Date : Sun Apr 28 19:24:39 2024 6 | **************************************** 7 | Utilization Ratio: 0.6155 8 | Utilization options: 9 | - Area calculation based on: site_row of block UART 10 | - Categories of objects excluded: hard_macros macro_keepouts soft_macros io_cells hard_blockages 11 | Total Area: 2079.1521 12 | Total Capacity Area: 2079.1521 13 | Total Area of cells: 1279.6150 14 | Area of excluded objects: 15 | - hard_macros : 0.0000 16 | - macro_keepouts : 0.0000 17 | - soft_macros : 0.0000 18 | - io_cells : 0.0000 19 | - hard_blockages : 0.0000 20 | 21 | Utilization of site-rows with: 22 | - Site 'unit': 0.6155 23 | 24 | 0.6155 25 | -------------------------------------------------------------------------------- /pnr/reports/Powerplanning/check_pg_connectivity.rpt: -------------------------------------------------------------------------------- 1 | Loading cell instances... 2 | Number of Standard Cells: 0 3 | Number of Macro Cells: 0 4 | Number of IO Pad Cells: 0 5 | Number of Blocks: 0 6 | Loading P/G wires and vias... 7 | Number of VDD Wires: 26 8 | Number of VDD Vias: 428 9 | Number of VDD Terminals: 8 10 | Number of VSS Wires: 27 11 | Number of VSS Vias: 532 12 | Number of VSS Terminals: 8 13 | **************Verify net VDD connectivity***************** 14 | Number of floating wires: 0 15 | Number of floating vias: 0 16 | Number of floating std cells: 0 17 | Number of floating hard macros: 0 18 | Number of floating I/O pads: 0 19 | Number of floating terminals: 0 20 | Number of floating hierarchical blocks: 0 21 | ************************************************************ 22 | **************Verify net VSS connectivity***************** 23 | Number of floating wires: 0 24 | Number of floating vias: 0 25 | Number of floating std cells: 0 26 | Number of floating hard macros: 0 27 | Number of floating I/O pads: 0 28 | Number of floating terminals: 0 29 | Number of floating hierarchical blocks: 0 30 | ************************************************************ 31 | Overall runtime: 0 seconds. 32 | -------------------------------------------------------------------------------- /pnr/reports/Powerplanning/check_pg_drc.rpt: -------------------------------------------------------------------------------- 1 | Command check_pg_drc started at Sun Apr 28 19:24:22 2024 2 | Command check_pg_drc finished at Sun Apr 28 19:24:22 2024 3 | CPU usage for check_pg_drc: 0.01 seconds ( 0.00 hours) 4 | Elapsed time for check_pg_drc: 0.01 seconds ( 0.00 hours) 5 | No errors found. 6 | -------------------------------------------------------------------------------- /pnr/reports/Powerplanning/check_pg_missing_vias.rpt: -------------------------------------------------------------------------------- 1 | Check net VDD vias... 2 | Number of missing vias: 0 3 | Checking net VDD vias took 0 seconds. 4 | Check net VSS vias... 5 | Number of missing vias: 0 6 | Checking net VSS vias took 0 seconds. 7 | Overall runtime: 0 seconds. 8 | -------------------------------------------------------------------------------- /pnr/reports/Powerplanning/report_qor.summary.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : qor 3 | -summary 4 | -include { setup } 5 | Design : UART 6 | Version: O-2018.06-SP1 7 | Date : Sun Apr 28 19:24:21 2024 8 | **************************************** 9 | Information: The stitching and editing of coupling caps is turned OFF for design 'UART.dlib:UART.design'. (TIM-125) 10 | Warning: Technology layer 'MRDL' setting 'routing-direction' is not valid (NEX-001) 11 | Information: Design Average RC for design UART (NEX-011) 12 | Information: r = 1.788571 ohm/um, via_r = 0.489881 ohm/cut, c = 0.070408 ff/um, cc = 0.000000 ff/um (X dir) (NEX-017) 13 | Information: r = 1.785715 ohm/um, via_r = 0.603342 ohm/cut, c = 0.079106 ff/um, cc = 0.000000 ff/um (Y dir) (NEX-017) 14 | Information: The RC mode used is VR for design 'UART'. (NEX-022) 15 | Information: Update timing completed net estimation for all the timing graph nets (TIM-111) 16 | Information: Net estimation statistics: timing graph nets = 435, routed nets = 0, across physical hierarchy nets = 0, parasitics cached nets = 5, delay annotated nets = 0, parasitics annotated nets = 0, multi-voltage nets = 0. (TIM-112) 17 | 18 | Timing 19 | --------------------------------------------------------------------------- 20 | Context WNS TNS NVE 21 | --------------------------------------------------------------------------- 22 | Design (Setup) 97.24 0.00 0 23 | 24 | --------------------------------------------------------------------------- 25 | 26 | 1 27 | -------------------------------------------------------------------------------- /pnr/reports/Routing/check_legality.rpt: -------------------------------------------------------------------------------- 1 | 2 | ************************ 3 | 4 | running check_legality 5 | 6 | Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 7 | Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 8 | PDC app_options settings ========= 9 | place.legalize.enable_prerouted_net_check: 1 10 | place.legalize.num_tracks_for_access_check: 1 11 | place.legalize.use_eol_spacing_for_access_check: 0 12 | place.legalize.allow_touch_track_for_access_check: 1 13 | place.legalize.reduce_conservatism_in_eol_check: 0 14 | place.legalize.preroute_shape_merge_distance: 0.0 15 | place.legalize.enable_non_preferred_direction_span_check: 0 16 | 17 | Layer M1: cached 0 shapes out of 413 total shapes. 18 | Layer M2: cached 0 shapes out of 1805 total shapes. 19 | Cached 252 vias out of 3742 total vias. 20 | 21 | check_legality for block design UART ... 22 | Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 23 | Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) 24 | Design has no advanced rules 25 | Checking legality 26 | Checking cell legality: 27 | 0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% 28 | Sorting rows. 29 | Checking spacing rule legality. 30 | 0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% 31 | Checking packing rule legality. 32 | 33 | 34 | **************************************** 35 | Report : Legality 36 | **************************************** 37 | 38 | VIOLATIONS BY CATEGORY: 39 | MOVABLE APP-FIXED USER-FIXED DESCRIPTION 40 | 0 0 0 Two objects overlap. 41 | 0 0 0 A cell violates a pnet. 42 | 0 0 0 A cell is illegal at a site. 43 | 0 0 0 A cell is not aligned with a site. 44 | 0 0 0 A cell has an illegal orientation. 45 | 0 0 0 A cell spacing rule is violated. 46 | 0 0 0 A layer rule is violated. 47 | 0 0 0 A cell is in the wrong region. 48 | 0 0 0 Two cells violate cts margins. 49 | 0 0 0 Two cells violate coloring. 50 | 51 | 0 0 0 TOTAL 52 | 53 | TOTAL 0 Violations. 54 | 55 | VIOLATIONS BY SUBCATEGORY: 56 | MOVABLE APP-FIXED USER-FIXED DESCRIPTION 57 | 58 | 0 0 0 Two objects overlap. 59 | 0 0 0 Two cells overlap. 60 | 0 0 0 Two cells have overlapping keepout margins. 61 | 0 0 0 A cell overlaps a blockage. 62 | 0 0 0 A cell keepout margin overlaps a blockage. 63 | 64 | 0 0 0 A cell violates a pnet. 65 | 66 | 0 0 0 A cell is illegal at a site. 67 | 0 0 0 A cell violates pin-track alignment rules. 68 | 0 0 0 A cell is illegal at a site. 69 | 0 0 0 A cell violates legal index rule. 70 | 0 0 0 A cell has the wrong variant for its location. 71 | 72 | 0 0 0 A cell is not aligned with a site. 73 | 0 0 0 A cell is not aligned with the base site. 74 | 0 0 0 A cell is not aligned with an overlaid site. 75 | 76 | 0 0 0 A cell has an illegal orientation. 77 | 78 | 0 0 0 A cell spacing rule is violated. 79 | 0 0 0 A spacing rule is violated in a row. 80 | 0 0 0 A spacing rule is violated between adjacent rows. 81 | 0 0 0 A cell violates vertical abutment rule. 82 | 0 0 0 A cell violates metal spacing rule. 83 | 84 | 0 0 0 A layer rule is violated. 85 | 0 0 0 A layer VTH rule is violated. 86 | 0 0 0 A layer OD rule is violated. 87 | 0 0 0 A layer OD max-width rule is violated. 88 | 0 0 0 A layer ALL_OD corner rule is violated. 89 | 0 0 0 A layer max-vertical-length rule is violated. 90 | 0 0 0 A layer TPO rule is violated. 91 | 0 0 0 Filler cell insertion cannot satisfy layer rules. 92 | 93 | 0 0 0 A cell is in the wrong region. 94 | 0 0 0 A cell is outside its hard bound. 95 | 0 0 0 A cell is in the wrong voltage area. 96 | 0 0 0 A cell violates an exclusive movebound. 97 | 98 | 0 0 0 Two cells violate cts margins. 99 | 100 | 0 0 0 Two cells violate coloring. 101 | 102 | 103 | check_legality for block design UART succeeded! 104 | 105 | 106 | check_legality succeeded. 107 | 108 | ************************** 109 | 110 | 1 111 | -------------------------------------------------------------------------------- /pnr/reports/Routing/check_lvs.rpt: -------------------------------------------------------------------------------- 1 | Information: Using 1 threads for LVS 2 | [Check Short] Stage 1 Elapsed = 0:00:00, CPU = 0:00:00 3 | [Check Short] Stage 1-2 Elapsed = 0:00:00, CPU = 0:00:00 4 | [Check Short] Stage 2 Elapsed = 0:00:00, CPU = 0:00:00 5 | [Check Short] Stage 2-2 Elapsed = 0:00:00, CPU = 0:00:00 6 | [Check Short] Stage 3 Elapsed = 0:00:00, CPU = 0:00:00 7 | [Check Short] End Elapsed = 0:00:00, CPU = 0:00:00 8 | [Check Net] Init Elapsed = 0:00:00, CPU = 0:00:00 9 | [Check Net] 10% Elapsed = 0:00:00, CPU = 0:00:00 10 | [Check Net] 20% Elapsed = 0:00:00, CPU = 0:00:00 11 | [Check Net] 30% Elapsed = 0:00:00, CPU = 0:00:00 12 | [Check Net] 40% Elapsed = 0:00:00, CPU = 0:00:00 13 | [Check Net] 50% Elapsed = 0:00:00, CPU = 0:00:00 14 | [Check Net] 60% Elapsed = 0:00:00, CPU = 0:00:00 15 | [Check Net] 70% Elapsed = 0:00:00, CPU = 0:00:00 16 | [Check Net] 80% Elapsed = 0:00:00, CPU = 0:00:00 17 | [Check Net] 90% Elapsed = 0:00:00, CPU = 0:00:00 18 | [Check Net] All nets are submitted. 19 | [Check Net] 100% Elapsed = 0:00:00, CPU = 0:00:00 20 | 21 | =============================================================== 22 | Maximum number of violations is set to 20 23 | Abort checking when more than 20 violations are found 24 | All violations might not be found. 25 | =============================================================== 26 | Total number of input nets is 443. 27 | Total number of short violations is 0. 28 | Total number of open nets is 0. 29 | Total number of floating route violations is 0. 30 | 31 | Elapsed = 0:00:00, CPU = 0:00:00 32 | 1 33 | -------------------------------------------------------------------------------- /pnr/reports/Routing/report_constraints_max_capacitance.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : constraint 3 | -verbose 4 | -all_violators 5 | -max_capacitance 6 | Design : UART 7 | Version: O-2018.06-SP1 8 | Date : Sat Apr 27 15:21:24 2024 9 | **************************************** 10 | 11 | 12 | 13 | 14 | Total number of violation(s): 0 15 | 1 16 | **************************************** 17 | Report : constraint 18 | -verbose 19 | -all_violators 20 | -max_capacitance 21 | Design : UART 22 | Version: O-2018.06-SP1 23 | Date : Sat Apr 27 16:42:21 2024 24 | **************************************** 25 | 26 | 27 | 28 | 29 | Total number of violation(s): 0 30 | 1 31 | **************************************** 32 | Report : constraint 33 | -verbose 34 | -all_violators 35 | -max_capacitance 36 | Design : UART 37 | Version: O-2018.06-SP1 38 | Date : Sun Apr 28 19:14:25 2024 39 | **************************************** 40 | 41 | 42 | 43 | 44 | Total number of violation(s): 0 45 | 1 46 | **************************************** 47 | Report : constraint 48 | -verbose 49 | -all_violators 50 | -max_capacitance 51 | Design : UART 52 | Version: O-2018.06-SP1 53 | Date : Sun Apr 28 19:25:17 2024 54 | **************************************** 55 | 56 | 57 | 58 | 59 | Total number of violation(s): 0 60 | 1 61 | -------------------------------------------------------------------------------- /pnr/reports/Routing/report_constraints_max_transition.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : constraint 3 | -verbose 4 | -all_violators 5 | -max_transition 6 | Design : UART 7 | Version: O-2018.06-SP1 8 | Date : Sun Apr 28 19:25:17 2024 9 | **************************************** 10 | 11 | 12 | 13 | 14 | Total number of violation(s): 0 15 | 1 16 | -------------------------------------------------------------------------------- /pnr/reports/Routing/report_qor.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : qor 3 | -summary 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Sun Apr 28 19:25:17 2024 7 | **************************************** 8 | Information: Timer using 'SI, Timing Window Analysis, CRPR'. (TIM-050) 9 | 10 | Timing 11 | --------------------------------------------------------------------------- 12 | Context WNS TNS NVE 13 | --------------------------------------------------------------------------- 14 | Design (Setup) 97.22 0.00 0 15 | 16 | Design (Hold) 0.29 0.00 0 17 | --------------------------------------------------------------------------- 18 | 19 | Miscellaneous 20 | --------------------------------------------------------------------------- 21 | Cell Area (netlist): 1283.68 22 | Cell Area (netlist and physical only): 1283.68 23 | Nets with DRC Violations: 0 24 | 1 25 | -------------------------------------------------------------------------------- /pnr/reports/Routing/report_timing.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : timing 3 | -path_type full 4 | -delay_type max 5 | -max_paths 5 6 | -report_by design 7 | Design : UART 8 | Version: O-2018.06-SP1 9 | Date : Sun Apr 28 19:25:17 2024 10 | **************************************** 11 | Information: Timer using 'SI, Timing Window Analysis, CRPR'. (TIM-050) 12 | 13 | Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 14 | Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 15 | Mode: default 16 | Corner: default 17 | Scenario: default 18 | Path Group: SCAN_CLK 19 | Path Type: max 20 | 21 | Point Incr Path 22 | ------------------------------------------------------------------------ 23 | clock SCAN_CLK (rise edge) 0.00 0.00 24 | clock network delay (propagated) 0.32 0.32 25 | 26 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 27 | 0.00 0.32 r 28 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 29 | 0.55 0.86 r 30 | U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.12 0.98 f 31 | U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.24 1.22 r 32 | U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.14 1.36 r 33 | U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 34 | 0.22 1.58 f 35 | U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.33 1.91 f 36 | U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.26 2.17 f 37 | U0_UART_RX/U0_data_sampling/U28/Y (NOR4X0_RVT) 0.29 2.46 r 38 | U0_UART_RX/U0_data_sampling/U27/Y (MUX21X1_RVT) 39 | 0.20 2.66 f 40 | U0_UART_RX/U0_data_sampling/Samples_reg_2_/D (SDFFARX1_RVT) 41 | 0.00 2.66 f 42 | data arrival time 2.66 43 | 44 | clock SCAN_CLK (rise edge) 100.00 100.00 45 | clock network delay (propagated) 0.29 100.29 46 | clock reconvergence pessimism 0.03 100.32 47 | U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 48 | 0.00 100.32 r 49 | clock uncertainty -0.20 100.12 50 | library setup time -0.24 99.88 51 | data required time 99.88 52 | ------------------------------------------------------------------------ 53 | data required time 99.88 54 | data arrival time -2.66 55 | ------------------------------------------------------------------------ 56 | slack (MET) 97.22 57 | 58 | 59 | 60 | Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 61 | Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 62 | Mode: default 63 | Corner: default 64 | Scenario: default 65 | Path Group: SCAN_CLK 66 | Path Type: max 67 | 68 | Point Incr Path 69 | ------------------------------------------------------------------------ 70 | clock SCAN_CLK (rise edge) 0.00 0.00 71 | clock network delay (propagated) 0.32 0.32 72 | 73 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 74 | 0.00 0.32 r 75 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 76 | 0.55 0.86 r 77 | U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.12 0.98 f 78 | U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.24 1.22 r 79 | U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.14 1.36 r 80 | U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 81 | 0.22 1.58 f 82 | U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.33 1.91 f 83 | U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.26 2.17 f 84 | U0_UART_RX/U0_data_sampling/U37/Y (MUX21X1_RVT) 85 | 0.24 2.41 f 86 | U0_UART_RX/U0_data_sampling/Samples_reg_1_/D (SDFFARX1_RVT) 87 | 0.00 2.41 f 88 | data arrival time 2.41 89 | 90 | clock SCAN_CLK (rise edge) 100.00 100.00 91 | clock network delay (propagated) 0.29 100.29 92 | clock reconvergence pessimism 0.03 100.32 93 | U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 94 | 0.00 100.32 r 95 | clock uncertainty -0.20 100.12 96 | library setup time -0.24 99.88 97 | data required time 99.88 98 | ------------------------------------------------------------------------ 99 | data required time 99.88 100 | data arrival time -2.41 101 | ------------------------------------------------------------------------ 102 | slack (MET) 97.47 103 | 104 | 105 | 106 | Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 107 | Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 108 | Mode: default 109 | Corner: default 110 | Scenario: default 111 | Path Group: SCAN_CLK 112 | Path Type: max 113 | 114 | Point Incr Path 115 | ------------------------------------------------------------------------ 116 | clock SCAN_CLK (rise edge) 0.00 0.00 117 | clock network delay (propagated) 0.32 0.32 118 | 119 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 120 | 0.00 0.32 r 121 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 122 | 0.55 0.87 r 123 | U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.30 1.16 r 124 | U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.12 1.28 f 125 | U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.34 1.62 r 126 | U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.25 1.86 f 127 | U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.26 2.13 r 128 | U0_UART_RX/U0_deserializer/U16/Y (AO22X1_RVT) 0.19 2.32 r 129 | U0_UART_RX/U0_deserializer/P_DATA_reg_7_/D (SDFFARX1_RVT) 130 | 0.00 2.32 r 131 | data arrival time 2.32 132 | 133 | clock SCAN_CLK (rise edge) 100.00 100.00 134 | clock network delay (propagated) 0.29 100.29 135 | clock reconvergence pessimism 0.03 100.32 136 | U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 137 | 0.00 100.32 r 138 | clock uncertainty -0.20 100.12 139 | library setup time -0.24 99.88 140 | data required time 99.88 141 | ------------------------------------------------------------------------ 142 | data required time 99.88 143 | data arrival time -2.32 144 | ------------------------------------------------------------------------ 145 | slack (MET) 97.56 146 | 147 | 148 | 149 | Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 150 | Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 151 | Mode: default 152 | Corner: default 153 | Scenario: default 154 | Path Group: SCAN_CLK 155 | Path Type: max 156 | 157 | Point Incr Path 158 | ------------------------------------------------------------------------ 159 | clock SCAN_CLK (rise edge) 0.00 0.00 160 | clock network delay (propagated) 0.32 0.32 161 | 162 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 163 | 0.00 0.32 r 164 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 165 | 0.55 0.87 r 166 | U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.30 1.16 r 167 | U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.12 1.28 f 168 | U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.34 1.62 r 169 | U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.25 1.86 f 170 | U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.26 2.13 r 171 | U0_UART_RX/U0_deserializer/U12/Y (AO22X1_RVT) 0.18 2.31 r 172 | U0_UART_RX/U0_deserializer/P_DATA_reg_5_/D (SDFFARX1_RVT) 173 | 0.01 2.32 r 174 | data arrival time 2.32 175 | 176 | clock SCAN_CLK (rise edge) 100.00 100.00 177 | clock network delay (propagated) 0.29 100.29 178 | clock reconvergence pessimism 0.03 100.32 179 | U0_UART_RX/U0_deserializer/P_DATA_reg_5_/CLK (SDFFARX1_RVT) 180 | 0.00 100.32 r 181 | clock uncertainty -0.20 100.12 182 | library setup time -0.24 99.87 183 | data required time 99.87 184 | ------------------------------------------------------------------------ 185 | data required time 99.87 186 | data arrival time -2.32 187 | ------------------------------------------------------------------------ 188 | slack (MET) 97.56 189 | 190 | 191 | 192 | Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 193 | Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) 194 | Mode: default 195 | Corner: default 196 | Scenario: default 197 | Path Group: SCAN_CLK 198 | Path Type: max 199 | 200 | Point Incr Path 201 | ------------------------------------------------------------------------ 202 | clock SCAN_CLK (rise edge) 0.00 0.00 203 | clock network delay (propagated) 0.32 0.32 204 | 205 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 206 | 0.00 0.32 r 207 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 208 | 0.55 0.87 r 209 | U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.30 1.16 r 210 | U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.12 1.28 f 211 | U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.34 1.62 r 212 | U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.25 1.86 f 213 | U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.26 2.13 r 214 | U0_UART_RX/U0_deserializer/U10/Y (AO22X1_RVT) 0.18 2.30 r 215 | U0_UART_RX/U0_deserializer/P_DATA_reg_4_/D (SDFFARX1_RVT) 216 | 0.01 2.31 r 217 | data arrival time 2.31 218 | 219 | clock SCAN_CLK (rise edge) 100.00 100.00 220 | clock network delay (propagated) 0.29 100.29 221 | clock reconvergence pessimism 0.03 100.32 222 | U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 223 | 0.00 100.32 r 224 | clock uncertainty -0.20 100.12 225 | library setup time -0.24 99.88 226 | data required time 99.88 227 | ------------------------------------------------------------------------ 228 | data required time 99.88 229 | data arrival time -2.31 230 | ------------------------------------------------------------------------ 231 | slack (MET) 97.56 232 | 233 | 234 | 1 235 | -------------------------------------------------------------------------------- /pnr/scripts/ndr.tcl: -------------------------------------------------------------------------------- 1 | set CTS_NDR_MIN_ROUTING_LAYER "M4" 2 | set CTS_NDR_MAX_ROUTING_LAYER "M5" 3 | set CTS_LEAF_NDR_MIN_ROUTING_LAYER "M1" 4 | set CTS_LEAF_NDR_MAX_ROUTING_LAYER "M5" 5 | set CTS_NDR_RULE_NAME "cts_w2_s2_vlg" 6 | set CTS_LEAF_NDR_RULE_NAME "cts_w1_s2" 7 | 8 | 9 | create_routing_rule $CTS_NDR_RULE_NAME \ 10 | -default_reference_rule \ 11 | -widths { M1 0.1 M2 0.11 M3 0.11 M4 0.11 M5 0.11 } \ 12 | -spacings { M2 0.16 M3 0.45 M4 0.45 M5 1.1 } \ 13 | -spacing_length_thresholds {M2 3.0 M3 3.0 M4 4.0 M5 4.0} \ 14 | -taper_distance 0.4 \ 15 | -driver_taper_distance 0.4 \ 16 | -cuts { \ 17 | { VIA1 {V1LG 1} } \ 18 | { VIA2 {V2LG 1} } \ 19 | { VIA3 {V3LG 1} } \ 20 | { VIA4 {V4LG 1} } \ 21 | { VIA5 {V5LG 1} } \ 22 | } 23 | 24 | set_clock_routing_rules -rules $CTS_NDR_RULE_NAME \ 25 | -min_routing_layer $CTS_NDR_MIN_ROUTING_LAYER \ 26 | -max_routing_layer $CTS_NDR_MAX_ROUTING_LAYER 27 | 28 | 29 | 30 | 31 | create_routing_rule $CTS_LEAF_NDR_RULE_NAME \ 32 | -default_reference_rule \ 33 | -spacings { M2 0.16 M3 0.45 M4 0.45 M5 1.1 } 34 | 35 | set_clock_routing_rules -net_type sink -rules $CTS_LEAF_NDR_RULE_NAME \ 36 | -min_routing_layer $CTS_LEAF_NDR_MIN_ROUTING_LAYER \ 37 | -max_routing_layer $CTS_LEAF_NDR_MAX_ROUTING_LAYER 38 | 39 | -------------------------------------------------------------------------------- /pnr/scripts/power_network.tcl: -------------------------------------------------------------------------------- 1 | ### connect pg 2 | connect_pg_net -automatic 3 | 4 | ### remove before create 5 | remove_pg_strategies -all 6 | remove_pg_patterns -all 7 | remove_pg_regions -all 8 | remove_pg_via_master_rules -all 9 | remove_pg_strategy_via_rules -all 10 | remove_routes -net_types {power ground} -ring -stripe -lib_cell_pin_connect > /dev/null 11 | 12 | ################################################################################ 13 | # Application options 14 | ################################################################################ 15 | 16 | #To enable the compile_pg, create_pg_strap and create_pg_vias commands to validate the DRC correctness of power straps and vias with respect to signal routes 17 | set_app_options -name plan.pgroute.honor_signal_route_drc -value true 18 | 19 | # command merges overlapping shapes for via connection. By default, the tool does not merge the overlapping shapes 20 | set_app_options -name plan.pgroute.merge_shapes_for_via_creation -value true 21 | 22 | 23 | connect_pg_net -net VDD [get_pins -physical_context *VDD] 24 | connect_pg_net -net VSS [get_pins -physical_context *VSS] 25 | 26 | ################################################################################ 27 | # Build the main power mesh and ring. 28 | ################################################################################ 29 | 30 | create_pg_ring_pattern ring_pattern -horizontal_layer @hlayer \ 31 | -horizontal_width {@hwidth} -horizontal_spacing {@hspace} \ 32 | -vertical_layer @vlayer -vertical_width {@vwidth} \ 33 | -vertical_spacing {@vspace} -corner_bridge @cbridge \ 34 | -parameters {hlayer hwidth hspace vlayer vwidth vspace cbridge} 35 | 36 | # Set the ring strategy to apply the ring_pattern pattern to the core area and set the width and spacing parameters 37 | set_pg_strategy ring_strat -core \ 38 | -pattern {{name: ring_pattern} {nets: {VDD VSS}} 39 | {offset: {1 1}} {parameters: {M9 1 0.4 M8 1 0.4 true}}} \ 40 | -extension {{stop: design_boundary_and_generate_pin}} 41 | 42 | # Create the ring in the design 43 | compile_pg -strategies {ring_strat} 44 | 45 | # Define a new via rule, VIA_3x3, for the power mesh 46 | set_pg_via_master_rule VIA_3x3 -via_array_dimension {3 3} 47 | 48 | # Create the power and ground mesh pattern 49 | create_pg_mesh_pattern mesh_pattern -layers { 50 | {{vertical_layer: M8 } {width: 0.8} {spacing: interleaving} {pitch: 10}} \ 51 | {{horizontal_layer: M9} {width: 0.8} {spacing: interleaving} {pitch: 10}}} \ 52 | -via_rule {{{layers: M8} {layers: M9} {via_master: VIA_3x3}}} 53 | 54 | # Set the mesh strategy to apply the mesh_pattern pattern to the core area. Extend the mesh to the outermost ring 55 | set_pg_strategy mesh_strat -core -pattern {{pattern: mesh_pattern} {nets: {VDD VSS}}} -extension {{stop: outermost_ring}} 56 | 57 | # Create the mesh in the design 58 | compile_pg -strategies {mesh_strat} 59 | 60 | ################################################################################ 61 | # Build the standard cell rails 62 | ################################################################################ 63 | 64 | # Create a new 1x2 via 65 | set_pg_via_master_rule via1x2 -via_array_dimension {1 2} 66 | 67 | # Create the power and ground rail pattern 68 | create_pg_std_cell_conn_pattern rail_pattern -layers {M1} 69 | 70 | # Set the power and ground rail strategy to apply the rail_pattern pattern to the core area 71 | set_pg_strategy rail_strat \ 72 | -core \ 73 | -pattern {{pattern: rail_pattern}{nets: {VSS VDD}}} 74 | 75 | # Define a via strategy to insert via1x2 vias between existing straps and the new power rails specified by rail_strat strategy on the M8 layer 76 | set_pg_strategy_via_rule rail_rule -via_rule { 77 | {{{existing: strap} {layers: M8}} {strategies: rail_strat} {via_master: via1x2}} 78 | {{intersection: undefined} {via_master: nil}}} 79 | 80 | # Insert the new rails 81 | compile_pg -strategies rail_strat -via_rule rail_rule 82 | 83 | 84 | 85 | -------------------------------------------------------------------------------- /rtl/UART_RX/UART_RX.v: -------------------------------------------------------------------------------- 1 | 2 | module UART_RX # (parameter DATA_WIDTH = 8) 3 | 4 | ( 5 | input wire CLK, 6 | input wire RST, 7 | input wire RX_IN, 8 | input wire parity_enable, 9 | input wire parity_type, 10 | input wire [5:0] Prescale, 11 | output wire [DATA_WIDTH-1:0] P_DATA, 12 | output wire data_valid, 13 | output wire parity_error, 14 | output wire framing_error 15 | ); 16 | 17 | 18 | wire [3:0] bit_count ; 19 | wire [5:0] edge_count ; 20 | 21 | wire edge_bit_en; 22 | wire deser_en; 23 | wire par_chk_en; 24 | wire stp_chk_en; 25 | wire strt_chk_en; 26 | wire strt_glitch; 27 | wire sampled_bit; 28 | wire dat_samp_en; 29 | 30 | 31 | uart_rx_fsm # ( .DATA_WIDTH(8)) U0_uart_fsm ( 32 | .CLK(CLK), 33 | .RST(RST), 34 | .S_DATA(RX_IN), 35 | .Prescale(Prescale), 36 | .bit_count(bit_count), 37 | .parity_enable(parity_enable), 38 | .edge_count(edge_count), 39 | .strt_glitch(strt_glitch), 40 | .par_err(parity_error), 41 | .stp_err(framing_error), 42 | .strt_chk_en(strt_chk_en), 43 | .edge_bit_en(edge_bit_en), 44 | .deser_en(deser_en), 45 | .par_chk_en(par_chk_en), 46 | .stp_chk_en(stp_chk_en), 47 | .dat_samp_en(dat_samp_en), 48 | .data_valid(data_valid) 49 | ); 50 | 51 | 52 | edge_bit_counter U0_edge_bit_counter ( 53 | .CLK(CLK), 54 | .RST(RST), 55 | .Prescale(Prescale), 56 | .Enable(edge_bit_en), 57 | .bit_count(bit_count), 58 | .edge_count(edge_count) 59 | ); 60 | 61 | data_sampling U0_data_sampling ( 62 | .CLK(CLK), 63 | .RST(RST), 64 | .S_DATA(RX_IN), 65 | .Prescale(Prescale), 66 | .Enable(dat_samp_en), 67 | .edge_count(edge_count), 68 | .sampled_bit(sampled_bit) 69 | ); 70 | 71 | deserializer # ( .DATA_WIDTH(8)) U0_deserializer ( 72 | .CLK(CLK), 73 | .RST(RST), 74 | .Prescale(Prescale), 75 | .sampled_bit(sampled_bit), 76 | .Enable(deser_en), 77 | .edge_count(edge_count), 78 | .P_DATA(P_DATA) 79 | ); 80 | 81 | strt_chk U0_strt_chk ( 82 | .CLK(CLK), 83 | .RST(RST), 84 | .sampled_bit(sampled_bit), 85 | .Enable(strt_chk_en), 86 | .strt_glitch(strt_glitch) 87 | ); 88 | 89 | par_chk # ( .DATA_WIDTH(8)) U0_par_chk ( 90 | .CLK(CLK), 91 | .RST(RST), 92 | .parity_type(parity_type), 93 | .sampled_bit(sampled_bit), 94 | .Enable(par_chk_en), 95 | .P_DATA(P_DATA), 96 | .par_err(parity_error) 97 | ); 98 | 99 | stp_chk U0_stp_chk ( 100 | .CLK(CLK), 101 | .RST(RST), 102 | .sampled_bit(sampled_bit), 103 | .Enable(stp_chk_en), 104 | .stp_err(framing_error) 105 | ); 106 | 107 | 108 | endmodule 109 | 110 | -------------------------------------------------------------------------------- /rtl/UART_RX/data_sampling.v: -------------------------------------------------------------------------------- 1 | 2 | module data_sampling ( 3 | input wire CLK, 4 | input wire RST, 5 | input wire S_DATA, 6 | input wire [5:0] Prescale, 7 | input wire [5:0] edge_count, 8 | input wire Enable, 9 | output reg sampled_bit 10 | ); 11 | 12 | 13 | reg [2:0] Samples ; 14 | 15 | wire [4:0] half_edges , 16 | half_edges_p1 , 17 | half_edges_n1 ; 18 | 19 | 20 | assign half_edges = (Prescale >> 1) - 'b1 ; 21 | assign half_edges_p1 = half_edges + 'b1 ; 22 | assign half_edges_n1 = half_edges - 'b1 ; 23 | 24 | 25 | always @ (posedge CLK or negedge RST) 26 | begin 27 | if(!RST) 28 | begin 29 | Samples <= 'b0 ; 30 | end 31 | else 32 | begin 33 | if(Enable) 34 | begin 35 | if(edge_count == half_edges_n1) 36 | begin 37 | Samples[0] <= S_DATA ; 38 | end 39 | else if(edge_count == half_edges) 40 | begin 41 | Samples[1] <= S_DATA ; 42 | end 43 | else if(edge_count == half_edges_p1) 44 | begin 45 | Samples[2] <= S_DATA ; 46 | end 47 | end 48 | else 49 | begin 50 | Samples <= 'b0 ; 51 | end 52 | end 53 | end 54 | 55 | 56 | //decision 57 | always @ (posedge CLK or negedge RST) 58 | begin 59 | if(!RST) 60 | begin 61 | sampled_bit <= 'b0 ; 62 | end 63 | else 64 | begin 65 | if(Enable) 66 | begin 67 | case (Samples) 68 | 3'b000 : begin 69 | sampled_bit <= 1'b0 ; 70 | end 71 | 3'b001 : begin 72 | sampled_bit <= 1'b0 ; 73 | end 74 | 3'b010 : begin 75 | sampled_bit <= 1'b0 ; 76 | end 77 | 3'b011 : begin 78 | sampled_bit <= 1'b1 ; 79 | end 80 | 3'b100 : begin 81 | sampled_bit <= 1'b0 ; 82 | end 83 | 3'b101 : begin 84 | sampled_bit <= 1'b1 ; 85 | end 86 | 3'b110 : begin 87 | sampled_bit <= 1'b1 ; 88 | end 89 | 3'b111 : begin 90 | sampled_bit <= 1'b1 ; 91 | end 92 | endcase 93 | end 94 | else 95 | begin 96 | sampled_bit <= 1'b0 ; 97 | end 98 | end 99 | end 100 | 101 | 102 | endmodule 103 | -------------------------------------------------------------------------------- /rtl/UART_RX/deserializer.v: -------------------------------------------------------------------------------- 1 | 2 | module deserializer # ( parameter DATA_WIDTH = 8 ) 3 | 4 | ( 5 | input wire CLK, 6 | input wire RST, 7 | input wire sampled_bit, 8 | input wire Enable, 9 | input wire [5:0] edge_count, 10 | input wire [5:0] Prescale, 11 | output reg [DATA_WIDTH-1:0] P_DATA 12 | ); 13 | 14 | 15 | //deserializer 16 | always @ (posedge CLK or negedge RST) 17 | begin 18 | if(!RST) 19 | begin 20 | P_DATA <= 'b0 ; 21 | end 22 | else if(Enable && edge_count == (Prescale - 6'b1)) 23 | begin 24 | P_DATA <= {sampled_bit,P_DATA[7:1]} ; 25 | end 26 | end 27 | 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /rtl/UART_RX/edge_bit_counter.v: -------------------------------------------------------------------------------- 1 | module edge_bit_counter 2 | ( 3 | input wire CLK, 4 | input wire RST, 5 | input wire Enable, 6 | input wire [5:0] Prescale, 7 | output reg [3:0] bit_count, 8 | output reg [5:0] edge_count 9 | ); 10 | 11 | 12 | 13 | wire edge_count_done ; 14 | 15 | 16 | //edge counter 17 | always @ (posedge CLK or negedge RST) 18 | begin 19 | if(!RST) 20 | begin 21 | edge_count <= 'b0 ; 22 | end 23 | else if(Enable) 24 | begin 25 | if (edge_count_done) 26 | begin 27 | edge_count <= 'b0 ; 28 | end 29 | else 30 | begin 31 | edge_count <= edge_count + 'b1 ; 32 | end 33 | end 34 | else 35 | begin 36 | edge_count <= 'b0 ; 37 | end 38 | end 39 | 40 | assign edge_count_done = (edge_count == (Prescale - 6'b1)) ? 1'b1 : 1'b0 ; 41 | 42 | 43 | // bit counter 44 | always @ (posedge CLK or negedge RST) 45 | begin 46 | if(!RST) 47 | begin 48 | bit_count <= 'b0 ; 49 | end 50 | else if(Enable) 51 | begin 52 | if (edge_count_done) 53 | begin 54 | bit_count <= bit_count + 'b1 ; 55 | end 56 | end 57 | else 58 | begin 59 | bit_count <= 'b0 ; 60 | end 61 | end 62 | 63 | 64 | 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /rtl/UART_RX/par_chk.v: -------------------------------------------------------------------------------- 1 | 2 | module par_chk # ( parameter DATA_WIDTH = 8 ) 3 | 4 | ( 5 | input wire CLK, 6 | input wire RST, 7 | input wire parity_type, 8 | input wire sampled_bit, 9 | input wire Enable, 10 | input wire [DATA_WIDTH-1:0] P_DATA, 11 | output reg par_err 12 | ); 13 | 14 | 15 | reg parity ; 16 | 17 | // parity calc 18 | always @ (*) 19 | begin 20 | case(parity_type) 21 | 1'b0 : begin 22 | parity <= ^P_DATA ; // Even Parity 23 | end 24 | 1'b1 : begin 25 | parity <= ~^P_DATA ; // Odd Parity 26 | end 27 | endcase 28 | end 29 | 30 | 31 | // error check 32 | always @ (posedge CLK or negedge RST) 33 | begin 34 | if(!RST) 35 | begin 36 | par_err <= 1'b0 ; 37 | end 38 | else if(Enable) 39 | begin 40 | par_err <= parity ^ sampled_bit ; 41 | end 42 | end 43 | 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/UART_RX/stp_chk.v: -------------------------------------------------------------------------------- 1 | 2 | module stp_chk ( 3 | input wire CLK, 4 | input wire RST, 5 | input wire sampled_bit, 6 | input wire Enable, 7 | output reg stp_err 8 | ); 9 | 10 | 11 | 12 | // error check 13 | always @ (posedge CLK or negedge RST) 14 | begin 15 | if(!RST) 16 | begin 17 | stp_err <= 'b0 ; 18 | end 19 | else if(Enable) 20 | begin 21 | stp_err <= 1'b1 ^ sampled_bit ; 22 | end 23 | end 24 | 25 | 26 | 27 | endmodule -------------------------------------------------------------------------------- /rtl/UART_RX/strt_chk.v: -------------------------------------------------------------------------------- 1 | 2 | module strt_chk ( 3 | input wire CLK, 4 | input wire RST, 5 | input wire sampled_bit, 6 | input wire Enable, 7 | output reg strt_glitch 8 | ); 9 | 10 | 11 | 12 | // error check 13 | always @ (posedge CLK or negedge RST) 14 | begin 15 | if(!RST) 16 | begin 17 | strt_glitch <= 'b0 ; 18 | end 19 | else if(Enable) 20 | begin 21 | strt_glitch <= sampled_bit ; 22 | end 23 | end 24 | 25 | 26 | 27 | endmodule -------------------------------------------------------------------------------- /rtl/UART_RX/uart_rx_fsm.v: -------------------------------------------------------------------------------- 1 | 2 | module uart_rx_fsm # ( parameter DATA_WIDTH = 8 ) ( 3 | 4 | input wire CLK, 5 | input wire RST, 6 | input wire S_DATA, 7 | input wire [5:0] Prescale, 8 | input wire parity_enable, 9 | input wire [3:0] bit_count, 10 | input wire [5:0] edge_count, 11 | input wire par_err, 12 | input wire stp_err, 13 | input wire strt_glitch, 14 | output reg strt_chk_en, 15 | output reg edge_bit_en, 16 | output reg deser_en, 17 | output reg par_chk_en, 18 | output reg stp_chk_en, 19 | output reg dat_samp_en, 20 | output reg data_valid 21 | ); 22 | 23 | 24 | // gray state encoding 25 | localparam [2:0] IDLE = 3'b000 , 26 | start = 3'b001 , 27 | data = 3'b011 , 28 | parity = 3'b010 , 29 | stop = 3'b110 , 30 | err_chk = 3'b111 ; 31 | 32 | reg [2:0] current_state , 33 | next_state ; 34 | 35 | wire [5:0] check_edge , 36 | error_check_edge; 37 | 38 | 39 | assign check_edge = (Prescale - 6'd1) ; 40 | assign error_check_edge = (Prescale - 6'd2) ; 41 | 42 | //state transiton 43 | always @ (posedge CLK or negedge RST) 44 | begin 45 | if(!RST) 46 | begin 47 | current_state <= IDLE ; 48 | end 49 | else 50 | begin 51 | current_state <= next_state ; 52 | end 53 | end 54 | 55 | 56 | // next state logic 57 | always @ (*) 58 | begin 59 | case(current_state) 60 | IDLE : begin 61 | if(!S_DATA) 62 | next_state = start ; 63 | else 64 | next_state = IDLE ; 65 | end 66 | start : begin 67 | if(bit_count == 4'd0 && edge_count == check_edge) 68 | begin 69 | if(!strt_glitch) // check that start bit not a glitch 70 | begin 71 | next_state = data ; 72 | end 73 | else 74 | begin 75 | next_state = IDLE ; 76 | end 77 | end 78 | else 79 | begin 80 | next_state = start ; 81 | end 82 | end 83 | data : begin 84 | if(bit_count == 4'd8 && edge_count == check_edge) 85 | begin 86 | if(parity_enable) 87 | begin 88 | next_state = parity ; 89 | end 90 | else 91 | begin 92 | next_state = stop ; 93 | end 94 | end 95 | else 96 | begin 97 | next_state = data ; 98 | end 99 | end 100 | parity : begin 101 | if(bit_count == 4'd9 && edge_count == check_edge) 102 | begin 103 | next_state = stop ; 104 | end 105 | else 106 | begin 107 | next_state = parity ; 108 | end 109 | end 110 | stop : begin 111 | if(parity_enable) 112 | begin 113 | if(bit_count == 4'd10 && edge_count == error_check_edge) 114 | begin 115 | next_state = err_chk ; 116 | end 117 | else 118 | begin 119 | next_state = stop ; 120 | end 121 | end 122 | else 123 | begin 124 | if(bit_count == 4'd9 && edge_count == error_check_edge) 125 | begin 126 | next_state = err_chk ; 127 | end 128 | else 129 | begin 130 | next_state = stop ; 131 | end 132 | end 133 | end 134 | err_chk : begin 135 | if(!S_DATA) 136 | next_state = start ; 137 | else 138 | next_state = IDLE ; 139 | end 140 | default: begin 141 | next_state = IDLE ; 142 | end 143 | endcase 144 | end 145 | 146 | 147 | // output logic 148 | always @ (*) 149 | begin 150 | edge_bit_en = 1'b0 ; 151 | dat_samp_en = 1'b0 ; 152 | deser_en = 1'b0 ; 153 | par_chk_en = 1'b0 ; 154 | stp_chk_en = 1'b0 ; 155 | data_valid = 1'b0 ; 156 | strt_chk_en = 1'b0 ; 157 | case(current_state) 158 | IDLE : begin 159 | if(!S_DATA) 160 | begin 161 | edge_bit_en = 1'b1 ; 162 | deser_en = 1'b0 ; 163 | par_chk_en = 1'b0 ; 164 | stp_chk_en = 1'b0 ; 165 | strt_chk_en = 1'b1 ; 166 | dat_samp_en = 1'b1 ; 167 | end 168 | else 169 | begin 170 | strt_chk_en = 1'b0 ; 171 | edge_bit_en = 1'b0 ; 172 | deser_en = 1'b0 ; 173 | par_chk_en = 1'b0 ; 174 | stp_chk_en = 1'b0 ; 175 | dat_samp_en = 1'b0 ; 176 | end 177 | end 178 | start : begin 179 | strt_chk_en = 1'b1 ; 180 | edge_bit_en = 1'b1 ; 181 | deser_en = 1'b0 ; 182 | par_chk_en = 1'b0 ; 183 | stp_chk_en = 1'b0 ; 184 | dat_samp_en = 1'b1 ; 185 | end 186 | data : begin 187 | edge_bit_en = 1'b1 ; 188 | deser_en = 1'b1 ; 189 | par_chk_en = 1'b0 ; 190 | stp_chk_en = 1'b0 ; 191 | dat_samp_en = 1'b1 ; 192 | end 193 | parity : begin 194 | edge_bit_en = 1'b1 ; 195 | deser_en = 1'b0 ; 196 | par_chk_en = 1'b1 ; 197 | stp_chk_en = 1'b0 ; 198 | dat_samp_en = 1'b1 ; 199 | end 200 | stop : begin 201 | edge_bit_en = 1'b1 ; 202 | deser_en = 1'b0 ; 203 | par_chk_en = 1'b0 ; 204 | stp_chk_en = 1'b1 ; 205 | dat_samp_en = 1'b1 ; 206 | end 207 | err_chk: begin 208 | edge_bit_en = 1'b0 ; 209 | deser_en = 1'b0 ; 210 | par_chk_en = 1'b0 ; 211 | stp_chk_en = 1'b0 ; 212 | dat_samp_en = 1'b1 ; 213 | if(par_err | stp_err) 214 | begin 215 | data_valid = 1'b0 ; 216 | end 217 | else 218 | begin 219 | data_valid = 1'b1 ; 220 | end 221 | end 222 | default: begin 223 | edge_bit_en = 1'b0 ; 224 | deser_en = 1'b0 ; 225 | par_chk_en = 1'b0 ; 226 | stp_chk_en = 1'b0 ; 227 | data_valid = 1'b0 ; 228 | dat_samp_en = 1'b0 ; 229 | end 230 | endcase 231 | end 232 | 233 | endmodule 234 | 235 | -------------------------------------------------------------------------------- /rtl/UART_TOP/UART.v: -------------------------------------------------------------------------------- 1 | 2 | module UART # ( parameter DATA_WIDTH = 8) 3 | 4 | ( 5 | input wire RST, 6 | input wire TX_CLK, 7 | input wire RX_CLK, 8 | input wire RX_IN_S, 9 | output wire [DATA_WIDTH-1:0] RX_OUT_P, 10 | output wire RX_OUT_V, 11 | input wire [DATA_WIDTH-1:0] TX_IN_P, 12 | input wire TX_IN_V, 13 | output wire TX_OUT_S, 14 | output wire TX_OUT_V, 15 | input wire [5:0] Prescale, 16 | input wire parity_enable, 17 | input wire parity_type, 18 | output wire parity_error, 19 | output wire framing_error 20 | ); 21 | 22 | 23 | UART_TX #(.DATA_WIDTH(DATA_WIDTH)) U0_UART_TX ( 24 | .CLK(TX_CLK), 25 | .RST(RST), 26 | .P_DATA(TX_IN_P), 27 | .Data_Valid(TX_IN_V), 28 | .parity_enable(parity_enable), 29 | .parity_type(parity_type), 30 | .TX_OUT(TX_OUT_S), 31 | .busy(TX_OUT_V) 32 | ); 33 | 34 | 35 | UART_RX U0_UART_RX ( 36 | .CLK(RX_CLK), 37 | .RST(RST), 38 | .RX_IN(RX_IN_S), 39 | .Prescale(Prescale), 40 | .parity_enable(parity_enable), 41 | .parity_type(parity_type), 42 | .P_DATA(RX_OUT_P), 43 | .data_valid(RX_OUT_V), 44 | .parity_error(parity_error), 45 | .framing_error(framing_error) 46 | ); 47 | 48 | 49 | 50 | 51 | endmodule 52 | 53 | -------------------------------------------------------------------------------- /rtl/UART_TOP_DFT/UART.v: -------------------------------------------------------------------------------- 1 | 2 | module UART # ( parameter DATA_WIDTH = 8) 3 | 4 | ( 5 | input wire RST, 6 | input wire TX_CLK, 7 | input wire RX_CLK, 8 | input wire RX_IN_S, 9 | output wire [DATA_WIDTH-1:0] RX_OUT_P, 10 | output wire RX_OUT_V, 11 | input wire [DATA_WIDTH-1:0] TX_IN_P, 12 | input wire TX_IN_V, 13 | output wire TX_OUT_S, 14 | output wire TX_OUT_V, 15 | input wire [5:0] Prescale, 16 | input wire parity_enable, 17 | input wire parity_type, 18 | output wire parity_error, 19 | output wire framing_error, 20 | 21 | input wire SI , 22 | input wire SE , 23 | output wire SO , 24 | input wire scan_clk, 25 | input wire scan_rst, 26 | input wire test_mode 27 | ); 28 | 29 | wire UART_RX_SCAN_CLK ; 30 | wire UART_TX_SCAN_CLK ; 31 | wire SCAN_RST ; 32 | 33 | // Mux generated UART_RX_CLK & SCAN_CLK 34 | mux2X1 U0_mux2X1 ( 35 | .IN_0(RX_CLK), 36 | .IN_1(scan_clk), 37 | .SEL(test_mode), 38 | .OUT(UART_RX_SCAN_CLK) 39 | ); 40 | 41 | // Mux generated UART_TX_CLK & SCAN_CLK 42 | mux2X1 U1_mux2X1 ( 43 | .IN_0(TX_CLK), 44 | .IN_1(scan_clk), 45 | .SEL(test_mode), 46 | .OUT(UART_TX_SCAN_CLK) 47 | ); 48 | 49 | // Mux RST & scan_rst 50 | mux2X1 U2_mux2X1 ( 51 | .IN_0(RST), 52 | .IN_1(scan_rst), 53 | .SEL(test_mode), 54 | .OUT(SCAN_RST) 55 | ); 56 | 57 | UART_TX #(.DATA_WIDTH(DATA_WIDTH)) U0_UART_TX ( 58 | .CLK(UART_TX_SCAN_CLK), 59 | .RST(SCAN_RST), 60 | .P_DATA(TX_IN_P), 61 | .Data_Valid(TX_IN_V), 62 | .parity_enable(parity_enable), 63 | .parity_type(parity_type), 64 | .TX_OUT(TX_OUT_S), 65 | .busy(TX_OUT_V) 66 | ); 67 | 68 | 69 | UART_RX U0_UART_RX ( 70 | .CLK(UART_RX_SCAN_CLK), 71 | .RST(SCAN_RST), 72 | .RX_IN(RX_IN_S), 73 | .Prescale(Prescale), 74 | .parity_enable(parity_enable), 75 | .parity_type(parity_type), 76 | .P_DATA(RX_OUT_P), 77 | .data_valid(RX_OUT_V), 78 | .parity_error(parity_error), 79 | .framing_error(framing_error) 80 | ); 81 | 82 | 83 | endmodule 84 | 85 | -------------------------------------------------------------------------------- /rtl/UART_TOP_DFT/mux2X1.v: -------------------------------------------------------------------------------- 1 | 2 | module mux2X1 ( 3 | 4 | input wire IN_0, 5 | input wire IN_1, 6 | input wire SEL, 7 | output wire OUT 8 | 9 | ); 10 | 11 | 12 | assign OUT = SEL ? IN_1 : IN_0 ; 13 | 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /rtl/UART_TX/Serializer.v: -------------------------------------------------------------------------------- 1 | 2 | module Serializer # ( parameter WIDTH = 8 ) 3 | 4 | ( 5 | input wire CLK, 6 | input wire RST, 7 | input wire [WIDTH-1:0] DATA, 8 | input wire Enable, 9 | input wire Busy, 10 | input wire Data_Valid, 11 | output wire ser_out, 12 | output wire ser_done 13 | ); 14 | 15 | reg [WIDTH-1:0] DATA_V ; 16 | reg [2:0] ser_count ; 17 | 18 | //isolate input 19 | always @ (posedge CLK or negedge RST) 20 | begin 21 | if(!RST) 22 | begin 23 | DATA_V <= 'b0 ; 24 | end 25 | else if(Data_Valid && !Busy) 26 | begin 27 | DATA_V <= DATA ; 28 | end 29 | else if(Enable) 30 | begin 31 | DATA_V <= DATA_V >> 1 ; // shift register 32 | end 33 | end 34 | 35 | 36 | //counter 37 | always @ (posedge CLK or negedge RST) 38 | begin 39 | if(!RST) 40 | begin 41 | ser_count <= 'b0 ; 42 | end 43 | else 44 | begin 45 | if (Enable) 46 | begin 47 | ser_count <= ser_count + 'b1 ; 48 | end 49 | else 50 | begin 51 | ser_count <= 'b0 ; 52 | end 53 | end 54 | end 55 | 56 | assign ser_done = (ser_count == 'b111) ? 1'b1 : 1'b0 ; 57 | 58 | assign ser_out = DATA_V[0] ; 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /rtl/UART_TX/UART_TX.v: -------------------------------------------------------------------------------- 1 | 2 | module UART_TX # (parameter DATA_WIDTH = 8) 3 | ( 4 | input wire CLK, 5 | input wire RST, 6 | input wire [DATA_WIDTH-1:0] P_DATA, 7 | input wire Data_Valid, 8 | input wire parity_enable, 9 | input wire parity_type, 10 | output wire TX_OUT, 11 | output wire busy 12 | 13 | ); 14 | 15 | wire seriz_en , 16 | seriz_done , 17 | ser_data , 18 | parity ; 19 | 20 | wire [1:0] mux_sel ; 21 | 22 | uart_tx_fsm U0_fsm ( 23 | .CLK(CLK), 24 | .RST(RST), 25 | .Data_Valid(Data_Valid), 26 | .parity_enable(parity_enable), 27 | .ser_done(seriz_done), 28 | .Ser_enable(seriz_en), 29 | .mux_sel(mux_sel), 30 | .busy(busy) 31 | ); 32 | 33 | Serializer # (.WIDTH(DATA_WIDTH)) U0_Serializer ( 34 | .CLK(CLK), 35 | .RST(RST), 36 | .DATA(P_DATA), 37 | .Busy(busy), 38 | .Enable(seriz_en), 39 | .Data_Valid(Data_Valid), 40 | .ser_out(ser_data), 41 | .ser_done(seriz_done) 42 | ); 43 | 44 | mux U0_mux ( 45 | .CLK(CLK), 46 | .RST(RST), 47 | .IN_0(1'b0), 48 | .IN_1(ser_data), 49 | .IN_2(parity), 50 | .IN_3(1'b1), 51 | .SEL(mux_sel), 52 | .OUT(TX_OUT) 53 | ); 54 | 55 | parity_calc # (.WIDTH(DATA_WIDTH)) U0_parity_calc ( 56 | .CLK(CLK), 57 | .RST(RST), 58 | .parity_enable(parity_enable), 59 | .parity_type(parity_type), 60 | .DATA(P_DATA), 61 | .Busy(busy), 62 | .Data_Valid(Data_Valid), 63 | .parity(parity) 64 | ); 65 | 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /rtl/UART_TX/mux.v: -------------------------------------------------------------------------------- 1 | 2 | module mux ( 3 | 4 | input wire CLK, 5 | input wire RST, 6 | input wire IN_0, 7 | input wire IN_1, 8 | input wire IN_2, 9 | input wire IN_3, 10 | input wire [1:0] SEL, 11 | output reg OUT 12 | 13 | ); 14 | 15 | reg mux_out ; 16 | 17 | always @ (*) 18 | begin 19 | case(SEL) 20 | 2'b00 : begin 21 | mux_out = IN_0 ; 22 | end 23 | 2'b01 : begin 24 | mux_out = IN_1 ; 25 | end 26 | 2'b10 : begin 27 | mux_out = IN_2 ; 28 | end 29 | 2'b11 : begin 30 | mux_out = IN_3 ; 31 | end 32 | endcase 33 | end 34 | 35 | 36 | //register mux output 37 | always @ (posedge CLK or negedge RST) 38 | begin 39 | if(!RST) 40 | begin 41 | OUT <= 'b0 ; 42 | end 43 | else 44 | begin 45 | OUT <= mux_out ; 46 | end 47 | end 48 | 49 | 50 | endmodule 51 | 52 | -------------------------------------------------------------------------------- /rtl/UART_TX/mux.v~: -------------------------------------------------------------------------------- 1 | 2 | module mux ( 3 | 4 | input wire CLK, 5 | input wire RST, 6 | input wire IN_0, 7 | input wire IN_1, 8 | input wire IN_2, 9 | input wire IN_3, 10 | input wire [1:0] SEL, 11 | output reg OUT 12 | 13 | ); 14 | 15 | reg mux_out ; 16 | 17 | always @ (*) 18 | begin 19 | case(SEL) 20 | 2'b00 : begin 21 | mux_out <= IN_0 ; 22 | end 23 | 2'b01 : begin 24 | mux_out <= IN_1 ; 25 | end 26 | 2'b10 : begin 27 | mux_out <= IN_2 ; 28 | end 29 | 2'b11 : begin 30 | mux_out <= IN_3 ; 31 | end 32 | endcase 33 | end 34 | 35 | 36 | //register mux output 37 | always @ (posedge CLK or negedge RST) 38 | begin 39 | if(!RST) 40 | begin 41 | OUT <= 'b0 ; 42 | end 43 | else 44 | begin 45 | OUT <= mux_out ; 46 | end 47 | end 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /rtl/UART_TX/parity_calc.v: -------------------------------------------------------------------------------- 1 | module parity_calc # ( parameter WIDTH = 8 ) 2 | 3 | ( 4 | input wire CLK, 5 | input wire RST, 6 | input wire parity_enable, 7 | input wire parity_type, 8 | input wire Busy, 9 | input wire [WIDTH-1:0] DATA, 10 | input wire Data_Valid, 11 | output reg parity 12 | ); 13 | 14 | reg [WIDTH-1:0] DATA_V ; 15 | 16 | //isolate input 17 | always @ (posedge CLK or negedge RST) 18 | begin 19 | if(!RST) 20 | begin 21 | DATA_V <= 'b0 ; 22 | end 23 | else if(Data_Valid && !Busy) 24 | begin 25 | DATA_V <= DATA ; 26 | end 27 | end 28 | 29 | 30 | always @ (posedge CLK or negedge RST) 31 | begin 32 | if(!RST) 33 | begin 34 | parity <= 'b0 ; 35 | end 36 | else 37 | begin 38 | if (parity_enable) 39 | begin 40 | case(parity_type) 41 | 1'b0 : begin 42 | parity <= ^DATA_V ; // Even Parity 43 | end 44 | 1'b1 : begin 45 | parity <= ~^DATA_V ; // Odd Parity 46 | end 47 | endcase 48 | end 49 | end 50 | end 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /rtl/UART_TX/uart_tx_fsm.v: -------------------------------------------------------------------------------- 1 | 2 | module uart_tx_fsm ( 3 | 4 | input wire CLK, 5 | input wire RST, 6 | input wire Data_Valid, 7 | input wire ser_done, 8 | input wire parity_enable, 9 | output reg Ser_enable, 10 | output reg [1:0] mux_sel, 11 | output reg busy 12 | ); 13 | 14 | 15 | // gray state encoding 16 | parameter [2:0] IDLE = 3'b000, 17 | start = 3'b001, 18 | data = 3'b011, 19 | parity = 3'b010, 20 | stop = 3'b110 ; 21 | 22 | reg [2:0] current_state , next_state ; 23 | 24 | 25 | reg busy_c ; 26 | 27 | //state transiton 28 | always @ (posedge CLK or negedge RST) 29 | begin 30 | if(!RST) 31 | begin 32 | current_state <= IDLE ; 33 | end 34 | else 35 | begin 36 | current_state <= next_state ; 37 | end 38 | end 39 | 40 | 41 | // next state logic 42 | always @ (*) 43 | begin 44 | case(current_state) 45 | IDLE : begin 46 | if(Data_Valid) 47 | next_state = start ; 48 | else 49 | next_state = IDLE ; 50 | end 51 | start : begin 52 | next_state = data ; 53 | end 54 | data : begin 55 | if(ser_done) 56 | begin 57 | if(parity_enable) 58 | next_state = parity ; 59 | else 60 | next_state = stop ; 61 | end 62 | else 63 | next_state = data ; 64 | end 65 | parity : begin 66 | next_state = stop ; 67 | end 68 | stop : begin 69 | next_state = IDLE ; 70 | end 71 | default: begin 72 | next_state = IDLE ; 73 | end 74 | endcase 75 | end 76 | 77 | 78 | // output logic 79 | always @ (*) 80 | begin 81 | Ser_enable = 1'b0 ; 82 | mux_sel = 2'b00 ; 83 | busy_c = 1'b0 ; 84 | case(current_state) 85 | IDLE : begin 86 | Ser_enable = 1'b0 ; 87 | mux_sel = 2'b11 ; 88 | busy_c = 1'b0 ; 89 | end 90 | start : begin 91 | Ser_enable = 1'b0 ; 92 | busy_c = 1'b1 ; 93 | mux_sel = 2'b00 ; 94 | end 95 | data : begin 96 | Ser_enable = 1'b1 ; 97 | busy_c = 1'b1 ; 98 | mux_sel = 2'b01 ; 99 | if(ser_done) 100 | Ser_enable = 1'b0 ; 101 | else 102 | Ser_enable = 1'b1 ; 103 | end 104 | parity : begin 105 | busy_c = 1'b1 ; 106 | mux_sel = 2'b10 ; 107 | end 108 | stop : begin 109 | busy_c = 1'b1 ; 110 | mux_sel = 2'b11 ; 111 | end 112 | default: begin 113 | busy_c = 1'b0 ; 114 | Ser_enable = 1'b0 ; 115 | mux_sel = 2'b00 ; 116 | end 117 | endcase 118 | end 119 | 120 | 121 | 122 | //register output 123 | always @ (posedge CLK or negedge RST) 124 | begin 125 | if(!RST) 126 | begin 127 | busy <= 1'b0 ; 128 | end 129 | else 130 | begin 131 | busy <= busy_c ; 132 | end 133 | end 134 | 135 | 136 | endmodule 137 | 138 | -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test1.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test2.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test3.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test4.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test5.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test6.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test7.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test8.png -------------------------------------------------------------------------------- /sim/UART_RX/Test_cases/Test9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_RX/Test_cases/Test9.png -------------------------------------------------------------------------------- /sim/UART_RX/UART_RX_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module UART_RX_TB (); 3 | 4 | ///////////////////////////////////////////////////////// 5 | ///////////////////// Parameters //////////////////////// 6 | ///////////////////////////////////////////////////////// 7 | 8 | parameter DATA_WIDTH = 8 ; 9 | parameter RX_CLK_PERIOD = 10 ; 10 | 11 | ///////////////////////////////////////////////////////// 12 | //////////////////// DUT Signals //////////////////////// 13 | ///////////////////////////////////////////////////////// 14 | 15 | reg RX_CLK_TB; 16 | reg RST_TB; 17 | reg RX_IN_TB; 18 | reg [5:0] Prescale_TB; 19 | reg parity_enable_TB; 20 | reg parity_type_TB; 21 | wire [DATA_WIDTH-1:0] P_DATA_TB; 22 | wire data_valid_TB; 23 | wire parity_error_TB; 24 | wire framing_error_TB; 25 | 26 | reg TX_CLK_TB; 27 | 28 | //////////////////////////////////////////////////////// 29 | ////////////////// initial block /////////////////////// 30 | //////////////////////////////////////////////////////// 31 | 32 | initial 33 | begin 34 | 35 | // Initialization 36 | initialize() ; 37 | 38 | // Reset 39 | reset() ; 40 | 41 | ////////////// Test Case 1 ////////////////// 42 | 43 | // UART Configuration (Parity Enable = 1 && Parity Type = 1 && Prescale = 32) 44 | UART_CONFG (1'b1,1'b1,6'd32); 45 | 46 | // Load Data 47 | DATA_IN(8'hBB); 48 | 49 | // Check Output 50 | chk_rx_out(8'hBB,1) ; 51 | 52 | ////////////// Test Case 2 ////////////////// 53 | 54 | // UART Configuration (Parity Enable = 1 && Parity Type = 0 && Prescale = 32) 55 | UART_CONFG (1'b1,1'b0,6'd32); 56 | 57 | // Load Data 58 | DATA_IN(8'hBB); 59 | 60 | // Check Output 61 | chk_rx_out(8'hBB,2) ; 62 | 63 | ////////////// Test Case 3 ////////////////// 64 | 65 | // UART Configuration (Parity Enable = 0 && Parity Type = 0 && Prescale = 32) 66 | UART_CONFG (1'b0,1'b0,6'd32); 67 | 68 | // Load Data 69 | DATA_IN(8'hBB); 70 | 71 | // Check Output 72 | chk_rx_out(8'hBB,3) ; 73 | 74 | ////////////// Test Case 4 ////////////////// 75 | 76 | // UART Configuration (Parity Enable = 1 && Parity Type = 1 && Prescale = 16) 77 | UART_CONFG (1'b1,1'b1,6'd16); 78 | 79 | // Load Data 80 | DATA_IN(8'hBB); 81 | 82 | // Check Output 83 | chk_rx_out(8'hBB,4) ; 84 | 85 | ////////////// Test Case 5 ////////////////// 86 | 87 | // UART Configuration (Parity Enable = 1 && Parity Type = 0 && Prescale = 16) 88 | UART_CONFG (1'b1,1'b0,6'd16); 89 | 90 | // Load Data 91 | DATA_IN(8'hBB); 92 | 93 | // Check Output 94 | chk_rx_out(8'hBB,5) ; 95 | 96 | ////////////// Test Case 6 ////////////////// 97 | 98 | // UART Configuration (Parity Enable = 0 && Parity Type = 0 && Prescale = 16) 99 | UART_CONFG (1'b0,1'b0,6'd16); 100 | 101 | // Load Data 102 | DATA_IN(8'hBB); 103 | 104 | // Check Output 105 | chk_rx_out(8'hBB,6) ; 106 | 107 | ////////////// Test Case 7 ////////////////// 108 | 109 | // UART Configuration (Parity Enable = 1 && Parity Type = 1 && Prescale = 8) 110 | UART_CONFG (1'b1,1'b1,6'd8); 111 | 112 | // Load Data 113 | DATA_IN(8'hBB); 114 | 115 | // Check Output 116 | chk_rx_out(8'hBB,7) ; 117 | 118 | ////////////// Test Case 8 ////////////////// 119 | 120 | // UART Configuration (Parity Enable = 1 && Parity Type = 1 && Prescale = 8) 121 | UART_CONFG (1'b1,1'b0,6'd8); 122 | 123 | // Load Data 124 | DATA_IN(8'hBB); 125 | 126 | // Check Output 127 | chk_rx_out(8'hBB,8) ; 128 | 129 | ////////////// Test Case 9 ////////////////// 130 | 131 | // UART Configuration (Parity Enable = 1 && Parity Type = 1 && Prescale = 8) 132 | UART_CONFG (1'b0,1'b0,6'd8); 133 | 134 | // Load Data 135 | DATA_IN(8'hBB); 136 | 137 | // Check Output 138 | chk_rx_out(8'hBB,9) ; 139 | 140 | #4000 141 | 142 | $stop ; 143 | 144 | end 145 | 146 | ///////////////////// Clock Generator ////////////////// 147 | 148 | always #(RX_CLK_PERIOD/2) RX_CLK_TB = ~RX_CLK_TB ; 149 | 150 | always #(Prescale_TB*RX_CLK_PERIOD/2) TX_CLK_TB = ~TX_CLK_TB ; 151 | 152 | //////////////////////////////////////////////////////// 153 | /////////////////////// TASKS ////////////////////////// 154 | //////////////////////////////////////////////////////// 155 | 156 | /////////////// Signals Initialization ////////////////// 157 | 158 | task initialize ; 159 | begin 160 | RX_CLK_TB = 1'b0 ; 161 | TX_CLK_TB = 1'b0 ; 162 | RST_TB = 1'b1 ; // rst is deactivated 163 | Prescale_TB = 6'b100000 ; // prescale = 32 164 | parity_enable_TB = 1'b1 ; 165 | parity_type_TB = 1'b0 ; 166 | RX_IN_TB = 1'b1 ; 167 | end 168 | endtask 169 | 170 | ///////////////////////// RESET ///////////////////////// 171 | task reset ; 172 | begin 173 | #(RX_CLK_PERIOD) 174 | RST_TB = 'b0; // rst is activated 175 | #(RX_CLK_PERIOD) 176 | RST_TB = 'b1; 177 | #(RX_CLK_PERIOD) ; 178 | end 179 | endtask 180 | 181 | ///////////////////// Configuration //////////////////// 182 | task UART_CONFG ; 183 | input PAR_EN ; 184 | input PAR_TYP ; 185 | input [5:0] PRESCALE; 186 | 187 | begin 188 | parity_enable_TB = PAR_EN ; 189 | parity_type_TB = PAR_TYP ; 190 | Prescale_TB = PRESCALE ; 191 | end 192 | endtask 193 | 194 | /////////////////////// Data IN ///////////////////////// 195 | task DATA_IN ; 196 | input [DATA_WIDTH-1:0] DATA ; 197 | 198 | integer i ; 199 | 200 | begin 201 | 202 | @ (posedge TX_CLK_TB) 203 | RX_IN_TB <= 1'b0 ; // start_bit 204 | 205 | for(i=0; i<8; i=i+1) 206 | begin 207 | @(posedge TX_CLK_TB) 208 | RX_IN_TB <= DATA[i] ; // data bits 209 | end 210 | 211 | if(parity_enable_TB) 212 | begin 213 | @ (posedge TX_CLK_TB) 214 | case(parity_type_TB) 215 | 1'b0 : RX_IN_TB <= ^DATA ; // Even Parity 216 | 1'b1 : RX_IN_TB <= ~^DATA ; // Odd Parity 217 | endcase 218 | end 219 | 220 | @ (posedge TX_CLK_TB) 221 | RX_IN_TB <= 1'b1 ; // stop_bit 222 | 223 | end 224 | endtask 225 | 226 | 227 | ////////////////// Check Output //////////////////// 228 | task chk_rx_out ; 229 | input [DATA_WIDTH-1:0] expec_out ; 230 | input [4:0] Test_NUM; 231 | 232 | begin 233 | 234 | @(posedge data_valid_TB) 235 | if(P_DATA_TB == expec_out) 236 | begin 237 | $display("Test Case %d is succeeded",Test_NUM,); 238 | end 239 | else 240 | begin 241 | $display("Test Case %d is failed", Test_NUM); 242 | end 243 | end 244 | endtask 245 | 246 | //////////////////////////////////////////////////////// 247 | ///////////////// Design Instaniation ////////////////// 248 | //////////////////////////////////////////////////////// 249 | 250 | UART_RX DUT ( 251 | .CLK(RX_CLK_TB), 252 | .RST(RST_TB), 253 | .RX_IN(RX_IN_TB), 254 | .Prescale(Prescale_TB), 255 | .parity_enable(parity_enable_TB), 256 | .parity_type(parity_type_TB), 257 | .P_DATA(P_DATA_TB), 258 | .data_valid(data_valid_TB), 259 | .parity_error(parity_error_TB), 260 | .framing_error(framing_error_TB) 261 | ); 262 | 263 | endmodule 264 | -------------------------------------------------------------------------------- /sim/UART_TX/Test_cases/Test1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_TX/Test_cases/Test1.png -------------------------------------------------------------------------------- /sim/UART_TX/Test_cases/Test2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_TX/Test_cases/Test2.png -------------------------------------------------------------------------------- /sim/UART_TX/Test_cases/Test3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/sim/UART_TX/Test_cases/Test3.png -------------------------------------------------------------------------------- /sim/UART_TX/UART_TX_TB.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module UART_TX_TB (); 4 | 5 | ///////////////////////////////////////////////////////// 6 | ///////////////////// Parameters //////////////////////// 7 | ///////////////////////////////////////////////////////// 8 | 9 | parameter DATA_WD_TB = 8 ; 10 | parameter CLK_PERIOD = 10 ; 11 | 12 | 13 | ///////////////////////////////////////////////////////// 14 | //////////////////// DUT Signals //////////////////////// 15 | ///////////////////////////////////////////////////////// 16 | 17 | 18 | reg CLK_TB; 19 | reg RST_TB; 20 | reg [DATA_WD_TB-1:0] P_DATA_TB; 21 | reg Data_Valid_TB; 22 | reg parity_enable_TB; 23 | reg parity_type_TB; 24 | wire TX_OUT_TB; 25 | wire busy_TB; 26 | 27 | 28 | 29 | //////////////////////////////////////////////////////// 30 | ////////////////// initial block /////////////////////// 31 | //////////////////////////////////////////////////////// 32 | 33 | initial 34 | begin 35 | 36 | // Initialization 37 | initialize() ; 38 | 39 | // Reset 40 | reset() ; 41 | 42 | 43 | ////////////// Test Case 1 (No Parity) ////////////////// 44 | 45 | // UART Configuration (Parity Enable = 0) 46 | UART_CONFG (1'b0,1'b0); 47 | 48 | // Load Data 49 | DATA_IN(8'hA3); 50 | 51 | // Check Output 52 | chk_tx_out(8'hA3,0,0,0) ; 53 | 54 | #20 55 | 56 | ////////////// Test Case 2 (Even Parity) //////////////// 57 | 58 | // UART Configuration (Parity Enable = 1 && Parity Type = 0) 59 | UART_CONFG (1'b1,1'b0); 60 | 61 | // Load Data 62 | DATA_IN(8'hB4); 63 | 64 | // Check Output 65 | chk_tx_out(8'hB4,1,0,1) ; 66 | 67 | #20 68 | 69 | ////////////// Test Case 3 (Odd Parity) //////////////// 70 | 71 | // UART Configuration (Parity Enable = 1 && Parity Type = 1) 72 | UART_CONFG (1'b1,1'b1); 73 | 74 | // Load Data 75 | DATA_IN(8'hD2); 76 | 77 | // Check Output 78 | chk_tx_out(8'hD2,1,1,2) ; 79 | 80 | #100 81 | 82 | $stop ; 83 | 84 | end 85 | 86 | 87 | 88 | ///////////////////// Clock Generator ////////////////// 89 | 90 | always #(CLK_PERIOD/2) CLK_TB = ~CLK_TB ; 91 | 92 | //////////////////////////////////////////////////////// 93 | /////////////////////// TASKS ////////////////////////// 94 | //////////////////////////////////////////////////////// 95 | 96 | /////////////// Signals Initialization ////////////////// 97 | 98 | task initialize ; 99 | begin 100 | CLK_TB = 1'b0 ; 101 | RST_TB = 1'b1 ; // rst is deactivated 102 | P_DATA_TB = 8'h00 ; 103 | parity_enable_TB = 1'b0 ; 104 | parity_type_TB = 1'b0 ; 105 | Data_Valid_TB = 1'b0 ; 106 | end 107 | endtask 108 | 109 | ///////////////////////// RESET ///////////////////////// 110 | task reset ; 111 | begin 112 | #(CLK_PERIOD) 113 | RST_TB = 'b0; // rst is activated 114 | #(CLK_PERIOD) 115 | RST_TB = 'b1; 116 | #(CLK_PERIOD) ; 117 | end 118 | endtask 119 | 120 | ///////////////////// Configuration //////////////////// 121 | task UART_CONFG ; 122 | input PAR_EN ; 123 | input PAR_TYP ; 124 | 125 | begin 126 | parity_enable_TB = PAR_EN ; 127 | parity_type_TB = PAR_TYP ; 128 | end 129 | endtask 130 | 131 | /////////////////////// Data IN ///////////////////////// 132 | task DATA_IN ; 133 | input [DATA_WD_TB-1:0] DATA ; 134 | 135 | begin 136 | P_DATA_TB = DATA ; 137 | Data_Valid_TB = 1'b1 ; 138 | #CLK_PERIOD 139 | Data_Valid_TB = 1'b0 ; 140 | end 141 | endtask 142 | 143 | ////////////////// Check Output //////////////////// 144 | task chk_tx_out ; 145 | input [DATA_WD_TB-1:0] DATA ; 146 | input PAR_EN ; 147 | input PAR_TYP ; 148 | input [2:0] Test_NUM; 149 | 150 | reg [10:0] gener_out ,expec_out; //longest frame = 11 bits (1-start,1-stop,8-data,1-parity) 151 | reg parity_bit; 152 | 153 | integer i ; 154 | 155 | begin 156 | 157 | @(posedge busy_TB) 158 | for(i=0; i<11; i=i+1) 159 | begin 160 | @(negedge CLK_TB) gener_out[i] = TX_OUT_TB ; 161 | end 162 | 163 | if(parity_enable_TB) 164 | if(parity_type_TB) 165 | parity_bit = ~^DATA ; 166 | else 167 | parity_bit = ^DATA ; 168 | else 169 | parity_bit = 1'b1 ; 170 | 171 | if(parity_enable_TB) 172 | expec_out = {1'b1,parity_bit,DATA,1'b0} ; 173 | else 174 | expec_out = {1'b1,1'b1,DATA,1'b0} ; 175 | 176 | if(gener_out == expec_out) 177 | begin 178 | $display("Test Case %d is succeeded",Test_NUM); 179 | end 180 | else 181 | begin 182 | $display("Test Case %d is failed", Test_NUM); 183 | end 184 | end 185 | endtask 186 | ///////////////// Design Instaniation ////////////////// 187 | UART_TX DUT ( 188 | .CLK(CLK_TB), 189 | .RST(RST_TB), 190 | .P_DATA(P_DATA_TB), 191 | .Data_Valid(Data_Valid_TB), 192 | .parity_enable(parity_enable_TB), 193 | .parity_type(parity_type_TB), 194 | .TX_OUT(TX_OUT_TB), 195 | .busy(busy_TB) 196 | ); 197 | 198 | endmodule 199 | -------------------------------------------------------------------------------- /syn/cons/cons.tcl: -------------------------------------------------------------------------------- 1 | 2 | # Constraints 3 | # ---------------------------------------------------------------------------- 4 | # 5 | # 1. Master Clock Definitions 6 | # 7 | # 2. Clock Uncertainties 8 | # 9 | # 3. set input/output delay on ports 10 | # 11 | # 4. Driving cells 12 | # 13 | # 5. Output load 14 | 15 | 16 | #################################################################################### 17 | ######################################################### 18 | #### Section 1 : Clock Definition #### 19 | ######################################################### 20 | #################################################################################### 21 | # 1. Master Clock Definitions 22 | # 2. Clock Uncertainties 23 | # 3. Clock Transitions 24 | #################################################################################### 25 | 26 | #baud rate =115200 bits/sec = 112.5 KHz 27 | 28 | # UART_CLK_TX = 112.5 KHz 29 | set CLK1_NAME UART_CLK_TX 30 | set CLK1_PER 8680.5 31 | 32 | # UART_CLK_RX =115200 * 32= 3.515 MHz 33 | set CLK2_NAME UART_CLK_RX 34 | set CLK2_PER 271.316 35 | 36 | set CLK_SETUP_SKEW 0.25 37 | set CLK_HOLD_SKEW 0.1 38 | set CLK_TRA 0.1 39 | 40 | 41 | create_clock -name $CLK1_NAME -period $CLK1_PER -waveform "0 [expr $CLK1_PER/2]" [get_ports TX_CLK] 42 | set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK1_NAME] 43 | set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK1_NAME] 44 | 45 | create_clock -name $CLK2_NAME -period $CLK2_PER -waveform "0 [expr $CLK2_PER/2]" [get_ports RX_CLK] 46 | set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK2_NAME] 47 | set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK2_NAME] 48 | 49 | set_clock_transition -rise $CLK_TRA [get_clocks $CLK1_NAME] 50 | set_clock_transition -rise $CLK_TRA [get_clocks $CLK2_NAME] 51 | 52 | set_dont_touch_network {UART_CLK_TX UART_CLK_RX} 53 | 54 | # Don’t optimize logic crossing clock domains 55 | set_false_path -from [get_clocks $CLK1_NAME] -to [get_clocks $CLK2_NAME] 56 | set_false_path -from [get_clocks $CLK2_NAME] -to [get_clocks $CLK1_NAME] 57 | 58 | #################################################################################### 59 | ######################################################### 60 | #### Section 2 : set input/output delay on ports #### 61 | ######################################################### 62 | #################################################################################### 63 | 64 | set in_delay [expr 0.3*$CLK2_PER] 65 | set out_delay [expr 0.3*$CLK2_PER] 66 | 67 | #Constrain Input Paths 68 | set_input_delay $in_delay -clock $CLK2_NAME [remove_from_collection [all_inputs] [get_ports {TX_CLK RX_CLK RST}]] 69 | 70 | 71 | #Constrain Output Paths 72 | set_output_delay $out_delay -clock $CLK2_NAME [all_outputs] 73 | 74 | #################################################################################### 75 | ######################################################### 76 | #### Section 4 : Driving cells #### 77 | ######################################################### 78 | #################################################################################### 79 | 80 | set_driving_cell -no_design_rule -max -lib_cell NBUFFX4_RVT [remove_from_collection [all_inputs] [get_ports {TX_CLK RX_CLK}]] 81 | 82 | #################################################################################### 83 | ######################################################### 84 | #### Section 5 : Output load #### 85 | ######################################################### 86 | #################################################################################### 87 | 88 | set_load -max [expr {2 * [load_of saed32rvt_ss0p75v125c/NBUFFX4_RVT/A]}] [all_outputs] 89 | 90 | #################################################################################### 91 | ######################################################### 92 | #### Section 6 : min and max library #### 93 | ######################################################### 94 | #################################################################################### 95 | 96 | set_min_library saed32rvt_ss0p75v125c.db -min_version saed32rvt_ff1p16vn40c.db 97 | 98 | #################################################################################### 99 | ######################################################### 100 | #### Section 7 : wireload Model #### 101 | ######################################################### 102 | #################################################################################### 103 | 104 | set auto_wire_load_selection area_reselect 105 | set_wire_load_mode enclosed 106 | set_wire_load_selection_group predcaps 107 | 108 | 109 | -------------------------------------------------------------------------------- /syn/output/UART.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/syn/output/UART.svf -------------------------------------------------------------------------------- /syn/output/UART_mapped.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/basemhesham/Design-and-ASIC-Implementation-of-UART/57d912ff8d83a6ce8a4ded6503f8ada695e8e1d6/syn/output/UART_mapped.ddc -------------------------------------------------------------------------------- /syn/output/UART_mapped.sdc: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | 3 | # Created by write_sdc on Sat Apr 20 12:22:46 2024 4 | 5 | ################################################################### 6 | set sdc_version 2.1 7 | 8 | set_units -time ns -resistance MOhm -capacitance fF -voltage V -current uA 9 | set_wire_load_mode enclosed 10 | set_wire_load_selection_group predcaps 11 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports RST] 12 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports RX_IN_S] 13 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[7]}] 14 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[6]}] 15 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[5]}] 16 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[4]}] 17 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[3]}] 18 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[2]}] 19 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[1]}] 20 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[0]}] 21 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports TX_IN_V] 22 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[5]}] 23 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[4]}] 24 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[3]}] 25 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[2]}] 26 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[1]}] 27 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[0]}] 28 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports parity_enable] 29 | set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports parity_type] 30 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[7]}] 31 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[6]}] 32 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[5]}] 33 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[4]}] 34 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[3]}] 35 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[2]}] 36 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[1]}] 37 | set_load -pin_load 1.18475 [get_ports {RX_OUT_P[0]}] 38 | set_load -pin_load 1.18475 [get_ports RX_OUT_V] 39 | set_load -pin_load 1.18475 [get_ports TX_OUT_S] 40 | set_load -pin_load 1.18475 [get_ports TX_OUT_V] 41 | set_load -pin_load 1.18475 [get_ports parity_error] 42 | set_load -pin_load 1.18475 [get_ports framing_error] 43 | create_clock [get_ports TX_CLK] -name UART_CLK_TX -period 8680.5 -waveform {0 4340.25} 44 | set_clock_uncertainty -setup 0.25 [get_clocks UART_CLK_TX] 45 | set_clock_uncertainty -hold 0.1 [get_clocks UART_CLK_TX] 46 | set_clock_transition -max -rise 0.1 [get_clocks UART_CLK_TX] 47 | set_clock_transition -min -rise 0.1 [get_clocks UART_CLK_TX] 48 | create_clock [get_ports RX_CLK] -name UART_CLK_RX -period 271.316 -waveform {0 135.658} 49 | set_clock_uncertainty -setup 0.25 [get_clocks UART_CLK_RX] 50 | set_clock_uncertainty -hold 0.1 [get_clocks UART_CLK_RX] 51 | set_clock_transition -max -rise 0.1 [get_clocks UART_CLK_RX] 52 | set_clock_transition -min -rise 0.1 [get_clocks UART_CLK_RX] 53 | group_path -name INOUT -from [list [get_ports RST] [get_ports TX_CLK] [get_ports RX_CLK] [get_ports RX_IN_S] [get_ports {TX_IN_P[7]}] [get_ports {TX_IN_P[6]}] [get_ports {TX_IN_P[5]}] [get_ports {TX_IN_P[4]}] [get_ports {TX_IN_P[3]}] [get_ports {TX_IN_P[2]}] [get_ports {TX_IN_P[1]}] [get_ports {TX_IN_P[0]}] [get_ports TX_IN_V] [get_ports {Prescale[5]}] [get_ports {Prescale[4]}] [get_ports {Prescale[3]}] [get_ports {Prescale[2]}] [get_ports {Prescale[1]}] [get_ports {Prescale[0]}] [get_ports parity_enable] [get_ports parity_type]] -to [list [get_ports {RX_OUT_P[7]}] [get_ports {RX_OUT_P[6]}] [get_ports {RX_OUT_P[5]}] [get_ports {RX_OUT_P[4]}] [get_ports {RX_OUT_P[3]}] [get_ports {RX_OUT_P[2]}] [get_ports {RX_OUT_P[1]}] [get_ports {RX_OUT_P[0]}] [get_ports RX_OUT_V] [get_ports TX_OUT_S] [get_ports TX_OUT_V] [get_ports parity_error] [get_ports framing_error]] 54 | group_path -name INREG -from [list [get_ports RST] [get_ports TX_CLK] [get_ports RX_CLK] [get_ports RX_IN_S] [get_ports {TX_IN_P[7]}] [get_ports {TX_IN_P[6]}] [get_ports {TX_IN_P[5]}] [get_ports {TX_IN_P[4]}] [get_ports {TX_IN_P[3]}] [get_ports {TX_IN_P[2]}] [get_ports {TX_IN_P[1]}] [get_ports {TX_IN_P[0]}] [get_ports TX_IN_V] [get_ports {Prescale[5]}] [get_ports {Prescale[4]}] [get_ports {Prescale[3]}] [get_ports {Prescale[2]}] [get_ports {Prescale[1]}] [get_ports {Prescale[0]}] [get_ports parity_enable] [get_ports parity_type]] 55 | group_path -name REGOUT -to [list [get_ports {RX_OUT_P[7]}] [get_ports {RX_OUT_P[6]}] [get_ports {RX_OUT_P[5]}] [get_ports {RX_OUT_P[4]}] [get_ports {RX_OUT_P[3]}] [get_ports {RX_OUT_P[2]}] [get_ports {RX_OUT_P[1]}] [get_ports {RX_OUT_P[0]}] [get_ports RX_OUT_V] [get_ports TX_OUT_S] [get_ports TX_OUT_V] [get_ports parity_error] [get_ports framing_error]] 56 | set_false_path -from [get_clocks UART_CLK_TX] -to [get_clocks UART_CLK_RX] 57 | set_false_path -from [get_clocks UART_CLK_RX] -to [get_clocks UART_CLK_TX] 58 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports RX_IN_S] 59 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[7]}] 60 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[6]}] 61 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[5]}] 62 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[4]}] 63 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[3]}] 64 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[2]}] 65 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[1]}] 66 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[0]}] 67 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports TX_IN_V] 68 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[5]}] 69 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[4]}] 70 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[3]}] 71 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[2]}] 72 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[1]}] 73 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[0]}] 74 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports parity_enable] 75 | set_input_delay -clock UART_CLK_RX 81.3948 [get_ports parity_type] 76 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[7]}] 77 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[6]}] 78 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[5]}] 79 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[4]}] 80 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[3]}] 81 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[2]}] 82 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[1]}] 83 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[0]}] 84 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports RX_OUT_V] 85 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports TX_OUT_S] 86 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports TX_OUT_V] 87 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports parity_error] 88 | set_output_delay -clock UART_CLK_RX 81.3948 [get_ports framing_error] 89 | -------------------------------------------------------------------------------- /syn/reports/area.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : area 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Sat Apr 20 12:22:46 2024 7 | **************************************** 8 | 9 | Library(s) Used: 10 | 11 | saed32rvt_ss0p75v125c (File: /home/ICer/Projects/UART/ref/std_cells/saed32rvt_ss0p75v125c.db) 12 | 13 | Number of ports: 233 14 | Number of nets: 552 15 | Number of cells: 333 16 | Number of combinational cells: 264 17 | Number of sequential cells: 56 18 | Number of macros/black boxes: 0 19 | Number of buf/inv: 52 20 | Number of references: 3 21 | 22 | Combinational area: 608.420738 23 | Buf/Inv area: 66.077440 24 | Noncombinational area: 377.149703 25 | Macro/Black Box area: 0.000000 26 | Net Interconnect area: 181.195949 27 | 28 | Total cell area: 985.570441 29 | Total area: 1166.766390 30 | 31 | Hierarchical area distribution 32 | ------------------------------ 33 | 34 | Global cell area Local cell area 35 | ------------------ --------------------------- 36 | Hierarchical cell Absolute Percent Combi- Noncombi- Black- 37 | Total Total national national boxes Design 38 | -------------------------------- --------- ------- -------- --------- ------ ------------------------ 39 | UART 985.5704 100.0 1.2707 0.0000 0.0000 UART 40 | U0_UART_RX 674.4982 68.4 0.0000 0.0000 0.0000 UART_RX 41 | U0_UART_RX/U0_data_sampling 129.8676 13.2 101.4035 28.4641 0.0000 data_sampling 42 | U0_UART_RX/U0_deserializer 133.1715 13.5 76.2432 56.9283 0.0000 deserializer_DATA_WIDTH8 43 | U0_UART_RX/U0_edge_bit_counter 170.7848 17.3 99.6244 71.1603 0.0000 edge_bit_counter 44 | U0_UART_RX/U0_par_chk 33.5470 3.4 26.4310 7.1160 0.0000 par_chk_DATA_WIDTH8 45 | U0_UART_RX/U0_stp_chk 12.1989 1.2 5.0829 7.1160 0.0000 stp_chk 46 | U0_UART_RX/U0_strt_chk 10.9282 1.1 3.8122 7.1160 0.0000 strt_chk 47 | U0_UART_RX/U0_uart_fsm 184.0003 18.7 162.6522 21.3481 0.0000 uart_rx_fsm_DATA_WIDTH8 48 | U0_UART_TX 309.8015 31.4 0.0000 0.0000 0.0000 UART_TX_DATA_WIDTH8 49 | U0_UART_TX/U0_Serializer 127.3261 12.9 49.0498 78.2764 0.0000 Serializer_WIDTH8 50 | U0_UART_TX/U0_fsm 61.7570 6.3 33.2929 28.4641 0.0000 uart_tx_fsm 51 | U0_UART_TX/U0_mux 10.4199 1.1 3.3039 7.1160 0.0000 mux 52 | U0_UART_TX/U0_parity_calc 110.2985 11.2 46.2542 64.0443 0.0000 parity_calc_WIDTH8 53 | -------------------------------- --------- ------- -------- --------- ------ ------------------------ 54 | Total 608.4207 377.1497 0.0000 55 | 56 | 1 57 | -------------------------------------------------------------------------------- /syn/reports/constraints.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : constraint 4 | -all_violators 5 | Design : UART 6 | Version: O-2018.06-SP1 7 | Date : Sat Apr 20 12:22:46 2024 8 | **************************************** 9 | 10 | 11 | min_delay/hold ('UART_CLK_RX' group) 12 | 13 | Required Actual 14 | Endpoint Path Delay Path Delay Slack 15 | ----------------------------------------------------------------- 16 | U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/D 17 | 0.10 0.09 f -0.01 (VIOLATED) 18 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/D 19 | 0.10 0.09 f -0.01 (VIOLATED) 20 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/D 21 | 0.10 0.09 f -0.01 (VIOLATED) 22 | U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/D 23 | 0.10 0.09 f -0.01 (VIOLATED) 24 | 25 | 26 | min_delay/hold ('UART_CLK_TX' group) 27 | 28 | Required Actual 29 | Endpoint Path Delay Path Delay Slack 30 | ----------------------------------------------------------------- 31 | U0_UART_TX/U0_Serializer/ser_count_reg_0_/D 32 | 0.10 0.08 f -0.02 (VIOLATED) 33 | 34 | 35 | 1 36 | -------------------------------------------------------------------------------- /syn/reports/power.rpt: -------------------------------------------------------------------------------- 1 | Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) 2 | Warning: Design has unannotated primary inputs. (PWR-414) 3 | Warning: Design has unannotated sequential cell outputs. (PWR-415) 4 | 5 | **************************************** 6 | Report : power 7 | -hier 8 | -analysis_effort low 9 | Design : UART 10 | Version: O-2018.06-SP1 11 | Date : Sat Apr 20 12:22:46 2024 12 | **************************************** 13 | 14 | 15 | Library(s) Used: 16 | 17 | saed32rvt_ss0p75v125c (File: /home/ICer/Projects/UART/ref/std_cells/saed32rvt_ss0p75v125c.db) 18 | 19 | 20 | Operating Conditions: ss0p75v125c Library: saed32rvt_ss0p75v125c 21 | Wire Load Model Mode: enclosed 22 | 23 | Design Wire Load Model Library 24 | ------------------------------------------------ 25 | UART 8000 saed32rvt_ss0p75v125c 26 | UART_TX_DATA_WIDTH8 8000 saed32rvt_ss0p75v125c 27 | UART_RX 8000 saed32rvt_ss0p75v125c 28 | uart_tx_fsm ForQA saed32rvt_ss0p75v125c 29 | Serializer_WIDTH8 ForQA saed32rvt_ss0p75v125c 30 | mux ForQA saed32rvt_ss0p75v125c 31 | parity_calc_WIDTH8 ForQA saed32rvt_ss0p75v125c 32 | uart_rx_fsm_DATA_WIDTH8 33 | ForQA saed32rvt_ss0p75v125c 34 | edge_bit_counter ForQA saed32rvt_ss0p75v125c 35 | data_sampling ForQA saed32rvt_ss0p75v125c 36 | deserializer_DATA_WIDTH8 37 | ForQA saed32rvt_ss0p75v125c 38 | strt_chk ForQA saed32rvt_ss0p75v125c 39 | par_chk_DATA_WIDTH8 ForQA saed32rvt_ss0p75v125c 40 | stp_chk ForQA saed32rvt_ss0p75v125c 41 | 42 | 43 | Global Operating Voltage = 0.75 44 | Power-specific unit information : 45 | Voltage Units = 1V 46 | Capacitance Units = 1.000000ff 47 | Time Units = 1ns 48 | Dynamic Power Units = 1uW (derived from V,C,T units) 49 | Leakage Power Units = 1pW 50 | 51 | 52 | -------------------------------------------------------------------------------- 53 | Switch Int Leak Total 54 | Hierarchy Power Power Power Power % 55 | -------------------------------------------------------------------------------- 56 | UART 3.90e-02 0.518 1.62e+07 16.752 100.0 57 | U0_UART_RX (UART_RX) 3.29e-02 0.462 1.06e+07 11.058 66.0 58 | U0_stp_chk (stp_chk) 5.25e-06 1.38e-02 2.14e+05 0.228 1.4 59 | U0_par_chk (par_chk_DATA_WIDTH8) 8.21e-05 1.43e-02 5.68e+05 0.582 3.5 60 | U0_strt_chk (strt_chk) 7.61e-05 1.40e-02 1.95e+05 0.209 1.2 61 | U0_deserializer (deserializer_DATA_WIDTH8) 62 | 3.45e-03 0.117 2.20e+06 2.318 13.8 63 | U0_data_sampling (data_sampling) 8.22e-03 7.36e-02 2.19e+06 2.274 13.6 64 | U0_edge_bit_counter (edge_bit_counter) 65 | 1.14e-02 0.172 2.96e+06 3.139 18.7 66 | U0_uart_fsm (uart_rx_fsm_DATA_WIDTH8) 67 | 9.59e-03 5.71e-02 2.24e+06 2.308 13.8 68 | U0_UART_TX (UART_TX_DATA_WIDTH8) 6.19e-03 5.62e-02 5.62e+06 5.684 33.9 69 | U0_parity_calc (parity_calc_WIDTH8) 70 | 3.23e-03 2.27e-02 2.11e+06 2.138 12.8 71 | U0_mux (mux) 4.76e-05 1.90e-03 2.15e+05 0.217 1.3 72 | U0_Serializer (Serializer_WIDTH8) 2.50e-03 2.38e-02 2.26e+06 2.288 13.7 73 | U0_fsm (uart_tx_fsm) 4.10e-04 7.78e-03 1.03e+06 1.041 6.2 74 | 1 75 | -------------------------------------------------------------------------------- /syn/reports/qor.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : qor 4 | Design : UART 5 | Version: O-2018.06-SP1 6 | Date : Sat Apr 20 12:22:46 2024 7 | **************************************** 8 | 9 | 10 | Timing Path Group 'INREG' 11 | ----------------------------------- 12 | Levels of Logic: 13.00 13 | Critical Path Length: 1.88 14 | Critical Path Slack: 187.69 15 | Critical Path Clk Period: 271.32 16 | Total Negative Slack: 0.00 17 | No. of Violating Paths: 0.00 18 | Worst Hold Violation: 0.00 19 | Total Hold Violation: 0.00 20 | No. of Hold Violations: 0.00 21 | ----------------------------------- 22 | 23 | Timing Path Group 'REGOUT' 24 | ----------------------------------- 25 | Levels of Logic: 2.00 26 | Critical Path Length: 0.77 27 | Critical Path Slack: 188.90 28 | Critical Path Clk Period: 271.32 29 | Total Negative Slack: 0.00 30 | No. of Violating Paths: 0.00 31 | Worst Hold Violation: 0.00 32 | Total Hold Violation: 0.00 33 | No. of Hold Violations: 0.00 34 | ----------------------------------- 35 | 36 | Timing Path Group 'UART_CLK_RX' 37 | ----------------------------------- 38 | Levels of Logic: 7.00 39 | Critical Path Length: 2.18 40 | Critical Path Slack: 268.78 41 | Critical Path Clk Period: 271.32 42 | Total Negative Slack: 0.00 43 | No. of Violating Paths: 0.00 44 | Worst Hold Violation: -0.01 45 | Total Hold Violation: -0.04 46 | No. of Hold Violations: 4.00 47 | ----------------------------------- 48 | 49 | Timing Path Group 'UART_CLK_TX' 50 | ----------------------------------- 51 | Levels of Logic: 5.00 52 | Critical Path Length: 1.76 53 | Critical Path Slack: 8678.37 54 | Critical Path Clk Period: 8680.50 55 | Total Negative Slack: 0.00 56 | No. of Violating Paths: 0.00 57 | Worst Hold Violation: -0.02 58 | Total Hold Violation: -0.02 59 | No. of Hold Violations: 1.00 60 | ----------------------------------- 61 | 62 | 63 | Cell Count 64 | ----------------------------------- 65 | Hierarchical Cell Count: 13 66 | Hierarchical Port Count: 199 67 | Leaf Cell Count: 317 68 | Buf/Inv Cell Count: 52 69 | Buf Cell Count: 0 70 | Inv Cell Count: 52 71 | CT Buf/Inv Cell Count: 0 72 | Combinational Cell Count: 264 73 | Sequential Cell Count: 53 74 | Macro Count: 0 75 | ----------------------------------- 76 | 77 | 78 | Area 79 | ----------------------------------- 80 | Combinational Area: 608.420738 81 | Noncombinational Area: 377.149703 82 | Buf/Inv Area: 66.077440 83 | Total Buffer Area: 0.00 84 | Total Inverter Area: 66.08 85 | Macro/Black Box Area: 0.000000 86 | Net Area: 181.195949 87 | ----------------------------------- 88 | Cell Area: 985.570441 89 | Design Area: 1166.766390 90 | 91 | 92 | Design Rules 93 | ----------------------------------- 94 | Total Number of Nets: 356 95 | Nets With Violations: 0 96 | Max Trans Violations: 0 97 | Max Cap Violations: 0 98 | ----------------------------------- 99 | 100 | 101 | Hostname: IC_EDA 102 | 103 | Compile CPU Statistics 104 | ----------------------------------------- 105 | Resource Sharing: 0.80 106 | Logic Optimization: 0.19 107 | Mapping Optimization: 1.16 108 | ----------------------------------------- 109 | Overall Compile Time: 20.76 110 | Overall Compile Wall Clock Time: 31.52 111 | 112 | -------------------------------------------------------------------- 113 | 114 | Design WNS: 0.00 TNS: 0.00 Number of Violating Paths: 0 115 | 116 | 117 | Design (Hold) WNS: 0.02 TNS: 0.06 Number of Violating Paths: 5 118 | 119 | -------------------------------------------------------------------- 120 | 121 | 122 | 1 123 | -------------------------------------------------------------------------------- /syn/script/syn_script.tcl: -------------------------------------------------------------------------------- 1 | 2 | ########################### Define Top Module ############################ 3 | 4 | set top_module UART 5 | 6 | ########################### Define SVF File ############################ 7 | set_svf $top_module.svf 8 | 9 | ##################### Define Working Library Directory ###################### 10 | 11 | define_design_lib work -path ./work 12 | 13 | ################## Design Compiler Library Files #setup ###################### 14 | 15 | puts "###########################################" 16 | puts "# #setting Design Libraries #" 17 | puts "###########################################" 18 | 19 | #Add the path of the libraries to the search_path variable 20 | lappend search_path /home/ICer/Projects/UART/ref/std_cells 21 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TX 22 | lappend search_path /home/ICer/Projects/UART/rtl/UART_RX 23 | lappend search_path /home/ICer/Projects/UART/rtl/UART_TOP 24 | 25 | set SSLIB "saed32rvt_ss0p75v125c.db" 26 | 27 | ## Standard Cell libraries 28 | set target_library [list $SSLIB] 29 | 30 | ## Standard Cell & Hard Macros libraries 31 | set link_library [list * $SSLIB] 32 | 33 | ######################## Reading RTL Files ################################# 34 | 35 | puts "###########################################" 36 | puts "# Reading RTL Files #" 37 | puts "###########################################" 38 | 39 | set file_format verilog 40 | 41 | analyze -format $file_format { mux.v \ 42 | parity_calc.v \ 43 | Serializer.v \ 44 | uart_tx_fsm.v \ 45 | UART_TX.v \ 46 | data_sampling.v \ 47 | deserializer.v \ 48 | edge_bit_counter.v \ 49 | par_chk.v \ 50 | stp_chk.v \ 51 | strt_chk.v \ 52 | uart_rx_fsm.v \ 53 | UART_RX.v \ 54 | UART.v } 55 | 56 | elaborate -lib work UART 57 | 58 | ###################### Defining toplevel ################################### 59 | 60 | current_design $top_module 61 | 62 | #################### Liniking All The Design Parts ######################### 63 | puts "###############################################" 64 | puts "######## Liniking All The Design Parts ########" 65 | puts "###############################################" 66 | 67 | link 68 | 69 | #################### Liniking All The Design Parts ######################### 70 | puts "###############################################" 71 | puts "######## checking design consistency ##########" 72 | puts "###############################################" 73 | 74 | check_design 75 | 76 | ############################### Path groups ################################ 77 | puts "###############################################" 78 | puts "################ Path groups ##################" 79 | puts "###############################################" 80 | 81 | group_path -name INREG -from [all_inputs] 82 | group_path -name REGOUT -to [all_outputs] 83 | group_path -name INOUT -from [all_inputs] -to [all_outputs] 84 | 85 | #################### Define Design Constraints ######################### 86 | puts "###############################################" 87 | puts "############ Design Constraints #### ##########" 88 | puts "###############################################" 89 | 90 | source -echo ./cons.tcl 91 | 92 | ###################### Mapping and optimization ######################## 93 | puts "###############################################" 94 | puts "######## Preventing Multiple Port Nets ########" 95 | puts "###############################################" 96 | 97 | set case_analysis_with_logic_constants true 98 | 99 | set_fix_multiple_port_nets -all 100 | 101 | puts "###############################################" 102 | puts "########## Mapping & Optimization #############" 103 | puts "###############################################" 104 | 105 | compile_ultra -no_autoungroup 106 | 107 | set_svf -off 108 | 109 | ############################################################################# 110 | # Write out Design after initial compile 111 | ############################################################################# 112 | 113 | puts "###############################################" 114 | puts "########## Remove Special Characters ##########" 115 | puts "###############################################" 116 | 117 | set verilogout_equation false 118 | 119 | change_names -rule verilog -hierarchy 120 | 121 | write_file -format verilog -hierarchy -output UART_mapped.v 122 | write_file -format ddc -hierarchy -output UART_mapped.ddc 123 | write_sdc -nosplit UART_mapped.sdc 124 | write_sdf UART_mapped.sdf 125 | 126 | ################# reporting ####################### 127 | 128 | report_area -hierarchy > reports/area.rpt 129 | report_power -hierarchy > reports/power.rpt 130 | report_timing -max_paths 100 -delay_type min > reports/hold.rpt 131 | report_timing -max_paths 100 -delay_type max > reports/setup.rpt 132 | report_constraint -all_violators > reports/constraints.rpt 133 | report_qor > reports/qor.rpt 134 | 135 | ################# starting graphical user interface ####################### 136 | 137 | gui_start 138 | 139 | --------------------------------------------------------------------------------