├── README.md ├── dft ├── cons │ └── cons.tcl ├── output │ ├── UART.def │ ├── UART.svf │ ├── UART_mapped.ddc │ ├── UART_mapped.sdc │ ├── UART_mapped.sdf │ └── UART_mapped.v ├── reports │ ├── area.rpt │ ├── constraints.rpt │ ├── hold.rpt │ ├── power.rpt │ ├── qor.rpt │ └── setup.rpt └── script │ └── dft_script.tcl ├── fm ├── post_DFT │ ├── fm_reports │ │ ├── aborted_points.rpt │ │ ├── failing_points.rpt │ │ ├── passing_points.rpt │ │ └── unverified_points.rpt │ ├── fm_script.tcl │ └── formality_svf │ │ └── svf.txt └── post_synthesis │ ├── fm_reports │ ├── aborted_points.rpt │ ├── failing_points.rpt │ ├── passing_points.rpt │ └── unverified_points.rpt │ ├── fm_script.tcl │ └── formality_svf │ ├── d1 │ └── netlists │ │ └── S1 │ │ └── J1 │ │ └── dw-1 │ │ ├── data_sampling_DP_OP_13J1_124_7424_J1_0.b │ │ ├── deserializer_DATA_WIDTH8_DP_OP_3J1_126_2816_J1_0.b │ │ ├── edge_bit_counter_DP_OP_10J1_125_9618_J1_0.b │ │ ├── uart_rx_fsm_DATA_WIDTH8_DP_OP_29J1_122_2437_J1_0.b │ │ └── uart_rx_fsm_DATA_WIDTH8_DP_OP_30J1_123_2437_J1_0.b │ └── svf.txt ├── pnr ├── output │ ├── UART.def │ ├── UART.gds │ ├── UART.lef │ ├── UART.lvs.v │ ├── UART.tlef │ └── UART.v ├── pnr.tcl ├── reports │ ├── CTS │ │ ├── check_legality.rpt │ │ ├── latency.rpt │ │ ├── local_skew.rpt │ │ ├── report_clock_qor.rpt │ │ ├── report_constraints_max_capacitance.rpt │ │ ├── report_constraints_max_transition.rpt │ │ └── report_qor.rpt │ ├── Placement │ │ ├── check_legality.rpt │ │ ├── report_congestion.rpt │ │ ├── report_qor.summary.rpt │ │ ├── report_timing.data.rpt │ │ ├── report_timing.full.rpt │ │ └── report_utilization.rpt │ ├── Powerplanning │ │ ├── check_pg_connectivity.rpt │ │ ├── check_pg_drc.rpt │ │ ├── check_pg_missing_vias.rpt │ │ ├── report_qor.summary.rpt │ │ └── report_timing.rpt │ └── Routing │ │ ├── check_legality.rpt │ │ ├── check_lvs.rpt │ │ ├── check_routes.rpt │ │ ├── report_constraints_max_capacitance.rpt │ │ ├── report_constraints_max_transition.rpt │ │ ├── report_qor.rpt │ │ └── report_timing.rpt └── scripts │ ├── ndr.tcl │ └── power_network.tcl ├── rtl ├── UART_RX │ ├── UART_RX.v │ ├── data_sampling.v │ ├── deserializer.v │ ├── edge_bit_counter.v │ ├── par_chk.v │ ├── stp_chk.v │ ├── strt_chk.v │ └── uart_rx_fsm.v ├── UART_TOP │ └── UART.v ├── UART_TOP_DFT │ ├── UART.v │ └── mux2X1.v └── UART_TX │ ├── Serializer.v │ ├── UART_TX.v │ ├── mux.v │ ├── mux.v~ │ ├── parity_calc.v │ └── uart_tx_fsm.v ├── sim ├── UART_RX │ ├── Test_cases │ │ ├── Test1.png │ │ ├── Test2.png │ │ ├── Test3.png │ │ ├── Test4.png │ │ ├── Test5.png │ │ ├── Test6.png │ │ ├── Test7.png │ │ ├── Test8.png │ │ └── Test9.png │ └── UART_RX_TB.v └── UART_TX │ ├── Test_cases │ ├── Test1.png │ ├── Test2.png │ └── Test3.png │ └── UART_TX_TB.v └── syn ├── cons └── cons.tcl ├── output ├── UART.svf ├── UART_mapped.ddc ├── UART_mapped.sdc ├── UART_mapped.sdf └── UART_mapped.v ├── reports ├── area.rpt ├── constraints.rpt ├── hold.rpt ├── power.rpt ├── qor.rpt └── setup.rpt └── script └── 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