├── LICENSE ├── README.md └── arch └── arm └── boot └── dts ├── BB-ADC-00A0.dts ├── BB-BONE-AUDI-01-00A0.dts ├── BB-BONE-AUDI-02-00A0.dts ├── BB-BONE-BACON-00A0.dts ├── BB-BONE-BACONE-00A0.dts ├── BB-BONE-BACONE2-00A0.dts ├── BB-BONE-CAM-VVDN-00A0.dts ├── BB-BONE-CAM3-01-00A2.dts ├── BB-BONE-CRYPTO-00A0.dts ├── BB-BONE-GPEVT-00A0.dts ├── BB-BONE-GPS-00A0.dts ├── BB-BONE-HAS-00R1.dts ├── BB-BONE-LCD4-01-00A0.dts ├── BB-BONE-LCD4-01-00A1.dts ├── BB-BONE-LCD7-01-00A2.dts ├── BB-BONE-LCD7-01-00A3.dts ├── BB-BONE-LCD7-01-00A4.dts ├── BB-BONE-LOGIBONE-00R1.dts ├── BB-BONE-PRU-01-00A0.dts ├── BB-BONE-PRU-02-00A0.dts ├── BB-BONE-PRU-03-00A0.dts ├── BB-BONE-PRU-04-00A0.dts ├── BB-BONE-PWMT-00A0.dts ├── BB-BONE-REPLICAP-00A1.dts ├── BB-BONE-REPLICAP-00A2.dts ├── BB-BONE-REPLICAP-00A3.dts ├── BB-BONE-REPLICAP-00A4.dts ├── BB-BONE-REPLICAP-0A4A.dts ├── BB-BONE-RS232-00A0.dts ├── BB-BONE-RST-00A0.dts ├── BB-BONE-RST2-00A0.dts ├── BB-BONE-RTC-00A0.dts ├── BB-BONE-SERL-01-00A1.dts ├── BB-BONE-SERL-03-00A1.dts ├── BB-BONE-eMMC1-01-00A0.dts ├── BB-BONELT-BT-00A0.dts ├── BB-GPIOHELP-00A0.dts ├── BB-I2C1-00A0.dts ├── BB-I2C1A1-00A0.dts ├── BB-SPIDEV0-00A0.dts ├── BB-SPIDEV1-00A0.dts ├── BB-SPIDEV1A1-00A0.dts ├── BB-UART1-00A0.dts ├── BB-UART2-00A0.dts ├── BB-UART2-RTSCTS-00A0.dts ├── BB-UART4-00A0.dts ├── BB-UART4-RTSCTS-00A0.dts ├── BB-UART5-00A0.dts ├── BB-VIEW-LCD4-01-00A0.dts ├── BB-VIEW-LCD7-01-00A0.dts ├── CBB-Relay-00A0.dts ├── DNIL-AMPCAPE-1-00R1.dts ├── Makefile ├── TT3201-001-01.dts ├── am335x-base0033.dts ├── am335x-bone-common.dtsi ├── am335x-bone.dts ├── am335x-boneblack.dts ├── am335x-evmsk.dts ├── am335x-nano.dts ├── am33xx-clocks.dtsi ├── am33xx.dtsi ├── am33xx_pwm-00A0.dts ├── am35xx-clocks.dtsi ├── bone_eqep0-00A0.dts ├── bone_eqep1-00A0.dts ├── bone_eqep2-00A0.dts ├── bone_pwm_P8_13-00A0.dts ├── bone_pwm_P8_19-00A0.dts ├── bone_pwm_P8_34-00A0.dts ├── bone_pwm_P8_36-00A0.dts ├── bone_pwm_P8_45-00A0.dts ├── bone_pwm_P8_46-00A0.dts ├── bone_pwm_P9_14-00A0.dts ├── bone_pwm_P9_16-00A0.dts ├── bone_pwm_P9_21-00A0.dts ├── bone_pwm_P9_22-00A0.dts ├── bone_pwm_P9_28-00A0.dts ├── bone_pwm_P9_29-00A0.dts ├── bone_pwm_P9_31-00A0.dts ├── bone_pwm_P9_42-00A0.dts ├── cape-CBB-Serial-r01.dts ├── cape-bebopr-R2.dts ├── cape-bebopr-brdg-R2.dts ├── cape-bebopr-ena-R2.dts ├── cape-bone-2g-emmc1.dts ├── cape-bone-adafruit-lcd-00A0.dts ├── cape-bone-argus-00A0.dts ├── cape-bone-dvi-00A0.dts ├── cape-bone-dvi-00A1.dts ├── cape-bone-dvi-00A2.dts ├── cape-bone-exptest-00A0.dts ├── cape-bone-geiger-00A0.dts ├── cape-bone-hexy-00A0.dts ├── cape-bone-ibb-00A0.dts ├── cape-bone-iio-00A0.dts ├── cape-bone-lcd3-00A0.dts ├── cape-bone-lcd3-00A2.dts ├── cape-bone-mrf24j40-00A0.dts ├── cape-bone-nixie-00A0.dts ├── cape-bone-pinmux-test-00A0.dts ├── cape-bone-proto-00A0.dts ├── cape-bone-tester-00A0.dts ├── cape-bone-weather-00A0.dts ├── cape-bone-weather-00B0.dts ├── cape-boneblack-hdmi-00A0.dts ├── cape-boneblack-hdmin-00A0.dts ├── cape-univ-emmc-00A0.dts ├── cape-universal-00A0.dts ├── cape-universaln-00A0.dts ├── include └── dt-bindings ├── omap-gpmc-smsc911x.dtsi ├── omap-gpmc-smsc9221.dtsi ├── omap3-beagle-xm-ab.dts ├── omap3-beagle-xm.dts ├── omap3-beagle.dts ├── omap3.dtsi ├── omap3430es1-clocks.dtsi ├── omap34xx-hs.dtsi ├── omap34xx-omap36xx-clocks.dtsi ├── omap34xx.dtsi ├── omap36xx-am35xx-omap3430es2plus-clocks.dtsi ├── omap36xx-clocks.dtsi ├── omap36xx-hs.dtsi ├── omap36xx-omap3430es2plus-clocks.dtsi ├── omap36xx.dtsi ├── omap3xxx-clocks.dtsi ├── skeleton.dtsi ├── tps6507x.dtsi ├── tps65217.dtsi ├── tps65910.dtsi ├── twl4030.dtsi ├── twl4030_omap3.dtsi ├── twl6030.dtsi └── twl6030_omap4.dtsi /README.md: -------------------------------------------------------------------------------- 1 | This tree is now deprecated 2 | =========================== 3 | 4 | Please see https://github.com/beagleboard/linux for the latest sources. 5 | 6 | 7 | 8 | devicetree-source 9 | ================= 10 | 11 | The soon-to-be definitive source for all the devicetree bits for all of the BeagleBoard.org boards and capes. 12 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-ADC-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-ADC"; 16 | 17 | /* state the resources this cape uses */ 18 | exclusive-use = 19 | /* the pin header uses */ 20 | "P9.39", /* AIN0 */ 21 | "P9.40", /* AIN1 */ 22 | "P9.37", /* AIN2 */ 23 | "P9.38", /* AIN3 */ 24 | "P9.33", /* AIN4 */ 25 | "P9.36", /* AIN5 */ 26 | "P9.35", /* AIN6 */ 27 | /* the hardware IP uses */ 28 | "tscadc"; 29 | 30 | fragment@0 { 31 | target = <&ocp>; 32 | __overlay__ { 33 | /* avoid stupid warning */ 34 | #address-cells = <1>; 35 | #size-cells = <1>; 36 | 37 | tscadc { 38 | compatible = "ti,ti-tscadc"; 39 | reg = <0x44e0d000 0x1000>; 40 | 41 | interrupt-parent = <&intc>; 42 | interrupts = <16>; 43 | ti,hwmods = "adc_tsc"; 44 | status = "okay"; 45 | 46 | adc { 47 | ti,adc-channels = <0 1 2 3 4 5 6 7>; 48 | }; 49 | }; 50 | 51 | test_helper: helper { 52 | compatible = "bone-iio-helper"; 53 | vsense-name = "AIN0", "AIN1", "AIN2", "AIN3", "AIN4", "AIN5", "AIN6", "AIN7"; 54 | vsense-scale = <100 100 100 100 100 100 100 100>; 55 | status = "okay"; 56 | }; 57 | }; 58 | }; 59 | }; 60 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-AUDI-01-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-AUDI-01"; 16 | version = "00A0", "A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.14", /* leds: gpio1_18 */ 22 | "P9.16", /* leds: gpio1_19 */ 23 | "P9.31", /* mcasp0: mcasp0_aclkx */ 24 | "P9.29", /* mcasp0: mcasp0_fsx */ 25 | "P9.28", /* mcasp0: mcasp0_axr2 */ 26 | "P9.25", /* mcasp0: mcasp0_ahclkx */ 27 | /* the hardware ip uses */ 28 | "gpio1_18", "gpio1_19", 29 | "mcasp0"; 30 | 31 | fragment@0 { 32 | target = <&am33xx_pinmux>; 33 | __overlay__ { 34 | 35 | bone_audio_cape_led_pins: pinmux_bone_audio_cape_led_pins { 36 | pinctrl-single,pins = < 37 | 0x48 0x07 /* gpmc_a2.gpio1_18, OUTPUT | MODE7 */ 38 | 0x4c 0x07 /* gpmc_a3.gpio1_19, OUTPUT | MODE7 */ 39 | >; 40 | }; 41 | 42 | bone_audio_cape_audio_pins: pinmux_bone_audio_cape_audio_pins { 43 | pinctrl-single,pins = < 44 | 0x190 0x20 /* mcasp0_aclkx.mcasp0_aclkx, INPUT | MODE0 */ 45 | 0x194 0x20 /* mcasp0_fsx.mcasp0_fsx, INPUT | MODE0 */ 46 | 0x19c 0x22 /* mcasp0_ahclkr.mcasp0_axr2, INPUT | MODE2 */ 47 | 0x1ac 0x22 /* mcasp0_ahclkx.mcasp0_axr3, INPUT | MODE2 */ 48 | 49 | >; 50 | }; 51 | }; 52 | }; 53 | 54 | fragment@1 { 55 | target = <&ocp>; 56 | __overlay__ { 57 | 58 | /* avoid stupid warning */ 59 | #address-cells = <1>; 60 | #size-cells = <1>; 61 | 62 | gpio-leds-cape-audio { 63 | compatible = "gpio-leds"; 64 | pinctrl-names = "default"; 65 | pinctrl-0 = <&bone_audio_cape_led_pins>; 66 | 67 | audio-led0 { 68 | label = "audio:green:usr0"; 69 | gpios = <&gpio2 18 0>; 70 | linux,default-trigger = "heartbeat"; 71 | default-state = "off"; 72 | }; 73 | 74 | audio-led1 { 75 | label = "audio:green:usr1"; 76 | gpios = <&gpio2 19 0>; 77 | linux,default-trigger = "mmc0"; 78 | default-state = "off"; 79 | }; 80 | }; 81 | }; 82 | }; 83 | 84 | fragment@2 { 85 | target = <&i2c2>; 86 | __overlay__ { 87 | #address-cells = <1>; 88 | #size-cells = <0>; 89 | 90 | tlv320aic3x: tlv320aic3x@1b { 91 | compatible = "ti,tlv320aic3x"; 92 | reg = <0x1b>; 93 | status = "okay"; 94 | }; 95 | }; 96 | }; 97 | 98 | fragment@3 { 99 | target = <&mcasp0>; 100 | __overlay__ { 101 | pinctrl-names = "default"; 102 | pinctrl-0 = <&bone_audio_cape_audio_pins>; 103 | 104 | status = "okay"; 105 | 106 | op-mode = <0>; /* MCASP_IIS_MODE */ 107 | tdm-slots = <2>; 108 | num-serializer = <16>; 109 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 110 | 0 0 2 1 111 | 0 0 0 0 112 | 0 0 0 0 113 | 0 0 0 0 114 | >; 115 | tx-num-evt = <1>; 116 | rx-num-evt = <1>; 117 | }; 118 | }; 119 | 120 | fragment@4 { 121 | target = <&ocp>; 122 | __overlay__ { 123 | sound { 124 | compatible = "ti,da830-evm-audio"; 125 | ti,model = "DA830 EVM"; 126 | ti,audio-codec = <&tlv320aic3x>; 127 | ti,mcasp-controller = <&mcasp0>; 128 | ti,codec-clock-rate = <12000000>; 129 | ti,audio-routing = 130 | "Headphone Jack", "HPLOUT", 131 | "Headphone Jack", "HPROUT", 132 | "LINE1L", "Line In", 133 | "LINE1R", "Line In"; 134 | }; 135 | }; 136 | 137 | }; 138 | }; 139 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-AUDI-02-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-AUDI-02"; 16 | version = "00A0", "A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.31", /* mcasp0: mcasp0_aclkx */ 22 | "P9.29", /* mcasp0: mcasp0_fsx */ 23 | "P9.28", /* mcasp0: mcasp0_axr2 */ 24 | "P9.25", /* mcasp0: mcasp0_ahclkx */ 25 | /* the hardware ip uses */ 26 | "gpio1_18", "gpio1_19", 27 | "mcasp0"; 28 | 29 | fragment@0 { 30 | target = <&am33xx_pinmux>; 31 | __overlay__ { 32 | 33 | i2c2_pins: pinmux_i2c2_pins { 34 | pinctrl-single,pins = < 35 | 0x150 0x72 /*spi0_scl.i2c2_sda,SLEWCTRL_SLOW | INPUT_PULLUP |MODE2*/ 36 | 0x154 0x72 /*spi0_d0.i2c2_scl,SLEWCTRL_SLOW | INPUT_PULLUP | MODE2*/ 37 | >; 38 | }; 39 | 40 | bone_audio_cape_audio_pins: pinmux_bone_audio_cape_audio_pins { 41 | pinctrl-single,pins = < 42 | 0x1ac 0x00 /* mcasp0_ahclkx, MODE0 | INPUT */ 43 | 0x19c 0x22 /* mcasp0_ahclkr, */ 44 | 0x194 0x20 /* mcasp0_fsx, MODE0 | OUTPUT */ 45 | 0x190 0x20 /* mcasp0_aclkr.mcasp0_aclkx, MODE0 | OUTPUT_PULLDOWN */ 46 | 0x198 0x20 47 | >; 48 | }; 49 | }; 50 | }; 51 | 52 | fragment@1 { 53 | target = <&i2c2>; 54 | __overlay__ { 55 | #address-cells = <1>; 56 | #size-cells = <0>; 57 | clock-frequency = <100000>; 58 | status = "okay"; 59 | pinctrl-names = "default"; 60 | pinctrl-0 = <&i2c2_pins>; 61 | 62 | 63 | tlv320aic3x: tlv320aic3x@18 { 64 | compatible = "ti,tlv320aic3x"; 65 | reg = <0x18>; 66 | status = "okay"; 67 | }; 68 | }; 69 | }; 70 | 71 | fragment@2 { 72 | target = <&mcasp0>; 73 | __overlay__ { 74 | pinctrl-names = "default"; 75 | pinctrl-0 = <&bone_audio_cape_audio_pins>; 76 | 77 | status = "okay"; 78 | 79 | op-mode = <0>; /* MCASP_IIS_MODE */ 80 | tdm-slots = <2>; 81 | num-serializer = <16>; 82 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 83 | 2 0 1 0 84 | 0 0 0 0 85 | 0 0 0 0 86 | 0 0 0 0 87 | >; 88 | tx-num-evt = <1>; 89 | rx-num-evt = <1>; 90 | }; 91 | }; 92 | 93 | fragment@3 { 94 | target = <&ocp>; 95 | __overlay__ { 96 | sound { 97 | compatible = "ti,da830-evm-audio"; 98 | ti,model = "DA830 EVM"; 99 | ti,audio-codec = <&tlv320aic3x>; 100 | ti,mcasp-controller = <&mcasp0>; 101 | ti,codec-clock-rate = <12000000>; 102 | ti,audio-routing = 103 | "Headphone Jack", "HPLOUT", 104 | "Headphone Jack", "HPROUT", 105 | "LINE1L", "Line In", 106 | "LINE1R", "Line In"; 107 | }; 108 | }; 109 | 110 | }; 111 | }; 112 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-BACON-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Circuit Co. 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-BACON"; 16 | 17 | /* state the resources this cape uses */ 18 | exclusive-use = 19 | /* the pin header uses */ 20 | "P9.36", /* AIN5 */ 21 | "P8.19", /* gpio-keys: gpio0_23 */ 22 | "P9.14", /* pwm: ehrpwm1A */ 23 | "P9.16", /* pwm: ehrpwm1B */ 24 | "P9.42", /* pwm: eCAP0_in_PWM0_out */ 25 | "P9.17", /* shift: gpio0_5 LATCH */ 26 | "P9.18", /* shift: gpio0_4 SERIAL */ 27 | "P9.22", /* shift: gpio0_2 CLOCK */ 28 | /* the hardware IP uses */ 29 | "tscadc", 30 | "gpio0_23", 31 | "ehrpwm1A", 32 | "ehrpwm1B", 33 | "eCAP0_in_PWM0_out", 34 | "gpio0_5", 35 | "gpio0_4", 36 | "gpio0_2"; 37 | 38 | fragment@0 { 39 | target = <&am33xx_pinmux>; 40 | __overlay__ { 41 | 42 | bacon_key_pins: pinmux_bacon_key_pins { 43 | pinctrl-single,pins = < 44 | 0x020 0x2f /* gpmc_ad8.gpio0_22, INPUT | PULLDIS | MODE7 */ 45 | >; 46 | }; 47 | 48 | bacon_ehrpwm1_pins: pinmux_bacon_ehrpwm1_pins { 49 | pinctrl-single,pins = < 50 | 0x048 0x6 /* P9_14 (ZCZ ball U14) | MODE 6 */ 51 | 0x04c 0x6 /* P9_16 (ZCZ ball T14) | MODE 6 */ 52 | >; 53 | }; 54 | 55 | bacon_ecap0_pins: pinmux_bacon_ecap0_pins { 56 | pinctrl-single,pins = < 57 | 0x164 0x0 /* P9_42 (ZCZ ball C18) | MODE 0 */ 58 | >; 59 | }; 60 | 61 | bacon_gpiohelp_pins: pinmux_bacon_gpio_helper_pins { 62 | pinctrl-single,pins = < 63 | 0x15c 0x0f /* P9 17 spi0_cs0.gpio0_5 | MODE7 | OUTPUT */ 64 | 0x158 0x0f /* P9 18 spi0_d1.gpio0_4 | MODE7 | OUTPUT */ 65 | 0x150 0x0f /* P9 22 spi0_sclk.gpio0_2 | MODE7 | OUTPUT */ 66 | >; 67 | }; 68 | }; 69 | }; 70 | 71 | fragment@1 { 72 | target = <&ocp>; 73 | __overlay__ { 74 | /* avoid stupid warning */ 75 | #address-cells = <1>; 76 | #size-cells = <1>; 77 | 78 | tscadc { 79 | compatible = "ti,ti-tscadc"; 80 | reg = <0x44e0d000 0x1000>; 81 | 82 | interrupt-parent = <&intc>; 83 | interrupts = <16>; 84 | ti,hwmods = "adc_tsc"; 85 | status = "okay"; 86 | 87 | adc { 88 | ti,adc-channels = <0 1 2 3 4 5 6 7>; /* 8 channels (but only #5 is used) */ 89 | }; 90 | }; 91 | 92 | bacon_adc_helper { 93 | compatible = "bone-iio-helper"; 94 | vsense-name = "AIN0", "AIN1", "AIN2", "AIN3", "AIN4", "AIN5", "AIN6", "AIN7"; 95 | /* report micro-volts */ 96 | vsense-scale = <100000 100000 100000 100000 100000 100000 100000 100000>; 97 | status = "okay"; 98 | }; 99 | 100 | /* the single button */ 101 | bacon_gpio_keys { 102 | compatible = "gpio-keys"; 103 | pinctrl-names = "default"; 104 | pinctrl-0 = <&bacon_key_pins>; 105 | 106 | #address-cells = <1>; 107 | #size-cells = <0>; 108 | 109 | button@0 { 110 | debounce_interval = <50>; 111 | linux,code = <28>; 112 | label = "enter"; 113 | gpios = <&gpio1 22 0x1>; /* really gpio0_23 */ 114 | gpio-key,wakeup; 115 | }; 116 | }; 117 | }; 118 | }; 119 | 120 | fragment@3 { 121 | target = <&epwmss0>; 122 | __overlay__ { 123 | status = "okay"; 124 | }; 125 | }; 126 | 127 | fragment@4 { 128 | target = <&ecap0>; 129 | __overlay__ { 130 | pinctrl-names = "default"; 131 | pinctrl-0 = <&bacon_ecap0_pins>; 132 | status = "okay"; 133 | }; 134 | }; 135 | 136 | fragment@5 { 137 | target = <&epwmss1>; 138 | __overlay__ { 139 | status = "okay"; 140 | }; 141 | }; 142 | 143 | fragment@6 { 144 | target = <&ehrpwm1>; 145 | __overlay__ { 146 | pinctrl-names = "default"; 147 | pinctrl-0 = <&bacon_ehrpwm1_pins>; 148 | status = "okay"; 149 | }; 150 | }; 151 | 152 | fragment@7 { 153 | target = <&ocp>; 154 | __overlay__ { 155 | bacon_pwm_leds { 156 | compatible = "pwm-leds"; 157 | 158 | bacon_pwm_green { 159 | label = "bacon::green"; 160 | pwms = <&ehrpwm1 0 500000 0>; 161 | max-brightness = <255>; 162 | }; 163 | 164 | bacon_pwm_blue { 165 | label = "bacon::blue"; 166 | pwms = <&ehrpwm1 1 500000 0>; 167 | max-brightness = <255>; 168 | }; 169 | 170 | bacon_pwm_red { 171 | label = "bacon::red"; 172 | pwms = <&ecap0 0 500000 0>; 173 | max-brightness = <255>; 174 | }; 175 | }; 176 | }; 177 | }; 178 | 179 | fragment@8 { 180 | target = <&ocp>; 181 | __overlay__ { 182 | 183 | bacon_gpiohelp { 184 | compatible = "gpio-of-helper"; 185 | status = "okay"; 186 | pinctrl-names = "default"; 187 | pinctrl-0 = <&bacon_gpiohelp_pins>; 188 | 189 | /* declare your gpios */ 190 | LATCH { 191 | gpio-name = "LATCH"; 192 | gpio = <&gpio1 5 0x00>; /* gpio1 is gpio0 */ 193 | output; 194 | init-high; 195 | }; 196 | 197 | SERIAL { 198 | gpio-name = "SERIAL"; 199 | gpio = <&gpio1 4 0x00>; /* gpio1 is gpio0 */ 200 | output; 201 | init-low; 202 | }; 203 | 204 | CLOCK { 205 | gpio-name = "CLOCK"; 206 | gpio = <&gpio1 2 0x00>; /* gpio1 is gpio0 */ 207 | output; 208 | init-low; 209 | }; 210 | }; 211 | }; 212 | }; 213 | 214 | 215 | 216 | }; 217 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-BACONE-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Circuit Co. 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-BACONE"; 16 | 17 | /* state the resources this cape uses */ 18 | exclusive-use = 19 | /* the pin header uses */ 20 | "P9.36", /* AIN5 */ 21 | "P8.19", /* gpio-keys: gpio0_23 */ 22 | "P9.14", /* pwm: ehrpwm1A */ 23 | "P9.16", /* pwm: ehrpwm1B */ 24 | "P9.42", /* pwm: eCAP0_in_PWM0_out */ 25 | "P9.17", /* shift: gpio0_5 LATCH */ 26 | "P9.18", /* shift: gpio0_4 SERIAL */ 27 | "P9.22", /* shift: gpio0_2 CLOCK */ 28 | /* the hardware IP uses */ 29 | "tscadc", 30 | "gpio0_23", 31 | "ehrpwm1A", 32 | "ehrpwm1B", 33 | "eCAP0_in_PWM0_out", 34 | "gpio0_5", 35 | "gpio0_4", 36 | "gpio0_2"; 37 | 38 | fragment@0 { 39 | target = <&am33xx_pinmux>; 40 | __overlay__ { 41 | 42 | bacon_ehrpwm1_pins: pinmux_bacon_ehrpwm1_pins { 43 | pinctrl-single,pins = < 44 | 0x048 0x6 /* P9_14 (ZCZ ball U14) | MODE 6 */ 45 | 0x04c 0x6 /* P9_16 (ZCZ ball T14) | MODE 6 */ 46 | >; 47 | }; 48 | 49 | bacon_ecap0_pins: pinmux_bacon_ecap0_pins { 50 | pinctrl-single,pins = < 51 | 0x164 0x0 /* P9_42 (ZCZ ball C18) | MODE 0 */ 52 | >; 53 | }; 54 | 55 | bacon_gpiohelp_pins: pinmux_bacon_gpio_helper_pins { 56 | pinctrl-single,pins = < 57 | 0x020 0x2f /* gpmc_ad8.gpio0_22, INPUT | PULLDIS | MODE7 */ 58 | 0x15c 0x0f /* P9 17 spi0_cs0.gpio0_5 | MODE7 | OUTPUT */ 59 | 0x158 0x0f /* P9 18 spi0_d1.gpio0_4 | MODE7 | OUTPUT */ 60 | 0x150 0x0f /* P9 22 spi0_sclk.gpio0_2 | MODE7 | OUTPUT */ 61 | >; 62 | }; 63 | }; 64 | }; 65 | 66 | fragment@1 { 67 | target = <&ocp>; 68 | __overlay__ { 69 | /* avoid stupid warning */ 70 | #address-cells = <1>; 71 | #size-cells = <1>; 72 | 73 | tscadc { 74 | compatible = "ti,ti-tscadc"; 75 | reg = <0x44e0d000 0x1000>; 76 | 77 | interrupt-parent = <&intc>; 78 | interrupts = <16>; 79 | ti,hwmods = "adc_tsc"; 80 | status = "okay"; 81 | 82 | adc { 83 | ti,adc-channels = <0 1 2 3 4 5 6 7>; /* 8 channels (but only #5 is used) */ 84 | }; 85 | }; 86 | 87 | bacon_adc_helper { 88 | compatible = "bone-iio-helper"; 89 | vsense-name = "AIN0", "AIN1", "AIN2", "AIN3", "AIN4", "AIN5", "AIN6", "AIN7"; 90 | /* report micro-volts */ 91 | vsense-scale = <100000 100000 100000 100000 100000 100000 100000 100000>; 92 | status = "okay"; 93 | }; 94 | }; 95 | }; 96 | 97 | fragment@3 { 98 | target = <&epwmss0>; 99 | __overlay__ { 100 | status = "okay"; 101 | }; 102 | }; 103 | 104 | fragment@4 { 105 | target = <&ecap0>; 106 | __overlay__ { 107 | pinctrl-names = "default"; 108 | pinctrl-0 = <&bacon_ecap0_pins>; 109 | status = "okay"; 110 | }; 111 | }; 112 | 113 | fragment@5 { 114 | target = <&epwmss1>; 115 | __overlay__ { 116 | status = "okay"; 117 | }; 118 | }; 119 | 120 | fragment@6 { 121 | target = <&ehrpwm1>; 122 | __overlay__ { 123 | pinctrl-names = "default"; 124 | pinctrl-0 = <&bacon_ehrpwm1_pins>; 125 | status = "okay"; 126 | }; 127 | }; 128 | 129 | fragment@8 { 130 | target = <&ocp>; 131 | __overlay__ { 132 | 133 | bacon_gpiohelp { 134 | compatible = "gpio-of-helper"; 135 | status = "okay"; 136 | pinctrl-names = "default"; 137 | pinctrl-0 = <&bacon_gpiohelp_pins>; 138 | 139 | /* declare your gpios */ 140 | LATCH { 141 | gpio-name = "LATCH"; 142 | gpio = <&gpio1 5 0x00>; /* gpio1 is gpio0 */ 143 | output; 144 | init-high; 145 | }; 146 | 147 | SERIAL { 148 | gpio-name = "SERIAL"; 149 | gpio = <&gpio1 4 0x00>; /* gpio1 is gpio0 */ 150 | output; 151 | init-low; 152 | }; 153 | 154 | CLOCK { 155 | gpio-name = "CLOCK"; 156 | gpio = <&gpio1 2 0x00>; /* gpio1 is gpio0 */ 157 | output; 158 | init-low; 159 | }; 160 | 161 | BUTTON { 162 | gpio-name = "BUTTON"; 163 | gpio = <&gpio1 22 0x01>; /* gpio1 is gpio0 */ 164 | input; 165 | }; 166 | }; 167 | }; 168 | }; 169 | }; 170 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-BACONE2-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Circuit Co. 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-BACONE2"; 16 | 17 | /* state the resources this cape uses */ 18 | exclusive-use = 19 | /* the pin header uses */ 20 | "P9.36", /* AIN5 */ 21 | "P8.19", /* gpio-keys: gpio0_23 */ 22 | "P9.14", /* pwm: ehrpwm1A */ 23 | "P9.16", /* pwm: ehrpwm1B */ 24 | "P9.42", /* pwm: eCAP0_in_PWM0_out */ 25 | "P9.17", /* shift: gpio0_5 LATCH */ 26 | "P9.18", /* shift: gpio0_4 SERIAL */ 27 | "P9.22", /* shift: gpio0_2 CLOCK */ 28 | /* the hardware IP uses */ 29 | "tscadc", 30 | "gpio0_23", 31 | "ehrpwm1A", 32 | "ehrpwm1B", 33 | "eCAP0_in_PWM0_out", 34 | "gpio0_5", 35 | "gpio0_4", 36 | "gpio0_2"; 37 | 38 | fragment@0 { 39 | target = <&am33xx_pinmux>; 40 | __overlay__ { 41 | 42 | bacon_ehrpwm1_pins: pinmux_bacon_ehrpwm1_pins { 43 | pinctrl-single,pins = < 44 | 0x048 0x6 /* P9_14 (ZCZ ball U14) | MODE 6 */ 45 | 0x04c 0x6 /* P9_16 (ZCZ ball T14) | MODE 6 */ 46 | >; 47 | }; 48 | 49 | bacon_ecap0_pins: pinmux_bacon_ecap0_pins { 50 | pinctrl-single,pins = < 51 | 0x164 0x0 /* P9_42 (ZCZ ball C18) | MODE 0 */ 52 | >; 53 | }; 54 | 55 | bacon_gpiohelp_pins: pinmux_bacon_gpio_helper_pins { 56 | pinctrl-single,pins = < 57 | 0x020 0x2f /* gpmc_ad8.gpio0_22, INPUT | PULLDIS | MODE7 */ 58 | >; 59 | }; 60 | 61 | bacon_LATCH_in_pins: pinmux_bacon_LATCH_in_pins { 62 | pinctrl-single,pins = < 63 | 0x15c 0x0f /* P9 17 spi0_cs0.gpio0_5 | MODE7 | OUTPUT */ 64 | >; 65 | }; 66 | 67 | bacon_LATCH_out_pins: pinmux_bacon_LATCH_out_pins { 68 | pinctrl-single,pins = < 69 | 0x15c 0x2f /* P9 17 spi0_cs0.gpio0_5 | MODE7 | PULLDIS | INPUT */ 70 | >; 71 | }; 72 | 73 | bacon_SERIAL_in_pins: pinmux_bacon_SERIAL_in_pins { 74 | pinctrl-single,pins = < 75 | 0x158 0x2f /* P9 18 spi0_d1.gpio0_4 | MODE7 | PULLDIS | INPUT */ 76 | >; 77 | }; 78 | 79 | bacon_SERIAL_out_pins: pinmux_bacon_SERIAL_out_pins { 80 | pinctrl-single,pins = < 81 | 0x158 0x0f /* P9 18 spi0_d1.gpio0_4 | MODE7 | OUTPUT */ 82 | >; 83 | }; 84 | 85 | bacon_CLOCK_in_pins: pinmux_bacon_CLOCK_in_pins { 86 | pinctrl-single,pins = < 87 | 0x150 0x2f /* P9 22 spi0_sclk.gpio0_2 | MODE7 | PULLDIS | INPUT */ 88 | >; 89 | }; 90 | 91 | bacon_CLOCK_out_pins: pinmux_bacon_CLOCK_out_pins { 92 | pinctrl-single,pins = < 93 | 0x150 0x0f /* P9 22 spi0_sclk.gpio0_2 | MODE7 | OUTPUT */ 94 | >; 95 | }; 96 | }; 97 | }; 98 | 99 | fragment@1 { 100 | target = <&ocp>; 101 | __overlay__ { 102 | /* avoid stupid warning */ 103 | #address-cells = <1>; 104 | #size-cells = <1>; 105 | 106 | tscadc { 107 | compatible = "ti,ti-tscadc"; 108 | reg = <0x44e0d000 0x1000>; 109 | 110 | interrupt-parent = <&intc>; 111 | interrupts = <16>; 112 | ti,hwmods = "adc_tsc"; 113 | status = "okay"; 114 | 115 | adc { 116 | ti,adc-channels = <0 1 2 3 4 5 6 7>; /* 8 channels (but only #5 is used) */ 117 | }; 118 | }; 119 | 120 | bacon_adc_helper { 121 | compatible = "bone-iio-helper"; 122 | vsense-name = "AIN0", "AIN1", "AIN2", "AIN3", "AIN4", "AIN5", "AIN6", "AIN7"; 123 | /* report micro-volts */ 124 | vsense-scale = <100000 100000 100000 100000 100000 100000 100000 100000>; 125 | status = "okay"; 126 | }; 127 | }; 128 | }; 129 | 130 | fragment@3 { 131 | target = <&epwmss0>; 132 | __overlay__ { 133 | status = "okay"; 134 | }; 135 | }; 136 | 137 | fragment@4 { 138 | target = <&ecap0>; 139 | __overlay__ { 140 | pinctrl-names = "default"; 141 | pinctrl-0 = <&bacon_ecap0_pins>; 142 | status = "okay"; 143 | }; 144 | }; 145 | 146 | fragment@5 { 147 | target = <&epwmss1>; 148 | __overlay__ { 149 | status = "okay"; 150 | }; 151 | }; 152 | 153 | fragment@6 { 154 | target = <&ehrpwm1>; 155 | __overlay__ { 156 | pinctrl-names = "default"; 157 | pinctrl-0 = <&bacon_ehrpwm1_pins>; 158 | status = "okay"; 159 | }; 160 | }; 161 | 162 | fragment@8 { 163 | target = <&ocp>; 164 | __overlay__ { 165 | 166 | LATCH_helper { 167 | compatible = "bone-pinmux-helper"; 168 | status = "okay"; 169 | pinctrl-names = "in", "out"; 170 | pinctrl-0 = <&bacon_LATCH_in_pins>; 171 | pinctrl-1 = <&bacon_LATCH_out_pins>; 172 | }; 173 | 174 | SERIAL_helper { 175 | compatible = "bone-pinmux-helper"; 176 | status = "okay"; 177 | pinctrl-names = "in", "out"; 178 | pinctrl-0 = <&bacon_SERIAL_in_pins>; 179 | pinctrl-1 = <&bacon_SERIAL_out_pins>; 180 | }; 181 | 182 | CLOCK_helper { 183 | compatible = "bone-pinmux-helper"; 184 | status = "okay"; 185 | pinctrl-names = "in", "out"; 186 | pinctrl-0 = <&bacon_CLOCK_in_pins>; 187 | pinctrl-1 = <&bacon_CLOCK_out_pins>; 188 | }; 189 | 190 | bacon_gpiohelp { 191 | compatible = "gpio-of-helper"; 192 | status = "okay"; 193 | pinctrl-names = "default"; 194 | pinctrl-0 = <&bacon_gpiohelp_pins>; 195 | 196 | BUTTON { 197 | gpio-name = "BUTTON"; 198 | gpio = <&gpio1 22 0x01>; /* gpio1 is gpio0 */ 199 | input; 200 | }; 201 | }; 202 | }; 203 | }; 204 | }; 205 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-CRYPTO-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2014 Cryptotronix 3 | * 4 | * Cape support for the CryptoCape 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-BONE-CRYPTO"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | /* For Flashing the ATmega328p */ 24 | "P9.13", /* uart4_txd */ 25 | "P9.11", /* uart4_rxd */ 26 | "P9.23", /* gpio1_17 */ 27 | /* As the AUTHO Input from the AES132 */ 28 | "P8.11", /* gpio1_13 */ 29 | /* the hardware ip uses */ 30 | "uart4", 31 | "gpio1_13", 32 | "gpio1_17"; 33 | 34 | fragment@0 { 35 | target = <&am33xx_pinmux>; 36 | __overlay__ { 37 | 38 | cryptocape_pins: pinmux_cryptocape_pins { 39 | pinctrl-single,pins = < 40 | 0x044 0x17 /* gpio1_17 FAST | OUTPUT | PULLUP | MODE7 */ 41 | 0x034 0x2F /* gpio1_13 FAST | INPUT | PULLDOWN | MODE7 */ 42 | >; 43 | }; 44 | 45 | cryptocape_uart4_pins: pinmux_cryptocape_uart4_pins { 46 | pinctrl-single,pins = < 47 | 0x070 0x26 /* uart4_rxd | FAST | INPUT | MODE6 */ 48 | 0x074 0x06 /* uart4_txd | FAST | OUTPUT | MODE6 */ 49 | >; 50 | }; 51 | }; 52 | }; 53 | 54 | fragment@1 { 55 | target = <&uart5>; /* uart4 to the BBB hardware */ 56 | __overlay__ { 57 | status = "okay"; 58 | pinctrl-names = "default"; 59 | pinctrl-0 = <&cryptocape_uart4_pins>; 60 | }; 61 | }; 62 | 63 | 64 | fragment@2 { 65 | target = <&i2c2>; 66 | 67 | __overlay__ { 68 | /* needed to avoid gripping by DTC */ 69 | #address-cells = <1>; 70 | #size-cells = <0>; 71 | 72 | /* Real Time Clock */ 73 | ds1307@68 { 74 | compatible = "ds1307"; 75 | reg = <0x68>; 76 | }; 77 | 78 | /* TPM - Driver currently only available in 3.13.x */ 79 | tpm_i2c_atmel@29 { 80 | compatible = "tpm_i2c_atmel"; 81 | reg = <0x29>; 82 | }; 83 | }; 84 | }; 85 | 86 | fragment@3 { 87 | target = <&ocp>; 88 | __overlay__ { 89 | 90 | cryptocape_gpio_helper { 91 | compatible = "gpio-of-helper"; 92 | status = "okay"; 93 | pinctrl-names = "default"; 94 | pinctrl-0 = <&cryptocape_pins>; 95 | 96 | /* declare your gpios */ 97 | atmega_rst { 98 | gpio-name = "atmega_rst"; 99 | gpio = <&gpio2 17 0x00>; /* gpio2 is gpio1 */ 100 | output; 101 | init-high; 102 | }; 103 | 104 | ataes132_auth { 105 | gpio-name = "test_input"; 106 | gpio = <&gpio2 13 0x00>; /* gpio2 is gpio1 */ 107 | input; 108 | count-rising-edge; 109 | count-falling-edge; 110 | }; 111 | }; 112 | }; 113 | }; 114 | }; 115 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-GPEVT-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * This program is free software; you can redistribute it and/or modify 3 | * it under the terms of the GNU General Public License version 2 as 4 | * published by the Free Software Foundation. 5 | */ 6 | /dts-v1/; 7 | /plugin/; 8 | 9 | / { 10 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 11 | 12 | /* identification */ 13 | part-number = "BB-BONE-GPEVT"; 14 | version = "00A0"; 15 | 16 | /* state the resources this cape uses */ 17 | exclusive-use = 18 | /* the pin header uses */ 19 | "P8.7", 20 | /* the hardware IP uses */ 21 | "gpio2_2"; 22 | 23 | fragment@0 { 24 | target = <&am33xx_pinmux>; 25 | __overlay__ { 26 | gpevt_pins_s0: pinmux_gpevt_pins_s0 { 27 | pinctrl-single,pins = < 28 | 0x090 0x37 /* gpmc_advn_ale.gpio2_2, INPUT_PULLUP | MODE7 */ 29 | >; 30 | }; 31 | }; 32 | }; 33 | 34 | fragment@1 { 35 | target = <&ocp>; 36 | __overlay__ { 37 | gpevt { 38 | compatible = "gpevt"; 39 | pinctrl-names = "default"; 40 | pinctrl-0 = <&gpevt_pins_s0>; 41 | 42 | dmas = <&edma 12>; 43 | dma-names = "gpioevt"; 44 | gpio-evt = <&gpio3 2 0>; 45 | }; 46 | }; 47 | }; 48 | }; 49 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-GPS-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-GPS"; 16 | version = "00A0"; 17 | 18 | fragment@0 { 19 | target = <&am33xx_pinmux>; 20 | __overlay__ { 21 | uart_pins: pinmux_uart_pins { 22 | pinctrl-single,pins = < 23 | 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 | PULL_UP */ 24 | 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ 25 | >; 26 | }; 27 | 28 | pps_pins: pinmux_pps_pins { 29 | pinctrl-single,pins = < 30 | 0x040 0x27 /* gpmc_a0.gpio1_16, INPUT | PULLDIS | MODE7 */ 31 | >; 32 | }; 33 | }; 34 | }; 35 | 36 | fragment@1 { 37 | target = <&uart3>; 38 | __overlay__ { 39 | status = "okay"; 40 | pinctrl-names = "default"; 41 | pinctrl-0 = <&uart_pins>; 42 | }; 43 | }; 44 | 45 | fragment@2 { 46 | target = <&ocp>; 47 | __overlay__ { 48 | pps { 49 | compatible = "pps-gpio"; 50 | status = "okay"; 51 | pinctrl-names = "default"; 52 | pinctrl-0 = <&pps_pins>; 53 | 54 | gpios = <&gpio2 16 0>; 55 | assert-falling-edge; 56 | }; 57 | }; 58 | }; 59 | }; 60 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-HAS-00R1.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2014 Dennie de Groot 3 | * 4 | * Cape support for the Home Automation System 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | 11 | /dts-v1/; 12 | /plugin/; 13 | 14 | / { 15 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 16 | 17 | /* identification */ 18 | part-number = "BB-BONE-HAS"; 19 | version = "00R1"; 20 | 21 | /* state the resources this cape uses */ 22 | exclusive-use = 23 | /* the pin header uses */ 24 | "P9.22", /* uart2_rxd */ 25 | "P9.23", /* gpio1.17 */ 26 | "P9.24", /* uart1_txd */ 27 | "P9.25", /* gpio3.21 */ 28 | "P9.26", /* uart1_rxd */ 29 | /* the hardware ip uses */ 30 | "uart1", 31 | "uart2", 32 | "gpio1_17", 33 | "gpio3_21"; 34 | 35 | fragment@0 { 36 | target = <&am33xx_pinmux>; 37 | __overlay__ { 38 | bb_uart1_pins: pinmux_bb_uart1_pins { 39 | pinctrl-single,pins = < 40 | 0x184 0x20 /* P9.24 uart1_txd.uart1_txd | OUTPUT | MODE 0 */ 41 | 0x180 0x20 /* P9.26 uart1_rxd.uart1_rxd | INPUT | MODE 0 */ 42 | >; 43 | }; 44 | 45 | bb_uart2_pins: pinmux_bb_uart2_pins { 46 | pinctrl-single,pins = < 47 | 0x150 0x21 /* P9.22 spi0_sclk.uart2_rxd | INPUT | MODE1 */ 48 | >; 49 | }; 50 | 51 | bb_gpio_pins: pinmux_bb_gpio_pins { 52 | pinctrl-single,pins = < 53 | 0x044 0x07 /* P9.23 gpmc_a1.gpio1[17] | OUTPUT | MODE7 */ 54 | 0x1AC 0x07 /* P9.25 mcasp0_ahclkx.gpio3[21] | OUTPUT | MODE7 */ 55 | >; 56 | }; 57 | }; 58 | }; 59 | 60 | fragment@1 { 61 | target = <&uart2>; 62 | __overlay__ { 63 | status = "okay"; 64 | pinctrl-names = "default"; 65 | pinctrl-0 = <&bb_uart1_pins>; 66 | }; 67 | }; 68 | 69 | fragment@2 { 70 | target = <&uart3>; 71 | __overlay__ { 72 | status = "okay"; 73 | pinctrl-names = "default"; 74 | pinctrl-0 = <&bb_uart2_pins>; 75 | }; 76 | }; 77 | 78 | fragment@3 { 79 | target = <&ocp>; 80 | __overlay__ { 81 | gpio_helper { 82 | compatible = "gpio-of-helper"; 83 | status = "okay"; 84 | pinctrl-names = "default"; 85 | pinctrl-0 = <&bb_gpio_pins>; 86 | 87 | RESET { 88 | gpio-name = "has:reset"; 89 | gpio = <&gpio2 17 0x00>; 90 | output; 91 | init-low; 92 | }; 93 | 94 | P1 { 95 | gpio-name = "has:p1"; 96 | gpio = <&gpio4 21 0x00>; 97 | output; 98 | init-low; 99 | }; 100 | }; 101 | }; 102 | }; 103 | 104 | fragment@4 { 105 | target = <&i2c2>; 106 | __overlay__ { 107 | #address-cells = <1>; 108 | #size-cells = <0>; 109 | 110 | rtc@68 { 111 | compatible = "dallas,ds3231"; 112 | reg = <0x68>; 113 | }; 114 | }; 115 | }; 116 | }; 117 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-LCD4-01-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-LCD4-01"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P8.45", /* lcd: lcd_data0 */ 22 | "P8.46", /* lcd: lcd_data1 */ 23 | "P8.43", /* lcd: lcd_data2 */ 24 | "P8.44", /* lcd: lcd_data3 */ 25 | "P8.41", /* lcd: lcd_data4 */ 26 | "P8.42", /* lcd: lcd_data5 */ 27 | "P8.39", /* lcd: lcd_data6 */ 28 | "P8.40", /* lcd: lcd_data7 */ 29 | "P8.37", /* lcd: lcd_data8 */ 30 | "P8.38", /* lcd: lcd_data9 */ 31 | "P8.36", /* lcd: lcd_data10 */ 32 | "P8.34", /* lcd: lcd_data11 */ 33 | "P8.35", /* lcd: lcd_data12 */ 34 | "P8.33", /* lcd: lcd_data13 */ 35 | "P8.31", /* lcd: lcd_data14 */ 36 | "P8.32", /* lcd: lcd_data15 */ 37 | "P8.27", /* lcd: lcd_vsync */ 38 | "P8.29", /* lcd: lcd_hsync */ 39 | "P8.28", /* lcd: lcd_pclk */ 40 | "P8.30", /* lcd: lcd_ac_bias_en */ 41 | "P9.16", /* tsc: gpio1_19 */ 42 | "P9.14", /* led: gpio1_18 */ 43 | /* the hardware IP uses */ 44 | "gpio1_19", 45 | "gpio1_18", 46 | "lcd", 47 | "tps-bl"; 48 | 49 | fragment@0 { 50 | target = <&am33xx_pinmux>; 51 | __overlay__ { 52 | 53 | bone_lcd4_cape_led_00A0_pins: pinmux_bone_lcd4_cape_led_00A0_pins { 54 | pinctrl-single,pins = < 55 | 0x48 0x07 /* gpmc_a2.gpio1_18, OUTPUT | MODE7 */ 56 | >; 57 | }; 58 | 59 | bone_lcd4_cape_lcd_pins: pinmux_bone_lcd4_cape_lcd_pins { 60 | pinctrl-single,pins = < 61 | 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 62 | 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 63 | 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 64 | 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 65 | 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 66 | 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 67 | 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 68 | 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 69 | 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 70 | 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 71 | 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 72 | 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 73 | 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 74 | 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 75 | 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 76 | 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 77 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 78 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 79 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 80 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 81 | 0x4c 0x27 /* TSC_INT gpmc_a3.gpio1_19, INPUT | MODE7 */ 82 | >; 83 | }; 84 | 85 | }; 86 | }; 87 | 88 | fragment@1 { 89 | target = <&tps>; 90 | __overlay__ { 91 | backlight { 92 | compatible = "not-tps65217-backlight"; 93 | isel = <1>; 94 | fdim = <200>; 95 | brightness = <100>; 96 | tps = <&tps>; 97 | }; 98 | }; 99 | }; 100 | 101 | fragment@2 { 102 | target = <&ocp>; 103 | 104 | __overlay__ { 105 | 106 | /* avoid stupid warning */ 107 | #address-cells = <1>; 108 | #size-cells = <1>; 109 | 110 | tscadc { 111 | compatible = "ti,ti-tscadc"; 112 | reg = <0x44e0d000 0x1000>; 113 | 114 | interrupt-parent = <&intc>; 115 | interrupts = <16>; 116 | ti,hwmods = "adc_tsc"; 117 | status = "okay"; 118 | 119 | tsc { 120 | ti,wires = <4>; 121 | ti,x-plate-resistance = <200>; 122 | ti,coordinate-readouts = <5>; 123 | ti,wire-config = <0x00 0x11 0x22 0x33>; 124 | }; 125 | 126 | adc { 127 | ti,adc-channels = <4 5 6 7>; 128 | }; 129 | }; 130 | 131 | gpio-leds-cape-lcd4 { 132 | compatible = "gpio-leds"; 133 | pinctrl-names = "default"; 134 | 135 | pinctrl-0 = <&bone_lcd4_cape_led_00A0_pins>; 136 | 137 | lcd4-led0 { 138 | label = "lcd4:green:usr0"; 139 | gpios = <&gpio2 18 0>; 140 | linux,default-trigger = "heartbeat"; 141 | default-state = "off"; 142 | }; 143 | }; 144 | 145 | /* Settings for NHD-4.3-ATXI#-T-1 / LCD4 cape: */ 146 | panel { 147 | compatible = "tilcdc,panel"; 148 | pinctrl-names = "default"; 149 | pinctrl-0 = <&bone_lcd4_cape_lcd_pins>; 150 | panel-info { 151 | ac-bias = <255>; 152 | ac-bias-intrpt = <0>; 153 | dma-burst-sz = <16>; 154 | bpp = <24>; 155 | fdd = <0x80>; 156 | tft-alt-mode = <0>; 157 | stn-565-mode = <0>; 158 | mono-8bit-mode = <0>; 159 | sync-edge = <0>; 160 | sync-ctrl = <1>; 161 | raster-order = <0>; 162 | fifo-th = <0>; 163 | }; 164 | display-timings { 165 | native-mode = <&timing0>; 166 | timing0: 480x272 { 167 | hactive = <480>; 168 | vactive = <272>; 169 | hback-porch = <44>; 170 | hfront-porch = <9>; 171 | hsync-len = <5>; 172 | vback-porch = <13>; 173 | vfront-porch = <4>; 174 | vsync-len = <10>; 175 | clock-frequency = <9000000>; 176 | hsync-active = <0>; 177 | vsync-active = <0>; 178 | }; 179 | }; 180 | }; 181 | 182 | fb { 183 | compatible = "ti,am33xx-tilcdc"; 184 | reg = <0x4830e000 0x1000>; 185 | interrupt-parent = <&intc>; 186 | interrupts = <36>; 187 | ti,hwmods = "lcdc"; 188 | }; 189 | 190 | }; 191 | }; 192 | }; 193 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-PRU-01-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-PRU-01"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.27", /* pru0: pr1_pru0_pru_r30_5 */ 22 | /* the hardware IP uses */ 23 | "pru0"; 24 | 25 | fragment@0 { 26 | target = <&am33xx_pinmux>; 27 | __overlay__ { 28 | 29 | pru_gpio_pins: pinmux_pru_gpio_pins { 30 | pinctrl-single,pins = < 31 | 0x1a4 0x0f /* P9 27 GPIO3_19: mcasp0_fsr.gpio3[19] | MODE7 | OUTPUT */ 32 | >; 33 | }; 34 | 35 | pru_pru_pins: pinmux_pru_pru_pins { 36 | pinctrl-single,pins = < 37 | 0x1a4 0x25 /* mcasp0_fsr.pr1_pru0_pru_r30_5, MODE5 | OUTPUT | PRU */ 38 | >; 39 | }; 40 | }; 41 | }; 42 | 43 | fragment@2 { 44 | target = <&pruss>; 45 | __overlay__ { 46 | status = "okay"; 47 | 48 | pinctrl-names = "default"; 49 | pinctrl-0 = <&pru_pru_pins>; 50 | }; 51 | }; 52 | }; 53 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-PRU-02-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-PRU-01"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.27", /* pru0: pr1_pru0_pru_r30_5 */ 22 | /* the hardware IP uses */ 23 | "pru0"; 24 | 25 | fragment@0 { 26 | target = <&am33xx_pinmux>; 27 | __overlay__ { 28 | 29 | pru_gpio_pins: pinmux_pru_gpio_pins { 30 | pinctrl-single,pins = < 31 | 0x1a4 0x0f /* P9 27 GPIO3_19: mcasp0_fsr.gpio3[19] | MODE7 | OUTPUT */ 32 | >; 33 | }; 34 | 35 | pru_pru_pins: pinmux_pru_pru_pins { 36 | pinctrl-single,pins = < 37 | 0x1a4 0x25 /* mcasp0_fsr.pr1_pru0_pru_r30_5, MODE5 | OUTPUT | PRU */ 38 | >; 39 | }; 40 | }; 41 | }; 42 | 43 | fragment@2 { 44 | target = <&ocp>; 45 | 46 | __overlay__ { 47 | 48 | /* avoid stupid warning */ 49 | #address-cells = <1>; 50 | #size-cells = <1>; 51 | 52 | prurproc { 53 | compatible = "ti,pru-rproc"; 54 | 55 | pinctrl-names = "default"; 56 | pinctrl-0 = <&pru_pru_pins>; 57 | 58 | ti,hwmods = "pruss"; 59 | ti,deassert-hard-reset = "pruss", "pruss"; 60 | reg = <0x4a300000 0x080000>; 61 | ti,pintc-offset = <0x20000>; 62 | interrupt-parent = <&intc>; 63 | status = "okay"; 64 | interrupts = <20 21 22 23 24 25 26 27>; 65 | }; 66 | }; 67 | }; 68 | }; 69 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-PWMT-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-PWMT"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.22", /* pwm: ehrpwm0a */ 22 | /* the hardware ip uses */ 23 | "ehrpwm0a"; 24 | 25 | fragment@0 { 26 | target = <&am33xx_pinmux>; 27 | __overlay__ { 28 | pwm_test_pins: pinmux_pwm_test_pins { 29 | pinctrl-single,pins = <0x150 0x3>; /* spi0_sclk = ehrpwm0A = P9_14 | MODE 3 */ 30 | }; 31 | }; 32 | }; 33 | 34 | fragment@1 { 35 | target = <&epwmss0>; 36 | __overlay__ { 37 | status = "okay"; 38 | }; 39 | }; 40 | 41 | fragment@2 { 42 | target = <&ehrpwm0>; 43 | __overlay__ { 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&pwm_test_pins>; 46 | status = "okay"; 47 | }; 48 | }; 49 | 50 | fragment@3 { 51 | target = <&ocp>; 52 | __overlay__ { 53 | pwm_test { 54 | compatible = "pwm_test"; 55 | pwms = <&ehrpwm0 0 500000 1>; 56 | pwm-names = "PWM0"; 57 | enabled = <1>; 58 | duty = <0>; 59 | status = "okay"; 60 | }; 61 | }; 62 | }; 63 | }; 64 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-RS232-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-RS232"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.22", /* rs232: uart2_rxd */ 22 | "P9.21", /* rs232: uart2_txd */ 23 | /* the hardware IP uses */ 24 | "uart2"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | uart_pins: pinmux_uart_pins { 30 | pinctrl-single,pins = < 31 | 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 | PULL_UP */ 32 | 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ 33 | >; 34 | }; 35 | }; 36 | }; 37 | 38 | fragment@1 { 39 | target = <&uart3>; 40 | __overlay__ { 41 | status = "okay"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&uart_pins>; 44 | }; 45 | }; 46 | 47 | }; 48 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-RST-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * This program is free software; you can redistribute it and/or modify 3 | * it under the terms of the GNU General Public License version 2 as 4 | * published by the Free Software Foundation. 5 | */ 6 | /dts-v1/; 7 | /plugin/; 8 | 9 | / { 10 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 11 | 12 | /* identification */ 13 | part-number = "BB-BONE-RST"; 14 | version = "00A0"; 15 | 16 | fragment@0 { 17 | target = <&ocp>; 18 | __overlay__ { 19 | test_rctrl: test_reset { 20 | compatible = "test-rctrl"; 21 | #reset-cells = <2>; 22 | }; 23 | }; 24 | }; 25 | 26 | fragment@1 { 27 | target = <&ocp>; 28 | __overlay__ { 29 | test_consumer_rctrl: test_consumer_reset { 30 | compatible = "test-consumer-rctrl"; 31 | 32 | reset = <&test_rctrl 0 0>; 33 | reset-names = "RESET_1"; 34 | }; 35 | }; 36 | }; 37 | 38 | fragment@2 { 39 | target = <&ocp>; 40 | __overlay__ { 41 | gpio_rctrl: gpio_reset { 42 | compatible = "gpio-rctrl"; 43 | #reset-cells = <2>; 44 | 45 | gpios = <&gpio2 28 0x1>, <&gpio2 29 0x0>; 46 | gpio-names = "HDMI-reset", "eMMC-reset"; 47 | }; 48 | }; 49 | }; 50 | 51 | fragment@3 { 52 | target = <&ocp>; 53 | __overlay__ { 54 | gpio_consumer_rctrl:gpio_consumer_reset { 55 | compatible = "test-consumer-rctrl"; 56 | 57 | reset = <&gpio_rctrl 0 0>, <&gpio_rctrl 1 0>; 58 | reset-names = "RESET_1", "RESET_2"; 59 | }; 60 | }; 61 | }; 62 | }; 63 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-RST2-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * This program is free software; you can redistribute it and/or modify 3 | * it under the terms of the GNU General Public License version 2 as 4 | * published by the Free Software Foundation. 5 | */ 6 | /dts-v1/; 7 | /plugin/; 8 | 9 | / { 10 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 11 | 12 | /* identification */ 13 | part-number = "BB-BONE-RST2"; 14 | version = "00A0"; 15 | 16 | fragment@0 { 17 | target = <&ocp>; 18 | __overlay__ { 19 | emmc_reset_consumer_rctrl: emmc_reset_consumer { 20 | compatible = "test-consumer-rctrl"; 21 | 22 | reset = <&rstctl 0 0>; 23 | reset-names = "eMMC_RSTn-CONSUMER"; 24 | }; 25 | }; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-RTC-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | /* 12 | * Pin assignments 13 | * 14 | * Module Connector 15 | * SCL -> P9.19 16 | * SDA <- P9.20 17 | * SQW/PPS <- P9.15 18 | * 19 | */ 20 | 21 | / { 22 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 23 | part-number = "BB-BONE-RTC-01"; 24 | version = "00A0"; 25 | 26 | /* state the resources this cape uses */ 27 | exclusive-use = 28 | /* the pin header uses */ 29 | "P9.15"; /*gpio1_16 */ 30 | 31 | 32 | fragment@0 { 33 | target = <&am33xx_pinmux>; 34 | __overlay__ { 35 | pps_pins: pinmux_pps_pins { 36 | pinctrl-single,pins = < 37 | 0x040 0x27 /* gpmc_a0.gpio1_16, INPUT | PULLDIS | MODE7 */ 38 | >; 39 | }; 40 | }; 41 | }; 42 | 43 | 44 | fragment@1 { 45 | target = <&i2c2>; 46 | 47 | __overlay__ { 48 | /* shut up DTC warnings */ 49 | #address-cells = <1>; 50 | #size-cells = <0>; 51 | 52 | /* DS1307 RTC module */ 53 | rtc@68 { 54 | compatible = "dallas,ds1307"; 55 | reg = <0x68>; 56 | }; 57 | }; 58 | }; 59 | 60 | fragment@2 { 61 | target = <&ocp>; 62 | __overlay__ { 63 | pps { 64 | compatible = "pps-gpio"; 65 | status = "okay"; 66 | pinctrl-names = "default"; 67 | pinctrl-0 = <&pps_pins>; 68 | 69 | gpios = <&gpio2 16 0>; 70 | assert-falling-edge; 71 | }; 72 | }; 73 | }; 74 | }; 75 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-SERL-01-00A1.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Martin Gysel 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | part-number = "BB-BONE-SERL-01"; 15 | version = "00A1"; 16 | 17 | /* state the resources this cape uses */ 18 | exclusive-use = 19 | /* the pin header uses */ 20 | "P9.26", /* dcan1: dcan1_tx */ 21 | "P9.24", /* dcan1: dcan1_rx */ 22 | /* the hardware IP uses */ 23 | "dcan1"; 24 | 25 | fragment@0 { 26 | target = <&am33xx_pinmux>; 27 | __overlay__ { 28 | bone_serl_01_dcan1_pins: bone_serl_01_dcan1_pins { 29 | pinctrl-single,pins = < 30 | 0x180 0x02 /* uart1_rxd.d_can1_tx", OUTPUT | MODE2 */ 31 | 0x184 0x32 /* uart1_txd.d_can1_rx", INPUT_PULLUP | MODE2 */ 32 | >; 33 | }; 34 | }; 35 | }; 36 | 37 | fragment@1 { 38 | target = <&dcan1>; 39 | __overlay__ { 40 | status = "okay"; 41 | pinctrl-names = "default"; 42 | pinctrl-0 = <&bone_serl_01_dcan1_pins>; 43 | }; 44 | }; 45 | }; 46 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-SERL-03-00A1.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * RS232 cape for the default configuration on UART2 5 | * Use one of the BB-UART* examples if you modify the default 6 | * configuration. 7 | * 8 | * This program is free software; you can redistribute it and/or modify 9 | * it under the terms of the GNU General Public License version 2 as 10 | * published by the Free Software Foundation. 11 | */ 12 | /dts-v1/; 13 | /plugin/; 14 | 15 | / { 16 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 17 | 18 | /* identification */ 19 | part-number = "BB-BONE-SERL-03"; 20 | version = "00A1"; 21 | 22 | /* state the resources this cape uses */ 23 | exclusive-use = 24 | /* the pin header uses */ 25 | "P9.21", /* uart2_txd */ 26 | "P9.22", /* uart2_rxd */ 27 | /* the hardware ip uses */ 28 | "uart2"; 29 | 30 | fragment@0 { 31 | target = <&am33xx_pinmux>; 32 | __overlay__ { 33 | bb_uart2_pins: pinmux_bb_uart2_pins { 34 | pinctrl-single,pins = < 35 | 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 */ 36 | 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ 37 | >; 38 | }; 39 | }; 40 | }; 41 | 42 | fragment@1 { 43 | target = <&uart3>; /* really uart2 */ 44 | __overlay__ { 45 | status = "okay"; 46 | pinctrl-names = "default"; 47 | pinctrl-0 = <&bb_uart2_pins>; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONE-eMMC1-01-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-eMMC1-01"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P8.21", /* mmc1: mmc1_clk */ 22 | "P8.20", /* mmc1: mmc1_cmd */ 23 | "P8.25", /* mmc1: mmc1_dat0 */ 24 | "P8.24", /* mmc1: mmc1_dat1 */ 25 | "P8.5", /* mmc1: mmc1_dat2 */ 26 | "P8.6", /* mmc1: mmc1_dat3 */ 27 | "P8.23", /* mmc1: mmc1_dat4 */ 28 | "P8.22", /* mmc1: mmc1_dat5 */ 29 | "P8.3", /* mmc1: mmc1_dat6 */ 30 | "P8.4", /* mmc1: mmc1_dat7 */ 31 | /* the hardware IP uses */ 32 | "mmc1"; 33 | 34 | fragment@0 { 35 | target = <&am33xx_pinmux>; 36 | __overlay__ { 37 | emmc2_pins: pinmux_emmc2_pins { 38 | pinctrl-single,pins = < 39 | 0x80 0x32 /* gpmc_csn1.mmc1_clk, INPUT_PULLUP | MODE2 */ 40 | 0x84 0x32 /* gpmc_csn1.mmc1_cmd, INPUT_PULLUP | MODE2 */ 41 | 0x00 0x31 /* gpmc_ad0.mmc1_dat0, INPUT_PULLUP | MODE1 */ 42 | 0x04 0x31 /* gpmc_ad1.mmc1_dat1, INPUT_PULLUP | MODE1 */ 43 | 0x08 0x31 /* gpmc_ad2.mmc1_dat2, INPUT_PULLUP | MODE1 */ 44 | 0x0c 0x31 /* gpmc_ad3.mmc1_dat3, INPUT_PULLUP | MODE1 */ 45 | 0x10 0x31 /* gpmc_ad4.mmc1_dat4, INPUT_PULLUP | MODE1 */ 46 | 0x14 0x31 /* gpmc_ad5.mmc1_dat5, INPUT_PULLUP | MODE1 */ 47 | 0x18 0x31 /* gpmc_ad6.mmc1_dat6, INPUT_PULLUP | MODE1 */ 48 | 0x1c 0x31 /* gpmc_ad7.mmc1_dat7, INPUT_PULLUP | MODE1 */ 49 | >; 50 | }; 51 | }; 52 | }; 53 | fragment@1 { 54 | target = <&mmc2>; 55 | __overlay__ { 56 | pinctrl-names = "default"; 57 | pinctrl-0 = <&emmc2_pins>; /* wrong numbering */ 58 | vmmc-supply = <&ldo3_reg>; 59 | bus-width = <8>; 60 | ti,non-removable; 61 | status = "okay"; 62 | ti,vcc-aux-disable-is-sleep; 63 | 64 | reset = <&rstctl 0 0>; 65 | reset-names = "eMMC_RSTn"; 66 | }; 67 | }; 68 | }; 69 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-BONELT-BT-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONELT-BT"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P8.43", /* bt: gpio2_8 */ 22 | /* the hardware IP uses */ 23 | "gpio2_8"; 24 | 25 | fragment@0 { 26 | target = <&am33xx_pinmux>; 27 | __overlay__ { 28 | 29 | bone_bt_cape_key_pins: pinmux_bone_bt_cape_key_pins { 30 | pinctrl-single,pins = < 31 | 0x0a8 0x2f /* P8.43 lcd_data2.gpio2[8] DISABLE internal pullup */ 32 | >; 33 | }; 34 | }; 35 | }; 36 | 37 | fragment@1 { 38 | target = <&ocp>; 39 | __overlay__ { 40 | bt_gpio_key { 41 | compatible = "gpio-keys"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&bone_bt_cape_key_pins>; 44 | 45 | #address-cells = <1>; 46 | #size-cells = <0>; 47 | 48 | button@1 { 49 | debounce_interval = <0>; 50 | linux,code = <28>; 51 | label = "enter"; 52 | gpios = <&gpio3 8 0x0>; 53 | }; 54 | }; 55 | }; 56 | }; 57 | }; 58 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-GPIOHELP-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Pantelis Antoniou 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-GPIOHELP"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.27", /* gpio */ 22 | "P9.28", /* gpio */ 23 | /* the hardware IP uses */ 24 | "gpio3_19", "gpio3_17"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | gpio_helper_pins: pinmux_gpio_helper_pins { 30 | pinctrl-single,pins = < 31 | 0x1a4 0x0f /* P9 27 GPIO3_19: mcasp0_fsr.gpio3_19 | MODE7 | OUTPUT */ 32 | 0x19c 0x2f /* P9 28 SPI1_CS0: mcasp0_ahclkr.gpio3_17 | MODE7 | INPUT */ 33 | >; 34 | }; 35 | }; 36 | }; 37 | 38 | fragment@2 { 39 | target = <&ocp>; 40 | __overlay__ { 41 | 42 | gpio_helper { 43 | compatible = "gpio-of-helper"; 44 | status = "okay"; 45 | pinctrl-names = "default"; 46 | pinctrl-0 = <&gpio_helper_pins>; 47 | 48 | /* declare your gpios */ 49 | test_led { 50 | gpio-name = "test_led"; 51 | gpio = <&gpio4 19 0x00>; /* gpio4 is gpio3 */ 52 | output; 53 | init-high; 54 | }; 55 | 56 | test_input { 57 | gpio-name = "test_input"; 58 | gpio = <&gpio4 17 0x00>; /* gpio4 is gpio3 */ 59 | input; 60 | count-rising-edge; 61 | count-falling-edge; 62 | }; 63 | }; 64 | }; 65 | }; 66 | }; 67 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-I2C1-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for I2C1 on connector pins P9.17 P9.18 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-I2C1"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.18", /* i2c1_sda */ 24 | "P9.17", /* i2c1_scl */ 25 | /* the hardware ip uses */ 26 | "i2c1"; 27 | 28 | fragment@0 { 29 | target = <&am33xx_pinmux>; 30 | __overlay__ { 31 | bb_i2c1_pins: pinmux_bb_i2c1_pins { 32 | pinctrl-single,pins = < 33 | 0x158 0x72 /* spi0_d1.i2c1_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */ 34 | 0x15c 0x72 /* spi0_cs0.i2c1_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */ 35 | >; 36 | }; 37 | }; 38 | }; 39 | 40 | fragment@1 { 41 | target = <&i2c1>; /* i2c1 is numbered correctly */ 42 | __overlay__ { 43 | status = "okay"; 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&bb_i2c1_pins>; 46 | 47 | /* this is the configuration part */ 48 | clock-frequency = <100000>; 49 | 50 | #address-cells = <1>; 51 | #size-cells = <0>; 52 | 53 | /* add any i2c devices on the bus here */ 54 | 55 | // commented out example of a touchscreen (taken from BB-BONE-LCD7-01-00A4) */ 56 | // maxtouch@4a { 57 | // compatible = "mXT224"; 58 | // reg = <0x4a>; 59 | // interrupt-parent = <&gpio4>; 60 | // interrupts = <19 0x0>; 61 | // atmel,irq-gpio = <&gpio4 19 0>; 62 | // }; 63 | }; 64 | }; 65 | }; 66 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-I2C1A1-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for I2C1 on connector pins P9.26 P9.24 (ALT config #1) 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-I2C1A1"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.26", /* i2c1_sda */ 24 | "P9.24", /* i2c1_scl */ 25 | /* the hardware ip uses */ 26 | "i2c1"; 27 | 28 | fragment@0 { 29 | target = <&am33xx_pinmux>; 30 | __overlay__ { 31 | bb_i2c1a1_pins: pinmux_bb_i2c1a1_pins { 32 | pinctrl-single,pins = < 33 | 0x180 0x73 /* uart1_rxd.i2c1_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ 34 | 0x184 0x73 /* uart1_txdi2c1_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ 35 | >; 36 | }; 37 | }; 38 | }; 39 | 40 | fragment@1 { 41 | target = <&i2c1>; /* i2c1 is numbered correctly */ 42 | __overlay__ { 43 | status = "okay"; 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&bb_i2c1a1_pins>; 46 | 47 | /* this is the configuration part */ 48 | clock-frequency = <100000>; 49 | 50 | #address-cells = <1>; 51 | #size-cells = <0>; 52 | 53 | /* add any i2c devices on the bus here */ 54 | 55 | // commented out example of a touchscreen (taken from BB-BONE-LCD7-01-00A4) */ 56 | // maxtouch@4a { 57 | // compatible = "mXT224"; 58 | // reg = <0x4a>; 59 | // interrupt-parent = <&gpio4>; 60 | // interrupts = <19 0x0>; 61 | // atmel,irq-gpio = <&gpio4 19 0>; 62 | // }; 63 | }; 64 | }; 65 | }; 66 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-SPIDEV0-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for SPI0 on connector pins P9.22 P9.21 P9.18 P9.17 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-SPI0"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.17", /* spi0_cs0 */ 24 | "P9.18", /* spi0_d1 */ 25 | "P9.21", /* spi0_d0 */ 26 | "P9.22", /* spi0_sclk */ 27 | /* the hardware ip uses */ 28 | "spi0"; 29 | 30 | fragment@0 { 31 | target = <&am33xx_pinmux>; 32 | __overlay__ { 33 | /* default state has all gpios released and mode set to uart1 */ 34 | bb_spi0_pins: pinmux_bb_spi0_pins { 35 | pinctrl-single,pins = < 36 | 0x150 0x30 /* spi0_sclk.spi0_sclk, INPUT_PULLUP | MODE0 */ 37 | 0x154 0x30 /* spi0_d0.spi0_d0, INPUT_PULLUP | MODE0 */ 38 | 0x158 0x10 /* spi0_d1.spi0_d1, OUTPUT_PULLUP | MODE0 */ 39 | 0x15c 0x10 /* spi0_cs0.spi0_cs0, OUTPUT_PULLUP | MODE0 */ 40 | >; 41 | }; 42 | }; 43 | }; 44 | 45 | fragment@1 { 46 | target = <&spi0>; /* spi0 is numbered correctly */ 47 | __overlay__ { 48 | #address-cells = <1>; 49 | #size-cells = <0>; 50 | 51 | status = "okay"; 52 | pinctrl-names = "default"; 53 | pinctrl-0 = <&bb_spi0_pins>; 54 | 55 | 56 | channel@0 { 57 | #address-cells = <1>; 58 | #size-cells = <0>; 59 | 60 | compatible = "spidev"; 61 | 62 | reg = <0>; 63 | spi-max-frequency = <16000000>; 64 | spi-cpha; 65 | }; 66 | 67 | 68 | channel@1 { 69 | #address-cells = <1>; 70 | #size-cells = <0>; 71 | 72 | compatible = "spidev"; 73 | 74 | reg = <1>; 75 | spi-max-frequency = <16000000>; 76 | }; 77 | }; 78 | }; 79 | }; 80 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-SPIDEV1-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for SPI1 on connector pins P9.29 P9.31 P9.30 P9.28 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-SPI1"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.31", /* spi1_sclk */ 24 | "P9.29", /* spi1_d0 */ 25 | "P9.30", /* spi1_d1 */ 26 | "P9.28", /* spi1_cs0 */ 27 | // "P9.42", /* spi1_cs1 */ 28 | /* the hardware ip uses */ 29 | "spi1"; 30 | 31 | fragment@0 { 32 | target = <&am33xx_pinmux>; 33 | __overlay__ { 34 | /* default state has all gpios released and mode set to uart1 */ 35 | bb_spi1_pins: pinmux_bb_spi1_pins { 36 | pinctrl-single,pins = < 37 | 0x190 0x33 /* mcasp0_aclkx.spi1_sclk, INPUT_PULLUP | MODE3 */ 38 | 0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */ 39 | 0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */ 40 | 0x19c 0x13 /* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE3 */ 41 | // 0x164 0x12 /* eCAP0_in_PWM0_out.spi1_cs1 OUTPUT_PULLUP | MODE2 */ 42 | >; 43 | }; 44 | }; 45 | }; 46 | 47 | fragment@1 { 48 | target = <&spi1>; /* spi1 is numbered correctly */ 49 | __overlay__ { 50 | status = "okay"; 51 | pinctrl-names = "default"; 52 | pinctrl-0 = <&bb_spi1_pins>; 53 | 54 | #address-cells = <1>; 55 | #size-cells = <0>; 56 | 57 | channel@0 { 58 | #address-cells = <1>; 59 | #size-cells = <0>; 60 | 61 | compatible = "spidev"; 62 | 63 | reg = <0>; 64 | spi-max-frequency = <16000000>; 65 | spi-cpha; 66 | }; 67 | 68 | 69 | channel@1 { 70 | #address-cells = <1>; 71 | #size-cells = <0>; 72 | 73 | compatible = "spidev"; 74 | 75 | reg = <1>; 76 | spi-max-frequency = <16000000>; 77 | }; 78 | }; 79 | }; 80 | }; 81 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-SPIDEV1A1-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for SPI1 (ALT #1) on connector pins 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-SPI1"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.42", /* spi1_sclk */ 24 | "P9.29", /* spi1_d0 */ 25 | "P9.30", /* spi1_d1 */ 26 | "P9.20", /* spi1_cs0 */ 27 | /* the hardware ip uses */ 28 | "spi1"; 29 | 30 | fragment@0 { 31 | target = <&am33xx_pinmux>; 32 | __overlay__ { 33 | /* default state has all gpios released and mode set to uart1 */ 34 | bb_spi1_pins: pinmux_bb_spi1_pins { 35 | pinctrl-single,pins = < 36 | 0x164 0x34 /* eCAP0_in_PWM0_out.spi1_sclk, INPUT_PULLUP | MODE4 */ 37 | /* NOTE: P9.42 is connected to two pads */ 38 | // 0x1A0 0x27 /* set the other pad to gpio input */ 39 | 0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */ 40 | 0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */ 41 | 0x178 0x14 /* uart1_ctsn.spi1_cs0, OUTPUT_PULLUP | MODE4 */ 42 | >; 43 | }; 44 | }; 45 | }; 46 | 47 | fragment@1 { 48 | target = <&spi1>; /* spi1 is numbered correctly */ 49 | __overlay__ { 50 | status = "okay"; 51 | pinctrl-names = "default"; 52 | pinctrl-0 = <&bb_spi1_pins>; 53 | 54 | #address-cells = <1>; 55 | #size-cells = <0>; 56 | 57 | channel@0 { 58 | #address-cells = <1>; 59 | #size-cells = <0>; 60 | 61 | compatible = "spidev"; 62 | 63 | reg = <0>; 64 | spi-max-frequency = <16000000>; 65 | spi-cpha; 66 | }; 67 | 68 | 69 | channel@1 { 70 | #address-cells = <1>; 71 | #size-cells = <0>; 72 | 73 | compatible = "spidev"; 74 | 75 | reg = <1>; 76 | spi-max-frequency = <16000000>; 77 | }; 78 | }; 79 | }; 80 | }; 81 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-UART1-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for UART1 on connector pins P9.24 P9.26 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-UART1"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.24", /* uart1_txd */ 24 | "P9.26", /* uart1_rxd */ 25 | /* the hardware ip uses */ 26 | "uart1"; 27 | 28 | fragment@0 { 29 | target = <&am33xx_pinmux>; 30 | __overlay__ { 31 | bb_uart1_pins: pinmux_bb_uart1_pins { 32 | pinctrl-single,pins = < 33 | 0x184 0x20 /* P9.24 uart1_txd.uart1_txd OUTPUT */ 34 | 0x180 0x20 /* P9.26 uart1_rxd.uart1_rxd INPUT */ 35 | >; 36 | }; 37 | }; 38 | }; 39 | 40 | fragment@1 { 41 | target = <&uart2>; /* really uart1 */ 42 | __overlay__ { 43 | status = "okay"; 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&bb_uart1_pins>; 46 | }; 47 | }; 48 | }; 49 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-UART2-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for UART2 on connector pins P9.21 P9.22 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-UART2"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.21", /* uart2_txd */ 24 | "P9.22", /* uart2_rxd */ 25 | /* the hardware ip uses */ 26 | "uart2"; 27 | 28 | fragment@0 { 29 | target = <&am33xx_pinmux>; 30 | __overlay__ { 31 | bb_uart2_pins: pinmux_bb_uart2_pins { 32 | pinctrl-single,pins = < 33 | 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 */ 34 | 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ 35 | >; 36 | }; 37 | }; 38 | }; 39 | 40 | fragment@1 { 41 | target = <&uart3>; /* really uart2 */ 42 | __overlay__ { 43 | status = "okay"; 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&bb_uart2_pins>; 46 | }; 47 | }; 48 | }; 49 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-UART2-RTSCTS-00A0.dts: -------------------------------------------------------------------------------- 1 | /* BB-UART2-RTSCTS-00A0.dts 2 | * Written by Alexander Hiam 3 | * for Logic Supply - http://logicsupply.com 4 | * Jan 28, 2014 5 | * 6 | * This overlay enables RTS/CTS flow control for UART2. 7 | * HDMI must be disabled before enabling this overlay, see: 8 | * http://www.logicsupply.com/blog/2013/07/18/disabling-the-beaglebone-black-hdmi-cape/ 9 | * 10 | * Copyright (c) 2014 - Logic Supply (http://logicsupply.com) 11 | * This program is free software; you can redistribute it and/or modify 12 | * it under the terms of the GNU General Public License version 2 as 13 | * published by the Free Software Foundation. 14 | */ 15 | 16 | /dts-v1/; 17 | /plugin/; 18 | 19 | /{ 20 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 21 | 22 | part-number = "BB-UART2-RTSCTS"; 23 | version = "00A0"; 24 | 25 | exclusive-use = 26 | "P8.38", /* uart2 rts */ 27 | "P8.37"; /* uart2 cts */ 28 | 29 | fragment@0 { 30 | /* Sets pinmux for flow control pins. */ 31 | target = <&am33xx_pinmux>; 32 | __overlay__ { 33 | u2_rtscts_pins: pinmux_u2_rtscts_pins { 34 | pinctrl-single,pins = < 35 | 0x0c4 0x0e /* lcd_data9 - pullup | mode 6 (uart2_rtsn) */ 36 | 0x0c0 0x36 /* lcd_data8 - rx enable | pullup | mode 6 (uart2_ctsn) */ 37 | >; 38 | }; 39 | }; 40 | }; 41 | 42 | fragment@1 { 43 | /* Enable pinmux-helper driver for setting mux configuration. */ 44 | target = <&ocp>; /* On-Chip Peripherals */ 45 | __overlay__ { 46 | uart2-rtscts-pinmux { 47 | compatible = "bone-pinmux-helper"; /* Use the pinmux helper */ 48 | status="okay"; 49 | /* Define custom names for indexes in pinctrl array: */ 50 | pinctrl-names = "default"; 51 | /* Set the elements of the pinctrl array to the pinmux overlays 52 | defined above: */ 53 | pinctrl-0 = <&u2_rtscts_pins>; 54 | }; 55 | }; 56 | }; 57 | }; 58 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-UART4-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for UART4 on connector pins P9.13 P9.11 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-UART4"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P9.13", /* uart4_txd */ 24 | "P9.11", /* uart4_rxd */ 25 | /* the hardware ip uses */ 26 | "uart4"; 27 | 28 | fragment@0 { 29 | target = <&am33xx_pinmux>; 30 | __overlay__ { 31 | bb_uart4_pins: pinmux_bb_uart4_pins { 32 | pinctrl-single,pins = < 33 | 0x070 0x26 /* gpmc_wait0.uart4_rxd | MODE6 */ 34 | 0x074 0x06 /* gpmc_wpn.uart4_txd | MODE6 */ 35 | >; 36 | }; 37 | }; 38 | }; 39 | 40 | fragment@1 { 41 | target = <&uart5>; /* really uart4 */ 42 | __overlay__ { 43 | status = "okay"; 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&bb_uart4_pins>; 46 | }; 47 | }; 48 | }; 49 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-UART4-RTSCTS-00A0.dts: -------------------------------------------------------------------------------- 1 | /* BB-UART4-RTSCTS-00A0.dts 2 | * Written by Alexander Hiam 3 | * for Logic Supply - http://logicsupply.com 4 | * Jan 28, 2014 5 | * 6 | * This overlay enables RTS/CTS flow control for UART4. 7 | * HDMI must be disabled before enabling this overlay, see: 8 | * http://www.logicsupply.com/blog/2013/07/18/disabling-the-beaglebone-black-hdmi-cape/ 9 | * 10 | * Copyright (c) 2014 - Logic Supply (http://logicsupply.com) 11 | * This program is free software; you can redistribute it and/or modify 12 | * it under the terms of the GNU General Public License version 2 as 13 | * published by the Free Software Foundation. 14 | */ 15 | 16 | /dts-v1/; 17 | /plugin/; 18 | 19 | /{ 20 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 21 | 22 | part-number = "BB-UART4-RTSCTS"; 23 | version = "00A0"; 24 | 25 | exclusive-use = 26 | "P8.33", /* uart4 rts */ 27 | "P8.35"; /* uart4 cts */ 28 | 29 | fragment@0 { 30 | /* Sets pinmux for flow control pins. */ 31 | target = <&am33xx_pinmux>; 32 | __overlay__ { 33 | u4_rtscts_pins: pinmux_u4_rtscts_pins { 34 | pinctrl-single,pins = < 35 | 0x0d4 0x0e /* lcd_data13 - pullup | mode 6 (uart4_rtsn) */ 36 | 0x0d0 0x36 /* lcd_data12 - rx enable | pullup | mode 6 (uart4_ctsn) */ 37 | >; 38 | }; 39 | }; 40 | }; 41 | 42 | fragment@1 { 43 | /* Enable pinmux-helper driver for setting mux configuration. */ 44 | target = <&ocp>; /* On-Chip Peripherals */ 45 | __overlay__ { 46 | uart4-rtscts-pinmux { 47 | compatible = "bone-pinmux-helper"; /* Use the pinmux helper */ 48 | status="okay"; 49 | /* Define custom names for indexes in pinctrl array: */ 50 | pinctrl-names = "default"; 51 | /* Set the elements of the pinctrl array to the pinmux overlays 52 | defined above: */ 53 | pinctrl-0 = <&u4_rtscts_pins>; 54 | }; 55 | }; 56 | }; 57 | }; 58 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/BB-UART5-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * 4 | * Virtual cape for UART5 on connector pins P9.37 P8.38 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "BB-UART5"; 18 | version = "00A0"; 19 | 20 | /* state the resources this cape uses */ 21 | exclusive-use = 22 | /* the pin header uses */ 23 | "P8.37", /* uart5_txd */ 24 | "P8.38", /* uart5_rxd */ 25 | /* the hardware ip uses */ 26 | "uart5"; 27 | 28 | fragment@0 { 29 | target = <&am33xx_pinmux>; 30 | __overlay__ { 31 | bb_uart5_pins: pinmux_bb_uart5_pins { 32 | pinctrl-single,pins = < 33 | /* the uart pins */ 34 | 0x0C4 0x24 /* lcd_data9.uart5_rxd | MODE4 */ 35 | 0x0C0 0x04 /* lcd_data8.uart5_txd | MODE4 */ 36 | >; 37 | }; 38 | }; 39 | }; 40 | 41 | fragment@1 { 42 | target = <&uart6>; /* really uart5 */ 43 | __overlay__ { 44 | status = "okay"; 45 | pinctrl-names = "default"; 46 | pinctrl-0 = <&bb_uart5_pins>; 47 | }; 48 | }; 49 | }; 50 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/DNIL-AMPCAPE-1-00R1.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Overlay for DNIL Electronic Audio Amplifier Cape. 3 | * Copyright (C) 2013 DNIL Electronic - http://www.dnil.se 4 | * 5 | * Work based on Beagle Board Toys Audio Cape; 6 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 7 | * 8 | * This program is free software; you can redistribute it and/or modify 9 | * it under the terms of the GNU General Public License version 2 as 10 | * published by the Free Software Foundation. 11 | */ 12 | /dts-v1/; 13 | /plugin/; 14 | 15 | / { 16 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 17 | 18 | /* identification */ 19 | part-number = "DNIL-AMPCAPE-1"; 20 | version = "00R1"; 21 | 22 | /* state the resources this cape uses */ 23 | exclusive-use = 24 | /* the pin header uses */ 25 | "P9.14", /* leds: gpio1_18 */ 26 | "P9.16", /* leds: gpio1_19 */ 27 | "P9.31", /* mcasp0: mcasp0_aclkx */ 28 | "P9.29", /* mcasp0: mcasp0_fsx */ 29 | "P9.28", /* mcasp0: mcasp0_axr2 Codec -> SoC */ 30 | "P9.25", /* mcasp0: mcasp0_axr3 SoC -> Codec */ 31 | /* the hardware ip uses */ 32 | "gpio1_18", "gpio1_19", 33 | "mcasp0"; 34 | 35 | fragment@0 { 36 | target = <&am33xx_pinmux>; 37 | __overlay__ { 38 | 39 | dnil_ampcape_led_pins: pinmux_dnil_ampcape_led_pins { 40 | pinctrl-single,pins = < 41 | 0x48 0x07 /* gpmc_a2.gpio1_18, OUTPUT | MODE7 */ 42 | 0x4c 0x07 /* gpmc_a3.gpio1_19, OUTPUT | MODE7 */ 43 | >; 44 | }; 45 | 46 | dnil_ampcape_audio_pins: pinmux_dnil_ampcape_audio_pins { 47 | pinctrl-single,pins = < 48 | 0x190 0x20 /* mcasp0_aclkx, INPUT | MODE0 */ 49 | 0x194 0x20 /* mcasp0_fsx, INPUT | MODE0 */ 50 | 0x19c 0x22 /* mcasp0_axr2, INPUT | MODE2 */ 51 | 0x1ac 0x22 /* mcasp0_axr3, OUTPUT | MODE2 */ 52 | 53 | >; 54 | }; 55 | }; 56 | }; 57 | 58 | fragment@1 { 59 | target = <&ocp>; 60 | __overlay__ { 61 | 62 | /* avoid stupid warning */ 63 | #address-cells = <1>; 64 | #size-cells = <1>; 65 | 66 | gpio-leds-cape-audio { 67 | compatible = "gpio-leds"; 68 | pinctrl-names = "default"; 69 | pinctrl-0 = <&dnil_ampcape_led_pins>; 70 | 71 | audio-led0 { 72 | label = "audio:green:usr0"; 73 | gpios = <&gpio2 18 0>; 74 | linux,default-trigger = "heartbeat"; 75 | default-state = "off"; 76 | }; 77 | 78 | audio-led1 { 79 | label = "audio:green:usr1"; 80 | gpios = <&gpio2 19 0>; 81 | linux,default-trigger = "mmc0"; 82 | default-state = "off"; 83 | }; 84 | }; 85 | }; 86 | }; 87 | 88 | fragment@2 { 89 | target = <&i2c2>; 90 | __overlay__ { 91 | #address-cells = <1>; 92 | #size-cells = <0>; 93 | 94 | tlv320aic3x: tlv320aic3x@1b { 95 | compatible = "ti,tlv320aic3x"; 96 | reg = <0x1b>; 97 | status = "okay"; 98 | }; 99 | }; 100 | }; 101 | 102 | fragment@3 { 103 | target = <&mcasp0>; 104 | __overlay__ { 105 | compatible = "ti,omap2-mcasp-audio"; 106 | pinctrl-names = "default"; 107 | pinctrl-0 = <&dnil_ampcape_audio_pins>; 108 | 109 | status = "okay"; 110 | 111 | op-mode = <0>; /* MCASP_IIS_MODE */ 112 | tdm-slots = <2>; 113 | num-serializer = <16>; 114 | serial-dir = < 115 | 0 0 2 1 /* 0: INACTIVE, 1: TX, 2: RX */ 116 | 0 0 0 0 117 | 0 0 0 0 118 | 0 0 0 0 >; 119 | tx-num-evt = <1>; 120 | rx-num-evt = <1>; 121 | }; 122 | }; 123 | 124 | fragment@4 { 125 | target = <&ocp>; 126 | __overlay__ { 127 | sound { 128 | compatible = "ti,da830-evm-audio"; 129 | ti,model = "DNIL_AMPCAPE"; 130 | ti,audio-codec = <&tlv320aic3x>; 131 | ti,mcasp-controller = <&mcasp0>; 132 | ti,codec-clock-rate = <12000000>; 133 | ti,audio-routing = 134 | "Line Out", "LLOUT", 135 | "Line Out", "RLOUT", 136 | "LINE1L", "Line In", 137 | "LINE1R", "Line In"; 138 | }; 139 | }; 140 | 141 | }; 142 | }; 143 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/Makefile: -------------------------------------------------------------------------------- 1 | ifeq ($(CONFIG_OF),y) 2 | 3 | dtb-$(CONFIG_ARCH_OMAP2PLUS) += \ 4 | omap3-beagle.dtb \ 5 | omap3-beagle-xm.dtb \ 6 | omap3-beagle-xm-ab.dtb \ 7 | am335x-bone.dtb \ 8 | am335x-boneblack.dtb 9 | 10 | targets += dtbs dtbs_install 11 | targets += $(dtb-y) 12 | endif 13 | 14 | # *.dtb used to be generated in the directory above. Clean out the 15 | # old build results so people don't accidentally use them. 16 | dtbs: $(addprefix $(obj)/, $(dtb-y)) 17 | $(Q)rm -f $(obj)/../*.dtb 18 | 19 | clean-files := *.dtb 20 | 21 | dtbs_install: $(addsuffix _dtbinst_, $(dtb-y)) 22 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/TT3201-001-01.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Tower Technologies 3 | * Written by Alessandro Zummo 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | part-number = "TT3201-001"; 16 | version = "01"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.27", /* spi irq: gpio3_19 */ 22 | "P9.25", /* spi irq: gpio3_21 */ 23 | "P9.31", /* spi: spi1_sclk */ 24 | "P9.29", /* spi: spi1_d0 */ 25 | "P9.30", /* spi: spi1_d1 */ 26 | "P9.28", /* spi: spi1_cs0 */ 27 | "P9.42", /* spi: spi1_cs1 */ 28 | "P9.26", /* dcan1: dcan1_tx */ 29 | "P9.24", /* dcan1: dcan1_rx */ 30 | /* the hardware IP uses */ 31 | "gpio3_19", 32 | "gpio3_21", 33 | "spi1", 34 | "dcan1"; 35 | 36 | fragment@0 { 37 | target = <&am33xx_pinmux>; 38 | __overlay__ { 39 | 40 | bone_tt3201_dcan1_pins: bone_tt3201_dcan1_pins { 41 | pinctrl-single,pins = < 42 | 0x180 0x02 /* uart1_rxd.d_can1_tx", OUTPUT | MODE2 */ 43 | 0x184 0x32 /* uart1_txd.d_can1_rx", INPUT_PULLUP | MODE2 */ 44 | >; 45 | }; 46 | 47 | bone_tt3201_spi1_pins: pinmux_bone_tt3201_spi1_pins { 48 | pinctrl-single,pins = < 49 | 0x190 0x33 /* mcasp0_aclkx.spi1_sclk, RX_ENABLED | PULLUP | MODE3 */ 50 | 0x194 0x33 /* mcasp0_fsx.spi1_d0, RX_ENABLED | PULLUP | MODE3 */ 51 | 0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */ 52 | 0x19c 0x13 /* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE3 */ 53 | 0x164 0x12 /* ecap0_in_pwm0_out.spi1_cs1, OUTPUT_PULLUP | MODE2 */ 54 | >; 55 | }; 56 | 57 | bone_tt3201_mcp2515_0_pins: pinmux_bone_tt3201_0_mcp2515_pins { 58 | pinctrl-single,pins = < 59 | 0x1a4 0x37 /* mcasp0_fsr.gpio3_19, RX_ENABLED | PULLUP | MODE7 */ 60 | >; 61 | }; 62 | 63 | bone_tt3201_mcp2515_1_pins: pinmux_bone_tt3201_1_mcp2515_pins { 64 | pinctrl-single,pins = < 65 | 0x1ac 0x37 /* mcasp0_ahclkx.gpio3_21, RX_ENABLED | PULLUP | MODE7 */ 66 | >; 67 | }; 68 | }; 69 | }; 70 | 71 | fragment@1 { 72 | target = <&spi1>; 73 | 74 | __overlay__ { 75 | #address-cells = <1>; 76 | #size-cells = <0>; 77 | 78 | status = "okay"; 79 | pinctrl-names = "default"; 80 | pinctrl-0 = <&bone_tt3201_spi1_pins>; 81 | 82 | cs-gpios = <&gpio4 17 0>, <&gpio1 7 0>; 83 | 84 | mcp2515@0 { 85 | 86 | compatible = "microchip,mcp2515"; 87 | reg = <1>; /* cs1 */ 88 | mode = <0>; 89 | 90 | spi-max-frequency = <10000000>; 91 | 92 | pinctrl-names = "default"; 93 | pinctrl-0 = <&bone_tt3201_mcp2515_1_pins>; 94 | 95 | interrupt-parent = <&gpio4>; 96 | interrupts = <21>; 97 | 98 | mcp251x,oscillator-frequency = <16000000>; 99 | mcp251x,irq-gpios = <&gpio4 21 0>; 100 | mcp251x,stay-awake = <1>; 101 | }; 102 | 103 | mcp2515@1 { 104 | 105 | compatible = "microchip,mcp2515"; 106 | reg = <0>; /* cs0 */ 107 | mode = <0>; 108 | 109 | spi-max-frequency = <10000000>; 110 | 111 | pinctrl-names = "default"; 112 | pinctrl-0 = <&bone_tt3201_mcp2515_0_pins>; 113 | 114 | interrupt-parent = <&gpio4>; 115 | interrupts = <19>; 116 | 117 | mcp251x,oscillator-frequency = <16000000>; 118 | mcp251x,irq-gpios = <&gpio4 19 0>; 119 | mcp251x,stay-awake = <1>; 120 | mcp251x,enable-clkout = <1>; 121 | }; 122 | }; 123 | }; 124 | 125 | fragment@2 { 126 | target = <&dcan1>; 127 | __overlay__ { 128 | status = "okay"; 129 | pinctrl-names = "default"; 130 | pinctrl-0 = <&bone_tt3201_dcan1_pins>; 131 | }; 132 | }; 133 | }; 134 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/am335x-base0033.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION 3 | * 4 | * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | 11 | #include "am335x-igep0033.dtsi" 12 | 13 | / { 14 | model = "IGEP COM AM335x on AQUILA Expansion"; 15 | compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; 16 | 17 | hdmi { 18 | compatible = "ti,tilcdc,slave"; 19 | i2c = <&i2c0>; 20 | pinctrl-names = "default", "off"; 21 | pinctrl-0 = <&nxp_hdmi_pins>; 22 | pinctrl-1 = <&nxp_hdmi_off_pins>; 23 | status = "okay"; 24 | }; 25 | 26 | leds_base { 27 | pinctrl-names = "default"; 28 | pinctrl-0 = <&leds_base_pins>; 29 | 30 | compatible = "gpio-leds"; 31 | 32 | led@0 { 33 | label = "base:red:user"; 34 | gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ 35 | default-state = "off"; 36 | }; 37 | 38 | led@1 { 39 | label = "base:green:user"; 40 | gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ 41 | default-state = "off"; 42 | }; 43 | }; 44 | }; 45 | 46 | &am33xx_pinmux { 47 | nxp_hdmi_pins: pinmux_nxp_hdmi_pins { 48 | pinctrl-single,pins = < 49 | 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ 50 | 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */ 51 | 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */ 52 | 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */ 53 | 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */ 54 | 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */ 55 | 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */ 56 | 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */ 57 | 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */ 58 | 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */ 59 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */ 60 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */ 61 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */ 62 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */ 63 | 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */ 64 | 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */ 65 | 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */ 66 | 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */ 67 | 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */ 68 | 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */ 69 | 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */ 70 | >; 71 | }; 72 | nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { 73 | pinctrl-single,pins = < 74 | 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ 75 | >; 76 | }; 77 | 78 | leds_base_pins: pinmux_leds_base_pins { 79 | pinctrl-single,pins = < 80 | 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ 81 | 0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ 82 | >; 83 | }; 84 | }; 85 | 86 | &lcdc { 87 | status = "okay"; 88 | }; 89 | 90 | &i2c0 { 91 | eeprom: eeprom@50 { 92 | compatible = "at,24c256"; 93 | reg = <0x50>; 94 | }; 95 | }; 96 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/am335x-bone.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | 10 | #include "am33xx.dtsi" 11 | #include "am335x-bone-common.dtsi" 12 | 13 | &ldo3_reg { 14 | regulator-min-microvolt = <1800000>; 15 | regulator-max-microvolt = <3300000>; 16 | regulator-always-on; 17 | }; 18 | 19 | &mmc1 { 20 | vmmc-supply = <&ldo3_reg>; 21 | }; 22 | 23 | &sham { 24 | status = "okay"; 25 | }; 26 | 27 | &aes { 28 | status = "okay"; 29 | }; 30 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/am335x-boneblack.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | 10 | #include "am33xx.dtsi" 11 | #include "am335x-bone-common.dtsi" 12 | 13 | &ldo3_reg { 14 | regulator-min-microvolt = <1800000>; 15 | regulator-max-microvolt = <1800000>; 16 | regulator-always-on; 17 | }; 18 | 19 | &mmc1 { 20 | vmmc-supply = <&vmmcsd_fixed>; 21 | }; 22 | 23 | &mmc2 { 24 | vmmc-supply = <&vmmcsd_fixed>; 25 | pinctrl-names = "default"; 26 | pinctrl-0 = <&emmc_pins>; 27 | bus-width = <8>; 28 | status = "okay"; 29 | ti,vcc-aux-disable-is-sleep; 30 | }; 31 | 32 | &am33xx_pinmux { 33 | nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { 34 | pinctrl-single,pins = < 35 | 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ 36 | 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 37 | 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 38 | 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 39 | 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 40 | 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 41 | 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 42 | 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 43 | 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 44 | 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 45 | 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 46 | 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 47 | 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 48 | 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 49 | 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 50 | 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 51 | 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 52 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 53 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 54 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 55 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 56 | >; 57 | }; 58 | nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { 59 | pinctrl-single,pins = < 60 | 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ 61 | >; 62 | }; 63 | }; 64 | 65 | &lcdc { 66 | status = "okay"; 67 | }; 68 | 69 | / { 70 | hdmi { 71 | compatible = "ti,tilcdc,slave"; 72 | i2c = <&i2c0>; 73 | pinctrl-names = "default", "off"; 74 | pinctrl-0 = <&nxp_hdmi_bonelt_pins>; 75 | pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; 76 | status = "okay"; 77 | }; 78 | }; 79 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/am33xx_pwm-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "test1"; 17 | version = "00A0"; 18 | 19 | fragment@0 { 20 | target = <&epwmss0>; 21 | __overlay__ { 22 | status = "okay"; 23 | }; 24 | }; 25 | 26 | fragment@1 { 27 | target = <&ehrpwm0>; 28 | __overlay__ { 29 | status = "okay"; 30 | }; 31 | }; 32 | 33 | fragment@2 { 34 | target = <&ecap0>; 35 | __overlay__ { 36 | status = "okay"; 37 | }; 38 | }; 39 | 40 | fragment@3 { 41 | target = <&epwmss1>; 42 | __overlay__ { 43 | status = "okay"; 44 | }; 45 | }; 46 | 47 | fragment@4 { 48 | target = <&ehrpwm1>; 49 | __overlay__ { 50 | status = "okay"; 51 | }; 52 | }; 53 | 54 | fragment@5 { 55 | target = <&epwmss2>; 56 | __overlay__ { 57 | status = "okay"; 58 | }; 59 | }; 60 | 61 | fragment@6 { 62 | target = <&ehrpwm2>; 63 | __overlay__ { 64 | status = "okay"; 65 | }; 66 | }; 67 | 68 | fragment@7 { 69 | target = <&ecap2>; 70 | __overlay__ { 71 | status = "okay"; 72 | }; 73 | }; 74 | }; 75 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/am35xx-clocks.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Source for OMAP3 clock data 3 | * 4 | * Copyright (C) 2013 Texas Instruments, Inc. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | &scrm_clocks { 11 | emac_ick: emac_ick { 12 | #clock-cells = <0>; 13 | compatible = "ti,am35xx-gate-clock"; 14 | clocks = <&ipss_ick>; 15 | reg = <0x059c>; 16 | ti,bit-shift = <1>; 17 | }; 18 | 19 | emac_fck: emac_fck { 20 | #clock-cells = <0>; 21 | compatible = "ti,gate-clock"; 22 | clocks = <&rmii_ck>; 23 | reg = <0x059c>; 24 | ti,bit-shift = <9>; 25 | }; 26 | 27 | vpfe_ick: vpfe_ick { 28 | #clock-cells = <0>; 29 | compatible = "ti,am35xx-gate-clock"; 30 | clocks = <&ipss_ick>; 31 | reg = <0x059c>; 32 | ti,bit-shift = <2>; 33 | }; 34 | 35 | vpfe_fck: vpfe_fck { 36 | #clock-cells = <0>; 37 | compatible = "ti,gate-clock"; 38 | clocks = <&pclk_ck>; 39 | reg = <0x059c>; 40 | ti,bit-shift = <10>; 41 | }; 42 | 43 | hsotgusb_ick_am35xx: hsotgusb_ick_am35xx { 44 | #clock-cells = <0>; 45 | compatible = "ti,am35xx-gate-clock"; 46 | clocks = <&ipss_ick>; 47 | reg = <0x059c>; 48 | ti,bit-shift = <0>; 49 | }; 50 | 51 | hsotgusb_fck_am35xx: hsotgusb_fck_am35xx { 52 | #clock-cells = <0>; 53 | compatible = "ti,gate-clock"; 54 | clocks = <&sys_ck>; 55 | reg = <0x059c>; 56 | ti,bit-shift = <8>; 57 | }; 58 | 59 | hecc_ck: hecc_ck { 60 | #clock-cells = <0>; 61 | compatible = "ti,am35xx-gate-clock"; 62 | clocks = <&sys_ck>; 63 | reg = <0x059c>; 64 | ti,bit-shift = <3>; 65 | }; 66 | }; 67 | &cm_clocks { 68 | ipss_ick: ipss_ick { 69 | #clock-cells = <0>; 70 | compatible = "ti,am35xx-interface-clock"; 71 | clocks = <&core_l3_ick>; 72 | reg = <0x0a10>; 73 | ti,bit-shift = <4>; 74 | }; 75 | 76 | rmii_ck: rmii_ck { 77 | #clock-cells = <0>; 78 | compatible = "fixed-clock"; 79 | clock-frequency = <50000000>; 80 | }; 81 | 82 | pclk_ck: pclk_ck { 83 | #clock-cells = <0>; 84 | compatible = "fixed-clock"; 85 | clock-frequency = <27000000>; 86 | }; 87 | 88 | uart4_ick_am35xx: uart4_ick_am35xx { 89 | #clock-cells = <0>; 90 | compatible = "ti,omap3-interface-clock"; 91 | clocks = <&core_l4_ick>; 92 | reg = <0x0a10>; 93 | ti,bit-shift = <23>; 94 | }; 95 | 96 | uart4_fck_am35xx: uart4_fck_am35xx { 97 | #clock-cells = <0>; 98 | compatible = "ti,wait-gate-clock"; 99 | clocks = <&core_48m_fck>; 100 | reg = <0x0a00>; 101 | ti,bit-shift = <23>; 102 | }; 103 | }; 104 | 105 | &cm_clockdomains { 106 | core_l3_clkdm: core_l3_clkdm { 107 | compatible = "ti,clockdomain"; 108 | clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, 109 | <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, 110 | <&hecc_ck>; 111 | }; 112 | 113 | core_l4_clkdm: core_l4_clkdm { 114 | compatible = "ti,clockdomain"; 115 | clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, 116 | <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, 117 | <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, 118 | <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, 119 | <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, 120 | <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, 121 | <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, 122 | <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, 123 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 124 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 125 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, 126 | <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; 127 | }; 128 | }; 129 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_eqep0-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Nathaniel R. Lewis - http://teknoman117.wordpress.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | * 8 | * Enable eQEP0 on the Beaglebone Black - incompatible with BB White because 9 | * most of the eQEP0 pins on Beaglebone white are not broken out. 10 | */ 11 | /dts-v1/; 12 | /plugin/; 13 | 14 | / { 15 | compatible = "ti,beaglebone-black"; 16 | 17 | /* identification */ 18 | part-number = "bone_eqep0"; 19 | version = "00A0"; 20 | 21 | fragment@0 { 22 | target = <&am33xx_pinmux>; 23 | __overlay__ { 24 | pinctrl_eqep0: pinctrl_eqep0_pins { 25 | pinctrl-single,pins = < 26 | 0x1A8 0x21 /* P9_41 = GPIO3_20 = EQEP0_index, MODE1 */ 27 | 0x1AC 0x21 /* P9_25 = GPIO3_21 = EQEP0_strobe, MODE1 */ 28 | 0x1A0 0x31 /* P9_42 = GPIO3_18 = EQEP0A_in, MODE1 */ 29 | 0x1A4 0x31 /* P9_27 = GPIO3_19 = EQEP0B_in, MODE1 */ 30 | >; 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&epwmss0>; 37 | __overlay__ { 38 | status = "okay"; 39 | }; 40 | }; 41 | 42 | fragment@2 { 43 | target = <&eqep0>; 44 | __overlay__ { 45 | pinctrl-names = "default"; 46 | pinctrl-0 = <&pinctrl_eqep0>; 47 | 48 | count_mode = <0>; /* 0 - Quadrature mode, normal 90 phase offset cha & chb. 1 - Direction mode. cha input = clock, chb input = direction */ 49 | swap_inputs = <0>; /* Are channel A and channel B swapped? (0 - no, 1 - yes) */ 50 | invert_qa = <1>; /* Should we invert the channel A input? */ 51 | invert_qb = <1>; /* Should we invert the channel B input? I invert these because my encoder outputs drive transistors that pull down the pins */ 52 | invert_qi = <0>; /* Should we invert the index input? */ 53 | invert_qs = <0>; /* Should we invert the strobe input? */ 54 | 55 | status = "okay"; 56 | }; 57 | }; 58 | }; 59 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_eqep1-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Nathaniel R. Lewis - http://teknoman117.wordpress.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | * 8 | * Enable eQEP1 on the Beaglebone White and Black 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "bone_eqep1"; 18 | version = "00A0"; 19 | 20 | fragment@0 { 21 | target = <&am33xx_pinmux>; 22 | __overlay__ { 23 | pinctrl_eqep1: pinctrl_eqep1_pins { 24 | pinctrl-single,pins = < 25 | 0x0D8 0x22 /* P8_31 = GPIO0_10 = EQEP1_index, MODE2 */ 26 | 0x0DC 0x22 /* P8_32 = GPIO0_11 = EQEP1_strobe, MODE2 */ 27 | 0x0D4 0x32 /* P8_33 = GPIO0_9 = EQEP1B_in, MODE2 */ 28 | 0x0D0 0x32 /* P8_35 = GPIO0_8 = EQEP1A_in, MODE2 */ 29 | >; 30 | }; 31 | }; 32 | }; 33 | 34 | fragment@1 { 35 | target = <&epwmss1>; 36 | __overlay__ { 37 | status = "okay"; 38 | }; 39 | }; 40 | 41 | fragment@2 { 42 | target = <&eqep1>; 43 | __overlay__ { 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&pinctrl_eqep1>; 46 | 47 | count_mode = <0>; /* 0 - Quadrature mode, normal 90 phase offset cha & chb. 1 - Direction mode. cha input = clock, chb input = direction */ 48 | swap_inputs = <0>; /* Are channel A and channel B swapped? (0 - no, 1 - yes) */ 49 | invert_qa = <1>; /* Should we invert the channel A input? */ 50 | invert_qb = <1>; /* Should we invert the channel B input? I invert these because my encoder outputs drive transistors that pull down the pins */ 51 | invert_qi = <0>; /* Should we invert the index input? */ 52 | invert_qs = <0>; /* Should we invert the strobe input? */ 53 | 54 | status = "okay"; 55 | }; 56 | }; 57 | }; 58 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_eqep2-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Nathaniel R. Lewis - http://teknoman117.wordpress.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | * 8 | * Enable eQEP2 on the Beaglebone White and Black 9 | */ 10 | /dts-v1/; 11 | /plugin/; 12 | 13 | / { 14 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 15 | 16 | /* identification */ 17 | part-number = "bone_eqep2"; 18 | version = "00A0"; 19 | 20 | fragment@0 { 21 | target = <&am33xx_pinmux>; 22 | __overlay__ { 23 | pinctrl_eqep2: pinctrl_eqep2_pins { 24 | pinctrl-single,pins = < 25 | 0x0B8 0x23 /* P8_39 = GPIO2_12 = EQEP2_index, MODE3 */ 26 | 0x0BC 0x23 /* P8_40 = GPIO2_13 = EQEP2_strobe, MODE3 */ 27 | 0x0B0 0x33 /* P8_41 = GPIO2_10 = EQEP2A_in, MODE3 */ 28 | 0x0B4 0x33 /* P8_42 = GPIO2_11 = EQEP2B_in, MODE3 */ 29 | >; 30 | }; 31 | }; 32 | }; 33 | 34 | fragment@1 { 35 | target = <&epwmss2>; 36 | __overlay__ { 37 | status = "okay"; 38 | }; 39 | }; 40 | 41 | fragment@2 { 42 | target = <&eqep2>; 43 | __overlay__ { 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&pinctrl_eqep2>; 46 | 47 | count_mode = <0>; /* 0 - Quadrature mode, normal 90 phase offset cha & chb. 1 - Direction mode. cha input = clock, chb input = direction */ 48 | swap_inputs = <0>; /* Are channel A and channel B swapped? (0 - no, 1 - yes) */ 49 | invert_qa = <1>; /* Should we invert the channel A input? */ 50 | invert_qb = <1>; /* Should we invert the channel B input? I invert these because my encoder outputs drive transistors that pull down the pins */ 51 | invert_qi = <0>; /* Should we invert the index input? */ 52 | invert_qs = <0>; /* Should we invert the strobe input? */ 53 | 54 | status = "okay"; 55 | }; 56 | }; 57 | }; 58 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P8_13-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P8_13"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.13", /* pwm: ehrpwm2B */ 23 | /* the hardware IP uses */ 24 | "ehrpwm2B"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P8_13: pinmux_pwm_P8_13_pins { 30 | pinctrl-single,pins = <0x024 0x4>; /* P8_13 (ZCZ ball T10) | MODE 4 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P8_13 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm2 1 500000 1>; 41 | pwm-names = "PWM_P8_13"; 42 | 43 | pinctrl-names = "default"; 44 | pinctrl-0 = <&pwm_P8_13>; 45 | 46 | enabled = <1>; 47 | duty = <0>; 48 | status = "okay"; 49 | }; 50 | }; 51 | }; 52 | }; 53 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P8_19-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P8_19"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.19", /* pwm: ehrpwm2A */ 23 | /* the hardware IP uses */ 24 | "ehrpwm2A"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P8_19: pinmux_pwm_P8_19_pins { 30 | pinctrl-single,pins = <0x020 0x4>; /* P8_19 (ZCZ ball U10) | MODE 4 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P8_19 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm2 0 500000 1>; 41 | pwm-names = "PWM_P8_19"; 42 | 43 | pinctrl-names = "default"; 44 | pinctrl-0 = <&pwm_P8_19>; 45 | 46 | enabled = <1>; 47 | duty = <0>; 48 | status = "okay"; 49 | }; 50 | }; 51 | }; 52 | }; 53 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P8_34-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P8_34"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.34", /* pwm: ehrpwm1B */ 23 | /* the hardware IP uses */ 24 | "ehrpwm1B"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P8_34: pinmux_pwm_P8_34_pins { 30 | pinctrl-single,pins = <0x0cc 0x2>; /* P8_34 (ZCZ ball U4) | MODE 2 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P8_34 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm1 1 500000 1>; 41 | pwm-names = "PWM_P8_34"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P8_34>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P8_36-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P8_36"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.36", /* pwm: ehrpwm1A */ 23 | /* the hardware IP uses */ 24 | "ehrpwm1A"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P8_36: pinmux_pwm_P8_36_pins { 30 | pinctrl-single,pins = <0x0c8 0x2>; /* P8_36 (ZCZ ball U3) | MODE 2 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P8_36 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm1 0 500000 1>; 41 | pwm-names = "PWM_P8_36"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P8_36>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P8_45-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P8_45"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.45", /* pwm: ehrpwm2A */ 23 | /* the hardware IP uses */ 24 | "ehrpwm2A"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P8_45: pinmux_pwm_P8_45_pins { 30 | pinctrl-single,pins = <0x0a0 0x3>; /* P8_45 (ZCZ ball R1) | MODE 3 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P8_45 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm2 0 500000 1>; 41 | pwm-names = "PWM_P8_45"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P8_45>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P8_46-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P8_46"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.46", /* pwm: ehrpwm2B */ 23 | /* the hardware IP uses */ 24 | "ehrpwm2B"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P8_46: pinmux_pwm_P8_46_pins { 30 | pinctrl-single,pins = <0x0a4 0x3>; /* P8_46 (ZCZ ball R2) | MODE 3 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P8_46 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm2 1 500000 1>; 41 | pwm-names = "PWM_P8_46"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P8_46>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_14-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_14"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.14", /* pwm: ehrpwm1A */ 23 | /* the hardware IP uses */ 24 | "ehrpwm1A"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_14: pinmux_pwm_P9_14_pins { 30 | pinctrl-single,pins = <0x048 0x6>; /* P9_14 (ZCZ ball U14) | MODE 6 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_14 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm1 0 500000 1>; 41 | pwm-names = "PWM_P9_14"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_14>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_16-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_16"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.16", /* pwm: ehrpwm1B */ 23 | /* the hardware IP uses */ 24 | "ehrpwm1B"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_16: pinmux_pwm_P9_16_pins { 30 | pinctrl-single,pins = <0x04c 0x6>; /* P9_16 (ZCZ ball T14) | MODE 6 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_16 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm1 1 500000 1>; 41 | pwm-names = "PWM_P9_16"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_16>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_21-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_21"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.21", /* pwm: ehrpwm0B */ 23 | /* the hardware IP uses */ 24 | "ehrpwm0B"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_21: pinmux_pwm_P9_21_pins { 30 | pinctrl-single,pins = <0x154 0x3>; /* P9_21 (ZCZ ball B17) | MODE 3 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_21 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm0 1 500000 1>; 41 | pwm-names = "PWM_P9_21"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_21>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_22-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_22"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.22", /* pwm: ehrpwm0A */ 23 | /* the hardware IP uses */ 24 | "ehrpwm0A"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_22: pinmux_pwm_P9_22_pins { 30 | pinctrl-single,pins = <0x150 0x3>; /* P9_22 (ZCZ ball A17) | MODE 3 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_22 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm0 0 500000 1>; 41 | pwm-names = "PWM_P9_22"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_22>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_28-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_28"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.28", /* pwm: eCAP2_in_PWM2_out */ 23 | /* the hardware IP uses */ 24 | "eCAP2_in_PWM2_out"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_28: pinmux_pwm_P9_28_pins { 30 | pinctrl-single,pins = <0x19c 0x4>; /* P9_28 (ZCZ ball C12) | MODE 4 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_28 { 39 | compatible = "pwm_test"; 40 | pwms = <&ecap2 0 500000 1>; 41 | pwm-names = "PWM_P9_28"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_28>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_29-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_29"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.29", /* pwm: ehrpwm0B */ 23 | /* the hardware IP uses */ 24 | "ehrpwm0B"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_29: pinmux_pwm_P9_29_pins { 30 | pinctrl-single,pins = <0x194 0x1>; /* P9_29 (ZCZ ball B13) | MODE 1 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_29 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm0 1 500000 1>; 41 | pwm-names = "PWM_P9_29"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_29>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_31-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_31"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.31", /* pwm: ehrpwm0A */ 23 | /* the hardware IP uses */ 24 | "ehrpwm0A"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_31: pinmux_pwm_P9_31_pins { 30 | pinctrl-single,pins = <0x190 0x1>; /* P9_31 (ZCZ ball A13) | MODE 1 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_31 { 39 | compatible = "pwm_test"; 40 | pwms = <&ehrpwm0 0 500000 1>; 41 | pwm-names = "PWM_P9_31"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_31>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/bone_pwm_P9_42-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 CircuitCo 3 | * Copyright (C) 2013 Texas Instruments 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 14 | 15 | /* identification */ 16 | part-number = "bone_pwm_P9_42"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P9.42", /* pwm: eCAP0_in_PWM0_out */ 23 | /* the hardware IP uses */ 24 | "eCAP0_in_PWM0_out"; 25 | 26 | fragment@0 { 27 | target = <&am33xx_pinmux>; 28 | __overlay__ { 29 | pwm_P9_42: pinmux_pwm_P9_42_pins { 30 | pinctrl-single,pins = <0x164 0x0>; /* P9_42 (ZCZ ball C18) | MODE 0 */ 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&ocp>; 37 | __overlay__ { 38 | pwm_test_P9_42 { 39 | compatible = "pwm_test"; 40 | pwms = <&ecap0 0 500000 1>; 41 | pwm-names = "PWM_P9_42"; 42 | pinctrl-names = "default"; 43 | pinctrl-0 = <&pwm_P9_42>; 44 | enabled = <1>; 45 | duty = <0>; 46 | status = "okay"; 47 | }; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-CBB-Serial-r01.dts: -------------------------------------------------------------------------------- 1 | /* cape-CBB-Serial-r01.dts 2 | * Written by Alexander Hiam 3 | * for Logic Supply - http://logicsupply.com 4 | * Jan 28, 2014 5 | * 6 | * This is the Device Tree overlay for the CBB-Serial BeagleBone and 7 | * BeagleBone Black cape. It will enable the UART2, UART4 and DCAN1 8 | * interfaces, as well as mux GPIO1_16 for userspace control for 9 | * using software control of the RS485 receiver/driver enable. 10 | * 11 | * Note: the BeagleBone Black has GPIO1_16 tied to GPIO2_0 (which 12 | * is not exposed on the header), so this overlay muxes and controls 13 | * both pins. 14 | * 15 | * Copyright (c) 2014 - Logic Supply (http://logicsupply.com) 16 | * This program is free software; you can redistribute it and/or modify 17 | * it under the terms of the GNU General Public License version 2 as 18 | * published by the Free Software Foundation. 19 | */ 20 | 21 | /dts-v1/; 22 | /plugin/; 23 | 24 | /{ 25 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 26 | 27 | part-number = "cape-CBB-Serial"; 28 | version = "r01"; 29 | 30 | /* state the resources this cape uses */ 31 | exclusive-use = 32 | /* the pin header uses */ 33 | "P9.15", /* GPIO1_16 */ 34 | 35 | "P9.21", /* uart2_txd */ 36 | "P9.22", /* uart2_rxd */ 37 | 38 | "P9.13", /* uart4_txd */ 39 | "P9.11", /* uart4_rxd */ 40 | 41 | "P9.24", /* dcan1_rx */ 42 | "P9.26", /* dcan1_tx */ 43 | 44 | /* the hardware IP uses */ 45 | "gpio1_16", 46 | "gpio2_0", 47 | "uart2", 48 | "uart4", 49 | "dcan1"; 50 | 51 | fragment@0 { 52 | target = <&am33xx_pinmux>; 53 | __overlay__ { 54 | 55 | cbb_serial_uart2_pins: pinmux_cbb_serial_uart2_pins { 56 | pinctrl-single,pins = < 57 | 0x150 0x21 /* spi0_sclk - RX_ENABLED | MODE6 (UART2 RX) */ 58 | 0x154 0x01 /* spi0_d0 - MODE6 (UART2 TX) */ 59 | >; 60 | }; 61 | 62 | cbb_serial_uart4_pins: pinmux_cbb_serial_uart4_pins { 63 | pinctrl-single,pins = < 64 | 0x070 0x26 /* gpmc_wait0 - RX_ENABLED | MODE6 (UART4 RX) */ 65 | 0x074 0x06 /* gpmc_wpn - MODE6 (UART4 TX) */ 66 | 0x040 0x2f /* gpmc_a0 - pull disabled | MODE7 (GPIO1_16) */ 67 | 0x088 0x2f /* gpmc_csn3 - pull disabled | MODE7 (GPIO2_0) */ 68 | >; 69 | }; 70 | 71 | cbb_serial_dcan1_pins: pinmux_cbb_serial_dcan1_pins { 72 | pinctrl-single,pins = < 73 | 0x180 0x12 /* uart1_rxd - PULLUP | MODE2 (DCAN TX) */ 74 | 0x184 0x32 /* uart1_txd - RX_ENABLED | PULLUP | MODE2 (DCAN1 RX) */ 75 | >; 76 | }; 77 | }; 78 | }; 79 | 80 | fragment@1 { 81 | target = <&uart3>; 82 | __overlay__ { 83 | status = "okay"; 84 | pinctrl-names = "default"; 85 | pinctrl-0 = <&cbb_serial_uart2_pins>; 86 | }; 87 | }; 88 | 89 | fragment@2 { 90 | target = <&uart5>; 91 | __overlay__ { 92 | status = "okay"; 93 | pinctrl-names = "default"; 94 | pinctrl-0 = <&cbb_serial_uart4_pins>; 95 | }; 96 | }; 97 | 98 | fragment@3 { 99 | target = <&dcan1>; 100 | __overlay__ { 101 | status = "okay"; 102 | pinctrl-names = "default"; 103 | pinctrl-0 = <&cbb_serial_dcan1_pins>; 104 | }; 105 | }; 106 | }; 107 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-2g-emmc1.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone-black"; 13 | ti,on-baseboard; 14 | 15 | /* identification */ 16 | part-number = "*"; /* any part number */ 17 | version = "*"; /* any version */ 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.21", /* mmc1: mmc1_clk */ 23 | "P8.20", /* mmc1: mmc1_cmd */ 24 | "P8.25", /* mmc1: mmc1_dat0 */ 25 | "P8.24", /* mmc1: mmc1_dat1 */ 26 | "P8.5", /* mmc1: mmc1_dat2 */ 27 | "P8.6", /* mmc1: mmc1_dat3 */ 28 | "P8.23", /* mmc1: mmc1_dat4 */ 29 | "P8.22", /* mmc1: mmc1_dat5 */ 30 | "P8.3", /* mmc1: mmc1_dat6 */ 31 | "P8.4", /* mmc1: mmc1_dat7 */ 32 | /* the hardware IP uses */ 33 | "mmc1", 34 | /* the reset pin */ 35 | "eMMC_RSTn"; 36 | 37 | fragment@0 { 38 | target = <&am33xx_pinmux>; 39 | __overlay__ { 40 | emmc2_pins: pinmux_emmc2_pins { 41 | pinctrl-single,pins = < 42 | 0x80 0x32 /* gpmc_csn1.mmc1_clk, INPUT_PULLUP | MODE2 */ 43 | 0x84 0x32 /* gpmc_csn2.mmc1_cmd, INPUT_PULLUP | MODE2 */ 44 | 0x00 0x31 /* gpmc_ad0.mmc1_dat0, INPUT_PULLUP | MODE1 */ 45 | 0x04 0x31 /* gpmc_ad1.mmc1_dat1, INPUT_PULLUP | MODE1 */ 46 | 0x08 0x31 /* gpmc_ad2.mmc1_dat2, INPUT_PULLUP | MODE1 */ 47 | 0x0c 0x31 /* gpmc_ad3.mmc1_dat3, INPUT_PULLUP | MODE1 */ 48 | 0x10 0x31 /* gpmc_ad4.mmc1_dat4, INPUT_PULLUP | MODE1 */ 49 | 0x14 0x31 /* gpmc_ad5.mmc1_dat5, INPUT_PULLUP | MODE1 */ 50 | 0x18 0x31 /* gpmc_ad6.mmc1_dat6, INPUT_PULLUP | MODE1 */ 51 | 0x1c 0x31 /* gpmc_ad7.mmc1_dat7, INPUT_PULLUP | MODE1 */ 52 | >; 53 | }; 54 | }; 55 | }; 56 | fragment@1 { 57 | target = <&mmc2>; 58 | __overlay__ { 59 | pinctrl-names = "default"; 60 | pinctrl-0 = <&emmc2_pins>; /* wrong numbering */ 61 | vmmc-supply = <&ldo3_reg>; 62 | bus-width = <8>; 63 | ti,non-removable; 64 | status = "okay"; 65 | ti,vcc-aux-disable-is-sleep; 66 | 67 | reset = <&rstctl 0 0>; 68 | reset-names = "eMMC_RSTn"; 69 | }; 70 | }; 71 | }; 72 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-adafruit-lcd-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | /* 12 | * Pin assignments 13 | * 14 | * Module Connector 15 | * LITE <- P8.19 16 | * MISO -> P9.29 17 | * SCK <- P9.31 18 | * MOSI <- P9.30 19 | * TFT_CS <- P9.28 20 | * CARD_CS <- NC 21 | * D/C <- P9.25 22 | * RESET <- P9.27 23 | * 24 | */ 25 | 26 | / { 27 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 28 | part-number = "BB-BONE-TFT-01"; 29 | version = "00A0"; 30 | 31 | /* state the resources this cape uses */ 32 | exclusive-use = 33 | /* the pin header uses */ 34 | "P8.19", /* bl: ehrpwm2A */ 35 | "P9.27", /* lcd: gpio3_19 */ 36 | "P9.25", /* lcd: gpio3_21 */ 37 | "P9.31", /* spi: spi1_sclk */ 38 | "P9.29", /* spi: spi1_d0 */ 39 | "P9.30", /* spi: spi1_d1 */ 40 | "P9.28", /* spi: spi1_cs0 */ 41 | /* the hardware IP uses */ 42 | "gpio3_19", 43 | "gpio3_21", 44 | "ehrpwm2A", 45 | "spi1"; 46 | 47 | fragment@0 { 48 | target = <&am33xx_pinmux>; 49 | __overlay__ { 50 | pwm_backlight_pins: pinmux_pwm_backlight_pins { 51 | pinctrl-single,pins = < 52 | 0x020 0x4 /* gpmc_ad8.gpio0_22 | MODE4 */ 53 | >; 54 | }; 55 | 56 | bone_adafruit_lcd_pins: pinmux_bone_adafruit_lcd_pins { 57 | pinctrl-single,pins = < 58 | 0x1a4 0x17 /* mcasp0_fsr.gpio3_19, OUTPUT_PULLUP | MODE7 */ 59 | 0x1ac 0x17 /* mcasp0_ahclkx.gpio3_21, OUTPUT_PULLUP | MODE7 */ 60 | >; 61 | }; 62 | 63 | bone_adafruit_spi1_pins: pinmux_adafruit_spi1_pins { 64 | pinctrl-single,pins = < 65 | 0x190 0x33 /* mcasp0_aclkx.spi1_sclk, INPUT_PULLUP | MODE3 */ 66 | 0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */ 67 | 0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */ 68 | 0x19c 0x13 /* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE3 */ 69 | >; 70 | }; 71 | }; 72 | }; 73 | 74 | fragment@1 { 75 | target = <&epwmss2>; 76 | __overlay__ { 77 | status = "okay"; 78 | }; 79 | }; 80 | 81 | fragment@2 { 82 | target = <&ehrpwm2>; 83 | __overlay__ { 84 | status = "okay"; 85 | }; 86 | }; 87 | 88 | 89 | fragment@3 { 90 | target = <&spi1>; 91 | 92 | __overlay__ { 93 | #address-cells = <1>; 94 | #size-cells = <0>; 95 | 96 | status = "okay"; 97 | pinctrl-names = "default"; 98 | pinctrl-0 = <&bone_adafruit_spi1_pins>; 99 | 100 | lcd@0 { 101 | #address-cells = <1>; 102 | #size-cells = <0>; 103 | 104 | compatible = "adafruit,tft-lcd-1.8-red", "sitronix,st7735"; 105 | reg = <0>; 106 | 107 | spi-max-frequency = <8000000>; 108 | spi-cpol; 109 | spi-cpha; 110 | 111 | pinctrl-names = "default"; 112 | pinctrl-0 = <&bone_adafruit_lcd_pins>; 113 | 114 | st7735-rst = <&gpio4 19 0>; 115 | st7735-dc = <&gpio4 21 0>; 116 | }; 117 | }; 118 | }; 119 | 120 | fragment@4 { 121 | target = <&ocp>; 122 | 123 | /* avoid stupid warning */ 124 | #address-cells = <1>; 125 | #size-cells = <1>; 126 | 127 | __overlay__ { 128 | adafruit-tft-backlight { 129 | compatible = "pwm-backlight"; 130 | pinctrl-names = "default"; 131 | pinctrl-0 = <&pwm_backlight_pins>; 132 | 133 | pwms = <&ehrpwm2 0 500000 0>; 134 | 135 | pwm-names = "st7735fb"; 136 | brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; 137 | default-brightness-level = <101>; /* index to the array above */ 138 | }; 139 | }; 140 | }; 141 | }; 142 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-argus-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 David Lambert - Breakaway Systems LLC> 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | * 8 | * This has been, and continues to be very confusing to me!!! 9 | * 10 | */ 11 | /dts-v1/; 12 | /plugin/; 13 | 14 | / { 15 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 16 | 17 | /* identification */ 18 | part-number = "argus-ups"; 19 | version = "00A0"; 20 | 21 | /* state the resources this cape uses */ 22 | exclusive-use = 23 | /* the pin header usage */ 24 | "P8.11", /* Request from UPS */ 25 | "P8.17", /* Acknowledge to UPS */ 26 | "P8.18", /* Watchdog to UPS */ 27 | "P8.7", /* LED 1 Green */ 28 | "P8.8", /* LED 1 Red */ 29 | "P8.9", /* LED 2 Green */ 30 | "P8.10", /* LED 2 Red */ 31 | "P9.41", /* General Output #1 */ 32 | "P9.42", /* General Output #2 */ 33 | /* the hardware IP usage - note that gpios here need to be numbered 0-n */ 34 | /* whereas in the fragments they are numbered 1-(n+1)????? */ 35 | "gpio0_30", 36 | "gpio0_5", 37 | "gpio0_4", 38 | "gpio2_2", /* LED 1 Green */ 39 | "gpio2_3", /* LED 1 Red */ 40 | "gpio2_5", /* LED 2 Green */ 41 | "gpio2_4", /* LED 2 Red */ 42 | "gpio0_20", /* General Output #1 */ 43 | "gpio0_7"; /* General Output #2 */ 44 | 45 | fragment@0 { /* Deals with the pinmux */ 46 | target = <&am33xx_pinmux>; 47 | __overlay__ { 48 | argus_ups_pins: pinmux_argus_ups_pins { /* Set up pinmux */ 49 | pinctrl-single,pins = < 50 | 0x070 0x27 /* gpmc_wait0.gpio0_30, OMAP_MUX_MODE7 | INPUT_PULLDOWN */ 51 | 0x15c 0x17 /* spi0_cs0.gpio0_5, OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 52 | 0x158 0x17 /* spi0_d1.gpio0_4, OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 53 | 0x090 0x17 /* gpmc_advn_ale.gpio_2 , OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 54 | 0x094 0x17 /* gpmc_oen_ren.gpio2_3 , OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 55 | 0x09c 0x17 /* gpmc_ben0_cle.gpio2_5 , OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 56 | 0x098 0x17 /* gpmc_gpmc_wen.gpio2_4 , OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 57 | 0x1b4 0x17 /* xdma_event_intr1.gpio0_20 , OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 58 | 0x164 0x17 /* ecap0_in_pwm0_out.gpio0_7 , OMAP_MUX_MODE7 | OUTPUT_PULLUP */ 59 | >; 60 | }; 61 | }; 62 | }; 63 | 64 | fragment@1 { 65 | target = <&ocp>; 66 | __overlay__ { 67 | argus-ups { 68 | compatible = "argus-ups"; 69 | status = "okay"; 70 | 71 | pinctrl-names = "default"; 72 | pinctrl-0 = <&argus_ups_pins>; /* Refer to previous label */ 73 | /* This section communicates the gpio numbers to the driver module */ 74 | /* Note that gpio controllers appear to be numbered from 1-n here rather than 0-(n-1)????? */ 75 | gpios = <&gpio1 30 0>, /* Request */ 76 | <&gpio1 5 0>, /* Acknowledge */ 77 | <&gpio1 4 0>, /* Watchdog */ 78 | <&gpio3 2 0>, /* LED 1 Green */ 79 | <&gpio3 3 0>, /* LED 1 Red */ 80 | <&gpio3 5 0>, /* LED 2 Green */ 81 | <&gpio3 4 0>, /* LED 2 Red */ 82 | <&gpio1 20 0>, /* General Output #1 */ 83 | <&gpio1 7 0>; /* General Output #2 */ 84 | debug = <0>; 85 | shutdown = <1>; 86 | 87 | }; 88 | }; 89 | }; 90 | }; 91 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-dvi-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-DVID-01"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.14", /* led: gpio1_18 */ 22 | "P9.16", /* led: gpio1_19 */ 23 | "P8.4", /* lcd: gpio1_7 */ 24 | "P8.45", /* lcd: lcd_data0 */ 25 | "P8.46", /* lcd: lcd_data1 */ 26 | "P8.43", /* lcd: lcd_data2 */ 27 | "P8.44", /* lcd: lcd_data3 */ 28 | "P8.41", /* lcd: lcd_data4 */ 29 | "P8.42", /* lcd: lcd_data5 */ 30 | "P8.39", /* lcd: lcd_data6 */ 31 | "P8.40", /* lcd: lcd_data7 */ 32 | "P8.37", /* lcd: lcd_data8 */ 33 | "P8.38", /* lcd: lcd_data9 */ 34 | "P8.36", /* lcd: lcd_data10 */ 35 | "P8.34", /* lcd: lcd_data11 */ 36 | "P8.35", /* lcd: lcd_data12 */ 37 | "P8.33", /* lcd: lcd_data13 */ 38 | "P8.31", /* lcd: lcd_data14 */ 39 | "P8.32", /* lcd: lcd_data15 */ 40 | "P8.27", /* lcd: lcd_vsync */ 41 | "P8.29", /* lcd: lcd_hsync */ 42 | "P8.28", /* lcd: lcd_pclk */ 43 | "P8.30", /* lcd: lcd_ac_bias_en */ 44 | /* the hardware IP uses */ 45 | "gpio1_18", 46 | "gpio1_19", 47 | "gpio1_7", 48 | "lcd"; 49 | 50 | fragment@0 { 51 | target = <&am33xx_pinmux>; 52 | __overlay__ { 53 | 54 | bone_dvi_cape_led_pins: pinmux_bone_dvi_cape_led_pins { 55 | pinctrl-single,pins = < 56 | 0x48 0x07 /* gpmc_a2.gpio1_18, OUTPUT | MODE7 */ 57 | 0x4c 0x07 /* gpmc_a3.gpio1_19, OUTPUT | MODE7 */ 58 | >; 59 | }; 60 | 61 | bone_dvi_cape_dvi_00A0_pins: pinmux_bone_dvi_cape_dvi_00A0_pins { 62 | pinctrl-single,pins = < 63 | 0x1c 0x07 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 - DVIPDn */ 64 | 65 | 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 66 | 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 67 | 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 68 | 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 69 | 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 70 | 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 71 | 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 72 | 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 73 | 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 74 | 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 75 | 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 76 | 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 77 | 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 78 | 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 79 | 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 80 | 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 81 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 82 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 83 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 84 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 85 | >; 86 | }; 87 | }; 88 | }; 89 | 90 | fragment@1 { 91 | target = <&ocp>; 92 | __overlay__ { 93 | 94 | /* avoid stupid warning */ 95 | #address-cells = <1>; 96 | #size-cells = <1>; 97 | 98 | gpio-leds-cape-dvi { 99 | compatible = "gpio-leds"; 100 | pinctrl-names = "default"; 101 | pinctrl-0 = <&bone_dvi_cape_led_pins>; 102 | 103 | dvi-led0 { 104 | label = "dvi:green:usr0"; 105 | gpios = <&gpio2 18 0>; 106 | linux,default-trigger = "heartbeat"; 107 | default-state = "off"; 108 | }; 109 | 110 | dvi-led1 { 111 | label = "dvi:green:usr1"; 112 | gpios = <&gpio2 19 0>; 113 | linux,default-trigger = "mmc0"; 114 | default-state = "off"; 115 | }; 116 | }; 117 | 118 | /* use the DVI panel now */ 119 | panel { 120 | compatible = "tilcdc,tfp410"; 121 | pinctrl-names = "default"; 122 | pinctrl-0 = <&bone_dvi_cape_dvi_00A0_pins>; 123 | ti,power-gpio = <&gpio1 7 0x0>; 124 | i2c = <&i2c2>; 125 | }; 126 | 127 | fb { 128 | compatible = "ti,am33xx-tilcdc"; 129 | reg = <0x4830e000 0x1000>; 130 | interrupt-parent = <&intc>; 131 | interrupts = <36>; 132 | ti,hwmods = "lcdc"; 133 | }; 134 | 135 | }; 136 | }; 137 | }; 138 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-dvi-00A2.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-DVID-01"; 16 | version = "00A3", "00A2", "A2"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.14", /* led: gpio1_18 */ 22 | "P9.16", /* led: gpio1_19 */ 23 | "P8.4", /* lcd: gpio1_7 */ 24 | "P8.45", /* lcd: lcd_data0 */ 25 | "P8.46", /* lcd: lcd_data1 */ 26 | "P8.43", /* lcd: lcd_data2 */ 27 | "P8.44", /* lcd: lcd_data3 */ 28 | "P8.41", /* lcd: lcd_data4 */ 29 | "P8.42", /* lcd: lcd_data5 */ 30 | "P8.39", /* lcd: lcd_data6 */ 31 | "P8.40", /* lcd: lcd_data7 */ 32 | "P8.37", /* lcd: lcd_data8 */ 33 | "P8.38", /* lcd: lcd_data9 */ 34 | "P8.36", /* lcd: lcd_data10 */ 35 | "P8.34", /* lcd: lcd_data11 */ 36 | "P8.35", /* lcd: lcd_data12 */ 37 | "P8.33", /* lcd: lcd_data13 */ 38 | "P8.31", /* lcd: lcd_data14 */ 39 | "P8.32", /* lcd: lcd_data15 */ 40 | "P8.27", /* lcd: lcd_vsync */ 41 | "P8.29", /* lcd: lcd_hsync */ 42 | "P8.28", /* lcd: lcd_pclk */ 43 | "P8.30", /* lcd: lcd_ac_bias_en */ 44 | /* the hardware IP uses */ 45 | "gpio1_18", 46 | "gpio1_19", 47 | "gpio1_7", 48 | "lcd"; 49 | 50 | fragment@0 { 51 | target = <&am33xx_pinmux>; 52 | __overlay__ { 53 | 54 | bone_dvi_cape_led_pins: pinmux_bone_dvi_cape_led_pins { 55 | pinctrl-single,pins = < 56 | 0x48 0x07 /* gpmc_a2.gpio1_18, OUTPUT | MODE7 */ 57 | 0x4c 0x07 /* gpmc_a3.gpio1_19, OUTPUT | MODE7 */ 58 | >; 59 | }; 60 | 61 | bone_dvi_cape_dvi_00A2_pins: pinmux_bone_dvi_cape_dvi_00A2_pins { 62 | pinctrl-single,pins = < 63 | 0x1c 0x07 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 - DVIPDn */ 64 | 65 | 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 66 | 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 67 | 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 68 | 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 69 | 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 70 | 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 71 | 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 72 | 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 73 | 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 74 | 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 75 | 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 76 | 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 77 | 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 78 | 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 79 | 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 80 | 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 81 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 82 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 83 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 84 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 85 | >; 86 | }; 87 | }; 88 | }; 89 | 90 | fragment@1 { 91 | target = <&ocp>; 92 | __overlay__ { 93 | 94 | /* avoid stupid warning */ 95 | #address-cells = <1>; 96 | #size-cells = <1>; 97 | 98 | gpio-leds-cape-dvi { 99 | compatible = "gpio-leds"; 100 | pinctrl-names = "default"; 101 | pinctrl-0 = <&bone_dvi_cape_led_pins>; 102 | 103 | dvi-led0 { 104 | label = "dvi:green:usr0"; 105 | gpios = <&gpio2 18 0>; 106 | linux,default-trigger = "heartbeat"; 107 | default-state = "off"; 108 | }; 109 | 110 | dvi-led1 { 111 | label = "dvi:green:usr1"; 112 | gpios = <&gpio2 19 0>; 113 | linux,default-trigger = "mmc0"; 114 | default-state = "off"; 115 | }; 116 | }; 117 | 118 | /* use the DVI panel now */ 119 | panel { 120 | compatible = "tilcdc,tfp410"; 121 | pinctrl-names = "default"; 122 | pinctrl-0 = <&bone_dvi_cape_dvi_00A2_pins>; 123 | ti,power-gpio = <&gpio1 31 0x0>; 124 | i2c = <&i2c2>; 125 | }; 126 | 127 | fb { 128 | compatible = "ti,am33xx-tilcdc"; 129 | reg = <0x4830e000 0x1000>; 130 | interrupt-parent = <&intc>; 131 | interrupts = <36>; 132 | ti,hwmods = "lcdc"; 133 | }; 134 | 135 | }; 136 | }; 137 | }; 138 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-geiger-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Pantelis Antoniou 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-GEIGER"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P8.29", /* led: gpio2_23 */ 22 | "P8.30", /* led: gpio2_25 */ 23 | "P9.14", /* geiger: ehrpwm1A */ 24 | "P9.28", /* geiger: gpio3_17 */ 25 | "P9.36", /* geiger: AIN5 */ 26 | /* the hardware IP uses */ 27 | "gpio2_23", 28 | "gpio2_25", 29 | "gpio3_17", 30 | "ehrpwm1A", 31 | "tscadc"; 32 | 33 | fragment@0 { 34 | target = <&am33xx_pinmux>; 35 | __overlay__ { 36 | 37 | bone_geiger_cape_led_pins: pinmux_bone_geiger_cape_led_pins { 38 | pinctrl-single,pins = < 39 | 0xe4 0x07 /* lcd_hsync.gpio2_23, OUTPUT | MODE7 */ 40 | 0xec 0x07 /* lcd_ac_bias_en.gpio2_25, OUTPUT | MODE7 */ 41 | >; 42 | }; 43 | 44 | bone_geiger_cape_pins: pinmux_bone_geiger_cape_pins { 45 | pinctrl-single,pins = < 46 | 0x48 0x06 /* gpmc_a2.ehrpwm1a, OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT */ 47 | /* 0x19c 0x34 */ /* mcasp0_ahclkr.eCAP2_in_PWM2_out, OMAP_MUX_MODE4 | INPUT_PULLUP */ 48 | 0x19c 0x37 /* mcasp0_ahclkr.gpio3_17, OMAP_MUX_MODE7 | INPUT_PULLUP */ 49 | >; 50 | }; 51 | }; 52 | }; 53 | 54 | fragment@1 { 55 | target = <&epwmss1>; 56 | __overlay__ { 57 | status = "okay"; 58 | }; 59 | }; 60 | 61 | fragment@2 { 62 | target = <&ehrpwm1>; 63 | __overlay__ { 64 | status = "okay"; 65 | }; 66 | }; 67 | 68 | fragment@3 { 69 | target = <&ocp>; 70 | __overlay__ { 71 | 72 | /* avoid stupid warning */ 73 | #address-cells = <1>; 74 | #size-cells = <1>; 75 | 76 | gpio-leds-cape-geiger { 77 | compatible = "gpio-leds"; 78 | pinctrl-names = "default"; 79 | pinctrl-0 = <&bone_geiger_cape_led_pins>; 80 | 81 | geiger-led0 { 82 | label = "geiger:green:usr0"; 83 | gpios = <&gpio3 23 0>; 84 | linux,default-trigger = "geiger-run"; 85 | default-state = "off"; 86 | }; 87 | 88 | geiger-led1 { 89 | label = "geiger:red:usr1"; 90 | gpios = <&gpio3 25 0>; 91 | linux,default-trigger = "geiger-event"; 92 | default-state = "off"; 93 | }; 94 | 95 | }; 96 | 97 | tscadc { 98 | compatible = "ti,ti-tscadc"; 99 | reg = <0x44e0d000 0x1000>; 100 | 101 | interrupt-parent = <&intc>; 102 | interrupts = <16>; 103 | ti,hwmods = "adc_tsc"; 104 | status = "okay"; 105 | 106 | adc { 107 | ti,adc-channels = <0 1 2 3 4 5 6 7>; 108 | }; 109 | }; 110 | 111 | bone-cape-geiger { 112 | compatible = "bone-cape-geiger"; 113 | status = "okay"; 114 | 115 | pinctrl-names = "default"; 116 | pinctrl-0 = <&bone_geiger_cape_pins>; 117 | 118 | pwms = <&ehrpwm1 0 500000 0>; 119 | pwm-names = "bone-geiger-cape"; 120 | 121 | pwm-frequency = <20000>; /* 20KHz */ 122 | pwm-duty-cycle = <60>; /* 60% */ 123 | 124 | event-blink-delay = <30>; /* 30ms */ 125 | 126 | gpios = <&gpio4 17 0>; /* pulse */ 127 | 128 | vsense-name = "AIN5"; /* analog vsense */ 129 | vsense-scale = <37325>; /* scaling */ 130 | }; 131 | }; 132 | }; 133 | }; 134 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-hexy-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * Copyright (C) 2013 Koen Kooi 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | /* 13 | * Pin assignments 14 | * 15 | * Module Connector 16 | * LITE <- P8.19 17 | * MISO -> P9.29 18 | * SCK <- P9.31 19 | * MOSI <- P9.30 20 | * TFT_CS <- P9.28 21 | * CARD_CS <- NC 22 | * D/C <- P9.25 23 | * RESET <- P9.27 24 | * 25 | */ 26 | 27 | / { 28 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 29 | part-number = "BB-BONE-HEXY-01"; 30 | version = "00A0"; 31 | 32 | fragment@0 { 33 | target = <&am33xx_pinmux>; 34 | __overlay__ { 35 | pwm_backlight_pins: pinmux_pwm_backlight_pins { 36 | pinctrl-single,pins = < 37 | 0x020 0x4 /* gpmc_ad8.gpio0_22 | MODE4 */ 38 | >; 39 | }; 40 | 41 | bone_hexy_lcd_pins: pinmux_bone_hexy_lcd_pins { 42 | pinctrl-single,pins = < 43 | 0x1a4 0x17 /* mcasp0_fsr.gpio3_19, OUTPUT_PULLUP | MODE7 */ 44 | 0x1ac 0x17 /* mcasp0_ahclkx.gpio3_21, OUTPUT_PULLUP | MODE7 */ 45 | >; 46 | }; 47 | 48 | bone_hexy_spi1_pins: pinmux_adafruit_spi1_pins { 49 | pinctrl-single,pins = < 50 | 0x190 0x33 /* mcasp0_aclkx.spi1_sclk, INPUT_PULLUP | MODE3 */ 51 | 0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */ 52 | 0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */ 53 | 0x19c 0x13 /* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE3 */ 54 | >; 55 | }; 56 | }; 57 | }; 58 | 59 | fragment@1 { 60 | target = <&epwmss2>; 61 | __overlay__ { 62 | status = "okay"; 63 | }; 64 | }; 65 | 66 | fragment@2 { 67 | target = <&ehrpwm2>; 68 | __overlay__ { 69 | status = "okay"; 70 | }; 71 | }; 72 | 73 | 74 | fragment@3 { 75 | target = <&spi1>; 76 | 77 | __overlay__ { 78 | #address-cells = <1>; 79 | #size-cells = <0>; 80 | 81 | status = "okay"; 82 | pinctrl-names = "default"; 83 | pinctrl-0 = <&bone_hexy_spi1_pins>; 84 | 85 | lcd@0 { 86 | #address-cells = <1>; 87 | #size-cells = <0>; 88 | 89 | compatible = "adafruit,tft-lcd-1.8-green", "sitronix,st7735"; 90 | reg = <0>; 91 | 92 | spi-max-frequency = <16000000>; 93 | spi-cpol; 94 | spi-cpha; 95 | 96 | pinctrl-names = "default"; 97 | pinctrl-0 = <&bone_hexy_lcd_pins>; 98 | 99 | st7735-rst = <&gpio4 19 0>; 100 | st7735-dc = <&gpio4 21 0>; 101 | }; 102 | }; 103 | }; 104 | 105 | fragment@4 { 106 | target = <&ocp>; 107 | 108 | /* avoid stupid warning */ 109 | #address-cells = <1>; 110 | #size-cells = <1>; 111 | 112 | __overlay__ { 113 | hexy_display { 114 | compatible = "pwm-backlight"; 115 | pinctrl-names = "default"; 116 | pinctrl-0 = <&pwm_backlight_pins>; 117 | 118 | pwms = <&ehrpwm2 0 500000 0>; 119 | 120 | pwm-names = "st7735fb"; 121 | brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; 122 | default-brightness-level = <101>; /* index to the array above */ 123 | }; 124 | }; 125 | }; 126 | 127 | fragment@5 { 128 | target = <&i2c2>; 129 | 130 | __overlay__ { 131 | /* needed to avoid gripping by DTC */ 132 | #address-cells = <1>; 133 | #size-cells = <0>; 134 | 135 | lsm303dlhc_magn@1e { 136 | compatible = "st,lsm303dlhc_magn"; 137 | reg = <0x1E>; 138 | }; 139 | 140 | lsm303dlh_accel@1e { 141 | compatible = "st,lsm303dlhc_accel"; 142 | reg = <0x19>; 143 | }; 144 | 145 | vcnl4000@13 { 146 | compatible = "vishay,vcnl4000"; 147 | reg = <0x13>; 148 | }; 149 | 150 | ssd1306: oled@3c { 151 | compatible = "solomon,ssd1306fb-i2c"; 152 | reg = <0x3c>; 153 | reset-gpios = <&gpio2 17 0>; 154 | solomon,height = <32>; 155 | solomon,width = <128>; 156 | solomon,page-offset = <0>; 157 | }; 158 | }; 159 | }; 160 | 161 | fragment@6 { 162 | target = <&ocp>; 163 | __overlay__ { 164 | /* avoid stupid warning */ 165 | #address-cells = <1>; 166 | #size-cells = <1>; 167 | 168 | tscadc { 169 | compatible = "ti,ti-tscadc"; 170 | reg = <0x44e0d000 0x1000>; 171 | 172 | interrupt-parent = <&intc>; 173 | interrupts = <16>; 174 | ti,hwmods = "adc_tsc"; 175 | status = "okay"; 176 | 177 | adc { 178 | ti,adc-channels = <0 1 2 3 4 5 6 7>; 179 | }; 180 | }; 181 | 182 | test_helper: helper { 183 | compatible = "bone-iio-helper"; 184 | vsense-name = "AIN0", "AIN1", "AIN2", "AIN3", "AIN4", "AIN5", "AIN6", "AIN7"; 185 | vsense-scale = <100 100 100 100 100 100 100 100>; 186 | status = "okay"; 187 | }; 188 | }; 189 | }; 190 | }; 191 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-ibb-00A0.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 6 | part-number = "cape-bone-ibb"; 7 | version = "00A0"; 8 | exclusive-use = "P9.24", "P9.26", "uart1", 9 | "P9.21", "P9.22", "uart2", 10 | "P9.13", "P9.11", "uart4", 11 | "P9.15"; 12 | 13 | fragment@0 { 14 | target = <&am33xx_pinmux>; 15 | __overlay__ { 16 | bb_uart1_pins: pinmux_bb_uart1_pins { 17 | pinctrl-single,pins = <0x180 0x20 0x184 0x00>; 18 | }; 19 | bb_uart2_pins: pinmux_bb_uart2_pins { 20 | pinctrl-single,pins = <0x150 0x21 0x154 0x01>; 21 | }; 22 | bb_uart4_pins: pinmux_bb_uart4_pins { 23 | pinctrl-single,pins = <0x70 0x26 0x74 0x06>; 24 | }; 25 | rtc_int_pin: pinmux_rtc_int_pin { 26 | pinctrl-single,pins = <0x40 0x37>; /* GPIO1_16 gpmc_a0 */ 27 | }; 28 | }; 29 | }; 30 | 31 | fragment@1 { 32 | target = <&uart2>; /* really uart1 */ 33 | __overlay__ { 34 | status = "okay"; 35 | pinctrl-names = "default"; 36 | pinctrl-0 = <&bb_uart1_pins>; 37 | }; 38 | }; 39 | 40 | fragment@2 { 41 | target = <&uart3>; /* really uart2 */ 42 | __overlay__ { 43 | status = "okay"; 44 | pinctrl-names = "default"; 45 | pinctrl-0 = <&bb_uart2_pins>; 46 | }; 47 | }; 48 | 49 | fragment@3 { 50 | target = <&uart5>; /* really uart4 */ 51 | __overlay__ { 52 | status = "okay"; 53 | pinctrl-names = "default"; 54 | pinctrl-0 = <&bb_uart4_pins>; 55 | }; 56 | }; 57 | 58 | fragment@4 { 59 | target = <&i2c2>; 60 | __overlay__ { 61 | /* shut up DTC warnings */ 62 | #address-cells = <1>; 63 | #size-cells = <0>; 64 | 65 | /* DS1307 RTC module */ 66 | rtc@68 { 67 | compatible = "dallas,ds3231"; 68 | reg = <0x68>; 69 | }; 70 | 71 | /* PCA9546 I2C multiplexer */ 72 | i2cmux@70 { 73 | #address-cells = <1>; 74 | #size-cells = <0>; 75 | compatible = "nxp,pca9545"; 76 | reg = <0x70>; 77 | 78 | i2c@0 { 79 | #address-cells = <1>; 80 | #size-cells = <0>; 81 | compatible = "nxp,pca954x-bus"; 82 | reg = <0>; 83 | deselect_on_exit; 84 | }; 85 | i2c@1 { 86 | #address-cells = <1>; 87 | #size-cells = <0>; 88 | compatible = "nxp,pca954x-bus"; 89 | reg = <1>; 90 | deselect_on_exit; 91 | }; 92 | i2c@2 { 93 | #address-cells = <1>; 94 | #size-cells = <0>; 95 | compatible = "nxp,pca954x-bus"; 96 | reg = <2>; 97 | deselect_on_exit; 98 | }; 99 | i2c@3 { 100 | #address-cells = <1>; 101 | #size-cells = <0>; 102 | compatible = "nxp,pca954x-bus"; 103 | reg = <3>; 104 | deselect_on_exit; 105 | }; 106 | }; 107 | }; 108 | }; 109 | 110 | fragment@5 { 111 | target = <&ocp>; 112 | __overlay__ { 113 | gpio_keys { 114 | compatible = "gpio-keys"; 115 | pinctrl-names = "default"; 116 | pinctrl-0 = <&rtc_int_pin>; 117 | int_x1 { 118 | label = "RTC-INT"; 119 | debounce_interval = <50>; 120 | linux,code = <1>; 121 | gpios = <&gpio2 16 0x5>; 122 | gpio-key,wakeup; 123 | }; 124 | }; 125 | }; 126 | }; 127 | 128 | }; 129 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-iio-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "iio-test"; 16 | 17 | /* state the resources this cape uses */ 18 | exclusive-use = 19 | /* the pin header uses */ 20 | "P9.39", /* AIN0 */ 21 | "P9.40", /* AIN1 */ 22 | "P9.37", /* AIN2 */ 23 | "P9.38", /* AIN3 */ 24 | "P9.33", /* AIN4 */ 25 | "P9.36", /* AIN5 */ 26 | "P9.35", /* AIN6 */ 27 | /* the hardware IP uses */ 28 | "tscadc"; 29 | 30 | fragment@0 { 31 | target = <&ocp>; 32 | __overlay__ { 33 | /* avoid stupid warning */ 34 | #address-cells = <1>; 35 | #size-cells = <1>; 36 | 37 | tscadc { 38 | compatible = "ti,ti-tscadc"; 39 | reg = <0x44e0d000 0x1000>; 40 | 41 | interrupt-parent = <&intc>; 42 | interrupts = <16>; 43 | ti,hwmods = "adc_tsc"; 44 | status = "okay"; 45 | 46 | adc { 47 | ti,adc-channels = <0 1 2 3 4 5 6 7>; 48 | }; 49 | }; 50 | 51 | test_helper: helper { 52 | compatible = "bone-iio-helper"; 53 | vsense-name = "AIN0", "AIN1", "AIN2", "AIN3", "AIN4", "AIN5", "AIN6", "AIN7"; 54 | vsense-scale = <100 100 100 100 100 100 100 100>; 55 | status = "okay"; 56 | }; 57 | }; 58 | }; 59 | }; 60 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-mrf24j40-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Alan Ott 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | /dts-v1/; 10 | /plugin/; 11 | 12 | / { 13 | compatible = "ti,beaglebone", "ti-beaglebone-black"; 14 | 15 | /* Identification */ 16 | part-number = "BB-BONE-MRF24J40"; 17 | version = "00A0"; 18 | 19 | /* state the resources this cape uses */ 20 | exclusive-use = 21 | /* the pin header uses */ 22 | "P8.11", /* gpio1_13 */ 23 | "P8.16", /* gpio1_14 */ 24 | "P8.26", /* gpio1_29 */ 25 | "P9.31", /* spi1_sclk */ 26 | "P9.29", /* spi1_d0 */ 27 | "P9.30", /* spi1_d1 */ 28 | "P9.28", /* spi1_cs0 */ 29 | /* the hardware IP uses */ 30 | "gpio1_13", 31 | "gpio1_14", 32 | "gpio1_29", 33 | "spi1"; 34 | 35 | fragment@0 { 36 | target = <&am33xx_pinmux>; 37 | __overlay__ { 38 | mrf24j40_cape_pins: pinmux_mrf24j40_cape_pins { 39 | pinctrl-single,pins = < 40 | /* Pinmux comes from TRM section 41 | 9.3.1: CONTROL_MODULE Regusters. */ 42 | 43 | /* so use GPIO1_13 (rst), GPIO1_14 (wake), then SPI1_CS0 (CS), and GPIO1_29 (INT) */ 44 | 0x34 0x37 /* gpmc_ad13.gpio1_13 input, pull up, mode 7 */ 45 | 0x38 0x2f /* gpmc_ad14.gpio1_14 input, no pull, mode 7 */ 46 | 0x7c 0x2f /* gpmc_csn0.gpio1_29 input, no pull, mode 7 */ 47 | >; 48 | }; 49 | bone_mrf24j40_spi1_pins: pinmux_bone_mrf24j40_spi1_pins { 50 | pinctrl-single,pins = < 51 | 0x190 0x33 /* mcasp0_aclkx.spi1_sclk, RX_ENABLED | PULLUP | MODE3 */ 52 | 0x194 0x33 /* mcasp0_fsx.spi1_d0, RX_ENABLED | PULLUP | MODE3 */ 53 | 0x198 0x33 /* mcasp0_axr0.spi1_d1, RX_ENABLED | PULLUP | MODE3 */ 54 | 0x19c 0x33 /* mcasp0_ahclkr.spi1_cs0, RX_ENABLED | PULLUP | MODE3 */ 55 | >; 56 | }; 57 | }; 58 | }; 59 | 60 | 61 | fragment@1 { 62 | target = <&spi1>; 63 | 64 | __overlay__ { 65 | /* needed to avoid DTC warnings */ 66 | #address-cells = <1>; 67 | #size-cells = <0>; 68 | 69 | status = "okay"; 70 | pinctrl-names = "default"; 71 | pinctrl-0 = <&bone_mrf24j40_spi1_pins>; 72 | 73 | mrf24j40@0 { 74 | compatible = "mrf24j40ma"; 75 | reg = <0>; /* CHIPSEL */ 76 | spi-max-frequency = <20000000>; 77 | mode = <0>; 78 | pinctrl-names = "default"; 79 | pinctrl-0 = <&mrf24j40_cape_pins>; 80 | 81 | interrupt-parent = <&gpio2>; 82 | interrupts = <29>; 83 | 84 | //mrf24j40-wake = <&gpio4 19>; 85 | //mrf24j40-reset = ; 86 | }; 87 | }; 88 | }; 89 | }; 90 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-nixie-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Matt Ranostay 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "BB-BONE-NIXIE"; 16 | version = "00A0"; 17 | 18 | /* state the resources this cape uses */ 19 | exclusive-use = 20 | /* the pin header uses */ 21 | "P9.25", /* gpio3_21 */ 22 | "P8.45", /* ehrpwm2A */ 23 | "P8.46", /* ehrpwm2B */ 24 | "P9.31", /* pr1_pru0_pru_r30_0 */ 25 | "P9.29", /* pr1_pru0_pru_r30_1 */ 26 | "P9.27", /* pr1_pru0_pru_r30_5 */ 27 | /* the hardware IP uses */ 28 | "gpio3_21", 29 | "ehrpwm2A", "ehrpwm2B", 30 | "pru"; 31 | 32 | fragment@0 { 33 | target = <&am33xx_pinmux>; 34 | __overlay__ { 35 | 36 | bone_nixie_cape_led_pins: pinmux_bone_nixie_cape_led_pins { 37 | pinctrl-single,pins = < 38 | 0x1ac 0x07 /* mcasp0_ahclkx.gpio3_21, MODE7 */ 39 | >; 40 | }; 41 | 42 | bone_nixie_cape_pins: pinmux_bone_nixie_cape_pins { 43 | pinctrl-single,pins = < 44 | 0x0a0 0x03 /* lcd_data0.gpio2_6 | MODE3 */ 45 | 0x0a4 0x03 /* lcd_data1.gpio2_7 | MODE3 */ 46 | >; 47 | }; 48 | 49 | pruss_pins: pinmux_pruss_pins { 50 | pinctrl-single,pins = < 51 | 0x190 0x05 /* mcasp0_aclkx.pr1_pru0_pru_r30_0, MODE5 | DATA */ 52 | 0x194 0x05 /* mcasp0_fsx.pr1_pru0_pru_r30_1, MODE5 | LATCH */ 53 | 0x1a4 0x05 /* mcasp0_fsr.pr1_pru1_pru_r30_5, MODE5 | CLK */ 54 | >; 55 | }; 56 | }; 57 | }; 58 | 59 | fragment@2 { 60 | target = <&epwmss2>; 61 | __overlay__ { 62 | status = "okay"; 63 | }; 64 | }; 65 | 66 | fragment@1 { 67 | target = <&ehrpwm2>; 68 | __overlay__ { 69 | status = "okay"; 70 | }; 71 | }; 72 | 73 | fragment@3 { 74 | target = <&ocp>; 75 | __overlay__ { 76 | 77 | /* avoid stupid warning */ 78 | #address-cells = <1>; 79 | #size-cells = <1>; 80 | 81 | gpio-leds-cape-nixie { 82 | compatible = "gpio-leds"; 83 | pinctrl-names = "default"; 84 | pinctrl-0 = <&bone_nixie_cape_led_pins>; 85 | 86 | nixie-led0 { 87 | label = "nixie:green:usr0"; 88 | gpios = <&gpio4 21 0>; 89 | linux,default-trigger = "nixie-run"; 90 | default-state = "off"; 91 | }; 92 | }; 93 | 94 | bone-cape-nixie { 95 | compatible = "bone-cape-nixie"; 96 | status = "okay"; 97 | 98 | pinctrl-names = "default"; 99 | pinctrl-0 = <&bone_nixie_cape_pins>; 100 | 101 | pwms = <&ehrpwm2 0 500000 0>; 102 | pwm-names = "bone-nixie-cape"; 103 | 104 | pwm-frequency = <9250>; /* 9.250KHz */ 105 | pwm-duty-cycle = <35>; /* 35% */ 106 | 107 | default-brightness = <35>; /* 35% */ 108 | }; 109 | }; 110 | }; 111 | 112 | fragment@4 { 113 | target = <&pruss>; 114 | __overlay__ { 115 | status = "okay"; 116 | 117 | pinctrl-names = "default"; 118 | pinctrl-0 = <&pruss_pins>; 119 | }; 120 | }; 121 | }; 122 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-pinmux-test-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | /* identification */ 15 | part-number = "pinctrl-test"; 16 | 17 | fragment@0 { 18 | target = <&am33xx_pinmux>; 19 | __overlay__ { 20 | pinctrl_test_7: pinctrl_test_7_pins { 21 | pinctrl-single,pins = < 22 | 0x164 0x07 /* P9_42 muxRegOffset, OUTPUT | MODE7 */ 23 | >; 24 | }; 25 | }; 26 | }; 27 | 28 | fragment@1 { 29 | target = <&ocp>; 30 | __overlay__ { 31 | /* avoid stupid warning */ 32 | #address-cells = <1>; 33 | #size-cells = <1>; 34 | 35 | test_helper: helper { 36 | compatible = "bone-pinmux-helper"; 37 | pinctrl-names = "default"; 38 | pinctrl-0 = <&pinctrl_test_7>; 39 | status = "okay"; 40 | }; 41 | }; 42 | }; 43 | }; 44 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-weather-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | part-number = "BB-BONE-WTHR-01"; 15 | version = "00A0"; 16 | 17 | /* state the resources this cape uses */ 18 | exclusive-use = 19 | /* the pin header uses */ 20 | "P8.6", /* gpio1_3 */ 21 | /* the hardware IP uses */ 22 | "gpio1_3"; 23 | 24 | fragment@0 { 25 | target = <&am33xx_pinmux>; 26 | __overlay__ { 27 | weather_cape_w1_pins: pinmux_weather_cape_w1_pins { 28 | pinctrl-single,pins = < 29 | 0x0c 0x37 /* gpmc_ad3.gpio1_3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE7 - w1-gpio */ 30 | >; 31 | }; 32 | }; 33 | }; 34 | 35 | fragment@1 { 36 | target = <&i2c2>; 37 | 38 | __overlay__ { 39 | /* needed to avoid gripping by DTC */ 40 | #address-cells = <1>; 41 | #size-cells = <0>; 42 | 43 | /* Ambient light sensor */ 44 | tsl2550@39 { 45 | compatible = "tsl,tsl2550"; 46 | reg = <0x39>; 47 | }; 48 | 49 | /* Humidity Sensor */ 50 | sht21@40 { 51 | compatible = "sensiron,sht21"; 52 | reg = <0x40>; 53 | }; 54 | 55 | /* Barometric pressure sensor */ 56 | bmp085@77 { 57 | compatible = "bosch,bmp085"; 58 | reg = <0x77>; 59 | }; 60 | }; 61 | }; 62 | 63 | fragment@2 { 64 | target = <&ocp>; 65 | __overlay__ { 66 | onewire@0 { 67 | compatible = "w1-gpio"; 68 | pinctrl-names = "default"; 69 | pinctrl-0 = <&weather_cape_w1_pins>; 70 | status = "okay"; 71 | 72 | gpios = <&gpio2 3 0>; 73 | }; 74 | }; 75 | }; 76 | }; 77 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-bone-weather-00B0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 13 | 14 | part-number = "BB-BONE-WTHR-01"; 15 | version = "00B0"; 16 | 17 | /* state the resources this cape uses */ 18 | fragment@0 { 19 | target = <&i2c2>; 20 | 21 | __overlay__ { 22 | /* needed to avoid gripping by DTC */ 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | 26 | /* Ambient light sensor */ 27 | tsl2550@39 { 28 | compatible = "tsl,tsl2550"; 29 | reg = <0x39>; 30 | }; 31 | 32 | /* Humidity Sensor */ 33 | htu21@40 { 34 | compatible = "meas-spec,htu21"; 35 | reg = <0x40>; 36 | }; 37 | 38 | /* Barometric pressure sensor */ 39 | bmp085@77 { 40 | compatible = "bosch,bmp085"; 41 | reg = <0x77>; 42 | }; 43 | }; 44 | }; 45 | 46 | }; 47 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-boneblack-hdmi-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone-black"; 13 | part-number = "BB-BONELT-HDMI"; 14 | version = "00A0"; 15 | 16 | /* state the resources this cape uses */ 17 | exclusive-use = 18 | /* the pin header uses */ 19 | "P9.25", /* mcasp0: mcasp0_ahclkx */ 20 | "P9.28", /* mcasp0: mcasp0_axr2 */ 21 | "P9.29", /* mcasp0: mcasp0_fsx */ 22 | "P9.31", /* mcasp0: mcasp0_aclkx */ 23 | "P8.45", /* lcd: lcd_data0 */ 24 | "P8.46", /* lcd: lcd_data1 */ 25 | "P8.43", /* lcd: lcd_data2 */ 26 | "P8.44", /* lcd: lcd_data3 */ 27 | "P8.41", /* lcd: lcd_data4 */ 28 | "P8.42", /* lcd: lcd_data5 */ 29 | "P8.39", /* lcd: lcd_data6 */ 30 | "P8.40", /* lcd: lcd_data7 */ 31 | "P8.37", /* lcd: lcd_data8 */ 32 | "P8.38", /* lcd: lcd_data9 */ 33 | "P8.36", /* lcd: lcd_data10 */ 34 | "P8.34", /* lcd: lcd_data11 */ 35 | "P8.35", /* lcd: lcd_data12 */ 36 | "P8.33", /* lcd: lcd_data13 */ 37 | "P8.31", /* lcd: lcd_data14 */ 38 | "P8.32", /* lcd: lcd_data15 */ 39 | "P8.27", /* lcd: lcd_vsync */ 40 | "P8.29", /* lcd: lcd_hsync */ 41 | "P8.28", /* lcd: lcd_pclk */ 42 | "P8.30", /* lcd: lcd_ac_bias_en */ 43 | /* the hardware IP uses */ 44 | "gpio1_27", 45 | "mcasp0", 46 | "lcd"; 47 | 48 | fragment@0 { 49 | target = <&am33xx_pinmux>; 50 | __overlay__ { 51 | nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { 52 | pinctrl-single,pins = < 53 | 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ 54 | 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 55 | 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 56 | 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 57 | 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 58 | 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 59 | 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 60 | 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 61 | 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 62 | 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 63 | 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 64 | 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 65 | 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 66 | 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 67 | 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 68 | 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 69 | 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 70 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 71 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 72 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 73 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 74 | >; 75 | }; 76 | nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { 77 | pinctrl-single,pins = < 78 | 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ 79 | >; 80 | }; 81 | 82 | mcasp0_pins: mcasp0_pins { 83 | pinctrl-single,pins = < 84 | 0x1ac 0x30 /* mcasp0_ahclkx, MODE0 | INPUT */ 85 | 0x19c 0x02 /* mcasp0_ahclkr, */ 86 | 0x194 0x10 /* mcasp0_fsx, MODE0 | OUTPUT */ 87 | 0x190 0x00 /* mcasp0_aclkr.mcasp0_aclkx, MODE0 | OUTPUT_PULLDOWN */ 88 | 0x1a8 0x1f /* mcasp0_axr1 GPIO1_27 | OUTPUT | PULLUP */ 89 | >; 90 | }; 91 | }; 92 | }; 93 | 94 | fragment@2 { 95 | target = <&ocp>; 96 | __overlay__ { 97 | 98 | /* avoid stupid warning */ 99 | #address-cells = <1>; 100 | #size-cells = <1>; 101 | 102 | nxptda: nxptda@0 { 103 | compatible = "nxp,nxptda"; 104 | status = "okay"; 105 | }; 106 | 107 | hdmi { 108 | compatible = "tilcdc,slave"; 109 | i2c = <&i2c0>; 110 | pinctrl-names = "default", "off"; 111 | pinctrl-0 = <&nxp_hdmi_bonelt_pins>; 112 | pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; 113 | 114 | panel-info { 115 | bpp = <16>; 116 | ac-bias = <255>; 117 | ac-bias-intrpt = <0>; 118 | dma-burst-sz = <16>; 119 | fdd = <16>; 120 | sync-edge = <1>; 121 | sync-ctrl = <1>; 122 | raster-order = <0>; 123 | fifo-th = <0>; 124 | invert-pxl-clk; 125 | }; 126 | }; 127 | 128 | fb { 129 | compatible = "ti,am33xx-tilcdc"; 130 | reg = <0x4830e000 0x1000>; 131 | interrupt-parent = <&intc>; 132 | interrupts = <36>; 133 | ti,hwmods = "lcdc"; 134 | ti,allow-non-reduced-blanking-modes; 135 | }; 136 | 137 | }; 138 | }; 139 | 140 | fragment@3 { 141 | target = <&mcasp0>; 142 | __overlay__ { 143 | pinctrl-names = "default"; 144 | pinctrl-0 = <&mcasp0_pins>; 145 | 146 | status = "okay"; 147 | 148 | op-mode = <0>; /* MCASP_IIS_MODE */ 149 | tdm-slots = <2>; 150 | num-serializer = <16>; 151 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 152 | 0 0 1 0 153 | 0 0 0 0 154 | 0 0 0 0 155 | 0 0 0 0 156 | >; 157 | tx-num-evt = <1>; 158 | rx-num-evt = <1>; 159 | }; 160 | }; 161 | 162 | fragment@4 { 163 | target = <&ocp>; 164 | __overlay__ { 165 | sound { 166 | compatible = "ti,am33xx-beaglebone-black"; 167 | ti,model = "TI BeagleBone Black"; 168 | ti,audio-codec = <&nxptda>; 169 | ti,mcasp-controller = <&mcasp0>; 170 | ti,codec-clock-rate = <2457600>; 171 | mcasp_clock_enable = <&gpio2 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ 172 | }; 173 | }; 174 | 175 | }; 176 | 177 | }; 178 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/cape-boneblack-hdmin-00A0.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | /plugin/; 10 | 11 | / { 12 | compatible = "ti,beaglebone-black"; 13 | part-number = "BB-BONELT-HDMIN"; /* No audio */ 14 | version = "00A0"; 15 | 16 | /* state the resources this cape uses */ 17 | exclusive-use = 18 | /* the pin header uses */ 19 | "P8.45", /* lcd: lcd_data0 */ 20 | "P8.46", /* lcd: lcd_data1 */ 21 | "P8.43", /* lcd: lcd_data2 */ 22 | "P8.44", /* lcd: lcd_data3 */ 23 | "P8.41", /* lcd: lcd_data4 */ 24 | "P8.42", /* lcd: lcd_data5 */ 25 | "P8.39", /* lcd: lcd_data6 */ 26 | "P8.40", /* lcd: lcd_data7 */ 27 | "P8.37", /* lcd: lcd_data8 */ 28 | "P8.38", /* lcd: lcd_data9 */ 29 | "P8.36", /* lcd: lcd_data10 */ 30 | "P8.34", /* lcd: lcd_data11 */ 31 | "P8.35", /* lcd: lcd_data12 */ 32 | "P8.33", /* lcd: lcd_data13 */ 33 | "P8.31", /* lcd: lcd_data14 */ 34 | "P8.32", /* lcd: lcd_data15 */ 35 | "P8.27", /* lcd: lcd_vsync */ 36 | "P8.29", /* lcd: lcd_hsync */ 37 | "P8.28", /* lcd: lcd_pclk */ 38 | "P8.30", /* lcd: lcd_ac_bias_en */ 39 | /* the hardware IP uses */ 40 | "gpio1_27", 41 | "lcd"; 42 | 43 | fragment@0 { 44 | target = <&am33xx_pinmux>; 45 | __overlay__ { 46 | nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { 47 | pinctrl-single,pins = < 48 | 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ 49 | 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 50 | 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 51 | 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 52 | 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 53 | 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 54 | 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 55 | 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 56 | 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 57 | 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 58 | 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 59 | 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 60 | 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 61 | 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 62 | 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 63 | 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 64 | 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ 65 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 66 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 67 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 68 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ 69 | >; 70 | }; 71 | nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { 72 | pinctrl-single,pins = < 73 | 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ 74 | >; 75 | }; 76 | }; 77 | }; 78 | 79 | fragment@2 { 80 | target = <&ocp>; 81 | __overlay__ { 82 | 83 | /* avoid stupid warning */ 84 | #address-cells = <1>; 85 | #size-cells = <1>; 86 | 87 | nxptda: nxptda@0 { 88 | compatible = "nxp,nxptda"; 89 | status = "okay"; 90 | }; 91 | 92 | hdmi { 93 | compatible = "tilcdc,slave"; 94 | i2c = <&i2c0>; 95 | pinctrl-names = "default", "off"; 96 | pinctrl-0 = <&nxp_hdmi_bonelt_pins>; 97 | pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; 98 | 99 | panel-info { 100 | bpp = <16>; 101 | ac-bias = <255>; 102 | ac-bias-intrpt = <0>; 103 | dma-burst-sz = <16>; 104 | fdd = <16>; 105 | sync-edge = <1>; 106 | sync-ctrl = <1>; 107 | raster-order = <0>; 108 | fifo-th = <0>; 109 | invert-pxl-clk; 110 | }; 111 | }; 112 | 113 | fb { 114 | compatible = "ti,am33xx-tilcdc"; 115 | reg = <0x4830e000 0x1000>; 116 | interrupt-parent = <&intc>; 117 | interrupts = <36>; 118 | ti,hwmods = "lcdc"; 119 | ti,allow-non-reduced-blanking-modes; 120 | ti,allow-non-audio-modes; 121 | }; 122 | 123 | }; 124 | }; 125 | }; 126 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/include/dt-bindings: -------------------------------------------------------------------------------- 1 | ../../../../../include/dt-bindings -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Common file for GPMC connected smsc911x on omaps 3 | * 4 | * Note that the board specifc DTS file needs to specify 5 | * ranges, pinctrl, reg, interrupt parent and interrupts. 6 | */ 7 | 8 | / { 9 | vddvario: regulator-vddvario { 10 | compatible = "regulator-fixed"; 11 | regulator-name = "vddvario"; 12 | regulator-always-on; 13 | }; 14 | 15 | vdd33a: regulator-vdd33a { 16 | compatible = "regulator-fixed"; 17 | regulator-name = "vdd33a"; 18 | regulator-always-on; 19 | }; 20 | }; 21 | 22 | &gpmc { 23 | ethernet@gpmc { 24 | compatible = "smsc,lan9221", "smsc,lan9115"; 25 | bank-width = <2>; 26 | gpmc,mux-add-data; 27 | gpmc,cs-on-ns = <1>; 28 | gpmc,cs-rd-off-ns = <180>; 29 | gpmc,cs-wr-off-ns = <180>; 30 | gpmc,adv-rd-off-ns = <18>; 31 | gpmc,adv-wr-off-ns = <48>; 32 | gpmc,oe-on-ns = <54>; 33 | gpmc,oe-off-ns = <168>; 34 | gpmc,we-on-ns = <54>; 35 | gpmc,we-off-ns = <168>; 36 | gpmc,rd-cycle-ns = <186>; 37 | gpmc,wr-cycle-ns = <186>; 38 | gpmc,access-ns = <144>; 39 | gpmc,page-burst-access-ns = <24>; 40 | gpmc,bus-turnaround-ns = <90>; 41 | gpmc,cycle2cycle-delay-ns = <90>; 42 | gpmc,cycle2cycle-samecsen; 43 | gpmc,cycle2cycle-diffcsen; 44 | vddvario-supply = <&vddvario>; 45 | vdd33a-supply = <&vdd33a>; 46 | reg-io-width = <4>; 47 | smsc,save-mac-address; 48 | }; 49 | }; 50 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Common file for GPMC connected smsc9221 on omaps 3 | * 4 | * Compared to smsc911x, smsc9221 (and others like smsc9217 5 | * or smsc 9218) has faster timings, leading to higher 6 | * bandwidth. 7 | * 8 | * Note that the board specifc DTS file needs to specify 9 | * ranges, pinctrl, reg, interrupt parent and interrupts. 10 | */ 11 | 12 | / { 13 | vddvario: regulator-vddvario { 14 | compatible = "regulator-fixed"; 15 | regulator-name = "vddvario"; 16 | regulator-always-on; 17 | }; 18 | 19 | vdd33a: regulator-vdd33a { 20 | compatible = "regulator-fixed"; 21 | regulator-name = "vdd33a"; 22 | regulator-always-on; 23 | }; 24 | }; 25 | 26 | &gpmc { 27 | ethernet@gpmc { 28 | compatible = "smsc,lan9221","smsc,lan9115"; 29 | bank-width = <2>; 30 | 31 | gpmc,mux-add-data; 32 | gpmc,cs-on-ns = <0>; 33 | gpmc,cs-rd-off-ns = <42>; 34 | gpmc,cs-wr-off-ns = <36>; 35 | gpmc,adv-on-ns = <6>; 36 | gpmc,adv-rd-off-ns = <12>; 37 | gpmc,adv-wr-off-ns = <12>; 38 | gpmc,oe-on-ns = <0>; 39 | gpmc,oe-off-ns = <42>; 40 | gpmc,we-on-ns = <0>; 41 | gpmc,we-off-ns = <36>; 42 | gpmc,rd-cycle-ns = <60>; 43 | gpmc,wr-cycle-ns = <54>; 44 | gpmc,access-ns = <36>; 45 | gpmc,page-burst-access-ns = <0>; 46 | gpmc,bus-turnaround-ns = <0>; 47 | gpmc,cycle2cycle-delay-ns = <0>; 48 | gpmc,wr-data-mux-bus-ns = <18>; 49 | gpmc,wr-access-ns = <42>; 50 | gpmc,cycle2cycle-samecsen; 51 | gpmc,cycle2cycle-diffcsen; 52 | 53 | vddvario-supply = <&vddvario>; 54 | vdd33a-supply = <&vdd33a>; 55 | reg-io-width = <4>; 56 | smsc,save-mac-address; 57 | }; 58 | }; 59 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap3-beagle-xm-ab.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | #include "omap3-beagle-xm.dts" 10 | 11 | / { 12 | /* HS USB Port 2 Power enable was inverted with the xM C */ 13 | hsusb2_power: hsusb2_power_reg { 14 | enable-active-high; 15 | }; 16 | }; 17 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap3430es1-clocks.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Source for OMAP3430 ES1 clock data 3 | * 4 | * Copyright (C) 2013 Texas Instruments, Inc. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | &cm_clocks { 11 | gfx_l3_ck: gfx_l3_ck { 12 | #clock-cells = <0>; 13 | compatible = "ti,wait-gate-clock"; 14 | clocks = <&l3_ick>; 15 | reg = <0x0b10>; 16 | ti,bit-shift = <0>; 17 | }; 18 | 19 | gfx_l3_fck: gfx_l3_fck { 20 | #clock-cells = <0>; 21 | compatible = "ti,divider-clock"; 22 | clocks = <&l3_ick>; 23 | ti,max-div = <7>; 24 | reg = <0x0b40>; 25 | ti,index-starts-at-one; 26 | }; 27 | 28 | gfx_l3_ick: gfx_l3_ick { 29 | #clock-cells = <0>; 30 | compatible = "fixed-factor-clock"; 31 | clocks = <&gfx_l3_ck>; 32 | clock-mult = <1>; 33 | clock-div = <1>; 34 | }; 35 | 36 | gfx_cg1_ck: gfx_cg1_ck { 37 | #clock-cells = <0>; 38 | compatible = "ti,wait-gate-clock"; 39 | clocks = <&gfx_l3_fck>; 40 | reg = <0x0b00>; 41 | ti,bit-shift = <1>; 42 | }; 43 | 44 | gfx_cg2_ck: gfx_cg2_ck { 45 | #clock-cells = <0>; 46 | compatible = "ti,wait-gate-clock"; 47 | clocks = <&gfx_l3_fck>; 48 | reg = <0x0b00>; 49 | ti,bit-shift = <2>; 50 | }; 51 | 52 | d2d_26m_fck: d2d_26m_fck { 53 | #clock-cells = <0>; 54 | compatible = "ti,wait-gate-clock"; 55 | clocks = <&sys_ck>; 56 | reg = <0x0a00>; 57 | ti,bit-shift = <3>; 58 | }; 59 | 60 | fshostusb_fck: fshostusb_fck { 61 | #clock-cells = <0>; 62 | compatible = "ti,wait-gate-clock"; 63 | clocks = <&core_48m_fck>; 64 | reg = <0x0a00>; 65 | ti,bit-shift = <5>; 66 | }; 67 | 68 | ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 { 69 | #clock-cells = <0>; 70 | compatible = "ti,composite-no-wait-gate-clock"; 71 | clocks = <&corex2_fck>; 72 | ti,bit-shift = <0>; 73 | reg = <0x0a00>; 74 | }; 75 | 76 | ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 { 77 | #clock-cells = <0>; 78 | compatible = "ti,composite-divider-clock"; 79 | clocks = <&corex2_fck>; 80 | ti,bit-shift = <8>; 81 | reg = <0x0a40>; 82 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 83 | }; 84 | 85 | ssi_ssr_fck: ssi_ssr_fck_3430es1 { 86 | #clock-cells = <0>; 87 | compatible = "ti,composite-clock"; 88 | clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; 89 | }; 90 | 91 | ssi_sst_fck: ssi_sst_fck_3430es1 { 92 | #clock-cells = <0>; 93 | compatible = "fixed-factor-clock"; 94 | clocks = <&ssi_ssr_fck>; 95 | clock-mult = <1>; 96 | clock-div = <2>; 97 | }; 98 | 99 | hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 { 100 | #clock-cells = <0>; 101 | compatible = "ti,omap3-no-wait-interface-clock"; 102 | clocks = <&core_l3_ick>; 103 | reg = <0x0a10>; 104 | ti,bit-shift = <4>; 105 | }; 106 | 107 | fac_ick: fac_ick { 108 | #clock-cells = <0>; 109 | compatible = "ti,omap3-interface-clock"; 110 | clocks = <&core_l4_ick>; 111 | reg = <0x0a10>; 112 | ti,bit-shift = <8>; 113 | }; 114 | 115 | ssi_l4_ick: ssi_l4_ick { 116 | #clock-cells = <0>; 117 | compatible = "fixed-factor-clock"; 118 | clocks = <&l4_ick>; 119 | clock-mult = <1>; 120 | clock-div = <1>; 121 | }; 122 | 123 | ssi_ick: ssi_ick_3430es1 { 124 | #clock-cells = <0>; 125 | compatible = "ti,omap3-no-wait-interface-clock"; 126 | clocks = <&ssi_l4_ick>; 127 | reg = <0x0a10>; 128 | ti,bit-shift = <0>; 129 | }; 130 | 131 | usb_l4_gate_ick: usb_l4_gate_ick { 132 | #clock-cells = <0>; 133 | compatible = "ti,composite-interface-clock"; 134 | clocks = <&l4_ick>; 135 | ti,bit-shift = <5>; 136 | reg = <0x0a10>; 137 | }; 138 | 139 | usb_l4_div_ick: usb_l4_div_ick { 140 | #clock-cells = <0>; 141 | compatible = "ti,composite-divider-clock"; 142 | clocks = <&l4_ick>; 143 | ti,bit-shift = <4>; 144 | ti,max-div = <1>; 145 | reg = <0x0a40>; 146 | ti,index-starts-at-one; 147 | }; 148 | 149 | usb_l4_ick: usb_l4_ick { 150 | #clock-cells = <0>; 151 | compatible = "ti,composite-clock"; 152 | clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; 153 | }; 154 | 155 | dss1_alwon_fck: dss1_alwon_fck_3430es1 { 156 | #clock-cells = <0>; 157 | compatible = "ti,gate-clock"; 158 | clocks = <&dpll4_m4x2_ck>; 159 | ti,bit-shift = <0>; 160 | reg = <0x0e00>; 161 | ti,set-rate-parent; 162 | }; 163 | 164 | dss_ick: dss_ick_3430es1 { 165 | #clock-cells = <0>; 166 | compatible = "ti,omap3-no-wait-interface-clock"; 167 | clocks = <&l4_ick>; 168 | reg = <0x0e10>; 169 | ti,bit-shift = <0>; 170 | }; 171 | }; 172 | 173 | &cm_clockdomains { 174 | core_l3_clkdm: core_l3_clkdm { 175 | compatible = "ti,clockdomain"; 176 | clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; 177 | }; 178 | 179 | gfx_3430es1_clkdm: gfx_3430es1_clkdm { 180 | compatible = "ti,clockdomain"; 181 | clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; 182 | }; 183 | 184 | dss_clkdm: dss_clkdm { 185 | compatible = "ti,clockdomain"; 186 | clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, 187 | <&dss1_alwon_fck>, <&dss_ick>; 188 | }; 189 | 190 | d2d_clkdm: d2d_clkdm { 191 | compatible = "ti,clockdomain"; 192 | clocks = <&d2d_26m_fck>; 193 | }; 194 | 195 | core_l4_clkdm: core_l4_clkdm { 196 | compatible = "ti,clockdomain"; 197 | clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, 198 | <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, 199 | <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, 200 | <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, 201 | <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, 202 | <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, 203 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 204 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 205 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, 206 | <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; 207 | }; 208 | }; 209 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap34xx-hs.dtsi: -------------------------------------------------------------------------------- 1 | /* Disabled modules for secure omaps */ 2 | 3 | #include "omap34xx.dtsi" 4 | 5 | /* Secure omaps have some devices inaccessible depending on the firmware */ 6 | &aes { 7 | status = "disabled"; 8 | }; 9 | 10 | &sham { 11 | status = "disabled"; 12 | }; 13 | 14 | &timer12 { 15 | status = "disabled"; 16 | }; 17 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap34xx.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Source for OMAP34xx/OMAP35xx SoC 3 | * 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5 | * 6 | * This file is licensed under the terms of the GNU General Public License 7 | * version 2. This program is licensed "as is" without any warranty of any 8 | * kind, whether express or implied. 9 | */ 10 | 11 | #include "omap3.dtsi" 12 | 13 | / { 14 | cpus { 15 | cpu@0 { 16 | /* OMAP343x/OMAP35xx variants OPP1-5 */ 17 | operating-points = < 18 | /* kHz uV */ 19 | 125000 975000 20 | 250000 1075000 21 | 500000 1200000 22 | 550000 1270000 23 | 600000 1350000 24 | >; 25 | clock-latency = <300000>; /* From legacy driver */ 26 | }; 27 | }; 28 | 29 | ocp { 30 | omap3_pmx_core2: pinmux@480025d8 { 31 | compatible = "ti,omap3-padconf", "pinctrl-single"; 32 | reg = <0x480025d8 0x24>; 33 | #address-cells = <1>; 34 | #size-cells = <0>; 35 | #interrupt-cells = <1>; 36 | interrupt-controller; 37 | pinctrl-single,register-width = <16>; 38 | pinctrl-single,function-mask = <0xff1f>; 39 | }; 40 | }; 41 | }; 42 | 43 | /include/ "omap34xx-omap36xx-clocks.dtsi" 44 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" 45 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 46 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap36xx-clocks.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Source for OMAP36xx clock data 3 | * 4 | * Copyright (C) 2013 Texas Instruments, Inc. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | &cm_clocks { 11 | dpll4_ck: dpll4_ck { 12 | #clock-cells = <0>; 13 | compatible = "ti,omap3-dpll-per-j-type-clock"; 14 | clocks = <&sys_ck>, <&sys_ck>; 15 | reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; 16 | }; 17 | 18 | dpll4_m5x2_ck: dpll4_m5x2_ck { 19 | #clock-cells = <0>; 20 | compatible = "ti,hsdiv-gate-clock"; 21 | clocks = <&dpll4_m5x2_mul_ck>; 22 | ti,bit-shift = <0x1e>; 23 | reg = <0x0d00>; 24 | ti,set-rate-parent; 25 | ti,set-bit-to-disable; 26 | }; 27 | 28 | dpll4_m2x2_ck: dpll4_m2x2_ck { 29 | #clock-cells = <0>; 30 | compatible = "ti,hsdiv-gate-clock"; 31 | clocks = <&dpll4_m2x2_mul_ck>; 32 | ti,bit-shift = <0x1b>; 33 | reg = <0x0d00>; 34 | ti,set-bit-to-disable; 35 | }; 36 | 37 | dpll3_m3x2_ck: dpll3_m3x2_ck { 38 | #clock-cells = <0>; 39 | compatible = "ti,hsdiv-gate-clock"; 40 | clocks = <&dpll3_m3x2_mul_ck>; 41 | ti,bit-shift = <0xc>; 42 | reg = <0x0d00>; 43 | ti,set-bit-to-disable; 44 | }; 45 | 46 | dpll4_m3x2_ck: dpll4_m3x2_ck { 47 | #clock-cells = <0>; 48 | compatible = "ti,hsdiv-gate-clock"; 49 | clocks = <&dpll4_m3x2_mul_ck>; 50 | ti,bit-shift = <0x1c>; 51 | reg = <0x0d00>; 52 | ti,set-bit-to-disable; 53 | }; 54 | 55 | dpll4_m6x2_ck: dpll4_m6x2_ck { 56 | #clock-cells = <0>; 57 | compatible = "ti,hsdiv-gate-clock"; 58 | clocks = <&dpll4_m6x2_mul_ck>; 59 | ti,bit-shift = <0x1f>; 60 | reg = <0x0d00>; 61 | ti,set-bit-to-disable; 62 | }; 63 | 64 | uart4_fck: uart4_fck { 65 | #clock-cells = <0>; 66 | compatible = "ti,wait-gate-clock"; 67 | clocks = <&per_48m_fck>; 68 | reg = <0x1000>; 69 | ti,bit-shift = <18>; 70 | }; 71 | }; 72 | 73 | &dpll4_m2x2_mul_ck { 74 | clock-mult = <1>; 75 | }; 76 | 77 | &dpll4_m3x2_mul_ck { 78 | clock-mult = <1>; 79 | }; 80 | 81 | &dpll4_m4x2_mul_ck { 82 | ti,clock-mult = <1>; 83 | }; 84 | 85 | &dpll4_m5x2_mul_ck { 86 | clock-mult = <1>; 87 | }; 88 | 89 | &dpll4_m6x2_mul_ck { 90 | clock-mult = <1>; 91 | }; 92 | 93 | &cm_clockdomains { 94 | dpll4_clkdm: dpll4_clkdm { 95 | compatible = "ti,clockdomain"; 96 | clocks = <&dpll4_ck>; 97 | }; 98 | 99 | per_clkdm: per_clkdm { 100 | compatible = "ti,clockdomain"; 101 | clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, 102 | <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, 103 | <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, 104 | <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, 105 | <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, 106 | <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, 107 | <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, 108 | <&mcbsp4_ick>, <&uart4_fck>; 109 | }; 110 | }; 111 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap36xx-hs.dtsi: -------------------------------------------------------------------------------- 1 | /* Disabled modules for secure omaps */ 2 | 3 | #include "omap36xx.dtsi" 4 | 5 | /* Secure omaps have some devices inaccessible depending on the firmware */ 6 | &aes { 7 | status = "disabled"; 8 | }; 9 | 10 | &sham { 11 | status = "disabled"; 12 | }; 13 | 14 | &timer12 { 15 | status = "disabled"; 16 | }; 17 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Source for OMAP34xx/OMAP36xx clock data 3 | * 4 | * Copyright (C) 2013 Texas Instruments, Inc. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | */ 10 | &cm_clocks { 11 | ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 { 12 | #clock-cells = <0>; 13 | compatible = "ti,composite-no-wait-gate-clock"; 14 | clocks = <&corex2_fck>; 15 | ti,bit-shift = <0>; 16 | reg = <0x0a00>; 17 | }; 18 | 19 | ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { 20 | #clock-cells = <0>; 21 | compatible = "ti,composite-divider-clock"; 22 | clocks = <&corex2_fck>; 23 | ti,bit-shift = <8>; 24 | reg = <0x0a40>; 25 | ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 26 | }; 27 | 28 | ssi_ssr_fck: ssi_ssr_fck_3430es2 { 29 | #clock-cells = <0>; 30 | compatible = "ti,composite-clock"; 31 | clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; 32 | }; 33 | 34 | ssi_sst_fck: ssi_sst_fck_3430es2 { 35 | #clock-cells = <0>; 36 | compatible = "fixed-factor-clock"; 37 | clocks = <&ssi_ssr_fck>; 38 | clock-mult = <1>; 39 | clock-div = <2>; 40 | }; 41 | 42 | hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 { 43 | #clock-cells = <0>; 44 | compatible = "ti,omap3-hsotgusb-interface-clock"; 45 | clocks = <&core_l3_ick>; 46 | reg = <0x0a10>; 47 | ti,bit-shift = <4>; 48 | }; 49 | 50 | ssi_l4_ick: ssi_l4_ick { 51 | #clock-cells = <0>; 52 | compatible = "fixed-factor-clock"; 53 | clocks = <&l4_ick>; 54 | clock-mult = <1>; 55 | clock-div = <1>; 56 | }; 57 | 58 | ssi_ick: ssi_ick_3430es2 { 59 | #clock-cells = <0>; 60 | compatible = "ti,omap3-ssi-interface-clock"; 61 | clocks = <&ssi_l4_ick>; 62 | reg = <0x0a10>; 63 | ti,bit-shift = <0>; 64 | }; 65 | 66 | usim_gate_fck: usim_gate_fck { 67 | #clock-cells = <0>; 68 | compatible = "ti,composite-gate-clock"; 69 | clocks = <&omap_96m_fck>; 70 | ti,bit-shift = <9>; 71 | reg = <0x0c00>; 72 | }; 73 | 74 | sys_d2_ck: sys_d2_ck { 75 | #clock-cells = <0>; 76 | compatible = "fixed-factor-clock"; 77 | clocks = <&sys_ck>; 78 | clock-mult = <1>; 79 | clock-div = <2>; 80 | }; 81 | 82 | omap_96m_d2_fck: omap_96m_d2_fck { 83 | #clock-cells = <0>; 84 | compatible = "fixed-factor-clock"; 85 | clocks = <&omap_96m_fck>; 86 | clock-mult = <1>; 87 | clock-div = <2>; 88 | }; 89 | 90 | omap_96m_d4_fck: omap_96m_d4_fck { 91 | #clock-cells = <0>; 92 | compatible = "fixed-factor-clock"; 93 | clocks = <&omap_96m_fck>; 94 | clock-mult = <1>; 95 | clock-div = <4>; 96 | }; 97 | 98 | omap_96m_d8_fck: omap_96m_d8_fck { 99 | #clock-cells = <0>; 100 | compatible = "fixed-factor-clock"; 101 | clocks = <&omap_96m_fck>; 102 | clock-mult = <1>; 103 | clock-div = <8>; 104 | }; 105 | 106 | omap_96m_d10_fck: omap_96m_d10_fck { 107 | #clock-cells = <0>; 108 | compatible = "fixed-factor-clock"; 109 | clocks = <&omap_96m_fck>; 110 | clock-mult = <1>; 111 | clock-div = <10>; 112 | }; 113 | 114 | dpll5_m2_d4_ck: dpll5_m2_d4_ck { 115 | #clock-cells = <0>; 116 | compatible = "fixed-factor-clock"; 117 | clocks = <&dpll5_m2_ck>; 118 | clock-mult = <1>; 119 | clock-div = <4>; 120 | }; 121 | 122 | dpll5_m2_d8_ck: dpll5_m2_d8_ck { 123 | #clock-cells = <0>; 124 | compatible = "fixed-factor-clock"; 125 | clocks = <&dpll5_m2_ck>; 126 | clock-mult = <1>; 127 | clock-div = <8>; 128 | }; 129 | 130 | dpll5_m2_d16_ck: dpll5_m2_d16_ck { 131 | #clock-cells = <0>; 132 | compatible = "fixed-factor-clock"; 133 | clocks = <&dpll5_m2_ck>; 134 | clock-mult = <1>; 135 | clock-div = <16>; 136 | }; 137 | 138 | dpll5_m2_d20_ck: dpll5_m2_d20_ck { 139 | #clock-cells = <0>; 140 | compatible = "fixed-factor-clock"; 141 | clocks = <&dpll5_m2_ck>; 142 | clock-mult = <1>; 143 | clock-div = <20>; 144 | }; 145 | 146 | usim_mux_fck: usim_mux_fck { 147 | #clock-cells = <0>; 148 | compatible = "ti,composite-mux-clock"; 149 | clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; 150 | ti,bit-shift = <3>; 151 | reg = <0x0c40>; 152 | ti,index-starts-at-one; 153 | }; 154 | 155 | usim_fck: usim_fck { 156 | #clock-cells = <0>; 157 | compatible = "ti,composite-clock"; 158 | clocks = <&usim_gate_fck>, <&usim_mux_fck>; 159 | }; 160 | 161 | usim_ick: usim_ick { 162 | #clock-cells = <0>; 163 | compatible = "ti,omap3-interface-clock"; 164 | clocks = <&wkup_l4_ick>; 165 | reg = <0x0c10>; 166 | ti,bit-shift = <9>; 167 | }; 168 | }; 169 | 170 | &cm_clockdomains { 171 | core_l3_clkdm: core_l3_clkdm { 172 | compatible = "ti,clockdomain"; 173 | clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; 174 | }; 175 | 176 | wkup_clkdm: wkup_clkdm { 177 | compatible = "ti,clockdomain"; 178 | clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, 179 | <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, 180 | <&gpt1_ick>, <&usim_ick>; 181 | }; 182 | 183 | core_l4_clkdm: core_l4_clkdm { 184 | compatible = "ti,clockdomain"; 185 | clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, 186 | <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, 187 | <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, 188 | <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, 189 | <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, 190 | <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, 191 | <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, 192 | <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, 193 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 194 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 195 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, 196 | <&ssi_ick>; 197 | }; 198 | }; 199 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/omap36xx.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Source for OMAP3 SoC 3 | * 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 5 | * 6 | * This file is licensed under the terms of the GNU General Public License 7 | * version 2. This program is licensed "as is" without any warranty of any 8 | * kind, whether express or implied. 9 | */ 10 | 11 | #include "omap3.dtsi" 12 | 13 | / { 14 | aliases { 15 | serial3 = &uart4; 16 | }; 17 | 18 | cpus { 19 | /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ 20 | cpu@0 { 21 | operating-points = < 22 | /* kHz uV */ 23 | 300000 1012500 24 | 600000 1200000 25 | 800000 1325000 26 | >; 27 | clock-latency = <300000>; /* From legacy driver */ 28 | }; 29 | }; 30 | 31 | ocp { 32 | uart4: serial@49042000 { 33 | compatible = "ti,omap3-uart"; 34 | reg = <0x49042000 0x400>; 35 | interrupts = <80>; 36 | dmas = <&sdma 81 &sdma 82>; 37 | dma-names = "tx", "rx"; 38 | ti,hwmods = "uart4"; 39 | clock-frequency = <48000000>; 40 | }; 41 | 42 | abb_mpu_iva: regulator-abb-mpu { 43 | compatible = "ti,abb-v1"; 44 | regulator-name = "abb_mpu_iva"; 45 | #address-cell = <0>; 46 | #size-cells = <0>; 47 | reg = <0x483072f0 0x8>, <0x48306818 0x4>; 48 | reg-names = "base-address", "int-address"; 49 | ti,tranxdone-status-mask = <0x4000000>; 50 | clocks = <&sys_ck>; 51 | ti,settling-time = <30>; 52 | ti,clock-cycles = <8>; 53 | ti,abb_info = < 54 | /*uV ABB efuse rbb_m fbb_m vset_m*/ 55 | 1012500 0 0 0 0 0 56 | 1200000 0 0 0 0 0 57 | 1325000 0 0 0 0 0 58 | 1375000 1 0 0 0 0 59 | >; 60 | }; 61 | 62 | omap3_pmx_core2: pinmux@480025a0 { 63 | compatible = "ti,omap3-padconf", "pinctrl-single"; 64 | reg = <0x480025a0 0x5c>; 65 | #address-cells = <1>; 66 | #size-cells = <0>; 67 | #interrupt-cells = <1>; 68 | interrupt-controller; 69 | pinctrl-single,register-width = <16>; 70 | pinctrl-single,function-mask = <0xff1f>; 71 | }; 72 | }; 73 | }; 74 | 75 | /* OMAP3630 needs dss_96m_fck for VENC */ 76 | &venc { 77 | clocks = <&dss_tv_fck>, <&dss_96m_fck>; 78 | clock-names = "fck", "tv_dac_clk"; 79 | }; 80 | 81 | /include/ "omap34xx-omap36xx-clocks.dtsi" 82 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" 83 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 84 | /include/ "omap36xx-clocks.dtsi" 85 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/tps6507x.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | /* 10 | * Integrated Power Management Chip 11 | * http://www.ti.com/lit/ds/symlink/tps65070.pdf 12 | */ 13 | 14 | &tps { 15 | compatible = "ti,tps6507x"; 16 | 17 | regulators { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | 21 | vdcdc1_reg: regulator@0 { 22 | reg = <0>; 23 | regulator-compatible = "VDCDC1"; 24 | }; 25 | 26 | vdcdc2_reg: regulator@1 { 27 | reg = <1>; 28 | regulator-compatible = "VDCDC2"; 29 | }; 30 | 31 | vdcdc3_reg: regulator@2 { 32 | reg = <2>; 33 | regulator-compatible = "VDCDC3"; 34 | }; 35 | 36 | ldo1_reg: regulator@3 { 37 | reg = <3>; 38 | regulator-compatible = "LDO1"; 39 | }; 40 | 41 | ldo2_reg: regulator@4 { 42 | reg = <4>; 43 | regulator-compatible = "LDO2"; 44 | }; 45 | 46 | }; 47 | }; 48 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/tps65217.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | /* 10 | * Integrated Power Management Chip 11 | * http://www.ti.com/lit/ds/symlink/tps65217.pdf 12 | */ 13 | 14 | &tps { 15 | compatible = "ti,tps65217"; 16 | 17 | regulators { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | 21 | dcdc1_reg: regulator@0 { 22 | reg = <0>; 23 | regulator-compatible = "dcdc1"; 24 | }; 25 | 26 | dcdc2_reg: regulator@1 { 27 | reg = <1>; 28 | regulator-compatible = "dcdc2"; 29 | }; 30 | 31 | dcdc3_reg: regulator@2 { 32 | reg = <2>; 33 | regulator-compatible = "dcdc3"; 34 | }; 35 | 36 | ldo1_reg: regulator@3 { 37 | reg = <3>; 38 | regulator-compatible = "ldo1"; 39 | }; 40 | 41 | ldo2_reg: regulator@4 { 42 | reg = <4>; 43 | regulator-compatible = "ldo2"; 44 | }; 45 | 46 | ldo3_reg: regulator@5 { 47 | reg = <5>; 48 | regulator-compatible = "ldo3"; 49 | }; 50 | 51 | ldo4_reg: regulator@6 { 52 | reg = <6>; 53 | regulator-compatible = "ldo4"; 54 | }; 55 | }; 56 | }; 57 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/tps65910.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | /* 10 | * Integrated Power Management Chip 11 | * http://www.ti.com/lit/ds/symlink/tps65910.pdf 12 | */ 13 | 14 | &tps { 15 | compatible = "ti,tps65910"; 16 | 17 | regulators { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | 21 | vrtc_reg: regulator@0 { 22 | reg = <0>; 23 | regulator-compatible = "vrtc"; 24 | }; 25 | 26 | vio_reg: regulator@1 { 27 | reg = <1>; 28 | regulator-compatible = "vio"; 29 | }; 30 | 31 | vdd1_reg: regulator@2 { 32 | reg = <2>; 33 | regulator-compatible = "vdd1"; 34 | }; 35 | 36 | vdd2_reg: regulator@3 { 37 | reg = <3>; 38 | regulator-compatible = "vdd2"; 39 | }; 40 | 41 | vdd3_reg: regulator@4 { 42 | reg = <4>; 43 | regulator-compatible = "vdd3"; 44 | }; 45 | 46 | vdig1_reg: regulator@5 { 47 | reg = <5>; 48 | regulator-compatible = "vdig1"; 49 | }; 50 | 51 | vdig2_reg: regulator@6 { 52 | reg = <6>; 53 | regulator-compatible = "vdig2"; 54 | }; 55 | 56 | vpll_reg: regulator@7 { 57 | reg = <7>; 58 | regulator-compatible = "vpll"; 59 | }; 60 | 61 | vdac_reg: regulator@8 { 62 | reg = <8>; 63 | regulator-compatible = "vdac"; 64 | }; 65 | 66 | vaux1_reg: regulator@9 { 67 | reg = <9>; 68 | regulator-compatible = "vaux1"; 69 | }; 70 | 71 | vaux2_reg: regulator@10 { 72 | reg = <10>; 73 | regulator-compatible = "vaux2"; 74 | }; 75 | 76 | vaux33_reg: regulator@11 { 77 | reg = <11>; 78 | regulator-compatible = "vaux33"; 79 | }; 80 | 81 | vmmc_reg: regulator@12 { 82 | reg = <12>; 83 | regulator-compatible = "vmmc"; 84 | }; 85 | 86 | vbb_reg: regulator@13 { 87 | reg = <13>; 88 | regulator-compatible = "vbb"; 89 | }; 90 | }; 91 | }; 92 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/twl4030.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | /* 10 | * Integrated Power Management Chip 11 | */ 12 | &twl { 13 | compatible = "ti,twl4030"; 14 | interrupt-controller; 15 | #interrupt-cells = <1>; 16 | 17 | rtc { 18 | compatible = "ti,twl4030-rtc"; 19 | interrupts = <11>; 20 | }; 21 | 22 | charger: bci { 23 | compatible = "ti,twl4030-bci"; 24 | interrupts = <9>, <2>; 25 | bci3v1-supply = <&vusb3v1>; 26 | }; 27 | 28 | watchdog { 29 | compatible = "ti,twl4030-wdt"; 30 | }; 31 | 32 | vaux1: regulator-vaux1 { 33 | compatible = "ti,twl4030-vaux1"; 34 | }; 35 | 36 | vaux2: regulator-vaux2 { 37 | compatible = "ti,twl4030-vaux2"; 38 | }; 39 | 40 | vaux3: regulator-vaux3 { 41 | compatible = "ti,twl4030-vaux3"; 42 | }; 43 | 44 | vaux4: regulator-vaux4 { 45 | compatible = "ti,twl4030-vaux4"; 46 | }; 47 | 48 | vcc: regulator-vdd1 { 49 | compatible = "ti,twl4030-vdd1"; 50 | regulator-min-microvolt = <600000>; 51 | regulator-max-microvolt = <1450000>; 52 | }; 53 | 54 | vdac: regulator-vdac { 55 | compatible = "ti,twl4030-vdac"; 56 | regulator-min-microvolt = <1800000>; 57 | regulator-max-microvolt = <1800000>; 58 | }; 59 | 60 | vio: regulator-vio { 61 | compatible = "ti,twl4030-vio"; 62 | }; 63 | 64 | vintana1: regulator-vintana1 { 65 | compatible = "ti,twl4030-vintana1"; 66 | }; 67 | 68 | vintana2: regulator-vintana2 { 69 | compatible = "ti,twl4030-vintana2"; 70 | }; 71 | 72 | vintdig: regulator-vintdig { 73 | compatible = "ti,twl4030-vintdig"; 74 | }; 75 | 76 | vmmc1: regulator-vmmc1 { 77 | compatible = "ti,twl4030-vmmc1"; 78 | regulator-min-microvolt = <1850000>; 79 | regulator-max-microvolt = <3150000>; 80 | }; 81 | 82 | vmmc2: regulator-vmmc2 { 83 | compatible = "ti,twl4030-vmmc2"; 84 | regulator-min-microvolt = <1850000>; 85 | regulator-max-microvolt = <3150000>; 86 | }; 87 | 88 | vusb1v5: regulator-vusb1v5 { 89 | compatible = "ti,twl4030-vusb1v5"; 90 | }; 91 | 92 | vusb1v8: regulator-vusb1v8 { 93 | compatible = "ti,twl4030-vusb1v8"; 94 | }; 95 | 96 | vusb3v1: regulator-vusb3v1 { 97 | compatible = "ti,twl4030-vusb3v1"; 98 | }; 99 | 100 | vpll1: regulator-vpll1 { 101 | compatible = "ti,twl4030-vpll1"; 102 | }; 103 | 104 | vpll2: regulator-vpll2 { 105 | compatible = "ti,twl4030-vpll2"; 106 | regulator-min-microvolt = <1800000>; 107 | regulator-max-microvolt = <1800000>; 108 | }; 109 | 110 | vsim: regulator-vsim { 111 | compatible = "ti,twl4030-vsim"; 112 | regulator-min-microvolt = <1800000>; 113 | regulator-max-microvolt = <3000000>; 114 | }; 115 | 116 | twl_gpio: gpio { 117 | compatible = "ti,twl4030-gpio"; 118 | gpio-controller; 119 | #gpio-cells = <2>; 120 | interrupt-controller; 121 | #interrupt-cells = <1>; 122 | }; 123 | 124 | usb2_phy: twl4030-usb { 125 | compatible = "ti,twl4030-usb"; 126 | interrupts = <10>, <4>; 127 | usb1v5-supply = <&vusb1v5>; 128 | usb1v8-supply = <&vusb1v8>; 129 | usb3v1-supply = <&vusb3v1>; 130 | usb_mode = <1>; 131 | #phy-cells = <0>; 132 | }; 133 | 134 | twl_pwm: pwm { 135 | compatible = "ti,twl4030-pwm"; 136 | #pwm-cells = <2>; 137 | }; 138 | 139 | twl_pwmled: pwmled { 140 | compatible = "ti,twl4030-pwmled"; 141 | #pwm-cells = <2>; 142 | }; 143 | 144 | twl_pwrbutton: pwrbutton { 145 | compatible = "ti,twl4030-pwrbutton"; 146 | interrupts = <8>; 147 | }; 148 | 149 | twl_keypad: keypad { 150 | compatible = "ti,twl4030-keypad"; 151 | interrupts = <1>; 152 | keypad,num-rows = <8>; 153 | keypad,num-columns = <8>; 154 | }; 155 | }; 156 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/twl4030_omap3.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Linaro, Ltd. 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | &twl { 10 | pinctrl-names = "default"; 11 | pinctrl-0 = <&twl4030_pins>; 12 | }; 13 | 14 | &omap3_pmx_core { 15 | /* 16 | * On most OMAP3 platforms, the twl4030 IRQ line is connected 17 | * to the SYS_NIRQ line on OMAP. Therefore, configure the 18 | * defaults for the SYS_NIRQ pin here. 19 | */ 20 | twl4030_pins: pinmux_twl4030_pins { 21 | pinctrl-single,pins = < 22 | 0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ 23 | >; 24 | }; 25 | }; 26 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/twl6030.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | /* 10 | * Integrated Power Management Chip 11 | * http://www.ti.com/lit/ds/symlink/twl6030.pdf 12 | */ 13 | &twl { 14 | compatible = "ti,twl6030"; 15 | interrupt-controller; 16 | #interrupt-cells = <1>; 17 | 18 | rtc { 19 | compatible = "ti,twl4030-rtc"; 20 | interrupts = <11>; 21 | }; 22 | 23 | vaux1: regulator-vaux1 { 24 | compatible = "ti,twl6030-vaux1"; 25 | regulator-min-microvolt = <1000000>; 26 | regulator-max-microvolt = <3000000>; 27 | }; 28 | 29 | vaux2: regulator-vaux2 { 30 | compatible = "ti,twl6030-vaux2"; 31 | regulator-min-microvolt = <1200000>; 32 | regulator-max-microvolt = <2800000>; 33 | }; 34 | 35 | vaux3: regulator-vaux3 { 36 | compatible = "ti,twl6030-vaux3"; 37 | regulator-min-microvolt = <1000000>; 38 | regulator-max-microvolt = <3000000>; 39 | }; 40 | 41 | vmmc: regulator-vmmc { 42 | compatible = "ti,twl6030-vmmc"; 43 | regulator-min-microvolt = <1200000>; 44 | regulator-max-microvolt = <3000000>; 45 | }; 46 | 47 | vpp: regulator-vpp { 48 | compatible = "ti,twl6030-vpp"; 49 | regulator-min-microvolt = <1800000>; 50 | regulator-max-microvolt = <2500000>; 51 | }; 52 | 53 | vusim: regulator-vusim { 54 | compatible = "ti,twl6030-vusim"; 55 | regulator-min-microvolt = <1200000>; 56 | regulator-max-microvolt = <2900000>; 57 | }; 58 | 59 | vdac: regulator-vdac { 60 | compatible = "ti,twl6030-vdac"; 61 | }; 62 | 63 | vana: regulator-vana { 64 | compatible = "ti,twl6030-vana"; 65 | }; 66 | 67 | vcxio: regulator-vcxio { 68 | compatible = "ti,twl6030-vcxio"; 69 | regulator-always-on; 70 | }; 71 | 72 | vusb: regulator-vusb { 73 | compatible = "ti,twl6030-vusb"; 74 | }; 75 | 76 | v1v8: regulator-v1v8 { 77 | compatible = "ti,twl6030-v1v8"; 78 | regulator-always-on; 79 | }; 80 | 81 | v2v1: regulator-v2v1 { 82 | compatible = "ti,twl6030-v2v1"; 83 | regulator-always-on; 84 | }; 85 | 86 | clk32kg: regulator-clk32kg { 87 | compatible = "ti,twl6030-clk32kg"; 88 | }; 89 | 90 | twl_usb_comparator: usb-comparator { 91 | compatible = "ti,twl6030-usb"; 92 | interrupts = <4>, <10>; 93 | }; 94 | 95 | twl_pwm: pwm { 96 | /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ 97 | compatible = "ti,twl6030-pwm"; 98 | #pwm-cells = <2>; 99 | }; 100 | 101 | twl_pwmled: pwmled { 102 | /* provides one PWM (id 0 for Charging indicator LED) */ 103 | compatible = "ti,twl6030-pwmled"; 104 | #pwm-cells = <2>; 105 | }; 106 | }; 107 | -------------------------------------------------------------------------------- /arch/arm/boot/dts/twl6030_omap4.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | 9 | &twl { 10 | /* 11 | * On most OMAP4 platforms, the twl6030 IRQ line is connected 12 | * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is 13 | * connected to the fref_clk0_out.sys_drm_msecure line. 14 | * Therefore, configure the defaults for the SYS_NIRQ1 and 15 | * fref_clk0_out.sys_drm_msecure pins here. 16 | */ 17 | pinctrl-names = "default"; 18 | pinctrl-0 = < 19 | &twl6030_pins 20 | &twl6030_wkup_pins 21 | >; 22 | }; 23 | 24 | &omap4_pmx_wkup { 25 | twl6030_wkup_pins: pinmux_twl6030_wkup_pins { 26 | pinctrl-single,pins = < 27 | 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ 28 | >; 29 | }; 30 | }; 31 | 32 | &omap4_pmx_core { 33 | twl6030_pins: pinmux_twl6030_pins { 34 | pinctrl-single,pins = < 35 | 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ 36 | >; 37 | }; 38 | }; 39 | --------------------------------------------------------------------------------