├── LICENSE └── README.md /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Ben Marshall 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Open Hardware Verification 2 | 3 | *A curated List of Free and Open Source hardware verification tools and frameworks.* 4 | 5 | The aim here is to curate a (mostly) comprehensive list of available tools for verifying 6 | the functional correctness of Free and Open Source Hardware designs. The list can 7 | include: 8 | - [Tools](#tools) which contain or implement verification related functionality 9 | - [Testbench Frameworks](#frameworks) which make writing testbenches easier 10 | - [Projects](#projects) which are good examples of free/open hardware verification efforts 11 | - [Verification Guides](#guides) and blog posts on how to actually go about verifying a hardware design 12 | - [Conferences](#conferences) where new work on open source hardware verification is talked about 13 | 14 | Pull requests and submissions are encouraged! 15 | 16 | **Some Rules:** 17 | 18 | This list focuses on *Verification* and not *design*. While there are lots of cool new 19 | languages and frameworks aimed at making hardware design easier (or at least, *not Verilog/VHDL*), 20 | verification can sometimes get left out in the cold. 21 | 22 | While some new design tools/languages claim that "our new design tool `X` makes verification 23 | easier because it is written in high level language `Y`", it can often be much harder to find 24 | evidence of this in terms of re-usable verification IP/frameworks/methods which are written 25 | in "new language/tool `Y`". It might seem mean, but being a new design language which 26 | *theoretically* makes verification easier is not enough to merit inclusion on this list. What's 27 | needed is *practical* demonstration of making verification easier. This can be through libraries or 28 | IP which use "new language/tool `Y`", or in depth tutorials which explain how to use it for proper 29 | design verification. 30 | 31 | If you're after hardware *design* tools, these awesome lists are a good place to start: 32 | - [awesome-hdl](https://github.com/drom/awesome-hdl) 33 | 34 | Further, entries in this list should not only be open source themselves, but *be usable* by 35 | people developing open source hardware using open source tools. For example, if company `X` 36 | releases a set of re-usable verification components written using 37 | [UVM](https://www.accellera.org/downloads/standards/uvm) 38 | and SystemVerilog, is there an Free and Open Source SystemVerilog implementation which can make 39 | use of them? 40 | 41 | ## Contents 42 | 43 | This list has grown a lot lately, and the original taxonomy of tools/frameworks 44 | I had is starting to break down. I'll probably switch to a proper website 45 | when I get the time to remember how Github Pages works. 46 | 47 | ### Tools 48 | 49 | #### Formal Verification: 50 | 51 | - [Symbiyosys](#symbiyosys) 52 | - [riscv-formal](#riscv-formal) 53 | - [MCY](#mcy) - Testbench coverage tool. 54 | - [EBMC / CBMC](#ebmc--cbmc) (Model checker for C/C++ and hardware designs) 55 | 56 | #### Simulation: 57 | 58 | - [Verilator](#verilator) - Verilog Simulator 59 | - [Icarus Verilog](#icarus-Verilog) - Icarus Verilog Simulator 60 | 61 | #### Build Systems and Continuous Integration: 62 | 63 | - [LibreCores CI](#libreCores-ci) 64 | - [FuseSoc](#fusesoc) - Package manager and build abstraction tool for FPGA/ASIC development. 65 | - [fsva](#fsva) - FuseSoC Verification Automation 66 | 67 | #### Test / Program / Code Generators: 68 | 69 | - [AAPG (Automated Assembly Program Generator)](#aapg) 70 | - [riscv-dv](#riscv-dv) - Instruction sequence generator for RISC-V 71 | - [rggen](#rggen) (Code generation tool for configuration and status registers) 72 | - [FORCE-RISCV](#force-riscv) - Another instruction sequence generator for RISC-V 73 | 74 | #### Coverage: 75 | 76 | - [covered](#covered) 77 | 78 | #### Linting and Parsing: 79 | 80 | - [svlint](#svlint) 81 | - [sv-parser](#sv-parser) 82 | - [Surelog](#surelog-system-verilog-2017-pre-processor-parser) 83 | 84 | ### Testbench Frameworks: 85 | 86 | - [cocotb](#cocotb) - Python based testbench environment for many simulators 87 | - [python-uvm](#python-uvm) - A port of UVM 1.2 to Python and [cocotb](#cocotb). 88 | - [cocotb-coverage](#cocotb-coverage) - Functional Coverage and Constrained Randomization extensions for Cocotb. 89 | - [Verification IPs](#cocotb-ips) - Various cocotb packages for common interfaces: AXI/Ethernet/PCIE 90 | - [fvutils/pyvsc](#fvutilspyvsc) - Python packages providing a library for Verification Stimulus and Coverage 91 | - [chiselverify](#chisel-verify) - UVM-like verification for the Chisel HDL 92 | - [UVVM](#uvvm) 93 | - [OSVVM](#osvvm) 94 | - [VUnit](#vunit) 95 | - [V3](#v3) 96 | - [ROHD Verification Framework](#rohd-verification-framework) - Hardware verification framework upon [ROHD](https://github.com/intel/rohd) for building and executing testbenches. 97 | 98 | ### Components / VIPs 99 | 100 | - [uvm_axi](#uvm_axi) 101 | - [AXI Bus Formal VIP](#axi-bus-formal-vip) 102 | - [AXI Bus Functional Model tvip-axi](#axi-bus-functional-model---tvip-axi) 103 | - [AXI SystemVerilog Modules and Verification Infrastructure](#axi-systemverilog-modules-and-verification-infrastructure) 104 | - [APB Bus Functional Model tvip-apb](#apb-bus-functional-model---tvip-apb) 105 | - [USB 1.1 Test Suite](#antmicro-usb-test-suite) 106 | - [Cocotb Verification IPs](#cocotb-ips) - Various cocotb packages for common interfaces: AXI/Ethernet/PCIE 107 | - [RISC-V-TLM](#risc-v-tlm) - A SystemC transaction level model of RISC-V 108 | 109 | ### Projects 110 | 111 | - [OpenHW Group Functional Verification](#openhw-group-functional-verification) 112 | - [LowRISC Style Guides](#lowrisc-style-guides) 113 | 114 | ### Guides & Blogs: 115 | 116 | - [Dan Gisselquist Formal Verification Blogs](#dan-gisselquist-formal-verification-blogs) 117 | - [Verification Gentleman Blog](#verification-gentleman-blog) 118 | - [Bits, Bytes and Gates](#bits-bytes-and-gates) 119 | 120 | ### Conferences: 121 | 122 | - [ORCONF](#orconf) 123 | - [OSDA](#osda) 124 | - [CHIPS Alliance Workshop on Open Source Design Verification](#chips-alliance-workshop-on-open-source-design-verification) 125 | - [Workshop on Open-Source EDA Technology (WOSET)](#workshop-on-open-source-eda-technology-woset) 126 | 127 | --- 128 | 129 | ## Tools: 130 | 131 | ### SymbiYosys 132 | 133 | *"SymbiYosis a front-end driver program for Yosys-based formal hardware 134 | verification flows. SymbiYosys provides flows for the following formal tasks: 135 | Bounded verification of safety properties (assertions), 136 | Unbounded verification of safety properties, 137 | Generation of test benches from cover statements, 138 | Verification of liveness properties"* 139 | 140 | SymbiYosys requires [Yosys](https://github.com/YosysHQ/yosys) (an open 141 | source synthesis tool) and one or more formal reasoning engines (listed 142 | [here](https://symbiyosys.readthedocs.io/en/latest/quickstart.html#prerequisites)to work. 143 | 144 | - Written In: Python 145 | - Write Assertions In: Verilog/SystemVerilog Assertions (SVA) 146 | - Supports: Formal verification of correctness properties. 147 | - Link: https://symbiyosys.readthedocs.io/en/latest/ 148 | 149 | ### MCY 150 | 151 | *"mcy is a new tool to help digital designers and project managers understand and improve testbench coverage. [...] Given a self checking testbench, mcy generates 1000s of mutations by modifying individual signals in a post synthesis netlist. These mutations are then filtered using Formal Verification techniques, keeping only those that can cause an important change in the design’s output. All mutated designs are run against the testbench to check that the testbench will detect and fail for a relevant mutation. The testbench can then be improved to get 100% complete coverage."* 152 | 153 | - Written In: C++ / Python 154 | - License: [ISC](https://github.com/YosysHQ/mcy/blob/master/COPYING) 155 | - Link: https://github.com/YosysHQ/mcy 156 | 157 | ### Verilator 158 | 159 | Verilator is "the fastest free Verilog HDL simulator". From a verification 160 | perspective it supports *line coverage*, *signal toggle coverage* and limited 161 | specification of *functional coverage* using SystemVerilog Assertions. 162 | It also allows one to write testbenches in C++ or SystemC. 163 | 164 | - Written In: C++ 165 | - Write testbenches in: C++/SystemC/Verilog 166 | - Supports: Design simuation, *Coverage collection from simulations*. 167 | - Link: https://www.veripool.org/projects/verilator/wiki/Intro 168 | 169 | ### Icarus Verilog 170 | 171 | The excellent Icarus Verilog simulator. 172 | Slower than Verilator, but it supports full 4-state simulation (i.e. X's and 173 | Z's). 174 | 175 | - Write testbenches in: Verilog, or use [cocotb](#cocotb). 176 | - Link: https://github.com/steveicarus/iverilog 177 | 178 | ### LibreCores CI 179 | 180 | *"LibreCores CI is a service, which provides Continuous Integration of projects being hosted on LibreCores. The objective of the service is to improve the contributor experience and to increase trust to projects by providing automated testing and health metrics of the projects."* 181 | 182 | - Currently under development at the time of writing (Dec 2018) 183 | - Aims to allow automation of testing for hardware designs. Think "Travis for hardware". 184 | - Link: https://www.librecores.org/static/librecores-ci 185 | 186 | ## AAPG 187 | 188 | *"Automated Assembly Program Generator (aapg) is a tool that is intended to generate random RISC-V programs to test RISC-V cores."* 189 | 190 | From the [Shakti](https://gitlab.com/shaktiproject) RISC-V core project. 191 | Acts as a way to generate random stimulus for a RISC-V core. 192 | Output of the programs can then be checked between DUT and a GRM. 193 | 194 | - Link: https://gitlab.com/shaktiproject/tools/aapg 195 | - License: BSD 3-clause 196 | - Written In: Python 197 | 198 | ## riscv-dv 199 | 200 | Similar to [AAPG](#aapg), but this time from Google/ CHIPS Alliance. 201 | Generates randomised RISC-V programs which can 202 | then be run by the DUT and A GRM and checked for equivilence. 203 | It has knowledge of interesting features like page tables, CSR access and 204 | trap/interrupt handling. 205 | Can generate randomised instruction streams with features like loops 206 | and function calls etc. 207 | 208 | This project cannot be used with current free open source HDL simulators 209 | since it relies on the object orientated parts of UVM. It is still a 210 | useful piece of Verification IP though, and serves as a guide for other 211 | similar projects. 212 | The project also has a Python generator, which, while less capable 213 | as of the time of this writing, can be run with FOSS HDL simulators. 214 | 215 | - Link: https://github.com/chipsalliance/riscv-dv 216 | - License: Apache-2.0 217 | - Written In: SystemVerilog + UVM 218 | 219 | ### covered 220 | 221 | *"Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test."* ... *"Covered reads in the Verilog design files and a VCD, LXT or FST formatted dumpfile from a diagnostic run and generates a database file called a Coverage Description Database (CDD) file"* ... "*Once a CDD file is created, the user can use Covered to generate various human-readable coverage reports in an ASCII format or use Covered's GUI to interactively look at coverage results*". 222 | 223 | - Link: https://github.com/anders-code/verilog-covered 224 | - License: GPL-2.0 225 | - Written In: C 226 | 227 | ### svlint 228 | 229 | An open source, MIT licensed SystemVerilog linting tool. Built on top of an open source [SystemVerilog parser](#sv-parser). 230 | 231 | - Link: https://github.com/dalance/svlint 232 | - License: MIT 233 | - Written In: Rust 234 | 235 | ### sv-parser 236 | 237 | An open source, MIT/Apache licensed SystemVerilog parser/ Useful for quickly building custom tools / checkers. 238 | 239 | - Link: https://github.com/dalance/sv-parser 240 | - License: MIT / Apache 241 | - Written In: Rust 242 | 243 | ### Surelog: System Verilog 2017 Pre-processor, Parser 244 | 245 | *"This project aims at providing a complete System Verilog 2017 front-end: 246 | a preprocessor, a parser, an elaborator for both design and testbench."* 247 | 248 | *"Linter, Simulator, Synthesis tool, Formal tools can use this front-end. 249 | They either can be developed as plugins (linked with) or use this front-end 250 | as an intermediate step of their compilation flows"*. 251 | 252 | - Link: https://github.com/chipsalliance/Surelog 253 | - License: Apache 2.0 254 | - Written In: C++ with Python bindings. 255 | 256 | ### RgGen 257 | 258 | "*RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will 259 | automatically generate soruce code related to configuration and status 260 | registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from 261 | human readable register map specifications.*" 262 | 263 | - Link: https://github.com/rggen/rggen 264 | - License: MIT 265 | - Written in: Ruby 266 | 267 | 268 | ### EBMC / CBMC 269 | 270 | **EBMC:** 271 | 272 | "*EBMC is a Model Checker for hardware designs. It includes both bounded and 273 | unbounded analysis, i.e., it can both discover bugs and is also able to prove 274 | the absence of bugs. It can read Netlists (ISCAS89 format), Verilog, System 275 | Verilog and SMV files. Properties can be given in LTL or a fragment of System 276 | Verilog Assertions.*" 277 | 278 | - Link: http://www.cprover.org/ebmc/ 279 | - Licence: http://www.cprover.org/ebmc/download/license.txt 280 | - Written in: _Unknown_. 281 | 282 | Note: Only the binaries for EBMC can be downloaded, no source-code is 283 | available. It's included on this list because it is a powerful tool which 284 | would otherwise not be available to the open hardware community. 285 | For a completely free and open tool with similar capabilities, 286 | look at [SymbiYosys](#symbiyosys). 287 | 288 | **CBMC:** 289 | 290 | "*CBMC is a Bounded Model Checker for C and C++ programs.*" 291 | 292 | "*Furthermore, it can check C and C++ for consistency with other languages, 293 | such as Verilog. The verification is performed by unwinding the loops in the 294 | program and passing the resulting equation to a decision procedure.*" 295 | 296 | - Link: http://www.cprover.org/cbmc/ 297 | - Source: https://github.com/diffblue/cbmc 298 | - Licence: https://github.com/diffblue/cbmc/blob/develop/LICENSE 299 | - Written in: C++. 300 | 301 | ### FuseSoC 302 | 303 | From the project README: *FuseSoC is an award-winning package manager and a set 304 | of build tools for HDL (Hardware Description Language) code. Its main purpose 305 | is to increase reuse of IP (Intellectual Property) cores and be an aid for 306 | creating, building and simulating SoC solutions.* 307 | 308 | My Opinion: If you need a tool to manage you HDL or testbench dependencies, 309 | package your IP for easy sharing, or generally just make your hardware design 310 | and verification life easier, FuseSoC is a great place to start. 311 | 312 | - Link: https://github.com/olofk/fusesoc 313 | - Written in: Python 314 | - License: [BSD-2-Clause](https://github.com/olofk/fusesoc/blob/master/LICENSE) 315 | 316 | ### fsva 317 | 318 | "*fsva (FuseSoc Verification Automation) is a tool that aims to automate 319 | the verification process of libraries and HDL design projects managed 320 | with [FuseSoc](https://github.com/olofk/fusesoc) build tool/system.*" 321 | 322 | - Link: https://github.com/m-kru/fsva 323 | - License: MIT 324 | - Written in: Python 325 | 326 | ### FORCE-RISCV 327 | 328 | "*FORCE-RISCV is an instruction sequence generator (ISG) for the RISC-V instruction set architecture. It can be used to generate tests for design verification of RISC-V processors. FORCE-RISCV uses randomization to choose instructions, registers, addresses and data for the tests, and can generate valid test sequences with very little input from the user. However, FORCE-RISCV provides a set of APIs with extensive capabilities which gives the user a high level of control over how the instruction generation takes place.*" 329 | 330 | This makes it similar to [riscv-dv](#riscv-dv), but you don't 331 | need a SystemVerilog simulator to run it. 332 | It is maintained by the [OpenHW Group](https://www.openhwgroup.org/) 333 | 334 | Feature set: 335 | - RV64G - (RV64I, MAFDC). (V extension support planned) 336 | - RISC-V privileged ISA, including full support for the U, S, and M privilege levels. 337 | - RISC-V traps and exceptions basic handling. 338 | - Support for non-trivial exception handlers is planned. 339 | - Full support for the v48 virtual memory systems, including 4KB, 2MB, 1GB and 512GB page sizes. 340 | 341 | Details: 342 | - Link: https://github.com/openhwgroup/force-riscv 343 | - License: [Apache-2.0](https://github.com/openhwgroup/force-riscv/blob/master/LICENSE) 344 | - Written In: C++, Python3 345 | - Write Tests In: Python3 346 | 347 | ### RISC-V-TLM 348 | 349 | "*This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2. It supports RV32IMAC Instruction set by now.*" 350 | 351 | Details: 352 | - Link: https://github.com/mariusmm/RISC-V-TLM 353 | - License: [GPL-3.0](https://github.com/mariusmm/RISC-V-TLM/blob/master/LICENSE) 354 | - Written In: C++ / SystemC 355 | 356 | ## Frameworks: 357 | 358 | ### Cocotb 359 | *"cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python."* 360 | 361 | - Licence: [Revised BSD License](https://github.com/cocotb/cocotb/blob/master/LICENSE) 362 | - Implemented in: Python 363 | - Write Testbeches In: Python 364 | - Link: https://github.com/cocotb/cocotb 365 | 366 | 367 | ### python-uvm 368 | 369 | *"This is a port of SystemVerilog (SV) Universal Verification Methodology (UVM) 1.2 to Python and cocotb. [...] 370 | UVM is not currently supported by any open source/free tools. cocotb offers excellent solution to interact 371 | with any simulator (free/commercial), so testbenches can be written in Python as well. uvm-python tries to 372 | offer an API similar to the original SV version. This means that many UVM verificaton skills are 373 | transferable from SV to Python very easily."* 374 | 375 | - License: [Apache-2.0](https://github.com/tpoikela/uvm-python/blob/master/LICENSE) 376 | - Implemented in: Python 377 | - Write Testbenches In: Python 378 | - Link: https://github.com/tpoikela/uvm-python 379 | - Documentation: https://uvm-python.readthedocs.io/en/latest/ 380 | - Users Guide: https://uvm-python.readthedocs.io/en/latest/uvm_users_guide_1.2.html 381 | 382 | 383 | ### Cocotb Coverage 384 | 385 | *Functional Coverage and Constrained Randomization Extensions for Cocotb.* 386 | 387 | *This package allows you to use constrained randomization and functional coverage techniques known from CRV (constrained random verification) and MDV (metric-driven verification) methodologies, available in SystemVerilog or e. Such extensions enable the implementation of an advanced verification environment for complex projects.* 388 | 389 | There is also a DVCon'17 [presentation](http://events.dvcon.org/2017/proceedings/papers/02_3.pdf). 390 | 391 | - Implemented in: Python 392 | - Write Testbenches in: Python 393 | - License: [BSD-2-Clause](https://github.com/mciepluc/cocotb-coverage/blob/master/LICENSE) 394 | - Link: https://github.com/mciepluc/cocotb-coverage 395 | 396 | 397 | ### Cocotb IPs 398 | 399 | Listed here are various cocotb plugins for common interfaces or modules: 400 | 401 | Interface / Module | Author | License 402 | -------------------|--------|---------------- 403 | [AXI Bus](https://github.com/alexforencich/cocotbext-axi) | [Alex Forencich](http://www.alexforencich.com/wiki/en/start) | MIT 404 | [Ethernet](https://github.com/alexforencich/cocotbext-eth) | [Alex Forencich](http://www.alexforencich.com/wiki/en/start) | MIT 405 | [PCIe](https://github.com/alexforencich/cocotbext-pcie) | [Alex Forencich](http://www.alexforencich.com/wiki/en/start) | MIT 406 | 407 | 408 | ### fvutils/pyvsc 409 | 410 | *"PyVSC is a Python library that implements random verification-stimulus generation and coverage collection. 411 | [...] Currently, the Python-embedded domain-specific language supports similar features to those supported by SystemVerilog. Not all SystemVerilog features are supported, but in some cases features not supported by SystemVerilog are also supported. Please see the following section [PyVSC Features](https://py-vsc.readthedocs.io/en/latest/features.html#pyvsc-features)"* 412 | 413 | - Written in: Python 414 | - License: [Apache-2.0](https://github.com/fvutils/pyvsc/blob/master/LICENSE) 415 | - Documentation: https://py-vsc.readthedocs.io/en/latest/ 416 | - Link: https://github.com/fvutils/pyvsc 417 | 418 | ### riscv-formal 419 | 420 | A re-usable formal verification framework for RISC-V CPU designs. 421 | Uses the [Yosys/SymbiYosys](#symbiyosys) tools. 422 | 423 | - License: [ISC](https://github.com/SymbioticEDA/riscv-formal/blob/master/COPYING) 424 | - Written In: Verilog 425 | - Link: https://github.com/SymbioticEDA/riscv-formal 426 | 427 | ### UVVM 428 | 429 | *"Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement"* 430 | 431 | There is also an accompanying library of user contributed VIPs: [UVVM_Community_VIPs](https://github.com/UVVM/UVVM_Community_VIPs). 432 | 433 | - License: [MIT](https://github.com/UVVM/UVVM/blob/master/LICENSE) 434 | - Written In: VHDL 435 | - Write Testbenches In: VHDL 436 | - Supports: [a bunch of stuff](https://github.com/UVVM/UVVM#main-features) 437 | - Link: https://github.com/UVVM/UVVM 438 | 439 | 440 | ### Chisel Verify 441 | 442 | From the project README: *This repo is for the project to explore the 443 | combination and interaction of Chisel and UVM. The ultimate goal is a 444 | verification framework within Scala for digital hardware described in Chisel 445 | also supporting legacy components in VHDL, Verilog, or SystemVerilog.* 446 | 447 | - Written In: Scala/Chisel 448 | - Write testbenches in: Scala/Chisel 449 | - License: [Apache-2.0](https://github.com/chiselverify/chiselverify/blob/master/LICENSE.txt) 450 | - Link: https://github.com/chiselverify/chiselverify 451 | 452 | ### OSVVM 453 | 454 | OSVVM is a VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow. OSVVM provides VHDL with buzz word verification capabilities including Transaction Level Modeling, Constrained Random, Functional Coverage, Scoreboards, and Error Reporting that are simple to use and feel like built-in language features. The reporting capabilities include HTML outputs for human readability and JUnit based XML for CI/CD tools. 455 | 456 | The GitHub organisation includes verification components: 457 | - [AXI4 Full - Manager, Memory, Subordinate](https://github.com/OSVVM/AXI4) 458 | - [AXI4 Lite - Manager, Memory, Subordinate](https://github.com/OSVVM/AXI4) 459 | - [AXI4 Stream - Transmitter and Receiver](https://github.com/OSVVM/AXI4) 460 | - [UART - Transmitter and Receiver](https://github.com/OSVVM/UART) 461 | - [DPRAM - Memory Model and Controller](https://github.com/OSVVM/DpRam) 462 | 463 | - License: APACHE-2.0 464 | - Written In: VHDL/TCL 465 | - Documentation: https://osvvm.github.io/ 466 | - Supports: Constrained Random Test Generation, Functional Coverage Collection, [and more](https://osvvm.org/about-os-vvm) 467 | - Link: https://osvvm.org/ 468 | - GitHub: https://github.com/OSVVM/OsvvmLibraries 469 | 470 | ### VUnit 471 | 472 | *"VUnit is an open source unit testing framework for VHDL/SystemVerilog \[...\] It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn’t replace but rather complements traditional testing methodologies by supporting a “test early and often” approach through automation."* 473 | 474 | Based partially on [OSVVM](#osvvm) 475 | 476 | - Written In: VHDL/Python 477 | - Write Testbenches In: VHDL/System Verilog 478 | - License: [Mozilla Public License, v. 2.0.](https://github.com/VUnit/vunit/blob/master/LICENSE.txt) baring OSVVM components. 479 | - Link: https://vunit.github.io/index.html 480 | 481 | ### V3 482 | 483 | *"V3 is a new and extensible framework for hardware verification and debugging researches on both Boolean-level and word-level designs. It is a powerful tool for users and an elaborate framework for developers as well."* 484 | 485 | Academic project, looks unmaintained since 2014. 486 | 487 | - Written In: C++ 488 | - Write Testbenches In: Unclear? 489 | - License: [Non-commercial](https://github.com/chengyinwu/V3/blob/master/COPYING) 490 | - Supports: formal methods based approaches using AGIER / SAT Solving over verilog input files. Not entirely clear how one specifies correctness properties. 491 | - Link: https://github.com/chengyinwu/V3 492 | 493 | ### ROHD Verification Framework 494 | *"The [ROHD Verification Framework (ROHD-VF)](https://github.com/intel/rohd-vf) is a verification framework built upon the [Rapid Open Hardware Development (ROHD) framework](https://github.com/intel/rohd). It enables testbench organization in a way similar to UVM. A key motivation behind it is that hardware testbenches are really just software, and verification engineers should be empowered to write them as great software. The ROHD Verification Framework enables development of a testbench in a modern programming language, taking advantage of recent innovations in the software industry. With ROHD and ROHD-VF, your testbench and hardware execute natively in Dart in a single fully-debuggable process. "* 495 | 496 | - Written in: Dart 497 | - Write Testbenches In: Dart with [ROHD](https://github.com/intel/rohd) 498 | - License: [BSD-3-Clause](https://github.com/intel/rohd-vf/blob/main/LICENSE) 499 | - Supports: Organizing testbenches in a way similar to UVM; natively executing, debugging, and simulating hardware and the testbench in Dart; all features of [ROHD](https://github.com/intel/rohd) including a fast event-based simulator 500 | - Link: https://github.com/intel/rohd-vf 501 | 502 | ## Components / VIPs 503 | 504 | ### uvm_axi 505 | 506 | A bus functional model for ARM's AXI bus protocol. Looks like it has been written as a standard UVM Verification Package. 507 | Being written in SystemVerilog (using all of its object orientated, behavioural modelling features) makes it hard 508 | to re-use with the current set of FOSS simulators. It is still a good example of re-usable verification IP. 509 | 510 | Last commit in 2013, so likely un-maintained. 511 | 512 | - Link: https://github.com/funningboy/uvm_axi 513 | - Written in: System Verilog 514 | - Write Testbenches In: System Verilog 515 | - License: GNU Lesser General Public License 516 | 517 | ### AXI Bus Formal VIP 518 | 519 | A set of formal properties for checking for correct protocol behaviour in an AXI bus. 520 | Used as part of a Wishbone-AXI bus bridge, but usable with any AXI bus. 521 | There is a great blog post on it's use [here](https://zipcpu.com/formal/2018/12/28/axilite.html) from ZipCPU. 522 | It works with SymbiYosys. 523 | 524 | - Link: https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v 525 | - Written in: Verilog 526 | - Write Testbenches In: Verilog 527 | - License: None specified 528 | 529 | ### AXI Bus Functional Model - tvip-axi 530 | 531 | Bus function model for AMBA AXI protocol. 532 | Supports master and slave agents, AXI4 and AXI4-Lite protocols. 533 | Configurable address/data/id widths. 534 | Supports in/out-of-order responses, delayed responses and read interleaving. 535 | 536 | - Link: https://github.com/taichi-ishitani/tvip-axi 537 | - Written in: SystemVerilog and UVM 538 | - License: Apache-2.0 539 | 540 | ### AXI SystemVerilog Modules and Verification Infrastructure 541 | 542 | SystemVerilog modules, testbenches, and test classes for AMBA AXI4 and 543 | AXI4-Lite. Provides parametrizable and synthesizable implementations of many 544 | common AXI modules (e.g., crossbars, data width converters) and testbenches for 545 | them. Provides test classes (drivers and monitors) to write custom testbenches. 546 | Provides protocol-compliant multiplexers and demultiplexers to simplify the 547 | implementation and verification of custom AXI modules. 548 | 549 | - Link: https://github.com/pulp-platform/axi 550 | - Written in: SystemVerilog 551 | - License: Solderpad Hardware License v0.51 552 | 553 | 554 | ### APB Bus Functional Model - tvip-apb 555 | 556 | Bus function model for AMBA APB protocol 557 | 558 | - Link: https://github.com/taichi-ishitani/tvip-apb 559 | - Written in: SystemVerilog and UVM 560 | - License: Apache-2.0 561 | 562 | 563 | ### Antmicro USB Test Suite 564 | 565 | "*This is a [Cocotb](https://github.com/cocotb/cocotb) based 566 | USB 1.1 test suite (to be extended to cover higher versions of 567 | the standard) for FPGA IP, with testbenches for a variety of open 568 | source USB cores.*" 569 | 570 | - Link: https://github.com/antmicro/usb-test-suite-build 571 | - Written in: Cocotb / Python 3 572 | - License: Apache-2.0 573 | 574 | 575 | ## Guides: 576 | 577 | ### Dan Gisselquist Formal Verification Blogs 578 | 579 | A set of posts on experiences using [Symbiyosys/Yosys](#symbiyosys) for formally verifying a CPU design. 580 | Includes lots of useful insights and guides for specific and general use cases. 581 | 582 | - Link: https://zipcpu.com/formal/formal.html 583 | 584 | ### Verification Gentleman Blog 585 | 586 | Written by [Tudor Timi](https://github.com/tudortimi): 587 | *"I started the Verification Gentleman blog to store 588 | solutions to small (and big) problems I've faced in my 589 | day to day work. I want to share them with the 590 | community in the hope that they may be useful to someone else."* 591 | 592 | - Link: https://blog.verificationgentleman.com/ 593 | - GitHub organisation with example code: https://github.com/verification-gentleman-blog 594 | 595 | ### Bits Bytes and Gates 596 | 597 | This is [Matthew Ballance's](https://github.com/mballance) 598 | (author of [fvutils/pycsv](#fvutilspyvsc)) blog, 599 | full of 600 | "*Musings on hardware and embedded software design and verification, 601 | and the EDA tools and methodologies that support them.*" 602 | 603 | There's some good stuff on using Python for coverage, constrained 604 | random stimulus generation and verification / EDA generally. 605 | 606 | - Link: http://bitsbytesgates.blogspot.com/ 607 | 608 | 609 | ## Projects 610 | 611 | ### OpenHW Group Functional Verification 612 | 613 | The [OpenHW group](https://www.openhwgroup.org/) are a 614 | not-for-profit focused on "*development of open-source cores, 615 | related IP, tools and software.*" 616 | 617 | This particular repository contains their functional verification 618 | efforts for their open source RISC-V CPUs. It's a good place 619 | to look at how a large verification project is planned and 620 | organised. 621 | 622 | - Github Link: https://github.com/openhwgroup/core-v-verif 623 | - Verification Strategy Document: https://core-v-docs-verif-strat.readthedocs.io/en/latest/ 624 | - License: [Solderpad V2](https://github.com/openhwgroup/core-v-verif/blob/master/LICENSE.md) 625 | 626 | ### LowRISC Style Guides 627 | 628 | These are the style guides used by the 629 | [LowRISC project](https://www.lowrisc.org/) 630 | for writing both RTL and UVM based testbenches. 631 | 632 | - License: [CC-BY-4.0](https://github.com/lowRISC/style-guides/blob/master/LICENSE) 633 | - Link: https://github.com/lowRISC/style-guides 634 | 635 | ## Conferences: 636 | 637 | ### ORCONF 638 | 639 | *"ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space."* 640 | 641 | - Link: https://orconf.org/ 642 | 643 | ### OSDA 644 | 645 | *"Workshop on Open Source Design Automation (OSDA)"* 646 | 647 | *"This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry. These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate 'open access' for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions."* 648 | 649 | - Longer Description: https://osda.gitlab.io/motivation.html 650 | - Link: https://osda.gitlab.io/ 651 | 652 | ### CHIPS Alliance Workshop on Open Source Design Verification 653 | 654 | *"The workshop invites contributions from industry, academia and hobbyists, either as talk or tutorial. Proposals should cover open source design simulation and verification, for example in the following categories (but not limited to): 655 | 656 | Open source simulation tools 657 | Open source design verification tools 658 | Open source rapid prototyping tools and methodologies 659 | Open source libraries for design verification 660 | Open source standards and methodologies for design verification 661 | Industry case studies of usage and integration of the aforementioned 662 | 663 | Most importantly, your submitted proposal should cover the open source aspect."* 664 | 665 | - Link: https://chipsalliance.org/workshops-meetings/ 666 | - Location: Munich, Germany 667 | 668 | 669 | ### Workshop on Open-Source EDA Technology (WOSET) 670 | 671 | *"The WOSET workshop aims to galvanize the open-source EDA movement. 672 | The workshop will bring together EDA researchers who are committed to 673 | open-source principles to share their experiences and coordinate efforts 674 | towards developing a reliable, fully open-source EDA flow."* 675 | 676 | - Link: https://woset-workshop.github.io/ 677 | 678 | Often has verification related tools, presentations and papers Submissions (2-4 pages) 679 | can include: 680 | 681 | - Overview of an existing or under-development open-source EDA tool. 682 | - Overview of support infrastructure (e.g. EDA databases and design benchmarks). 683 | - Open-source cloud-based EDA tools 684 | - Position statements (e.g. critical gaps, blockers/obstacles) 685 | --------------------------------------------------------------------------------