├── LICENSE.txt ├── README.md ├── example_project_directory ├── add_two_8bit_buses.v ├── add_two_8bit_buses │ ├── add_two_8bit_buses.v │ ├── answer.json │ ├── out.svg │ └── output.v ├── bcd_to_hex.v ├── bcd_to_hex │ ├── answer.json │ ├── bcd_to_hex.v │ ├── out.svg │ └── output.v ├── cells.lib ├── cells.v ├── cells │ ├── answer.json │ ├── cells.v │ ├── out.svg │ └── output.v ├── comparator_8bit.v ├── comparator_8bit │ ├── answer.json │ ├── comparator_8bit.v │ ├── out.svg │ └── output.v ├── compare_two_8bit_buses.v ├── compare_two_8bit_buses │ ├── answer.json │ ├── compare_two_8bit_buses.v │ ├── out.svg │ └── output.v ├── control_unit_example.v ├── control_unit_example │ ├── answer.json │ ├── control_unit_example.v │ ├── out.svg │ └── output.v ├── default.svg ├── equal_to_one_8bit.v ├── equal_to_one_8bit │ ├── answer.json │ ├── equal_to_one_8bit.v │ ├── out.svg │ └── output.v ├── equal_to_zero_8bit.v ├── equal_to_zero_8bit │ ├── answer.json │ ├── equal_to_zero_8bit.v │ ├── out.svg │ └── output.v ├── logical_and_8bit.v ├── logical_and_8bit │ ├── answer.json │ ├── logical_and_8bit.v │ ├── out.svg │ └── output.v ├── logical_or_8bit.v ├── logical_or_8bit │ ├── answer.json │ ├── logical_or_8bit.v │ ├── out.svg │ └── output.v ├── meme.v ├── meme │ ├── answer.json │ ├── meme.v │ ├── out.svg │ └── output.v ├── multiply.v ├── multiply │ ├── answer.json │ ├── multiply.v │ ├── out.svg │ └── output.v ├── mux2_8bit.v ├── mux2_8bit │ ├── answer.json │ ├── mux2_8bit.v │ ├── out.svg │ └── output.v ├── truth_table.v └── truth_table │ ├── answer.json │ ├── out.svg │ ├── output.v │ └── truth_table.v └── images └── patrick_quote2.svg /LICENSE.txt: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Benjamin Feaster 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | [![Contributors][contributors-shield]][contributors-url] 3 | [![Forks][forks-shield]][forks-url] 4 | [![Stargazers][stars-shield]][stars-url] 5 | [![Issues][issues-shield]][issues-url] 6 | 7 | 8 | 9 | 10 | ```console 11 | # Build from source: 12 | cd ~ 13 | sudo rm -r yosys 14 | mkdir yosys 15 | cd yosys 16 | sudo docker pull ubuntu:latest 17 | sudo docker run -it --rm ubuntu:latest 18 | apt update && apt install git wget -y && wget https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2024-12-26/oss-cad-suite-linux-x64-20241226.tgz && \ 19 | tar -xvzf oss-cad-suite-linux-x64-20241226.tgz 20 | cd oss-cad-suite 21 | source ./environment 22 | apt install npm -y && git clone https://github.com/nturley/netlistsvg 23 | cd netlistsvg 24 | npm install 25 | npm install -g . 26 | npm install elkjs --force 27 | git clone https://github.com/benipoo/yosys-docker.git 28 | cd yosys-docker/example_project_directory/ 29 | rm -R -- */ ; 30 | for file in *.v; do dir=${file%%.*} ; mkdir -p "$dir" ; cp "$file" "$dir" ; cd "$dir" ; yosys -p 'synth -auto-top ; abc -g NAND; write_verilog output.v' "$file" -p 'write_json answer.json'; netlistsvg answer.json ; cd ../ ; done 31 | git add . 32 | git config --global user.email 33 | git commit -m "commit message" 34 | git push 35 | ``` 36 | 37 | 38 | 39 | [contributors-shield]: https://img.shields.io/github/contributors/benipoo/yosys-docker.svg?style=for-the-badge 40 | [contributors-url]: https://github.com/benipoo/yosys-docker/graphs/contributors 41 | [forks-shield]: https://img.shields.io/github/forks/benipoo/yosys-docker.svg?style=for-the-badge 42 | [forks-url]: https://github.com/benipoo/yosys-docker/network/members 43 | [stars-shield]: https://img.shields.io/github/stars/benipoo/yosys-docker.svg?style=for-the-badge 44 | [stars-url]: https://github.com/benipoo/yosys-docker/stargazers 45 | [issues-shield]: https://img.shields.io/github/issues/benipoo/yosys-docker.svg?style=for-the-badge 46 | [issues-url]: https://github.com/benipoo/yosys-docker/issues 47 | -------------------------------------------------------------------------------- /example_project_directory/add_two_8bit_buses.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module add_two_8bit_buses( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output reg [7:0] Y); 8 | 9 | always @(*) 10 | Y = A + B; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /example_project_directory/add_two_8bit_buses/add_two_8bit_buses.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module add_two_8bit_buses( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output reg [7:0] Y); 8 | 9 | always @(*) 10 | Y = A + B; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /example_project_directory/add_two_8bit_buses/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\add_two_8bit_buses" *) 4 | (* top = 1 *) 5 | (* src = "add_two_8bit_buses.v:3.1-12.10" *) 6 | module add_two_8bit_buses(A, B, Y); 7 | wire _000_; 8 | wire _001_; 9 | wire _002_; 10 | wire _003_; 11 | wire _004_; 12 | wire _005_; 13 | wire _006_; 14 | wire _007_; 15 | wire _008_; 16 | wire _009_; 17 | wire _010_; 18 | wire _011_; 19 | wire _012_; 20 | wire _013_; 21 | wire _014_; 22 | wire _015_; 23 | wire _016_; 24 | wire _017_; 25 | wire _018_; 26 | wire _019_; 27 | wire _020_; 28 | wire _021_; 29 | wire _022_; 30 | wire _023_; 31 | wire _024_; 32 | wire _025_; 33 | wire _026_; 34 | wire _027_; 35 | wire _028_; 36 | wire _029_; 37 | wire _030_; 38 | wire _031_; 39 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 40 | wire _032_; 41 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 42 | wire _033_; 43 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 44 | wire _034_; 45 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 46 | wire _035_; 47 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 48 | wire _036_; 49 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 50 | wire _037_; 51 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 52 | wire _038_; 53 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 54 | wire _039_; 55 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 56 | wire _040_; 57 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 58 | wire _041_; 59 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 60 | wire _042_; 61 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 62 | wire _043_; 63 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 64 | wire _044_; 65 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 66 | wire _045_; 67 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 68 | wire _046_; 69 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 70 | wire _047_; 71 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 72 | wire _048_; 73 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 74 | wire _049_; 75 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 76 | wire _050_; 77 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 78 | wire _051_; 79 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 80 | wire _052_; 81 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 82 | wire _053_; 83 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 84 | wire _054_; 85 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 86 | wire _055_; 87 | wire _056_; 88 | wire _057_; 89 | wire _058_; 90 | wire _059_; 91 | wire _060_; 92 | wire _061_; 93 | wire _062_; 94 | wire _063_; 95 | wire _064_; 96 | wire _065_; 97 | wire _066_; 98 | wire _067_; 99 | wire _068_; 100 | wire _069_; 101 | wire _070_; 102 | wire _071_; 103 | wire _072_; 104 | wire _073_; 105 | wire _074_; 106 | wire _075_; 107 | wire _076_; 108 | wire _077_; 109 | wire _078_; 110 | wire _079_; 111 | wire _080_; 112 | wire _081_; 113 | wire _082_; 114 | wire _083_; 115 | wire _084_; 116 | wire _085_; 117 | wire _086_; 118 | wire _087_; 119 | wire _088_; 120 | wire _089_; 121 | wire _090_; 122 | wire _091_; 123 | wire _092_; 124 | wire _093_; 125 | wire _094_; 126 | wire _095_; 127 | wire _096_; 128 | wire _097_; 129 | wire _098_; 130 | wire _099_; 131 | wire _100_; 132 | wire _101_; 133 | wire _102_; 134 | wire _103_; 135 | wire _104_; 136 | wire _105_; 137 | wire _106_; 138 | wire _107_; 139 | wire _108_; 140 | wire _109_; 141 | wire _110_; 142 | wire _111_; 143 | wire _112_; 144 | wire _113_; 145 | wire _114_; 146 | wire _115_; 147 | wire _116_; 148 | wire _117_; 149 | wire _118_; 150 | wire _119_; 151 | wire _120_; 152 | wire _121_; 153 | wire _122_; 154 | wire _123_; 155 | wire _124_; 156 | wire _125_; 157 | wire _126_; 158 | wire _127_; 159 | wire _128_; 160 | wire _129_; 161 | wire _130_; 162 | wire _131_; 163 | wire _132_; 164 | wire _133_; 165 | wire _134_; 166 | wire _135_; 167 | wire _136_; 168 | wire _137_; 169 | wire _138_; 170 | wire _139_; 171 | (* src = "add_two_8bit_buses.v:5.17-5.18" *) 172 | input [7:0] A; 173 | wire [7:0] A; 174 | (* src = "add_two_8bit_buses.v:6.17-6.18" *) 175 | input [7:0] B; 176 | wire [7:0] B; 177 | (* src = "add_two_8bit_buses.v:7.22-7.23" *) 178 | output [7:0] Y; 179 | wire [7:0] Y; 180 | assign _070_ = ~_041_; 181 | assign _071_ = ~_033_; 182 | assign _072_ = ~_040_; 183 | assign _073_ = ~_032_; 184 | assign _074_ = ~_042_; 185 | assign _075_ = ~_034_; 186 | assign _076_ = ~_043_; 187 | assign _077_ = ~_035_; 188 | assign _078_ = ~_044_; 189 | assign _079_ = ~_036_; 190 | assign _080_ = ~_045_; 191 | assign _081_ = ~_037_; 192 | assign _082_ = ~_046_; 193 | assign _083_ = ~_038_; 194 | assign _084_ = ~_047_; 195 | assign _085_ = ~_039_; 196 | assign _086_ = ~(_040_ & _032_); 197 | assign _087_ = ~_086_; 198 | assign _088_ = ~(_041_ & _033_); 199 | assign _089_ = ~(_070_ & _071_); 200 | assign _090_ = ~(_088_ & _089_); 201 | assign _091_ = ~_090_; 202 | assign _092_ = ~(_087_ & _091_); 203 | assign _093_ = ~(_086_ & _090_); 204 | assign _094_ = ~(_092_ & _093_); 205 | assign _049_ = ~_094_; 206 | assign _095_ = ~(_088_ & _092_); 207 | assign _096_ = ~_095_; 208 | assign _097_ = ~(_042_ & _034_); 209 | assign _098_ = ~(_074_ & _075_); 210 | assign _099_ = ~(_097_ & _098_); 211 | assign _100_ = ~_099_; 212 | assign _101_ = ~(_095_ & _100_); 213 | assign _102_ = ~(_096_ & _099_); 214 | assign _103_ = ~(_101_ & _102_); 215 | assign _050_ = ~_103_; 216 | assign _104_ = ~(_097_ & _101_); 217 | assign _105_ = ~_104_; 218 | assign _106_ = ~(_043_ & _035_); 219 | assign _107_ = ~(_076_ & _077_); 220 | assign _108_ = ~(_106_ & _107_); 221 | assign _109_ = ~_108_; 222 | assign _110_ = ~(_105_ & _109_); 223 | assign _111_ = ~(_104_ & _108_); 224 | assign _051_ = ~(_110_ & _111_); 225 | assign _112_ = ~(_044_ & _036_); 226 | assign _113_ = ~(_078_ & _079_); 227 | assign _114_ = ~(_112_ & _113_); 228 | assign _115_ = ~_114_; 229 | assign _116_ = ~(_104_ & _107_); 230 | assign _117_ = ~(_105_ & _106_); 231 | assign _118_ = ~(_107_ & _117_); 232 | assign _119_ = ~(_106_ & _116_); 233 | assign _120_ = ~(_115_ & _119_); 234 | assign _121_ = ~(_114_ & _118_); 235 | assign _122_ = ~(_120_ & _121_); 236 | assign _052_ = ~_122_; 237 | assign _123_ = ~(_112_ & _120_); 238 | assign _124_ = ~_123_; 239 | assign _125_ = ~(_045_ & _037_); 240 | assign _126_ = ~(_080_ & _081_); 241 | assign _127_ = ~(_125_ & _126_); 242 | assign _128_ = ~_127_; 243 | assign _129_ = ~(_123_ & _127_); 244 | assign _130_ = ~(_124_ & _128_); 245 | assign _053_ = ~(_129_ & _130_); 246 | assign _131_ = ~(_046_ & _038_); 247 | assign _132_ = ~(_082_ & _083_); 248 | assign _133_ = ~(_131_ & _132_); 249 | assign _134_ = ~_133_; 250 | assign _135_ = ~(_123_ & _126_); 251 | assign _136_ = ~(_124_ & _125_); 252 | assign _137_ = ~(_126_ & _136_); 253 | assign _138_ = ~(_125_ & _135_); 254 | assign _139_ = ~(_134_ & _138_); 255 | assign _056_ = ~(_133_ & _137_); 256 | assign _057_ = ~(_139_ & _056_); 257 | assign _054_ = ~_057_; 258 | assign _058_ = ~(_131_ & _139_); 259 | assign _059_ = ~_058_; 260 | assign _060_ = ~(_084_ & _085_); 261 | assign _061_ = ~(_047_ & _039_); 262 | assign _062_ = ~(_047_ & _085_); 263 | assign _063_ = ~(_084_ & _039_); 264 | assign _064_ = ~(_062_ & _063_); 265 | assign _065_ = ~(_060_ & _061_); 266 | assign _066_ = ~(_059_ & _064_); 267 | assign _067_ = ~(_058_ & _065_); 268 | assign _055_ = ~(_066_ & _067_); 269 | assign _068_ = ~(_072_ & _073_); 270 | assign _069_ = ~(_086_ & _068_); 271 | assign _048_ = ~_069_; 272 | assign _041_ = B[1]; 273 | assign _033_ = A[1]; 274 | assign _040_ = B[0]; 275 | assign _032_ = A[0]; 276 | assign Y[1] = _049_; 277 | assign _042_ = B[2]; 278 | assign _034_ = A[2]; 279 | assign Y[2] = _050_; 280 | assign _043_ = B[3]; 281 | assign _035_ = A[3]; 282 | assign Y[3] = _051_; 283 | assign _044_ = B[4]; 284 | assign _036_ = A[4]; 285 | assign Y[4] = _052_; 286 | assign _045_ = B[5]; 287 | assign _037_ = A[5]; 288 | assign Y[5] = _053_; 289 | assign _046_ = B[6]; 290 | assign _038_ = A[6]; 291 | assign Y[6] = _054_; 292 | assign _047_ = B[7]; 293 | assign _039_ = A[7]; 294 | assign Y[7] = _055_; 295 | assign Y[0] = _048_; 296 | endmodule 297 | -------------------------------------------------------------------------------- /example_project_directory/bcd_to_hex.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module bcd_to_7seg( 4 | 5 | input [3:0] bcd, 6 | output reg [6:0] seg); 7 | 8 | always @(*) 9 | begin 10 | case (bcd) 11 | 0 : seg = 7'b1111110; 12 | 1 : seg = 7'b0110000; 13 | 2 : seg = 7'b1101101; 14 | 3 : seg = 7'b1111001; 15 | 4 : seg = 7'b0110011; 16 | 5 : seg = 7'b1011011; 17 | 6 : seg = 7'b1011111; 18 | 7 : seg = 7'b1110000; 19 | 8 : seg = 7'b1111111; 20 | 9 : seg = 7'b1110011; 21 | 10 : seg = 7'b1110111; 22 | 11 : seg = 7'b0011111; 23 | 12 : seg = 7'b1001110; 24 | 13 : seg = 7'b0111101; 25 | 14 : seg = 7'b1001111; 26 | 15 : seg = 7'b1000111; 27 | endcase 28 | end 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /example_project_directory/bcd_to_hex/bcd_to_hex.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module bcd_to_7seg( 4 | 5 | input [3:0] bcd, 6 | output reg [6:0] seg); 7 | 8 | always @(*) 9 | begin 10 | case (bcd) 11 | 0 : seg = 7'b1111110; 12 | 1 : seg = 7'b0110000; 13 | 2 : seg = 7'b1101101; 14 | 3 : seg = 7'b1111001; 15 | 4 : seg = 7'b0110011; 16 | 5 : seg = 7'b1011011; 17 | 6 : seg = 7'b1011111; 18 | 7 : seg = 7'b1110000; 19 | 8 : seg = 7'b1111111; 20 | 9 : seg = 7'b1110011; 21 | 10 : seg = 7'b1110111; 22 | 11 : seg = 7'b0011111; 23 | 12 : seg = 7'b1001110; 24 | 13 : seg = 7'b0111101; 25 | 14 : seg = 7'b1001111; 26 | 15 : seg = 7'b1000111; 27 | endcase 28 | end 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /example_project_directory/bcd_to_hex/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\bcd_to_7seg" *) 4 | (* top = 1 *) 5 | (* src = "bcd_to_hex.v:3.1-29.10" *) 6 | module bcd_to_7seg(bcd, seg); 7 | wire _000_; 8 | wire _001_; 9 | wire _002_; 10 | wire _003_; 11 | wire _004_; 12 | wire _005_; 13 | wire _006_; 14 | wire _007_; 15 | wire _008_; 16 | wire _009_; 17 | wire _010_; 18 | wire _011_; 19 | wire _012_; 20 | wire _013_; 21 | wire _014_; 22 | wire _015_; 23 | wire _016_; 24 | wire _017_; 25 | wire _018_; 26 | wire _019_; 27 | wire _020_; 28 | wire _021_; 29 | wire _022_; 30 | wire _023_; 31 | wire _024_; 32 | (* src = "bcd_to_hex.v:5.14-5.17" *) 33 | wire _025_; 34 | (* src = "bcd_to_hex.v:5.14-5.17" *) 35 | wire _026_; 36 | (* src = "bcd_to_hex.v:5.14-5.17" *) 37 | wire _027_; 38 | (* src = "bcd_to_hex.v:5.14-5.17" *) 39 | wire _028_; 40 | wire _029_; 41 | wire _030_; 42 | wire _031_; 43 | wire _032_; 44 | wire _033_; 45 | wire _034_; 46 | wire _035_; 47 | wire _036_; 48 | wire _037_; 49 | wire _038_; 50 | wire _039_; 51 | wire _040_; 52 | wire _041_; 53 | wire _042_; 54 | wire _043_; 55 | wire _044_; 56 | wire _045_; 57 | wire _046_; 58 | wire _047_; 59 | wire _048_; 60 | wire _049_; 61 | wire _050_; 62 | wire _051_; 63 | wire _052_; 64 | wire _053_; 65 | wire _054_; 66 | wire _055_; 67 | wire _056_; 68 | wire _057_; 69 | wire _058_; 70 | wire _059_; 71 | wire _060_; 72 | wire _061_; 73 | wire _062_; 74 | wire _063_; 75 | wire _064_; 76 | wire _065_; 77 | wire _066_; 78 | wire _067_; 79 | wire _068_; 80 | wire _069_; 81 | wire _070_; 82 | wire _071_; 83 | wire _072_; 84 | wire _073_; 85 | wire _074_; 86 | wire _075_; 87 | wire _076_; 88 | wire _077_; 89 | wire _078_; 90 | wire _079_; 91 | wire _080_; 92 | wire _081_; 93 | wire _082_; 94 | (* src = "bcd_to_hex.v:6.19-6.22" *) 95 | wire _083_; 96 | (* src = "bcd_to_hex.v:6.19-6.22" *) 97 | wire _084_; 98 | (* src = "bcd_to_hex.v:6.19-6.22" *) 99 | wire _085_; 100 | (* src = "bcd_to_hex.v:6.19-6.22" *) 101 | wire _086_; 102 | (* src = "bcd_to_hex.v:6.19-6.22" *) 103 | wire _087_; 104 | (* src = "bcd_to_hex.v:6.19-6.22" *) 105 | wire _088_; 106 | (* src = "bcd_to_hex.v:6.19-6.22" *) 107 | wire _089_; 108 | (* src = "bcd_to_hex.v:5.14-5.17" *) 109 | input [3:0] bcd; 110 | wire [3:0] bcd; 111 | (* src = "bcd_to_hex.v:6.19-6.22" *) 112 | output [6:0] seg; 113 | wire [6:0] seg; 114 | assign _029_ = ~_027_; 115 | assign _030_ = ~_025_; 116 | assign _031_ = ~_026_; 117 | assign _032_ = ~_028_; 118 | assign _033_ = ~(_027_ & _031_); 119 | assign _034_ = ~_033_; 120 | assign _035_ = ~(_028_ & _034_); 121 | assign _036_ = ~_035_; 122 | assign _037_ = ~(_030_ & _036_); 123 | assign _038_ = ~(_025_ & _026_); 124 | assign _039_ = ~(_027_ & _038_); 125 | assign _040_ = ~(_029_ & _026_); 126 | assign _041_ = ~_040_; 127 | assign _042_ = ~(_032_ & _040_); 128 | assign _043_ = ~_042_; 129 | assign _044_ = ~(_039_ & _043_); 130 | assign _045_ = ~(_037_ & _044_); 131 | assign _083_ = ~_045_; 132 | assign _046_ = ~(_025_ & _036_); 133 | assign _047_ = ~(_030_ & _031_); 134 | assign _048_ = ~(_032_ & _047_); 135 | assign _049_ = ~_048_; 136 | assign _050_ = ~(_039_ & _049_); 137 | assign _051_ = ~(_046_ & _050_); 138 | assign _084_ = ~_051_; 139 | assign _052_ = ~(_030_ & _033_); 140 | assign _053_ = ~_052_; 141 | assign _054_ = ~(_029_ & _031_); 142 | assign _055_ = ~(_028_ & _054_); 143 | assign _085_ = ~(_052_ & _055_); 144 | assign _056_ = ~(_030_ & _032_); 145 | assign _057_ = ~(_033_ & _040_); 146 | assign _058_ = ~(_056_ & _057_); 147 | assign _059_ = ~_058_; 148 | assign _060_ = ~(_053_ & _058_); 149 | assign _061_ = ~(_052_ & _059_); 150 | assign _062_ = ~(_025_ & _031_); 151 | assign _063_ = ~(_029_ & _062_); 152 | assign _064_ = ~(_027_ & _047_); 153 | assign _065_ = ~_064_; 154 | assign _066_ = ~(_038_ & _065_); 155 | assign _067_ = ~(_032_ & _066_); 156 | assign _086_ = ~(_060_ & _061_); 157 | assign _068_ = ~(_027_ & _062_); 158 | assign _069_ = ~(_028_ & _068_); 159 | assign _070_ = ~_069_; 160 | assign _071_ = ~(_030_ & _041_); 161 | assign _072_ = ~(_032_ & _071_); 162 | assign _087_ = ~(_069_ & _072_); 163 | assign _073_ = ~(_029_ & _038_); 164 | assign _074_ = ~_073_; 165 | assign _075_ = ~(_028_ & _074_); 166 | assign _076_ = ~(_032_ & _064_); 167 | assign _077_ = ~_076_; 168 | assign _078_ = ~(_046_ & _067_); 169 | assign _079_ = ~_078_; 170 | assign _088_ = ~(_075_ & _079_); 171 | assign _080_ = ~(_070_ & _073_); 172 | assign _081_ = ~(_063_ & _077_); 173 | assign _082_ = ~(_080_ & _081_); 174 | assign _089_ = ~_082_; 175 | assign _027_ = bcd[2]; 176 | assign _025_ = bcd[0]; 177 | assign _026_ = bcd[1]; 178 | assign _028_ = bcd[3]; 179 | assign seg[0] = _083_; 180 | assign seg[1] = _084_; 181 | assign seg[2] = _085_; 182 | assign seg[3] = _086_; 183 | assign seg[4] = _087_; 184 | assign seg[5] = _088_; 185 | assign seg[6] = _089_; 186 | endmodule 187 | -------------------------------------------------------------------------------- /example_project_directory/cells.lib: -------------------------------------------------------------------------------- 1 | // test comment 2 | /* test comment */ 3 | library(cells) { 4 | cell(BUF) { 5 | area: 1; 6 | pin(A) { direction: input; } 7 | pin(Y) { direction: output; 8 | function: "A"; } 9 | } 10 | 11 | cell(NAND2) { 12 | area: 2; 13 | pin(A) { direction: input; } 14 | pin(B) { direction: input; } 15 | pin(Y) { direction: output; 16 | function: "(A*B)'"; } 17 | } 18 | cell(DFF) { 19 | area: 18; 20 | ff(IQ, IQN) { clocked_on: C; 21 | next_state: D; } 22 | pin(C) { direction: input; 23 | clock: true; } 24 | pin(D) { direction: input; } 25 | pin(Q) { direction: output; 26 | function: "IQ"; } 27 | } 28 | } 29 | 30 | -------------------------------------------------------------------------------- /example_project_directory/cells.v: -------------------------------------------------------------------------------- 1 | 2 | module BUF(A, Y); 3 | input A; 4 | output Y; 5 | assign Y = A; 6 | endmodule 7 | 8 | module NAND2(A, B, Y); 9 | input A, B; 10 | output Y; 11 | assign Y = ~(A & B); 12 | endmodule 13 | 14 | module DFF(C, D, Q); 15 | input C, D; 16 | output reg Q; 17 | always @(posedge C) 18 | Q <= D; 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /example_project_directory/cells/answer.json: -------------------------------------------------------------------------------- 1 | { 2 | "creator": "Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os)", 3 | "modules": { 4 | "DFF": { 5 | "attributes": { 6 | "hdlname": "\\DFF", 7 | "top": "00000000000000000000000000000001", 8 | "src": "cells.v:14.1-19.10" 9 | }, 10 | "ports": { 11 | "C": { 12 | "direction": "input", 13 | "bits": [ 2 ] 14 | }, 15 | "D": { 16 | "direction": "input", 17 | "bits": [ 3 ] 18 | }, 19 | "Q": { 20 | "direction": "output", 21 | "bits": [ 4 ] 22 | } 23 | }, 24 | "cells": { 25 | "$auto$ff.cc:266:slice$80": { 26 | "hide_name": 1, 27 | "type": "$_DFF_P_", 28 | "parameters": { 29 | }, 30 | "attributes": { 31 | "src": "cells.v:17.1-18.9" 32 | }, 33 | "port_directions": { 34 | "C": "input", 35 | "D": "input", 36 | "Q": "output" 37 | }, 38 | "connections": { 39 | "C": [ 2 ], 40 | "D": [ 3 ], 41 | "Q": [ 4 ] 42 | } 43 | } 44 | }, 45 | "netnames": { 46 | "C": { 47 | "hide_name": 0, 48 | "bits": [ 2 ], 49 | "attributes": { 50 | "src": "cells.v:15.7-15.8" 51 | } 52 | }, 53 | "D": { 54 | "hide_name": 0, 55 | "bits": [ 3 ], 56 | "attributes": { 57 | "src": "cells.v:15.10-15.11" 58 | } 59 | }, 60 | "Q": { 61 | "hide_name": 0, 62 | "bits": [ 4 ], 63 | "attributes": { 64 | "src": "cells.v:16.12-16.13" 65 | } 66 | } 67 | } 68 | } 69 | } 70 | } 71 | -------------------------------------------------------------------------------- /example_project_directory/cells/cells.v: -------------------------------------------------------------------------------- 1 | 2 | module BUF(A, Y); 3 | input A; 4 | output Y; 5 | assign Y = A; 6 | endmodule 7 | 8 | module NAND2(A, B, Y); 9 | input A, B; 10 | output Y; 11 | assign Y = ~(A & B); 12 | endmodule 13 | 14 | module DFF(C, D, Q); 15 | input C, D; 16 | output reg Q; 17 | always @(posedge C) 18 | Q <= D; 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /example_project_directory/cells/out.svg: -------------------------------------------------------------------------------- 1 | CDQ -------------------------------------------------------------------------------- /example_project_directory/cells/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\DFF" *) 4 | (* top = 1 *) 5 | (* src = "cells.v:14.1-19.10" *) 6 | module DFF(C, D, Q); 7 | (* src = "cells.v:15.7-15.8" *) 8 | input C; 9 | wire C; 10 | (* src = "cells.v:15.10-15.11" *) 11 | input D; 12 | wire D; 13 | (* src = "cells.v:16.12-16.13" *) 14 | output Q; 15 | reg Q; 16 | (* src = "cells.v:17.1-18.9" *) 17 | always @(posedge C) 18 | Q <= D; 19 | endmodule 20 | -------------------------------------------------------------------------------- /example_project_directory/comparator_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module comparator_8bit( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output reg Y); 8 | 9 | always @(*) 10 | if(A > B) 11 | begin 12 | Y = 1; 13 | end 14 | else 15 | begin 16 | Y = 0; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /example_project_directory/comparator_8bit/comparator_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module comparator_8bit( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output reg Y); 8 | 9 | always @(*) 10 | if(A > B) 11 | begin 12 | Y = 1; 13 | end 14 | else 15 | begin 16 | Y = 0; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /example_project_directory/comparator_8bit/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\comparator_8bit" *) 4 | (* top = 1 *) 5 | (* src = "comparator_8bit.v:3.1-18.10" *) 6 | module comparator_8bit(A, B, Y); 7 | wire _000_; 8 | wire _001_; 9 | wire _002_; 10 | wire _003_; 11 | wire _004_; 12 | wire _005_; 13 | wire _006_; 14 | wire _007_; 15 | wire _008_; 16 | wire _009_; 17 | wire _010_; 18 | wire _011_; 19 | wire _012_; 20 | wire _013_; 21 | wire _014_; 22 | wire _015_; 23 | wire _016_; 24 | wire _017_; 25 | wire _018_; 26 | wire _019_; 27 | wire _020_; 28 | wire _021_; 29 | wire _022_; 30 | wire _023_; 31 | wire _024_; 32 | wire _025_; 33 | wire _026_; 34 | wire _027_; 35 | wire _028_; 36 | wire _029_; 37 | wire _030_; 38 | wire _031_; 39 | wire _032_; 40 | wire _033_; 41 | wire _034_; 42 | wire _035_; 43 | wire _036_; 44 | (* src = "comparator_8bit.v:5.19-5.20" *) 45 | wire _037_; 46 | (* src = "comparator_8bit.v:5.19-5.20" *) 47 | wire _038_; 48 | (* src = "comparator_8bit.v:5.19-5.20" *) 49 | wire _039_; 50 | (* src = "comparator_8bit.v:5.19-5.20" *) 51 | wire _040_; 52 | (* src = "comparator_8bit.v:5.19-5.20" *) 53 | wire _041_; 54 | (* src = "comparator_8bit.v:5.19-5.20" *) 55 | wire _042_; 56 | (* src = "comparator_8bit.v:5.19-5.20" *) 57 | wire _043_; 58 | (* src = "comparator_8bit.v:5.19-5.20" *) 59 | wire _044_; 60 | (* src = "comparator_8bit.v:6.15-6.16" *) 61 | wire _045_; 62 | (* src = "comparator_8bit.v:6.15-6.16" *) 63 | wire _046_; 64 | (* src = "comparator_8bit.v:6.15-6.16" *) 65 | wire _047_; 66 | (* src = "comparator_8bit.v:6.15-6.16" *) 67 | wire _048_; 68 | (* src = "comparator_8bit.v:6.15-6.16" *) 69 | wire _049_; 70 | (* src = "comparator_8bit.v:6.15-6.16" *) 71 | wire _050_; 72 | (* src = "comparator_8bit.v:6.15-6.16" *) 73 | wire _051_; 74 | (* src = "comparator_8bit.v:6.15-6.16" *) 75 | wire _052_; 76 | (* src = "comparator_8bit.v:7.18-7.19" *) 77 | wire _053_; 78 | wire _054_; 79 | wire _055_; 80 | wire _056_; 81 | wire _057_; 82 | wire _058_; 83 | wire _059_; 84 | wire _060_; 85 | wire _061_; 86 | wire _062_; 87 | wire _063_; 88 | wire _064_; 89 | wire _065_; 90 | wire _066_; 91 | wire _067_; 92 | wire _068_; 93 | wire _069_; 94 | wire _070_; 95 | wire _071_; 96 | wire _072_; 97 | wire _073_; 98 | wire _074_; 99 | wire _075_; 100 | wire _076_; 101 | wire _077_; 102 | wire _078_; 103 | wire _079_; 104 | wire _080_; 105 | wire _081_; 106 | wire _082_; 107 | wire _083_; 108 | wire _084_; 109 | wire _085_; 110 | wire _086_; 111 | wire _087_; 112 | wire _088_; 113 | wire _089_; 114 | wire _090_; 115 | wire _091_; 116 | wire _092_; 117 | wire _093_; 118 | wire _094_; 119 | wire _095_; 120 | wire _096_; 121 | wire _097_; 122 | wire _098_; 123 | wire _099_; 124 | wire _100_; 125 | wire _101_; 126 | wire _102_; 127 | wire _103_; 128 | wire _104_; 129 | wire _105_; 130 | wire _106_; 131 | wire _107_; 132 | wire _108_; 133 | wire _109_; 134 | wire _110_; 135 | wire _111_; 136 | wire _112_; 137 | wire _113_; 138 | wire _114_; 139 | wire _115_; 140 | wire _116_; 141 | wire _117_; 142 | wire _118_; 143 | wire _119_; 144 | wire _120_; 145 | wire _121_; 146 | wire _122_; 147 | wire _123_; 148 | wire _124_; 149 | wire _125_; 150 | wire _126_; 151 | wire _127_; 152 | wire _128_; 153 | wire _129_; 154 | wire _130_; 155 | (* src = "comparator_8bit.v:5.19-5.20" *) 156 | input [7:0] A; 157 | wire [7:0] A; 158 | (* src = "comparator_8bit.v:6.15-6.16" *) 159 | input [7:0] B; 160 | wire [7:0] B; 161 | (* src = "comparator_8bit.v:7.18-7.19" *) 162 | output Y; 163 | wire Y; 164 | assign _054_ = ~_044_; 165 | assign _055_ = ~_052_; 166 | assign _056_ = ~_051_; 167 | assign _057_ = ~_043_; 168 | assign _058_ = ~_050_; 169 | assign _059_ = ~_042_; 170 | assign _060_ = ~_041_; 171 | assign _061_ = ~_049_; 172 | assign _062_ = ~_048_; 173 | assign _063_ = ~_040_; 174 | assign _064_ = ~_047_; 175 | assign _065_ = ~_039_; 176 | assign _066_ = ~_046_; 177 | assign _067_ = ~_038_; 178 | assign _068_ = ~_037_; 179 | assign _069_ = ~_045_; 180 | assign _070_ = ~(_044_ & _055_); 181 | assign _071_ = ~(_056_ & _043_); 182 | assign _072_ = ~(_070_ & _071_); 183 | assign _073_ = ~_072_; 184 | assign _074_ = ~(_051_ & _057_); 185 | assign _075_ = ~(_054_ & _052_); 186 | assign _076_ = ~(_074_ & _075_); 187 | assign _077_ = ~_076_; 188 | assign _078_ = ~(_073_ & _077_); 189 | assign _079_ = ~_078_; 190 | assign _080_ = ~(_041_ & _061_); 191 | assign _081_ = ~(_058_ & _042_); 192 | assign _082_ = ~(_080_ & _081_); 193 | assign _083_ = ~_082_; 194 | assign _084_ = ~(_050_ & _059_); 195 | assign _085_ = ~(_060_ & _049_); 196 | assign _086_ = ~(_084_ & _085_); 197 | assign _087_ = ~_086_; 198 | assign _088_ = ~(_083_ & _087_); 199 | assign _089_ = ~_088_; 200 | assign _090_ = ~(_079_ & _089_); 201 | assign _091_ = ~_090_; 202 | assign _092_ = ~(_048_ & _063_); 203 | assign _093_ = ~(_062_ & _040_); 204 | assign _094_ = ~(_092_ & _093_); 205 | assign _095_ = ~_094_; 206 | assign _096_ = ~(_064_ & _039_); 207 | assign _097_ = ~_096_; 208 | assign _098_ = ~(_047_ & _065_); 209 | assign _099_ = ~(_096_ & _098_); 210 | assign _100_ = ~_099_; 211 | assign _101_ = ~(_095_ & _100_); 212 | assign _102_ = ~_101_; 213 | assign _103_ = ~(_066_ & _038_); 214 | assign _104_ = ~(_046_ & _067_); 215 | assign _105_ = ~(_068_ & _045_); 216 | assign _106_ = ~(_103_ & _105_); 217 | assign _107_ = ~_106_; 218 | assign _108_ = ~(_104_ & _107_); 219 | assign _109_ = ~_108_; 220 | assign _110_ = ~(_103_ & _108_); 221 | assign _111_ = ~(_102_ & _110_); 222 | assign _112_ = ~(_092_ & _097_); 223 | assign _113_ = ~(_093_ & _112_); 224 | assign _114_ = ~_113_; 225 | assign _115_ = ~(_111_ & _114_); 226 | assign _116_ = ~(_091_ & _115_); 227 | assign _117_ = ~(_082_ & _084_); 228 | assign _118_ = ~_117_; 229 | assign _119_ = ~(_079_ & _118_); 230 | assign _120_ = ~(_072_ & _075_); 231 | assign _121_ = ~(_119_ & _120_); 232 | assign _122_ = ~_121_; 233 | assign _123_ = ~(_116_ & _122_); 234 | assign _124_ = ~(_037_ & _069_); 235 | assign _125_ = ~(_102_ & _124_); 236 | assign _126_ = ~_125_; 237 | assign _127_ = ~(_091_ & _126_); 238 | assign _128_ = ~_127_; 239 | assign _129_ = ~(_109_ & _128_); 240 | assign _130_ = ~(_123_ & _129_); 241 | assign _053_ = ~_130_; 242 | assign _044_ = A[7]; 243 | assign _052_ = B[7]; 244 | assign _051_ = B[6]; 245 | assign _043_ = A[6]; 246 | assign _050_ = B[5]; 247 | assign _042_ = A[5]; 248 | assign _041_ = A[4]; 249 | assign _049_ = B[4]; 250 | assign _048_ = B[3]; 251 | assign _040_ = A[3]; 252 | assign _047_ = B[2]; 253 | assign _039_ = A[2]; 254 | assign _046_ = B[1]; 255 | assign _038_ = A[1]; 256 | assign _037_ = A[0]; 257 | assign _045_ = B[0]; 258 | assign Y = _053_; 259 | endmodule 260 | -------------------------------------------------------------------------------- /example_project_directory/compare_two_8bit_buses.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module compare_two_8bit_buses( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output reg Y); 8 | 9 | always @(*) 10 | if(A == B) 11 | Y = 1; 12 | else 13 | Y = 0; 14 | endmodule 15 | -------------------------------------------------------------------------------- /example_project_directory/compare_two_8bit_buses/compare_two_8bit_buses.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module compare_two_8bit_buses( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output reg Y); 8 | 9 | always @(*) 10 | if(A == B) 11 | Y = 1; 12 | else 13 | Y = 0; 14 | endmodule 15 | -------------------------------------------------------------------------------- /example_project_directory/compare_two_8bit_buses/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\compare_two_8bit_buses" *) 4 | (* top = 1 *) 5 | (* src = "compare_two_8bit_buses.v:3.1-14.10" *) 6 | module compare_two_8bit_buses(A, B, Y); 7 | wire _000_; 8 | wire _001_; 9 | wire _002_; 10 | wire _003_; 11 | wire _004_; 12 | wire _005_; 13 | wire _006_; 14 | wire _007_; 15 | wire _008_; 16 | wire _009_; 17 | wire _010_; 18 | wire _011_; 19 | wire _012_; 20 | wire _013_; 21 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 22 | wire _014_; 23 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 24 | wire _015_; 25 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 26 | wire _016_; 27 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 28 | wire _017_; 29 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 30 | wire _018_; 31 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 32 | wire _019_; 33 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 34 | wire _020_; 35 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 36 | wire _021_; 37 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 38 | wire _022_; 39 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 40 | wire _023_; 41 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 42 | wire _024_; 43 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 44 | wire _025_; 45 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 46 | wire _026_; 47 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 48 | wire _027_; 49 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 50 | wire _028_; 51 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 52 | wire _029_; 53 | (* src = "compare_two_8bit_buses.v:7.16-7.17" *) 54 | wire _030_; 55 | wire _031_; 56 | wire _032_; 57 | wire _033_; 58 | wire _034_; 59 | wire _035_; 60 | wire _036_; 61 | wire _037_; 62 | wire _038_; 63 | wire _039_; 64 | wire _040_; 65 | wire _041_; 66 | wire _042_; 67 | wire _043_; 68 | wire _044_; 69 | wire _045_; 70 | wire _046_; 71 | wire _047_; 72 | wire _048_; 73 | wire _049_; 74 | wire _050_; 75 | wire _051_; 76 | wire _052_; 77 | wire _053_; 78 | wire _054_; 79 | wire _055_; 80 | wire _056_; 81 | wire _057_; 82 | wire _058_; 83 | wire _059_; 84 | wire _060_; 85 | wire _061_; 86 | wire _062_; 87 | wire _063_; 88 | wire _064_; 89 | wire _065_; 90 | wire _066_; 91 | wire _067_; 92 | wire _068_; 93 | wire _069_; 94 | wire _070_; 95 | wire _071_; 96 | wire _072_; 97 | wire _073_; 98 | wire _074_; 99 | wire _075_; 100 | wire _076_; 101 | wire _077_; 102 | wire _078_; 103 | wire _079_; 104 | wire _080_; 105 | wire _081_; 106 | wire _082_; 107 | wire _083_; 108 | wire _084_; 109 | wire _085_; 110 | wire _086_; 111 | (* src = "compare_two_8bit_buses.v:5.17-5.18" *) 112 | input [7:0] A; 113 | wire [7:0] A; 114 | (* src = "compare_two_8bit_buses.v:6.17-6.18" *) 115 | input [7:0] B; 116 | wire [7:0] B; 117 | (* src = "compare_two_8bit_buses.v:7.16-7.17" *) 118 | output Y; 119 | wire Y; 120 | assign _031_ = ~_022_; 121 | assign _032_ = ~_014_; 122 | assign _033_ = ~_023_; 123 | assign _034_ = ~_015_; 124 | assign _035_ = ~_024_; 125 | assign _036_ = ~_016_; 126 | assign _037_ = ~_025_; 127 | assign _038_ = ~_017_; 128 | assign _039_ = ~_026_; 129 | assign _040_ = ~_018_; 130 | assign _041_ = ~_027_; 131 | assign _042_ = ~_019_; 132 | assign _043_ = ~_028_; 133 | assign _044_ = ~_020_; 134 | assign _045_ = ~_029_; 135 | assign _046_ = ~_021_; 136 | assign _047_ = ~(_027_ & _042_); 137 | assign _048_ = ~(_041_ & _019_); 138 | assign _049_ = ~(_047_ & _048_); 139 | assign _050_ = ~_049_; 140 | assign _051_ = ~(_028_ & _044_); 141 | assign _052_ = ~(_043_ & _020_); 142 | assign _053_ = ~(_051_ & _052_); 143 | assign _054_ = ~_053_; 144 | assign _055_ = ~(_050_ & _054_); 145 | assign _056_ = ~_055_; 146 | assign _057_ = ~(_022_ & _014_); 147 | assign _058_ = ~(_031_ & _032_); 148 | assign _059_ = ~(_057_ & _058_); 149 | assign _060_ = ~(_029_ & _021_); 150 | assign _061_ = ~(_045_ & _046_); 151 | assign _062_ = ~(_060_ & _061_); 152 | assign _063_ = ~(_023_ & _015_); 153 | assign _064_ = ~(_033_ & _034_); 154 | assign _065_ = ~(_063_ & _064_); 155 | assign _066_ = ~(_039_ & _040_); 156 | assign _067_ = ~(_026_ & _018_); 157 | assign _068_ = ~(_066_ & _067_); 158 | assign _069_ = ~(_065_ & _068_); 159 | assign _070_ = ~_069_; 160 | assign _071_ = ~(_035_ & _036_); 161 | assign _072_ = ~(_024_ & _016_); 162 | assign _073_ = ~(_071_ & _072_); 163 | assign _074_ = ~(_025_ & _038_); 164 | assign _075_ = ~(_037_ & _017_); 165 | assign _076_ = ~(_074_ & _075_); 166 | assign _077_ = ~_076_; 167 | assign _078_ = ~(_056_ & _070_); 168 | assign _079_ = ~_078_; 169 | assign _080_ = ~(_059_ & _073_); 170 | assign _081_ = ~_080_; 171 | assign _082_ = ~(_062_ & _077_); 172 | assign _083_ = ~_082_; 173 | assign _084_ = ~(_081_ & _083_); 174 | assign _085_ = ~_084_; 175 | assign _086_ = ~(_079_ & _085_); 176 | assign _030_ = ~_086_; 177 | assign _022_ = B[0]; 178 | assign _014_ = A[0]; 179 | assign _023_ = B[1]; 180 | assign _015_ = A[1]; 181 | assign _024_ = B[2]; 182 | assign _016_ = A[2]; 183 | assign _025_ = B[3]; 184 | assign _017_ = A[3]; 185 | assign _026_ = B[4]; 186 | assign _018_ = A[4]; 187 | assign _027_ = B[5]; 188 | assign _019_ = A[5]; 189 | assign _028_ = B[6]; 190 | assign _020_ = A[6]; 191 | assign _029_ = B[7]; 192 | assign _021_ = A[7]; 193 | assign Y = _030_; 194 | endmodule 195 | -------------------------------------------------------------------------------- /example_project_directory/control_unit_example.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module control_unit_example( 4 | input A, 5 | input B, 6 | input C, 7 | input D, 8 | input E, 9 | output reg CTRL0, 10 | output reg CTRL1, 11 | output reg CTRL2, 12 | output reg CTRL3, 13 | output reg CTRL4, 14 | output reg CTRL5, 15 | output reg CTRL6, 16 | output reg CTRL7); 17 | 18 | always @(*) 19 | begin 20 | if (A == 1) 21 | begin 22 | CTRL0 = 1; 23 | CTRL1 = 0; 24 | CTRL2 = 1; 25 | CTRL3 = 1; 26 | CTRL4 = 0; 27 | CTRL5 = 1; 28 | CTRL6 = 1; 29 | CTRL7 = 1; 30 | end 31 | else if (B == 1) 32 | begin 33 | CTRL0 = 0; 34 | CTRL1 = 1; 35 | CTRL2 = 0; 36 | CTRL3 = 1; 37 | CTRL4 = 1; 38 | CTRL5 = 1; 39 | CTRL6 = 0; 40 | CTRL7 = 0; 41 | end 42 | else if (C == 1) 43 | begin 44 | CTRL0 = 1; 45 | CTRL1 = 0; 46 | CTRL2 = 0; 47 | CTRL3 = 1; 48 | CTRL4 = 0; 49 | CTRL5 = 1; 50 | CTRL6 = 1; 51 | CTRL7 = 1; 52 | end 53 | else 54 | if ((D == 1)) 55 | begin 56 | CTRL0 = 0; 57 | CTRL1 = 1; 58 | CTRL2 = 0; 59 | CTRL3 = 1; 60 | CTRL4 = 1; 61 | CTRL5 = 1; 62 | CTRL6 = 0; 63 | CTRL7 = 0; 64 | end 65 | else if ((E == 0)) 66 | begin 67 | CTRL0 = 0; 68 | CTRL1 = 0; 69 | CTRL2 = 0; 70 | CTRL3 = 0; 71 | CTRL4 = 1; 72 | CTRL5 = 0; 73 | CTRL6 = 1; 74 | CTRL7 = 0; 75 | end 76 | end 77 | endmodule 78 | -------------------------------------------------------------------------------- /example_project_directory/control_unit_example/control_unit_example.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module control_unit_example( 4 | input A, 5 | input B, 6 | input C, 7 | input D, 8 | input E, 9 | output reg CTRL0, 10 | output reg CTRL1, 11 | output reg CTRL2, 12 | output reg CTRL3, 13 | output reg CTRL4, 14 | output reg CTRL5, 15 | output reg CTRL6, 16 | output reg CTRL7); 17 | 18 | always @(*) 19 | begin 20 | if (A == 1) 21 | begin 22 | CTRL0 = 1; 23 | CTRL1 = 0; 24 | CTRL2 = 1; 25 | CTRL3 = 1; 26 | CTRL4 = 0; 27 | CTRL5 = 1; 28 | CTRL6 = 1; 29 | CTRL7 = 1; 30 | end 31 | else if (B == 1) 32 | begin 33 | CTRL0 = 0; 34 | CTRL1 = 1; 35 | CTRL2 = 0; 36 | CTRL3 = 1; 37 | CTRL4 = 1; 38 | CTRL5 = 1; 39 | CTRL6 = 0; 40 | CTRL7 = 0; 41 | end 42 | else if (C == 1) 43 | begin 44 | CTRL0 = 1; 45 | CTRL1 = 0; 46 | CTRL2 = 0; 47 | CTRL3 = 1; 48 | CTRL4 = 0; 49 | CTRL5 = 1; 50 | CTRL6 = 1; 51 | CTRL7 = 1; 52 | end 53 | else 54 | if ((D == 1)) 55 | begin 56 | CTRL0 = 0; 57 | CTRL1 = 1; 58 | CTRL2 = 0; 59 | CTRL3 = 1; 60 | CTRL4 = 1; 61 | CTRL5 = 1; 62 | CTRL6 = 0; 63 | CTRL7 = 0; 64 | end 65 | else if ((E == 0)) 66 | begin 67 | CTRL0 = 0; 68 | CTRL1 = 0; 69 | CTRL2 = 0; 70 | CTRL3 = 0; 71 | CTRL4 = 1; 72 | CTRL5 = 0; 73 | CTRL6 = 1; 74 | CTRL7 = 0; 75 | end 76 | end 77 | endmodule 78 | -------------------------------------------------------------------------------- /example_project_directory/control_unit_example/out.svg: -------------------------------------------------------------------------------- 1 | undefined -------------------------------------------------------------------------------- /example_project_directory/control_unit_example/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\control_unit_example" *) 4 | (* top = 1 *) 5 | (* src = "control_unit_example.v:3.1-77.10" *) 6 | module control_unit_example(A, B, C, D, E, CTRL0, CTRL1, CTRL2, CTRL3, CTRL4, CTRL5, CTRL6, CTRL7); 7 | (* src = "control_unit_example.v:18.5-76.6" *) 8 | wire _00_; 9 | (* src = "control_unit_example.v:18.5-76.6" *) 10 | wire _01_; 11 | (* src = "control_unit_example.v:18.5-76.6" *) 12 | wire _02_; 13 | (* src = "control_unit_example.v:18.5-76.6" *) 14 | wire _03_; 15 | (* src = "control_unit_example.v:18.5-76.6" *) 16 | wire _04_; 17 | wire _05_; 18 | wire _06_; 19 | wire _07_; 20 | wire _08_; 21 | wire _09_; 22 | wire _10_; 23 | wire _11_; 24 | wire _12_; 25 | wire _13_; 26 | wire _14_; 27 | wire _15_; 28 | wire _16_; 29 | wire _17_; 30 | wire _18_; 31 | wire _19_; 32 | wire _20_; 33 | wire _21_; 34 | wire _22_; 35 | wire _23_; 36 | (* src = "control_unit_example.v:18.5-76.6" *) 37 | wire _24_; 38 | (* src = "control_unit_example.v:18.5-76.6" *) 39 | wire _25_; 40 | (* src = "control_unit_example.v:18.5-76.6" *) 41 | wire _26_; 42 | (* src = "control_unit_example.v:18.5-76.6" *) 43 | wire _27_; 44 | (* src = "control_unit_example.v:18.5-76.6" *) 45 | wire _28_; 46 | (* src = "control_unit_example.v:4.11-4.12" *) 47 | wire _29_; 48 | (* src = "control_unit_example.v:5.11-5.12" *) 49 | wire _30_; 50 | (* src = "control_unit_example.v:6.11-6.12" *) 51 | wire _31_; 52 | (* src = "control_unit_example.v:7.11-7.12" *) 53 | wire _32_; 54 | (* src = "control_unit_example.v:8.11-8.12" *) 55 | wire _33_; 56 | wire _34_; 57 | wire _35_; 58 | wire _36_; 59 | wire _37_; 60 | wire _38_; 61 | wire _39_; 62 | wire _40_; 63 | wire _41_; 64 | wire _42_; 65 | wire _43_; 66 | wire _44_; 67 | wire _45_; 68 | (* src = "control_unit_example.v:4.11-4.12" *) 69 | input A; 70 | wire A; 71 | (* src = "control_unit_example.v:5.11-5.12" *) 72 | input B; 73 | wire B; 74 | (* src = "control_unit_example.v:6.11-6.12" *) 75 | input C; 76 | wire C; 77 | (* src = "control_unit_example.v:9.16-9.21" *) 78 | output CTRL0; 79 | reg CTRL0; 80 | (* src = "control_unit_example.v:10.16-10.21" *) 81 | output CTRL1; 82 | reg CTRL1; 83 | (* src = "control_unit_example.v:11.16-11.21" *) 84 | output CTRL2; 85 | reg CTRL2; 86 | (* src = "control_unit_example.v:12.16-12.21" *) 87 | output CTRL3; 88 | reg CTRL3; 89 | (* src = "control_unit_example.v:13.16-13.21" *) 90 | output CTRL4; 91 | reg CTRL4; 92 | (* src = "control_unit_example.v:14.16-14.21" *) 93 | output CTRL5; 94 | wire CTRL5; 95 | (* src = "control_unit_example.v:15.16-15.21" *) 96 | output CTRL6; 97 | reg CTRL6; 98 | (* src = "control_unit_example.v:16.16-16.21" *) 99 | output CTRL7; 100 | wire CTRL7; 101 | (* src = "control_unit_example.v:7.11-7.12" *) 102 | input D; 103 | wire D; 104 | (* src = "control_unit_example.v:8.11-8.12" *) 105 | input E; 106 | wire E; 107 | assign _35_ = ~_29_; 108 | assign _36_ = ~_31_; 109 | assign _37_ = ~_30_; 110 | assign _38_ = ~_32_; 111 | assign _39_ = ~(_35_ & _36_); 112 | assign _40_ = ~_39_; 113 | assign _41_ = ~(_35_ & _30_); 114 | assign _27_ = ~(_39_ & _41_); 115 | assign _24_ = ~_27_; 116 | assign _42_ = ~(_37_ & _38_); 117 | assign _43_ = ~_42_; 118 | assign _28_ = ~(_27_ & _42_); 119 | assign _25_ = ~_28_; 120 | assign _26_ = ~(_40_ & _43_); 121 | assign _44_ = ~_26_; 122 | assign _45_ = ~(_33_ & _44_); 123 | assign _34_ = ~_45_; 124 | (* src = "control_unit_example.v:18.5-76.6" *) 125 | always @* 126 | if (!_05_) CTRL0 = _00_; 127 | (* src = "control_unit_example.v:18.5-76.6" *) 128 | always @* 129 | if (!_05_) CTRL1 = _01_; 130 | (* src = "control_unit_example.v:18.5-76.6" *) 131 | always @* 132 | if (!_05_) CTRL2 = A; 133 | (* src = "control_unit_example.v:18.5-76.6" *) 134 | always @* 135 | if (!_05_) CTRL3 = _02_; 136 | (* src = "control_unit_example.v:18.5-76.6" *) 137 | always @* 138 | if (!_05_) CTRL4 = _03_; 139 | (* src = "control_unit_example.v:18.5-76.6" *) 140 | always @* 141 | if (!_05_) CTRL6 = _04_; 142 | assign CTRL5 = CTRL3; 143 | assign CTRL7 = CTRL0; 144 | assign _29_ = A; 145 | assign _31_ = C; 146 | assign _30_ = B; 147 | assign _03_ = _27_; 148 | assign _32_ = D; 149 | assign _01_ = _25_; 150 | assign _00_ = _24_; 151 | assign _04_ = _28_; 152 | assign _02_ = _26_; 153 | assign _33_ = E; 154 | assign _05_ = _34_; 155 | endmodule 156 | -------------------------------------------------------------------------------- /example_project_directory/default.svg: -------------------------------------------------------------------------------- 1 | 5 | 6 | 11 | 12 | 13 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | input 79 | 80 | 81 | 82 | 83 | 84 | 85 | constant 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | output 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | hi:lo 252 | 253 | 254 | hi:lo 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | hi:lo 264 | 265 | 266 | hi:lo 267 | 268 | 269 | 270 | 271 | 272 | 273 | generic 274 | 275 | 276 | 277 | out0 278 | 279 | 280 | out1 281 | 282 | 283 | in0 284 | 285 | 286 | in1 287 | 288 | 289 | 290 | 291 | 292 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_one_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module equal_to_one_8bit( 4 | 5 | input [7:0] A, 6 | output reg Y); 7 | 8 | always @(*) 9 | if(A == 1) 10 | begin 11 | Y = 1; 12 | end 13 | else 14 | begin 15 | Y = 0; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_one_8bit/answer.json: -------------------------------------------------------------------------------- 1 | { 2 | "creator": "Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os)", 3 | "modules": { 4 | "equal_to_one_8bit": { 5 | "attributes": { 6 | "hdlname": "\\equal_to_one_8bit", 7 | "top": "00000000000000000000000000000001", 8 | "src": "equal_to_one_8bit.v:3.1-17.10" 9 | }, 10 | "ports": { 11 | "A": { 12 | "direction": "input", 13 | "bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ] 14 | }, 15 | "Y": { 16 | "direction": "output", 17 | "bits": [ 10 ] 18 | } 19 | }, 20 | "cells": { 21 | "$abc$117$auto$blifparse.cc:386:parse_blif$118": { 22 | "hide_name": 1, 23 | "type": "$_NOT_", 24 | "parameters": { 25 | }, 26 | "attributes": { 27 | }, 28 | "port_directions": { 29 | "A": "input", 30 | "Y": "output" 31 | }, 32 | "connections": { 33 | "A": [ 3 ], 34 | "Y": [ 11 ] 35 | } 36 | }, 37 | "$abc$117$auto$blifparse.cc:386:parse_blif$119": { 38 | "hide_name": 1, 39 | "type": "$_NOT_", 40 | "parameters": { 41 | }, 42 | "attributes": { 43 | }, 44 | "port_directions": { 45 | "A": "input", 46 | "Y": "output" 47 | }, 48 | "connections": { 49 | "A": [ 5 ], 50 | "Y": [ 12 ] 51 | } 52 | }, 53 | "$abc$117$auto$blifparse.cc:386:parse_blif$120": { 54 | "hide_name": 1, 55 | "type": "$_NOT_", 56 | "parameters": { 57 | }, 58 | "attributes": { 59 | }, 60 | "port_directions": { 61 | "A": "input", 62 | "Y": "output" 63 | }, 64 | "connections": { 65 | "A": [ 4 ], 66 | "Y": [ 13 ] 67 | } 68 | }, 69 | "$abc$117$auto$blifparse.cc:386:parse_blif$121": { 70 | "hide_name": 1, 71 | "type": "$_NOT_", 72 | "parameters": { 73 | }, 74 | "attributes": { 75 | }, 76 | "port_directions": { 77 | "A": "input", 78 | "Y": "output" 79 | }, 80 | "connections": { 81 | "A": [ 7 ], 82 | "Y": [ 14 ] 83 | } 84 | }, 85 | "$abc$117$auto$blifparse.cc:386:parse_blif$122": { 86 | "hide_name": 1, 87 | "type": "$_NOT_", 88 | "parameters": { 89 | }, 90 | "attributes": { 91 | }, 92 | "port_directions": { 93 | "A": "input", 94 | "Y": "output" 95 | }, 96 | "connections": { 97 | "A": [ 6 ], 98 | "Y": [ 15 ] 99 | } 100 | }, 101 | "$abc$117$auto$blifparse.cc:386:parse_blif$123": { 102 | "hide_name": 1, 103 | "type": "$_NOT_", 104 | "parameters": { 105 | }, 106 | "attributes": { 107 | }, 108 | "port_directions": { 109 | "A": "input", 110 | "Y": "output" 111 | }, 112 | "connections": { 113 | "A": [ 9 ], 114 | "Y": [ 16 ] 115 | } 116 | }, 117 | "$abc$117$auto$blifparse.cc:386:parse_blif$124": { 118 | "hide_name": 1, 119 | "type": "$_NOT_", 120 | "parameters": { 121 | }, 122 | "attributes": { 123 | }, 124 | "port_directions": { 125 | "A": "input", 126 | "Y": "output" 127 | }, 128 | "connections": { 129 | "A": [ 8 ], 130 | "Y": [ 17 ] 131 | } 132 | }, 133 | "$abc$117$auto$blifparse.cc:386:parse_blif$125": { 134 | "hide_name": 1, 135 | "type": "$_NAND_", 136 | "parameters": { 137 | }, 138 | "attributes": { 139 | }, 140 | "port_directions": { 141 | "A": "input", 142 | "B": "input", 143 | "Y": "output" 144 | }, 145 | "connections": { 146 | "A": [ 14 ], 147 | "B": [ 15 ], 148 | "Y": [ 18 ] 149 | } 150 | }, 151 | "$abc$117$auto$blifparse.cc:386:parse_blif$126": { 152 | "hide_name": 1, 153 | "type": "$_NOT_", 154 | "parameters": { 155 | }, 156 | "attributes": { 157 | }, 158 | "port_directions": { 159 | "A": "input", 160 | "Y": "output" 161 | }, 162 | "connections": { 163 | "A": [ 18 ], 164 | "Y": [ 19 ] 165 | } 166 | }, 167 | "$abc$117$auto$blifparse.cc:386:parse_blif$127": { 168 | "hide_name": 1, 169 | "type": "$_NAND_", 170 | "parameters": { 171 | }, 172 | "attributes": { 173 | }, 174 | "port_directions": { 175 | "A": "input", 176 | "B": "input", 177 | "Y": "output" 178 | }, 179 | "connections": { 180 | "A": [ 16 ], 181 | "B": [ 17 ], 182 | "Y": [ 20 ] 183 | } 184 | }, 185 | "$abc$117$auto$blifparse.cc:386:parse_blif$128": { 186 | "hide_name": 1, 187 | "type": "$_NOT_", 188 | "parameters": { 189 | }, 190 | "attributes": { 191 | }, 192 | "port_directions": { 193 | "A": "input", 194 | "Y": "output" 195 | }, 196 | "connections": { 197 | "A": [ 20 ], 198 | "Y": [ 21 ] 199 | } 200 | }, 201 | "$abc$117$auto$blifparse.cc:386:parse_blif$129": { 202 | "hide_name": 1, 203 | "type": "$_NAND_", 204 | "parameters": { 205 | }, 206 | "attributes": { 207 | }, 208 | "port_directions": { 209 | "A": "input", 210 | "B": "input", 211 | "Y": "output" 212 | }, 213 | "connections": { 214 | "A": [ 19 ], 215 | "B": [ 21 ], 216 | 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"src": "equal_to_one_8bit.v:5.17-5.18" 421 | } 422 | }, 423 | "$abc$117$A[2]": { 424 | "hide_name": 1, 425 | "bits": [ 4 ], 426 | "attributes": { 427 | "src": "equal_to_one_8bit.v:5.17-5.18" 428 | } 429 | }, 430 | "$abc$117$A[3]": { 431 | "hide_name": 1, 432 | "bits": [ 5 ], 433 | "attributes": { 434 | "src": "equal_to_one_8bit.v:5.17-5.18" 435 | } 436 | }, 437 | "$abc$117$A[4]": { 438 | "hide_name": 1, 439 | "bits": [ 6 ], 440 | "attributes": { 441 | "src": "equal_to_one_8bit.v:5.17-5.18" 442 | } 443 | }, 444 | "$abc$117$A[5]": { 445 | "hide_name": 1, 446 | "bits": [ 7 ], 447 | "attributes": { 448 | "src": "equal_to_one_8bit.v:5.17-5.18" 449 | } 450 | }, 451 | "$abc$117$A[6]": { 452 | "hide_name": 1, 453 | "bits": [ 8 ], 454 | "attributes": { 455 | "src": "equal_to_one_8bit.v:5.17-5.18" 456 | } 457 | }, 458 | "$abc$117$A[7]": { 459 | "hide_name": 1, 460 | "bits": [ 9 ], 461 | "attributes": { 462 | "src": "equal_to_one_8bit.v:5.17-5.18" 463 | } 464 | }, 465 | "$abc$117$Y": { 466 | "hide_name": 1, 467 | "bits": [ 10 ], 468 | "attributes": { 469 | "src": "equal_to_one_8bit.v:6.16-6.17" 470 | } 471 | }, 472 | "$abc$117$new_n10_": { 473 | "hide_name": 1, 474 | "bits": [ 11 ], 475 | "attributes": { 476 | } 477 | }, 478 | "$abc$117$new_n11_": { 479 | "hide_name": 1, 480 | "bits": [ 12 ], 481 | "attributes": { 482 | } 483 | }, 484 | "$abc$117$new_n12_": { 485 | "hide_name": 1, 486 | "bits": [ 13 ], 487 | "attributes": { 488 | } 489 | }, 490 | "$abc$117$new_n13_": { 491 | "hide_name": 1, 492 | "bits": [ 14 ], 493 | "attributes": { 494 | } 495 | }, 496 | "$abc$117$new_n14_": { 497 | "hide_name": 1, 498 | "bits": [ 15 ], 499 | "attributes": { 500 | } 501 | }, 502 | "$abc$117$new_n15_": { 503 | "hide_name": 1, 504 | "bits": [ 16 ], 505 | "attributes": { 506 | } 507 | }, 508 | "$abc$117$new_n16_": { 509 | "hide_name": 1, 510 | "bits": [ 17 ], 511 | "attributes": { 512 | } 513 | }, 514 | "$abc$117$new_n17_": { 515 | "hide_name": 1, 516 | "bits": [ 18 ], 517 | "attributes": { 518 | } 519 | }, 520 | "$abc$117$new_n18_": { 521 | "hide_name": 1, 522 | "bits": [ 19 ], 523 | "attributes": { 524 | } 525 | }, 526 | "$abc$117$new_n19_": { 527 | "hide_name": 1, 528 | "bits": [ 20 ], 529 | "attributes": { 530 | } 531 | }, 532 | "$abc$117$new_n20_": { 533 | "hide_name": 1, 534 | "bits": [ 21 ], 535 | "attributes": { 536 | } 537 | }, 538 | "$abc$117$new_n21_": { 539 | "hide_name": 1, 540 | "bits": [ 22 ], 541 | "attributes": { 542 | } 543 | }, 544 | "$abc$117$new_n22_": { 545 | "hide_name": 1, 546 | "bits": [ 23 ], 547 | "attributes": { 548 | } 549 | }, 550 | "$abc$117$new_n23_": { 551 | "hide_name": 1, 552 | "bits": [ 24 ], 553 | "attributes": { 554 | } 555 | }, 556 | "$abc$117$new_n24_": { 557 | "hide_name": 1, 558 | "bits": [ 25 ], 559 | "attributes": { 560 | } 561 | }, 562 | "$abc$117$new_n25_": { 563 | "hide_name": 1, 564 | "bits": [ 26 ], 565 | "attributes": { 566 | } 567 | }, 568 | "$abc$117$new_n26_": { 569 | "hide_name": 1, 570 | "bits": [ 27 ], 571 | "attributes": { 572 | } 573 | }, 574 | "$abc$117$new_n27_": { 575 | "hide_name": 1, 576 | "bits": [ 28 ], 577 | "attributes": { 578 | } 579 | }, 580 | "$abc$117$new_n28_": { 581 | "hide_name": 1, 582 | "bits": [ 29 ], 583 | "attributes": { 584 | } 585 | }, 586 | "$abc$117$new_n29_": { 587 | "hide_name": 1, 588 | "bits": [ 30 ], 589 | "attributes": { 590 | } 591 | }, 592 | "A": { 593 | "hide_name": 0, 594 | "bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ], 595 | "attributes": { 596 | "src": "equal_to_one_8bit.v:5.17-5.18" 597 | } 598 | }, 599 | "Y": { 600 | "hide_name": 0, 601 | "bits": [ 10 ], 602 | "attributes": { 603 | "src": "equal_to_one_8bit.v:6.16-6.17" 604 | } 605 | } 606 | } 607 | } 608 | } 609 | } 610 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_one_8bit/equal_to_one_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module equal_to_one_8bit( 4 | 5 | input [7:0] A, 6 | output reg Y); 7 | 8 | always @(*) 9 | if(A == 1) 10 | begin 11 | Y = 1; 12 | end 13 | else 14 | begin 15 | Y = 0; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_one_8bit/out.svg: -------------------------------------------------------------------------------- 1 | AY13254760/8/ -------------------------------------------------------------------------------- /example_project_directory/equal_to_one_8bit/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\equal_to_one_8bit" *) 4 | (* top = 1 *) 5 | (* src = "equal_to_one_8bit.v:3.1-17.10" *) 6 | module equal_to_one_8bit(A, Y); 7 | wire _00_; 8 | wire _01_; 9 | wire _02_; 10 | wire _03_; 11 | wire _04_; 12 | wire _05_; 13 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 14 | wire _06_; 15 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 16 | wire _07_; 17 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 18 | wire _08_; 19 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 20 | wire _09_; 21 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 22 | wire _10_; 23 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 24 | wire _11_; 25 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 26 | wire _12_; 27 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 28 | wire _13_; 29 | (* src = "equal_to_one_8bit.v:6.16-6.17" *) 30 | wire _14_; 31 | wire _15_; 32 | wire _16_; 33 | wire _17_; 34 | wire _18_; 35 | wire _19_; 36 | wire _20_; 37 | wire _21_; 38 | wire _22_; 39 | wire _23_; 40 | wire _24_; 41 | wire _25_; 42 | wire _26_; 43 | wire _27_; 44 | wire _28_; 45 | wire _29_; 46 | wire _30_; 47 | wire _31_; 48 | wire _32_; 49 | wire _33_; 50 | wire _34_; 51 | (* src = "equal_to_one_8bit.v:5.17-5.18" *) 52 | input [7:0] A; 53 | wire [7:0] A; 54 | (* src = "equal_to_one_8bit.v:6.16-6.17" *) 55 | output Y; 56 | wire Y; 57 | assign _15_ = ~_07_; 58 | assign _16_ = ~_09_; 59 | assign _17_ = ~_08_; 60 | assign _18_ = ~_11_; 61 | assign _19_ = ~_10_; 62 | assign _20_ = ~_13_; 63 | assign _21_ = ~_12_; 64 | assign _22_ = ~(_18_ & _19_); 65 | assign _23_ = ~_22_; 66 | assign _24_ = ~(_20_ & _21_); 67 | assign _25_ = ~_24_; 68 | assign _26_ = ~(_23_ & _25_); 69 | assign _27_ = ~_26_; 70 | assign _28_ = ~(_06_ & _15_); 71 | assign _29_ = ~_28_; 72 | assign _30_ = ~(_16_ & _17_); 73 | assign _31_ = ~_30_; 74 | assign _32_ = ~(_29_ & _31_); 75 | assign _33_ = ~_32_; 76 | assign _34_ = ~(_27_ & _33_); 77 | assign _14_ = ~_34_; 78 | assign _06_ = A[0]; 79 | assign _07_ = A[1]; 80 | assign _09_ = A[3]; 81 | assign _08_ = A[2]; 82 | assign _11_ = A[5]; 83 | assign _10_ = A[4]; 84 | assign _13_ = A[7]; 85 | assign _12_ = A[6]; 86 | assign Y = _14_; 87 | endmodule 88 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_zero_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module equal_to_zero_8bit( 4 | 5 | input [7:0] A, 6 | output reg Y); 7 | 8 | always @(*) 9 | if(A == 0) 10 | begin 11 | Y = 1; 12 | end 13 | else 14 | begin 15 | Y = 0; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_zero_8bit/answer.json: -------------------------------------------------------------------------------- 1 | { 2 | "creator": "Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os)", 3 | "modules": { 4 | "equal_to_zero_8bit": { 5 | "attributes": { 6 | "hdlname": "\\equal_to_zero_8bit", 7 | "top": "00000000000000000000000000000001", 8 | "src": "equal_to_zero_8bit.v:3.1-17.10" 9 | }, 10 | "ports": { 11 | "A": { 12 | "direction": "input", 13 | "bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ] 14 | }, 15 | "Y": { 16 | "direction": "output", 17 | "bits": [ 10 ] 18 | } 19 | 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579 | "hide_name": 1, 580 | "bits": [ 32 ], 581 | "attributes": { 582 | } 583 | }, 584 | "$abc$94$new_n11_": { 585 | "hide_name": 1, 586 | "bits": [ 33 ], 587 | "attributes": { 588 | } 589 | }, 590 | "$abc$94$new_n12_": { 591 | "hide_name": 1, 592 | "bits": [ 34 ], 593 | "attributes": { 594 | } 595 | }, 596 | "$abc$94$new_n13_": { 597 | "hide_name": 1, 598 | "bits": [ 35 ], 599 | "attributes": { 600 | } 601 | }, 602 | "$abc$94$new_n14_": { 603 | "hide_name": 1, 604 | "bits": [ 36 ], 605 | "attributes": { 606 | } 607 | }, 608 | "$abc$94$new_n15_": { 609 | "hide_name": 1, 610 | "bits": [ 37 ], 611 | "attributes": { 612 | } 613 | }, 614 | "A": { 615 | "hide_name": 0, 616 | "bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ], 617 | "attributes": { 618 | "src": "equal_to_zero_8bit.v:5.17-5.18" 619 | } 620 | }, 621 | "Y": { 622 | "hide_name": 0, 623 | "bits": [ 10 ], 624 | "attributes": { 625 | "src": "equal_to_zero_8bit.v:6.16-6.17" 626 | } 627 | } 628 | } 629 | } 630 | } 631 | } 632 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_zero_8bit/equal_to_zero_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module equal_to_zero_8bit( 4 | 5 | input [7:0] A, 6 | output reg Y); 7 | 8 | always @(*) 9 | if(A == 0) 10 | begin 11 | Y = 1; 12 | end 13 | else 14 | begin 15 | Y = 0; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /example_project_directory/equal_to_zero_8bit/out.svg: -------------------------------------------------------------------------------- 1 | AY10325476/8/ -------------------------------------------------------------------------------- /example_project_directory/equal_to_zero_8bit/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\equal_to_zero_8bit" *) 4 | (* top = 1 *) 5 | (* src = "equal_to_zero_8bit.v:3.1-17.10" *) 6 | module equal_to_zero_8bit(A, Y); 7 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 8 | wire _00_; 9 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 10 | wire _01_; 11 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 12 | wire _02_; 13 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 14 | wire _03_; 15 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 16 | wire _04_; 17 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 18 | wire _05_; 19 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 20 | wire _06_; 21 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 22 | wire _07_; 23 | (* src = "equal_to_zero_8bit.v:6.16-6.17" *) 24 | wire _08_; 25 | wire _09_; 26 | wire _10_; 27 | wire _11_; 28 | wire _12_; 29 | wire _13_; 30 | wire _14_; 31 | wire _15_; 32 | wire _16_; 33 | wire _17_; 34 | wire _18_; 35 | wire _19_; 36 | wire _20_; 37 | wire _21_; 38 | wire _22_; 39 | wire _23_; 40 | wire _24_; 41 | wire _25_; 42 | wire _26_; 43 | wire _27_; 44 | wire _28_; 45 | wire _29_; 46 | wire _30_; 47 | wire _31_; 48 | wire _32_; 49 | wire _33_; 50 | wire _34_; 51 | wire _35_; 52 | (* src = "equal_to_zero_8bit.v:5.17-5.18" *) 53 | input [7:0] A; 54 | wire [7:0] A; 55 | (* src = "equal_to_zero_8bit.v:6.16-6.17" *) 56 | output Y; 57 | wire Y; 58 | assign _09_ = ~_01_; 59 | assign _10_ = ~_00_; 60 | assign _11_ = ~_03_; 61 | assign _12_ = ~_02_; 62 | assign _13_ = ~_05_; 63 | assign _14_ = ~_04_; 64 | assign _15_ = ~_07_; 65 | assign _16_ = ~_06_; 66 | assign _17_ = ~(_13_ & _14_); 67 | assign _18_ = ~_17_; 68 | assign _19_ = ~(_15_ & _16_); 69 | assign _20_ = ~_19_; 70 | assign _21_ = ~(_18_ & _20_); 71 | assign _22_ = ~_21_; 72 | assign _23_ = ~(_09_ & _10_); 73 | assign _24_ = ~_23_; 74 | assign _25_ = ~(_11_ & _12_); 75 | assign _26_ = ~_25_; 76 | assign _27_ = ~(_24_ & _26_); 77 | assign _28_ = ~_27_; 78 | assign _29_ = ~(_22_ & _28_); 79 | assign _08_ = ~_29_; 80 | assign Y = _08_; 81 | assign _01_ = A[1]; 82 | assign _00_ = A[0]; 83 | assign _03_ = A[3]; 84 | assign _02_ = A[2]; 85 | assign _05_ = A[5]; 86 | assign _04_ = A[4]; 87 | assign _07_ = A[7]; 88 | assign _06_ = A[6]; 89 | endmodule 90 | -------------------------------------------------------------------------------- /example_project_directory/logical_and_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module logical_and_8bit( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output wire Y); 8 | 9 | begin 10 | assign Y = A && B; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /example_project_directory/logical_and_8bit/logical_and_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module logical_and_8bit( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output wire Y); 8 | 9 | begin 10 | assign Y = A && B; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /example_project_directory/logical_and_8bit/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\logical_and_8bit" *) 4 | (* top = 1 *) 5 | (* src = "logical_and_8bit.v:3.1-13.10" *) 6 | module logical_and_8bit(A, B, Y); 7 | wire _000_; 8 | wire _001_; 9 | wire _002_; 10 | wire _003_; 11 | wire _004_; 12 | wire _005_; 13 | wire _006_; 14 | wire _007_; 15 | wire _008_; 16 | wire _009_; 17 | wire _010_; 18 | wire _011_; 19 | wire _012_; 20 | wire _013_; 21 | (* src = "logical_and_8bit.v:5.17-5.18" *) 22 | wire _014_; 23 | (* src = "logical_and_8bit.v:5.17-5.18" *) 24 | wire _015_; 25 | (* src = "logical_and_8bit.v:5.17-5.18" *) 26 | wire _016_; 27 | (* src = "logical_and_8bit.v:5.17-5.18" *) 28 | wire _017_; 29 | (* src = "logical_and_8bit.v:5.17-5.18" *) 30 | wire _018_; 31 | (* src = "logical_and_8bit.v:5.17-5.18" *) 32 | wire _019_; 33 | (* src = "logical_and_8bit.v:5.17-5.18" *) 34 | wire _020_; 35 | (* src = "logical_and_8bit.v:5.17-5.18" *) 36 | wire _021_; 37 | (* src = "logical_and_8bit.v:6.17-6.18" *) 38 | wire _022_; 39 | (* src = "logical_and_8bit.v:6.17-6.18" *) 40 | wire _023_; 41 | (* src = "logical_and_8bit.v:6.17-6.18" *) 42 | wire _024_; 43 | (* src = "logical_and_8bit.v:6.17-6.18" *) 44 | wire _025_; 45 | (* src = "logical_and_8bit.v:6.17-6.18" *) 46 | wire _026_; 47 | (* src = "logical_and_8bit.v:6.17-6.18" *) 48 | wire _027_; 49 | (* src = "logical_and_8bit.v:6.17-6.18" *) 50 | wire _028_; 51 | (* src = "logical_and_8bit.v:6.17-6.18" *) 52 | wire _029_; 53 | (* src = "logical_and_8bit.v:7.17-7.18" *) 54 | wire _030_; 55 | wire _031_; 56 | wire _032_; 57 | wire _033_; 58 | wire _034_; 59 | wire _035_; 60 | wire _036_; 61 | wire _037_; 62 | wire _038_; 63 | wire _039_; 64 | wire _040_; 65 | wire _041_; 66 | wire _042_; 67 | wire _043_; 68 | wire _044_; 69 | wire _045_; 70 | wire _046_; 71 | wire _047_; 72 | wire _048_; 73 | wire _049_; 74 | wire _050_; 75 | wire _051_; 76 | wire _052_; 77 | wire _053_; 78 | wire _054_; 79 | wire _055_; 80 | wire _056_; 81 | wire _057_; 82 | wire _058_; 83 | wire _059_; 84 | wire _060_; 85 | wire _061_; 86 | wire _062_; 87 | wire _063_; 88 | wire _064_; 89 | wire _065_; 90 | wire _066_; 91 | wire _067_; 92 | wire _068_; 93 | wire _069_; 94 | wire _070_; 95 | wire _071_; 96 | wire _072_; 97 | wire _073_; 98 | (* src = "logical_and_8bit.v:5.17-5.18" *) 99 | input [7:0] A; 100 | wire [7:0] A; 101 | (* src = "logical_and_8bit.v:6.17-6.18" *) 102 | input [7:0] B; 103 | wire [7:0] B; 104 | (* src = "logical_and_8bit.v:7.17-7.18" *) 105 | output Y; 106 | wire Y; 107 | assign _031_ = ~_015_; 108 | assign _032_ = ~_014_; 109 | assign _033_ = ~_017_; 110 | assign _034_ = ~_016_; 111 | assign _035_ = ~_019_; 112 | assign _036_ = ~_018_; 113 | assign _037_ = ~_021_; 114 | assign _038_ = ~_020_; 115 | assign _039_ = ~_023_; 116 | assign _040_ = ~_022_; 117 | assign _041_ = ~_025_; 118 | assign _042_ = ~_024_; 119 | assign _043_ = ~_027_; 120 | assign _044_ = ~_026_; 121 | assign _045_ = ~_029_; 122 | assign _046_ = ~_028_; 123 | assign _047_ = ~(_043_ & _044_); 124 | assign _048_ = ~_047_; 125 | assign _049_ = ~(_045_ & _046_); 126 | assign _050_ = ~_049_; 127 | assign _051_ = ~(_048_ & _050_); 128 | assign _052_ = ~_051_; 129 | assign _053_ = ~(_039_ & _040_); 130 | assign _054_ = ~_053_; 131 | assign _055_ = ~(_041_ & _042_); 132 | assign _056_ = ~_055_; 133 | assign _057_ = ~(_054_ & _056_); 134 | assign _058_ = ~_057_; 135 | assign _059_ = ~(_052_ & _058_); 136 | assign _060_ = ~(_035_ & _036_); 137 | assign _061_ = ~_060_; 138 | assign _062_ = ~(_037_ & _038_); 139 | assign _063_ = ~_062_; 140 | assign _064_ = ~(_061_ & _063_); 141 | assign _065_ = ~_064_; 142 | assign _066_ = ~(_031_ & _032_); 143 | assign _067_ = ~_066_; 144 | assign _068_ = ~(_033_ & _034_); 145 | assign _069_ = ~_068_; 146 | assign _070_ = ~(_067_ & _069_); 147 | assign _071_ = ~_070_; 148 | assign _072_ = ~(_065_ & _071_); 149 | assign _073_ = ~(_059_ & _072_); 150 | assign _030_ = ~_073_; 151 | assign _015_ = A[1]; 152 | assign _014_ = A[0]; 153 | assign _017_ = A[3]; 154 | assign _016_ = A[2]; 155 | assign _019_ = A[5]; 156 | assign _018_ = A[4]; 157 | assign _021_ = A[7]; 158 | assign _020_ = A[6]; 159 | assign _023_ = B[1]; 160 | assign _022_ = B[0]; 161 | assign _025_ = B[3]; 162 | assign _024_ = B[2]; 163 | assign _027_ = B[5]; 164 | assign _026_ = B[4]; 165 | assign _029_ = B[7]; 166 | assign _028_ = B[6]; 167 | assign Y = _030_; 168 | endmodule 169 | -------------------------------------------------------------------------------- /example_project_directory/logical_or_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module logical_or_8bit( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output wire Y); 8 | 9 | begin 10 | assign Y = A || B; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /example_project_directory/logical_or_8bit/logical_or_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module logical_or_8bit( 4 | 5 | input [7:0] A, 6 | input [7:0] B, 7 | output wire Y); 8 | 9 | begin 10 | assign Y = A || B; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /example_project_directory/logical_or_8bit/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\logical_or_8bit" *) 4 | (* top = 1 *) 5 | (* src = "logical_or_8bit.v:3.1-13.10" *) 6 | module logical_or_8bit(A, B, Y); 7 | wire _000_; 8 | wire _001_; 9 | wire _002_; 10 | wire _003_; 11 | wire _004_; 12 | wire _005_; 13 | wire _006_; 14 | wire _007_; 15 | wire _008_; 16 | wire _009_; 17 | wire _010_; 18 | wire _011_; 19 | wire _012_; 20 | wire _013_; 21 | (* src = "logical_or_8bit.v:5.17-5.18" *) 22 | wire _014_; 23 | (* src = "logical_or_8bit.v:5.17-5.18" *) 24 | wire _015_; 25 | (* src = "logical_or_8bit.v:5.17-5.18" *) 26 | wire _016_; 27 | (* src = "logical_or_8bit.v:5.17-5.18" *) 28 | wire _017_; 29 | (* src = "logical_or_8bit.v:5.17-5.18" *) 30 | wire _018_; 31 | (* src = "logical_or_8bit.v:5.17-5.18" *) 32 | wire _019_; 33 | (* src = "logical_or_8bit.v:5.17-5.18" *) 34 | wire _020_; 35 | (* src = "logical_or_8bit.v:5.17-5.18" *) 36 | wire _021_; 37 | (* src = "logical_or_8bit.v:6.17-6.18" *) 38 | wire _022_; 39 | (* src = "logical_or_8bit.v:6.17-6.18" *) 40 | wire _023_; 41 | (* src = "logical_or_8bit.v:6.17-6.18" *) 42 | wire _024_; 43 | (* src = "logical_or_8bit.v:6.17-6.18" *) 44 | wire _025_; 45 | (* src = "logical_or_8bit.v:6.17-6.18" *) 46 | wire _026_; 47 | (* src = "logical_or_8bit.v:6.17-6.18" *) 48 | wire _027_; 49 | (* src = "logical_or_8bit.v:6.17-6.18" *) 50 | wire _028_; 51 | (* src = "logical_or_8bit.v:6.17-6.18" *) 52 | wire _029_; 53 | (* src = "logical_or_8bit.v:7.17-7.18" *) 54 | wire _030_; 55 | wire _031_; 56 | wire _032_; 57 | wire _033_; 58 | wire _034_; 59 | wire _035_; 60 | wire _036_; 61 | wire _037_; 62 | wire _038_; 63 | wire _039_; 64 | wire _040_; 65 | wire _041_; 66 | wire _042_; 67 | wire _043_; 68 | wire _044_; 69 | wire _045_; 70 | wire _046_; 71 | wire _047_; 72 | wire _048_; 73 | wire _049_; 74 | wire _050_; 75 | wire _051_; 76 | wire _052_; 77 | wire _053_; 78 | wire _054_; 79 | wire _055_; 80 | wire _056_; 81 | wire _057_; 82 | wire _058_; 83 | wire _059_; 84 | wire _060_; 85 | wire _061_; 86 | wire _062_; 87 | wire _063_; 88 | wire _064_; 89 | wire _065_; 90 | wire _066_; 91 | wire _067_; 92 | wire _068_; 93 | wire _069_; 94 | wire _070_; 95 | wire _071_; 96 | wire _072_; 97 | wire _073_; 98 | wire _074_; 99 | (* src = "logical_or_8bit.v:5.17-5.18" *) 100 | input [7:0] A; 101 | wire [7:0] A; 102 | (* src = "logical_or_8bit.v:6.17-6.18" *) 103 | input [7:0] B; 104 | wire [7:0] B; 105 | (* src = "logical_or_8bit.v:7.17-7.18" *) 106 | output Y; 107 | wire Y; 108 | assign _031_ = ~_015_; 109 | assign _032_ = ~_014_; 110 | assign _033_ = ~_017_; 111 | assign _034_ = ~_016_; 112 | assign _035_ = ~_019_; 113 | assign _036_ = ~_018_; 114 | assign _037_ = ~_021_; 115 | assign _038_ = ~_020_; 116 | assign _039_ = ~_023_; 117 | assign _040_ = ~_022_; 118 | assign _041_ = ~_025_; 119 | assign _042_ = ~_024_; 120 | assign _043_ = ~_027_; 121 | assign _044_ = ~_026_; 122 | assign _045_ = ~_029_; 123 | assign _046_ = ~_028_; 124 | assign _047_ = ~(_036_ & _037_); 125 | assign _048_ = ~_047_; 126 | assign _049_ = ~(_031_ & _034_); 127 | assign _050_ = ~_049_; 128 | assign _051_ = ~(_048_ & _050_); 129 | assign _052_ = ~_051_; 130 | assign _053_ = ~(_043_ & _046_); 131 | assign _054_ = ~_053_; 132 | assign _055_ = ~(_040_ & _041_); 133 | assign _056_ = ~_055_; 134 | assign _057_ = ~(_054_ & _056_); 135 | assign _058_ = ~_057_; 136 | assign _059_ = ~(_052_ & _058_); 137 | assign _060_ = ~_059_; 138 | assign _061_ = ~(_035_ & _038_); 139 | assign _062_ = ~_061_; 140 | assign _063_ = ~(_032_ & _033_); 141 | assign _064_ = ~_063_; 142 | assign _065_ = ~(_062_ & _064_); 143 | assign _066_ = ~_065_; 144 | assign _067_ = ~(_044_ & _045_); 145 | assign _068_ = ~_067_; 146 | assign _069_ = ~(_039_ & _042_); 147 | assign _070_ = ~_069_; 148 | assign _071_ = ~(_068_ & _070_); 149 | assign _072_ = ~_071_; 150 | assign _073_ = ~(_066_ & _072_); 151 | assign _074_ = ~_073_; 152 | assign _030_ = ~(_060_ & _074_); 153 | assign _015_ = A[1]; 154 | assign _014_ = A[0]; 155 | assign _017_ = A[3]; 156 | assign _016_ = A[2]; 157 | assign _019_ = A[5]; 158 | assign _018_ = A[4]; 159 | assign _021_ = A[7]; 160 | assign _020_ = A[6]; 161 | assign _023_ = B[1]; 162 | assign _022_ = B[0]; 163 | assign _025_ = B[3]; 164 | assign _024_ = B[2]; 165 | assign _027_ = B[5]; 166 | assign _026_ = B[4]; 167 | assign _029_ = B[7]; 168 | assign _028_ = B[6]; 169 | assign Y = _030_; 170 | endmodule 171 | -------------------------------------------------------------------------------- /example_project_directory/meme.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module meme( 4 | 5 | input [8:0] A, 6 | output reg [6:0] Y); 7 | 8 | always @(*) 9 | if(A == 420) 10 | Y = 69; 11 | else 12 | Y = 0; 13 | endmodule 14 | -------------------------------------------------------------------------------- /example_project_directory/meme/answer.json: -------------------------------------------------------------------------------- 1 | { 2 | "creator": "Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os)", 3 | "modules": { 4 | "meme": { 5 | "attributes": { 6 | "hdlname": "\\meme", 7 | "top": "00000000000000000000000000000001", 8 | "src": "meme.v:3.1-13.10" 9 | }, 10 | "ports": { 11 | "A": { 12 | "direction": "input", 13 | "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10 ] 14 | }, 15 | "Y": { 16 | "direction": "output", 17 | "bits": [ 11, "0", 11, "0", "0", "0", 11 ] 18 | } 19 | }, 20 | "cells": { 21 | "$abc$127$auto$blifparse.cc:386:parse_blif$128": { 22 | "hide_name": 1, 23 | "type": "$_NOT_", 24 | "parameters": { 25 | }, 26 | "attributes": { 27 | }, 28 | "port_directions": { 29 | "A": "input", 30 | "Y": "output" 31 | }, 32 | "connections": { 33 | "A": [ 3 ], 34 | "Y": [ 12 ] 35 | } 36 | }, 37 | "$abc$127$auto$blifparse.cc:386:parse_blif$129": { 38 | "hide_name": 1, 39 | "type": "$_NOT_", 40 | "parameters": { 41 | }, 42 | "attributes": { 43 | }, 44 | "port_directions": { 45 | "A": "input", 46 | "Y": "output" 47 | }, 48 | "connections": { 49 | "A": [ 2 ], 50 | "Y": [ 13 ] 51 | } 52 | }, 53 | "$abc$127$auto$blifparse.cc:386:parse_blif$130": { 54 | "hide_name": 1, 55 | "type": "$_NOT_", 56 | "parameters": { 57 | }, 58 | "attributes": { 59 | }, 60 | "port_directions": { 61 | "A": "input", 62 | "Y": "output" 63 | }, 64 | "connections": { 65 | "A": [ 5 ], 66 | "Y": [ 14 ] 67 | } 68 | }, 69 | "$abc$127$auto$blifparse.cc:386:parse_blif$131": { 70 | "hide_name": 1, 71 | "type": "$_NOT_", 72 | "parameters": { 73 | }, 74 | "attributes": { 75 | }, 76 | "port_directions": { 77 | "A": "input", 78 | "Y": "output" 79 | }, 80 | "connections": { 81 | "A": [ 6 ], 82 | "Y": [ 15 ] 83 | } 84 | }, 85 | "$abc$127$auto$blifparse.cc:386:parse_blif$132": { 86 | "hide_name": 1, 87 | "type": "$_NOT_", 88 | "parameters": { 89 | }, 90 | "attributes": { 91 | }, 92 | "port_directions": { 93 | "A": "input", 94 | "Y": "output" 95 | }, 96 | "connections": { 97 | "A": [ 8 ], 98 | "Y": [ 16 ] 99 | } 100 | }, 101 | "$abc$127$auto$blifparse.cc:386:parse_blif$133": { 102 | "hide_name": 1, 103 | "type": "$_NAND_", 104 | "parameters": { 105 | }, 106 | "attributes": { 107 | }, 108 | "port_directions": { 109 | "A": "input", 110 | "B": "input", 111 | "Y": "output" 112 | }, 113 | "connections": { 114 | "A": [ 9 ], 115 | "B": [ 10 ], 116 | "Y": [ 17 ] 117 | } 118 | }, 119 | "$abc$127$auto$blifparse.cc:386:parse_blif$134": { 120 | "hide_name": 1, 121 | "type": "$_NOT_", 122 | "parameters": { 123 | }, 124 | "attributes": { 125 | }, 126 | "port_directions": { 127 | "A": "input", 128 | "Y": "output" 129 | }, 130 | "connections": { 131 | "A": [ 17 ], 132 | "Y": [ 18 ] 133 | } 134 | }, 135 | "$abc$127$auto$blifparse.cc:386:parse_blif$135": { 136 | "hide_name": 1, 137 | "type": "$_NAND_", 138 | "parameters": { 139 | }, 140 | "attributes": { 141 | }, 142 | "port_directions": { 143 | "A": "input", 144 | "B": "input", 145 | "Y": "output" 146 | }, 147 | "connections": { 148 | "A": [ 16 ], 149 | "B": [ 18 ], 150 | "Y": [ 19 ] 151 | } 152 | }, 153 | "$abc$127$auto$blifparse.cc:386:parse_blif$136": { 154 | "hide_name": 1, 155 | "type": "$_NOT_", 156 | "parameters": { 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}, 208 | "attributes": { 209 | }, 210 | "port_directions": { 211 | "A": "input", 212 | "B": "input", 213 | "Y": "output" 214 | }, 215 | "connections": { 216 | "A": [ 14 ], 217 | "B": [ 4 ], 218 | "Y": [ 23 ] 219 | } 220 | }, 221 | "$abc$127$auto$blifparse.cc:386:parse_blif$140": { 222 | "hide_name": 1, 223 | "type": "$_NOT_", 224 | "parameters": { 225 | }, 226 | "attributes": { 227 | }, 228 | "port_directions": { 229 | "A": "input", 230 | "Y": "output" 231 | }, 232 | "connections": { 233 | "A": [ 23 ], 234 | "Y": [ 24 ] 235 | } 236 | }, 237 | "$abc$127$auto$blifparse.cc:386:parse_blif$141": { 238 | "hide_name": 1, 239 | "type": "$_NAND_", 240 | "parameters": { 241 | }, 242 | "attributes": { 243 | }, 244 | "port_directions": { 245 | "A": "input", 246 | "B": "input", 247 | "Y": "output" 248 | }, 249 | "connections": { 250 | "A": [ 15 ], 251 | "B": [ 7 ], 252 | "Y": [ 25 ] 253 | } 254 | }, 255 | "$abc$127$auto$blifparse.cc:386:parse_blif$142": { 256 | "hide_name": 1, 257 | "type": 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"meme.v:6.22-6.23" 619 | } 620 | } 621 | } 622 | } 623 | } 624 | } 625 | -------------------------------------------------------------------------------- /example_project_directory/meme/meme.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module meme( 4 | 5 | input [8:0] A, 6 | output reg [6:0] Y); 7 | 8 | always @(*) 9 | if(A == 420) 10 | Y = 69; 11 | else 12 | Y = 0; 13 | endmodule 14 | -------------------------------------------------------------------------------- /example_project_directory/meme/out.svg: -------------------------------------------------------------------------------- 1 | AY00000123:56103467825/7//3//9/ -------------------------------------------------------------------------------- /example_project_directory/meme/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\meme" *) 4 | (* top = 1 *) 5 | (* src = "meme.v:3.1-13.10" *) 6 | module meme(A, Y); 7 | wire _00_; 8 | wire _01_; 9 | wire _02_; 10 | wire _03_; 11 | wire _04_; 12 | wire _05_; 13 | wire _06_; 14 | (* src = "meme.v:5.17-5.18" *) 15 | wire _07_; 16 | (* src = "meme.v:5.17-5.18" *) 17 | wire _08_; 18 | (* src = "meme.v:5.17-5.18" *) 19 | wire _09_; 20 | (* src = "meme.v:5.17-5.18" *) 21 | wire _10_; 22 | (* src = "meme.v:5.17-5.18" *) 23 | wire _11_; 24 | (* src = "meme.v:5.17-5.18" *) 25 | wire _12_; 26 | (* src = "meme.v:5.17-5.18" *) 27 | wire _13_; 28 | (* src = "meme.v:5.17-5.18" *) 29 | wire _14_; 30 | (* src = "meme.v:5.17-5.18" *) 31 | wire _15_; 32 | (* src = "meme.v:6.22-6.23" *) 33 | wire _16_; 34 | wire _17_; 35 | wire _18_; 36 | wire _19_; 37 | wire _20_; 38 | wire _21_; 39 | wire _22_; 40 | wire _23_; 41 | wire _24_; 42 | wire _25_; 43 | wire _26_; 44 | wire _27_; 45 | wire _28_; 46 | wire _29_; 47 | wire _30_; 48 | wire _31_; 49 | wire _32_; 50 | wire _33_; 51 | wire _34_; 52 | wire _35_; 53 | wire _36_; 54 | (* src = "meme.v:5.17-5.18" *) 55 | input [8:0] A; 56 | wire [8:0] A; 57 | (* src = "meme.v:6.22-6.23" *) 58 | output [6:0] Y; 59 | wire [6:0] Y; 60 | assign _17_ = ~_08_; 61 | assign _18_ = ~_07_; 62 | assign _19_ = ~_10_; 63 | assign _20_ = ~_11_; 64 | assign _21_ = ~_13_; 65 | assign _22_ = ~(_14_ & _15_); 66 | assign _23_ = ~_22_; 67 | assign _24_ = ~(_21_ & _23_); 68 | assign _25_ = ~_24_; 69 | assign _26_ = ~(_17_ & _18_); 70 | assign _27_ = ~_26_; 71 | assign _28_ = ~(_19_ & _09_); 72 | assign _29_ = ~_28_; 73 | assign _30_ = ~(_20_ & _12_); 74 | assign _31_ = ~_30_; 75 | assign _32_ = ~(_29_ & _31_); 76 | assign _33_ = ~_32_; 77 | assign _34_ = ~(_27_ & _33_); 78 | assign _35_ = ~_34_; 79 | assign _36_ = ~(_25_ & _35_); 80 | assign _16_ = ~_36_; 81 | assign Y[5:0] = { 3'h0, Y[6], 1'h0, Y[6] }; 82 | assign _08_ = A[1]; 83 | assign _07_ = A[0]; 84 | assign _10_ = A[3]; 85 | assign _09_ = A[2]; 86 | assign _11_ = A[4]; 87 | assign _12_ = A[5]; 88 | assign _13_ = A[6]; 89 | assign _14_ = A[7]; 90 | assign _15_ = A[8]; 91 | assign Y[6] = _16_; 92 | endmodule 93 | -------------------------------------------------------------------------------- /example_project_directory/multiply.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module multiply( 4 | 5 | input [3:0] A, 6 | input [3:0] B, 7 | output reg [7:0] Y); 8 | 9 | always @(*) 10 | Y = A * B; 11 | endmodule 12 | -------------------------------------------------------------------------------- /example_project_directory/multiply/multiply.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module multiply( 4 | 5 | input [3:0] A, 6 | input [3:0] B, 7 | output reg [7:0] Y); 8 | 9 | always @(*) 10 | Y = A * B; 11 | endmodule 12 | -------------------------------------------------------------------------------- /example_project_directory/multiply/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\multiply" *) 4 | (* top = 1 *) 5 | (* src = "multiply.v:3.1-11.10" *) 6 | module multiply(A, B, Y); 7 | wire _000_; 8 | wire _001_; 9 | wire _002_; 10 | wire _003_; 11 | wire _004_; 12 | wire _005_; 13 | wire _006_; 14 | wire _007_; 15 | wire _008_; 16 | wire _009_; 17 | wire _010_; 18 | wire _011_; 19 | wire _012_; 20 | wire _013_; 21 | wire _014_; 22 | wire _015_; 23 | wire _016_; 24 | wire _017_; 25 | wire _018_; 26 | wire _019_; 27 | wire _020_; 28 | wire _021_; 29 | wire _022_; 30 | wire _023_; 31 | wire _024_; 32 | wire _025_; 33 | wire _026_; 34 | wire _027_; 35 | wire _028_; 36 | wire _029_; 37 | wire _030_; 38 | wire _031_; 39 | wire _032_; 40 | wire _033_; 41 | wire _034_; 42 | wire _035_; 43 | wire _036_; 44 | wire _037_; 45 | wire _038_; 46 | wire _039_; 47 | wire _040_; 48 | wire _041_; 49 | wire _042_; 50 | wire _043_; 51 | wire _044_; 52 | wire _045_; 53 | wire _046_; 54 | wire _047_; 55 | wire _048_; 56 | wire _049_; 57 | wire _050_; 58 | wire _051_; 59 | wire _052_; 60 | wire _053_; 61 | wire _054_; 62 | wire _055_; 63 | wire _056_; 64 | wire _057_; 65 | wire _058_; 66 | wire _059_; 67 | wire _060_; 68 | (* src = "multiply.v:5.17-5.18" *) 69 | wire _061_; 70 | (* src = "multiply.v:5.17-5.18" *) 71 | wire _062_; 72 | (* src = "multiply.v:5.17-5.18" *) 73 | wire _063_; 74 | (* src = "multiply.v:5.17-5.18" *) 75 | wire _064_; 76 | (* src = "multiply.v:6.17-6.18" *) 77 | wire _065_; 78 | (* src = "multiply.v:6.17-6.18" *) 79 | wire _066_; 80 | (* src = "multiply.v:6.17-6.18" *) 81 | wire _067_; 82 | (* src = "multiply.v:6.17-6.18" *) 83 | wire _068_; 84 | (* src = "multiply.v:7.22-7.23" *) 85 | wire _069_; 86 | (* src = "multiply.v:7.22-7.23" *) 87 | wire _070_; 88 | (* src = "multiply.v:7.22-7.23" *) 89 | wire _071_; 90 | (* src = "multiply.v:7.22-7.23" *) 91 | wire _072_; 92 | (* src = "multiply.v:7.22-7.23" *) 93 | wire _073_; 94 | (* src = "multiply.v:7.22-7.23" *) 95 | wire _074_; 96 | (* src = "multiply.v:7.22-7.23" *) 97 | wire _075_; 98 | (* src = "multiply.v:7.22-7.23" *) 99 | wire _076_; 100 | wire _077_; 101 | wire _078_; 102 | wire _079_; 103 | wire _080_; 104 | wire _081_; 105 | wire _082_; 106 | wire _083_; 107 | wire _084_; 108 | wire _085_; 109 | wire _086_; 110 | wire _087_; 111 | wire _088_; 112 | wire _089_; 113 | wire _090_; 114 | wire _091_; 115 | wire _092_; 116 | wire _093_; 117 | wire _094_; 118 | wire _095_; 119 | wire _096_; 120 | wire _097_; 121 | wire _098_; 122 | wire _099_; 123 | wire _100_; 124 | wire _101_; 125 | wire _102_; 126 | wire _103_; 127 | wire _104_; 128 | wire _105_; 129 | wire _106_; 130 | wire _107_; 131 | wire _108_; 132 | wire _109_; 133 | wire _110_; 134 | wire _111_; 135 | wire _112_; 136 | wire _113_; 137 | wire _114_; 138 | wire _115_; 139 | wire _116_; 140 | wire _117_; 141 | wire _118_; 142 | wire _119_; 143 | wire _120_; 144 | wire _121_; 145 | wire _122_; 146 | wire _123_; 147 | wire _124_; 148 | wire _125_; 149 | wire _126_; 150 | wire _127_; 151 | wire _128_; 152 | wire _129_; 153 | wire _130_; 154 | wire _131_; 155 | wire _132_; 156 | wire _133_; 157 | wire _134_; 158 | wire _135_; 159 | wire _136_; 160 | wire _137_; 161 | wire _138_; 162 | wire _139_; 163 | wire _140_; 164 | wire _141_; 165 | wire _142_; 166 | wire _143_; 167 | wire _144_; 168 | wire _145_; 169 | wire _146_; 170 | wire _147_; 171 | wire _148_; 172 | wire _149_; 173 | wire _150_; 174 | wire _151_; 175 | wire _152_; 176 | wire _153_; 177 | wire _154_; 178 | wire _155_; 179 | wire _156_; 180 | wire _157_; 181 | wire _158_; 182 | wire _159_; 183 | wire _160_; 184 | wire _161_; 185 | wire _162_; 186 | wire _163_; 187 | wire _164_; 188 | wire _165_; 189 | wire _166_; 190 | wire _167_; 191 | wire _168_; 192 | wire _169_; 193 | wire _170_; 194 | wire _171_; 195 | wire _172_; 196 | wire _173_; 197 | wire _174_; 198 | wire _175_; 199 | wire _176_; 200 | wire _177_; 201 | wire _178_; 202 | wire _179_; 203 | wire _180_; 204 | wire _181_; 205 | wire _182_; 206 | wire _183_; 207 | wire _184_; 208 | wire _185_; 209 | wire _186_; 210 | wire _187_; 211 | wire _188_; 212 | wire _189_; 213 | wire _190_; 214 | wire _191_; 215 | wire _192_; 216 | wire _193_; 217 | wire _194_; 218 | (* src = "multiply.v:5.17-5.18" *) 219 | input [3:0] A; 220 | wire [3:0] A; 221 | (* src = "multiply.v:6.17-6.18" *) 222 | input [3:0] B; 223 | wire [3:0] B; 224 | (* src = "multiply.v:7.22-7.23" *) 225 | output [7:0] Y; 226 | wire [7:0] Y; 227 | assign _115_ = ~(_066_ & _061_); 228 | assign _116_ = ~(_065_ & _062_); 229 | assign _117_ = ~_116_; 230 | assign _118_ = ~(_062_ & _066_); 231 | assign _119_ = ~_118_; 232 | assign _120_ = ~(_065_ & _061_); 233 | assign _069_ = ~_120_; 234 | assign _121_ = ~(_119_ & _069_); 235 | assign _122_ = ~_121_; 236 | assign _123_ = ~(_115_ & _116_); 237 | assign _124_ = ~(_121_ & _123_); 238 | assign _070_ = ~_124_; 239 | assign _125_ = ~(_061_ & _067_); 240 | assign _126_ = ~_125_; 241 | assign _127_ = ~(_065_ & _063_); 242 | assign _128_ = ~(_066_ & _063_); 243 | assign _129_ = ~_128_; 244 | assign _130_ = ~(_117_ & _129_); 245 | assign _131_ = ~(_118_ & _127_); 246 | assign _132_ = ~(_130_ & _131_); 247 | assign _133_ = ~_132_; 248 | assign _134_ = ~(_126_ & _133_); 249 | assign _135_ = ~(_125_ & _132_); 250 | assign _136_ = ~(_134_ & _135_); 251 | assign _137_ = ~_136_; 252 | assign _138_ = ~(_122_ & _137_); 253 | assign _139_ = ~_138_; 254 | assign _140_ = ~(_121_ & _136_); 255 | assign _141_ = ~(_138_ & _140_); 256 | assign _071_ = ~_141_; 257 | assign _142_ = ~(_130_ & _134_); 258 | assign _143_ = ~_142_; 259 | assign _144_ = ~(_065_ & _064_); 260 | assign _145_ = ~_144_; 261 | assign _146_ = ~(_128_ & _144_); 262 | assign _147_ = ~(_066_ & _064_); 263 | assign _148_ = ~(_129_ & _145_); 264 | assign _149_ = ~(_146_ & _148_); 265 | assign _150_ = ~_149_; 266 | assign _151_ = ~(_062_ & _067_); 267 | assign _152_ = ~_151_; 268 | assign _153_ = ~(_150_ & _152_); 269 | assign _154_ = ~(_149_ & _151_); 270 | assign _155_ = ~(_153_ & _154_); 271 | assign _156_ = ~_155_; 272 | assign _157_ = ~(_142_ & _156_); 273 | assign _158_ = ~(_143_ & _155_); 274 | assign _159_ = ~(_157_ & _158_); 275 | assign _160_ = ~_159_; 276 | assign _161_ = ~(_061_ & _068_); 277 | assign _162_ = ~_161_; 278 | assign _163_ = ~(_160_ & _162_); 279 | assign _164_ = ~(_159_ & _161_); 280 | assign _165_ = ~(_163_ & _164_); 281 | assign _166_ = ~_165_; 282 | assign _167_ = ~(_139_ & _166_); 283 | assign _168_ = ~_167_; 284 | assign _169_ = ~(_157_ & _163_); 285 | assign _170_ = ~_169_; 286 | assign _171_ = ~(_062_ & _068_); 287 | assign _172_ = ~_171_; 288 | assign _173_ = ~(_148_ & _153_); 289 | assign _174_ = ~_173_; 290 | assign _175_ = ~(_063_ & _067_); 291 | assign _176_ = ~(_147_ & _175_); 292 | assign _177_ = ~(_067_ & _064_); 293 | assign _178_ = ~_177_; 294 | assign _179_ = ~(_129_ & _178_); 295 | assign _180_ = ~(_176_ & _179_); 296 | assign _181_ = ~_180_; 297 | assign _182_ = ~(_173_ & _181_); 298 | assign _183_ = ~(_174_ & _180_); 299 | assign _184_ = ~(_182_ & _183_); 300 | assign _185_ = ~_184_; 301 | assign _186_ = ~(_172_ & _185_); 302 | assign _187_ = ~(_171_ & _184_); 303 | assign _188_ = ~(_186_ & _187_); 304 | assign _189_ = ~_188_; 305 | assign _190_ = ~(_170_ & _188_); 306 | assign _191_ = ~(_169_ & _189_); 307 | assign _192_ = ~_191_; 308 | assign _193_ = ~(_190_ & _191_); 309 | assign _194_ = ~_193_; 310 | assign _077_ = ~(_168_ & _194_); 311 | assign _078_ = ~(_167_ & _193_); 312 | assign _079_ = ~(_077_ & _078_); 313 | assign _073_ = ~_079_; 314 | assign _080_ = ~(_191_ & _077_); 315 | assign _081_ = ~_080_; 316 | assign _082_ = ~(_182_ & _186_); 317 | assign _083_ = ~_082_; 318 | assign _084_ = ~(_063_ & _068_); 319 | assign _085_ = ~_084_; 320 | assign _086_ = ~(_128_ & _178_); 321 | assign _087_ = ~_086_; 322 | assign _088_ = ~(_085_ & _087_); 323 | assign _089_ = ~(_084_ & _086_); 324 | assign _090_ = ~(_088_ & _089_); 325 | assign _091_ = ~_090_; 326 | assign _092_ = ~(_083_ & _090_); 327 | assign _093_ = ~(_082_ & _091_); 328 | assign _094_ = ~(_092_ & _093_); 329 | assign _095_ = ~_094_; 330 | assign _096_ = ~(_081_ & _095_); 331 | assign _097_ = ~(_080_ & _094_); 332 | assign _074_ = ~(_096_ & _097_); 333 | assign _098_ = ~(_179_ & _088_); 334 | assign _099_ = ~_098_; 335 | assign _100_ = ~(_064_ & _068_); 336 | assign _101_ = ~_100_; 337 | assign _102_ = ~(_098_ & _101_); 338 | assign _103_ = ~(_099_ & _100_); 339 | assign _104_ = ~(_102_ & _103_); 340 | assign _105_ = ~_104_; 341 | assign _106_ = ~(_192_ & _092_); 342 | assign _107_ = ~(_191_ & _093_); 343 | assign _108_ = ~(_092_ & _107_); 344 | assign _109_ = ~(_093_ & _106_); 345 | assign _110_ = ~(_105_ & _109_); 346 | assign _111_ = ~(_104_ & _108_); 347 | assign _112_ = ~(_110_ & _111_); 348 | assign _075_ = ~_112_; 349 | assign _113_ = ~(_138_ & _165_); 350 | assign _114_ = ~(_167_ & _113_); 351 | assign _072_ = ~_114_; 352 | assign _076_ = ~(_102_ & _110_); 353 | assign _065_ = B[0]; 354 | assign _062_ = A[1]; 355 | assign _066_ = B[1]; 356 | assign _061_ = A[0]; 357 | assign Y[1] = _070_; 358 | assign _063_ = A[2]; 359 | assign _067_ = B[2]; 360 | assign Y[2] = _071_; 361 | assign _064_ = A[3]; 362 | assign _068_ = B[3]; 363 | assign Y[4] = _073_; 364 | assign Y[5] = _074_; 365 | assign Y[6] = _075_; 366 | assign Y[3] = _072_; 367 | assign Y[7] = _076_; 368 | assign Y[0] = _069_; 369 | endmodule 370 | -------------------------------------------------------------------------------- /example_project_directory/mux2_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mux2_8bit( 4 | input [7:0] A, 5 | input [7:0] B, 6 | input S, 7 | output reg [7:0] Y); 8 | 9 | always @ (A or B or S) 10 | begin 11 | case(S) 12 | 0: 13 | begin 14 | Y = A; 15 | end 16 | 1: 17 | begin 18 | Y = B; 19 | end 20 | endcase 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /example_project_directory/mux2_8bit/answer.json: -------------------------------------------------------------------------------- 1 | { 2 | "creator": "Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os)", 3 | "modules": { 4 | "mux2_8bit": { 5 | "attributes": { 6 | "hdlname": "\\mux2_8bit", 7 | "top": "00000000000000000000000000000001", 8 | "src": "mux2_8bit.v:3.1-22.10" 9 | }, 10 | "ports": { 11 | "A": { 12 | "direction": "input", 13 | "bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ] 14 | }, 15 | "B": { 16 | "direction": "input", 17 | "bits": [ 10, 11, 12, 13, 14, 15, 16, 17 ] 18 | }, 19 | "S": { 20 | "direction": "input", 21 | "bits": [ 18 ] 22 | }, 23 | "Y": { 24 | "direction": "output", 25 | "bits": [ 19, 20, 21, 22, 23, 24, 25, 26 ] 26 | } 27 | }, 28 | "cells": { 29 | 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786 | } 787 | } 788 | -------------------------------------------------------------------------------- /example_project_directory/mux2_8bit/mux2_8bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mux2_8bit( 4 | input [7:0] A, 5 | input [7:0] B, 6 | input S, 7 | output reg [7:0] Y); 8 | 9 | always @ (A or B or S) 10 | begin 11 | case(S) 12 | 0: 13 | begin 14 | Y = A; 15 | end 16 | 1: 17 | begin 18 | Y = B; 19 | end 20 | endcase 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /example_project_directory/mux2_8bit/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\mux2_8bit" *) 4 | (* top = 1 *) 5 | (* src = "mux2_8bit.v:3.1-22.10" *) 6 | module mux2_8bit(A, B, S, Y); 7 | (* src = "mux2_8bit.v:4.15-4.16" *) 8 | wire _00_; 9 | (* src = "mux2_8bit.v:4.15-4.16" *) 10 | wire _01_; 11 | (* src = "mux2_8bit.v:4.15-4.16" *) 12 | wire _02_; 13 | (* src = "mux2_8bit.v:4.15-4.16" *) 14 | wire _03_; 15 | (* src = "mux2_8bit.v:4.15-4.16" *) 16 | wire _04_; 17 | (* src = "mux2_8bit.v:4.15-4.16" *) 18 | wire _05_; 19 | (* src = "mux2_8bit.v:4.15-4.16" *) 20 | wire _06_; 21 | (* src = "mux2_8bit.v:4.15-4.16" *) 22 | wire _07_; 23 | (* src = "mux2_8bit.v:5.19-5.20" *) 24 | wire _08_; 25 | (* src = "mux2_8bit.v:5.19-5.20" *) 26 | wire _09_; 27 | (* src = "mux2_8bit.v:5.19-5.20" *) 28 | wire _10_; 29 | (* src = "mux2_8bit.v:5.19-5.20" *) 30 | wire _11_; 31 | (* src = "mux2_8bit.v:5.19-5.20" *) 32 | wire _12_; 33 | (* src = "mux2_8bit.v:5.19-5.20" *) 34 | wire _13_; 35 | (* src = "mux2_8bit.v:5.19-5.20" *) 36 | wire _14_; 37 | (* src = "mux2_8bit.v:5.19-5.20" *) 38 | wire _15_; 39 | (* src = "mux2_8bit.v:6.13-6.14" *) 40 | wire _16_; 41 | (* src = "mux2_8bit.v:7.24-7.25" *) 42 | wire _17_; 43 | (* src = "mux2_8bit.v:7.24-7.25" *) 44 | wire _18_; 45 | (* src = "mux2_8bit.v:7.24-7.25" *) 46 | wire _19_; 47 | (* src = "mux2_8bit.v:7.24-7.25" *) 48 | wire _20_; 49 | (* src = "mux2_8bit.v:7.24-7.25" *) 50 | wire _21_; 51 | (* src = "mux2_8bit.v:7.24-7.25" *) 52 | wire _22_; 53 | (* src = "mux2_8bit.v:7.24-7.25" *) 54 | wire _23_; 55 | (* src = "mux2_8bit.v:7.24-7.25" *) 56 | wire _24_; 57 | wire _25_; 58 | wire _26_; 59 | wire _27_; 60 | wire _28_; 61 | wire _29_; 62 | wire _30_; 63 | wire _31_; 64 | wire _32_; 65 | wire _33_; 66 | wire _34_; 67 | wire _35_; 68 | wire _36_; 69 | wire _37_; 70 | wire _38_; 71 | wire _39_; 72 | wire _40_; 73 | wire _41_; 74 | (* src = "mux2_8bit.v:4.15-4.16" *) 75 | input [7:0] A; 76 | wire [7:0] A; 77 | (* src = "mux2_8bit.v:5.19-5.20" *) 78 | input [7:0] B; 79 | wire [7:0] B; 80 | (* src = "mux2_8bit.v:6.13-6.14" *) 81 | input S; 82 | wire S; 83 | (* src = "mux2_8bit.v:7.24-7.25" *) 84 | output [7:0] Y; 85 | wire [7:0] Y; 86 | assign _25_ = ~_16_; 87 | assign _26_ = ~(_08_ & _16_); 88 | assign _27_ = ~(_00_ & _25_); 89 | assign _17_ = ~(_26_ & _27_); 90 | assign _28_ = ~(_16_ & _09_); 91 | assign _29_ = ~(_25_ & _01_); 92 | assign _18_ = ~(_28_ & _29_); 93 | assign _30_ = ~(_16_ & _10_); 94 | assign _31_ = ~(_25_ & _02_); 95 | assign _19_ = ~(_30_ & _31_); 96 | assign _32_ = ~(_16_ & _11_); 97 | assign _33_ = ~(_25_ & _03_); 98 | assign _20_ = ~(_32_ & _33_); 99 | assign _34_ = ~(_16_ & _12_); 100 | assign _35_ = ~(_25_ & _04_); 101 | assign _21_ = ~(_34_ & _35_); 102 | assign _36_ = ~(_16_ & _13_); 103 | assign _37_ = ~(_25_ & _05_); 104 | assign _22_ = ~(_36_ & _37_); 105 | assign _38_ = ~(_16_ & _14_); 106 | assign _39_ = ~(_25_ & _06_); 107 | assign _23_ = ~(_38_ & _39_); 108 | assign _40_ = ~(_16_ & _15_); 109 | assign _41_ = ~(_25_ & _07_); 110 | assign _24_ = ~(_40_ & _41_); 111 | assign _00_ = A[0]; 112 | assign _08_ = B[0]; 113 | assign _16_ = S; 114 | assign Y[0] = _17_; 115 | assign _01_ = A[1]; 116 | assign _09_ = B[1]; 117 | assign Y[1] = _18_; 118 | assign _02_ = A[2]; 119 | assign _10_ = B[2]; 120 | assign Y[2] = _19_; 121 | assign _03_ = A[3]; 122 | assign _11_ = B[3]; 123 | assign Y[3] = _20_; 124 | assign _04_ = A[4]; 125 | assign _12_ = B[4]; 126 | assign Y[4] = _21_; 127 | assign _05_ = A[5]; 128 | assign _13_ = B[5]; 129 | assign Y[5] = _22_; 130 | assign _06_ = A[6]; 131 | assign _14_ = B[6]; 132 | assign Y[6] = _23_; 133 | assign _07_ = A[7]; 134 | assign _15_ = B[7]; 135 | assign Y[7] = _24_; 136 | endmodule 137 | -------------------------------------------------------------------------------- /example_project_directory/truth_table.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module truth_table( 4 | input CLK, 5 | input RST, 6 | output reg[7:0] out); 7 | 8 | always @ (posedge CLK or negedge RST) 9 | begin 10 | if (!RST) 11 | begin 12 | out <= 0; 13 | end 14 | else if (out == 255) 15 | begin 16 | out <= 0; 17 | end 18 | else 19 | begin 20 | out <= out + 1; 21 | end 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /example_project_directory/truth_table/output.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.28+1 (git sha1 a9c792dce, clang 10.0.0-4ubuntu1 -fPIC -Os) */ 2 | 3 | (* hdlname = "\\truth_table" *) 4 | (* top = 1 *) 5 | (* src = "truth_table.v:3.1-23.10" *) 6 | module truth_table(CLK, RST, out); 7 | (* src = "truth_table.v:8.1-22.4" *) 8 | wire [7:0] _000_; 9 | wire _001_; 10 | wire _002_; 11 | wire _003_; 12 | wire _004_; 13 | wire _005_; 14 | wire _006_; 15 | wire _007_; 16 | wire _008_; 17 | wire _009_; 18 | wire _010_; 19 | wire _011_; 20 | wire _012_; 21 | wire _013_; 22 | wire _014_; 23 | wire _015_; 24 | wire _016_; 25 | wire _017_; 26 | wire _018_; 27 | wire _019_; 28 | (* src = "truth_table.v:8.1-22.4" *) 29 | wire _020_; 30 | (* src = "truth_table.v:8.1-22.4" *) 31 | wire _021_; 32 | (* src = "truth_table.v:8.1-22.4" *) 33 | wire _022_; 34 | (* src = "truth_table.v:8.1-22.4" *) 35 | wire _023_; 36 | (* src = "truth_table.v:8.1-22.4" *) 37 | wire _024_; 38 | (* src = "truth_table.v:8.1-22.4" *) 39 | wire _025_; 40 | (* src = "truth_table.v:8.1-22.4" *) 41 | wire _026_; 42 | (* src = "truth_table.v:8.1-22.4" *) 43 | wire _027_; 44 | wire _028_; 45 | wire _029_; 46 | wire _030_; 47 | wire _031_; 48 | wire _032_; 49 | wire _033_; 50 | wire _034_; 51 | wire _035_; 52 | wire _036_; 53 | wire _037_; 54 | wire _038_; 55 | wire _039_; 56 | wire _040_; 57 | wire _041_; 58 | wire _042_; 59 | wire _043_; 60 | wire _044_; 61 | wire _045_; 62 | wire _046_; 63 | wire _047_; 64 | wire _048_; 65 | wire _049_; 66 | wire _050_; 67 | wire _051_; 68 | wire _052_; 69 | wire _053_; 70 | wire _054_; 71 | wire _055_; 72 | wire _056_; 73 | wire _057_; 74 | wire _058_; 75 | wire _059_; 76 | wire _060_; 77 | (* src = "truth_table.v:6.21-6.24" *) 78 | wire _061_; 79 | (* src = "truth_table.v:6.21-6.24" *) 80 | wire _062_; 81 | (* src = "truth_table.v:6.21-6.24" *) 82 | wire _063_; 83 | (* src = "truth_table.v:6.21-6.24" *) 84 | wire _064_; 85 | (* src = "truth_table.v:6.21-6.24" *) 86 | wire _065_; 87 | (* src = "truth_table.v:6.21-6.24" *) 88 | wire _066_; 89 | (* src = "truth_table.v:6.21-6.24" *) 90 | wire _067_; 91 | (* src = "truth_table.v:6.21-6.24" *) 92 | wire _068_; 93 | (* src = "truth_table.v:4.11-4.14" *) 94 | input CLK; 95 | wire CLK; 96 | (* src = "truth_table.v:5.11-5.14" *) 97 | input RST; 98 | wire RST; 99 | (* src = "truth_table.v:6.21-6.24" *) 100 | output [7:0] out; 101 | reg [7:0] out; 102 | assign _028_ = ~_062_; 103 | assign _020_ = ~_061_; 104 | assign _029_ = ~_064_; 105 | assign _030_ = ~_063_; 106 | assign _031_ = ~_066_; 107 | assign _032_ = ~_065_; 108 | assign _033_ = ~_067_; 109 | assign _034_ = ~_068_; 110 | assign _035_ = ~(_062_ & _061_); 111 | assign _036_ = ~_035_; 112 | assign _037_ = ~(_028_ & _020_); 113 | assign _038_ = ~(_035_ & _037_); 114 | assign _021_ = ~_038_; 115 | assign _039_ = ~(_030_ & _035_); 116 | assign _040_ = ~(_063_ & _036_); 117 | assign _041_ = ~_040_; 118 | assign _042_ = ~(_039_ & _040_); 119 | assign _022_ = ~_042_; 120 | assign _043_ = ~(_064_ & _041_); 121 | assign _044_ = ~_043_; 122 | assign _045_ = ~(_029_ & _040_); 123 | assign _046_ = ~(_043_ & _045_); 124 | assign _023_ = ~_046_; 125 | assign _047_ = ~(_032_ & _043_); 126 | assign _048_ = ~(_065_ & _044_); 127 | assign _049_ = ~_048_; 128 | assign _050_ = ~(_047_ & _048_); 129 | assign _024_ = ~_050_; 130 | assign _051_ = ~(_031_ & _048_); 131 | assign _052_ = ~(_066_ & _049_); 132 | assign _053_ = ~_052_; 133 | assign _054_ = ~(_051_ & _052_); 134 | assign _025_ = ~_054_; 135 | assign _055_ = ~(_033_ & _052_); 136 | assign _056_ = ~(_067_ & _053_); 137 | assign _057_ = ~_056_; 138 | assign _058_ = ~(_055_ & _056_); 139 | assign _026_ = ~_058_; 140 | assign _059_ = ~(_068_ & _056_); 141 | assign _060_ = ~(_034_ & _057_); 142 | assign _027_ = ~(_059_ & _060_); 143 | (* src = "truth_table.v:8.1-22.4" *) 144 | always @(posedge CLK, negedge RST) 145 | if (!RST) out[0] <= 1'h0; 146 | else out[0] <= _000_[0]; 147 | (* src = "truth_table.v:8.1-22.4" *) 148 | always @(posedge CLK, negedge RST) 149 | if (!RST) out[1] <= 1'h0; 150 | else out[1] <= _000_[1]; 151 | (* src = "truth_table.v:8.1-22.4" *) 152 | always @(posedge CLK, negedge RST) 153 | if (!RST) out[2] <= 1'h0; 154 | else out[2] <= _000_[2]; 155 | (* src = "truth_table.v:8.1-22.4" *) 156 | always @(posedge CLK, negedge RST) 157 | if (!RST) out[3] <= 1'h0; 158 | else out[3] <= _000_[3]; 159 | (* src = "truth_table.v:8.1-22.4" *) 160 | always @(posedge CLK, negedge RST) 161 | if (!RST) out[4] <= 1'h0; 162 | else out[4] <= _000_[4]; 163 | (* src = "truth_table.v:8.1-22.4" *) 164 | always @(posedge CLK, negedge RST) 165 | if (!RST) out[5] <= 1'h0; 166 | else out[5] <= _000_[5]; 167 | (* src = "truth_table.v:8.1-22.4" *) 168 | always @(posedge CLK, negedge RST) 169 | if (!RST) out[6] <= 1'h0; 170 | else out[6] <= _000_[6]; 171 | (* src = "truth_table.v:8.1-22.4" *) 172 | always @(posedge CLK, negedge RST) 173 | if (!RST) out[7] <= 1'h0; 174 | else out[7] <= _000_[7]; 175 | assign _062_ = out[1]; 176 | assign _061_ = out[0]; 177 | assign _064_ = out[3]; 178 | assign _063_ = out[2]; 179 | assign _066_ = out[5]; 180 | assign _065_ = out[4]; 181 | assign _067_ = out[6]; 182 | assign _068_ = out[7]; 183 | assign _000_[0] = _020_; 184 | assign _000_[1] = _021_; 185 | assign _000_[2] = _022_; 186 | assign _000_[3] = _023_; 187 | assign _000_[4] = _024_; 188 | assign _000_[5] = _025_; 189 | assign _000_[6] = _026_; 190 | assign _000_[7] = _027_; 191 | endmodule 192 | -------------------------------------------------------------------------------- /example_project_directory/truth_table/truth_table.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module truth_table( 4 | input CLK, 5 | input RST, 6 | output reg[7:0] out); 7 | 8 | always @ (posedge CLK or negedge RST) 9 | begin 10 | if (!RST) 11 | begin 12 | out <= 0; 13 | end 14 | else if (out == 255) 15 | begin 16 | out <= 0; 17 | end 18 | else 19 | begin 20 | out <= out + 1; 21 | end 22 | end 23 | endmodule 24 | --------------------------------------------------------------------------------