├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── examples ├── bsg_concentrate_static │ ├── bsg_concentrate_static.flist │ └── bsg_concentrate_static.v ├── gcd │ ├── gcd.flist │ └── gcd.v └── undefined │ ├── undefined.flist │ └── undefined.v ├── patches ├── pyverilog_add_wirelist_reglist.patch └── pyverilog_sensitivity_comp.patch └── scripts ├── py ├── bsg_ast_add_wrapper_inplace.py ├── bsg_ast_always_at_redux_opt_inplace.py ├── bsg_ast_concat_redux_opt_inplace.py ├── bsg_ast_walk_and_swap_inplace.py ├── bsg_ast_wire_reg_decl_opt_inplace.py ├── bsg_elab_to_rtl.py ├── bsg_generic_modules.py ├── bsg_gtech_modules.py ├── bsg_synthetic_modules.py └── bsg_utility_funcs.py └── tcl ├── filelist_include_to_flist.tcl └── run_dc.tcl /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bespoke-silicon-group/bsg_sv2v/HEAD/.gitignore -------------------------------------------------------------------------------- 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