├── .cargo └── config ├── .gitignore ├── .gitmodules ├── CODE_OF_CONDUCT.md ├── CONTRIBUTING.md ├── Cargo.lock ├── Cargo.toml ├── LICENSE ├── README.md ├── gateware ├── __init__.py ├── aes_opentitan.py ├── aes_reg_litex.sv ├── chacha │ ├── README.md │ ├── chacha.py │ ├── chacha_core.v │ └── chacha_qr.v ├── curve25519 │ ├── README.md │ ├── block_diagram.png │ ├── carry_prop3.png │ ├── engine.py │ ├── mapping.png │ ├── mpy_pipe3.png │ ├── normalize4.png │ ├── psum3.png │ └── reduction_diagram.png ├── i2c │ ├── __init__.py │ ├── core.py │ ├── i2c_controller_bit_ctrl.v │ ├── i2c_controller_byte_ctrl.v │ ├── i2c_controller_defines.v │ └── i2c_controller_top.v ├── ice40_hard_i2c.py ├── info │ ├── __init__.py │ ├── dna.py │ ├── git.py │ └── platform.py ├── jtag_phy.py ├── keyboard.py ├── keyrom.py ├── memlcd.py ├── messible.py ├── perfcounter.py ├── rom_block.py ├── sha2_litex.sv ├── sha2_opentitan.py ├── sha512 │ ├── hmac512_core.sv │ ├── hmac512_pkg.sv │ ├── prim_assert.sv │ ├── prim_packer512.sv │ ├── sha512.sv │ └── sha512_pad.sv ├── sha512_litex.sv ├── sha512_opentitan.py ├── spi_7series.py ├── spi_ice40.py ├── spimemio.v ├── spinor.py ├── sram_32.py ├── sram_32_cached.py ├── ticktimer.py ├── timer_alwayson.py ├── trng │ ├── __init__.py │ ├── ring_osc.py │ ├── ring_osc_v2.py │ ├── test_tests.py │ ├── trng_managed.py │ ├── v_ava_poweron.png │ └── v_noise_stable.png ├── usb │ ├── SpinalUsb │ │ ├── UsbDeviceWithPhyWishbone.v │ │ ├── UsbOhciWishbone.v │ │ ├── build.ps1 │ │ ├── build.sbt │ │ └── project │ │ │ └── build.properties │ ├── src │ │ └── main │ │ │ └── scala │ │ │ └── usbdevice │ │ │ ├── MyTopLevel.scala │ │ │ └── UsbDevice.scala │ └── usb_device.py └── wdt.py ├── sim ├── aes │ ├── aes │ │ ├── aes.sv │ │ ├── aes_cipher_control.sv │ │ ├── aes_cipher_core.sv │ │ ├── aes_control.sv │ │ ├── aes_core.sv │ │ ├── aes_ctr.sv │ │ ├── aes_key_expand.sv │ │ ├── aes_mix_columns.sv │ │ ├── aes_mix_single_column.sv │ │ ├── aes_pkg.sv │ │ ├── aes_prng.sv │ │ ├── aes_reg_pkg.sv │ │ ├── aes_reg_top.sv │ │ ├── aes_sbox.sv │ │ ├── aes_sbox_canright.sv │ │ ├── aes_sbox_lut.sv │ │ ├── aes_shift_rows.sv │ │ ├── aes_sub_bytes.sv │ │ ├── prim_assert.sv │ │ ├── prim_cipher_pkg.sv │ │ └── prim_lfsr.sv │ ├── dut.py │ ├── pac-cargo-template │ ├── testbench │ │ ├── .gitignore │ │ ├── Cargo.toml │ │ ├── Makefile │ │ ├── betrusted-hal │ │ │ ├── Cargo.toml │ │ │ └── src │ │ │ │ ├── hal_aes.rs │ │ │ │ └── lib.rs │ │ └── src │ │ │ ├── aes_test.rs │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── cleanup.sh ├── curve_engine │ ├── DSP48E1_sim.v │ ├── README.md │ ├── dut.py │ ├── minimal-workspace-template │ ├── testbench │ │ ├── .cargo │ │ │ └── config │ │ ├── .vscode │ │ │ └── settings.json │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── i2s │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── kbd │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── keyrom │ ├── .gitignore │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── memlcd │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── new_sim.py ├── rom_block │ ├── boot.bin │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── sha2 │ ├── dut.py │ ├── hmac │ │ ├── hmac_core.sv │ │ ├── hmac_pkg.sv │ │ ├── prim_assert.sv │ │ ├── prim_packer.sv │ │ ├── sha2.sv │ │ └── sha2_pad.sv │ ├── pac-cargo-template │ ├── testbench │ │ ├── .gitignore │ │ ├── Cargo.toml │ │ ├── Makefile │ │ ├── sha2-hal │ │ │ ├── Cargo.toml │ │ │ └── src │ │ │ │ ├── hal_sha2.rs │ │ │ │ └── lib.rs │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── sha512 │ ├── dut.py │ ├── pac-cargo-template │ ├── testbench │ │ ├── .gitignore │ │ ├── Cargo.toml │ │ ├── Makefile │ │ ├── sha512-hal │ │ │ ├── Cargo.toml │ │ │ └── src │ │ │ │ ├── hal_sha512.rs │ │ │ │ └── lib.rs │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── spi_basic │ ├── SB_IO.v │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── spi_dopi │ ├── BUFR.v │ ├── IDELAYE2.v │ ├── MX66UM1G45G │ │ ├── MX66UM1G45G.v │ │ └── README.txt │ ├── dut.py │ ├── make_memh.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── spififo │ ├── cells_sim.v │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ ├── top_tb_sim.wcfg │ └── top_tb_sim.wdb ├── sram32 │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── sram32_cached │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── template │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ └── top_tb.v ├── trng_managed │ ├── XADC.v │ ├── dut.py │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ └── top_tb.v └── wdt │ ├── dut.py │ ├── testbench │ ├── Cargo.toml │ ├── Makefile │ └── src │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg ├── sim_noci ├── jtag_phy │ ├── alloc-riscv │ │ ├── CHANGELOG.md │ │ ├── CODE_OF_CONDUCT.md │ │ ├── Cargo.toml │ │ ├── LICENSE-APACHE │ │ ├── LICENSE-MIT │ │ ├── README.md │ │ └── src │ │ │ └── lib.rs │ ├── dut.py │ ├── jtag │ │ ├── Cargo.toml │ │ └── src │ │ │ └── lib.rs │ ├── testbench │ │ ├── Cargo.toml │ │ ├── Makefile │ │ └── src │ │ │ └── main.rs │ ├── top_tb.v │ └── top_tb_sim.wcfg └── perfcounter │ ├── dut.py │ ├── testbench │ ├── Cargo.toml │ ├── Makefile │ ├── build.rs │ └── src │ │ └── main.rs │ └── top_tb.v ├── sim_support ├── __init__.py ├── common.v ├── glbl.v ├── memory_rom.x ├── memory_spi.x ├── placeholder_bios.bin ├── rust │ ├── bios │ │ ├── Cargo.toml │ │ ├── build.rs │ │ └── src │ │ │ └── lib.rs │ ├── pac │ │ ├── Cargo.toml │ │ ├── build.rs │ │ └── src │ │ │ └── lib.rs │ ├── svd2utra │ │ ├── .gitignore │ │ ├── Cargo.toml │ │ ├── README.md │ │ ├── build.rs │ │ ├── examples │ │ │ └── soc.svd │ │ └── src │ │ │ ├── generate.rs │ │ │ ├── lib.rs │ │ │ └── main.rs │ ├── utralib │ │ ├── .gitignore │ │ ├── Cargo.lock │ │ ├── Cargo.toml │ │ ├── README.md │ │ ├── build.rs │ │ └── src │ │ │ └── lib.rs │ └── xous-nommu │ │ ├── Cargo.toml │ │ └── src │ │ ├── definitions.rs │ │ ├── irq.rs │ │ ├── lib.rs │ │ ├── macros.rs │ │ └── syscalls.rs ├── sim_bench.py ├── top_tb_sim.wcfg └── xsim_extract.py └── vcd ├── LICENSE ├── README.md ├── __init__.py ├── parser.py ├── tracker.py ├── utils.py └── watcher.py /.cargo/config: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/.cargo/config -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/.gitignore -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/.gitmodules -------------------------------------------------------------------------------- /CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/CODE_OF_CONDUCT.md -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/CONTRIBUTING.md -------------------------------------------------------------------------------- /Cargo.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/Cargo.lock -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/Cargo.toml -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/README.md -------------------------------------------------------------------------------- /gateware/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /gateware/aes_opentitan.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/aes_opentitan.py -------------------------------------------------------------------------------- /gateware/aes_reg_litex.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/aes_reg_litex.sv -------------------------------------------------------------------------------- /gateware/chacha/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/chacha/README.md -------------------------------------------------------------------------------- /gateware/chacha/chacha.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/chacha/chacha.py -------------------------------------------------------------------------------- /gateware/chacha/chacha_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/chacha/chacha_core.v -------------------------------------------------------------------------------- /gateware/chacha/chacha_qr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/chacha/chacha_qr.v -------------------------------------------------------------------------------- /gateware/curve25519/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/README.md -------------------------------------------------------------------------------- /gateware/curve25519/block_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/block_diagram.png -------------------------------------------------------------------------------- /gateware/curve25519/carry_prop3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/carry_prop3.png -------------------------------------------------------------------------------- /gateware/curve25519/engine.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/engine.py -------------------------------------------------------------------------------- /gateware/curve25519/mapping.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/mapping.png -------------------------------------------------------------------------------- /gateware/curve25519/mpy_pipe3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/mpy_pipe3.png -------------------------------------------------------------------------------- /gateware/curve25519/normalize4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/normalize4.png -------------------------------------------------------------------------------- /gateware/curve25519/psum3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/psum3.png -------------------------------------------------------------------------------- /gateware/curve25519/reduction_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/curve25519/reduction_diagram.png -------------------------------------------------------------------------------- /gateware/i2c/__init__.py: -------------------------------------------------------------------------------- 1 | from gateware.i2c.core import RTLI2C 2 | 3 | -------------------------------------------------------------------------------- /gateware/i2c/core.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/i2c/core.py -------------------------------------------------------------------------------- /gateware/i2c/i2c_controller_bit_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/i2c/i2c_controller_bit_ctrl.v -------------------------------------------------------------------------------- /gateware/i2c/i2c_controller_byte_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/i2c/i2c_controller_byte_ctrl.v -------------------------------------------------------------------------------- /gateware/i2c/i2c_controller_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/i2c/i2c_controller_defines.v -------------------------------------------------------------------------------- /gateware/i2c/i2c_controller_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/i2c/i2c_controller_top.v -------------------------------------------------------------------------------- /gateware/ice40_hard_i2c.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/ice40_hard_i2c.py -------------------------------------------------------------------------------- /gateware/info/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/info/__init__.py -------------------------------------------------------------------------------- /gateware/info/dna.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/info/dna.py -------------------------------------------------------------------------------- /gateware/info/git.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/info/git.py -------------------------------------------------------------------------------- /gateware/info/platform.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/info/platform.py -------------------------------------------------------------------------------- /gateware/jtag_phy.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/jtag_phy.py -------------------------------------------------------------------------------- /gateware/keyboard.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/keyboard.py -------------------------------------------------------------------------------- /gateware/keyrom.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/keyrom.py -------------------------------------------------------------------------------- /gateware/memlcd.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/memlcd.py -------------------------------------------------------------------------------- /gateware/messible.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/messible.py -------------------------------------------------------------------------------- /gateware/perfcounter.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/perfcounter.py -------------------------------------------------------------------------------- /gateware/rom_block.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/rom_block.py -------------------------------------------------------------------------------- /gateware/sha2_litex.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha2_litex.sv -------------------------------------------------------------------------------- /gateware/sha2_opentitan.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha2_opentitan.py -------------------------------------------------------------------------------- /gateware/sha512/hmac512_core.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512/hmac512_core.sv -------------------------------------------------------------------------------- /gateware/sha512/hmac512_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512/hmac512_pkg.sv -------------------------------------------------------------------------------- /gateware/sha512/prim_assert.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512/prim_assert.sv -------------------------------------------------------------------------------- /gateware/sha512/prim_packer512.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512/prim_packer512.sv -------------------------------------------------------------------------------- /gateware/sha512/sha512.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512/sha512.sv -------------------------------------------------------------------------------- /gateware/sha512/sha512_pad.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512/sha512_pad.sv -------------------------------------------------------------------------------- /gateware/sha512_litex.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512_litex.sv -------------------------------------------------------------------------------- /gateware/sha512_opentitan.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sha512_opentitan.py -------------------------------------------------------------------------------- /gateware/spi_7series.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/spi_7series.py -------------------------------------------------------------------------------- /gateware/spi_ice40.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/spi_ice40.py -------------------------------------------------------------------------------- /gateware/spimemio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/spimemio.v -------------------------------------------------------------------------------- /gateware/spinor.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/spinor.py -------------------------------------------------------------------------------- /gateware/sram_32.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sram_32.py -------------------------------------------------------------------------------- /gateware/sram_32_cached.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/sram_32_cached.py -------------------------------------------------------------------------------- /gateware/ticktimer.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/ticktimer.py -------------------------------------------------------------------------------- /gateware/timer_alwayson.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/timer_alwayson.py -------------------------------------------------------------------------------- /gateware/trng/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/trng/__init__.py -------------------------------------------------------------------------------- /gateware/trng/ring_osc.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/trng/ring_osc.py -------------------------------------------------------------------------------- /gateware/trng/ring_osc_v2.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/trng/ring_osc_v2.py -------------------------------------------------------------------------------- /gateware/trng/test_tests.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/trng/test_tests.py -------------------------------------------------------------------------------- /gateware/trng/trng_managed.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/trng/trng_managed.py -------------------------------------------------------------------------------- /gateware/trng/v_ava_poweron.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/trng/v_ava_poweron.png -------------------------------------------------------------------------------- /gateware/trng/v_noise_stable.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/trng/v_noise_stable.png -------------------------------------------------------------------------------- /gateware/usb/SpinalUsb/UsbDeviceWithPhyWishbone.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/usb/SpinalUsb/UsbDeviceWithPhyWishbone.v -------------------------------------------------------------------------------- /gateware/usb/SpinalUsb/UsbOhciWishbone.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/usb/SpinalUsb/UsbOhciWishbone.v -------------------------------------------------------------------------------- /gateware/usb/SpinalUsb/build.ps1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/usb/SpinalUsb/build.ps1 -------------------------------------------------------------------------------- /gateware/usb/SpinalUsb/build.sbt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/usb/SpinalUsb/build.sbt -------------------------------------------------------------------------------- /gateware/usb/SpinalUsb/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.6.2 2 | -------------------------------------------------------------------------------- /gateware/usb/src/main/scala/usbdevice/MyTopLevel.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/usb/src/main/scala/usbdevice/MyTopLevel.scala -------------------------------------------------------------------------------- /gateware/usb/src/main/scala/usbdevice/UsbDevice.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/usb/src/main/scala/usbdevice/UsbDevice.scala -------------------------------------------------------------------------------- /gateware/usb/usb_device.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/usb/usb_device.py -------------------------------------------------------------------------------- /gateware/wdt.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/gateware/wdt.py -------------------------------------------------------------------------------- /sim/aes/aes/aes.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_cipher_control.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_cipher_control.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_cipher_core.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_cipher_core.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_control.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_control.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_core.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_core.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_ctr.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_ctr.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_key_expand.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_key_expand.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_mix_columns.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_mix_columns.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_mix_single_column.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_mix_single_column.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_pkg.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_prng.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_prng.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_reg_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_reg_pkg.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_reg_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_reg_top.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_sbox.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_sbox.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_sbox_canright.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_sbox_canright.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_sbox_lut.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_sbox_lut.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_shift_rows.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_shift_rows.sv -------------------------------------------------------------------------------- /sim/aes/aes/aes_sub_bytes.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/aes_sub_bytes.sv -------------------------------------------------------------------------------- /sim/aes/aes/prim_assert.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/prim_assert.sv -------------------------------------------------------------------------------- /sim/aes/aes/prim_cipher_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/prim_cipher_pkg.sv -------------------------------------------------------------------------------- /sim/aes/aes/prim_lfsr.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/aes/prim_lfsr.sv -------------------------------------------------------------------------------- /sim/aes/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/dut.py -------------------------------------------------------------------------------- /sim/aes/pac-cargo-template: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/pac-cargo-template -------------------------------------------------------------------------------- /sim/aes/testbench/.gitignore: -------------------------------------------------------------------------------- 1 | betrusted-pac/ 2 | -------------------------------------------------------------------------------- /sim/aes/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/aes/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/testbench/Makefile -------------------------------------------------------------------------------- /sim/aes/testbench/betrusted-hal/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/testbench/betrusted-hal/Cargo.toml -------------------------------------------------------------------------------- /sim/aes/testbench/betrusted-hal/src/hal_aes.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/testbench/betrusted-hal/src/hal_aes.rs -------------------------------------------------------------------------------- /sim/aes/testbench/betrusted-hal/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/testbench/betrusted-hal/src/lib.rs -------------------------------------------------------------------------------- /sim/aes/testbench/src/aes_test.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/testbench/src/aes_test.rs -------------------------------------------------------------------------------- /sim/aes/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/aes/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/top_tb.v -------------------------------------------------------------------------------- /sim/aes/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/aes/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/cleanup.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/cleanup.sh -------------------------------------------------------------------------------- /sim/curve_engine/DSP48E1_sim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/DSP48E1_sim.v -------------------------------------------------------------------------------- /sim/curve_engine/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/README.md -------------------------------------------------------------------------------- /sim/curve_engine/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/dut.py -------------------------------------------------------------------------------- /sim/curve_engine/minimal-workspace-template: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/minimal-workspace-template -------------------------------------------------------------------------------- /sim/curve_engine/testbench/.cargo/config: -------------------------------------------------------------------------------- 1 | [build] 2 | target="x86_64-unknown-linux-gnu" 3 | -------------------------------------------------------------------------------- /sim/curve_engine/testbench/.vscode/settings.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/testbench/.vscode/settings.json -------------------------------------------------------------------------------- /sim/curve_engine/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/curve_engine/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/testbench/Makefile -------------------------------------------------------------------------------- /sim/curve_engine/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/curve_engine/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/top_tb.v -------------------------------------------------------------------------------- /sim/curve_engine/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/curve_engine/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/i2s/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/i2s/dut.py -------------------------------------------------------------------------------- /sim/i2s/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/i2s/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/i2s/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/i2s/testbench/Makefile -------------------------------------------------------------------------------- /sim/i2s/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/i2s/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/i2s/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/i2s/top_tb.v -------------------------------------------------------------------------------- /sim/i2s/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/i2s/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/kbd/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/kbd/dut.py -------------------------------------------------------------------------------- /sim/kbd/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/kbd/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/kbd/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/kbd/testbench/Makefile -------------------------------------------------------------------------------- /sim/kbd/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/kbd/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/kbd/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/kbd/top_tb.v -------------------------------------------------------------------------------- /sim/kbd/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/kbd/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/keyrom/.gitignore: -------------------------------------------------------------------------------- 1 | rom.db 2 | -------------------------------------------------------------------------------- /sim/keyrom/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/keyrom/dut.py -------------------------------------------------------------------------------- /sim/keyrom/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/keyrom/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/keyrom/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/keyrom/testbench/Makefile -------------------------------------------------------------------------------- /sim/keyrom/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/keyrom/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/keyrom/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/keyrom/top_tb.v -------------------------------------------------------------------------------- /sim/keyrom/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/keyrom/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/memlcd/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/memlcd/dut.py -------------------------------------------------------------------------------- /sim/memlcd/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/memlcd/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/memlcd/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/memlcd/testbench/Makefile -------------------------------------------------------------------------------- /sim/memlcd/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/memlcd/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/memlcd/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/memlcd/top_tb.v -------------------------------------------------------------------------------- /sim/memlcd/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/memlcd/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/new_sim.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/new_sim.py -------------------------------------------------------------------------------- /sim/rom_block/boot.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/rom_block/boot.bin -------------------------------------------------------------------------------- /sim/rom_block/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/rom_block/dut.py -------------------------------------------------------------------------------- /sim/rom_block/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/rom_block/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/rom_block/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/rom_block/testbench/Makefile -------------------------------------------------------------------------------- /sim/rom_block/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/rom_block/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/rom_block/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/rom_block/top_tb.v -------------------------------------------------------------------------------- /sim/rom_block/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/rom_block/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/sha2/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/dut.py -------------------------------------------------------------------------------- /sim/sha2/hmac/hmac_core.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/hmac/hmac_core.sv -------------------------------------------------------------------------------- /sim/sha2/hmac/hmac_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/hmac/hmac_pkg.sv -------------------------------------------------------------------------------- /sim/sha2/hmac/prim_assert.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/hmac/prim_assert.sv -------------------------------------------------------------------------------- /sim/sha2/hmac/prim_packer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/hmac/prim_packer.sv -------------------------------------------------------------------------------- /sim/sha2/hmac/sha2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/hmac/sha2.sv -------------------------------------------------------------------------------- /sim/sha2/hmac/sha2_pad.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/hmac/sha2_pad.sv -------------------------------------------------------------------------------- /sim/sha2/pac-cargo-template: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/pac-cargo-template -------------------------------------------------------------------------------- /sim/sha2/testbench/.gitignore: -------------------------------------------------------------------------------- 1 | sha2-pac/ 2 | -------------------------------------------------------------------------------- /sim/sha2/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/sha2/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/testbench/Makefile -------------------------------------------------------------------------------- /sim/sha2/testbench/sha2-hal/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/testbench/sha2-hal/Cargo.toml -------------------------------------------------------------------------------- /sim/sha2/testbench/sha2-hal/src/hal_sha2.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/testbench/sha2-hal/src/hal_sha2.rs -------------------------------------------------------------------------------- /sim/sha2/testbench/sha2-hal/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/testbench/sha2-hal/src/lib.rs -------------------------------------------------------------------------------- /sim/sha2/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/sha2/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/top_tb.v -------------------------------------------------------------------------------- /sim/sha2/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha2/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/sha512/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/dut.py -------------------------------------------------------------------------------- /sim/sha512/pac-cargo-template: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/pac-cargo-template -------------------------------------------------------------------------------- /sim/sha512/testbench/.gitignore: -------------------------------------------------------------------------------- 1 | sha512-pac/ 2 | -------------------------------------------------------------------------------- /sim/sha512/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/sha512/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/testbench/Makefile -------------------------------------------------------------------------------- /sim/sha512/testbench/sha512-hal/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/testbench/sha512-hal/Cargo.toml -------------------------------------------------------------------------------- /sim/sha512/testbench/sha512-hal/src/hal_sha512.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/testbench/sha512-hal/src/hal_sha512.rs -------------------------------------------------------------------------------- /sim/sha512/testbench/sha512-hal/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/testbench/sha512-hal/src/lib.rs -------------------------------------------------------------------------------- /sim/sha512/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/sha512/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/top_tb.v -------------------------------------------------------------------------------- /sim/sha512/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sha512/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/spi_basic/SB_IO.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_basic/SB_IO.v -------------------------------------------------------------------------------- /sim/spi_basic/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_basic/dut.py -------------------------------------------------------------------------------- /sim/spi_basic/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_basic/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/spi_basic/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_basic/testbench/Makefile -------------------------------------------------------------------------------- /sim/spi_basic/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_basic/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/spi_basic/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_basic/top_tb.v -------------------------------------------------------------------------------- /sim/spi_basic/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_basic/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/spi_dopi/BUFR.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/BUFR.v -------------------------------------------------------------------------------- /sim/spi_dopi/IDELAYE2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/IDELAYE2.v -------------------------------------------------------------------------------- /sim/spi_dopi/MX66UM1G45G/MX66UM1G45G.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/MX66UM1G45G/MX66UM1G45G.v -------------------------------------------------------------------------------- /sim/spi_dopi/MX66UM1G45G/README.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/MX66UM1G45G/README.txt -------------------------------------------------------------------------------- /sim/spi_dopi/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/dut.py -------------------------------------------------------------------------------- /sim/spi_dopi/make_memh.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/make_memh.py -------------------------------------------------------------------------------- /sim/spi_dopi/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/spi_dopi/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/testbench/Makefile -------------------------------------------------------------------------------- /sim/spi_dopi/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/spi_dopi/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/top_tb.v -------------------------------------------------------------------------------- /sim/spi_dopi/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spi_dopi/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/spififo/cells_sim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/cells_sim.v -------------------------------------------------------------------------------- /sim/spififo/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/dut.py -------------------------------------------------------------------------------- /sim/spififo/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/spififo/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/testbench/Makefile -------------------------------------------------------------------------------- /sim/spififo/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/spififo/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/top_tb.v -------------------------------------------------------------------------------- /sim/spififo/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/spififo/top_tb_sim.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/spififo/top_tb_sim.wdb -------------------------------------------------------------------------------- /sim/sram32/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32/dut.py -------------------------------------------------------------------------------- /sim/sram32/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/sram32/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32/testbench/Makefile -------------------------------------------------------------------------------- /sim/sram32/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/sram32/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32/top_tb.v -------------------------------------------------------------------------------- /sim/sram32/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/sram32_cached/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32_cached/dut.py -------------------------------------------------------------------------------- /sim/sram32_cached/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32_cached/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/sram32_cached/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32_cached/testbench/Makefile -------------------------------------------------------------------------------- /sim/sram32_cached/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32_cached/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/sram32_cached/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32_cached/top_tb.v -------------------------------------------------------------------------------- /sim/sram32_cached/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/sram32_cached/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim/template/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/template/dut.py -------------------------------------------------------------------------------- /sim/template/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/template/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/template/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/template/testbench/Makefile -------------------------------------------------------------------------------- /sim/template/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/template/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/template/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/template/top_tb.v -------------------------------------------------------------------------------- /sim/trng_managed/XADC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/trng_managed/XADC.v -------------------------------------------------------------------------------- /sim/trng_managed/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/trng_managed/dut.py -------------------------------------------------------------------------------- /sim/trng_managed/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/trng_managed/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/trng_managed/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/trng_managed/testbench/Makefile -------------------------------------------------------------------------------- /sim/trng_managed/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/trng_managed/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/trng_managed/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/trng_managed/top_tb.v -------------------------------------------------------------------------------- /sim/wdt/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/wdt/dut.py -------------------------------------------------------------------------------- /sim/wdt/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/wdt/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim/wdt/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/wdt/testbench/Makefile -------------------------------------------------------------------------------- /sim/wdt/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/wdt/testbench/src/main.rs -------------------------------------------------------------------------------- /sim/wdt/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/wdt/top_tb.v -------------------------------------------------------------------------------- /sim/wdt/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim/wdt/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim_noci/jtag_phy/alloc-riscv/CHANGELOG.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/alloc-riscv/CHANGELOG.md -------------------------------------------------------------------------------- /sim_noci/jtag_phy/alloc-riscv/CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/alloc-riscv/CODE_OF_CONDUCT.md -------------------------------------------------------------------------------- /sim_noci/jtag_phy/alloc-riscv/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/alloc-riscv/Cargo.toml -------------------------------------------------------------------------------- /sim_noci/jtag_phy/alloc-riscv/LICENSE-APACHE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/alloc-riscv/LICENSE-APACHE -------------------------------------------------------------------------------- /sim_noci/jtag_phy/alloc-riscv/LICENSE-MIT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/alloc-riscv/LICENSE-MIT -------------------------------------------------------------------------------- /sim_noci/jtag_phy/alloc-riscv/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/alloc-riscv/README.md -------------------------------------------------------------------------------- /sim_noci/jtag_phy/alloc-riscv/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/alloc-riscv/src/lib.rs -------------------------------------------------------------------------------- /sim_noci/jtag_phy/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/dut.py -------------------------------------------------------------------------------- /sim_noci/jtag_phy/jtag/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/jtag/Cargo.toml -------------------------------------------------------------------------------- /sim_noci/jtag_phy/jtag/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/jtag/src/lib.rs -------------------------------------------------------------------------------- /sim_noci/jtag_phy/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim_noci/jtag_phy/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/testbench/Makefile -------------------------------------------------------------------------------- /sim_noci/jtag_phy/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/testbench/src/main.rs -------------------------------------------------------------------------------- /sim_noci/jtag_phy/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/top_tb.v -------------------------------------------------------------------------------- /sim_noci/jtag_phy/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/jtag_phy/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim_noci/perfcounter/dut.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/perfcounter/dut.py -------------------------------------------------------------------------------- /sim_noci/perfcounter/testbench/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/perfcounter/testbench/Cargo.toml -------------------------------------------------------------------------------- /sim_noci/perfcounter/testbench/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/perfcounter/testbench/Makefile -------------------------------------------------------------------------------- /sim_noci/perfcounter/testbench/build.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/perfcounter/testbench/build.rs -------------------------------------------------------------------------------- /sim_noci/perfcounter/testbench/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/perfcounter/testbench/src/main.rs -------------------------------------------------------------------------------- /sim_noci/perfcounter/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_noci/perfcounter/top_tb.v -------------------------------------------------------------------------------- /sim_support/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /sim_support/common.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/common.v -------------------------------------------------------------------------------- /sim_support/glbl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/glbl.v -------------------------------------------------------------------------------- /sim_support/memory_rom.x: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/memory_rom.x -------------------------------------------------------------------------------- /sim_support/memory_spi.x: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/memory_spi.x -------------------------------------------------------------------------------- /sim_support/placeholder_bios.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/placeholder_bios.bin -------------------------------------------------------------------------------- /sim_support/rust/bios/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/bios/Cargo.toml -------------------------------------------------------------------------------- /sim_support/rust/bios/build.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/bios/build.rs -------------------------------------------------------------------------------- /sim_support/rust/bios/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/bios/src/lib.rs -------------------------------------------------------------------------------- /sim_support/rust/pac/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/pac/Cargo.toml -------------------------------------------------------------------------------- /sim_support/rust/pac/build.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/pac/build.rs -------------------------------------------------------------------------------- /sim_support/rust/pac/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/pac/src/lib.rs -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | Cargo.lock 3 | -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/svd2utra/Cargo.toml -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/svd2utra/README.md -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/build.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/svd2utra/build.rs -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/examples/soc.svd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/svd2utra/examples/soc.svd -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/src/generate.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/svd2utra/src/generate.rs -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/svd2utra/src/lib.rs -------------------------------------------------------------------------------- /sim_support/rust/svd2utra/src/main.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/svd2utra/src/main.rs -------------------------------------------------------------------------------- /sim_support/rust/utralib/.gitignore: -------------------------------------------------------------------------------- 1 | target/ 2 | src/generated.rs 3 | -------------------------------------------------------------------------------- /sim_support/rust/utralib/Cargo.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/utralib/Cargo.lock -------------------------------------------------------------------------------- /sim_support/rust/utralib/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/utralib/Cargo.toml -------------------------------------------------------------------------------- /sim_support/rust/utralib/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/utralib/README.md -------------------------------------------------------------------------------- /sim_support/rust/utralib/build.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/utralib/build.rs -------------------------------------------------------------------------------- /sim_support/rust/utralib/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/utralib/src/lib.rs -------------------------------------------------------------------------------- /sim_support/rust/xous-nommu/Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/xous-nommu/Cargo.toml -------------------------------------------------------------------------------- /sim_support/rust/xous-nommu/src/definitions.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/xous-nommu/src/definitions.rs -------------------------------------------------------------------------------- /sim_support/rust/xous-nommu/src/irq.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/xous-nommu/src/irq.rs -------------------------------------------------------------------------------- /sim_support/rust/xous-nommu/src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/xous-nommu/src/lib.rs -------------------------------------------------------------------------------- /sim_support/rust/xous-nommu/src/macros.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/xous-nommu/src/macros.rs -------------------------------------------------------------------------------- /sim_support/rust/xous-nommu/src/syscalls.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/rust/xous-nommu/src/syscalls.rs -------------------------------------------------------------------------------- /sim_support/sim_bench.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/sim_bench.py -------------------------------------------------------------------------------- /sim_support/top_tb_sim.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/top_tb_sim.wcfg -------------------------------------------------------------------------------- /sim_support/xsim_extract.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/sim_support/xsim_extract.py -------------------------------------------------------------------------------- /vcd/LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/vcd/LICENSE -------------------------------------------------------------------------------- /vcd/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/vcd/README.md -------------------------------------------------------------------------------- /vcd/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/vcd/__init__.py -------------------------------------------------------------------------------- /vcd/parser.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/vcd/parser.py -------------------------------------------------------------------------------- /vcd/tracker.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/vcd/tracker.py -------------------------------------------------------------------------------- /vcd/utils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/vcd/utils.py -------------------------------------------------------------------------------- /vcd/watcher.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/betrusted-io/gateware/HEAD/vcd/watcher.py --------------------------------------------------------------------------------