├── .gitignore ├── Assignment 10 ├── problems.pdf ├── Q2-Alternating-Sum │ └── A10Q2.s └── Q1-Binary-Search │ └── A10Q1.s ├── Assignment 11 ├── problems.pdf ├── Q1-Booths-Algorithm │ ├── A11Q1_booth.v │ └── A11Q1_top.v └── Q2-Non-Restoring-Division │ ├── A11Q2_nrd.v │ └── A11Q2_top.v ├── Assignment 5 ├── problems.pdf ├── Q2-Smallest-Value │ ├── A5Q2_one_bit_comparator.v │ ├── A5Q2_three_bit_comparator.v │ ├── A5Q2_smallest_three_bit.v │ └── A5Q2_top.v └── Q1-Fsm │ ├── A5Q1_top.v │ └── A5Q1_fsm.v ├── Assignment 6 ├── problems.pdf └── Q1-Miniature-Processor │ ├── code.c │ ├── A6Q1_top.v │ └── A6Q1_call.v ├── Assignment 7 ├── problems.pdf ├── Q2-Instruction-Memory │ ├── A7Q2_onebit_addersub.v │ ├── A7Q2_top.v │ ├── A7Q2_eightbit_addersub.v │ └── A7Q2_main.v └── Q1-Instruction-Memory │ ├── A7Q1_top.v │ └── A7Q1_main.v ├── Assignment 8 ├── problems.pdf ├── Q2-MIPS-Processor │ ├── code.c │ ├── A8Q2_top.v │ └── A8Q2_main.v └── Q1-MIPS-Processor │ ├── A8Q1_top.v │ └── A8Q1_main.v ├── Assignment 9 ├── problems.pdf ├── Q2-Dot-Product │ └── A9Q2.s └── Q1-Fibonacci │ └── A9Q1.s ├── Assignment 4 ├── Q2-Grid-Walk │ ├── A4Q2_one_bit_adder_sub.v │ ├── A4Q2_fivebit_adder_sub.v │ ├── A4Q2_grid_walk.v │ └── A4Q2_top.v ├── Q1-EightBit-Adder-Subtractor │ ├── A4Q1_onebit_addersub.v │ ├── A4Q1_eightbit_addersub.v │ └── A4Q1_top.v └── README.md ├── Assignment 2 ├── Q1-Decoder-And-Encoder │ ├── A2Q1_encoder8to3.v │ ├── A2Q1_decoder3to8.v │ └── A2Q1_top.v ├── Q3- Blink │ ├── A2Q3_blink.v │ └── A2Q3_top.v ├── Q4-Rotate │ ├── A2Q4_rotate.v │ └── A2Q4_top.v ├── Q2-Priority-Encoder │ ├── A2Q2_priority_encoder8to3.v │ └── A2Q2_top.v └── README.md ├── Assignment 3 ├── Q2-Finite-State-Machine │ ├── A3Q2_fsm.v │ └── A3Q2_fsm_top.v ├── Q1-DRAM-Bank-Read │ ├── A3Q1_read_top.v │ └── A3Q1_read.v └── README.md ├── Assignment 1 ├── Q1-Eight-Bit-Full-Adder │ ├── A1Q1_one_bit_full_adder.v │ ├── A1Q1_eight_bit_adder.v │ └── A1Q1_eight_bit_adder_top.v ├── Q2-Eight-Bit-Comparator │ ├── A1Q2_one_bit_comparator.v │ ├── A1Q2_eight_bit_comparator_top.v │ └── A1Q2_eight_bit_comparator.v └── README.md └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | *.out -------------------------------------------------------------------------------- /Assignment 10/problems.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bhuvansingla/cs220-computer-organization/HEAD/Assignment 10/problems.pdf -------------------------------------------------------------------------------- /Assignment 11/problems.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bhuvansingla/cs220-computer-organization/HEAD/Assignment 11/problems.pdf -------------------------------------------------------------------------------- /Assignment 5/problems.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bhuvansingla/cs220-computer-organization/HEAD/Assignment 5/problems.pdf -------------------------------------------------------------------------------- /Assignment 6/problems.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bhuvansingla/cs220-computer-organization/HEAD/Assignment 6/problems.pdf -------------------------------------------------------------------------------- /Assignment 7/problems.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bhuvansingla/cs220-computer-organization/HEAD/Assignment 7/problems.pdf -------------------------------------------------------------------------------- /Assignment 8/problems.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bhuvansingla/cs220-computer-organization/HEAD/Assignment 8/problems.pdf -------------------------------------------------------------------------------- /Assignment 9/problems.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bhuvansingla/cs220-computer-organization/HEAD/Assignment 9/problems.pdf -------------------------------------------------------------------------------- /Assignment 7/Q2-Instruction-Memory/A7Q2_onebit_addersub.v: -------------------------------------------------------------------------------- 1 | module onebit(a,b,cin,opcode,sum,cout); 2 | input a,b,cin,opcode; 3 | output sum,cout; 4 | wire sum,cout; 5 | assign sum=a^(b^opcode)^cin; 6 | assign cout=(a&(b^opcode))|((b^opcode)&cin)|(cin&a); 7 | endmodule -------------------------------------------------------------------------------- /Assignment 4/Q2-Grid-Walk/A4Q2_one_bit_adder_sub.v: -------------------------------------------------------------------------------- 1 | module onebit(a,b,cin,opcode,sum,cout); 2 | 3 | input a,b,cin,opcode; 4 | output sum,cout; 5 | wire sum,cout; 6 | assign sum=a^(b^opcode)^cin; 7 | assign cout=(a&(b^opcode))|((b^opcode)&cin)|(cin&a); 8 | 9 | endmodule -------------------------------------------------------------------------------- /Assignment 4/Q1-EightBit-Adder-Subtractor/A4Q1_onebit_addersub.v: -------------------------------------------------------------------------------- 1 | module onebit(a,b,cin,opcode,sum,cout); 2 | input a,b,cin,opcode; 3 | output sum,cout; 4 | wire sum,cout; 5 | assign sum=a^(b^opcode)^cin; 6 | assign cout=(a&(b^opcode))|((b^opcode)&cin)|(cin&a); 7 | endmodule -------------------------------------------------------------------------------- /Assignment 8/Q2-MIPS-Processor/code.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main(){ 4 | int a, b, c, i, sum; 5 | a = 0; 6 | b = 10; 7 | c = 2; 8 | sum = 0; 9 | 10 | for (i = a; i < b; i+=c){ 11 | sum += i; 12 | } 13 | 14 | printf("%d", sum); 15 | 16 | return 0; 17 | } -------------------------------------------------------------------------------- /Assignment 2/Q1-Decoder-And-Encoder/A2Q1_encoder8to3.v: -------------------------------------------------------------------------------- 1 | module encoder8to3(in, out); 2 | 3 | input [7:0] in; 4 | output wire [2:0] out; 5 | 6 | assign out[0] = in[1] | in[3] | in[5] | in[7]; 7 | assign out[1] = in[2] | in[3] | in[6] | in[7]; 8 | assign out[2] = in[4] | in[5] | in[6] | in[7]; 9 | 10 | endmodule -------------------------------------------------------------------------------- /Assignment 6/Q1-Miniature-Processor/code.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main() 4 | { 5 | short a, b, c, d; 6 | a = 17; 7 | printf("%h", a); b = -9; 8 | printf("%h %h", a, b); c = 65; 9 | printf("%h %h", b, c); 10 | d = 8*c - 512*(a + b); 11 | printf("%h", d); 12 | return 0; 13 | } -------------------------------------------------------------------------------- /Assignment 2/Q3- Blink/A2Q3_blink.v: -------------------------------------------------------------------------------- 1 | module blink(clk, out); 2 | 3 | input clk; 4 | output reg out = 0; 5 | 6 | reg [15:0] cycles = 0; 7 | 8 | always @(posedge clk) begin 9 | cycles <= cycles + 1; 10 | if(cycles == 25000) begin 11 | out <= ~out; 12 | cycles <= 1; 13 | end 14 | end 15 | 16 | endmodule -------------------------------------------------------------------------------- /Assignment 3/Q2-Finite-State-Machine/A3Q2_fsm.v: -------------------------------------------------------------------------------- 1 | `define TICK #1 2 | 3 | module fsm(clk,in,op); 4 | 5 | input clk,in; 6 | output wire op; 7 | reg a=0; 8 | reg b=0; 9 | 10 | always @(posedge clk) begin 11 | b <= `TICK (~in|a); 12 | a <= `TICK (in|b); 13 | end 14 | 15 | assign op = (~b&~in)|(~a&in); 16 | 17 | endmodule -------------------------------------------------------------------------------- /Assignment 1/Q1-Eight-Bit-Full-Adder/A1Q1_one_bit_full_adder.v: -------------------------------------------------------------------------------- 1 | module one_bit_full_adder (a, b, cin, sum, cout); 2 | 3 | input a; 4 | input b; 5 | input cin; 6 | 7 | output sum; 8 | wire sum; 9 | output cout; 10 | wire cout; 11 | 12 | assign sum = a ^ b ^ cin; 13 | assign cout = ((a & b) | (b & cin) | (cin & a)); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /Assignment 2/Q4-Rotate/A2Q4_rotate.v: -------------------------------------------------------------------------------- 1 | module rotate(clk, out); 2 | 3 | input clk; 4 | output reg [3:0] out = 4'b1000; 5 | 6 | reg [15:0] cycles = 0; 7 | 8 | always @(posedge clk) begin 9 | cycles <= cycles + 1; 10 | if (cycles == 25000) begin 11 | out[3] <= out[2]; 12 | out[2] <= out[1]; 13 | out[1] <= out[0]; 14 | out[0] <= out[3];; 15 | cycles <= 1; 16 | end 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /Assignment 2/Q2-Priority-Encoder/A2Q2_priority_encoder8to3.v: -------------------------------------------------------------------------------- 1 | module priority_encoder8to3(in, out); 2 | 3 | input [7:0] in; 4 | output wire [2:0] out; 5 | 6 | assign out = in[0] ? 3'b000 : 7 | in[1] ? 3'b001 : 8 | in[2] ? 3'b010 : 9 | in[3] ? 3'b011 : 10 | in[4] ? 3'b100 : 11 | in[5] ? 3'b101 : 12 | in[6] ? 3'b110 : 13 | 3'b111; 14 | 15 | endmodule -------------------------------------------------------------------------------- /Assignment 5/Q2-Smallest-Value/A5Q2_one_bit_comparator.v: -------------------------------------------------------------------------------- 1 | module one_bit_comparator(a, b, e_n_1, g_n_1, l_n_1, e_n, g_n, l_n); 2 | 3 | input a; 4 | input b; 5 | input e_n_1; 6 | input g_n_1; 7 | input l_n_1; 8 | 9 | output wire e_n; 10 | output wire g_n; 11 | output wire l_n; 12 | 13 | assign g_n = g_n_1 | (e_n_1 & (a & (~b))); 14 | assign e_n= e_n_1 & ~(a^b); 15 | assign l_n = l_n_1 | (e_n_1 & ((~a) & b)); 16 | 17 | endmodule -------------------------------------------------------------------------------- /Assignment 1/Q2-Eight-Bit-Comparator/A1Q2_one_bit_comparator.v: -------------------------------------------------------------------------------- 1 | module one_bit_comparator(a, b, e_n_1, g_n_1, l_n_1, e_n, g_n, l_n); 2 | 3 | input a; 4 | input b; 5 | input e_n_1; 6 | input g_n_1; 7 | input l_n_1; 8 | 9 | output wire e_n; 10 | output wire g_n; 11 | output wire l_n; 12 | 13 | assign g_n = g_n_1 | (e_n_1 & (a & (~b))); 14 | assign e_n= e_n_1 & ~(a^b); 15 | assign l_n = l_n_1 | (e_n_1 & ((~a) & b)); 16 | 17 | endmodule -------------------------------------------------------------------------------- /Assignment 2/Q3- Blink/A2Q3_top.v: -------------------------------------------------------------------------------- 1 | `include "./A2Q3_blink.v" 2 | 3 | module top; 4 | 5 | reg clk; 6 | wire out; 7 | 8 | blink BLINK(clk, out); 9 | 10 | always @(out) begin 11 | $display("Time: %d | Blink: %d", $time, out); 12 | end 13 | 14 | initial begin 15 | forever begin 16 | clk = 1; 17 | #5 18 | clk = 0; 19 | #5 20 | clk = 1; 21 | end 22 | end 23 | 24 | initial begin 25 | #3100000 26 | $finish; 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /Assignment 2/Q4-Rotate/A2Q4_top.v: -------------------------------------------------------------------------------- 1 | `include "./A2Q4_rotate.v" 2 | 3 | module top; 4 | 5 | reg clk; 6 | wire [3:0] out; 7 | 8 | rotate ROTATE(clk, out); 9 | 10 | always @(out) begin 11 | $display("Time: %d | Output: %b", $time, out); 12 | end 13 | 14 | initial begin 15 | forever begin 16 | clk = 1; 17 | #5 18 | clk = 0; 19 | #5 20 | clk = 1; 21 | end 22 | end 23 | 24 | initial begin 25 | #3100000 26 | $finish; 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /Assignment 2/Q1-Decoder-And-Encoder/A2Q1_decoder3to8.v: -------------------------------------------------------------------------------- 1 | module decoder3to8(in, out); 2 | 3 | input [2:0] in; 4 | output wire [7:0] out; 5 | 6 | assign out[0] = ~in[2] & ~in[1] & ~in[0]; 7 | assign out[1] = ~in[2] & ~in[1] & in[0]; 8 | assign out[2] = ~in[2] & in[1] & ~in[0]; 9 | assign out[3] = ~in[2] & in[1] & in[0]; 10 | assign out[4] = in[2] & ~in[1] & ~in[0]; 11 | assign out[5] = in[2] & ~in[1] & in[0]; 12 | assign out[6] = in[2] & in[1] & ~in[0]; 13 | assign out[7] = in[2] & in[1] & in[0]; 14 | 15 | endmodule -------------------------------------------------------------------------------- /Assignment 7/Q2-Instruction-Memory/A7Q2_top.v: -------------------------------------------------------------------------------- 1 | `include "./A7Q2_main.v" 2 | 3 | module top; 4 | 5 | reg clk; 6 | wire done; 7 | wire signed [7:0] out; 8 | main MAIN(clk, done, out); 9 | 10 | always @(posedge done) begin 11 | $display("OUTPUT_REG contains %d", out); 12 | #1 13 | $finish; 14 | end 15 | 16 | initial begin 17 | forever begin 18 | clk = 0; 19 | #5 20 | clk = 1; 21 | #5 22 | clk = 0; 23 | end 24 | end 25 | endmodule -------------------------------------------------------------------------------- /Assignment 8/Q1-MIPS-Processor/A8Q1_top.v: -------------------------------------------------------------------------------- 1 | `include "./A8Q1_main.v" 2 | 3 | module top; 4 | 5 | reg clk; 6 | wire done; 7 | wire signed [7:0] out; 8 | main MAIN(clk, done, out); 9 | 10 | always @(posedge done) begin 11 | $display("OUTPUT_REG contains %d", out); 12 | #1 13 | $finish; 14 | end 15 | 16 | initial begin 17 | forever begin 18 | clk = 0; 19 | #5 20 | clk = 1; 21 | #5 22 | clk = 0; 23 | end 24 | end 25 | endmodule -------------------------------------------------------------------------------- /Assignment 8/Q2-MIPS-Processor/A8Q2_top.v: -------------------------------------------------------------------------------- 1 | `include "./A8Q2_main.v" 2 | 3 | module top; 4 | 5 | reg clk; 6 | wire done; 7 | wire signed [7:0] out; 8 | main MAIN(clk, done, out); 9 | 10 | always @(posedge done) begin 11 | $display("OUTPUT_REG contains %d", out); 12 | #1 13 | $finish; 14 | end 15 | 16 | initial begin 17 | forever begin 18 | clk = 0; 19 | #5 20 | clk = 1; 21 | #5 22 | clk = 0; 23 | end 24 | end 25 | endmodule -------------------------------------------------------------------------------- /Assignment 5/Q2-Smallest-Value/A5Q2_three_bit_comparator.v: -------------------------------------------------------------------------------- 1 | `include "./A5Q2_one_bit_comparator.v" 2 | 3 | module three_bit_comparator(a, b, l); 4 | 5 | input [2:0] a; 6 | input [2:0] b; 7 | 8 | wire e; 9 | wire g; 10 | output wire l; 11 | 12 | wire [1:0] intermediate_e; 13 | wire [1:0] intermediate_g; 14 | wire [1:0] intermediate_l; 15 | 16 | one_bit_comparator C1 (a[2], b[2], 1'b1, 1'b0, 1'b0, intermediate_e[0], intermediate_g[0], intermediate_l[0]); 17 | one_bit_comparator C2 (a[1], b[1], intermediate_e[0], intermediate_g[0], intermediate_l[0], intermediate_e[1], intermediate_g[1], intermediate_l[1]); 18 | one_bit_comparator C3 (a[0], b[0], intermediate_e[1], intermediate_g[1], intermediate_l[1], e, g, l); 19 | 20 | endmodule -------------------------------------------------------------------------------- /Assignment 4/Q2-Grid-Walk/A4Q2_fivebit_adder_sub.v: -------------------------------------------------------------------------------- 1 | `include "./A4Q2_one_bit_adder_sub.v" 2 | 3 | module fivebit(a,b,opcode,sum,cout,overflow); 4 | 5 | input [4:0] a; 6 | input [1:0] b; 7 | input opcode; 8 | output [4:0] sum; 9 | output cout,overflow; 10 | wire cout,overflow; 11 | wire signed [4:0] sum; 12 | wire [3:0] intermediate_carry; 13 | onebit A0(a[0],b[0],opcode,opcode,sum[0],intermediate_carry[0]); 14 | onebit A1(a[1],b[1],intermediate_carry[0],opcode,sum[1],intermediate_carry[1]); 15 | onebit A2(a[2], 1'b0,intermediate_carry[1],opcode,sum[2],intermediate_carry[2]); 16 | onebit A3(a[3],1'b0,intermediate_carry[2],opcode,sum[3],intermediate_carry[3]); 17 | onebit A7(a[4],1'b0,intermediate_carry[3],opcode,sum[4],cout); 18 | assign overflow=intermediate_carry[3]^cout; 19 | endmodule -------------------------------------------------------------------------------- /Assignment 7/Q1-Instruction-Memory/A7Q1_top.v: -------------------------------------------------------------------------------- 1 | `include "./A7Q1_main.v" 2 | 3 | module top; 4 | 5 | reg clk; 6 | wire [2:0] pc, r, i, j, three, four, five, six; 7 | 8 | main MAIN(clk, pc, r, i, j, three, four, five, six); 9 | 10 | initial begin 11 | forever begin 12 | clk = 0; 13 | #5 14 | clk = 1; 15 | #5 16 | clk = 0; 17 | end 18 | end 19 | 20 | initial begin 21 | #80 22 | $display("R-format: %d\n", r); 23 | $display("I-format: %d\n", i); 24 | $display("J-format: %d\n", j); 25 | $display("Writes to $3: %d\n", three); 26 | $display("Writes to $4: %d\n", four); 27 | $display("Writes to $5: %d\n", five); 28 | $display("Writes to $6: %d\n", six); 29 | #1 30 | $finish; 31 | end 32 | endmodule -------------------------------------------------------------------------------- /Assignment 2/Q1-Decoder-And-Encoder/A2Q1_top.v: -------------------------------------------------------------------------------- 1 | `include "./A2Q1_decoder3to8.v" 2 | `include "./A2Q1_encoder8to3.v" 3 | 4 | module top; 5 | 6 | reg [2:0] in; 7 | wire [7:0] decodedOut; 8 | wire [2:0] encodedOut; 9 | 10 | decoder3to8 DECODER(in, decodedOut); 11 | encoder8to3 ENCODER(decodedOut, encodedOut); 12 | 13 | always @(in or encodedOut) begin 14 | $display("Time : %d | Decoder Input: %b | Encoder Output: %b", $time, in, encodedOut); 15 | end 16 | 17 | initial begin 18 | in = 3'b000; 19 | #1 20 | $display("\n"); 21 | in = 3'b001; 22 | #1 23 | $display("\n"); 24 | in = 3'b010; 25 | #1 26 | $display("\n"); 27 | in = 3'b011; 28 | #1 29 | $display("\n"); 30 | in = 3'b100; 31 | #1 32 | $display("\n"); 33 | in = 3'b101; 34 | #1 35 | $display("\n"); 36 | in = 3'b110; 37 | #1 38 | $display("\n"); 39 | in = 3'b111; 40 | #1 41 | $display("\n"); 42 | end 43 | 44 | endmodule -------------------------------------------------------------------------------- /Assignment 3/Q2-Finite-State-Machine/A3Q2_fsm_top.v: -------------------------------------------------------------------------------- 1 | `include "./A3Q2_fsm.v" 2 | 3 | module top; 4 | reg clk,in; 5 | wire op; 6 | fsm FSM(clk,in,op); 7 | 8 | always @(posedge clk) begin 9 | $display("Time=%2d,Input=%b,Alternating=%b",$time,in,op); 10 | end 11 | 12 | initial begin 13 | #100 14 | $finish; 15 | end 16 | 17 | initial begin 18 | forever begin 19 | clk=0; 20 | #5 21 | clk=1; 22 | #5 23 | clk=0; 24 | end 25 | end 26 | 27 | initial begin 28 | #3 29 | in=1; 30 | #10 31 | in=0; 32 | #10 33 | in=1; 34 | #10 35 | in=0; 36 | #10 37 | in=0; 38 | #10 39 | in=1; 40 | #10 41 | in=1; 42 | #10 43 | in=0; 44 | #10 45 | in=1; 46 | #10 47 | in=0; 48 | end 49 | 50 | endmodule -------------------------------------------------------------------------------- /Assignment 7/Q2-Instruction-Memory/A7Q2_eightbit_addersub.v: -------------------------------------------------------------------------------- 1 | `include "./A7Q2_onebit_addersub.v" 2 | 3 | module eightbit(a,b,opcode,sum,cout); 4 | input [7:0] a,b; 5 | input opcode; 6 | output [7:0] sum; 7 | output cout; 8 | wire cout; 9 | wire signed [7:0] sum; 10 | wire [6:0] intermediate_carry; 11 | onebit A0(a[0],b[0],opcode,opcode,sum[0],intermediate_carry[0]); 12 | onebit A1(a[1],b[1],intermediate_carry[0],opcode,sum[1],intermediate_carry[1]); 13 | onebit A2(a[2],b[2],intermediate_carry[1],opcode,sum[2],intermediate_carry[2]); 14 | onebit A3(a[3],b[3],intermediate_carry[2],opcode,sum[3],intermediate_carry[3]); 15 | onebit A4(a[4],b[4],intermediate_carry[3],opcode,sum[4],intermediate_carry[4]); 16 | onebit A5(a[5],b[5],intermediate_carry[4],opcode,sum[5],intermediate_carry[5]); 17 | onebit A6(a[6],b[6],intermediate_carry[5],opcode,sum[6],intermediate_carry[6]); 18 | onebit A7(a[7],b[7],intermediate_carry[6],opcode,sum[7],cout); 19 | endmodule -------------------------------------------------------------------------------- /Assignment 5/Q1-Fsm/A5Q1_top.v: -------------------------------------------------------------------------------- 1 | `include "./A5Q1_fsm.v" 2 | 3 | 4 | module top; 5 | wire [3:0] curr; 6 | reg [1:0] in; 7 | reg clk; 8 | 9 | 10 | implement FSM (in,curr,clk); 11 | 12 | always @(posedge clk) begin 13 | $display("time=%2d-->Output=%d\n",$time,curr); 14 | end 15 | initial begin 16 | #100 17 | $finish; 18 | end 19 | 20 | initial begin 21 | forever begin 22 | clk=0; 23 | #5 24 | clk=1; 25 | #5 26 | clk=0; 27 | end 28 | end 29 | 30 | initial begin 31 | #3 32 | in=2'b00; 33 | #10 34 | $display("\n"); 35 | in=2'b01; 36 | #10 37 | $display("\n"); 38 | in=2'b10; 39 | #10 40 | $display("\n"); 41 | in=2'b11; 42 | #10 43 | $display("\n"); 44 | in=2'b00; 45 | #10 46 | $display("\n"); 47 | in=2'b01; 48 | #10 49 | $display("\n"); 50 | in=2'b10; 51 | #10 52 | $display("\n"); 53 | in=2'b11; 54 | #10 55 | $display("\n"); 56 | in=2'b01; 57 | #10 58 | $display("\n"); 59 | end 60 | 61 | endmodule -------------------------------------------------------------------------------- /Assignment 4/Q1-EightBit-Adder-Subtractor/A4Q1_eightbit_addersub.v: -------------------------------------------------------------------------------- 1 | module eightbit(a,b,opcode,sum,cout,overflow); 2 | input [7:0] a,b; 3 | input opcode; 4 | output [7:0] sum; 5 | output cout,overflow; 6 | wire cout,overflow; 7 | wire signed [7:0] sum; 8 | wire [6:0] intermediate_carry; 9 | onebit A0(a[0],b[0],opcode,opcode,sum[0],intermediate_carry[0]); 10 | onebit A1(a[1],b[1],intermediate_carry[0],opcode,sum[1],intermediate_carry[1]); 11 | onebit A2(a[2],b[2],intermediate_carry[1],opcode,sum[2],intermediate_carry[2]); 12 | onebit A3(a[3],b[3],intermediate_carry[2],opcode,sum[3],intermediate_carry[3]); 13 | onebit A4(a[4],b[4],intermediate_carry[3],opcode,sum[4],intermediate_carry[4]); 14 | onebit A5(a[5],b[5],intermediate_carry[4],opcode,sum[5],intermediate_carry[5]); 15 | onebit A6(a[6],b[6],intermediate_carry[5],opcode,sum[6],intermediate_carry[6]); 16 | onebit A7(a[7],b[7],intermediate_carry[6],opcode,sum[7],cout); 17 | assign overflow=intermediate_carry[6]^cout; 18 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # CS220 - Computer Organization 2 | 3 | This repositiory contains submissions for the assignments completed in the semester 2020-21-II offering of [CS220 (Computer Organization)](https://www.cse.iitk.ac.in/pages/CS220.html) at the [Indian Institue of Technology Kanpur](https://iitk.ac.in/). 4 | 5 | Assignments have been completed using [Verilog HDL](https://en.wikipedia.org/wiki/Verilog), [MIPS](https://en.wikipedia.org/wiki/MIPS_architecture) and [SPIM](https://en.wikipedia.org/wiki/SPIM). 6 | 7 | ## Collaborators 8 | - [Bhuvan Singla](https://github.com/bhuvansingla) 9 | - [Soham Ghosal](https://github.com/soham1192k) 10 | 11 | ## Course Instructor 12 | - [Dr. Mainak Chaudhuri](https://www.cse.iitk.ac.in/users/mainakc/) 13 | 14 | ## Installation and Execution 15 | ### Verilog 16 | ```bash 17 | # install verilog 18 | sudo apt update 19 | sudo apt install verilog 20 | 21 | # compile 22 | iverilog -o 23 | 24 | # run 25 | ./ 26 | ``` 27 | ### SPIM 28 | Download from http://spimsimulator.sourceforge.net/ 29 | 30 | -------------------------------------------------------------------------------- /Assignment 2/Q2-Priority-Encoder/A2Q2_top.v: -------------------------------------------------------------------------------- 1 | `include "./A2Q2_priority_encoder8to3.v" 2 | 3 | module top; 4 | 5 | reg [7:0] in; 6 | wire [2:0] encodedOut; 7 | 8 | priority_encoder8to3 ENCODER(in, encodedOut); 9 | 10 | always @(in or encodedOut) begin 11 | $display("Time = %d | Input: %b | Encoded: %b", $time, in, encodedOut); 12 | end 13 | 14 | initial begin 15 | $display("Format: Input: Y7Y6Y5Y4Y3Y2Y1Y0 | Encoded: X2X1X0\n"); 16 | in = 8'b00010000; 17 | #1 18 | $display("\n"); 19 | in = 8'b01000100; 20 | #1 21 | $display("\n"); 22 | in = 8'b11110000; 23 | #1 24 | $display("\n"); 25 | in = 8'b00010001; 26 | #1 27 | $display("\n"); 28 | in = 8'b11111111; 29 | #1 30 | $display("\n"); 31 | in = 8'b00011000; 32 | #1 33 | $display("\n"); 34 | in = 8'b00000110; 35 | #1 36 | $display("\n"); 37 | in = 8'b01010100; 38 | #1 39 | $display("\n"); 40 | in = 8'b00011101; 41 | #1 42 | $display("\n"); 43 | in = 8'b00100000; 44 | #1 45 | $display("\n"); 46 | end 47 | 48 | endmodule -------------------------------------------------------------------------------- /Assignment 1/Q1-Eight-Bit-Full-Adder/A1Q1_eight_bit_adder.v: -------------------------------------------------------------------------------- 1 | `include "./A1Q1_one_bit_full_adder.v" 2 | 3 | module eight_bit_adder (x, y, carry_in, sum, carry_out); 4 | 5 | input [7:0] x; 6 | input [7:0] y; 7 | input carry_in; 8 | 9 | output [7:0] sum; 10 | wire [7:0] sum; 11 | output carry_out; 12 | wire carry_out; 13 | 14 | wire [6:0] intermediate_carry; 15 | 16 | one_bit_full_adder FA0 (x[0], y[0], carry_in, sum[0], intermediate_carry[0]); 17 | one_bit_full_adder FA1 (x[1], y[1], intermediate_carry[0], sum[1], intermediate_carry[1]); 18 | one_bit_full_adder FA2 (x[2], y[2], intermediate_carry[1], sum[2], intermediate_carry[2]); 19 | one_bit_full_adder FA3 (x[3], y[3], intermediate_carry[2], sum[3], intermediate_carry[3]); 20 | one_bit_full_adder FA4 (x[4], y[4], intermediate_carry[3], sum[4], intermediate_carry[4]); 21 | one_bit_full_adder FA5 (x[5], y[5], intermediate_carry[4], sum[5], intermediate_carry[5]); 22 | one_bit_full_adder FA6 (x[6], y[6], intermediate_carry[5], sum[6], intermediate_carry[6]); 23 | one_bit_full_adder FA7 (x[7], y[7], intermediate_carry[6], sum[7], carry_out); 24 | 25 | endmodule -------------------------------------------------------------------------------- /Assignment 5/Q2-Smallest-Value/A5Q2_smallest_three_bit.v: -------------------------------------------------------------------------------- 1 | `include "./A5Q2_three_bit_comparator.v" 2 | 3 | module smallest(in0, in1, in2, in3, idx); 4 | 5 | input [2:0] in0; 6 | input [2:0] in1; 7 | input [2:0] in2; 8 | input [2:0] in3; 9 | 10 | wire smaller0vs1; 11 | wire smaller0vs2; 12 | wire smaller0vs3; 13 | wire smaller2vs3; 14 | wire smaller1vs2; 15 | wire smaller1vs3; 16 | 17 | three_bit_comparator C1(in0, in1, smaller0vs1); 18 | three_bit_comparator C2(in0, in2, smaller0vs2); 19 | three_bit_comparator C3(in0, in3, smaller0vs3); 20 | three_bit_comparator C4(in1, in2, smaller1vs2); 21 | three_bit_comparator C5(in1, in3, smaller1vs3); 22 | three_bit_comparator C6(in2, in3, smaller2vs3); 23 | 24 | output wire [1:0] idx; 25 | 26 | output wire isIndexZeroSmallest; 27 | output wire isIndexOneSmallest; 28 | output wire isIndexTwoSmallest; 29 | 30 | assign isIndexZeroSmallest = (smaller0vs1 ? (smaller0vs2 ? (smaller0vs3 ? 1 : 0) : 0) : 0); 31 | assign isIndexOneSmallest = (smaller1vs2 ? (smaller1vs3 ? 1 : 0) : 0); 32 | assign isIndexTwoSmallest = (smaller2vs3 ? 1 : 0); 33 | assign idx = isIndexZeroSmallest ? 2'b00 : (isIndexOneSmallest ? 2'b01 : (isIndexTwoSmallest ? 2'b10 : 2'b11)); 34 | 35 | endmodule -------------------------------------------------------------------------------- /Assignment 1/Q2-Eight-Bit-Comparator/A1Q2_eight_bit_comparator_top.v: -------------------------------------------------------------------------------- 1 | `include "./A1Q2_eight_bit_comparator.v" 2 | 3 | module eight_bit_comparator_top; 4 | 5 | reg [7:0] a; 6 | reg [7:0] b; 7 | 8 | wire e; 9 | wire g; 10 | wire l; 11 | 12 | eight_bit_comparator COMPARE(a, b, e, g, l); 13 | 14 | always @(g or e or l or a or b) begin 15 | $display("time = %d | a = %d, b = %d | G = %d, E = %d, L = %d", $time, a, b, g, e, l); 16 | end 17 | 18 | initial begin 19 | a = 10; b = 20; 20 | #1 21 | $display("\n"); 22 | a = 10; b = 10; 23 | #1 24 | $display("\n"); 25 | a = 1; b = 0; 26 | #1 27 | $display("\n"); 28 | a = 255; b = 255; 29 | #1 30 | $display("\n"); 31 | a = 0; b = 9; 32 | #1 33 | $display("\n"); 34 | a = 150; b = 111; 35 | #1 36 | $display("\n"); 37 | a = 12; b = 20; 38 | #1 39 | $display("\n"); 40 | a = 19; b = 91; 41 | #1 42 | $display("\n"); 43 | a = 22; b = 220; 44 | #1 45 | $display("\n"); 46 | a = 99; b = 99; 47 | #1 48 | $display("\n"); 49 | end 50 | 51 | endmodule -------------------------------------------------------------------------------- /Assignment 10/Q2-Alternating-Sum/A10Q2.s: -------------------------------------------------------------------------------- 1 | .data 2 | arrayX: .space 60 3 | msg: .asciiz "Answer: " 4 | endmsg: .asciiz "\n" 5 | 6 | .text 7 | .globl main 8 | main: li $v0,5 9 | syscall 10 | addi $t0,$v0,0 11 | addi $t2,$v0,0 12 | la $t1,arrayX 13 | 14 | loop: li $v0,6 15 | syscall 16 | swc1 $f0,0($t1) 17 | addi $t1,$t1,4 18 | addi $t0,$t0,-1 19 | bne $t0,$0,loop 20 | 21 | la $t1,arrayX 22 | mtc1 $0,$f3 23 | addi $t0,$t0,0 24 | addi $t6,$t6,2 25 | 26 | loop2: lwc1 $f1,0($t1) 27 | divu $t0,$t6 28 | mfhi $t7 29 | beq $t7,$0,positive 30 | sub.s $f3,$f3,$f1 31 | j out 32 | positive: add.s $f3,$f3,$f1 33 | out: addi $t1,$t1,4 34 | addi $t0,$t0,1 35 | bne $t0,$t2,loop2 36 | 37 | mov.s $f12,$f3 38 | li $v0,4 39 | la $a0,msg 40 | syscall 41 | li $v0,2 42 | syscall 43 | li $v0,4 44 | la $a0,endmsg 45 | syscall 46 | jr $ra 47 | -------------------------------------------------------------------------------- /Assignment 9/Q2-Dot-Product/A9Q2.s: -------------------------------------------------------------------------------- 1 | .data 2 | arrayX: .space 60 3 | arrayY: .space 60 4 | msg: .asciiz "Dot Product: " 5 | endmsg: .asciiz "\n" 6 | 7 | .text 8 | .globl main 9 | main: li $v0,5 10 | syscall 11 | addi $t0,$v0,0 12 | addi $t2,$v0,0 13 | la $t1,arrayX 14 | 15 | loop: li $v0,6 16 | syscall 17 | swc1 $f0,0($t1) 18 | addi $t1,$t1,4 19 | addi $t0,$t0,-1 20 | bne $t0,$0,loop 21 | 22 | la $t1,arrayY 23 | addi $t0,$t2,0 24 | 25 | loop1: li $v0,6 26 | syscall 27 | swc1 $f0,0($t1) 28 | addi $t1,$t1,4 29 | addi $t0,$t0,-1 30 | bne $t0,$0,loop1 31 | 32 | addi $t0,$t2,0 33 | la $t1,arrayX 34 | la $t3,arrayY 35 | mtc1 $0,$f3 36 | 37 | loop2: lwc1 $f1,0($t1) 38 | lwc1 $f2,0($t3) 39 | mul.s $f1,$f1,$f2 40 | add.s $f3,$f3,$f1 41 | addi $t1,$t1,4 42 | addi $t3,$t3,4 43 | addi $t0,$t0,-1 44 | bne $t0,$0,loop2 45 | mov.s $f12,$f3 46 | li $v0,4 47 | la $a0,msg 48 | syscall 49 | li $v0,2 50 | syscall 51 | li $v0,4 52 | la $a0,endmsg 53 | syscall 54 | jr $ra 55 | -------------------------------------------------------------------------------- /Assignment 9/Q1-Fibonacci/A9Q1.s: -------------------------------------------------------------------------------- 1 | .data 2 | input_msg: .asciiz "Enter n: " 3 | comma: .asciiz ", " 4 | .text 5 | .globl main 6 | fib: move $t1,$0 7 | move $t2,$sp 8 | li $t3,1 9 | addi $sp,$sp,-4 10 | sw $t0,0($sp) 11 | rec: beq $sp,$t2,fib_exit 12 | lw $t4,0($sp) 13 | addi $sp,$sp,4 14 | bleu $t4,$t3,rec_return 15 | sub $t4,$t4,1 16 | addi $sp,$sp,-4 17 | sw $t4,0($sp) 18 | sub $t4,$t4,1 19 | addi $sp,$sp,-4 20 | sw $t4,0($sp) 21 | j rec 22 | rec_return: add $t1,$t1,$t4 23 | j rec 24 | fib_exit: jr $ra 25 | main: li $v0,4 26 | la $a0,input_msg 27 | syscall 28 | li $v0,5 29 | syscall 30 | addi $t5,$v0,0 31 | addi $t5,$t5,1 32 | move $t0,$0 33 | loop: beq $t0,$t5,exit 34 | jal fib 35 | beq $t0,$0,go 36 | jal print 37 | go: addi $t0,$t0,1 38 | j loop 39 | print: li $v0,1 40 | addi $a0,$t1,0 41 | syscall 42 | addi $t6,$t5,-1 43 | beq $t6,$t0,label 44 | li $v0,4 45 | la $a0,comma 46 | syscall 47 | label: jr $ra 48 | exit: li $v0,10 49 | syscall 50 | -------------------------------------------------------------------------------- /Assignment 1/Q1-Eight-Bit-Full-Adder/A1Q1_eight_bit_adder_top.v: -------------------------------------------------------------------------------- 1 | `include "./A1Q1_eight_bit_adder.v" 2 | 3 | module eight_bit_adder_top; 4 | 5 | reg [7:0] A; 6 | reg [7:0] B; 7 | reg Cin; 8 | 9 | wire [7:0] Sum; 10 | wire Carry; 11 | 12 | eight_bit_adder ADDER (.x(A), .y(B), .carry_in(Cin), .sum(Sum), .carry_out(Carry)); 13 | 14 | always @ (A or B or Cin or Sum or Carry) 15 | begin 16 | $display("time=%d | %d + %d + %d = %d, carry = %d", $time, A, B, Cin, Sum, Carry); 17 | end 18 | 19 | initial begin 20 | A = 0; B = 0; Cin = 0; 21 | #1 22 | $display("\n"); 23 | A = 2; B = 4; Cin = 1; 24 | #1 25 | $display("\n"); 26 | A = 26; B = 144; Cin = 1; 27 | #1 28 | $display("\n"); 29 | A = 128; B = 8; Cin = 0; 30 | #1 31 | $display("\n"); 32 | A = 196; B = 36; Cin = 0; 33 | #1 34 | $display("\n"); 35 | A = 147; B = 120; Cin = 1; 36 | #1 37 | $display("\n"); 38 | A = 147; B = 120; Cin = 1; 39 | #1 40 | $display("\n"); 41 | A = 63; B = 18; Cin = 1; 42 | #1 43 | $display("\n"); 44 | A = 255; B = 254; Cin = 1; 45 | #1 46 | $display("\n"); 47 | A = 170; B = 255; Cin = 0; 48 | #1 49 | $display("\n"); 50 | A = 238; B = 17; Cin = 0; 51 | #1 52 | $display("\n"); 53 | $finish; 54 | end 55 | 56 | endmodule -------------------------------------------------------------------------------- /Assignment 4/Q2-Grid-Walk/A4Q2_grid_walk.v: -------------------------------------------------------------------------------- 1 | `include "./A4Q2_fivebit_adder_sub.v" 2 | 3 | module grid_walk(steps, direction, clk, x, y); 4 | 5 | 6 | input wire [1:0] steps; 7 | input wire [1:0] direction; 8 | input wire clk; 9 | 10 | output reg signed [4:0] x = 5'b00000, y = 5'b00000; 11 | 12 | assign direction_op_code = direction == 2'b00 | direction == 2'b01 ? 0 : 1; 13 | 14 | wire signed [4:0] newX, newY; 15 | 16 | wire coutX ,overflowX; 17 | wire coutY ,overflowY; 18 | 19 | fivebit addX(x, steps, direction_op_code, newX, coutX, overflowX); 20 | fivebit addY(y, steps, direction_op_code, newY, coutY, overflowY); 21 | 22 | always @(posedge clk) begin 23 | if (direction == 2'b00) begin 24 | if(newX[4] == 1) begin 25 | x <= 5'b01111; 26 | end 27 | else begin 28 | x <= newX; 29 | end 30 | end 31 | else if (direction == 2'b10) begin 32 | if(newX[4] == 1) begin 33 | x <= 5'b00000; 34 | end 35 | else begin 36 | x <= newX; 37 | end 38 | end 39 | else if (direction == 2'b01) begin 40 | if(newY[4] == 1) begin 41 | y <= 5'b01111; 42 | end 43 | else begin 44 | y <= newY; 45 | end 46 | end 47 | else begin 48 | if(newY[4] == 1) begin 49 | y <= 5'b00000; 50 | end 51 | else begin 52 | y <= newY; 53 | end 54 | end 55 | end 56 | 57 | endmodule -------------------------------------------------------------------------------- /Assignment 4/Q1-EightBit-Adder-Subtractor/A4Q1_top.v: -------------------------------------------------------------------------------- 1 | `include "./A4Q1_onebit_addersub.v" 2 | `include "./A4Q1_eightbit_addersub.v" 3 | 4 | module top; 5 | reg signed [7:0] a,b; 6 | reg opcode; 7 | wire signed [7:0] sum; 8 | wire cout; 9 | wire overflow; 10 | eightbit EIGHTBIT(a,b,opcode,sum,cout,overflow); 11 | always @ (a or b or opcode or sum or cout or overflow) 12 | begin 13 | $display("time=%d | A=%d, B=%d, OPCODE=%d, OUTPUT = %d, CARRY = %d, OVERFLOW = %b", $time, a, b, opcode, sum, cout, overflow); 14 | end 15 | initial begin 16 | a = 0; b = 0; opcode = 0; 17 | #1 18 | $display("\n"); 19 | a = 2; b = 4; opcode = 1; 20 | #1 21 | $display("\n"); 22 | a = 26; b = 127; opcode = 1; 23 | #1 24 | $display("\n"); 25 | a = 127; b = 1;opcode = 0; 26 | #1 27 | $display("\n"); 28 | a = 96; b = 36; opcode = 0; 29 | #1 30 | $display("\n"); 31 | a = 47; b = 120; opcode= 1; 32 | #1 33 | $display("\n"); 34 | a = 47; b = 120; opcode = 0; 35 | #1 36 | $display("\n"); 37 | a = 63; b = 18; opcode = 1; 38 | #1 39 | $display("\n"); 40 | a = 5; b = 54; opcode= 1; 41 | #1 42 | $display("\n"); 43 | a = 70; b = 35; opcode = 0; 44 | #1 45 | $display("\n"); 46 | a = 38; b = 17; opcode= 0; 47 | #1 48 | $display("\n"); 49 | $finish; 50 | end 51 | endmodule -------------------------------------------------------------------------------- /Assignment 1/Q2-Eight-Bit-Comparator/A1Q2_eight_bit_comparator.v: -------------------------------------------------------------------------------- 1 | `include "./A1Q2_one_bit_comparator.v" 2 | 3 | module eight_bit_comparator(a, b, e, g, l); 4 | 5 | input [7:0] a; 6 | input [7:0] b; 7 | 8 | output wire e; 9 | output wire g; 10 | output wire l; 11 | 12 | wire [6:0] intermediate_e; 13 | wire [6:0] intermediate_g; 14 | wire [6:0] intermediate_l; 15 | 16 | 17 | one_bit_comparator C1 (a[7], b[7], 1'b1, 1'b0, 1'b0, intermediate_e[0], intermediate_g[0], intermediate_l[0]); 18 | one_bit_comparator C2 (a[6], b[6], intermediate_e[0], intermediate_g[0], intermediate_l[0], intermediate_e[1], intermediate_g[1], intermediate_l[1]); 19 | one_bit_comparator C3 (a[5], b[5], intermediate_e[1], intermediate_g[1], intermediate_l[1], intermediate_e[2], intermediate_g[2], intermediate_l[2]); 20 | one_bit_comparator C4 (a[4], b[4], intermediate_e[2], intermediate_g[2], intermediate_l[2], intermediate_e[3], intermediate_g[3], intermediate_l[3]); 21 | one_bit_comparator C5 (a[3], b[3], intermediate_e[3], intermediate_g[3], intermediate_l[3], intermediate_e[4], intermediate_g[4], intermediate_l[4]); 22 | one_bit_comparator C6 (a[2], b[2], intermediate_e[4], intermediate_g[4], intermediate_l[4], intermediate_e[5], intermediate_g[5], intermediate_l[5]); 23 | one_bit_comparator C7 (a[1], b[1], intermediate_e[5], intermediate_g[5], intermediate_l[5], intermediate_e[6], intermediate_g[6], intermediate_l[6]); 24 | one_bit_comparator C8 (a[0], b[0], intermediate_e[6], intermediate_g[6], intermediate_l[6], e, g, l); 25 | 26 | endmodule -------------------------------------------------------------------------------- /Assignment 5/Q1-Fsm/A5Q1_fsm.v: -------------------------------------------------------------------------------- 1 | module implement(in,curr,clk); 2 | input [1:0] in;//2 bit input 3 | input clk;//clock 4 | 5 | output reg [3:0] curr=4'b0;//current state 6 | 7 | reg [2:0] microcode_rom [12:0];//13 states 8 | 9 | wire [3:0] micro_instruction;//4 bit microinstruction 10 | 11 | reg [3:0] dispatch_rom_1 [3:0]; 12 | reg [3:0] dispatch_rom_2 [3:0]; 13 | reg [3:0] dispatch_rom_3,dispatch_rom_4; 14 | 15 | initial begin 16 | microcode_rom[0]=0; 17 | microcode_rom[1]=0; 18 | microcode_rom[2]=0; 19 | microcode_rom[3]=1; 20 | microcode_rom[4]=3; 21 | microcode_rom[5]=3; 22 | microcode_rom[6]=3; 23 | microcode_rom[7]=0; 24 | microcode_rom[8]=0; 25 | microcode_rom[9]=0; 26 | microcode_rom[10]=2; 27 | microcode_rom[11]=4; 28 | microcode_rom[12]=4; 29 | dispatch_rom_1[0]=4; 30 | dispatch_rom_1[1]=5; 31 | dispatch_rom_1[2]=6; 32 | dispatch_rom_1[3]=6; 33 | dispatch_rom_2[0]=11; 34 | dispatch_rom_2[1]=12; 35 | dispatch_rom_2[2]=12; 36 | dispatch_rom_2[3]=12; 37 | dispatch_rom_3=7; 38 | dispatch_rom_4=0; 39 | end 40 | 41 | assign micro_instruction=microcode_rom[curr]; 42 | always @(posedge clk) begin 43 | if (micro_instruction==0) begin 44 | curr<=#2 curr+1; 45 | end 46 | else if (micro_instruction==1) begin 47 | curr<=#2 dispatch_rom_1[in]; 48 | end 49 | else if (micro_instruction==2) begin 50 | curr<=#2 dispatch_rom_2[in]; 51 | end 52 | else if (micro_instruction==3) begin 53 | curr<=#2 dispatch_rom_3; 54 | end 55 | else begin 56 | curr<=#2 dispatch_rom_4; 57 | end 58 | end 59 | endmodule -------------------------------------------------------------------------------- /Assignment 5/Q2-Smallest-Value/A5Q2_top.v: -------------------------------------------------------------------------------- 1 | `include "./A5Q2_smallest_three_bit.v" 2 | 3 | module top; 4 | 5 | reg [2:0] in0; 6 | reg [2:0] in1; 7 | reg [2:0] in2; 8 | reg [2:0] in3; 9 | 10 | wire [1:0] idx; 11 | 12 | smallest compare(in0, in1, in2, in3, idx); 13 | 14 | initial begin 15 | in0 = 3'b000; in1 = 3'b000; in2 = 3'b010; in3 = 3'b111; 16 | #1 17 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 18 | 19 | in0 = 3'b000; in1 = 3'b100; in2 = 3'b010; in3 = 3'b001; 20 | #1 21 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 22 | 23 | in0 = 3'b000; in1 = 3'b000; in2 = 3'b000; in3 = 3'b000; 24 | #1 25 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 26 | 27 | in0 = 3'b101; in1 = 3'b101; in2 = 3'b110; in3 = 3'b000; 28 | #1 29 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 30 | 31 | in0 = 3'b101; in1 = 3'b101; in2 = 3'b110; in3 = 3'b111; 32 | #1 33 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 34 | 35 | in0 = 3'b101; in1 = 3'b101; in2 = 3'b101; in3 = 3'b100; 36 | #1 37 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 38 | 39 | in0 = 3'b101; in1 = 3'b111; in2 = 3'b110; in3 = 3'b000; 40 | #1 41 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 42 | 43 | in0 = 3'b001; in1 = 3'b101; in2 = 3'b010; in3 = 3'b011; 44 | #1 45 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 46 | 47 | in0 = 3'b101; in1 = 3'b111; in2 = 3'b110; in3 = 3'b000; 48 | #1 49 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 50 | 51 | in0 = 3'b111; in1 = 3'b111; in2 = 3'b110; in3 = 3'b111; 52 | #1 53 | $display("%d, %d, %d, %d | Output: %d", in0, in1, in2, in3, idx); 54 | end 55 | 56 | endmodule -------------------------------------------------------------------------------- /Assignment 6/Q1-Miniature-Processor/A6Q1_top.v: -------------------------------------------------------------------------------- 1 | `include "./A6Q1_call.v" 2 | 3 | module top; 4 | 5 | reg [4:0] read1,read2,write; 6 | reg signed [15:0] data; 7 | reg [2:0] cmd; 8 | reg clk; 9 | wire done; 10 | reg start; 11 | 12 | reg [4:0] inst_num = 0; 13 | 14 | call CALL(read1, read2, write, data, cmd, clk, done); 15 | 16 | 17 | always @(posedge done or posedge start) begin 18 | 19 | if (inst_num == 0) begin 20 | cmd=3'b000; write=1; data=17; 21 | end 22 | else if (inst_num == 1) begin 23 | cmd=3'b011; read1=1; write=2; data=-9; 24 | end 25 | else if (inst_num == 2) begin 26 | cmd=3'b100; read1=1; read2=2; write=3; data=65; 27 | end 28 | else if (inst_num == 3) begin 29 | cmd=3'b010; read1=2; read2=3; 30 | end 31 | else if (inst_num == 4) begin 32 | cmd=3'b111; read1=3; write=5; data=3; 33 | end 34 | else if (inst_num == 5) begin 35 | cmd=3'b101; read1=1; read2=2; write=4; 36 | end 37 | else if (inst_num == 6) begin 38 | cmd=3'b111; read1=4; write=4; data=9; 39 | end 40 | else if (inst_num == 7) begin 41 | cmd=3'b110; read1=5; read2=4; write=6; 42 | end 43 | else if (inst_num == 8) begin 44 | cmd=3'b001; read1=6; 45 | end 46 | else begin 47 | $display("Program completed."); 48 | $finish; 49 | end 50 | 51 | inst_num <= inst_num + 1; 52 | end 53 | 54 | initial begin 55 | forever begin 56 | clk=0; 57 | #5 58 | clk=1; 59 | #5 60 | clk=0; 61 | end 62 | end 63 | 64 | initial begin 65 | start=1; 66 | #1 67 | start=0; 68 | end 69 | 70 | endmodule -------------------------------------------------------------------------------- /Assignment 3/Q1-DRAM-Bank-Read/A3Q1_read_top.v: -------------------------------------------------------------------------------- 1 | `include "./A3Q1_read.v" 2 | 3 | module read_top; 4 | reg clk,input_valid; 5 | reg [3:0] row_number; 6 | wire output_valid; 7 | wire [31:0] op; 8 | 9 | read READ(clk,row_number,input_valid,op,output_valid); 10 | 11 | always @(posedge output_valid) begin 12 | $display("Time=%3d,Row Number=%d,Output=%2d\n",$time,row_number,op); 13 | end 14 | 15 | initial begin 16 | #300 17 | $finish; 18 | end 19 | 20 | initial begin 21 | forever begin 22 | clk=0; 23 | #5 24 | clk=1; 25 | #5 26 | clk=0; 27 | end 28 | end 29 | 30 | initial begin 31 | #3 32 | input_valid=1; 33 | row_number=1; 34 | #10 35 | input_valid=0; 36 | #20 37 | input_valid=1; 38 | row_number=1; 39 | #10 40 | input_valid=0; 41 | #20 42 | input_valid=1; 43 | row_number=15; 44 | #10 45 | input_valid=0; 46 | #20 47 | input_valid=1; 48 | row_number=10; 49 | #10 50 | input_valid=0; 51 | #20 52 | input_valid=1; 53 | row_number=13; 54 | #10 55 | input_valid=0; 56 | #20 57 | input_valid=1; 58 | row_number=13; 59 | #10 60 | input_valid=0; 61 | #20 62 | input_valid=1; 63 | row_number=8; 64 | #10 65 | input_valid=0; 66 | #20 67 | input_valid=1; 68 | row_number=10; 69 | #10 70 | input_valid=0; 71 | #20 72 | input_valid=1; 73 | row_number=11; 74 | #10 75 | input_valid=0; 76 | #20 77 | input_valid=1; 78 | row_number=12; 79 | #10 80 | input_valid=0; 81 | end 82 | endmodule 83 | -------------------------------------------------------------------------------- /Assignment 11/Q1-Booths-Algorithm/A11Q1_booth.v: -------------------------------------------------------------------------------- 1 | `define SIZE 32 2 | 3 | module booth(multiplicand, multiplier, clk, newInput, product, done, numAdd, numSub); 4 | 5 | input signed [31:0] multiplicand, multiplier; 6 | input clk, newInput; 7 | 8 | output reg signed [63:0] product = 64'b0; 9 | output reg done = 0; 10 | output reg [4:0] numAdd = 0, numSub = 0; 11 | 12 | reg [4:0] curr_idx = 0; 13 | reg curr_multiplier_bit; 14 | reg prev_multiplier_bit = 0; 15 | reg signed [31:0] temp_multiplier; 16 | 17 | always @(posedge newInput) begin 18 | product <= 64'b0; 19 | curr_idx <= 0; 20 | prev_multiplier_bit <= 0; 21 | done <= 0; 22 | numAdd <= 0; 23 | numSub <= 0; 24 | end 25 | 26 | always @(posedge clk) begin 27 | curr_multiplier_bit <= multiplier[curr_idx]; 28 | #1 29 | if (curr_multiplier_bit != prev_multiplier_bit) begin 30 | if (curr_multiplier_bit == 1) begin 31 | product <= product - (multiplicand << curr_idx); 32 | numSub <= numSub + 1; 33 | end 34 | else begin 35 | product <= product + (multiplicand << curr_idx); 36 | numAdd <= numAdd + 1; 37 | end 38 | end 39 | 40 | temp_multiplier <= multiplier >>> (curr_idx + 1); 41 | #1 42 | if (curr_multiplier_bit == 0) begin 43 | if (temp_multiplier == 0) begin 44 | done <= 1; 45 | end 46 | end 47 | else begin 48 | if(temp_multiplier == -1) begin 49 | done <= 1; 50 | 51 | end 52 | end 53 | 54 | if (curr_idx == `SIZE - 1) begin 55 | done <= 1; 56 | end 57 | curr_idx <= curr_idx + 1; 58 | prev_multiplier_bit <= curr_multiplier_bit; 59 | end 60 | 61 | endmodule -------------------------------------------------------------------------------- /Assignment 4/README.md: -------------------------------------------------------------------------------- 1 | [40 points] 1. Design an eight-bit adder/subtracter to add/subtract two eight-bit two's complement numbers. Divide your design into three modules. One module implements a one-bit adder/subtracter with four inputs a, b, cin, and opcode and two outputs sum and carry. The input opcode is 0 if the operation is an addition and it is 1 if the operation is a subtraction. The second module implements the eight-bit adder/subtracter using the one-bit adder/subtracter module. This module takes three inputs namely, the two input numbers and the opcode. It produces three outputs namely, the sum, the carry out, and whether there is an overflow. Implement a top module to test your implementation. Keep one time unit gap between two consecutive test input sets. 2 | 3 | [60 points] 2. Imagine a 15x15 grid (length of each side is 15). The leftmost bottom corner is (0, 0). The leftmost top corner is (0, 15). The rightmost top corner is (15, 15). The rightmost bottom corner is (15, 0). A worm is sitting at (0, 0) to start with. In each move, the worm can take 0, 1, 2, or 3 steps 4 | along east, west, north, or south directions. If the move causes the worm to hit the boundary, it stops there. For example, at (0, 0) if it tries to move toward west or south it stays at (0 0); at (13 0) if it tries to move toward east three steps, it takes only two steps and stops at (15, 0). Two time units before each rising clock edge a new input is provided. The input comes in the form of a direction (two bits) and the number of steps (two bits). Write a module to compute the new coordinates of the worm based on the input using a five-bit adder/subtracter. The new coordinates are computed on each rising edge of the clock. Write a top module to test your design. You can display the new coordinates along with your inputs just before sending a new input. 5 | 6 | Submission: Submit your verilog files named clearly. Prefix the file names for Q1 using A4Q1_ and those for Q2 using A4_Q2_. Email the files as attachment to cs220spring2021submit@gmail.com. The subject line of the email MUST be the following (replace N by your group number): Assignment#4 submission for Group#N -------------------------------------------------------------------------------- /Assignment 11/Q2-Non-Restoring-Division/A11Q2_nrd.v: -------------------------------------------------------------------------------- 1 | `define SIZE 32 2 | 3 | module nrd(dividend, divisor, clk, len_dividend, len_divisor, newInput, quotient, remainder, done, numAdd, numSub); 4 | 5 | input [31:0] dividend, divisor; 6 | input signed [6:0] len_dividend, len_divisor; 7 | input clk, newInput; 8 | 9 | output reg [31:0] quotient = 0; 10 | output reg signed [32:0] remainder; 11 | output reg done = 1; 12 | output reg [5:0] numAdd = 0, numSub = 0; 13 | 14 | reg isFirstCycle = 1; 15 | 16 | reg [31:0] aligned_divisor; 17 | 18 | reg [5:0] iteration = 0; 19 | 20 | always @(posedge newInput) begin 21 | quotient <= 32'b0; 22 | remainder <= dividend; 23 | iteration <= 0; 24 | done <= 0; 25 | numAdd <= 0; 26 | numSub <= 0; 27 | isFirstCycle <= 1; 28 | end 29 | 30 | always @(posedge clk) begin 31 | if (len_dividend - len_divisor < 0) begin 32 | done <= 1; 33 | end 34 | else if (isFirstCycle == 1) begin 35 | aligned_divisor <= divisor << (len_dividend - len_divisor); 36 | isFirstCycle <= 0; 37 | end 38 | else begin 39 | 40 | if (remainder < 0) begin 41 | remainder <= remainder + aligned_divisor; 42 | numAdd <= numAdd + 1; 43 | quotient <= quotient ^ 1; 44 | end 45 | else begin 46 | remainder <= remainder - aligned_divisor; 47 | numSub <= numSub + 1; 48 | end 49 | #1 50 | quotient <= (quotient << 1) | 1; 51 | aligned_divisor <= aligned_divisor >> 1; 52 | iteration <= iteration + 1; 53 | #1 54 | if (iteration == len_dividend - len_divisor + 1) begin 55 | if (remainder < 0) begin 56 | remainder <= remainder + divisor; 57 | numAdd <= numAdd + 1; 58 | quotient <= quotient - 1; 59 | end 60 | #1 61 | done <= 1; 62 | end 63 | end 64 | end 65 | 66 | endmodule -------------------------------------------------------------------------------- /Assignment 3/Q1-DRAM-Bank-Read/A3Q1_read.v: -------------------------------------------------------------------------------- 1 | `define TICK #1 2 | 3 | module read(clk,row_number,input_valid,op,output_valid); 4 | 5 | input clk,input_valid; 6 | input [3:0] row_number; //15 rows,thus we require 4 bits 7 | output output_valid; 8 | output [31:0] op; 9 | reg [31:0] op; 10 | reg output_valid; 11 | reg [31:0] r[0:15]; 12 | reg [3:0] open_row_number=4'bz; 13 | reg [1:0] cycle=2'd0; 14 | reg is_open=1'b0; 15 | 16 | initial begin 17 | r[0]=32'd0; 18 | r[1]=32'd1; 19 | r[2]=32'd2; 20 | r[3]=32'd3; 21 | r[4]=32'd4; 22 | r[5]=32'd5; 23 | r[6]=32'd6; 24 | r[7]=32'd7; 25 | r[8]=32'd8; 26 | r[9]=32'd9; 27 | r[10]=32'd10; 28 | r[11]=32'd11; 29 | r[12]=32'd12; 30 | r[13]=32'd13; 31 | r[14]=32'd14; 32 | r[15]=32'd15; 33 | end 34 | 35 | always @(posedge clk) begin 36 | if(input_valid==1) begin 37 | if(is_open==1'b0) begin 38 | //one cycle later 39 | cycle<= `TICK 2'd1; 40 | output_valid<= `TICK 0; 41 | open_row_number<= `TICK row_number; 42 | is_open<=`TICK 1'b1; 43 | end 44 | else begin 45 | if(row_number==open_row_number) begin 46 | //same cycle 47 | cycle<= `TICK 2'd0; 48 | output_valid<= `TICK 1; 49 | // output_valid<= #1 0; 50 | end 51 | else begin 52 | //two cycles later 53 | cycle<= `TICK 2'd2; 54 | output_valid<= `TICK 0; 55 | open_row_number<= `TICK row_number; 56 | end 57 | end 58 | end 59 | if(cycle==1) begin 60 | cycle<= `TICK cycle-1; 61 | op<= `TICK r[row_number]; 62 | output_valid<= `TICK 1; 63 | output_valid<= `TICK 0; 64 | end 65 | else if(cycle==2) begin 66 | cycle<= `TICK cycle-1; 67 | output_valid<= `TICK 0; 68 | end 69 | end 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /Assignment 4/Q2-Grid-Walk/A4Q2_top.v: -------------------------------------------------------------------------------- 1 | `include "./A4Q2_grid_walk.v" 2 | 3 | module top; 4 | reg [1:0] steps, direction; 5 | reg clk; 6 | wire [4:0] x; 7 | wire [4:0] y; 8 | grid_walk GRID_WALK(steps, direction, clk, x, y); 9 | initial begin 10 | forever begin 11 | clk = 0; 12 | #5 13 | clk = 1; 14 | #5 15 | clk = 0; 16 | end 17 | end 18 | initial begin 19 | #100 20 | $finish; 21 | end 22 | initial begin 23 | // EAST = 0, NORTH = 1, WEST = 2, SOUTH = 3 24 | #3 25 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 26 | steps = 2; direction = 0; 27 | #10 28 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 29 | steps = 3; direction = 1; 30 | #10 31 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 32 | steps = 2; direction = 0; 33 | #10 34 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 35 | steps = 3; direction = 1; 36 | #10 37 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 38 | steps = 3; direction = 1; 39 | #10 40 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 41 | steps = 1; direction = 2; 42 | #10 43 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 44 | steps = 3; direction = 3; 45 | #10 46 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 47 | steps = 1; direction = 3; 48 | #10 49 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 50 | steps = 1; direction = 0; 51 | #10 52 | $display("Time= %2d , Previous Input: Steps = %d, Direction = %d | Currently At: (%d, %d)", $time,steps, direction, x, y); 53 | end 54 | endmodule -------------------------------------------------------------------------------- /Assignment 2/README.md: -------------------------------------------------------------------------------- 1 | # Assignment 2 2 | 3 | [30 points] 1. Implement a module for a 3-to-8 decoder. Implement another module for an 8-to-3 encoder. Implement a top module that instantiates a 3-to-8 decoder and an 8-to-3 encoder and connects them as follows. The decoder takes a three-bit input and feeds its outputs to the inputs of the encoder. It displays the decoder inputs and encoder outputs. Note that the displayed decoder inputs and encoder outputs must be identical. The top module must have all eight test cases. 4 | 5 | [35 points] 2. Implement an 8-to-3 priority encoder where priority is given to the least significant input position with a 1. For example, if the input is 10010000, the output would be 100 encoding the position of the least significant 1 in the input (leftmost bit is the most significant bit). Write a top module to test your encoder. You must have at least ten test cases separated by one time unit delay. 6 | 7 | [15 points] 3. Implement a module M with a single-bit output and clock input. The output toggles (i.e., changes from 0 to 1 or 1 to 0) every 25 thousand cycles. Initialize the output to 0 in the module. Write a top module that instantiates M and generates a clock signal of period ten time units and 50% duty cycle. Also, display the output of the module M whenever it changes. Do simulation for 310 thousand cycles. 8 | 9 | [20 points] 4. Implement a module M with a four-bit output and clock input. The output rotates to the left by one bit position every 25 thousand cycles. Initialize the output to 1000. So, the outputs in subsequent 25 thousand cycles intervals would be 0001, 0010, 0100, 1000, 0001, ... Write a top module that instantiates M and generates a clock signal of period ten time units and 50% duty cycle. Also, display the output of the module M whenever it changes. Do simulation for 310 thousand cycles. 10 | 11 | Submission: Submit your verilog files named clearly. For example, you could name the files as follows: 12 | 13 | A2Q1_decoder3to8.v, A2Q1_encoder8to3.v, A2Q1_top.v 14 | A2Q2_priority_encoder3to8.v, A2Q2_top.v 15 | A2Q3_blink.v, A2Q3_top.v 16 | A2Q4_rotate.v, A2Q4_top.v 17 | 18 | Email the files as attachment to cs220spring2021submit@gmail.com. The subject line of the email MUST be the following (replace N by your group number): Assignment#2 submission for Group#N 19 | -------------------------------------------------------------------------------- /Assignment 1/README.md: -------------------------------------------------------------------------------- 1 | # Assignment 1 2 | 3 | [40 points] 1. Implement an eight-bit ripple carry adder using eight one-bit full adders. Organize the design as follows. Write a module for one-bit full adder. Write another module for eight-bit ripple carry adder that instantiates eight one-bit full adders and connects them properly to build an eight-bit ripple carry adder. Write a top module to test the eight-bit adder. Make sure to display your inputs, sum, and carry out. Your top module must have ten different inputs. Put one time unit delay between consecutive inputs. Place one module in one verilog file i.e., you will have three verilog files. As a hint, the module skeletons are given below. 4 | 5 | ``` 6 | module one_bit_full_adder (a, b, cin, sum, cout); 7 | 8 | input a; 9 | input b; 10 | input cin; 11 | 12 | output sum; 13 | wire sum; 14 | output cout; 15 | wire cout; 16 | 17 | ... 18 | 19 | endmodule 20 | ``` 21 | 22 | ``` 23 | module eight_bit_adder (x, y, carry_in, sum, carry_out); 24 | 25 | input [7:0] x; 26 | input [7:0] y; 27 | input carry_in; 28 | 29 | output [7:0] sum; 30 | wire [7:0] sum; 31 | output carry_out; 32 | wire carry_out; 33 | 34 | wire [6:0] intermediate_carry; 35 | 36 | one_bit_full_adder FA0 (x[0], y[0], carry_in, sum[0], intermediate_carry[0]); 37 | one_bit_full_adder FA1 (...); 38 | 39 | ... 40 | 41 | endmodule 42 | ``` 43 | 44 | ``` 45 | module eight_bit_adder_top; 46 | 47 | reg [7:0] A; 48 | reg [7:0] B; 49 | reg Cin; 50 | 51 | wire [7:0] Sum; 52 | wire Carry; 53 | 54 | eight_bit_adder ADDER (A, B, Cin, Sum, Carry); 55 | 56 | always @ (A or B or Cin) 57 | ... 58 | 59 | endmodule 60 | ``` 61 | 62 | [60 points] 2. Implement an eight-bit comparator using eight one-bit comparators. Just like the previous question, organize your design into three different modules. The top module should have ten test cases. For each test case, display the inputs and the three outputs (less, equal, greater). Choose your test cases to cover all three outputs. In this case also, you will have three verilog files. 63 | 64 | Submission: Submit your verilog files (three files for each question) named clearly. For example, you could name the files as follows: A1Q1_one_bit_full_adder.v, A1Q1_eight_bit_adder.v, A1Q1_eight_bit_adder_top.v, A1Q2_one_bit_comparator.v, A1Q2_eight_bit_comparator.v, A1Q2_eight_bit_comparator_top.v. Email the files as attachment to cs220spring2021submit@gmail.com. The subject line of the email MUST be the following (replace N by your group number): Assignment#1 submission for Group#N 65 | -------------------------------------------------------------------------------- /Assignment 7/Q1-Instruction-Memory/A7Q1_main.v: -------------------------------------------------------------------------------- 1 | module main(clk, pc, r, i, j, three, four, five, six); 2 | 3 | input clk; 4 | output reg [2:0] pc = 3'b0; 5 | output reg [2:0] r = 3'b0; 6 | output reg [2:0] i = 3'b0; 7 | output reg [2:0] j = 3'b0; 8 | output reg [2:0] three = 3'b0; 9 | output reg [2:0] four = 3'b0; 10 | output reg [2:0] five = 3'b0; 11 | output reg [2:0] six = 3'b0; 12 | 13 | reg [31:0] registers[0:7]; 14 | 15 | wire [31:0] curr_inst; 16 | wire [5:0] curr_opcode; 17 | wire [4:0] curr_rd; 18 | wire [4:0] curr_rt; 19 | 20 | assign curr_inst = registers[pc]; 21 | assign curr_opcode = curr_inst[31:26]; 22 | assign curr_rd = curr_inst[15:11]; 23 | assign curr_rt = curr_inst[20:16]; 24 | 25 | initial begin 26 | registers[0]=32'b00100000000001000011010001010110; 27 | registers[1]=32'b00100000000001011111111111111111; 28 | registers[2]=32'b00000000101001000011000000010100; 29 | registers[3]=32'b00100000000000110000000000000111; 30 | registers[4]=32'b00000000110000110011000000000100; 31 | registers[5]=32'b00000000000000110001100001000010; 32 | registers[6]=32'b01011100100001011001101010111100; 33 | registers[7]=32'b00001000000100100011010001010110; 34 | end 35 | 36 | always @(posedge clk) begin 37 | 38 | if (curr_opcode == 0) begin 39 | // R 40 | r <= #1 r + 1; 41 | if (curr_rd == 3) begin 42 | three <= #1 three + 1; 43 | end 44 | else if (curr_rd == 4) begin 45 | four <= four + 1; 46 | end 47 | else if (curr_rd == 5) begin 48 | five <= five + 1; 49 | end 50 | else if (curr_rd == 6) begin 51 | six <= six + 1; 52 | end 53 | end 54 | else if (curr_opcode == 2 | curr_opcode == 3) begin 55 | // J 56 | j <= #1 j + 1; 57 | end 58 | else begin 59 | // I 60 | i<= #1 i + 1; 61 | if (curr_rt == 3) begin 62 | three <= #1 three + 1; 63 | end 64 | else if (curr_rt == 4) begin 65 | four <= four + 1; 66 | end 67 | else if (curr_rt == 5) begin 68 | five <= five + 1; 69 | end 70 | else if (curr_rt == 6) begin 71 | six <= six + 1; 72 | end 73 | end 74 | 75 | // $display("%b %b\n", curr_inst, curr_opcode); 76 | 77 | pc <= #1 pc + 1; 78 | end 79 | 80 | endmodule -------------------------------------------------------------------------------- /Assignment 11/Q1-Booths-Algorithm/A11Q1_top.v: -------------------------------------------------------------------------------- 1 | `include "./A11Q1_booth.v" 2 | 3 | module top; 4 | 5 | reg signed [31:0] multiplicand, multiplier; 6 | reg clk, newInput; 7 | 8 | wire signed [63:0] product; 9 | wire done; 10 | wire [4:0]numAdd, numSub; 11 | 12 | reg [3:0] test_case_num = 0; 13 | reg start; 14 | 15 | booth BOOTH(multiplicand, multiplier, clk, newInput, product, done, numAdd, numSub); 16 | 17 | always @(negedge clk or posedge start) begin 18 | if (done == 1) begin 19 | if (multiplier == 0 || multiplier == -1) begin 20 | newInput = 0; 21 | end 22 | if (test_case_num > 0) begin 23 | $display("%d, %d, %d, %d, %d", multiplicand, multiplier, product, numAdd, numSub); 24 | end 25 | 26 | if (test_case_num == 0) begin 27 | multiplicand = 2020; multiplier = -1; newInput = 1; 28 | end 29 | else if (test_case_num == 1) begin 30 | multiplicand = 9; multiplier = 2; newInput = 1; 31 | end 32 | else if (test_case_num == 2) begin 33 | multiplicand =10 ; multiplier = 1; newInput = 1; 34 | end 35 | else if (test_case_num == 3) begin 36 | multiplicand = -10; multiplier = 4; newInput = 1; 37 | end 38 | else if (test_case_num == 4) begin 39 | multiplicand = -50; multiplier = -5; newInput = 1; 40 | end 41 | else if (test_case_num == 5) begin 42 | multiplicand = 10; multiplier = 0; newInput = 1; 43 | end 44 | else if (test_case_num == 6) begin 45 | multiplicand = 100; multiplier = 100; newInput = 1; 46 | end 47 | else if (test_case_num == 7) begin 48 | multiplicand = 1000; multiplier = -1000; newInput = 1; 49 | end 50 | else if (test_case_num == 8) begin 51 | multiplicand = 99; multiplier = 1431655765; newInput = 1; 52 | end 53 | else if (test_case_num == 9) begin 54 | multiplicand = 1; multiplier = -1431655766; newInput = 1; 55 | end 56 | else begin 57 | $display("Program completed."); 58 | $finish; 59 | end 60 | 61 | test_case_num <= test_case_num + 1; 62 | end 63 | else begin 64 | newInput = 0; 65 | end 66 | end 67 | 68 | initial begin 69 | $display("multiplicand, multiplier, product, numAdd, numSub"); 70 | start=1; 71 | #1 72 | start=0; 73 | end 74 | 75 | initial begin 76 | forever begin 77 | clk <= 1; 78 | #5 79 | clk <= 0; 80 | #5 81 | clk <= 1; 82 | end 83 | end 84 | 85 | endmodule -------------------------------------------------------------------------------- /Assignment 3/README.md: -------------------------------------------------------------------------------- 1 | [40 points] 1. Model a small DRAM bank having 16 rows each 32 bits wide using the Verilog 2D array. Initialize the 16 rows as follows: r[0] = 0, r[1] = 1, ..., r[15] = 15. Write a module to read a row from the bank. The input to the module is the clock, a row number, and an input_valid bit. On a positive edge of a clock the module does its work as follows. If the input_valid is 1, it takes in the input row number and starts processing it. If the input row number does not match with the open row number, the contents of the requested row are output two cycles later. If there is no open row, the contents of the requested row appear in the next cycle. If the current input row matches the open row, the output appears in the same cycle. Initially, no row is open. Another output of the read module is an output_valid bit. Whenever the module produces a new output, it sets this bit to 1 for the environment to know that the output corresponding to the last input is available. When the module takes in a new input, it resets the output_valid to 0 if it cannot produce an output in the same cycle. Write a top module to test your read module. The top module generates a clock with period equal to ten time units and 50% duty cycle. Give a new row number two time units before every third rising clock edge. For example, if the rising clock edges come at times 5, 15, 25, etc., the new inputs should be given at times 3, 33, 63, etc.. Remember to set the input_valid input to 1 when you send a new row number; otherwise the input_valid input should be set to 0 by the top module two time units before a rising clock edge. Display the row number and the corresponding contents whenever a new output is produced (indicated by output_valid equal to 1). Simulate for 30 clock cycles. 2 | 3 | [60 points] 2. Write a module to implement a finite state machine that checks if the input sequence is alternating. The module takes one bit input and the clock signal. It outputs 0 if the input sequence seen so far is not alternating; otherwise it outputs 1. Write a top module to test your FSM. The top module generates a clock with period equal to ten time units and 50% duty cycle. Give a new input bit two time units before every rising clock edge. Display the output along with the time. Simulate for ten clock cycles. 4 | 5 | Submission: Submit your verilog files (two files for each question) named clearly. For example, you could name the files as follows: A3Q1_read.v, A3Q1_read_top.v, A3Q2_fsm.v, A3Q2_fsm_top.v. Email the files as attachment to cs220spring2021submit@gmail.com. The subject line of the email MUST be the following (replace N by your group number): Assignment#3 submission for Group#N -------------------------------------------------------------------------------- /Assignment 11/Q2-Non-Restoring-Division/A11Q2_top.v: -------------------------------------------------------------------------------- 1 | `include "./A11Q2_nrd.v" 2 | 3 | module top; 4 | 5 | reg [31:0] dividend, divisor; 6 | reg signed [6:0] len_dividend, len_divisor; 7 | reg clk, newInput; 8 | 9 | wire [31:0] quotient; 10 | wire signed [32:0] remainder; 11 | 12 | wire done; 13 | wire [5:0]numAdd, numSub; 14 | 15 | reg [3:0] test_case_num = 0; 16 | reg start; 17 | 18 | nrd NRD(dividend, divisor, clk, len_dividend, len_divisor, newInput, quotient, remainder, done, numAdd, numSub); 19 | 20 | always @(negedge clk or posedge start) begin 21 | if (done == 1) begin 22 | if (len_dividend - len_divisor < 0 ) begin 23 | newInput = 0; 24 | end 25 | if (test_case_num > 0) begin 26 | $display("%d, %d, %d, %d, %d, %d", dividend, divisor, quotient, remainder, numAdd, numSub); 27 | end 28 | if (test_case_num == 0) begin 29 | dividend = 2020; divisor = 20; len_dividend = 11; len_divisor = 5; newInput = 1; 30 | end 31 | else if (test_case_num == 1) begin 32 | dividend = 9; divisor = 2; len_dividend = 4; len_divisor = 2; newInput = 1; 33 | end 34 | else if (test_case_num == 2) begin 35 | dividend =10 ; divisor = 1; len_dividend = 4; len_divisor = 1; newInput = 1; 36 | end 37 | else if (test_case_num == 3) begin 38 | dividend =10; divisor = 4; len_dividend = 4; len_divisor = 3; newInput = 1; 39 | end 40 | else if (test_case_num == 4) begin 41 | dividend = 50; divisor = 5; len_dividend = 6; len_divisor = 3; newInput = 1; 42 | end 43 | else if (test_case_num == 5) begin 44 | dividend = 10; divisor = 100; len_dividend = 4; len_divisor = 7; newInput = 1; 45 | end 46 | else if (test_case_num == 6) begin 47 | dividend = 74; divisor = 9; len_dividend = 7; len_divisor = 4; newInput = 1; 48 | end 49 | else if (test_case_num == 7) begin 50 | dividend = 1000; divisor = 1000; len_dividend = 10; len_divisor = 10; newInput = 1; 51 | end 52 | else if (test_case_num == 8) begin 53 | dividend = 4294967295; divisor = 1; len_dividend = 32; len_divisor = 1;newInput = 1; 54 | end 55 | else if (test_case_num == 9) begin 56 | dividend = 2; divisor = 4294967295; len_dividend = 1; len_divisor = 32;newInput = 1; 57 | end 58 | else begin 59 | $display("Program completed."); 60 | $finish; 61 | end 62 | 63 | test_case_num <= test_case_num + 1; 64 | end 65 | else begin 66 | newInput = 0; 67 | end 68 | end 69 | 70 | initial begin 71 | $display("dividend, divisor, quotient, remainder, numAdd, numSub"); 72 | start=1; 73 | #1 74 | start=0; 75 | end 76 | 77 | initial begin 78 | forever begin 79 | clk <= 1; 80 | #5 81 | clk <= 0; 82 | #5 83 | clk <= 1; 84 | end 85 | end 86 | 87 | endmodule -------------------------------------------------------------------------------- /Assignment 10/Q1-Binary-Search/A10Q1.s: -------------------------------------------------------------------------------- 1 | .data 2 | array: .space 48 3 | msg_entern: .asciiz "Enter n: " 4 | msg_number: .asciiz "\nInput number: " 5 | msg_search: .asciiz "\nEnter number to search: " 6 | msg_found: .asciiz "\nFound element at index " 7 | msg_notfound: .asciiz "\nElement was not found" 8 | 9 | .text 10 | .globl main 11 | main: li $v0,4 12 | la $a0,msg_entern 13 | syscall 14 | li $v0,5 15 | syscall 16 | add $s0,$v0,$0 17 | add $t0,$s0,$0 18 | la $s1,array 19 | add $t1,$s1,$0 20 | 21 | loop: li $v0,4 22 | la $a0,msg_number 23 | syscall 24 | li $v0,5 25 | syscall 26 | sw $v0,0($t1) 27 | bne $t0,$s0,continue 28 | addi $t7,$v0,0 29 | 30 | continue: addi $t1,$t1,4 31 | addi $t0,$t0,-1 32 | bne $t0,$0,loop 33 | li $v0,4 34 | la $a0,msg_search 35 | syscall 36 | li $v0,5 37 | syscall 38 | add $s2,$v0,$0 39 | add $a0,$s1,$0 40 | add $a1,$0,$0 41 | addi $a2,$s0,0 42 | addi $a3,$s2,0 43 | slt $t7,$a3,$t7 44 | beq $t7,1,notfound 45 | addi $sp,$sp,-4 46 | sw $ra,0($sp) 47 | jal binarysearch 48 | lw $ra,0($sp) 49 | addi $sp,$sp,4 50 | add $a3,$v0,$0 51 | bne $a3,-1,found 52 | 53 | notfound: addi $v0,$0,4 54 | la $a0,msg_notfound 55 | syscall 56 | j jump 57 | 58 | found: addi $v0,$0,4 59 | la $a0,msg_found 60 | syscall 61 | addi $a0,$a3,0 62 | addi $v0,$0,1 63 | syscall 64 | 65 | jump: jr $ra 66 | 67 | binarysearch: sltu $t0,$a2,$a1 68 | beq $t0,$0,dontreturn 69 | addi $v0,$0,-1 70 | jr $ra 71 | 72 | dontreturn: add $t0,$a1,$a2 73 | srl $t0,$t0,1 74 | sll $t1,$t0,2 75 | add $t1,$a0,$t1 76 | lw $t1,0($t1) 77 | bne $t1,$a3,not_equal 78 | add $v0,$t0,$0 79 | jr $ra 80 | 81 | not_equal: sltu $t1,$a3,$t1 82 | beq $t1,$0,right 83 | addi $sp,$sp,-4 84 | sw $ra,0($sp) 85 | addi $a2,$t0,-1 86 | jal binarysearch 87 | lw $ra,0($sp) 88 | addi $sp,$sp,4 89 | addi $v0,$v0,0 90 | jr $ra 91 | 92 | right: addi $sp,$sp,-4 93 | sw $ra,0($sp) 94 | addi $a1,$t0,1 95 | jal binarysearch 96 | lw $ra,0($sp) 97 | addi $sp,$sp,4 98 | addi $v0,$v0,0 99 | jr $ra -------------------------------------------------------------------------------- /Assignment 7/Q2-Instruction-Memory/A7Q2_main.v: -------------------------------------------------------------------------------- 1 | `define MAX_PC 7 2 | `define OUTPUT_REG 5 3 | `include "./A7Q2_eightbit_addersub.v" 4 | 5 | module main(clk, done, out); 6 | 7 | input clk; 8 | reg [31:0] instructions[0:6]; 9 | reg [2:0] state = 0; 10 | reg [2:0] pc = 0; 11 | 12 | 13 | reg [31:0] curr_inst; 14 | reg [5:0] curr_opcode; 15 | reg [4:0] curr_rd; 16 | reg [4:0] curr_rs; 17 | reg [4:0] curr_rt; 18 | reg [4:0] curr_shft; 19 | reg [15:0] curr_imd; 20 | reg [5:0] curr_func; 21 | 22 | reg [7:0] readVal1; 23 | reg [7:0] readVal2; 24 | 25 | reg invalid = 0; // invalid = 0 means it is valid. 26 | 27 | reg signed [7:0] registers[0:31]; 28 | 29 | reg [7:0] a, b; 30 | reg opcode; 31 | wire [7:0] sum; 32 | wire cout; 33 | output reg done = 0; 34 | output reg [7:0] out; 35 | 36 | eightbit EIGHTBIT(a,b,opcode,sum,cout); 37 | 38 | initial begin 39 | instructions[0] =32'b00100100000000010000000000101101; 40 | instructions[1] =32'b00100100000000101111111111101100; 41 | instructions[2] =32'b00100100000000111111111111000100; 42 | instructions[3] =32'b00100100000001000000000000011110; 43 | instructions[4] =32'b00000000001000100010100000100001; 44 | instructions[5] =32'b00000000011001000011000000100001; 45 | instructions[6] =32'b00000000101001100010100000100011; 46 | end 47 | 48 | initial begin 49 | registers[0]=8'b0; 50 | registers[1]=8'b0; 51 | registers[2]=8'b0; 52 | registers[3]=8'b0; 53 | registers[4]=8'b0; 54 | registers[5]=8'b0; 55 | registers[6]=8'b0; 56 | registers[7]=8'b0; 57 | registers[8]=8'b0; 58 | registers[9]=8'b0; 59 | registers[10]=8'b0; 60 | registers[11]=8'b0; 61 | registers[12]=8'b0; 62 | registers[13]=8'b0; 63 | registers[14]=8'b0; 64 | registers[15]=8'b0; 65 | registers[16]=8'b0; 66 | registers[17]=8'b0; 67 | registers[18]=8'b0; 68 | registers[19]=8'b0; 69 | registers[20]=8'b0; 70 | registers[21]=8'b0; 71 | registers[22]=8'b0; 72 | registers[23]=8'b0; 73 | registers[24]=8'b0; 74 | registers[25]=8'b0; 75 | registers[26]=8'b0; 76 | registers[27]=8'b0; 77 | registers[28]=8'b0; 78 | registers[29]=8'b0; 79 | registers[30]=8'b0; 80 | registers[31]=8'b0; 81 | end 82 | 83 | always @(posedge clk) begin 84 | if (state == 0) begin 85 | curr_inst <= instructions[pc]; 86 | pc <= pc + 1; 87 | state <= 1; 88 | end 89 | else if (state == 1) begin 90 | curr_opcode <= curr_inst[31:26]; 91 | #1 92 | if (curr_opcode == 0) begin 93 | // R 94 | curr_rs <= curr_inst[25:21]; 95 | curr_rt <= curr_inst[20:16]; 96 | curr_rd <= curr_inst[15:11]; 97 | curr_shft <= curr_inst[10:6]; 98 | curr_func <= curr_inst[5:0]; 99 | 100 | end 101 | else if (curr_opcode != 2 | curr_opcode != 3) begin 102 | // I 103 | curr_rs <= curr_inst[25:21]; 104 | curr_rt <= curr_inst[20:16]; 105 | curr_imd <= curr_inst[15:0]; 106 | end 107 | state <= 2; 108 | end 109 | else if (state == 2) begin 110 | if (curr_opcode == 0) begin 111 | // R 112 | readVal1 <= registers[curr_rs]; 113 | readVal2 <= registers[curr_rt]; 114 | end 115 | else if (curr_opcode != 2 & curr_opcode != 3) begin 116 | // I 117 | readVal1 <= registers[curr_rs]; 118 | end 119 | state <= 3; 120 | end 121 | else if (state == 3) begin 122 | if(curr_opcode == 9) begin 123 | a <= readVal1; 124 | b <= curr_imd[7:0]; 125 | opcode <= 0; 126 | end 127 | else if (curr_opcode == 0 && curr_func == 33) begin 128 | a <= readVal1; 129 | b <= readVal2; 130 | opcode <= 0; 131 | end 132 | else if (curr_opcode == 0 && curr_func == 35) begin 133 | a <= readVal1; 134 | b <= readVal2; 135 | opcode <= 1; 136 | end 137 | else begin 138 | invalid <= 1; 139 | end 140 | state <= 4; 141 | end 142 | else if (state == 4) begin 143 | if(invalid == 0) begin 144 | if (curr_opcode == 0 & curr_rd != 0) begin 145 | // R 146 | registers[curr_rd] <= sum; 147 | end 148 | else if ((curr_opcode != 2 & curr_opcode != 3) & curr_rt != 0) begin 149 | // I 150 | registers[curr_rt] <= sum; 151 | end 152 | end 153 | if(pc < `MAX_PC) begin 154 | state <= 0; 155 | end 156 | else begin 157 | state <= 5; 158 | end 159 | end 160 | else if (state == 5) begin 161 | out <= registers[`OUTPUT_REG]; 162 | done <= #1 1; 163 | end 164 | end 165 | 166 | endmodule -------------------------------------------------------------------------------- /Assignment 6/Q1-Miniature-Processor/A6Q1_call.v: -------------------------------------------------------------------------------- 1 | module call(read1, read2, write, data, cmd, clk, done); 2 | 3 | input [4:0] read1,read2,write; 4 | input signed [15:0] data; 5 | input [2:0] cmd; 6 | input clk; 7 | 8 | output reg done; 9 | 10 | reg [4:0] cycles = 5'b0; 11 | reg signed [15:0] temp; 12 | 13 | reg signed [15:0] readval1,readval2; 14 | reg signed [15:0] registers[0:31]; 15 | 16 | initial begin 17 | registers[0]=16'b0; 18 | registers[1]=16'b0; 19 | registers[2]=16'b0; 20 | registers[3]=16'b0; 21 | registers[4]=16'b0; 22 | registers[5]=16'b0; 23 | registers[6]=16'b0; 24 | registers[7]=16'b0; 25 | registers[8]=16'b0; 26 | registers[9]=16'b0; 27 | registers[10]=16'b0; 28 | registers[11]=16'b0; 29 | registers[12]=16'b0; 30 | registers[13]=16'b0; 31 | registers[14]=16'b0; 32 | registers[15]=16'b0; 33 | registers[16]=16'b0; 34 | registers[17]=16'b0; 35 | registers[18]=16'b0; 36 | registers[19]=16'b0; 37 | registers[20]=16'b0; 38 | registers[21]=16'b0; 39 | registers[22]=16'b0; 40 | registers[23]=16'b0; 41 | registers[24]=16'b0; 42 | registers[25]=16'b0; 43 | registers[26]=16'b0; 44 | registers[27]=16'b0; 45 | registers[28]=16'b0; 46 | registers[29]=16'b0; 47 | registers[30]=16'b0; 48 | registers[31]=16'b0; 49 | end 50 | 51 | always @(posedge clk) begin 52 | 53 | if(cmd==0) begin 54 | if (cycles == 2) begin 55 | registers[write]<=data; 56 | cycles <= 0; 57 | #1 58 | done <= 1'b1; 59 | done <= #1 1'b0; 60 | end 61 | cycles <= cycles + 1; 62 | end 63 | 64 | else if(cmd==1) begin 65 | if (cycles == 2) begin 66 | readval1<=registers[read1]; 67 | cycles <= 0; 68 | #1 69 | $display("Read Address: %d | Read Value: %d\n", read1, readval1); 70 | done <= 1'b1; 71 | done <= #1 1'b0; 72 | end 73 | cycles <= cycles + 1; 74 | end 75 | 76 | else if(cmd==2) begin 77 | if (cycles == 2) begin 78 | 79 | readval1<=registers[read1]; 80 | readval2<=registers[read2]; 81 | cycles <= 0; 82 | #1 83 | $display("Read Address 1 = %d | Read Value 1 = %d\n" ,read1, readval1); 84 | $display("Read Address 2 = %d | Read Value 2 = %d\n" ,read2, readval2); 85 | 86 | done <= 1'b1; 87 | done <= #1 1'b0; 88 | 89 | end 90 | cycles <= cycles + 1; 91 | end 92 | 93 | else if(cmd==3) begin 94 | if (cycles == 2) begin 95 | readval1<=registers[read1]; 96 | registers[write]<=data; 97 | cycles <= 0; 98 | #1 99 | $display("Read Address = %d | Read Value = %d\n" , read1, readval1); 100 | done <= 1'b1; 101 | done <= #1 1'b0; 102 | end 103 | cycles <= cycles + 1; 104 | end 105 | 106 | else if(cmd==4) begin 107 | if (cycles == 2) begin 108 | readval1<=registers[read1]; 109 | readval2<=registers[read2]; 110 | registers[write]<=data; 111 | cycles <= 0; 112 | #1 113 | $display("Read Address 1 = %d | Read Value 1 = %d\n" ,read1, readval1); 114 | $display("Read Address 2 = %d | Read Value 2 = %d\n" ,read2, readval2); 115 | done <= 1'b1; 116 | done <= #1 1'b0; 117 | end 118 | cycles <= cycles + 1; 119 | end 120 | 121 | else if(cmd == 5) begin 122 | if (cycles == 2) begin 123 | readval1<=registers[read1]; 124 | readval2<=registers[read2]; 125 | end 126 | else if (cycles == 18) begin 127 | temp<=readval1+readval2; 128 | end 129 | else if (cycles == 20) begin 130 | registers[write]<=temp; 131 | cycles <= 0; 132 | #1 133 | $display("Write Address = %d | Written Value = %d\n", write, temp); 134 | done <= 1'b1; 135 | done <= #1 1'b0; 136 | end 137 | cycles<=cycles+1; 138 | end 139 | 140 | else if(cmd == 6) begin 141 | if (cycles == 2) begin 142 | readval1<=registers[read1]; 143 | readval2<=registers[read2]; 144 | end 145 | else if (cycles == 18) begin 146 | temp<=readval1-readval2; 147 | end 148 | else if (cycles == 20) begin 149 | registers[write]<=temp; 150 | cycles <= 0; 151 | #1 152 | $display("Write Address = %d | Written Value = %d\n", write, temp); 153 | done <= 1'b1; 154 | done <= #1 1'b0; 155 | end 156 | cycles<=cycles+1; 157 | end 158 | 159 | else if(cmd == 7) begin 160 | if (cycles == 2) begin 161 | readval1<=registers[read1]; 162 | end 163 | else if (cycles == 18) begin 164 | temp<=(readval1<