├── README.md ├── ip_rope ├── FDMA_v2 │ ├── component.xml │ ├── src │ │ └── fdma_v2.v │ └── xgui │ │ └── fdma_v2_v1_0.tcl ├── R0_FIFO │ ├── R0_FIFO.dcp │ ├── R0_FIFO.veo │ ├── R0_FIFO.vho │ ├── R0_FIFO.xci │ ├── R0_FIFO.xdc │ ├── R0_FIFO.xml │ ├── R0_FIFO_clocks.xdc │ ├── R0_FIFO_ooc.xdc │ ├── R0_FIFO_sim_netlist.v │ ├── R0_FIFO_sim_netlist.vhdl │ ├── R0_FIFO_stub.v │ ├── R0_FIFO_stub.vhdl │ ├── doc │ │ └── fifo_generator_v13_2_changelog.txt │ ├── hdl │ │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ ├── fifo_generator_v13_2_rfs.v │ │ ├── fifo_generator_v13_2_rfs.vhd │ │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ ├── sim │ │ └── R0_FIFO.v │ ├── simulation │ │ └── fifo_generator_vlog_beh.v │ └── synth │ │ └── R0_FIFO.vhd ├── VIP_Gray_Median_Filter │ ├── component.xml │ ├── src │ │ ├── CMOS_Capture_RAW_Gray.v │ │ ├── Median_Filter_3X3.v │ │ ├── Sort3.v │ │ ├── VIP_Gray_Median_Filter.v │ │ ├── VIP_Gray_Median_Filter_tb.v │ │ ├── VIP_Matrix_Generate_3x3_8Bit_v2.v │ │ ├── Video_Image_Simulate_CMOS.v │ │ └── shift_ram_3x3_8bit │ │ │ ├── shift_ram_3x3_8bit.xci │ │ │ └── shift_ram_3x3_8bit.xml │ └── xgui │ │ └── VIP_Gray_Median_Filter_v1_0.tcl ├── VIP_Gray_Median_Filter_0 │ ├── VIP_Gray_Median_Filter_0.dcp │ ├── VIP_Gray_Median_Filter_0.veo │ ├── VIP_Gray_Median_Filter_0.vho │ ├── VIP_Gray_Median_Filter_0.xci │ ├── VIP_Gray_Median_Filter_0.xml │ ├── VIP_Gray_Median_Filter_0_sim_netlist.v │ ├── VIP_Gray_Median_Filter_0_sim_netlist.vhdl │ ├── VIP_Gray_Median_Filter_0_stub.v │ ├── VIP_Gray_Median_Filter_0_stub.vhdl │ ├── sim │ │ └── VIP_Gray_Median_Filter_0.v │ ├── src │ │ ├── CMOS_Capture_RAW_Gray.v │ │ ├── Median_Filter_3X3.v │ │ ├── Sort3.v │ │ ├── VIP_Gray_Median_Filter.v │ │ ├── VIP_Gray_Median_Filter_tb.v │ │ ├── VIP_Matrix_Generate_3x3_8Bit_v2.v │ │ ├── Video_Image_Simulate_CMOS.v │ │ └── shift_ram_3x3_8bit │ │ │ ├── hdl │ │ │ ├── c_mux_bit_v12_0_vh_rfs.vhd │ │ │ ├── c_reg_fd_v12_0_vh_rfs.vhd │ │ │ ├── c_shift_ram_v12_0_vh_rfs.vhd │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ ├── shift_ram_3x3_8bit.xci │ │ │ ├── shift_ram_3x3_8bit.xml │ │ │ ├── sim │ │ │ └── shift_ram_3x3_8bit.vhd │ │ │ └── synth │ │ │ └── shift_ram_3x3_8bit.vhd │ └── synth │ │ └── VIP_Gray_Median_Filter_0.v ├── VIP_RAW8_RGB888_v2_0 │ ├── VIP_RAW8_RGB888_v2_0.dcp │ ├── VIP_RAW8_RGB888_v2_0.veo │ ├── VIP_RAW8_RGB888_v2_0.vho │ ├── VIP_RAW8_RGB888_v2_0.xci │ ├── VIP_RAW8_RGB888_v2_0.xml │ ├── VIP_RAW8_RGB888_v2_0_sim_netlist.v │ ├── VIP_RAW8_RGB888_v2_0_sim_netlist.vhdl │ ├── VIP_RAW8_RGB888_v2_0_stub.v │ ├── VIP_RAW8_RGB888_v2_0_stub.vhdl │ ├── sim │ │ └── VIP_RAW8_RGB888_v2_0.v │ ├── src │ │ ├── CMOS_Capture_RAW_Gray.v │ │ ├── VIP_Matrix_Generate_3x3_8Bit_v2.v │ │ ├── VIP_RAW8_RGB888_v2.v │ │ ├── VIP_RAW8_RGB888_v2_tb.v │ │ ├── Video_Image_Simulate_CMOS.v │ │ └── shift_ram_3x3_8bit │ │ │ ├── hdl │ │ │ ├── c_mux_bit_v12_0_vh_rfs.vhd │ │ │ ├── c_reg_fd_v12_0_vh_rfs.vhd │ │ │ ├── c_shift_ram_v12_0_vh_rfs.vhd │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ ├── shift_ram_3x3_8bit.xci │ │ │ ├── shift_ram_3x3_8bit.xml │ │ │ ├── sim │ │ │ └── shift_ram_3x3_8bit.vhd │ │ │ └── synth │ │ │ └── shift_ram_3x3_8bit.vhd │ └── synth │ │ └── VIP_RAW8_RGB888_v2_0.v ├── VIP_RGB888_YCbCr444 │ ├── component.xml │ ├── src │ │ └── VIP_RGB888_YCbCr444.v │ └── xgui │ │ └── VIP_RGB888_YCbCr444_v1_0.tcl ├── VIP_RGB888_YCbCr444_0 │ ├── VIP_RGB888_YCbCr444_0.dcp │ ├── VIP_RGB888_YCbCr444_0.veo │ ├── VIP_RGB888_YCbCr444_0.vho │ ├── VIP_RGB888_YCbCr444_0.xci │ ├── VIP_RGB888_YCbCr444_0.xml │ ├── VIP_RGB888_YCbCr444_0_sim_netlist.v │ ├── VIP_RGB888_YCbCr444_0_sim_netlist.vhdl │ ├── VIP_RGB888_YCbCr444_0_stub.v │ ├── VIP_RGB888_YCbCr444_0_stub.vhdl │ ├── sim │ │ └── VIP_RGB888_YCbCr444_0.v │ ├── src │ │ └── VIP_RGB888_YCbCr444.v │ └── synth │ │ └── VIP_RGB888_YCbCr444_0.v ├── VIP_Raw_RGB888 │ └── VIP_Raw_RGB888_v2 │ │ ├── component.xml │ │ ├── src │ │ ├── CMOS_Capture_RAW_Gray.v │ │ ├── VIP_Matrix_Generate_3x3_8Bit_v2.v │ │ ├── VIP_RAW8_RGB888_v2.v │ │ ├── VIP_RAW8_RGB888_v2_tb.v │ │ ├── Video_Image_Simulate_CMOS.v │ │ └── shift_ram_3x3_8bit │ │ │ ├── doc │ │ │ └── c_shift_ram_v12_0_changelog.txt │ │ │ ├── hdl │ │ │ ├── c_mux_bit_v12_0_vh_rfs.vhd │ │ │ ├── c_reg_fd_v12_0_vh_rfs.vhd │ │ │ ├── c_shift_ram_v12_0_vh_rfs.vhd │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ ├── shift_ram_3x3_8bit.veo │ │ │ ├── shift_ram_3x3_8bit.vho │ │ │ ├── shift_ram_3x3_8bit.xci │ │ │ ├── shift_ram_3x3_8bit.xml │ │ │ ├── sim │ │ │ └── shift_ram_3x3_8bit.vhd │ │ │ └── synth │ │ │ └── shift_ram_3x3_8bit.vhd │ │ └── xgui │ │ └── VIP_RAW8_RGB888_v2_v1_0.tcl ├── W0_FIFO │ ├── W0_FIFO.dcp │ ├── W0_FIFO.veo │ ├── W0_FIFO.vho │ ├── W0_FIFO.xci │ ├── W0_FIFO.xdc │ ├── W0_FIFO.xml │ ├── W0_FIFO_clocks.xdc │ ├── W0_FIFO_ooc.xdc │ ├── W0_FIFO_sim_netlist.v │ ├── W0_FIFO_sim_netlist.vhdl │ ├── W0_FIFO_stub.v │ ├── W0_FIFO_stub.vhdl │ ├── doc │ │ └── fifo_generator_v13_2_changelog.txt │ ├── hdl │ │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ ├── fifo_generator_v13_2_rfs.v │ │ ├── fifo_generator_v13_2_rfs.vhd │ │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ ├── sim │ │ └── W0_FIFO.v │ ├── simulation │ │ └── fifo_generator_vlog_beh.v │ └── synth │ │ └── W0_FIFO.vhd ├── fifo_xy │ ├── doc │ │ └── fifo_generator_v13_2_changelog.txt │ ├── fifo_xy.dcp │ ├── fifo_xy.veo │ ├── fifo_xy.vho │ ├── fifo_xy.xci │ ├── fifo_xy.xdc │ ├── fifo_xy.xml │ ├── fifo_xy_ooc.xdc │ ├── fifo_xy_sim_netlist.v │ ├── fifo_xy_sim_netlist.vhdl │ ├── fifo_xy_stub.v │ ├── fifo_xy_stub.vhdl │ ├── hdl │ │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ ├── fifo_generator_v13_2_rfs.v │ │ ├── fifo_generator_v13_2_rfs.vhd │ │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ ├── sim │ │ └── fifo_xy.v │ ├── simulation │ │ └── fifo_generator_vlog_beh.v │ └── synth │ │ └── fifo_xy.vhd ├── ov_camera_value │ └── camera_value_1.0 │ │ ├── bd │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── drivers │ │ └── camera_value_v1_0 │ │ │ ├── data │ │ │ ├── camera_value.mdd │ │ │ └── camera_value.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── camera_value.c │ │ │ ├── camera_value.h │ │ │ └── camera_value_selftest.c │ │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── camera_value_v1_0_tb.sv │ │ │ └── design.tcl │ │ └── debug_hw_design │ │ │ ├── camera_value_v1_0_hw_test.tcl │ │ │ └── design.tcl │ │ ├── hdl │ │ ├── camera_value_v1_0.v │ │ └── camera_value_v1_0_S00_AXI.v │ │ ├── src │ │ ├── fifo_generator_0 │ │ │ ├── doc │ │ │ │ └── fifo_generator_v13_2_changelog.txt │ │ │ ├── fifo_generator_0.dcp │ │ │ ├── fifo_generator_0.veo │ │ │ ├── fifo_generator_0.vho │ │ │ ├── fifo_generator_0.xci │ │ │ ├── fifo_generator_0.xdc │ │ │ ├── fifo_generator_0.xml │ │ │ ├── fifo_generator_0_clocks.xdc │ │ │ ├── fifo_generator_0_ooc.xdc │ │ │ ├── fifo_generator_0_sim_netlist.v │ │ │ ├── fifo_generator_0_sim_netlist.vhdl │ │ │ ├── fifo_generator_0_stub.v │ │ │ ├── fifo_generator_0_stub.vhdl │ │ │ ├── hdl │ │ │ │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ │ ├── fifo_generator_v13_2_rfs.v │ │ │ │ ├── fifo_generator_v13_2_rfs.vhd │ │ │ │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ │ │ ├── sim │ │ │ │ └── fifo_generator_0.v │ │ │ ├── simulation │ │ │ │ └── fifo_generator_vlog_beh.v │ │ │ └── synth │ │ │ │ └── fifo_generator_0.vhd │ │ └── fifo_generator_0_1 │ │ │ ├── doc │ │ │ └── fifo_generator_v13_2_changelog.txt │ │ │ ├── fifo_generator_0.veo │ │ │ ├── fifo_generator_0.vho │ │ │ ├── fifo_generator_0.xci │ │ │ ├── fifo_generator_0.xdc │ │ │ ├── fifo_generator_0.xml │ │ │ ├── fifo_generator_0_clocks.xdc │ │ │ ├── fifo_generator_0_ooc.xdc │ │ │ ├── hdl │ │ │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── fifo_generator_v13_2_rfs.v │ │ │ ├── fifo_generator_v13_2_rfs.vhd │ │ │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ │ │ ├── sim │ │ │ └── fifo_generator_0.v │ │ │ ├── simulation │ │ │ └── fifo_generator_vlog_beh.v │ │ │ └── synth │ │ │ └── fifo_generator_0.vhd │ │ └── xgui │ │ └── camera_value_v1_0.tcl ├── ov_capture_raw │ ├── component.xml │ ├── src │ │ └── capture_raw_data.v │ └── xgui │ │ └── capture_raw_data_v1_0.tcl ├── rgb2dvi_0 │ ├── rgb2dvi_0.dcp │ ├── rgb2dvi_0.veo │ ├── rgb2dvi_0.vho │ ├── rgb2dvi_0.xci │ ├── rgb2dvi_0.xml │ ├── rgb2dvi_0_sim_netlist.v │ ├── rgb2dvi_0_sim_netlist.vhdl │ ├── rgb2dvi_0_stub.v │ ├── rgb2dvi_0_stub.vhdl │ ├── sim │ │ └── rgb2dvi_0.vhd │ ├── src │ │ ├── ClockGen.vhd │ │ ├── DVI_Constants.vhd │ │ ├── OutputSERDES.vhd │ │ ├── SyncAsync.vhd │ │ ├── SyncAsyncReset.vhd │ │ ├── TMDS_Encoder.vhd │ │ ├── rgb2dvi.vhd │ │ ├── rgb2dvi.xdc │ │ ├── rgb2dvi_clocks.xdc │ │ └── rgb2dvi_ooc.xdc │ ├── synth │ │ └── rgb2dvi_0.vhd │ └── xil_defaultlib │ │ └── src │ │ ├── ClockGen.vhd │ │ ├── SyncAsync.vhd │ │ └── SyncAsyncReset.vhd ├── rgb2dvi_v1_3 │ ├── component.xml │ ├── docs │ │ └── rgb2dvi_v1_2.pdf │ ├── src │ │ ├── ClockGen.vhd │ │ ├── DVI_Constants.vhd │ │ ├── OutputSERDES.vhd │ │ ├── SyncAsync.vhd │ │ ├── SyncAsyncReset.vhd │ │ ├── TMDS_Encoder.vhd │ │ ├── rgb2dvi.vhd │ │ ├── rgb2dvi.xdc │ │ ├── rgb2dvi_clocks.xdc │ │ └── rgb2dvi_ooc.xdc │ └── xgui │ │ ├── rgb2dvi_v1_1.tcl │ │ ├── rgb2dvi_v1_2.tcl │ │ └── rgb2dvi_v1_3.tcl ├── sys_clk_ctrl │ ├── doc │ │ └── clk_wiz_v6_0_changelog.txt │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ ├── mmcm_pll_drp_func_7s_pll.vh │ ├── mmcm_pll_drp_func_us_mmcm.vh │ ├── mmcm_pll_drp_func_us_pll.vh │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ ├── mmcm_pll_drp_func_us_plus_pll.vh │ ├── sys_clk_ctrl.dcp │ ├── sys_clk_ctrl.v │ ├── sys_clk_ctrl.veo │ ├── sys_clk_ctrl.xci │ ├── sys_clk_ctrl.xdc │ ├── sys_clk_ctrl.xml │ ├── sys_clk_ctrl_board.xdc │ ├── sys_clk_ctrl_clk_wiz.v │ ├── sys_clk_ctrl_ooc.xdc │ ├── sys_clk_ctrl_sim_netlist.v │ ├── sys_clk_ctrl_sim_netlist.vhdl │ ├── sys_clk_ctrl_stub.v │ └── sys_clk_ctrl_stub.vhdl └── tmds_v1_0 │ ├── tmds.xml │ └── tmds_rtl.xml ├── make.tcl ├── src ├── CMOS_Capture_RAW_Gray.v ├── Frame_Threshold_Adj.v ├── Key_Filter.v ├── Key_Frame_Threshold.v ├── Video_Image_Processor.v ├── boundary_tracking.v ├── cmos_init.v ├── fdma_hdmi_top.v ├── i2c_bit_shift.v ├── i2c_control.v ├── lcd_driver_dualwin.v ├── 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