├── .github └── workflows │ ├── CI.yml │ └── release.yml ├── .gitignore ├── LICENSE.txt ├── Makefile ├── Readme.md ├── bin ├── .gitignore └── dep │ └── .gitignore ├── include ├── bootpin.h ├── config.h ├── crtp.h ├── loaderCommands.h ├── stm32f4xx_conf.h ├── syslink.h └── uart.h ├── lib ├── CMSIS │ ├── Include │ │ ├── arm_common_tables.h │ │ ├── arm_math.h │ │ ├── core_cm0.h │ │ ├── core_cm3.h │ │ ├── core_cm4.h │ │ ├── core_cm4_simd.h │ │ ├── core_cmFunc.h │ │ ├── core_cmInstr.h │ │ ├── core_sc000.h │ │ └── core_sc300.h │ └── STM32F4xx │ │ ├── Include │ │ ├── stm32f4xx.h │ │ └── system_stm32f4xx.h │ │ ├── Release_Notes.html │ │ └── Source │ │ ├── startup_stm32f40xx.s │ │ └── system_stm32f4xx.c ├── STM32F4xx_StdPeriph_Driver │ ├── Release_Notes.html │ ├── inc │ │ ├── stm32f4xx_adc.h │ │ ├── stm32f4xx_can.h │ │ ├── stm32f4xx_crc.h │ │ ├── stm32f4xx_cryp.h │ │ ├── stm32f4xx_dac.h │ │ ├── stm32f4xx_dbgmcu.h │ │ ├── stm32f4xx_dcmi.h │ │ ├── stm32f4xx_dma.h │ │ ├── stm32f4xx_dma2d.h │ │ ├── stm32f4xx_exti.h │ │ ├── stm32f4xx_flash.h │ │ ├── stm32f4xx_fmc.h │ │ ├── stm32f4xx_fsmc.h │ │ ├── stm32f4xx_gpio.h │ │ ├── stm32f4xx_hash.h │ │ ├── stm32f4xx_i2c.h │ │ ├── stm32f4xx_iwdg.h │ │ ├── stm32f4xx_ltdc.h │ │ ├── stm32f4xx_misc.h │ │ ├── stm32f4xx_pwr.h │ │ ├── stm32f4xx_rcc.h │ │ ├── stm32f4xx_rng.h │ │ ├── stm32f4xx_rtc.h │ │ ├── stm32f4xx_sai.h │ │ ├── stm32f4xx_sdio.h │ │ ├── stm32f4xx_spi.h │ │ ├── stm32f4xx_syscfg.h │ │ ├── stm32f4xx_tim.h │ │ ├── stm32f4xx_usart.h │ │ └── stm32f4xx_wwdg.h │ └── src │ │ ├── stm32f4xx_adc.c │ │ ├── stm32f4xx_can.c │ │ ├── stm32f4xx_crc.c │ │ ├── stm32f4xx_cryp.c │ │ ├── stm32f4xx_cryp_aes.c │ │ ├── stm32f4xx_cryp_des.c │ │ ├── stm32f4xx_cryp_tdes.c │ │ ├── stm32f4xx_dac.c │ │ ├── stm32f4xx_dbgmcu.c │ │ ├── stm32f4xx_dcmi.c │ │ ├── stm32f4xx_dma.c │ │ ├── stm32f4xx_dma2d.c │ │ ├── stm32f4xx_exti.c │ │ ├── stm32f4xx_flash.c │ │ ├── stm32f4xx_fmc.c │ │ ├── stm32f4xx_fsmc.c │ │ ├── stm32f4xx_gpio.c │ │ ├── stm32f4xx_hash.c │ │ ├── stm32f4xx_hash_md5.c │ │ ├── stm32f4xx_hash_sha1.c │ │ ├── stm32f4xx_i2c.c │ │ ├── stm32f4xx_iwdg.c │ │ ├── stm32f4xx_ltdc.c │ │ ├── stm32f4xx_misc.c │ │ ├── stm32f4xx_pwr.c │ │ ├── stm32f4xx_rcc.c │ │ ├── stm32f4xx_rng.c │ │ ├── stm32f4xx_rtc.c │ │ ├── stm32f4xx_sai.c │ │ ├── stm32f4xx_sdio.c │ │ ├── stm32f4xx_spi.c │ │ ├── stm32f4xx_syscfg.c │ │ ├── stm32f4xx_tim.c │ │ ├── stm32f4xx_usart.c │ │ └── stm32f4xx_wwdg.c └── STM32_CPAL_Driver │ ├── Release_Notes.html │ ├── devices │ ├── stm32f10x │ │ ├── cpal_i2c_hal_stm32f10x.c │ │ └── cpal_i2c_hal_stm32f10x.h │ ├── stm32f2xx │ │ ├── cpal_i2c_hal_stm32f2xx.c │ │ └── cpal_i2c_hal_stm32f2xx.h │ ├── stm32f4xx │ │ ├── cpal_i2c_hal_stm32f4xx.c │ │ └── cpal_i2c_hal_stm32f4xx.h │ └── stm32l1xx │ │ ├── cpal_i2c_hal_stm32l1xx.c │ │ └── cpal_i2c_hal_stm32l1xx.h │ ├── inc │ ├── cpal.h │ └── cpal_i2c.h │ └── src │ ├── cpal_hal.c │ ├── cpal_i2c.c │ └── cpal_usercallback_template.c ├── module.json ├── scripts ├── linker │ ├── STM32F103_32K_20K_DEF.ld │ ├── STM32F103_32K_20K_DEF_CLOAD.ld │ ├── STM32F103_32K_20K_FLASH.ld │ ├── STM32F103_32K_20K_FLASH_CLOAD.ld │ ├── STM32F10x_COMMON.ld │ ├── STM32F303xC.ld │ └── sections_FLASH.ld ├── print_revision.sh └── targets.mk ├── src ├── bootpin.c ├── main.c ├── syslink.c └── uart.c └── tools └── build └── build /.github/workflows/CI.yml: -------------------------------------------------------------------------------- 1 | # Build the project using the Bitcraze builder docker image 2 | name: CI 3 | 4 | on: 5 | push: 6 | branches: [ master ] 7 | pull_request: 8 | branches: [ master ] 9 | schedule: 10 | # Weekly build to make sure dependencies are OK 11 | - cron: '30 10 * * 2' 12 | 13 | jobs: 14 | build: 15 | uses: bitcraze/workflows/.github/workflows/basic_build.yml@b59a297ee5a6105780d4ac832100f8990f243d04 16 | with: 17 | builder_image: 'bitcraze/builder' 18 | -------------------------------------------------------------------------------- /.github/workflows/release.yml: -------------------------------------------------------------------------------- 1 | # Release jobs 2 | 3 | name: Release 4 | 5 | on: 6 | workflow_dispatch: 7 | 8 | jobs: 9 | build: 10 | uses: bitcraze/workflows/.github/workflows/basic_release.yml@b06a0f369e637f5f5a5f83f5e86d9b1f9e173289 11 | with: 12 | builder_image: 'bitcraze/builder' 13 | artifacts: 'cf2loader.bin' 14 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | ^bin/dep/all 3 | bin/* 4 | .cproject 5 | .project 6 | .settings/* 7 | *~ 8 | *.o 9 | *.elf 10 | *.d 11 | *.bin 12 | *.hex 13 | *.map 14 | config.mk 15 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # CrazyFlie's Makefile 2 | # Copyright (c) 2011,2012 Bitcraze AB 3 | # This Makefile compiles all the objet file to ./bin/ and the resulting firmware 4 | # image in ./cflie.elf and ./cflie.bin 5 | 6 | #Put your personal build config in config.mk and DO NOT COMMIT IT! 7 | -include config.mk 8 | 9 | ######### JTAG and environment configuration ########## 10 | OPENOCD ?= openocd 11 | OPENOCD_INTERFACE ?= interface/stlink-v2.cfg 12 | OPENOCD_TARGET ?= target/stm32f4x_stlink.cfg 13 | OPENOCD_CMDS ?= 14 | CROSS_COMPILE ?= arm-none-eabi- 15 | PYTHON2 ?= python 16 | CLOAD ?= 0 17 | DEBUG ?= 1 18 | CLOAD_SCRIPT ?= ../crazyflie-pc-client/bin/cfloader 19 | 20 | # Now needed for SYSLINK 21 | CFLAGS += -DUSE_SYSLINK_CRTP # Set CRTP link to syslink 22 | CFLAGS += -DENABLE_UART # To enable the uart 23 | 24 | ## Flag that can be added to config.mk 25 | # CFLAGS += -DUSE_ESKYLINK # Set CRTP link to E-SKY receiver 26 | # CFLAGS += -DDEBUG_PRINT_ON_UART # Redirect the console output to the UART 27 | 28 | REV ?= E 29 | 30 | #OpenOCD conf 31 | RTOS_DEBUG ?= 0 32 | 33 | ############### Location configuration ################ 34 | 35 | STLIB = lib/ 36 | 37 | ################ Build configuration ################## 38 | # St Lib 39 | VPATH += $(STLIB)/CMSIS/STM32F4xx/Source/ 40 | VPATH += $(STLIB)/STM32_CPAL_Driver/src 41 | VPATH += $(STLIB)/STM32_CPAL_Driver/devices/stm32f4xx 42 | VPATH += $(STLIB)/STM32F4xx_StdPeriph_Driver/src 43 | CRT0 = startup_stm32f40xx.o system_stm32f4xx.o 44 | 45 | # Should maybe be in separate file? 46 | #-include scripts/st_f405_obj.mk 47 | ST_OBJ += stm32f4xx_rcc.o stm32f4xx_gpio.o stm32f4xx_usart.o stm32f4xx_misc.o stm32f4xx_flash.o 48 | # ST_OBJ += cpal_hal.o cpal_i2c.o cpal_usercallback_template.o cpal_i2c_hal_stm32f4xx.o 49 | 50 | # Crazyflie 51 | VPATH += src 52 | 53 | 54 | ############### Source files configuration ################ 55 | 56 | PROJ_OBJ = main.o uart.o syslink.o bootpin.o 57 | 58 | 59 | OBJ = $(CRT0) $(ST_OBJ) $(PROJ_OBJ) 60 | 61 | ifdef P 62 | C_PROFILE = -D P_$(P) 63 | endif 64 | 65 | ############### Compilation configuration ################ 66 | AS = $(CROSS_COMPILE)as 67 | CC = $(CROSS_COMPILE)gcc 68 | LD = $(CROSS_COMPILE)gcc 69 | SIZE = $(CROSS_COMPILE)size 70 | OBJCOPY = $(CROSS_COMPILE)objcopy 71 | 72 | 73 | INCLUDES = -Iinclude -I$(PORT) -I. 74 | INCLUDES+= -Iconfig -Ihal/interface -Imodules/interface 75 | INCLUDES+= -Iutils/interface -Idrivers/interface -Iplatform 76 | INCLUDES+= -I$(STLIB)/CMSIS/Include 77 | 78 | INCLUDES+= -I$(STLIB)/STM32F4xx_StdPeriph_Driver/inc 79 | INCLUDES+= -I$(STLIB)/STM32_CPAL_Driver/inc 80 | INCLUDES+= -I$(STLIB)/STM32_CPAL_Driver/devices/stm32f4xx 81 | INCLUDES+= -I$(STLIB)/CMSIS/STM32F4xx/Include 82 | 83 | PROCESSOR = -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 84 | 85 | #Flags required by the ST library 86 | STFLAGS = -DSTM32F4XX -DSTM32F40_41xxx -DHSE_VALUE=8000000 -DUSE_STDPERIPH_DRIVER 87 | 88 | 89 | ifeq ($(DEBUG), 1) 90 | CFLAGS += -O0 -g3 91 | else 92 | CFLAGS += -Os -g3 93 | endif 94 | 95 | ifeq ($(LTO), 1) 96 | CFLAGS += -flto 97 | endif 98 | 99 | CFLAGS += -DBOARD_REV_$(REV) 100 | 101 | CFLAGS += $(PROCESSOR) $(INCLUDES) $(STFLAGS) -Wall -fno-strict-aliasing $(C_PROFILE) 102 | # Compiler flags to generate dependency files: 103 | CFLAGS += -MD -MP -MF $(BIN)/dep/$(@).d -MQ $(@) 104 | #Permits to remove un-used functions and global variables from output file 105 | CFLAGS += -ffunction-sections -fdata-sections 106 | 107 | ASFLAGS = $(PROCESSOR) $(INCLUDES) 108 | LDFLAGS = $(PROCESSOR) -Wl,-Map=$(PROG).map,--cref,--gc-sections 109 | 110 | ifeq ($(CLOAD), 1) 111 | LDFLAGS += -T scripts/linker/STM32F103_32K_20K_FLASH_CLOAD.ld 112 | else 113 | LDFLAGS += -T scripts/linker/STM32F103_32K_20K_FLASH.ld 114 | endif 115 | 116 | ifeq ($(LTO), 1) 117 | LDFLAGS += -Os -flto -fuse-linker-plugin 118 | endif 119 | 120 | #Program name 121 | PROG = cf2loader 122 | #Where to compile the .o 123 | BIN = bin 124 | VPATH += $(BIN) 125 | 126 | #Dependency files to include 127 | DEPS := $(foreach o,$(OBJ),$(BIN)/dep/$(o).d) 128 | 129 | ##################### Misc. ################################ 130 | ifeq ($(SHELL),/bin/sh) 131 | COL_RED=\033[1;31m 132 | COL_GREEN=\033[1;32m 133 | COL_RESET=\033[m 134 | endif 135 | 136 | #################### Targets ############################### 137 | 138 | 139 | all: build 140 | build: clean_version compile print_version size 141 | compile: clean_version $(PROG).hex $(PROG).bin 142 | 143 | clean_version: 144 | ifeq ($(SHELL),/bin/sh) 145 | @echo " CLEAN_VERSION" 146 | @rm -f version.c 147 | endif 148 | 149 | print_version: compile 150 | ifeq ($(SHELL),/bin/sh) 151 | @./scripts/print_revision.sh 152 | endif 153 | ifeq ($(CLOAD), 1) 154 | @echo "CrazyLoader build!" 155 | endif 156 | 157 | size: compile 158 | @$(SIZE) -B $(PROG).elf 159 | 160 | #Radio bootloader 161 | cload: 162 | ifeq ($(CLOAD), 1) 163 | $(CLOAD_SCRIPT) flash cflie.bin 164 | else 165 | @echo "Only cload build can be bootloaded. Launch build and cload with CLOAD=1" 166 | endif 167 | 168 | #Flash the stm. 169 | flash: 170 | $(OPENOCD) -d2 -f $(OPENOCD_INTERFACE) $(OPENOCD_CMDS) -f $(OPENOCD_TARGET) -c init -c targets -c "reset halt" \ 171 | -c "flash write_image erase $(PROG).elf" -c "verify_image $(PROG).elf" -c "reset run" -c shutdown 172 | 173 | #STM utility targets 174 | halt: 175 | $(OPENOCD) -d0 -f $(OPENOCD_INTERFACE) $(OPENOCD_CMDS) -f $(OPENOCD_TARGET) -c init -c targets -c "halt" -c shutdown 176 | 177 | reset: 178 | $(OPENOCD) -d0 -f $(OPENOCD_INTERFACE) $(OPENOCD_CMDS) -f $(OPENOCD_TARGET) -c init -c targets -c "reset" -c shutdown 179 | 180 | openocd: 181 | $(OPENOCD) -d2 -f $(OPENOCD_INTERFACE) $(OPENOCD_CMDS) -f $(OPENOCD_TARGET) -c init -c targets 182 | 183 | #Print preprocessor #defines 184 | prep: 185 | @$(CC) -dD 186 | 187 | include scripts/targets.mk 188 | 189 | #include dependencies 190 | -include $(DEPS) 191 | -------------------------------------------------------------------------------- /Readme.md: -------------------------------------------------------------------------------- 1 | # Crazyflie 2 STM Bootloader [![CI](https://github.com/bitcraze/crazyflie2-stm-bootloader/workflows/CI/badge.svg)](https://github.com/bitcraze/crazyflie2-stm-bootloader/actions?query=workflow%3ACI) 2 | 3 | Bootloader for the Crazyflie 2 4 | 5 | ## Architecture 6 | The Bootloader sits at the beginning of the flash memory 1) and handles the memory in pages: 7 | ``` 8 | +------------+ <- flashPages 9 | | | 10 | | | 11 | | | 12 | | | 13 | | | 14 | | | 15 | | | 16 | | | 17 | | | 18 | | | 19 | | Firmware | 20 | | | 21 | | | 22 | +------------+ <- flashStart 23 | | Bootloader | 24 | +------------+ <- Page 0 25 | ``` 26 | 27 | The size of the pages, the values flashStart and flashPages are communicated by the protocol. For simplicity of the bootloader implementation this architecture is exposed to the protocol 28 | ``` 29 | +---------------+ +--------------+ 30 | | Buffer page n | | Flash Page m | 31 | +---------------+ +--------------+ 32 | \ \ \ \ 33 | \ \ \ \ 34 | +---------------+ +-------+ +--------------+ 35 | | Buffer page 0 |----->| Flash |------>| Flash Page 0 | 36 | +---------------+ +-------+ +--------------+ 37 | ^ ^ | 38 | | | | 39 | v | v 40 | +------------------------------------------------------+ 41 | | Bootloader control | 42 | +------------------------------------------------------+ 43 | ``` 44 | 45 | The procedure to flash is then to send the data to the buffer, and then order the bootloader to flash the buffer(s) in flash. All parameters like page size, number of flash page, number of buffer pages, are accessible via the protocol so that it is possible to change these physical values without changing the bootloader client. 46 | 47 | ## Protocol 48 | 49 | All packets sent to the bootloader starts with “0xFF Target_number”, this kind of packets are called 'NULL Parcket' by CRTP and are ignored by the Crazyflie firmware. The target number has been introduced with Crazyflie 2 as it contains 2 bootloader. The mapping is as follow: 50 | 51 | | Board | Target_number | MCU | Protocol version | 52 | | ----- | ------------- | --- | ---------------- | 53 | | Crazyflie 1 | 0xFF | STM32F103 | 0x00 | 54 | | Crazyflie 2 | 0xFF | STM32F405 | 0x10 | 55 | | ::: | 0xFE | nRF51822 | 0x10 | 56 | 57 | The high nibble of the version aims at describing the board if board-specific change is required to the protocol (ie. GET_MAPPING that is specific to stm32f405). 58 | 59 | All packets have the following format: 60 | 61 | 62 | +------+---------------+---------+======+ 63 | | 0xFF | Target_number | Command | Data | 64 | +------+---------------+---------+======+ 65 | 1 1 1 0-28 Bytes 66 | 67 | 68 | In the rest of this page commands and data are described. 69 | 70 | ### Commands summary 71 | 72 | | Command | Name | Note | 73 | | ------- | ---- | ---- | 74 | | 0x10 | GET_INFO | | 75 | | 0x11 | SET_ADDRESS | Only implemented on Crazyflie version 0x00 | 76 | | 0x12 | GET_MAPPING | Only implemented in version 0x10 target 0xFF | 77 | | 0x14 | LOAD_BUFFER | | 78 | | 0x15 | READ_BUFFER | | 79 | | 0x18 | WRITE_FLASH | | 80 | | 0x19 | FLASH_STATUS | | 81 | | 0x1C | READ_FLASH | | 82 | | 0xFF | RESET_INIT | Only implemented in version 0x10 target 0xFE | 83 | | 0xF0 | RESET | Only implemented in version 0x10 target 0xFE | 84 | | 0x01 | ALLOFF | Only implemented in version 0x10 target 0xFE | 85 | | 0x02 | SYSOFF | Only implemented in version 0x10 target 0xFE | 86 | | 0x03 | SYSON | Only implemented in version 0x10 target 0xFE | 87 | | 0x04 | GETVBAT | Only implemented in version 0x10 target 0xFE | 88 | 89 | #### GET_INFO 90 | 91 | | Byte | Request fields | Content | 92 | | ---- | -------------- | ------- | 93 | | 0 | GET_INFO | 0x10 | 94 | 95 | | Byte | Answer fields | Content | 96 | | ---- | -------------- | ------- | 97 | | 0 | GET_INFO | 0x10 | 98 | | 1-2 | pageSize | Size in byte of flash and buffer page | 99 | | 3-4 | nBuffPage | Number of ram buffer page available | 100 | | 5-6 | nFlashPage | Total number of flash page | 101 | | 7-8 | flashStart | Start flash page of the firmware | 102 | | 9-21 | cpuId | Legacy 12Bytes CPUID, shall be ignored | 103 | | 22 | version | Version of the protocol | 104 | 105 | 106 | This exchange requests the bootloader info. The content of this packet contains all information required to program the flash. 107 | 108 | #### SET_ADDRESS 109 | 110 | | Byte | Request fields | Content | 111 | | ---- | -------------- | ------- | 112 | | 0 | SET_ADDRESS | 0x11 | 113 | | 1-6 | address | 5 Bytes radio (ESB) address | 114 | 115 | Sets the radio address. This allows to make sure no other computer will interfere with the flash process. It is not mandatory. 116 | 117 | #### GET_MAPPING 118 | 119 | | Byte | Request fields | Content | 120 | | ---- | -------------- | ------- | 121 | | 0 | GET_MAPPING | 0x12 | 122 | 123 | | Byte | Answer fields | Content | 124 | | ---- | -------------- | ------- | 125 | | 0 | GET_MAPPING | 0x12 | 126 | | 1-.. | mapping | Erase page mapping of the flash, up to 27 bytes | 127 | 128 | For all supported MCU except the STM32F405 when flashing one page the page is erased and then written with the new data. 129 | 130 | The STM32F405 though has a very large flash memory (1M) and fairly large erase sector that have a different size. On this chip the bootloader is setup with 1024Bytes pages and when a page happens to be the first of a sector the full sector is erased. This command allows to request the size of the sectors. 131 | 132 | The mapping field is encoded as a sequence of [Number of sector, Size of sector in page]. For example the STM32F405 has a mapping of [4, 16, 1, 64, 7, 128] because it contains 4 sector of 16KB, 1 of 64KB and 7 of 128KB. If this command where implemented in the STM32F103 the mapping would be [128, 1]. 133 | 134 | #### LOAD_BUFFER 135 | 136 | | Byte | Request fields | Content | 137 | | ---- | -------------- | ------- | 138 | | 0 | LOAD_BUFFER | 0x14 | 139 | | 1-2 | page | Buffer page to load into | 140 | | 3-4 | Address | Address in the buffer page to load from | 141 | | 5-31 | data | Data to load | 142 | 143 | #### READ_BUFFER 144 | 145 | | Byte | Request fields | Content | 146 | | ---- | -------------- | ------- | 147 | | 0 | READ_BUFFER | 0x15 | 148 | | 1-2 | page | Buffer page to read | 149 | | 3-4 | Address | Address in the buffer page to read from | 150 | 151 | | Byte | Answer fields | Content | 152 | | ---- | ------------- | ------- | 153 | | 0 | READ_BUFFER | 0x15 | 154 | | 1-2 | page | Buffer page read | 155 | | 3-4 | Address | Address in the buffer page read from | 156 | | 5-31 | data | Data read | 157 | 158 | #### WRITE_FLASH 159 | 160 | | Byte | Request fields | Content | 161 | | ---- | -------------- | ------- | 162 | | 0 | WRITE_BUFFER | 0x18 | 163 | | 1-2 | bufferPage | Buffer page source | 164 | | 3-4 | flashPage | Flash page destination | 165 | | 5-6 | nPages | Number of page to program | 166 | 167 | | Byte | Answer fields | Content | 168 | | ---- | ------------- | ------- | 169 | | 0 | WRITE_FLASH | 0x18 | 170 | | 1 | done | At 0 if the operation failed, not 0 otherwise | 171 | | 2 | Error | 0 if no error, otherwise contains error code | 172 | 173 | The error code can be: 174 | 175 | | Code | Meaning | 176 | | ---- | ------- | 177 | | 0 | No error | 178 | | 1 | Addresses are outside of authorized boundaries | 179 | | 2 | Flash erase failed | 180 | | 3 | Flash programming failed | 181 | 182 | #### FLASH_STATUS 183 | 184 | | Byte | Request fields | Content | 185 | | ---- | -------------- | ------- | 186 | | 0 | FLASH_STATUS | 0x19 | 187 | 188 | | Byte | Answer fields | Content | 189 | | ---- | -------------- | ------- | 190 | | 0 | FLASH_STATUS | 0x19 | 191 | | 1 | done | At 0 if the operation failed, not 0 otherwise | 192 | | 2 | Error | 0 if no error, otherwise contains error code | 193 | 194 | This message aims at checking the latest flash operation in case where the WRITE_FLASH answer would be lost. The error code follows the same format as for WRITE_FLASH. 195 | 196 | #### READ_FLASH 197 | 198 | | Byte | Request fields | Content | 199 | | ---- | -------------- | ------- | 200 | | 0 | READ_FLASH | 0x1C | 201 | | 1-2 | page | Flash page to read | 202 | | 3-4 | Address | Address in the flash page to read from | 203 | 204 | | Byte | Answer fields | Content | 205 | | ---- | -------------- | ------- | 206 | | 0 | READ_FLASH | 0x1C | 207 | | 1-2 | page | Flash page read | 208 | | 3-4 | Address | Address in the flash page read from | 209 | | 5-31 | data | Data read | 210 | 211 | #### RESET_INIT 212 | 213 | Prepare to reset (no additional data fields). The result will be the original request. 214 | 215 | #### RESET 216 | 217 | Reset (no additional data fields). No result will be sent. 218 | 219 | #### ALLOFF 220 | 221 | Turn everything off as if the power button would have been pressed (i.e. STM32 and radio). The CF won't be able to wake-up unless the power button is pressed. No result will be sent. 222 | 223 | #### SYSOFF 224 | 225 | Turn the STM32 off, but keep the NRF51 with radio awake. The CF can be woken up by: sending reset, pressing the power button, or sendind SYSON. No result will be sent. 226 | 227 | #### SYSON 228 | 229 | Turn the STM32 on. No result will be sent. 230 | 231 | #### GETVBAT 232 | 233 | | Byte | Answer fields | Content | 234 | | ---- | ------------- | ------- | 235 | | 0-3 | vbat | floating point value containing the current battery voltage in volts | 236 | 237 | Check battery status (works even if the STM32 is turned off). 238 | 239 | ## Contribute 240 | Go to the [contribute page](https://www.bitcraze.io/contribute/) on our website to learn more. 241 | 242 | ### Test code for contribution 243 | Run the automated build locally to test your code 244 | 245 | ./tools/build/build 246 | 247 | -------------------------------------------------------------------------------- /bin/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | !dep 4 | -------------------------------------------------------------------------------- /bin/dep/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | -------------------------------------------------------------------------------- /include/bootpin.h: -------------------------------------------------------------------------------- 1 | #ifndef __BOOTPIN_H__ 2 | #define __BOOTPIN_H__ 3 | 4 | #include 5 | 6 | void bootpinInit(void); 7 | 8 | void bootpinDeinit(void); 9 | 10 | bool bootpinStartFirmware(void); 11 | 12 | bool bootpinStartBootloader(void); 13 | 14 | bool bootpinNrfReset(void); 15 | 16 | #endif //__BOOTPIN_H__ 17 | -------------------------------------------------------------------------------- /include/config.h: -------------------------------------------------------------------------------- 1 | /** 2 | * || ____ _ __ ______ 3 | * +------+ / __ )(_) /_/ ____/_________ ____ ____ 4 | * | 0xBC | / __ / / __/ / / ___/ __ `/_ / / _ \ 5 | * +------+ / /_/ / / /_/ /___ / / / /_/ / / /_/ __/ 6 | * || || /_____/_/\__/\____//_/ \__,_/ /___/ \___/ 7 | * 8 | * CrazyLoader firmware 9 | * 10 | * Copyright (C) 2011-2013 Bitcraze AB 11 | * 12 | * This program is free software: you can redistribute it and/or modify 13 | * it under the terms of the GNU General Public License as published by 14 | * the Free Software Foundation, in version 3. 15 | * 16 | * This program is distributed in the hope that it will be useful, 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | * GNU General Public License for more details. 20 | * 21 | * You should have received a copy of the GNU General Public License 22 | * along with this program. If not, see . 23 | * 24 | * config.h - CrazyLoader config include file 25 | */ 26 | #ifndef __CONFIG_H__ 27 | #define __CONFIG_H__ 28 | 29 | 30 | //TODO: Most of that shall be possible to get automatically ... 31 | #define BUFFER_PAGES 10 32 | #define flashPages 1024 33 | #define FLASH_START 16 34 | 35 | #define PAGE_SIZE 1024 36 | 37 | #ifndef FLASH_BASE 38 | #define FLASH_BASE 0x08000000 39 | #endif 40 | 41 | #define FIRMWARE_START (FLASH_BASE+(FLASH_START*PAGE_SIZE)) 42 | 43 | #define SYSTEM_BASE 0x1FFF0000 44 | 45 | #define RADIO_CHANEL 110 46 | 47 | #endif /* __CONFIG_H__ */ 48 | -------------------------------------------------------------------------------- /include/crtp.h: -------------------------------------------------------------------------------- 1 | /* Crtp packet format header */ 2 | #ifndef __CTRP_H__ 3 | #define __CRTP_H__ 4 | 5 | #include 6 | 7 | #define CRTP_MAX_DATA_SIZE 31 8 | 9 | typedef struct crtpPacket_s { 10 | union { 11 | struct { 12 | union { 13 | uint8_t header; 14 | struct { 15 | uint8_t channel:2; 16 | uint8_t reserved:2; 17 | uint8_t port:4; 18 | }; 19 | }; 20 | uint8_t data[CRTP_MAX_DATA_SIZE]; 21 | } __attribute__((packed)); 22 | char raw[CRTP_MAX_DATA_SIZE +1]; 23 | }; 24 | uint8_t datalen; 25 | } CrtpPacket; 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /include/loaderCommands.h: -------------------------------------------------------------------------------- 1 | /** 2 | * || ____ _ __ ______ 3 | * +------+ / __ )(_) /_/ ____/_________ ____ ____ 4 | * | 0xBC | / __ / / __/ / / ___/ __ `/_ / / _ \ 5 | * +------+ / /_/ / / /_/ /___ / / / /_/ / / /_/ __/ 6 | * || || /_____/_/\__/\____//_/ \__,_/ /___/ \___/ 7 | * 8 | * CrazyLoader firmware 9 | * 10 | * Copyright (C) 2011-2013 Bitcraze AB 11 | * 12 | * This program is free software: you can redistribute it and/or modify 13 | * it under the terms of the GNU General Public License as published by 14 | * the Free Software Foundation, in version 3. 15 | * 16 | * This program is distributed in the hope that it will be useful, 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | * GNU General Public License for more details. 20 | * 21 | * You should have received a copy of the GNU General Public License 22 | * along with this program. If not, see . 23 | * 24 | * loaderCommands.h - Define the structures of the commands parameters and returns 25 | */ 26 | #ifndef __LOADER_COMMANDS_H__ 27 | #define __LOADER_COMMANDS_H__ 28 | 29 | /* XXX: Protocol version has to be increased each time a command is 30 | * added or modified! 31 | */ 32 | #define PROTOCOL_VERSION 0x10 33 | 34 | #define CPUID_LEN 12 35 | 36 | /******* GetInfo ******/ 37 | #define CMD_GET_INFO 0x10 38 | //Parameters ... void 39 | //Returns: 40 | typedef struct { 41 | short pageSize; 42 | short nBuffPages; 43 | short nFlashPages; 44 | short flashStart; 45 | char cpuId[CPUID_LEN]; 46 | char version; 47 | } __attribute__((__packed__)) GetInfoReturns_t; 48 | 49 | /****** SetAddress ****/ 50 | #define CMD_SET_ADDRESS 0x11 51 | //Parameters: 52 | typedef struct { 53 | char address[5]; 54 | } __attribute__((__packed__)) SetAddressParameters_t; 55 | //Returns ... void 56 | 57 | /******* GetInfo ******/ 58 | #define CMD_GET_MAPPING 0x12 59 | //Parameters ... void 60 | //Returns: 61 | typedef struct { 62 | char mapping[6]; 63 | } __attribute__((__packed__)) GetMappingReturns_t; 64 | 65 | /****** LoadBuffer ****/ 66 | #define CMD_LOAD_BUFFER 0x14 67 | //Parameters: 68 | typedef struct { 69 | unsigned short page; 70 | unsigned short address; 71 | } __attribute__((__packed__)) LoadBufferParameters_t; 72 | //Returns ... void 73 | 74 | /****** ReadBuffer ****/ 75 | #define CMD_READ_BUFFER 0x15 76 | //Parameters: 77 | typedef struct { 78 | unsigned short page; 79 | unsigned short address; 80 | } __attribute__((__packed__)) ReadBufferParameters_t; 81 | //Returns ... Same as parameters but with data 82 | 83 | /****** WriteFlash ****/ 84 | #define CMD_WRITE_FLASH 0x18 85 | //Parameters: 86 | typedef struct { 87 | unsigned short bufferPage; 88 | unsigned short flashPage; 89 | unsigned short nPages; 90 | } __attribute__((__packed__)) WriteFlashParameters_t; 91 | //Returns ... Same as parameters but with data 92 | typedef struct { 93 | char done; 94 | unsigned char error; 95 | } __attribute__((__packed__)) WriteFlashReturns_t; 96 | 97 | #define CMD_FLASH_STATUS 0x19 98 | //Parameters ... void 99 | //Returns: 100 | typedef struct { 101 | unsigned char done; 102 | unsigned char error; 103 | } __attribute__((__packed__)) FlashStatusReturns_t; 104 | 105 | /****** ReadBuffer ****/ 106 | #define CMD_READ_FLASH 0x1C 107 | //Parameters: 108 | typedef struct { 109 | unsigned short page; 110 | unsigned short address; 111 | } __attribute__((__packed__)) ReadFlashParameters_t; 112 | //Returns ... Same as parameters but with data 113 | 114 | 115 | 116 | #endif /* __LOADER_COMMANDS_H__ */ 117 | -------------------------------------------------------------------------------- /include/stm32f4xx_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2013 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __STM32F4xx_CONF_H 30 | #define __STM32F4xx_CONF_H 31 | 32 | /* Includes ------------------------------------------------------------------*/ 33 | /* Uncomment the line below to enable peripheral header file inclusion */ 34 | #include "stm32f4xx_adc.h" 35 | #include "stm32f4xx_crc.h" 36 | #include "stm32f4xx_dbgmcu.h" 37 | #include "stm32f4xx_dma.h" 38 | #include "stm32f4xx_exti.h" 39 | #include "stm32f4xx_flash.h" 40 | #include "stm32f4xx_gpio.h" 41 | #include "stm32f4xx_i2c.h" 42 | #include "stm32f4xx_iwdg.h" 43 | #include "stm32f4xx_pwr.h" 44 | #include "stm32f4xx_rcc.h" 45 | #include "stm32f4xx_rtc.h" 46 | #include "stm32f4xx_sdio.h" 47 | #include "stm32f4xx_spi.h" 48 | #include "stm32f4xx_syscfg.h" 49 | #include "stm32f4xx_tim.h" 50 | #include "stm32f4xx_usart.h" 51 | #include "stm32f4xx_wwdg.h" 52 | #include "stm32f4xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 53 | 54 | #if defined (STM32F429_439xx) 55 | #include "stm32f4xx_cryp.h" 56 | #include "stm32f4xx_hash.h" 57 | #include "stm32f4xx_rng.h" 58 | #include "stm32f4xx_can.h" 59 | #include "stm32f4xx_dac.h" 60 | #include "stm32f4xx_dcmi.h" 61 | #include "stm32f4xx_dma2d.h" 62 | #include "stm32f4xx_fmc.h" 63 | #include "stm32f4xx_ltdc.h" 64 | #include "stm32f4xx_sai.h" 65 | #endif /* STM32F429_439xx */ 66 | 67 | #if defined (STM32F427_437xx) 68 | #include "stm32f4xx_cryp.h" 69 | #include "stm32f4xx_hash.h" 70 | #include "stm32f4xx_rng.h" 71 | #include "stm32f4xx_can.h" 72 | #include "stm32f4xx_dac.h" 73 | #include "stm32f4xx_dcmi.h" 74 | #include "stm32f4xx_dma2d.h" 75 | #include "stm32f4xx_fmc.h" 76 | #include "stm32f4xx_sai.h" 77 | #endif /* STM32F427_437xx */ 78 | 79 | #if defined (STM32F40_41xxx) 80 | #include "stm32f4xx_cryp.h" 81 | #include "stm32f4xx_hash.h" 82 | #include "stm32f4xx_rng.h" 83 | #include "stm32f4xx_can.h" 84 | #include "stm32f4xx_dac.h" 85 | #include "stm32f4xx_dcmi.h" 86 | #include "stm32f4xx_fsmc.h" 87 | #endif /* STM32F40_41xxx */ 88 | 89 | /* Exported types ------------------------------------------------------------*/ 90 | /* Exported constants --------------------------------------------------------*/ 91 | 92 | /* If an external clock source is used, then the value of the following define 93 | should be set to the value of the external clock source, else, if no external 94 | clock is used, keep this define commented */ 95 | /*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ 96 | 97 | 98 | /* Uncomment the line below to expanse the "assert_param" macro in the 99 | Standard Peripheral Library drivers code */ 100 | /* #define USE_FULL_ASSERT 1 */ 101 | 102 | /* Exported macro ------------------------------------------------------------*/ 103 | #ifdef USE_FULL_ASSERT 104 | 105 | /** 106 | * @brief The assert_param macro is used for function's parameters check. 107 | * @param expr: If expr is false, it calls assert_failed function 108 | * which reports the name of the source file and the source 109 | * line number of the call that failed. 110 | * If expr is true, it returns no value. 111 | * @retval None 112 | */ 113 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 114 | /* Exported functions ------------------------------------------------------- */ 115 | void assert_failed(uint8_t* file, uint32_t line); 116 | #else 117 | #define assert_param(expr) ((void)0) 118 | #endif /* USE_FULL_ASSERT */ 119 | 120 | #endif /* __STM32F4xx_CONF_H */ 121 | 122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 123 | -------------------------------------------------------------------------------- /include/syslink.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSLINK_H__ 2 | #define __SYSLINK_H__ 3 | 4 | #include 5 | #include 6 | 7 | #define SYSLINK_MTU 32 8 | 9 | typedef struct syslinkPacket { 10 | union { 11 | struct { 12 | uint8_t type; 13 | uint8_t length; 14 | char data[SYSLINK_MTU]; 15 | } __attribute__((packed)); 16 | char raw[SYSLINK_MTU+2]; 17 | }; 18 | } syslinkPacket_t; 19 | 20 | bool syslinkReceive(struct syslinkPacket *packet); 21 | 22 | bool syslinkSend(struct syslinkPacket *packet); 23 | 24 | // Defined packet types 25 | #define SYSLINK_RADIO_RAW 0x00 26 | #define SYSLINK_RADIO_CHANNEL 0x01 27 | #define SYSLINK_RADIO_DATARATE 0x02 28 | 29 | 30 | #define SYSLINK_PM_SOURCE 0x10 31 | 32 | #define SYSLINK_PM_ONOFF_SWITCHOFF 0x11 33 | 34 | #define SYSLINK_PM_BATTERY_VOLTAGE 0x12 35 | #define SYSLINK_PM_BATTERY_STATE 0x13 36 | #define SYSLINK_PM_BATTERY_AUTOUPDATE 0x14 37 | 38 | #define SYSLINK_OW_SCAN 0x20 39 | #define SYSLINK_OW_READ 0x21 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /include/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef __UART_H__ 2 | #define __UART_H__ 3 | 4 | #include 5 | 6 | void uartInit(); 7 | bool uartIsRxReady(); 8 | char uartGetc(); 9 | bool uartIsTxReady(); 10 | void uartPutc(char data); 11 | void uartPuts(char *string); 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /lib/CMSIS/Include/arm_common_tables.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 11. November 2010 5 | * $Revision: V1.0.2 6 | * 7 | * Project: CMSIS DSP Library 8 | * Title: arm_common_tables.h 9 | * 10 | * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 11 | * 12 | * Target Processor: Cortex-M4/Cortex-M3 13 | * 14 | * Version 1.0.2 2010/11/11 15 | * Documentation updated. 16 | * 17 | * Version 1.0.1 2010/10/05 18 | * Production release and review comments incorporated. 19 | * 20 | * Version 1.0.0 2010/09/20 21 | * Production release and review comments incorporated. 22 | * -------------------------------------------------------------------- */ 23 | 24 | #ifndef _ARM_COMMON_TABLES_H 25 | #define _ARM_COMMON_TABLES_H 26 | 27 | #include "arm_math.h" 28 | 29 | extern uint16_t armBitRevTable[1024]; 30 | extern q15_t armRecipTableQ15[64]; 31 | extern q31_t armRecipTableQ31[64]; 32 | extern const q31_t realCoefAQ31[1024]; 33 | extern const q31_t realCoefBQ31[1024]; 34 | 35 | #endif /* ARM_COMMON_TABLES_H */ 36 | -------------------------------------------------------------------------------- /lib/CMSIS/STM32F4xx/Include/stm32f4xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bitcraze/crazyflie2-stm-bootloader/c79feab3e232d90f5de00f59542280fd559ee743/lib/CMSIS/STM32F4xx/Include/stm32f4xx.h -------------------------------------------------------------------------------- /lib/CMSIS/STM32F4xx/Include/system_stm32f4xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2013 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32f4xx_system 33 | * @{ 34 | */ 35 | 36 | /** 37 | * @brief Define to prevent recursive inclusion 38 | */ 39 | #ifndef __SYSTEM_STM32F4XX_H 40 | #define __SYSTEM_STM32F4XX_H 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /** @addtogroup STM32F4xx_System_Includes 47 | * @{ 48 | */ 49 | 50 | /** 51 | * @} 52 | */ 53 | 54 | 55 | /** @addtogroup STM32F4xx_System_Exported_types 56 | * @{ 57 | */ 58 | 59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 60 | 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @addtogroup STM32F4xx_System_Exported_Constants 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @addtogroup STM32F4xx_System_Exported_Macros 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @addtogroup STM32F4xx_System_Exported_Functions 83 | * @{ 84 | */ 85 | 86 | extern void SystemInit(void); 87 | extern void SystemCoreClockUpdate(void); 88 | /** 89 | * @} 90 | */ 91 | 92 | #ifdef __cplusplus 93 | } 94 | #endif 95 | 96 | #endif /*__SYSTEM_STM32F4XX_H */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 106 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/Release_Notes.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bitcraze/crazyflie2-stm-bootloader/c79feab3e232d90f5de00f59542280fd559ee743/lib/STM32F4xx_StdPeriph_Driver/Release_Notes.html -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_crc.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_CRC_H 31 | #define __STM32F4xx_CRC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CRC 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup CRC_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /* Exported macro ------------------------------------------------------------*/ 60 | /* Exported functions --------------------------------------------------------*/ 61 | 62 | void CRC_ResetDR(void); 63 | uint32_t CRC_CalcCRC(uint32_t Data); 64 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 65 | uint32_t CRC_GetCRC(void); 66 | void CRC_SetIDRegister(uint8_t IDValue); 67 | uint8_t CRC_GetIDRegister(void); 68 | 69 | #ifdef __cplusplus 70 | } 71 | #endif 72 | 73 | #endif /* __STM32F4xx_CRC_H */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 84 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the DBGMCU firmware library. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2013 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __STM32F4xx_DBGMCU_H 30 | #define __STM32F4xx_DBGMCU_H 31 | 32 | #ifdef __cplusplus 33 | extern "C" { 34 | #endif 35 | 36 | /* Includes ------------------------------------------------------------------*/ 37 | #include "stm32f4xx.h" 38 | 39 | /** @addtogroup STM32F4xx_StdPeriph_Driver 40 | * @{ 41 | */ 42 | 43 | /** @addtogroup DBGMCU 44 | * @{ 45 | */ 46 | 47 | /* Exported types ------------------------------------------------------------*/ 48 | /* Exported constants --------------------------------------------------------*/ 49 | 50 | /** @defgroup DBGMCU_Exported_Constants 51 | * @{ 52 | */ 53 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 54 | #define DBGMCU_STOP ((uint32_t)0x00000002) 55 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 56 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) 57 | 58 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) 59 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) 60 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) 61 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) 62 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) 63 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) 64 | #define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) 65 | #define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) 66 | #define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) 67 | #define DBGMCU_RTC_STOP ((uint32_t)0x00000400) 68 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) 69 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) 70 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) 71 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) 72 | #define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) 73 | #define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) 74 | #define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) 75 | #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) 76 | 77 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) 78 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) 79 | #define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) 80 | #define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) 81 | #define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) 82 | #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) 83 | /** 84 | * @} 85 | */ 86 | 87 | /* Exported macro ------------------------------------------------------------*/ 88 | /* Exported functions --------------------------------------------------------*/ 89 | uint32_t DBGMCU_GetREVID(void); 90 | uint32_t DBGMCU_GetDEVID(void); 91 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 92 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); 93 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); 94 | 95 | #ifdef __cplusplus 96 | } 97 | #endif 98 | 99 | #endif /* __STM32F4xx_DBGMCU_H */ 100 | 101 | /** 102 | * @} 103 | */ 104 | 105 | /** 106 | * @} 107 | */ 108 | 109 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 110 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_exti.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the EXTI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_EXTI_H 31 | #define __STM32F4xx_EXTI_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup EXTI 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief EXTI mode enumeration 52 | */ 53 | 54 | typedef enum 55 | { 56 | EXTI_Mode_Interrupt = 0x00, 57 | EXTI_Mode_Event = 0x04 58 | }EXTIMode_TypeDef; 59 | 60 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 61 | 62 | /** 63 | * @brief EXTI Trigger enumeration 64 | */ 65 | 66 | typedef enum 67 | { 68 | EXTI_Trigger_Rising = 0x08, 69 | EXTI_Trigger_Falling = 0x0C, 70 | EXTI_Trigger_Rising_Falling = 0x10 71 | }EXTITrigger_TypeDef; 72 | 73 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 74 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 75 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 76 | /** 77 | * @brief EXTI Init Structure definition 78 | */ 79 | 80 | typedef struct 81 | { 82 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 83 | This parameter can be any combination value of @ref EXTI_Lines */ 84 | 85 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 86 | This parameter can be a value of @ref EXTIMode_TypeDef */ 87 | 88 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 89 | This parameter can be a value of @ref EXTITrigger_TypeDef */ 90 | 91 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 92 | This parameter can be set either to ENABLE or DISABLE */ 93 | }EXTI_InitTypeDef; 94 | 95 | /* Exported constants --------------------------------------------------------*/ 96 | 97 | /** @defgroup EXTI_Exported_Constants 98 | * @{ 99 | */ 100 | 101 | /** @defgroup EXTI_Lines 102 | * @{ 103 | */ 104 | 105 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ 106 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ 107 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ 108 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ 109 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ 110 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ 111 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ 112 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ 113 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ 114 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ 115 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ 116 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ 117 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ 118 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ 119 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ 120 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ 121 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ 122 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 123 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ 124 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 125 | #define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ 126 | #define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ 127 | #define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ 128 | 129 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) 130 | 131 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 132 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 133 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 134 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 135 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 136 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 137 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 138 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 139 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 140 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ 141 | ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ 142 | ((LINE) == EXTI_Line22)) 143 | 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /* Exported macro ------------------------------------------------------------*/ 153 | /* Exported functions --------------------------------------------------------*/ 154 | 155 | /* Function used to set the EXTI configuration to the default reset state *****/ 156 | void EXTI_DeInit(void); 157 | 158 | /* Initialization and Configuration functions *********************************/ 159 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 160 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 161 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 162 | 163 | /* Interrupts and flags management functions **********************************/ 164 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 165 | void EXTI_ClearFlag(uint32_t EXTI_Line); 166 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 167 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 168 | 169 | #ifdef __cplusplus 170 | } 171 | #endif 172 | 173 | #endif /* __STM32F4xx_EXTI_H */ 174 | 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 184 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hash.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the HASH 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_HASH_H 31 | #define __STM32F4xx_HASH_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup HASH 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief HASH Init structure definition 52 | */ 53 | typedef struct 54 | { 55 | uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter 56 | can be a value of @ref HASH_Algo_Selection */ 57 | uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value 58 | of @ref HASH_processor_Algorithm_Mode */ 59 | uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 60 | bit string. This parameter can be a value of 61 | @ref HASH_Data_Type */ 62 | uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter 63 | can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ 64 | }HASH_InitTypeDef; 65 | 66 | /** 67 | * @brief HASH message digest result structure definition 68 | */ 69 | typedef struct 70 | { 71 | uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256, 72 | 7x 32bit wors for SHA-224, 73 | 5x 32bit words for SHA-1 or 74 | 4x 32bit words for MD5 */ 75 | } HASH_MsgDigest; 76 | 77 | /** 78 | * @brief HASH context swapping structure definition 79 | */ 80 | typedef struct 81 | { 82 | uint32_t HASH_IMR; 83 | uint32_t HASH_STR; 84 | uint32_t HASH_CR; 85 | uint32_t HASH_CSR[54]; 86 | }HASH_Context; 87 | 88 | /* Exported constants --------------------------------------------------------*/ 89 | 90 | /** @defgroup HASH_Exported_Constants 91 | * @{ 92 | */ 93 | 94 | /** @defgroup HASH_Algo_Selection 95 | * @{ 96 | */ 97 | #define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ 98 | #define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ 99 | #define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ 100 | #define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ 101 | 102 | #define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ 103 | ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \ 104 | ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \ 105 | ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) 106 | /** 107 | * @} 108 | */ 109 | 110 | /** @defgroup HASH_processor_Algorithm_Mode 111 | * @{ 112 | */ 113 | #define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ 114 | #define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ 115 | 116 | #define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ 117 | ((ALGOMODE) == HASH_AlgoMode_HMAC)) 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @defgroup HASH_Data_Type 123 | * @{ 124 | */ 125 | #define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ 126 | #define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ 127 | #define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ 128 | #define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ 129 | 130 | #define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ 131 | ((DATATYPE) == HASH_DataType_16b)|| \ 132 | ((DATATYPE) == HASH_DataType_8b) || \ 133 | ((DATATYPE) == HASH_DataType_1b)) 134 | /** 135 | * @} 136 | */ 137 | 138 | /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode 139 | * @{ 140 | */ 141 | #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ 142 | #define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */ 143 | 144 | #define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ 145 | ((KEYTYPE) == HASH_HMACKeyType_LongKey)) 146 | /** 147 | * @} 148 | */ 149 | 150 | /** @defgroup Number_of_valid_bits_in_last_word_of_the_message 151 | * @{ 152 | */ 153 | #define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) 154 | 155 | /** 156 | * @} 157 | */ 158 | 159 | /** @defgroup HASH_interrupts_definition 160 | * @{ 161 | */ 162 | #define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */ 163 | #define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */ 164 | 165 | #define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000)) 166 | #define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) 167 | 168 | /** 169 | * @} 170 | */ 171 | 172 | /** @defgroup HASH_flags_definition 173 | * @{ 174 | */ 175 | #define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */ 176 | #define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ 177 | #define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ 178 | #define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */ 179 | #define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */ 180 | 181 | #define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ 182 | ((FLAG) == HASH_FLAG_DCIS) || \ 183 | ((FLAG) == HASH_FLAG_DMAS) || \ 184 | ((FLAG) == HASH_FLAG_BUSY) || \ 185 | ((FLAG) == HASH_FLAG_DINNE)) 186 | 187 | #define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ 188 | ((FLAG) == HASH_FLAG_DCIS)) 189 | 190 | /** 191 | * @} 192 | */ 193 | 194 | /** 195 | * @} 196 | */ 197 | 198 | /* Exported macro ------------------------------------------------------------*/ 199 | /* Exported functions --------------------------------------------------------*/ 200 | 201 | /* Function used to set the HASH configuration to the default reset state ****/ 202 | void HASH_DeInit(void); 203 | 204 | /* HASH Configuration function ************************************************/ 205 | void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); 206 | void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); 207 | void HASH_Reset(void); 208 | 209 | /* HASH Message Digest generation functions ***********************************/ 210 | void HASH_DataIn(uint32_t Data); 211 | uint8_t HASH_GetInFIFOWordsNbr(void); 212 | void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); 213 | void HASH_StartDigest(void); 214 | void HASH_AutoStartDigest(FunctionalState NewState); 215 | void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); 216 | 217 | /* HASH Context swapping functions ********************************************/ 218 | void HASH_SaveContext(HASH_Context* HASH_ContextSave); 219 | void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); 220 | 221 | /* HASH DMA interface function ************************************************/ 222 | void HASH_DMACmd(FunctionalState NewState); 223 | 224 | /* HASH Interrupts and flags management functions *****************************/ 225 | void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState); 226 | FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG); 227 | void HASH_ClearFlag(uint32_t HASH_FLAG); 228 | ITStatus HASH_GetITStatus(uint32_t HASH_IT); 229 | void HASH_ClearITPendingBit(uint32_t HASH_IT); 230 | 231 | /* High Level SHA1 functions **************************************************/ 232 | ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); 233 | ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, 234 | uint8_t *Input, uint32_t Ilen, 235 | uint8_t Output[20]); 236 | 237 | /* High Level MD5 functions ***************************************************/ 238 | ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); 239 | ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, 240 | uint8_t *Input, uint32_t Ilen, 241 | uint8_t Output[16]); 242 | 243 | #ifdef __cplusplus 244 | } 245 | #endif 246 | 247 | #endif /*__STM32F4xx_HASH_H */ 248 | 249 | /** 250 | * @} 251 | */ 252 | 253 | /** 254 | * @} 255 | */ 256 | 257 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 258 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_iwdg.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_IWDG_H 31 | #define __STM32F4xx_IWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup IWDG 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup IWDG_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** @defgroup IWDG_WriteAccess 56 | * @{ 57 | */ 58 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 59 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 61 | ((ACCESS) == IWDG_WriteAccess_Disable)) 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup IWDG_prescaler 67 | * @{ 68 | */ 69 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 70 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 71 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 72 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 73 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 74 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 75 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 76 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 77 | ((PRESCALER) == IWDG_Prescaler_8) || \ 78 | ((PRESCALER) == IWDG_Prescaler_16) || \ 79 | ((PRESCALER) == IWDG_Prescaler_32) || \ 80 | ((PRESCALER) == IWDG_Prescaler_64) || \ 81 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 82 | ((PRESCALER) == IWDG_Prescaler_256)) 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @defgroup IWDG_Flag 88 | * @{ 89 | */ 90 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 91 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 92 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) 93 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 94 | /** 95 | * @} 96 | */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /* Exported macro ------------------------------------------------------------*/ 103 | /* Exported functions --------------------------------------------------------*/ 104 | 105 | /* Prescaler and Counter configuration functions ******************************/ 106 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 107 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 108 | void IWDG_SetReload(uint16_t Reload); 109 | void IWDG_ReloadCounter(void); 110 | 111 | /* IWDG activation function ***************************************************/ 112 | void IWDG_Enable(void); 113 | 114 | /* Flag management function ***************************************************/ 115 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 116 | 117 | #ifdef __cplusplus 118 | } 119 | #endif 120 | 121 | #endif /* __STM32F4xx_IWDG_H */ 122 | 123 | /** 124 | * @} 125 | */ 126 | 127 | /** 128 | * @} 129 | */ 130 | 131 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 132 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __MISC_H 31 | #define __MISC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup MISC 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief NVIC Init Structure definition 52 | */ 53 | 54 | typedef struct 55 | { 56 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 57 | This parameter can be an enumerator of @ref IRQn_Type 58 | enumeration (For the complete STM32 Devices IRQ Channels 59 | list, please refer to stm32f4xx.h file) */ 60 | 61 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel 62 | specified in NVIC_IRQChannel. This parameter can be a value 63 | between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table 64 | A lower priority value indicates a higher priority */ 65 | 66 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified 67 | in NVIC_IRQChannel. This parameter can be a value 68 | between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table 69 | A lower priority value indicates a higher priority */ 70 | 71 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 72 | will be enabled or disabled. 73 | This parameter can be set either to ENABLE or DISABLE */ 74 | } NVIC_InitTypeDef; 75 | 76 | /* Exported constants --------------------------------------------------------*/ 77 | 78 | /** @defgroup MISC_Exported_Constants 79 | * @{ 80 | */ 81 | 82 | /** @defgroup MISC_Vector_Table_Base 83 | * @{ 84 | */ 85 | 86 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000) 87 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) 88 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ 89 | ((VECTTAB) == NVIC_VectTab_FLASH)) 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup MISC_System_Low_Power 95 | * @{ 96 | */ 97 | 98 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 99 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 100 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 101 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 102 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 103 | ((LP) == NVIC_LP_SLEEPONEXIT)) 104 | /** 105 | * @} 106 | */ 107 | 108 | /** @defgroup MISC_Preemption_Priority_Group 109 | * @{ 110 | */ 111 | 112 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 113 | 4 bits for subpriority */ 114 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 115 | 3 bits for subpriority */ 116 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 117 | 2 bits for subpriority */ 118 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 119 | 1 bits for subpriority */ 120 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 121 | 0 bits for subpriority */ 122 | 123 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 124 | ((GROUP) == NVIC_PriorityGroup_1) || \ 125 | ((GROUP) == NVIC_PriorityGroup_2) || \ 126 | ((GROUP) == NVIC_PriorityGroup_3) || \ 127 | ((GROUP) == NVIC_PriorityGroup_4)) 128 | 129 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 130 | 131 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 132 | 133 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) 134 | 135 | /** 136 | * @} 137 | */ 138 | 139 | /** @defgroup MISC_SysTick_clock_source 140 | * @{ 141 | */ 142 | 143 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 144 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 145 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 146 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 147 | /** 148 | * @} 149 | */ 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /* Exported macro ------------------------------------------------------------*/ 156 | /* Exported functions --------------------------------------------------------*/ 157 | 158 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 159 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 160 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); 161 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 162 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 163 | 164 | #ifdef __cplusplus 165 | } 166 | #endif 167 | 168 | #endif /* __MISC_H */ 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | /** 175 | * @} 176 | */ 177 | 178 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 179 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_pwr.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_PWR_H 31 | #define __STM32F4xx_PWR_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup PWR 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup PWR_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** @defgroup PWR_PVD_detection_level 56 | * @{ 57 | */ 58 | #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 59 | #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 60 | #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 61 | #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 62 | #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 63 | #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 64 | #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 65 | #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 66 | 67 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ 68 | ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ 69 | ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ 70 | ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) 71 | /** 72 | * @} 73 | */ 74 | 75 | 76 | /** @defgroup PWR_Regulator_state_in_STOP_mode 77 | * @{ 78 | */ 79 | #define PWR_MainRegulator_ON ((uint32_t)0x00000000) 80 | #define PWR_LowPowerRegulator_ON PWR_CR_LPDS 81 | 82 | /* --- PWR_Legacy ---*/ 83 | #define PWR_Regulator_ON PWR_MainRegulator_ON 84 | #define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON 85 | 86 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \ 87 | ((REGULATOR) == PWR_LowPowerRegulator_ON)) 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @defgroup PWR_Regulator_state_in_UnderDrive_mode 94 | * @{ 95 | */ 96 | #define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS 97 | #define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) 98 | 99 | #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \ 100 | ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON)) 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @defgroup PWR_STOP_mode_entry 107 | * @{ 108 | */ 109 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 110 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 111 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) 112 | /** 113 | * @} 114 | */ 115 | 116 | /** @defgroup PWR_Regulator_Voltage_Scale 117 | * @{ 118 | */ 119 | #define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000) 120 | #define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000) 121 | #define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000) 122 | #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \ 123 | ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \ 124 | ((VOLTAGE) == PWR_Regulator_Voltage_Scale3)) 125 | /** 126 | * @} 127 | */ 128 | 129 | /** @defgroup PWR_Flag 130 | * @{ 131 | */ 132 | #define PWR_FLAG_WU PWR_CSR_WUF 133 | #define PWR_FLAG_SB PWR_CSR_SBF 134 | #define PWR_FLAG_PVDO PWR_CSR_PVDO 135 | #define PWR_FLAG_BRR PWR_CSR_BRR 136 | #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY 137 | #define PWR_FLAG_ODRDY PWR_CSR_ODRDY 138 | #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY 139 | #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY 140 | 141 | /* --- FLAG Legacy ---*/ 142 | #define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY 143 | 144 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 145 | ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ 146 | ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \ 147 | ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY)) 148 | 149 | 150 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 151 | ((FLAG) == PWR_FLAG_UDRDY)) 152 | 153 | /** 154 | * @} 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /* Exported macro ------------------------------------------------------------*/ 162 | /* Exported functions --------------------------------------------------------*/ 163 | 164 | /* Function used to set the PWR configuration to the default reset state ******/ 165 | void PWR_DeInit(void); 166 | 167 | /* Backup Domain Access function **********************************************/ 168 | void PWR_BackupAccessCmd(FunctionalState NewState); 169 | 170 | /* PVD configuration functions ************************************************/ 171 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 172 | void PWR_PVDCmd(FunctionalState NewState); 173 | 174 | /* WakeUp pins configuration functions ****************************************/ 175 | void PWR_WakeUpPinCmd(FunctionalState NewState); 176 | 177 | /* Main and Backup Regulators configuration functions *************************/ 178 | void PWR_BackupRegulatorCmd(FunctionalState NewState); 179 | void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); 180 | void PWR_OverDriveCmd(FunctionalState NewState); 181 | void PWR_OverDriveSWCmd(FunctionalState NewState); 182 | void PWR_UnderDriveCmd(FunctionalState NewState); 183 | 184 | /* FLASH Power Down configuration functions ***********************************/ 185 | void PWR_FlashPowerDownCmd(FunctionalState NewState); 186 | 187 | /* Low Power modes configuration functions ************************************/ 188 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 189 | void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 190 | void PWR_EnterSTANDBYMode(void); 191 | 192 | /* Flags management functions *************************************************/ 193 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 194 | void PWR_ClearFlag(uint32_t PWR_FLAG); 195 | 196 | #ifdef __cplusplus 197 | } 198 | #endif 199 | 200 | #endif /* __STM32F4xx_PWR_H */ 201 | 202 | /** 203 | * @} 204 | */ 205 | 206 | /** 207 | * @} 208 | */ 209 | 210 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 211 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_rng.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the Random 8 | * Number Generator(RNG) firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_RNG_H 31 | #define __STM32F4xx_RNG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup RNG 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup RNG_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** @defgroup RNG_flags_definition 56 | * @{ 57 | */ 58 | #define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ 59 | #define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ 60 | #define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ 61 | 62 | #define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ 63 | ((RNG_FLAG) == RNG_FLAG_CECS) || \ 64 | ((RNG_FLAG) == RNG_FLAG_SECS)) 65 | #define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ 66 | ((RNG_FLAG) == RNG_FLAG_SECS)) 67 | /** 68 | * @} 69 | */ 70 | 71 | /** @defgroup RNG_interrupts_definition 72 | * @{ 73 | */ 74 | #define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ 75 | #define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ 76 | 77 | #define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) 78 | #define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) 79 | /** 80 | * @} 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /* Exported macro ------------------------------------------------------------*/ 88 | /* Exported functions --------------------------------------------------------*/ 89 | 90 | /* Function used to set the RNG configuration to the default reset state *****/ 91 | void RNG_DeInit(void); 92 | 93 | /* Configuration function *****************************************************/ 94 | void RNG_Cmd(FunctionalState NewState); 95 | 96 | /* Get 32 bit Random number function ******************************************/ 97 | uint32_t RNG_GetRandomNumber(void); 98 | 99 | /* Interrupts and flags management functions **********************************/ 100 | void RNG_ITConfig(FunctionalState NewState); 101 | FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); 102 | void RNG_ClearFlag(uint8_t RNG_FLAG); 103 | ITStatus RNG_GetITStatus(uint8_t RNG_IT); 104 | void RNG_ClearITPendingBit(uint8_t RNG_IT); 105 | 106 | #ifdef __cplusplus 107 | } 108 | #endif 109 | 110 | #endif /*__STM32F4xx_RNG_H */ 111 | 112 | /** 113 | * @} 114 | */ 115 | 116 | /** 117 | * @} 118 | */ 119 | 120 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 121 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_syscfg.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the SYSCFG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_SYSCFG_H 31 | #define __STM32F4xx_SYSCFG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup SYSCFG 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup SYSCFG_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** @defgroup SYSCFG_EXTI_Port_Sources 56 | * @{ 57 | */ 58 | #define EXTI_PortSourceGPIOA ((uint8_t)0x00) 59 | #define EXTI_PortSourceGPIOB ((uint8_t)0x01) 60 | #define EXTI_PortSourceGPIOC ((uint8_t)0x02) 61 | #define EXTI_PortSourceGPIOD ((uint8_t)0x03) 62 | #define EXTI_PortSourceGPIOE ((uint8_t)0x04) 63 | #define EXTI_PortSourceGPIOF ((uint8_t)0x05) 64 | #define EXTI_PortSourceGPIOG ((uint8_t)0x06) 65 | #define EXTI_PortSourceGPIOH ((uint8_t)0x07) 66 | #define EXTI_PortSourceGPIOI ((uint8_t)0x08) 67 | #define EXTI_PortSourceGPIOJ ((uint8_t)0x09) 68 | #define EXTI_PortSourceGPIOK ((uint8_t)0x0A) 69 | 70 | #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ 71 | ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ 72 | ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ 73 | ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ 74 | ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ 75 | ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ 76 | ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ 77 | ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ 78 | ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \ 79 | ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \ 80 | ((PORTSOURCE) == EXTI_PortSourceGPIOK)) 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | 87 | /** @defgroup SYSCFG_EXTI_Pin_Sources 88 | * @{ 89 | */ 90 | #define EXTI_PinSource0 ((uint8_t)0x00) 91 | #define EXTI_PinSource1 ((uint8_t)0x01) 92 | #define EXTI_PinSource2 ((uint8_t)0x02) 93 | #define EXTI_PinSource3 ((uint8_t)0x03) 94 | #define EXTI_PinSource4 ((uint8_t)0x04) 95 | #define EXTI_PinSource5 ((uint8_t)0x05) 96 | #define EXTI_PinSource6 ((uint8_t)0x06) 97 | #define EXTI_PinSource7 ((uint8_t)0x07) 98 | #define EXTI_PinSource8 ((uint8_t)0x08) 99 | #define EXTI_PinSource9 ((uint8_t)0x09) 100 | #define EXTI_PinSource10 ((uint8_t)0x0A) 101 | #define EXTI_PinSource11 ((uint8_t)0x0B) 102 | #define EXTI_PinSource12 ((uint8_t)0x0C) 103 | #define EXTI_PinSource13 ((uint8_t)0x0D) 104 | #define EXTI_PinSource14 ((uint8_t)0x0E) 105 | #define EXTI_PinSource15 ((uint8_t)0x0F) 106 | #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ 107 | ((PINSOURCE) == EXTI_PinSource1) || \ 108 | ((PINSOURCE) == EXTI_PinSource2) || \ 109 | ((PINSOURCE) == EXTI_PinSource3) || \ 110 | ((PINSOURCE) == EXTI_PinSource4) || \ 111 | ((PINSOURCE) == EXTI_PinSource5) || \ 112 | ((PINSOURCE) == EXTI_PinSource6) || \ 113 | ((PINSOURCE) == EXTI_PinSource7) || \ 114 | ((PINSOURCE) == EXTI_PinSource8) || \ 115 | ((PINSOURCE) == EXTI_PinSource9) || \ 116 | ((PINSOURCE) == EXTI_PinSource10) || \ 117 | ((PINSOURCE) == EXTI_PinSource11) || \ 118 | ((PINSOURCE) == EXTI_PinSource12) || \ 119 | ((PINSOURCE) == EXTI_PinSource13) || \ 120 | ((PINSOURCE) == EXTI_PinSource14) || \ 121 | ((PINSOURCE) == EXTI_PinSource15)) 122 | /** 123 | * @} 124 | */ 125 | 126 | 127 | /** @defgroup SYSCFG_Memory_Remap_Config 128 | * @{ 129 | */ 130 | #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) 131 | #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) 132 | #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) 133 | #define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04) 134 | 135 | #if defined (STM32F40_41xxx) 136 | #define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) 137 | #endif /* STM32F40_41xxx */ 138 | 139 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) 140 | #define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02) 141 | #endif /* STM32F427_437xx || STM32F429_439xx */ 142 | 143 | #if defined (STM32F40_41xxx) 144 | #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ 145 | ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ 146 | ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ 147 | ((REMAP) == SYSCFG_MemoryRemap_FSMC)) 148 | #endif /* STM32F40_41xxx */ 149 | 150 | #if defined (STM32F401xx) 151 | #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ 152 | ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ 153 | ((REMAP) == SYSCFG_MemoryRemap_SRAM)) 154 | #endif /* STM32F401xx */ 155 | 156 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) 157 | #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ 158 | ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ 159 | ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ 160 | ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \ 161 | ((REMAP) == SYSCFG_MemoryRemap_FMC)) 162 | #endif /* STM32F427_437xx || STM32F429_439xx */ 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | 169 | /** @defgroup SYSCFG_ETHERNET_Media_Interface 170 | * @{ 171 | */ 172 | #define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) 173 | #define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) 174 | 175 | #define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ 176 | ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) 177 | /** 178 | * @} 179 | */ 180 | 181 | /** 182 | * @} 183 | */ 184 | 185 | /* Exported macro ------------------------------------------------------------*/ 186 | /* Exported functions --------------------------------------------------------*/ 187 | 188 | void SYSCFG_DeInit(void); 189 | void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); 190 | void SYSCFG_MemorySwappingBank(FunctionalState NewState); 191 | void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); 192 | void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); 193 | void SYSCFG_CompensationCellCmd(FunctionalState NewState); 194 | FlagStatus SYSCFG_GetCompensationCellStatus(void); 195 | 196 | #ifdef __cplusplus 197 | } 198 | #endif 199 | 200 | #endif /*__STM32F4xx_SYSCFG_H */ 201 | 202 | /** 203 | * @} 204 | */ 205 | 206 | /** 207 | * @} 208 | */ 209 | 210 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 211 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_wwdg.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file contains all the functions prototypes for the WWDG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F4xx_WWDG_H 31 | #define __STM32F4xx_WWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup WWDG 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup WWDG_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** @defgroup WWDG_Prescaler 56 | * @{ 57 | */ 58 | 59 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 60 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 61 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 62 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 63 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 64 | ((PRESCALER) == WWDG_Prescaler_2) || \ 65 | ((PRESCALER) == WWDG_Prescaler_4) || \ 66 | ((PRESCALER) == WWDG_Prescaler_8)) 67 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 68 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** 75 | * @} 76 | */ 77 | 78 | /* Exported macro ------------------------------------------------------------*/ 79 | /* Exported functions --------------------------------------------------------*/ 80 | 81 | /* Function used to set the WWDG configuration to the default reset state ****/ 82 | void WWDG_DeInit(void); 83 | 84 | /* Prescaler, Refresh window and Counter configuration functions **************/ 85 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 86 | void WWDG_SetWindowValue(uint8_t WindowValue); 87 | void WWDG_EnableIT(void); 88 | void WWDG_SetCounter(uint8_t Counter); 89 | 90 | /* WWDG activation function ***************************************************/ 91 | void WWDG_Enable(uint8_t Counter); 92 | 93 | /* Interrupts and flags management functions **********************************/ 94 | FlagStatus WWDG_GetFlagStatus(void); 95 | void WWDG_ClearFlag(void); 96 | 97 | #ifdef __cplusplus 98 | } 99 | #endif 100 | 101 | #endif /* __STM32F4xx_WWDG_H */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 112 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_crc.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file provides all the CRC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2013 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f4xx_crc.h" 30 | 31 | /** @addtogroup STM32F4xx_StdPeriph_Driver 32 | * @{ 33 | */ 34 | 35 | /** @defgroup CRC 36 | * @brief CRC driver modules 37 | * @{ 38 | */ 39 | 40 | /* Private typedef -----------------------------------------------------------*/ 41 | /* Private define ------------------------------------------------------------*/ 42 | /* Private macro -------------------------------------------------------------*/ 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* Private function prototypes -----------------------------------------------*/ 45 | /* Private functions ---------------------------------------------------------*/ 46 | 47 | /** @defgroup CRC_Private_Functions 48 | * @{ 49 | */ 50 | 51 | /** 52 | * @brief Resets the CRC Data register (DR). 53 | * @param None 54 | * @retval None 55 | */ 56 | void CRC_ResetDR(void) 57 | { 58 | /* Reset CRC generator */ 59 | CRC->CR = CRC_CR_RESET; 60 | } 61 | 62 | /** 63 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 64 | * @param Data: data word(32-bit) to compute its CRC 65 | * @retval 32-bit CRC 66 | */ 67 | uint32_t CRC_CalcCRC(uint32_t Data) 68 | { 69 | CRC->DR = Data; 70 | 71 | return (CRC->DR); 72 | } 73 | 74 | /** 75 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 76 | * @param pBuffer: pointer to the buffer containing the data to be computed 77 | * @param BufferLength: length of the buffer to be computed 78 | * @retval 32-bit CRC 79 | */ 80 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 81 | { 82 | uint32_t index = 0; 83 | 84 | for(index = 0; index < BufferLength; index++) 85 | { 86 | CRC->DR = pBuffer[index]; 87 | } 88 | return (CRC->DR); 89 | } 90 | 91 | /** 92 | * @brief Returns the current CRC value. 93 | * @param None 94 | * @retval 32-bit CRC 95 | */ 96 | uint32_t CRC_GetCRC(void) 97 | { 98 | return (CRC->DR); 99 | } 100 | 101 | /** 102 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 103 | * @param IDValue: 8-bit value to be stored in the ID register 104 | * @retval None 105 | */ 106 | void CRC_SetIDRegister(uint8_t IDValue) 107 | { 108 | CRC->IDR = IDValue; 109 | } 110 | 111 | /** 112 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 113 | * @param None 114 | * @retval 8-bit value of the ID register 115 | */ 116 | uint8_t CRC_GetIDRegister(void) 117 | { 118 | return (CRC->IDR); 119 | } 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | /** 126 | * @} 127 | */ 128 | 129 | /** 130 | * @} 131 | */ 132 | 133 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 134 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_cryp_des.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file provides high level functions to encrypt and decrypt an 8 | * input message using DES in ECB/CBC modes. 9 | * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP 10 | * peripheral. 11 | * 12 | @verbatim 13 | 14 | =================================================================== 15 | ##### How to use this driver ##### 16 | =================================================================== 17 | [..] 18 | (#) Enable The CRYP controller clock using 19 | RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. 20 | 21 | (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function. 22 | 23 | (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function. 24 | 25 | @endverbatim 26 | * 27 | ****************************************************************************** 28 | * @attention 29 | * 30 | *

© COPYRIGHT 2013 STMicroelectronics

31 | * 32 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 33 | * You may not use this file except in compliance with the License. 34 | * You may obtain a copy of the License at: 35 | * 36 | * http://www.st.com/software_license_agreement_liberty_v2 37 | * 38 | * Unless required by applicable law or agreed to in writing, software 39 | * distributed under the License is distributed on an "AS IS" BASIS, 40 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | * See the License for the specific language governing permissions and 42 | * limitations under the License. 43 | * 44 | ****************************************************************************** 45 | */ 46 | 47 | /* Includes ------------------------------------------------------------------*/ 48 | #include "stm32f4xx_cryp.h" 49 | 50 | 51 | /** @addtogroup STM32F4xx_StdPeriph_Driver 52 | * @{ 53 | */ 54 | 55 | /** @defgroup CRYP 56 | * @brief CRYP driver modules 57 | * @{ 58 | */ 59 | 60 | /* Private typedef -----------------------------------------------------------*/ 61 | /* Private define ------------------------------------------------------------*/ 62 | #define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) 63 | 64 | /* Private macro -------------------------------------------------------------*/ 65 | /* Private variables ---------------------------------------------------------*/ 66 | /* Private function prototypes -----------------------------------------------*/ 67 | /* Private functions ---------------------------------------------------------*/ 68 | 69 | 70 | /** @defgroup CRYP_Private_Functions 71 | * @{ 72 | */ 73 | 74 | /** @defgroup CRYP_Group8 High Level DES functions 75 | * @brief High Level DES functions 76 | * 77 | @verbatim 78 | =============================================================================== 79 | ##### High Level DES functions ##### 80 | =============================================================================== 81 | @endverbatim 82 | * @{ 83 | */ 84 | 85 | /** 86 | * @brief Encrypt and decrypt using DES in ECB Mode 87 | * @param Mode: encryption or decryption Mode. 88 | * This parameter can be one of the following values: 89 | * @arg MODE_ENCRYPT: Encryption 90 | * @arg MODE_DECRYPT: Decryption 91 | * @param Key: Key used for DES algorithm. 92 | * @param Ilength: length of the Input buffer, must be a multiple of 8. 93 | * @param Input: pointer to the Input buffer. 94 | * @param Output: pointer to the returned buffer. 95 | * @retval An ErrorStatus enumeration value: 96 | * - SUCCESS: Operation done 97 | * - ERROR: Operation failed 98 | */ 99 | ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, 100 | uint32_t Ilength, uint8_t *Output) 101 | { 102 | CRYP_InitTypeDef DES_CRYP_InitStructure; 103 | CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; 104 | __IO uint32_t counter = 0; 105 | uint32_t busystatus = 0; 106 | ErrorStatus status = SUCCESS; 107 | uint32_t keyaddr = (uint32_t)Key; 108 | uint32_t inputaddr = (uint32_t)Input; 109 | uint32_t outputaddr = (uint32_t)Output; 110 | uint32_t i = 0; 111 | 112 | /* Crypto structures initialisation*/ 113 | CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); 114 | 115 | /* Crypto Init for Encryption process */ 116 | if( Mode == MODE_ENCRYPT ) /* DES encryption */ 117 | { 118 | DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; 119 | } 120 | else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ 121 | { 122 | DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; 123 | } 124 | 125 | DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; 126 | DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; 127 | CRYP_Init(&DES_CRYP_InitStructure); 128 | 129 | /* Key Initialisation */ 130 | DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); 131 | keyaddr+=4; 132 | DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); 133 | CRYP_KeyInit(& DES_CRYP_KeyInitStructure); 134 | 135 | /* Flush IN/OUT FIFO */ 136 | CRYP_FIFOFlush(); 137 | 138 | /* Enable Crypto processor */ 139 | CRYP_Cmd(ENABLE); 140 | 141 | if(CRYP_GetCmdStatus() == DISABLE) 142 | { 143 | /* The CRYP peripheral clock is not enabled or the device doesn't embedd 144 | the CRYP peripheral (please check the device sales type. */ 145 | return(ERROR); 146 | } 147 | for(i=0; ((i
© COPYRIGHT 2013 STMicroelectronics
12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f4xx_dbgmcu.h" 30 | 31 | /** @addtogroup STM32F4xx_StdPeriph_Driver 32 | * @{ 33 | */ 34 | 35 | /** @defgroup DBGMCU 36 | * @brief DBGMCU driver modules 37 | * @{ 38 | */ 39 | 40 | /* Private typedef -----------------------------------------------------------*/ 41 | /* Private define ------------------------------------------------------------*/ 42 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) 43 | 44 | /* Private macro -------------------------------------------------------------*/ 45 | /* Private variables ---------------------------------------------------------*/ 46 | /* Private function prototypes -----------------------------------------------*/ 47 | /* Private functions ---------------------------------------------------------*/ 48 | 49 | /** @defgroup DBGMCU_Private_Functions 50 | * @{ 51 | */ 52 | 53 | /** 54 | * @brief Returns the device revision identifier. 55 | * @param None 56 | * @retval Device revision identifier 57 | */ 58 | uint32_t DBGMCU_GetREVID(void) 59 | { 60 | return(DBGMCU->IDCODE >> 16); 61 | } 62 | 63 | /** 64 | * @brief Returns the device identifier. 65 | * @param None 66 | * @retval Device identifier 67 | */ 68 | uint32_t DBGMCU_GetDEVID(void) 69 | { 70 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); 71 | } 72 | 73 | /** 74 | * @brief Configures low power mode behavior when the MCU is in Debug mode. 75 | * @param DBGMCU_Periph: specifies the low power mode. 76 | * This parameter can be any combination of the following values: 77 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode 78 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 79 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 80 | * @param NewState: new state of the specified low power mode in Debug mode. 81 | * This parameter can be: ENABLE or DISABLE. 82 | * @retval None 83 | */ 84 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 85 | { 86 | /* Check the parameters */ 87 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 88 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 89 | if (NewState != DISABLE) 90 | { 91 | DBGMCU->CR |= DBGMCU_Periph; 92 | } 93 | else 94 | { 95 | DBGMCU->CR &= ~DBGMCU_Periph; 96 | } 97 | } 98 | 99 | /** 100 | * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. 101 | * @param DBGMCU_Periph: specifies the APB1 peripheral. 102 | * This parameter can be any combination of the following values: 103 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted 104 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 105 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted 106 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted 107 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 108 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted 109 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted 110 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted 111 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 112 | * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. 113 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 114 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 115 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted 116 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted 117 | * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted 118 | * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted 119 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted 120 | * This parameter can be: ENABLE or DISABLE. 121 | * @retval None 122 | */ 123 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) 124 | { 125 | /* Check the parameters */ 126 | assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); 127 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 128 | 129 | if (NewState != DISABLE) 130 | { 131 | DBGMCU->APB1FZ |= DBGMCU_Periph; 132 | } 133 | else 134 | { 135 | DBGMCU->APB1FZ &= ~DBGMCU_Periph; 136 | } 137 | } 138 | 139 | /** 140 | * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. 141 | * @param DBGMCU_Periph: specifies the APB2 peripheral. 142 | * This parameter can be any combination of the following values: 143 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 144 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted 145 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted 146 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted 147 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted 148 | * @param NewState: new state of the specified peripheral in Debug mode. 149 | * This parameter can be: ENABLE or DISABLE. 150 | * @retval None 151 | */ 152 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) 153 | { 154 | /* Check the parameters */ 155 | assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); 156 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 157 | 158 | if (NewState != DISABLE) 159 | { 160 | DBGMCU->APB2FZ |= DBGMCU_Periph; 161 | } 162 | else 163 | { 164 | DBGMCU->APB2FZ &= ~DBGMCU_Periph; 165 | } 166 | } 167 | 168 | /** 169 | * @} 170 | */ 171 | 172 | /** 173 | * @} 174 | */ 175 | 176 | /** 177 | * @} 178 | */ 179 | 180 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 181 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hash_md5.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file provides high level functions to compute the HASH MD5 and 8 | * HMAC MD5 Digest of an input message. 9 | * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH 10 | * peripheral. 11 | * 12 | @verbatim 13 | =================================================================== 14 | ##### How to use this driver ##### 15 | =================================================================== 16 | [..] 17 | (#) Enable The HASH controller clock using 18 | RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. 19 | 20 | (#) Calculate the HASH MD5 Digest using HASH_MD5() function. 21 | 22 | (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function. 23 | 24 | @endverbatim 25 | * 26 | ****************************************************************************** 27 | * @attention 28 | * 29 | *

© COPYRIGHT 2013 STMicroelectronics

30 | * 31 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 32 | * You may not use this file except in compliance with the License. 33 | * You may obtain a copy of the License at: 34 | * 35 | * http://www.st.com/software_license_agreement_liberty_v2 36 | * 37 | * Unless required by applicable law or agreed to in writing, software 38 | * distributed under the License is distributed on an "AS IS" BASIS, 39 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | * See the License for the specific language governing permissions and 41 | * limitations under the License. 42 | * 43 | ****************************************************************************** 44 | */ 45 | 46 | /* Includes ------------------------------------------------------------------*/ 47 | #include "stm32f4xx_hash.h" 48 | 49 | /** @addtogroup STM32F4xx_StdPeriph_Driver 50 | * @{ 51 | */ 52 | 53 | /** @defgroup HASH 54 | * @brief HASH driver modules 55 | * @{ 56 | */ 57 | 58 | /* Private typedef -----------------------------------------------------------*/ 59 | /* Private define ------------------------------------------------------------*/ 60 | #define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) 61 | 62 | /* Private macro -------------------------------------------------------------*/ 63 | /* Private variables ---------------------------------------------------------*/ 64 | /* Private function prototypes -----------------------------------------------*/ 65 | /* Private functions ---------------------------------------------------------*/ 66 | 67 | /** @defgroup HASH_Private_Functions 68 | * @{ 69 | */ 70 | 71 | /** @defgroup HASH_Group7 High Level MD5 functions 72 | * @brief High Level MD5 Hash and HMAC functions 73 | * 74 | @verbatim 75 | =============================================================================== 76 | ##### High Level MD5 Hash and HMAC functions ##### 77 | =============================================================================== 78 | 79 | 80 | @endverbatim 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @brief Compute the HASH MD5 digest. 86 | * @param Input: pointer to the Input buffer to be treated. 87 | * @param Ilen: length of the Input buffer. 88 | * @param Output: the returned digest 89 | * @retval An ErrorStatus enumeration value: 90 | * - SUCCESS: digest computation done 91 | * - ERROR: digest computation failed 92 | */ 93 | ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) 94 | { 95 | HASH_InitTypeDef MD5_HASH_InitStructure; 96 | HASH_MsgDigest MD5_MessageDigest; 97 | __IO uint16_t nbvalidbitsdata = 0; 98 | uint32_t i = 0; 99 | __IO uint32_t counter = 0; 100 | uint32_t busystatus = 0; 101 | ErrorStatus status = SUCCESS; 102 | uint32_t inputaddr = (uint32_t)Input; 103 | uint32_t outputaddr = (uint32_t)Output; 104 | 105 | 106 | /* Number of valid bits in last word of the Input data */ 107 | nbvalidbitsdata = 8 * (Ilen % 4); 108 | 109 | /* HASH peripheral initialization */ 110 | HASH_DeInit(); 111 | 112 | /* HASH Configuration */ 113 | MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; 114 | MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; 115 | MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; 116 | HASH_Init(&MD5_HASH_InitStructure); 117 | 118 | /* Configure the number of valid bits in last word of the data */ 119 | HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); 120 | 121 | /* Write the Input block in the IN FIFO */ 122 | for(i=0; i 64) 197 | { 198 | /* HMAC long Key */ 199 | MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; 200 | } 201 | else 202 | { 203 | /* HMAC short Key */ 204 | MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; 205 | } 206 | HASH_Init(&MD5_HASH_InitStructure); 207 | 208 | /* Configure the number of valid bits in last word of the Key */ 209 | HASH_SetLastWordValidBitsNbr(nbvalidbitskey); 210 | 211 | /* Write the Key */ 212 | for(i=0; i
© COPYRIGHT 2013 STMicroelectronics
30 | * 31 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 32 | * You may not use this file except in compliance with the License. 33 | * You may obtain a copy of the License at: 34 | * 35 | * http://www.st.com/software_license_agreement_liberty_v2 36 | * 37 | * Unless required by applicable law or agreed to in writing, software 38 | * distributed under the License is distributed on an "AS IS" BASIS, 39 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | * See the License for the specific language governing permissions and 41 | * limitations under the License. 42 | * 43 | ****************************************************************************** 44 | */ 45 | 46 | /* Includes ------------------------------------------------------------------*/ 47 | #include "stm32f4xx_hash.h" 48 | 49 | /** @addtogroup STM32F4xx_StdPeriph_Driver 50 | * @{ 51 | */ 52 | 53 | /** @defgroup HASH 54 | * @brief HASH driver modules 55 | * @{ 56 | */ 57 | 58 | /* Private typedef -----------------------------------------------------------*/ 59 | /* Private define ------------------------------------------------------------*/ 60 | #define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) 61 | 62 | /* Private macro -------------------------------------------------------------*/ 63 | /* Private variables ---------------------------------------------------------*/ 64 | /* Private function prototypes -----------------------------------------------*/ 65 | /* Private functions ---------------------------------------------------------*/ 66 | 67 | /** @defgroup HASH_Private_Functions 68 | * @{ 69 | */ 70 | 71 | /** @defgroup HASH_Group6 High Level SHA1 functions 72 | * @brief High Level SHA1 Hash and HMAC functions 73 | * 74 | @verbatim 75 | =============================================================================== 76 | ##### High Level SHA1 Hash and HMAC functions ##### 77 | =============================================================================== 78 | 79 | 80 | @endverbatim 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @brief Compute the HASH SHA1 digest. 86 | * @param Input: pointer to the Input buffer to be treated. 87 | * @param Ilen: length of the Input buffer. 88 | * @param Output: the returned digest 89 | * @retval An ErrorStatus enumeration value: 90 | * - SUCCESS: digest computation done 91 | * - ERROR: digest computation failed 92 | */ 93 | ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) 94 | { 95 | HASH_InitTypeDef SHA1_HASH_InitStructure; 96 | HASH_MsgDigest SHA1_MessageDigest; 97 | __IO uint16_t nbvalidbitsdata = 0; 98 | uint32_t i = 0; 99 | __IO uint32_t counter = 0; 100 | uint32_t busystatus = 0; 101 | ErrorStatus status = SUCCESS; 102 | uint32_t inputaddr = (uint32_t)Input; 103 | uint32_t outputaddr = (uint32_t)Output; 104 | 105 | /* Number of valid bits in last word of the Input data */ 106 | nbvalidbitsdata = 8 * (Ilen % 4); 107 | 108 | /* HASH peripheral initialization */ 109 | HASH_DeInit(); 110 | 111 | /* HASH Configuration */ 112 | SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; 113 | SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; 114 | SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; 115 | HASH_Init(&SHA1_HASH_InitStructure); 116 | 117 | /* Configure the number of valid bits in last word of the data */ 118 | HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); 119 | 120 | /* Write the Input block in the IN FIFO */ 121 | for(i=0; i 64) 198 | { 199 | /* HMAC long Key */ 200 | SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; 201 | } 202 | else 203 | { 204 | /* HMAC short Key */ 205 | SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; 206 | } 207 | HASH_Init(&SHA1_HASH_InitStructure); 208 | 209 | /* Configure the number of valid bits in last word of the Key */ 210 | HASH_SetLastWordValidBitsNbr(nbvalidbitskey); 211 | 212 | /* Write the Key */ 213 | for(i=0; i
© COPYRIGHT 2013 STMicroelectronics
68 | * 69 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 70 | * You may not use this file except in compliance with the License. 71 | * You may obtain a copy of the License at: 72 | * 73 | * http://www.st.com/software_license_agreement_liberty_v2 74 | * 75 | * Unless required by applicable law or agreed to in writing, software 76 | * distributed under the License is distributed on an "AS IS" BASIS, 77 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 78 | * See the License for the specific language governing permissions and 79 | * limitations under the License. 80 | * 81 | ****************************************************************************** 82 | */ 83 | 84 | /* Includes ------------------------------------------------------------------*/ 85 | #include "stm32f4xx_iwdg.h" 86 | 87 | /** @addtogroup STM32F4xx_StdPeriph_Driver 88 | * @{ 89 | */ 90 | 91 | /** @defgroup IWDG 92 | * @brief IWDG driver modules 93 | * @{ 94 | */ 95 | 96 | /* Private typedef -----------------------------------------------------------*/ 97 | /* Private define ------------------------------------------------------------*/ 98 | 99 | /* KR register bit mask */ 100 | #define KR_KEY_RELOAD ((uint16_t)0xAAAA) 101 | #define KR_KEY_ENABLE ((uint16_t)0xCCCC) 102 | 103 | /* Private macro -------------------------------------------------------------*/ 104 | /* Private variables ---------------------------------------------------------*/ 105 | /* Private function prototypes -----------------------------------------------*/ 106 | /* Private functions ---------------------------------------------------------*/ 107 | 108 | /** @defgroup IWDG_Private_Functions 109 | * @{ 110 | */ 111 | 112 | /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions 113 | * @brief Prescaler and Counter configuration functions 114 | * 115 | @verbatim 116 | =============================================================================== 117 | ##### Prescaler and Counter configuration functions ##### 118 | =============================================================================== 119 | 120 | @endverbatim 121 | * @{ 122 | */ 123 | 124 | /** 125 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 126 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 127 | * This parameter can be one of the following values: 128 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 129 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 130 | * @retval None 131 | */ 132 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 133 | { 134 | /* Check the parameters */ 135 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 136 | IWDG->KR = IWDG_WriteAccess; 137 | } 138 | 139 | /** 140 | * @brief Sets IWDG Prescaler value. 141 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 142 | * This parameter can be one of the following values: 143 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 144 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 145 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 146 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 147 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 148 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 149 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 150 | * @retval None 151 | */ 152 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 153 | { 154 | /* Check the parameters */ 155 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 156 | IWDG->PR = IWDG_Prescaler; 157 | } 158 | 159 | /** 160 | * @brief Sets IWDG Reload value. 161 | * @param Reload: specifies the IWDG Reload value. 162 | * This parameter must be a number between 0 and 0x0FFF. 163 | * @retval None 164 | */ 165 | void IWDG_SetReload(uint16_t Reload) 166 | { 167 | /* Check the parameters */ 168 | assert_param(IS_IWDG_RELOAD(Reload)); 169 | IWDG->RLR = Reload; 170 | } 171 | 172 | /** 173 | * @brief Reloads IWDG counter with value defined in the reload register 174 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 175 | * @param None 176 | * @retval None 177 | */ 178 | void IWDG_ReloadCounter(void) 179 | { 180 | IWDG->KR = KR_KEY_RELOAD; 181 | } 182 | 183 | /** 184 | * @} 185 | */ 186 | 187 | /** @defgroup IWDG_Group2 IWDG activation function 188 | * @brief IWDG activation function 189 | * 190 | @verbatim 191 | =============================================================================== 192 | ##### IWDG activation function ##### 193 | =============================================================================== 194 | 195 | @endverbatim 196 | * @{ 197 | */ 198 | 199 | /** 200 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 201 | * @param None 202 | * @retval None 203 | */ 204 | void IWDG_Enable(void) 205 | { 206 | IWDG->KR = KR_KEY_ENABLE; 207 | } 208 | 209 | /** 210 | * @} 211 | */ 212 | 213 | /** @defgroup IWDG_Group3 Flag management function 214 | * @brief Flag management function 215 | * 216 | @verbatim 217 | =============================================================================== 218 | ##### Flag management function ##### 219 | =============================================================================== 220 | 221 | @endverbatim 222 | * @{ 223 | */ 224 | 225 | /** 226 | * @brief Checks whether the specified IWDG flag is set or not. 227 | * @param IWDG_FLAG: specifies the flag to check. 228 | * This parameter can be one of the following values: 229 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 230 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 231 | * @retval The new state of IWDG_FLAG (SET or RESET). 232 | */ 233 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 234 | { 235 | FlagStatus bitstatus = RESET; 236 | /* Check the parameters */ 237 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 238 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 239 | { 240 | bitstatus = SET; 241 | } 242 | else 243 | { 244 | bitstatus = RESET; 245 | } 246 | /* Return the flag status */ 247 | return bitstatus; 248 | } 249 | 250 | /** 251 | * @} 252 | */ 253 | 254 | /** 255 | * @} 256 | */ 257 | 258 | /** 259 | * @} 260 | */ 261 | 262 | /** 263 | * @} 264 | */ 265 | 266 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 267 | -------------------------------------------------------------------------------- /lib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_syscfg.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 08-November-2013 7 | * @brief This file provides firmware functions to manage the SYSCFG peripheral. 8 | * 9 | @verbatim 10 | 11 | =============================================================================== 12 | ##### How to use this driver ##### 13 | =============================================================================== 14 | [..] This driver provides functions for: 15 | 16 | (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() 17 | 18 | (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for 19 | STM32F42xxx/43xxx devices Devices. 20 | 21 | (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() 22 | 23 | (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() 24 | 25 | -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers, 26 | using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); 27 | 28 | @endverbatim 29 | ****************************************************************************** 30 | * @attention 31 | * 32 | *

© COPYRIGHT 2013 STMicroelectronics

33 | * 34 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 35 | * You may not use this file except in compliance with the License. 36 | * You may obtain a copy of the License at: 37 | * 38 | * http://www.st.com/software_license_agreement_liberty_v2 39 | * 40 | * Unless required by applicable law or agreed to in writing, software 41 | * distributed under the License is distributed on an "AS IS" BASIS, 42 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 43 | * See the License for the specific language governing permissions and 44 | * limitations under the License. 45 | * 46 | ****************************************************************************** 47 | */ 48 | 49 | /* Includes ------------------------------------------------------------------*/ 50 | #include "stm32f4xx_syscfg.h" 51 | #include "stm32f4xx_rcc.h" 52 | 53 | /** @addtogroup STM32F4xx_StdPeriph_Driver 54 | * @{ 55 | */ 56 | 57 | /** @defgroup SYSCFG 58 | * @brief SYSCFG driver modules 59 | * @{ 60 | */ 61 | 62 | /* Private typedef -----------------------------------------------------------*/ 63 | /* Private define ------------------------------------------------------------*/ 64 | /* ------------ RCC registers bit address in the alias region ----------- */ 65 | #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) 66 | /* --- MEMRMP Register ---*/ 67 | /* Alias word address of UFB_MODE bit */ 68 | #define MEMRMP_OFFSET SYSCFG_OFFSET 69 | #define UFB_MODE_BitNumber ((uint8_t)0x8) 70 | #define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) 71 | 72 | 73 | /* --- PMC Register ---*/ 74 | /* Alias word address of MII_RMII_SEL bit */ 75 | #define PMC_OFFSET (SYSCFG_OFFSET + 0x04) 76 | #define MII_RMII_SEL_BitNumber ((uint8_t)0x17) 77 | #define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) 78 | 79 | /* --- CMPCR Register ---*/ 80 | /* Alias word address of CMP_PD bit */ 81 | #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) 82 | #define CMP_PD_BitNumber ((uint8_t)0x00) 83 | #define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) 84 | 85 | /* Private macro -------------------------------------------------------------*/ 86 | /* Private variables ---------------------------------------------------------*/ 87 | /* Private function prototypes -----------------------------------------------*/ 88 | /* Private functions ---------------------------------------------------------*/ 89 | 90 | /** @defgroup SYSCFG_Private_Functions 91 | * @{ 92 | */ 93 | 94 | /** 95 | * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) 96 | * registers to their default reset values. 97 | * @param None 98 | * @retval None 99 | */ 100 | void SYSCFG_DeInit(void) 101 | { 102 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); 103 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); 104 | } 105 | 106 | /** 107 | * @brief Changes the mapping of the specified pin. 108 | * @param SYSCFG_Memory: selects the memory remapping. 109 | * This parameter can be one of the following values: 110 | * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 111 | * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 112 | * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices. 113 | * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices. 114 | * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 115 | * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices. 116 | * @retval None 117 | */ 118 | void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) 119 | { 120 | /* Check the parameters */ 121 | assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); 122 | 123 | SYSCFG->MEMRMP = SYSCFG_MemoryRemap; 124 | } 125 | 126 | /** 127 | * @brief Enables or disables the Interal FLASH Bank Swapping. 128 | * 129 | * @note This function can be used only for STM32F42xxx/43xxx devices. 130 | * 131 | * @param NewState: new state of Interal FLASH Bank swapping. 132 | * This parameter can be one of the following values: 133 | * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 134 | * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) 135 | * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) 136 | and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) 137 | * @retval None 138 | */ 139 | void SYSCFG_MemorySwappingBank(FunctionalState NewState) 140 | { 141 | /* Check the parameters */ 142 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 143 | 144 | *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState; 145 | } 146 | 147 | /** 148 | * @brief Selects the GPIO pin used as EXTI Line. 149 | * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for 150 | * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) 151 | * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) 152 | * for STM32401xx devices. 153 | * 154 | * @param EXTI_PinSourcex: specifies the EXTI line to be configured. 155 | * This parameter can be EXTI_PinSourcex where x can be (0..15, except 156 | * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx 157 | * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can 158 | * be (0..7) for STM32F42xxx/43xxx devices. 159 | * 160 | * @retval None 161 | */ 162 | void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) 163 | { 164 | uint32_t tmp = 0x00; 165 | 166 | /* Check the parameters */ 167 | assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); 168 | assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); 169 | 170 | tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); 171 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; 172 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); 173 | } 174 | 175 | /** 176 | * @brief Selects the ETHERNET media interface 177 | * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. 178 | * This parameter can be one of the following values: 179 | * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected 180 | * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected 181 | * @retval None 182 | */ 183 | void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) 184 | { 185 | assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); 186 | /* Configure MII_RMII selection bit */ 187 | *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; 188 | } 189 | 190 | /** 191 | * @brief Enables or disables the I/O Compensation Cell. 192 | * @note The I/O compensation cell can be used only when the device supply 193 | * voltage ranges from 2.4 to 3.6 V. 194 | * @param NewState: new state of the I/O Compensation Cell. 195 | * This parameter can be one of the following values: 196 | * @arg ENABLE: I/O compensation cell enabled 197 | * @arg DISABLE: I/O compensation cell power-down mode 198 | * @retval None 199 | */ 200 | void SYSCFG_CompensationCellCmd(FunctionalState NewState) 201 | { 202 | /* Check the parameters */ 203 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 204 | 205 | *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; 206 | } 207 | 208 | /** 209 | * @brief Checks whether the I/O Compensation Cell ready flag is set or not. 210 | * @param None 211 | * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) 212 | */ 213 | FlagStatus SYSCFG_GetCompensationCellStatus(void) 214 | { 215 | FlagStatus bitstatus = RESET; 216 | 217 | if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) 218 | { 219 | bitstatus = SET; 220 | } 221 | else 222 | { 223 | bitstatus = RESET; 224 | } 225 | return bitstatus; 226 | } 227 | 228 | /** 229 | * @} 230 | */ 231 | 232 | /** 233 | * @} 234 | */ 235 | 236 | /** 237 | * @} 238 | */ 239 | 240 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 241 | -------------------------------------------------------------------------------- /lib/STM32_CPAL_Driver/inc/cpal_i2c.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bitcraze/crazyflie2-stm-bootloader/c79feab3e232d90f5de00f59542280fd559ee743/lib/STM32_CPAL_Driver/inc/cpal_i2c.h -------------------------------------------------------------------------------- /lib/STM32_CPAL_Driver/src/cpal_hal.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file STM32_CPAL_Driver/src/cpal_hal.c 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 21-December-2012 7 | * @brief This file contains all the functions for the CPAL_HAL common 8 | * firmware layer. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2012 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | /* If STM32F10X family is used */ 31 | #if defined (STM32F10X_LD) || defined (STM32F10X_LD_VL) || defined (STM32F10X_MD) || defined (STM32F10X_MD_VL)\ 32 | || defined (STM32F10X_HD) || defined (STM32F10X_HD_VL) || defined (STM32F10X_XL) || defined (STM32F10X_CL) 33 | #include "stm32f10x.h" 34 | #endif 35 | 36 | /* If STM32L1XX family is used */ 37 | #if defined (STM32L1XX_MD) || defined (STM32L1XX_HD) 38 | #include "stm32l1xx.h" 39 | #endif 40 | 41 | /* If STM32F2XX family is used */ 42 | #ifdef STM32F2XX 43 | #include "stm32f2xx.h" 44 | #endif 45 | 46 | /* If STM32F4XX family is used */ 47 | #ifdef STM32F4XX 48 | #include "stm32f4xx.h" 49 | #endif 50 | 51 | #include "stm32f4xx_misc.h" 52 | #include "cpal.h" 53 | 54 | /* Private typedef -----------------------------------------------------------*/ 55 | /* Private defines -----------------------------------------------------------*/ 56 | /* Private macro -------------------------------------------------------------*/ 57 | /* Private variables ---------------------------------------------------------*/ 58 | /* Private function prototypes -----------------------------------------------*/ 59 | 60 | 61 | /* Private functions ---------------------------------------------------------*/ 62 | 63 | /** 64 | * @brief Configure NVIC Priority Group. 65 | * @param None. 66 | * @retval None. 67 | */ 68 | void CPAL_HAL_NVICInit(void) 69 | { 70 | /* Set NVIC Group Priority */ 71 | NVIC_PriorityGroupConfig (CPAL_NVIC_PRIOGROUP); 72 | } 73 | 74 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 75 | -------------------------------------------------------------------------------- /lib/STM32_CPAL_Driver/src/cpal_usercallback_template.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file cpal_usercallback_template.c 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 21-December-2012 7 | * @brief This file provides all the CPAL UserCallback functions . 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "cpal_i2c.h" 30 | 31 | /* Private typedef -----------------------------------------------------------*/ 32 | /* Private defines -----------------------------------------------------------*/ 33 | /* Private variables ---------------------------------------------------------*/ 34 | /* Private macro -------------------------------------------------------------*/ 35 | /* Private function prototypes -----------------------------------------------*/ 36 | /* Private functions ---------------------------------------------------------*/ 37 | 38 | 39 | 40 | /*------------------------------------------------------------------------------ 41 | CPAL User Callbacks implementations 42 | ------------------------------------------------------------------------------*/ 43 | 44 | 45 | /*=========== Timeout UserCallback ===========*/ 46 | 47 | 48 | /** 49 | * @brief User callback that manages the Timeout error. 50 | * @param pDevInitStruct . 51 | * @retval None. 52 | */ 53 | uint32_t CPAL_TIMEOUT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 54 | { 55 | 56 | return CPAL_PASS; 57 | } 58 | 59 | 60 | /*=========== Transfer UserCallback ===========*/ 61 | 62 | 63 | /** 64 | * @brief Manages the End of Tx transfer event. 65 | * @param pDevInitStruct 66 | * @retval None 67 | */ 68 | /*void CPAL_I2C_TXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 69 | { 70 | 71 | }*/ 72 | 73 | 74 | /** 75 | * @brief Manages the End of Rx transfer event. 76 | * @param pDevInitStruct 77 | * @retval None 78 | */ 79 | /*void CPAL_I2C_RXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 80 | { 81 | 82 | }*/ 83 | 84 | 85 | /** 86 | * @brief Manages Tx transfer event. 87 | * @param pDevInitStruct 88 | * @retval None 89 | */ 90 | /*void CPAL_I2C_TX_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 91 | { 92 | 93 | }*/ 94 | 95 | 96 | /** 97 | * @brief Manages Rx transfer event. 98 | * @param pDevInitStruct 99 | * @retval None 100 | */ 101 | /*void CPAL_I2C_RX_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 102 | { 103 | 104 | }*/ 105 | 106 | 107 | /** 108 | * @brief Manages the End of DMA Tx transfer event. 109 | * @param pDevInitStruct 110 | * @retval None 111 | */ 112 | /*void CPAL_I2C_DMATXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 113 | { 114 | 115 | }*/ 116 | 117 | 118 | /** 119 | * @brief Manages the Half of DMA Tx transfer event. 120 | * @param pDevInitStruct 121 | * @retval None 122 | */ 123 | /*void CPAL_I2C_DMATXHT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 124 | { 125 | 126 | }*/ 127 | 128 | 129 | /** 130 | * @brief Manages Error of DMA Tx transfer event. 131 | * @param pDevInitStruct 132 | * @retval None 133 | */ 134 | /*void CPAL_I2C_DMATXTE_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 135 | { 136 | 137 | }*/ 138 | 139 | 140 | /** 141 | * @brief Manages the End of DMA Rx transfer event. 142 | * @param pDevInitStruct 143 | * @retval None 144 | */ 145 | /*void CPAL_I2C_DMARXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 146 | { 147 | 148 | }*/ 149 | 150 | 151 | /** 152 | * @brief Manages the Half of DMA Rx transfer event. 153 | * @param pDevInitStruct 154 | * @retval None 155 | */ 156 | /*void CPAL_I2C_DMARXHT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 157 | { 158 | 159 | }*/ 160 | 161 | 162 | /** 163 | * @brief Manages Error of DMA Rx transfer event. 164 | * @param pDevInitStruct 165 | * @retval None 166 | */ 167 | /*void CPAL_I2C_DMARXTE_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 168 | { 169 | 170 | }*/ 171 | 172 | 173 | /*=========== Error UserCallback ===========*/ 174 | 175 | 176 | /** 177 | * @brief User callback that manages the I2C device errors. 178 | * @note Make sure that the define USE_SINGLE_ERROR_CALLBACK is uncommented in 179 | * the cpal_conf.h file, otherwise this callback will not be functional. 180 | * @param pDevInitStruct. 181 | * @param DeviceError. 182 | * @retval None 183 | */ 184 | /*void CPAL_I2C_ERR_UserCallback(CPAL_DevTypeDef pDevInstance, uint32_t DeviceError) 185 | { 186 | 187 | }*/ 188 | 189 | 190 | /** 191 | * @brief User callback that manages BERR I2C device errors. 192 | * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in 193 | * the cpal_conf.h file, otherwise this callback will not be functional. 194 | * @param pDevInstance. 195 | * @retval None 196 | */ 197 | /*void CPAL_I2C_BERR_UserCallback(CPAL_DevTypeDef pDevInstance) 198 | { 199 | 200 | }*/ 201 | 202 | 203 | /** 204 | * @brief User callback that manages ARLO I2C device errors. 205 | * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in 206 | * the cpal_conf.h file, otherwise this callback will not be functional. 207 | * @param pDevInstance. 208 | * @retval None 209 | */ 210 | /*void CPAL_I2C_ARLO_UserCallback(CPAL_DevTypeDef pDevInstance) 211 | { 212 | 213 | }*/ 214 | 215 | 216 | /** 217 | * @brief User callback that manages OVR I2C device errors. 218 | * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in 219 | * the cpal_conf.h file, otherwise this callback will not be functional. 220 | * @param pDevInstance. 221 | * @retval None 222 | */ 223 | /*void CPAL_I2C_OVR_UserCallback(CPAL_DevTypeDef pDevInstance) 224 | { 225 | 226 | }*/ 227 | 228 | 229 | /** 230 | * @brief User callback that manages AF I2C device errors. 231 | * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in 232 | * the cpal_conf.h file, otherwise this callback will not be functional. 233 | * @param pDevInstance. 234 | * @retval None 235 | */ 236 | /*void CPAL_I2C_AF_UserCallback(CPAL_DevTypeDef pDevInstance) 237 | { 238 | 239 | }*/ 240 | 241 | 242 | /*=========== Addressing Mode UserCallback ===========*/ 243 | 244 | 245 | /** 246 | * @brief User callback that manage General Call Addressing mode. 247 | * @param pDevInitStruct 248 | * @retval None 249 | */ 250 | /*void CPAL_I2C_GENCALL_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 251 | { 252 | 253 | }*/ 254 | 255 | 256 | /** 257 | * @brief User callback that manage Dual Address Addressing mode. 258 | * @param pDevInitStruct 259 | * @retval None 260 | */ 261 | /*void CPAL_I2C_DUALF_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 262 | { 263 | 264 | }*/ 265 | 266 | 267 | 268 | /*=========== Listen Mode UserCallback ===========*/ 269 | 270 | 271 | /** 272 | * @brief User callback that manage slave read operation. 273 | * @param pDevInitStruct 274 | * @retval None 275 | */ 276 | /*void CPAL_I2C_SLAVE_READ_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 277 | { 278 | }*/ 279 | 280 | 281 | /** 282 | * @brief User callback that manage slave write operation. 283 | * @param pDevInitStruct 284 | * @retval None 285 | */ 286 | /*void CPAL_I2C_SLAVE_WRITE_UserCallback(CPAL_InitTypeDef* pDevInitStruct) 287 | { 288 | }*/ 289 | 290 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 291 | -------------------------------------------------------------------------------- /module.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "2.0", 3 | "environmentReqs": { 4 | "build": ["arm-none-eabi"] 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /scripts/linker/STM32F103_32K_20K_DEF.ld: -------------------------------------------------------------------------------- 1 | /* 2 | Linker subscript for STM32F103 definitions with 32K Flash and 20K RAM 3 | Copyright RAISONANCE 2007-2009 4 | !!! This file is automatically generated by Ride !!! 5 | Do not modify it, as it will be erased at every link. 6 | You can use, copy and distribute this file freely, but without any waranty. 7 | */ 8 | 9 | /* Memory Spaces Definitions */ 10 | 11 | MEMORY 12 | { 13 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K 14 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K 15 | FLASHPATCH (r) : ORIGIN = 0x00000000, LENGTH = 0 16 | ENDFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0 17 | FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 18 | EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 19 | EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 20 | EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 21 | EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 22 | } 23 | 24 | /* higher address of the user mode stack */ 25 | _estack = 0x20005000; 26 | 27 | -------------------------------------------------------------------------------- /scripts/linker/STM32F103_32K_20K_DEF_CLOAD.ld: -------------------------------------------------------------------------------- 1 | /* 2 | Linker subscript for STM32F103 definitions with 32K Flash and 20K RAM 3 | Copyright RAISONANCE 2007-2009 4 | !!! This file is automatically generated by Ride !!! 5 | Do not modify it, as it will be erased at every link. 6 | You can use, copy and distribute this file freely, but without any waranty. 7 | */ 8 | 9 | /* Memory Spaces Definitions */ 10 | 11 | MEMORY 12 | { 13 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K 14 | FLASH (rx) : ORIGIN = 0x8002800, LENGTH = 118K 15 | FLASHPATCH (r) : ORIGIN = 0x00000000, LENGTH = 0 16 | ENDFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0 17 | FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 18 | EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 19 | EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 20 | EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 21 | EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 22 | } 23 | 24 | /* higher address of the user mode stack */ 25 | _estack = 0x20005000; 26 | 27 | -------------------------------------------------------------------------------- /scripts/linker/STM32F103_32K_20K_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | Default secondary/main linker script for STM32F103_32K_20K 3 | Copyright RAISONANCE S.A.S. 2007-2009 4 | 5 | !!! This file is automatically generated by Ride if the default linker script option is active !!! 6 | 7 | Do not modify it if the option is set, as it will be erased at every link. 8 | If you need to use your own script please configure your Ride7 project linker options to use your custom linker script 9 | You can take this one as example for wrting your custom linker script 10 | You can use, copy and distribute this file freely, but without any waranty.*/ 11 | 12 | SEARCH_DIR("./scripts/linker") 13 | 14 | /* include the common STMxxx sub-script */ 15 | INCLUDE "STM32F10x_COMMON.ld" 16 | 17 | /* include the memory spaces definitions sub-script */ 18 | INCLUDE "STM32F103_32K_20K_DEF.ld" 19 | 20 | /* include the sections management sub-script for FLASH mode */ 21 | INCLUDE "sections_FLASH.ld" 22 | -------------------------------------------------------------------------------- /scripts/linker/STM32F103_32K_20K_FLASH_CLOAD.ld: -------------------------------------------------------------------------------- 1 | /* 2 | Default secondary/main linker script for STM32F103_32K_20K 3 | Copyright RAISONANCE S.A.S. 2007-2009 4 | 5 | !!! This file is automatically generated by Ride if the default linker script option is active !!! 6 | 7 | Do not modify it if the option is set, as it will be erased at every link. 8 | If you need to use your own script please configure your Ride7 project linker options to use your custom linker script 9 | You can take this one as example for wrting your custom linker script 10 | You can use, copy and distribute this file freely, but without any waranty.*/ 11 | 12 | SEARCH_DIR("./scripts") 13 | 14 | /* include the common STMxxx sub-script */ 15 | INCLUDE "STM32F10x_COMMON.ld" 16 | 17 | /* include the memory spaces definitions sub-script */ 18 | INCLUDE "STM32F103_32K_20K_DEF_CLOAD.ld" 19 | 20 | /* include the sections management sub-script for FLASH mode */ 21 | INCLUDE "sections_FLASH.ld" 22 | -------------------------------------------------------------------------------- /scripts/linker/STM32F10x_COMMON.ld: -------------------------------------------------------------------------------- 1 | /* 2 | Common part of the linker scripts for STM32 devices 3 | Copyright RAISONANCE 2009 4 | You can use, modify and distribute this file freely, but without any waranty. 5 | */ 6 | 7 | 8 | /* default stack sizes. 9 | 10 | These are used by the startup in order to allocate stacks for the different modes. 11 | */ 12 | 13 | __Stack_Size = 1024 ; 14 | 15 | PROVIDE ( _Stack_Size = __Stack_Size ) ; 16 | 17 | __Stack_Init = _estack - __Stack_Size ; 18 | 19 | /*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ 20 | PROVIDE ( _Stack_Init = __Stack_Init ) ; 21 | 22 | /* 23 | There will be a link error if there is not this amount of RAM free at the end. 24 | */ 25 | _Minimum_Stack_Size = 0x100 ; 26 | 27 | 28 | 29 | /* 30 | this sends all unreferenced IRQHandlers to reset 31 | */ 32 | 33 | 34 | PROVIDE ( Undefined_Handler = 0 ) ; 35 | PROVIDE ( SWI_Handler = 0 ) ; 36 | PROVIDE ( IRQ_Handler = 0 ) ; 37 | PROVIDE ( Prefetch_Handler = 0 ) ; 38 | PROVIDE ( Abort_Handler = 0 ) ; 39 | PROVIDE ( FIQ_Handler = 0 ) ; 40 | 41 | PROVIDE ( NMIException = 0 ) ; 42 | PROVIDE ( NMI_Handler = 0 ) ; 43 | PROVIDE ( HardFaultException = 0 ) ; 44 | PROVIDE ( HardFault_Handler = 0 ) ; 45 | PROVIDE ( MemManageException = 0 ) ; 46 | PROVIDE ( MemManage_Handler = 0 ) ; 47 | PROVIDE ( BusFaultException = 0 ) ; 48 | PROVIDE ( BusFault_Handler = 0 ) ; 49 | PROVIDE ( UsageFaultException = 0 ) ; 50 | PROVIDE ( UsageFault_Handler = 0 ) ; 51 | 52 | PROVIDE ( SVCHandler = 0 ) ; 53 | PROVIDE ( SVC_Handler = 0 ) ; 54 | PROVIDE ( DebugMonitor = 0 ) ; 55 | PROVIDE ( DebugMon_Handler = 0 ) ; 56 | PROVIDE ( PendSVC = 0 ) ; 57 | PROVIDE ( PendSV_Handler = 0 ) ; 58 | PROVIDE ( SysTickHandler = 0 ) ; 59 | PROVIDE ( SysTick_Handler = 0 ) ; 60 | 61 | PROVIDE ( WWDG_IRQHandler = 0 ) ; 62 | PROVIDE ( PVD_IRQHandler = 0 ) ; 63 | PROVIDE ( TAMPER_IRQHandler = 0 ) ; 64 | PROVIDE ( RTC_IRQHandler = 0 ) ; 65 | PROVIDE ( FLASH_IRQHandler = 0 ) ; 66 | PROVIDE ( RCC_IRQHandler = 0 ) ; 67 | PROVIDE ( EXTI0_IRQHandler = 0 ) ; 68 | PROVIDE ( EXTI1_IRQHandler = 0 ) ; 69 | PROVIDE ( EXTI2_IRQHandler = 0 ) ; 70 | PROVIDE ( EXTI3_IRQHandler = 0 ) ; 71 | PROVIDE ( EXTI4_IRQHandler = 0 ) ; 72 | PROVIDE ( DMAChannel1_IRQHandler = 0 ) ; 73 | PROVIDE ( DMAChannel2_IRQHandler = 0 ) ; 74 | PROVIDE ( DMAChannel3_IRQHandler = 0 ) ; 75 | PROVIDE ( DMAChannel4_IRQHandler = 0 ) ; 76 | PROVIDE ( DMAChannel5_IRQHandler = 0 ) ; 77 | PROVIDE ( DMAChannel6_IRQHandler = 0 ) ; 78 | PROVIDE ( DMAChannel7_IRQHandler = 0 ) ; 79 | PROVIDE ( DMA1_Channel1_IRQHandler = 0 ) ; 80 | PROVIDE ( DMA1_Channel2_IRQHandler = 0 ) ; 81 | PROVIDE ( DMA1_Channel3_IRQHandler = 0 ) ; 82 | PROVIDE ( DMA1_Channel4_IRQHandler = 0 ) ; 83 | PROVIDE ( DMA1_Channel5_IRQHandler = 0 ) ; 84 | PROVIDE ( DMA1_Channel6_IRQHandler = 0 ) ; 85 | PROVIDE ( DMA1_Channel7_IRQHandler = 0 ) ; 86 | PROVIDE ( ADC_IRQHandler = 0 ) ; 87 | PROVIDE ( ADC1_2_IRQHandler = 0 ) ; 88 | PROVIDE ( USB_HP_CAN_TX_IRQHandler = 0 ) ; 89 | PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ; 90 | PROVIDE ( USB_LP_CAN_RX0_IRQHandler = 0 ) ; 91 | PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ; 92 | PROVIDE ( CAN_RX1_IRQHandler = 0 ) ; 93 | PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ; 94 | PROVIDE ( CAN_SCE_IRQHandler = 0 ) ; 95 | PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ; 96 | PROVIDE ( EXTI9_5_IRQHandler = 0 ) ; 97 | PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ; 98 | PROVIDE ( TIM1_UP_IRQHandler = 0 ) ; 99 | PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ; 100 | PROVIDE ( TIM1_CC_IRQHandler = 0 ) ; 101 | PROVIDE ( TIM2_IRQHandler = 0 ) ; 102 | PROVIDE ( TIM3_IRQHandler = 0 ) ; 103 | PROVIDE ( TIM4_IRQHandler = 0 ) ; 104 | PROVIDE ( I2C1_EV_IRQHandler = 0 ) ; 105 | PROVIDE ( I2C1_ER_IRQHandler = 0 ) ; 106 | PROVIDE ( I2C2_EV_IRQHandler = 0 ) ; 107 | PROVIDE ( I2C2_ER_IRQHandler = 0 ) ; 108 | PROVIDE ( SPI1_IRQHandler = 0 ) ; 109 | PROVIDE ( SPI2_IRQHandler = 0 ) ; 110 | PROVIDE ( USART1_IRQHandler = 0 ) ; 111 | PROVIDE ( USART2_IRQHandler = 0 ) ; 112 | PROVIDE ( USART3_IRQHandler = 0 ) ; 113 | PROVIDE ( EXTI15_10_IRQHandler = 0 ) ; 114 | PROVIDE ( RTCAlarm_IRQHandler = 0 ) ; 115 | PROVIDE ( USBWakeUp_IRQHandler = 0 ) ; 116 | PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ; 117 | PROVIDE ( TIM8_UP_IRQHandler = 0 ); 118 | PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ; 119 | PROVIDE ( TIM8_CC_IRQHandler = 0 ) ; 120 | PROVIDE ( ADC3_IRQHandler = 0 ) ; 121 | PROVIDE ( FSMC_IRQHandler = 0 ) ; 122 | PROVIDE ( SDIO_IRQHandler = 0 ) ; 123 | PROVIDE ( TIM5_IRQHandler = 0 ) ; 124 | PROVIDE ( SPI3_IRQHandler = 0 ) ; 125 | PROVIDE ( UART4_IRQHandler = 0 ) ; 126 | PROVIDE ( UART5_IRQHandler = 0 ) ; 127 | PROVIDE ( TIM6_IRQHandler = 0 ) ; 128 | PROVIDE ( TIM7_IRQHandler = 0 ) ; 129 | PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ; 130 | PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ; 131 | PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ; 132 | PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ; 133 | 134 | 135 | 136 | /******************************************************************************/ 137 | /* Peripheral memory map */ 138 | /******************************************************************************/ 139 | /*this allows to compile the ST lib in "non-debug" mode*/ 140 | 141 | 142 | /* Peripheral and SRAM base address in the alias region */ 143 | PERIPH_BB_BASE = 0x42000000; 144 | SRAM_BB_BASE = 0x22000000; 145 | 146 | /* Peripheral and SRAM base address in the bit-band region */ 147 | SRAM_BASE = 0x20000000; 148 | PERIPH_BASE = 0x40000000; 149 | 150 | /* Flash registers base address */ 151 | PROVIDE ( FLASH_BASE = 0x40022000); 152 | /* Flash Option Bytes base address */ 153 | PROVIDE ( OB_BASE = 0x1FFFF800); 154 | 155 | /* Peripheral memory map */ 156 | APB1PERIPH_BASE = PERIPH_BASE ; 157 | APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ; 158 | AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ; 159 | 160 | PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ; 161 | PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ; 162 | PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ; 163 | PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ; 164 | PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ; 165 | PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ; 166 | PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ; 167 | PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ; 168 | PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ; 169 | PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ; 170 | PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ; 171 | PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ; 172 | PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ; 173 | PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ; 174 | 175 | PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ; 176 | PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ; 177 | PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ; 178 | PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ; 179 | PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ; 180 | PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ; 181 | PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ; 182 | PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ; 183 | PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ; 184 | PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ; 185 | PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ; 186 | PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ; 187 | 188 | PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ; 189 | PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ; 190 | PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ; 191 | PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ; 192 | PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ; 193 | PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ; 194 | PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ; 195 | PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ; 196 | PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ; 197 | 198 | /* System Control Space memory map */ 199 | SCS_BASE = 0xE000E000; 200 | 201 | PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ; 202 | PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ; 203 | PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ; 204 | 205 | -------------------------------------------------------------------------------- /scripts/linker/STM32F303xC.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, 3 | 2011,2012 Giovanni Di Sirio. 4 | 5 | This file is part of ChibiOS/RT. 6 | 7 | ChibiOS/RT is free software; you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation; either version 3 of the License, or 10 | (at your option) any later version. 11 | 12 | ChibiOS/RT is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License 18 | along with this program. If not, see . 19 | */ 20 | 21 | /* 22 | * ST32F303xC memory setup. 23 | */ 24 | __main_stack_size__ = 0x0400; 25 | __process_stack_size__ = 0x0400; 26 | 27 | MEMORY 28 | { 29 | flash : org = 0x08000000, len = 256k 30 | ram : org = 0x20000000, len = 40k 31 | ccmram : org = 0x10000000, len = 8k 32 | } 33 | 34 | __ram_start__ = ORIGIN(ram); 35 | __ram_size__ = LENGTH(ram); 36 | __ram_end__ = __ram_start__ + __ram_size__; 37 | 38 | SECTIONS 39 | { 40 | . = 0; 41 | _text = .; 42 | 43 | startup : ALIGN(16) SUBALIGN(16) 44 | { 45 | KEEP(*(vectors)) 46 | } > flash 47 | 48 | constructors : ALIGN(4) SUBALIGN(4) 49 | { 50 | PROVIDE(__init_array_start = .); 51 | KEEP(*(SORT(.init_array.*))) 52 | KEEP(*(.init_array)) 53 | PROVIDE(__init_array_end = .); 54 | } > flash 55 | 56 | destructors : ALIGN(4) SUBALIGN(4) 57 | { 58 | PROVIDE(__fini_array_start = .); 59 | KEEP(*(.fini_array)) 60 | KEEP(*(SORT(.fini_array.*))) 61 | PROVIDE(__fini_array_end = .); 62 | } > flash 63 | 64 | .text : ALIGN(16) SUBALIGN(16) 65 | { 66 | *(.text.startup.*) 67 | *(.text) 68 | *(.text.*) 69 | *(.rodata) 70 | *(.rodata.*) 71 | *(.glue_7t) 72 | *(.glue_7) 73 | *(.gcc*) 74 | } > flash 75 | 76 | .ARM.extab : 77 | { 78 | *(.ARM.extab* .gnu.linkonce.armextab.*) 79 | } > flash 80 | 81 | .ARM.exidx : { 82 | PROVIDE(__exidx_start = .); 83 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 84 | PROVIDE(__exidx_end = .); 85 | } > flash 86 | 87 | .eh_frame_hdr : 88 | { 89 | *(.eh_frame_hdr) 90 | } > flash 91 | 92 | .eh_frame : ONLY_IF_RO 93 | { 94 | *(.eh_frame) 95 | } > flash 96 | 97 | .textalign : ONLY_IF_RO 98 | { 99 | . = ALIGN(8); 100 | } > flash 101 | 102 | _etext = .; 103 | _textdata = _etext; 104 | 105 | .stacks : 106 | { 107 | . = ALIGN(8); 108 | __main_stack_base__ = .; 109 | . += __main_stack_size__; 110 | . = ALIGN(8); 111 | __main_stack_end__ = .; 112 | __process_stack_base__ = .; 113 | __main_thread_stack_base__ = .; 114 | . += __process_stack_size__; 115 | . = ALIGN(8); 116 | __process_stack_end__ = .; 117 | __main_thread_stack_end__ = .; 118 | } > ram 119 | 120 | .data : 121 | { 122 | . = ALIGN(4); 123 | PROVIDE(_data = .); 124 | *(.data) 125 | . = ALIGN(4); 126 | *(.data.*) 127 | . = ALIGN(4); 128 | *(.ramtext) 129 | . = ALIGN(4); 130 | PROVIDE(_edata = .); 131 | } > ram AT > flash 132 | 133 | .bss : 134 | { 135 | . = ALIGN(4); 136 | PROVIDE(_bss_start = .); 137 | *(.bss) 138 | . = ALIGN(4); 139 | *(.bss.*) 140 | . = ALIGN(4); 141 | *(COMMON) 142 | . = ALIGN(4); 143 | PROVIDE(_bss_end = .); 144 | } > ram 145 | } 146 | 147 | PROVIDE(end = .); 148 | _end = .; 149 | 150 | __heap_base__ = _end; 151 | __heap_end__ = __ram_end__; 152 | -------------------------------------------------------------------------------- /scripts/linker/sections_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | Common part of the linker scripts for STR71x devices in FLASH mode 3 | (that is, the FLASH is seen at 0) 4 | Copyright RAISONANCE 2005 5 | You can use, modify and distribute thisfile freely, but without any waranty. 6 | */ 7 | 8 | 9 | 10 | /* Sections Definitions */ 11 | 12 | SECTIONS 13 | { 14 | /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ 15 | .isr_vector : 16 | { 17 | . = ALIGN(4); 18 | KEEP(*(.isr_vector)) /* Startup code */ 19 | . = ALIGN(4); 20 | } >FLASH 21 | 22 | /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ 23 | .flashtext : 24 | { 25 | . = ALIGN(4); 26 | *(.flashtext) /* Startup code */ 27 | . = ALIGN(4); 28 | } >FLASH 29 | 30 | 31 | /* the program code is stored in the .text section, which goes to Flash */ 32 | .text : 33 | { 34 | . = ALIGN(4); 35 | 36 | *(.text) /* remaining code */ 37 | *(.text.*) /* remaining code */ 38 | *(.rodata) /* read-only data (constants) */ 39 | *(.rodata*) 40 | *(.glue_7) 41 | *(.glue_7t) 42 | 43 | /* Some stuff of CodeSourcery? */ 44 | *(.init) 45 | *(.fini) 46 | *(.eh_frame) 47 | 48 | /* Parameters and log system datas */ 49 | . = ALIGN(4); 50 | _param_start = .; 51 | KEEP(*(.param)) 52 | KEEP(*(.param.*)) 53 | _param_stop = .; 54 | . = ALIGN(4); 55 | _log_start = .; 56 | KEEP(*(.log)) 57 | KEEP(*(.log.*)) 58 | _log_stop = .; 59 | 60 | 61 | . = ALIGN(4); 62 | _etext = .; 63 | /* This is used by the startup in order to initialize the .data secion */ 64 | /* _sidata = _etext; */ 65 | } >FLASH 66 | 67 | .libc : 68 | { 69 | . = ALIGN(4); 70 | *(.ARM.exidx*) 71 | . = ALIGN(4); 72 | 73 | _elibc = .; 74 | _sidata = _elibc; 75 | } >FLASH 76 | 77 | /* for some LPC devices, there is a FLASH patch to place at a specified address */ 78 | .flashpatch : 79 | { 80 | . = ALIGN(4); 81 | KEEP(*(.flashpatch)) /* flashpatch data */ 82 | . = ALIGN(4); 83 | } >FLASHPATCH 84 | 85 | /* for some LPC devices, there is a FLASH patch to place at a specified address 86 | and then there is the rest of the flash */ 87 | .endflash : 88 | { 89 | . = ALIGN(4); 90 | *(.endflash) /* endflash code */ 91 | . = ALIGN(4); 92 | } >ENDFLASH 93 | 94 | /* This is the initialized data section 95 | The program executes knowing that the data is in the RAM 96 | but the loader puts the initial values in the FLASH (inidata). 97 | It is one task of the startup to copy the initial values from FLASH to RAM. */ 98 | .data : AT ( _sidata ) 99 | { 100 | . = ALIGN(4); 101 | /* This is used by the startup in order to initialize the .data secion */ 102 | _sdata = . ; 103 | 104 | *(.data) 105 | *(.data.*) 106 | *(.RAMtext) 107 | 108 | . = ALIGN(4); 109 | /* This is used by the startup in order to initialize the .data secion */ 110 | _edata = . ; 111 | } >RAM 112 | 113 | 114 | 115 | /* This is the uninitialized data section */ 116 | .bss : 117 | { 118 | . = ALIGN(4); 119 | /* This is used by the startup in order to initialize the .bss secion */ 120 | _sbss = .; 121 | 122 | *(.bss) 123 | *(.bss.*) 124 | *(COMMON) 125 | 126 | . = ALIGN(4); 127 | /* This is used by the startup in order to initialize the .bss secion */ 128 | _ebss = . ; 129 | } >RAM 130 | 131 | PROVIDE ( end = _ebss ); 132 | PROVIDE ( _end = _ebss ); 133 | 134 | /* This is the user stack section 135 | This is just to check that there is enough RAM left for the User mode stack 136 | It should generate an error if it's full. 137 | */ 138 | ._usrstack : 139 | { 140 | . = ALIGN(4); 141 | _susrstack = . ; 142 | 143 | . = . + _Minimum_Stack_Size ; 144 | 145 | . = ALIGN(4); 146 | _eusrstack = . ; 147 | } >RAM 148 | 149 | 150 | 151 | /* this is the FLASH Bank1 */ 152 | /* the C or assembly source must explicitly place the code or data there 153 | using the "section" attribute */ 154 | .b1text : 155 | { 156 | *(.b1text) /* remaining code */ 157 | *(.b1rodata) /* read-only data (constants) */ 158 | *(.b1rodata*) 159 | } >FLASHB1 160 | 161 | /* this is the EXTMEM */ 162 | /* the C or assembly source must explicitly place the code or data there 163 | using the "section" attribute */ 164 | 165 | /* EXTMEM Bank0 */ 166 | .eb0text : 167 | { 168 | *(.eb0text) /* remaining code */ 169 | *(.eb0rodata) /* read-only data (constants) */ 170 | *(.eb0rodata*) 171 | } >EXTMEMB0 172 | 173 | /* EXTMEM Bank1 */ 174 | .eb1text : 175 | { 176 | *(.eb1text) /* remaining code */ 177 | *(.eb1rodata) /* read-only data (constants) */ 178 | *(.eb1rodata*) 179 | } >EXTMEMB1 180 | 181 | /* EXTMEM Bank2 */ 182 | .eb2text : 183 | { 184 | *(.eb2text) /* remaining code */ 185 | *(.eb2rodata) /* read-only data (constants) */ 186 | *(.eb2rodata*) 187 | } >EXTMEMB2 188 | 189 | /* EXTMEM Bank0 */ 190 | .eb3text : 191 | { 192 | *(.eb3text) /* remaining code */ 193 | *(.eb3rodata) /* read-only data (constants) */ 194 | *(.eb3rodata*) 195 | } >EXTMEMB3 196 | 197 | __exidx_start = .; 198 | __exidx_end = .; 199 | 200 | /* after that it's only debugging information. */ 201 | 202 | /* remove the debugging information from the standard libraries */ 203 | /DISCARD/ : 204 | { 205 | libc.a ( * ) 206 | libm.a ( * ) 207 | libgcc.a ( * ) 208 | } 209 | 210 | /* Stabs debugging sections. */ 211 | .stab 0 : { *(.stab) } 212 | .stabstr 0 : { *(.stabstr) } 213 | .stab.excl 0 : { *(.stab.excl) } 214 | .stab.exclstr 0 : { *(.stab.exclstr) } 215 | .stab.index 0 : { *(.stab.index) } 216 | .stab.indexstr 0 : { *(.stab.indexstr) } 217 | .comment 0 : { *(.comment) } 218 | /* DWARF debug sections. 219 | Symbols in the DWARF debugging sections are relative to the beginning 220 | of the section so we begin them at 0. */ 221 | /* DWARF 1 */ 222 | .debug 0 : { *(.debug) } 223 | .line 0 : { *(.line) } 224 | /* GNU DWARF 1 extensions */ 225 | .debug_srcinfo 0 : { *(.debug_srcinfo) } 226 | .debug_sfnames 0 : { *(.debug_sfnames) } 227 | /* DWARF 1.1 and DWARF 2 */ 228 | .debug_aranges 0 : { *(.debug_aranges) } 229 | .debug_pubnames 0 : { *(.debug_pubnames) } 230 | /* DWARF 2 */ 231 | .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } 232 | .debug_abbrev 0 : { *(.debug_abbrev) } 233 | .debug_line 0 : { *(.debug_line) } 234 | .debug_frame 0 : { *(.debug_frame) } 235 | .debug_str 0 : { *(.debug_str) } 236 | .debug_loc 0 : { *(.debug_loc) } 237 | .debug_macinfo 0 : { *(.debug_macinfo) } 238 | /* SGI/MIPS DWARF 2 extensions */ 239 | .debug_weaknames 0 : { *(.debug_weaknames) } 240 | .debug_funcnames 0 : { *(.debug_funcnames) } 241 | .debug_typenames 0 : { *(.debug_typenames) } 242 | .debug_varnames 0 : { *(.debug_varnames) } 243 | } 244 | 245 | 246 | 247 | -------------------------------------------------------------------------------- /scripts/print_revision.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | MODIFIED=0 4 | 5 | if test -d .git ; then 6 | # git 7 | ID=$(git describe --tags --abbrev=12 HEAD) 8 | REV=${ID##*-} 9 | REV=${REV:1} 10 | LOCAL=${ID#*-*-} 11 | TAG=${ID%-$LOCAL} 12 | LOCAL=${LOCAL%-*} 13 | git update-index -q --refresh 14 | if ! test -z "$(git diff-index --name-only HEAD --)" ; then 15 | MODIFIED=1 16 | fi 17 | else 18 | # mercury 19 | ID=$(hg identify -nit) 20 | 21 | REV=$(echo -n $ID | cut -d' ' -f1) 22 | LOCAL=$(echo -n $ID | cut -d' ' -f2) 23 | TAG=$(echo -n $ID | cut -d' ' -f3) 24 | 25 | #LOCAL=$(hg identify -n) 26 | #REV=$(hg identify -i) 27 | #TAG=$(hg identify -t) 28 | if echo -n $REV | grep +\$>/dev/null; then 29 | MODIFIED=1 30 | fi 31 | fi 32 | 33 | echo -n Build $LOCAL:$REV \($TAG\) 34 | 35 | if test $MODIFIED -eq 1 ; then 36 | echo -e " \033[1;31mMODIFIED\033[m" 37 | else 38 | echo -e " \033[1;32mCLEAN\033[m" 39 | fi 40 | -------------------------------------------------------------------------------- /scripts/targets.mk: -------------------------------------------------------------------------------- 1 | # Part of CrazyFlie's Makefile 2 | # Copyright (c) 2009, Arnaud Taffanel 3 | # Common targets with verbose support 4 | 5 | 6 | ifeq ($(V),) 7 | VERBOSE=_SILENT 8 | endif 9 | 10 | ifeq ($(V),0) 11 | QUIET=1 12 | endif 13 | 14 | target = @$(if $(QUIET), ,echo $($1_COMMAND$(VERBOSE)) ); @$($1_COMMAND) 15 | 16 | VTMPL_COMMAND=$(PYTHON2) scripts/versionTemplate.py $< $@ 17 | #$(BIN)/$(lastword $(subst /, ,$@)) 18 | VTMPL_COMMAND_SILENT=" VTMPL $@" 19 | %.c: %.vtpl 20 | @$(if $(QUIET), ,echo $(VTMPL_COMMAND$(VERBOSE)) ) 21 | @$(VTMPL_COMMAND) 22 | 23 | CC_COMMAND=$(CC) $(CFLAGS) -c $< -o $(BIN)/$@ 24 | CC_COMMAND_SILENT=" CC $@" 25 | .c.o: 26 | @$(if $(QUIET), ,echo $(CC_COMMAND$(VERBOSE)) ) 27 | @$(CC_COMMAND) 28 | 29 | LD_COMMAND=$(LD) $(LDFLAGS) $(foreach o,$(OBJ),$(BIN)/$(o)) -lm -o $@ 30 | LD_COMMAND_SILENT=" LD $@" 31 | $(PROG).elf: $(OBJ) 32 | @$(if $(QUIET), ,echo $(LD_COMMAND$(VERBOSE)) ) 33 | @$(LD_COMMAND) 34 | 35 | HEX_COMMAND=$(OBJCOPY) $< -O ihex $@ 36 | HEX_COMMAND_SILENT=" COPY $@" 37 | $(PROG).hex: $(PROG).elf 38 | @$(if $(QUIET), ,echo $(HEX_COMMAND$(VERBOSE)) ) 39 | @$(HEX_COMMAND) 40 | 41 | BIN_COMMAND=$(OBJCOPY) $< -O binary --pad-to 0 $@ 42 | BIN_COMMAND_SILENT=" COPY $@" 43 | $(PROG).bin: $(PROG).elf 44 | @$(if $(QUIET), ,echo $(BIN_COMMAND$(VERBOSE)) ) 45 | @$(BIN_COMMAND) 46 | 47 | AS_COMMAND=$(AS) $(ASFLAGS) $< -o $(BIN)/$@ 48 | AS_COMMAND_SILENT=" AS $@" 49 | .s.o: 50 | @$(if $(QUIET), ,echo $(AS_COMMAND$(VERBOSE)) ) 51 | @$(AS_COMMAND) 52 | 53 | CLEAN_O_COMMAND=rm -f $(foreach o,$(OBJ),$(BIN)/$(o)) 54 | CLEAN_O_COMMAND_SILENT=" CLEAN_O" 55 | clean_o: clean_version 56 | @$(if $(QUIET), ,echo $(CLEAN_O_COMMAND$(VERBOSE)) ) 57 | @$(CLEAN_O_COMMAND) 58 | 59 | CLEAN_COMMAND=rm -f $(PROG).elf $(PROG).hex $(PROG).bin $(PROG).map $(BIN)/dep/*.d 60 | CLEAN_COMMAND_SILENT=" CLEAN" 61 | clean: clean_o 62 | @$(if $(QUIET), ,echo $(CLEAN_COMMAND$(VERBOSE)) ) 63 | @$(CLEAN_COMMAND) 64 | 65 | MRPROPER_COMMAND=rm -f *~ hal/src/*~ hal/interface/*~ tasks/src/*~ tasks/inc/*~ utils/src/*~ utils/inc/*~ scripts/*~; rm -rf bin/dep ;rmdir bin 66 | MRPROPER_COMMAND_SILENT=" MRPROPER" 67 | mrproper: clean 68 | @$(if $(QUIET), ,echo $(MRPROPER_COMMAND$(VERBOSE)) ) 69 | @$(MRPROPER_COMMAND) 70 | 71 | 72 | -------------------------------------------------------------------------------- /src/bootpin.c: -------------------------------------------------------------------------------- 1 | /* Pin scheme used by the NRF to direct bootloader boot: 2 | * State | NRF_TX | NRF_FC | 3 | * ----------------+--------+--------+ 4 | * Boot Firmware | HIGH | LOW | 5 | * Boot Bootloader | HIGH | HIGH | 6 | * Error, boot DFU | HZ | HZ | 7 | * 8 | * NRF_TX and NRF_FC are configured with pull-down resistors 9 | * to detect the HZ state. 10 | */ 11 | 12 | #include "bootpin.h" 13 | 14 | #include 15 | 16 | void bootpinInit(void) 17 | { 18 | GPIO_InitTypeDef gpioInit; 19 | 20 | RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOAEN, ENABLE); 21 | RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOCEN, ENABLE); 22 | 23 | gpioInit.GPIO_Mode = GPIO_Mode_IN; 24 | gpioInit.GPIO_PuPd = GPIO_PuPd_DOWN; 25 | gpioInit.GPIO_Speed = GPIO_Speed_2MHz; 26 | gpioInit.GPIO_Pin = GPIO_Pin_4; 27 | GPIO_Init(GPIOA, &gpioInit); 28 | gpioInit.GPIO_Pin = GPIO_Pin_7; 29 | GPIO_Init(GPIOC, &gpioInit); 30 | } 31 | 32 | void bootpinDeinit(void) 33 | { 34 | GPIO_DeInit(GPIOA); 35 | GPIO_DeInit(GPIOC); 36 | 37 | RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOAEN, DISABLE); 38 | RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOCEN, DISABLE); 39 | } 40 | 41 | bool bootpinStartFirmware(void) 42 | { 43 | return GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_4) == Bit_RESET && 44 | GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_7) == Bit_SET; 45 | } 46 | 47 | bool bootpinStartBootloader(void) 48 | { 49 | return GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_4) == Bit_SET && 50 | GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_7) == Bit_SET; 51 | } 52 | 53 | bool bootpinNrfReset(void) 54 | { 55 | return GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_4) == Bit_RESET && 56 | GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_7) == Bit_RESET; 57 | } 58 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include 6 | #include "bootpin.h" 7 | #include "uart.h" 8 | #include "syslink.h" 9 | #include "crtp.h" 10 | #include "loaderCommands.h" 11 | #include "config.h" 12 | 13 | static volatile uint32_t tick; 14 | 15 | static bool bootloaderProcess(CrtpPacket *packet); 16 | 17 | void SysTick_Handler() 18 | { 19 | tick++; 20 | } 21 | 22 | void delayMs(int ms) { 23 | while (ms--) { 24 | while ((SysTick->CTRL&SysTick_CTRL_COUNTFLAG_Msk)==0); 25 | } 26 | } 27 | 28 | int main() 29 | { 30 | GPIO_InitTypeDef gpioInit = {0}; 31 | struct syslinkPacket slPacket; 32 | struct crtpPacket_s packet; 33 | unsigned int ledGreenTime=0; 34 | unsigned int ledRedTime = 0; 35 | unsigned int ledBlueTime = 0; 36 | 37 | 38 | /* Detecting if we need to boot firmware or DFU bootloader */ 39 | bootpinInit(); 40 | if (bootpinStartFirmware() == true) { 41 | if (*((uint32_t*)FIRMWARE_START) != 0xFFFFFFFFU) { 42 | void (*firmware)(void) __attribute__((noreturn)) = (void *)(*(uint32_t*)(FIRMWARE_START+4)); 43 | bootpinDeinit(); 44 | // Start firmware 45 | NVIC_SetVectorTable(FIRMWARE_START, 0); 46 | __set_MSP(*((uint32_t*)FIRMWARE_START)); 47 | firmware(); 48 | } 49 | } else if (bootpinNrfReset() == true) { 50 | void (*bootloader)(void) __attribute__((noreturn)) = (void *)(*(uint32_t*)(SYSTEM_BASE+4)); 51 | bootpinDeinit(); 52 | // Start bootloader 53 | NVIC_SetVectorTable(SYSTEM_BASE, 0); 54 | __set_MSP(*((uint32_t*)SYSTEM_BASE)); 55 | bootloader(); 56 | 57 | } 58 | bootpinDeinit(); 59 | 60 | /* Booting CRTP Bootloader! */ 61 | SystemInit(); 62 | uartInit(); 63 | 64 | 65 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); 66 | 67 | gpioInit.GPIO_Pin = GPIO_Pin_2; 68 | gpioInit.GPIO_Mode = GPIO_Mode_OUT; 69 | GPIO_Init(GPIOD, &gpioInit); 70 | 71 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); 72 | 73 | gpioInit.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_0; 74 | gpioInit.GPIO_Mode = GPIO_Mode_OUT; 75 | GPIO_Init(GPIOC, &gpioInit); 76 | GPIO_WriteBit(GPIOC, GPIO_Pin_0, 1); 77 | GPIO_WriteBit(GPIOC, GPIO_Pin_1, 1); 78 | 79 | SysTick->LOAD = (SystemCoreClock/8)/1000; // Set systick to overflow every 1ms 80 | SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk; 81 | NVIC_EnableIRQ(SysTick_IRQn); 82 | 83 | // Blue LED ON by default 84 | GPIO_WriteBit(GPIOD, GPIO_Pin_2, 1); 85 | 86 | while(1) { 87 | if (syslinkReceive(&slPacket)) { 88 | if (slPacket.type == SYSLINK_RADIO_RAW) { 89 | memcpy(packet.raw, slPacket.data, slPacket.length); 90 | packet.datalen = slPacket.length-1; 91 | 92 | ledGreenTime = tick; 93 | GPIO_WriteBit(GPIOC, GPIO_Pin_1, 0); 94 | 95 | if (bootloaderProcess(&packet)) { 96 | ledRedTime = tick; 97 | GPIO_WriteBit(GPIOC, GPIO_Pin_0, 0); 98 | 99 | memcpy(slPacket.data, packet.raw, packet.datalen+1); 100 | slPacket.length = packet.datalen+1; 101 | syslinkSend(&slPacket); 102 | } 103 | } 104 | } 105 | 106 | if (ledGreenTime!=0 && tick-ledGreenTime>10) { 107 | GPIO_WriteBit(GPIOC, GPIO_Pin_1, 1); 108 | ledGreenTime = 0; 109 | } 110 | if (ledRedTime!=0 && tick-ledRedTime>10) { 111 | GPIO_WriteBit(GPIOC, GPIO_Pin_0, 1); 112 | ledRedTime = 0; 113 | } 114 | 115 | if ((tick-ledBlueTime)>500) { 116 | if (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_2)) { 117 | GPIO_WriteBit(GPIOD, GPIO_Pin_2, 0); 118 | } else { 119 | GPIO_WriteBit(GPIOD, GPIO_Pin_2, 1); 120 | } 121 | ledBlueTime = tick; 122 | } 123 | } 124 | return 0; 125 | } 126 | 127 | static const uint32_t sector_address[] = { 128 | [0] = 0x08000000, 129 | [1] = 0x08004000, 130 | [2] = 0x08008000, 131 | [3] = 0x0800C000, 132 | [4] = 0x08010000, 133 | [5] = 0x08020000, 134 | [6] = 0x08040000, 135 | [7] = 0x08060000, 136 | [8] = 0x08080000, 137 | [9] = 0x080A0000, 138 | [10] = 0x080C0000, 139 | [11] = 0x080E0000, 140 | }; 141 | 142 | static bool bootloaderProcess(CrtpPacket *pk) 143 | { 144 | static char buffer[BUFFER_PAGES*PAGE_SIZE]; 145 | 146 | if ((pk->datalen>1) && (pk->header == 0xFF) && (pk->data[0]==0xFF)) 147 | { 148 | if (pk->data[1] == CMD_GET_INFO) 149 | { 150 | GetInfoReturns_t * info = (GetInfoReturns_t *)&pk->data[2]; 151 | 152 | info->pageSize = PAGE_SIZE; 153 | info->nBuffPages = BUFFER_PAGES; 154 | info->nFlashPages = flashPages; 155 | info->flashStart = FLASH_START; 156 | //memcpy(info->cpuId, cpuidGetId(), CPUID_LEN); 157 | info->version = PROTOCOL_VERSION; 158 | 159 | pk->datalen = 2+sizeof(GetInfoReturns_t); 160 | 161 | return true; 162 | } 163 | else if (pk->data[1] == CMD_GET_MAPPING) 164 | { 165 | const uint8_t mapping[] = {4, 16, 1, 64, 7, 128}; 166 | GetMappingReturns_t * returns = (GetMappingReturns_t *)&pk->data[2]; 167 | 168 | memcpy(returns->mapping, mapping, sizeof(mapping)); 169 | 170 | pk->datalen = 2+sizeof(mapping); 171 | 172 | return true; 173 | }/* 174 | else if (pk->data[1] == CMD_SET_ADDRESS) 175 | { 176 | SetAddressParameters_t * addressPk; 177 | addressPk = (SetAddressParameters_t *)&pk->data[2]; 178 | 179 | radioSetAddress(addressPk->address); 180 | } 181 | else */if (pk->data[1] == CMD_LOAD_BUFFER) 182 | { 183 | int i=0; 184 | LoadBufferParameters_t *params = (LoadBufferParameters_t *)&pk->data[2]; 185 | char *data = (char*) &pk->data[2+sizeof(LoadBufferParameters_t)]; 186 | 187 | //Fill the buffer with the given data 188 | for(i=0; i<(pk->datalen-(2+sizeof(LoadBufferParameters_t))) && (i+(params->page*PAGE_SIZE)+params->address)<(BUFFER_PAGES*PAGE_SIZE); i++) 189 | { 190 | buffer[(i+(params->page*PAGE_SIZE)+params->address)] = data[i]; 191 | } 192 | } 193 | else if (pk->data[1] == CMD_READ_BUFFER) 194 | { 195 | int i=0; 196 | ReadBufferParameters_t *params = (ReadBufferParameters_t *)&pk->data[2]; 197 | char *data = (char*) &pk->data[2+sizeof(ReadBufferParameters_t)]; 198 | 199 | //Return the data required 200 | for(i=0; i<25 && (i+(params->page*PAGE_SIZE)+params->address)<(BUFFER_PAGES*PAGE_SIZE); i++) 201 | { 202 | data[i] = buffer[(i+(params->page*PAGE_SIZE)+params->address)]; 203 | } 204 | 205 | pk->datalen += i; 206 | 207 | return true; 208 | } 209 | else if (pk->data[1] == CMD_READ_FLASH) 210 | { 211 | int i=0; 212 | char *data = (char*) &pk->data[2+sizeof(ReadFlashParameters_t)]; 213 | ReadFlashParameters_t *params = (ReadFlashParameters_t *)&pk->data[2]; 214 | char *flash= (char*)FLASH_BASE; 215 | 216 | //Return the data required 217 | for(i=0; i<25 && (i+(params->page*PAGE_SIZE)+params->address)<(flashPages*PAGE_SIZE); i++) 218 | { 219 | //data[i] = flash[(i+(params->page*PAGE_SIZE)+params->address)]; 220 | //data[i] = *((char*)(FLASH_BASE+i+(params->page*PAGE_SIZE)+params->address)); 221 | data[i] = flash[(i+(params->page*PAGE_SIZE)+params->address)]; 222 | } 223 | 224 | pk->datalen += i; 225 | 226 | return true; 227 | } 228 | else if (pk->data[1] == CMD_WRITE_FLASH) 229 | { 230 | int i; 231 | int j; 232 | unsigned int error = 0xFF; 233 | int flashAddress; 234 | uint32_t *bufferToFlash; 235 | WriteFlashParameters_t *params = (WriteFlashParameters_t *)&pk->data[2]; 236 | WriteFlashReturns_t *returns = (WriteFlashReturns_t *)&pk->data[2]; 237 | 238 | //Test if it is an acceptable write request 239 | if ( (params->flashPageflashPage>=flashPages) || 240 | ((params->flashPage+params->nPages)>flashPages) || (params->bufferPage>=BUFFER_PAGES) 241 | ) 242 | { 243 | //Return a failure answer 244 | returns->done = 0; 245 | returns->error = 1; 246 | pk->datalen = 2+sizeof(WriteFlashReturns_t); 247 | return true; 248 | } 249 | // Else, if everything is OK, flash the page(s) 250 | else 251 | { 252 | FLASH_Unlock(); 253 | FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_OPERR |FLASH_FLAG_WRPERR | 254 | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); 255 | 256 | __disable_irq(); 257 | //Erase the page(s) 258 | for(i=0; inPages; i++) 259 | { 260 | for (j=0; j<12; j++) { 261 | if ((uint32_t)(FLASH_BASE + ((uint32_t)params->flashPage*PAGE_SIZE) + (i*PAGE_SIZE)) == sector_address[j]) { 262 | if ( FLASH_EraseSector(j<<3, VoltageRange_3) != FLASH_COMPLETE) 263 | { 264 | error = 2; 265 | goto failure; 266 | } 267 | } 268 | } 269 | } 270 | 271 | //Write the data, long per long 272 | flashAddress = FLASH_BASE + (params->flashPage*PAGE_SIZE); 273 | bufferToFlash = (uint32_t *) (&buffer[0] + (params->bufferPage*PAGE_SIZE)); 274 | for (i=0; i<((params->nPages*PAGE_SIZE)/sizeof(uint32_t)); i++, flashAddress+=4) 275 | { 276 | if(FLASH_ProgramWord(flashAddress, bufferToFlash[i]) != FLASH_COMPLETE) 277 | { 278 | error = 3; 279 | goto failure; 280 | } 281 | } 282 | 283 | //Everything OK! great, send back an OK packet 284 | returns->done = 1; 285 | returns->error = 0; 286 | pk->datalen = 2+sizeof(WriteFlashReturns_t); 287 | FLASH_Lock(); 288 | __enable_irq(); 289 | return true; 290 | 291 | goto finally; 292 | 293 | failure: 294 | FLASH_Lock(); 295 | __enable_irq(); 296 | 297 | //If the write procedure failed, send the error packet 298 | //TODO: see if it is necessary or wanted to send the reason as well 299 | returns->done = 0; 300 | returns->error = error; 301 | pk->datalen = 2+sizeof(WriteFlashReturns_t); 302 | return true; 303 | 304 | finally: 305 | FLASH_Lock(); 306 | __enable_irq(); 307 | } 308 | } 309 | } 310 | return false; 311 | } 312 | -------------------------------------------------------------------------------- /src/syslink.c: -------------------------------------------------------------------------------- 1 | #include "syslink.h" 2 | #include "uart.h" 3 | 4 | #include 5 | #include 6 | 7 | /* Frame format: 8 | * +----+-----+------+-----+=============+-----+-----+ 9 | * | START | TYPE | LEN | DATA | CKSUM | 10 | * +----+-----+------+-----+=============+-----+-----+ 11 | * 12 | * - Start is 2 bytes constant, defined bellow 13 | * - Length and type are uint8_t 14 | * - Length define the data length 15 | * - CKSUM is 2 bytes Fletcher 8 bit checksum. See rfc1146. 16 | * Checksum is calculated with TYPE, LEN and DATA 17 | */ 18 | 19 | 20 | #define START "\xbc\xcf" 21 | #define START_BYTE1 0xBC 22 | #define START_BYTE2 0xCF 23 | 24 | bool syslinkReceive(struct syslinkPacket *packet) 25 | { 26 | static enum {state_first_start, state_second_start, state_length, state_type, state_data, state_cksum1, state_cksum2, state_done} state = state_first_start; 27 | static int step=0; 28 | static int length=0; 29 | static uint8_t cksum_a=0, cksum_b=0; 30 | char c; 31 | 32 | packet->length = 0; 33 | 34 | if (state == state_done) 35 | { 36 | state = state_first_start; 37 | step = 0; 38 | } 39 | 40 | while (uartIsRxReady() && (state != state_done)) 41 | { 42 | c = uartGetc(); 43 | 44 | switch(state) 45 | { 46 | case state_first_start: 47 | state = (c == START_BYTE1) ? state_second_start : state_first_start; 48 | break; 49 | case state_second_start: 50 | state = (c == START_BYTE2) ? state_type : state_first_start; 51 | break; 52 | case state_type: 53 | packet->type = c; 54 | cksum_a = c; 55 | cksum_b = cksum_a; 56 | state = state_length; 57 | break; 58 | case state_length: 59 | length = c; 60 | cksum_a += c; 61 | cksum_b += cksum_a; 62 | step = 0; 63 | if (length > 0) 64 | state = state_data; 65 | else if (length > SYSLINK_MTU) 66 | state = state_first_start; 67 | else 68 | state = state_cksum1; 69 | break; 70 | case state_data: 71 | if (step < SYSLINK_MTU) 72 | { 73 | packet->data[step] = c; 74 | cksum_a += c; 75 | cksum_b += cksum_a; 76 | } 77 | step++; 78 | if(step >= length) { 79 | state = state_cksum1; 80 | } 81 | break; 82 | case state_cksum1: 83 | if (c == cksum_a) 84 | { 85 | state = state_cksum2; 86 | } 87 | else 88 | { // Wrong checksum 89 | state = state_first_start; 90 | } 91 | break; 92 | case state_cksum2: 93 | if (c == cksum_b) 94 | { 95 | packet->length = length; 96 | state = state_done; 97 | } 98 | else 99 | { // Wrong checksum 100 | state = state_first_start; 101 | step = 0; 102 | } 103 | break; 104 | case state_done: 105 | break; 106 | } 107 | } 108 | 109 | return (state == state_done); 110 | } 111 | 112 | bool syslinkSend(struct syslinkPacket *packet) 113 | { 114 | uint8_t cksum_a=0; 115 | uint8_t cksum_b=0; 116 | int i; 117 | 118 | uartPuts(START); 119 | 120 | uartPutc((unsigned char)packet->type); 121 | cksum_a += packet->type; 122 | cksum_b += cksum_a; 123 | 124 | uartPutc((unsigned char)packet->length); 125 | cksum_a += packet->length; 126 | cksum_b += cksum_a; 127 | 128 | for (i=0; i < packet->length; i++) 129 | { 130 | uartPutc(packet->data[i]); 131 | cksum_a += packet->data[i]; 132 | cksum_b += cksum_a; 133 | } 134 | 135 | uartPutc(cksum_a); 136 | uartPutc(cksum_b); 137 | 138 | return true; 139 | } 140 | -------------------------------------------------------------------------------- /src/uart.c: -------------------------------------------------------------------------------- 1 | //UART driver specific to the Crazyflie 2.0 bootloader. Implements 2 | // 'soft-hard flow control' 3 | #include 4 | 5 | #include 6 | #include "uart.h" 7 | 8 | #define POLLING_TX 9 | 10 | #define TXQ_LEN 64 11 | #define RXQ_LEN 64 12 | 13 | static char rxq[RXQ_LEN]; 14 | static int rxqTail; 15 | static int rxqHead; 16 | 17 | #ifndef POLLING_TX 18 | static char txq[TXQ_LEN]; 19 | static int txqTail; 20 | static int txqHead; 21 | #endif 22 | 23 | static unsigned int dropped; 24 | static volatile int devnull; 25 | 26 | void USART6_IRQHandler() 27 | { 28 | #ifndef POLLING_TX 29 | if (USART_GetFlagStatus(USART6, USART_FLAG_TC)) { 30 | USART_ClearFlag(USART6, USART_FLAG_TC); 31 | if (txqHead != txqTail) { 32 | USART_SendData(USART6, txq[txqTail]); 33 | txqTail = (txqTail+1)%TXQ_LEN; 34 | } 35 | } 36 | #endif 37 | if (USART_GetFlagStatus(USART6, USART_FLAG_RXNE)) { 38 | if (((rxqHead+1)%RXQ_LEN)!=rxqTail) { 39 | rxq[rxqHead] = USART_ReceiveData(USART6); 40 | rxqHead = (rxqHead+1)%RXQ_LEN; 41 | } else { 42 | devnull = USART_ReceiveData(USART6); //Drop data 43 | dropped++; 44 | } 45 | } 46 | } 47 | 48 | void uartInit() 49 | { 50 | USART_InitTypeDef usartInit = {0}; 51 | GPIO_InitTypeDef gpioInit = {0}; 52 | NVIC_InitTypeDef nvicInit = {0}; 53 | 54 | //Enable clocks 55 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); 56 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); 57 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); 58 | 59 | //Uart GPIOs 60 | gpioInit.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; 61 | gpioInit.GPIO_Mode = GPIO_Mode_AF; 62 | gpioInit.GPIO_OType = GPIO_OType_PP; 63 | gpioInit.GPIO_Speed = GPIO_Speed_25MHz; 64 | gpioInit.GPIO_PuPd = GPIO_PuPd_NOPULL; 65 | GPIO_Init(GPIOC, &gpioInit); 66 | GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_USART6); 67 | GPIO_PinAFConfig(GPIOC, GPIO_PinSource7, GPIO_AF_USART6); 68 | 69 | usartInit.USART_BaudRate = 1000000; 70 | usartInit.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 71 | usartInit.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 72 | usartInit.USART_Parity = USART_Parity_No; 73 | usartInit.USART_WordLength = USART_WordLength_8b; 74 | usartInit.USART_StopBits = USART_StopBits_1; 75 | USART_Init(USART6, &usartInit); 76 | 77 | // Enable interrupt 78 | #ifndef POLLING_TX 79 | USART_ITConfig(USART6, USART_IT_TC, ENABLE); 80 | #endif 81 | USART_ITConfig(USART6, USART_IT_RXNE, ENABLE); 82 | nvicInit.NVIC_IRQChannel = USART6_IRQn; 83 | nvicInit.NVIC_IRQChannelCmd = ENABLE; 84 | NVIC_Init(&nvicInit); 85 | //NVIC_EnableIRQ(USART6_IRQn); 86 | 87 | //Enable flow control GPIO 88 | gpioInit.GPIO_Pin = GPIO_Pin_4; 89 | gpioInit.GPIO_Mode = GPIO_Mode_IN; 90 | gpioInit.GPIO_PuPd = GPIO_PuPd_DOWN; 91 | GPIO_Init(GPIOA, &gpioInit); 92 | 93 | USART_Cmd(USART6, ENABLE); 94 | } 95 | 96 | bool uartIsRxReady() 97 | { 98 | return rxqHead != rxqTail; 99 | } 100 | 101 | char uartGetc() 102 | { 103 | char data = 0; 104 | if (uartIsRxReady()) { 105 | data = rxq[rxqTail]; 106 | rxqTail = (rxqTail+1)%RXQ_LEN; 107 | } 108 | return data; 109 | } 110 | 111 | bool uartIsTxReady() 112 | { 113 | #ifdef POLLING_TX 114 | return true; 115 | #else 116 | return ((txqHead+1)%TXQ_LEN) != txqTail; 117 | #endif 118 | } 119 | 120 | void uartPutc(char data) 121 | { 122 | #ifdef POLLING_TX 123 | while (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_4) == Bit_SET); 124 | USART_SendData(USART6, data); 125 | while(USART_GetFlagStatus(USART6, USART_FLAG_TC) == RESET); 126 | #else 127 | if (uartIsTxReady()) { 128 | txq[txqHead] = data; 129 | txqHead = ((txqHead+1)%TXQ_LEN); 130 | 131 | if (USART_GetFlagStatus(USART6, USART_FLAG_TXE)) { 132 | USART_SendData(USART6, txq[txqTail]); 133 | txqTail = (txqTail+1)%TXQ_LEN; 134 | } 135 | } else { 136 | dropped++; 137 | } 138 | #endif 139 | } 140 | 141 | void uartPuts(char *string) 142 | { 143 | while (*string) { 144 | uartPutc(*string++); 145 | } 146 | } 147 | -------------------------------------------------------------------------------- /tools/build/build: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | set -e 3 | 4 | scriptDir=$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd ) 5 | 6 | make --directory=${scriptDir}/../.. ${@} 7 | --------------------------------------------------------------------------------