├── COPYING ├── README ├── docs ├── Digital_Camera.pdf └── Presentation.pdf └── src ├── I2C.vhd ├── KAC_data.vhd ├── KAC_i2c.vhd ├── LEDDecoder.vhd ├── asyn_fifo_distrib.edn ├── asyn_fifo_distrib.vhd ├── asyn_fifo_distrib_64.edn ├── asyn_fifo_distrib_64.vhd ├── block_ram_2kx16.edn ├── block_ram_2kx16.vhd ├── clock_generation.vhd ├── clockdivider.vhd ├── comp_pckgs.vhd ├── digital_camera.ucf ├── digital_camera.vhd ├── digital_camera_tb.vhd ├── master_control_signal_generator.vhd ├── ms_delay.vhd ├── one_shot.vhd ├── pp_upload.vhd ├── pullup.vhd ├── ram_control.vhd ├── sdramcntl.vhd └── signal_debounce.vhd /COPYING: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | /********************************************************** 2 | 3 | FPGA Digital Camera Controller 4 | Copyright 2013 Ryan Henderson 5 | Some parts are copyrighted by their respective authors 6 | License: GPLv3 7 | 8 | ***********************************************************/ 9 | 10 | Explination of files: 11 | 12 | digital_camera.vhd 13 | Project top level 14 | 15 | digital_camera_tb.vhd 16 | Top level test bench 17 | 18 | Asyn_fifo_distrib.vhd 19 | Xilinx Core Generator simulation file 20 | 21 | Asyn_fifo_distrib.edn 22 | Pulled in by P&R 23 | 24 | Asyn_fifo_distrib_64.vhd 25 | Asyn_fifo_distrib_64.edn 26 | Same as other fifo only 64 deep vs 16 27 | 28 | block_ram_2kx16.vhd 29 | block_ram_2kx16.edn 30 | 9 Block RAMs 31 | 32 | clock_generation.vhd 33 | 2 DLLs for clock sync and divide 34 | 35 | clockdivider.vhd 36 | Generic clock divider. Counter 37 | 38 | comp_pckgs.vhd 39 | components for entities in design 40 | 41 | I2C.vhd 42 | OpenCores I2C simple 43 | 44 | KAC_data.vhd 45 | Captures and buffers data from camera in FIFO. 46 | 47 | KAC_i2c.vhd 48 | Controls camera by i2c 49 | 50 | LEDDecoder.vhd 51 | For the one segment on XSA-100 board 52 | 53 | master_control_signal_generator.vhd 54 | Communicates with I2C controller, host PC, ram_control 55 | to control operation. 56 | 57 | ms_delay.vhd 58 | Startup delay for camera, SDRAM 59 | 60 | one_shot.vhd 61 | Shortens signals to one clock pulse 62 | 63 | pp_upload.vhd 64 | Reads from fifo buffer to send data in nibbles through parallel port 65 | 66 | pullup.vhd 67 | Used in testbench to pullup I2C lines 68 | 69 | ram_control.vhd 70 | Arbitrates SDRAM access 71 | 72 | sdramcntl.vhd 73 | Xess provided Interface to SDRAM 74 | 75 | signal_debounce.vhd 76 | Handles hardware switch bounce 77 | 78 | -------------------------------------------------------------------------------- /docs/Digital_Camera.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bitflippersanonymous/fpga-camera/58a5cc9626b133b1eb9bb86d62fced556db63a7b/docs/Digital_Camera.pdf -------------------------------------------------------------------------------- /docs/Presentation.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bitflippersanonymous/fpga-camera/58a5cc9626b133b1eb9bb86d62fced556db63a7b/docs/Presentation.pdf -------------------------------------------------------------------------------- /src/I2C.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- I2C.vhd 7 | -- 8 | -- Simple I2C controller written by Richard Herveille OpenCores 9 | -- 10 | -- 1) No multimaster 11 | -- 2) No slave mode 12 | -- 3) No fifo's 13 | -- 14 | -- notes: 15 | -- Every command is acknowledged. Do not set a new command before 16 | -- previous is acknowledged. Dout is available 1 clock cycle later as cmd_ack 17 | 18 | --********************************************************************************** 19 | 20 | library ieee; 21 | use ieee.std_logic_1164.all; 22 | use ieee.std_logic_arith.all; 23 | 24 | package I2C is 25 | component simple_i2c is 26 | port ( 27 | clk : in std_logic; 28 | ena : in std_logic; 29 | nReset : in std_logic; 30 | 31 | clk_cnt : in unsigned(7 downto 0); -- 4x SCL 32 | 33 | -- input signals 34 | start, 35 | stop, 36 | read, 37 | write, 38 | ack_in : std_logic; 39 | Din : in std_logic_vector(7 downto 0); 40 | 41 | -- output signals 42 | cmd_ack : out std_logic; 43 | ack_out : out std_logic; 44 | Dout : out std_logic_vector(7 downto 0); 45 | 46 | -- i2c signals 47 | SCL : inout std_logic; 48 | SDA : inout std_logic 49 | ); 50 | end component simple_i2c; 51 | end package I2C; 52 | 53 | 54 | library ieee; 55 | use ieee.std_logic_1164.all; 56 | use ieee.std_logic_arith.all; 57 | 58 | entity simple_i2c is 59 | port ( 60 | clk : in std_logic; 61 | ena : in std_logic; 62 | nReset : in std_logic; 63 | 64 | clk_cnt : in unsigned(7 downto 0); -- 4x SCL 65 | 66 | -- input signals 67 | start, 68 | stop, 69 | read, 70 | write, 71 | ack_in : std_logic; 72 | Din : in std_logic_vector(7 downto 0); 73 | 74 | -- output signals 75 | cmd_ack : out std_logic; 76 | ack_out : out std_logic; 77 | Dout : out std_logic_vector(7 downto 0); 78 | 79 | -- i2c signals 80 | SCL : inout std_logic; 81 | SDA : inout std_logic 82 | ); 83 | end entity simple_i2c; 84 | 85 | architecture structural of simple_i2c is 86 | component i2c_core is 87 | port ( 88 | clk : in std_logic; 89 | nReset : in std_logic; 90 | 91 | clk_cnt : in unsigned(7 downto 0); 92 | 93 | cmd : in std_logic_vector(2 downto 0); 94 | cmd_ack : out std_logic; 95 | busy : out std_logic; 96 | 97 | Din : in std_logic; 98 | Dout : out std_logic; 99 | 100 | SCL : inout std_logic; 101 | SDA : inout std_logic 102 | ); 103 | end component i2c_core; 104 | 105 | -- commands for i2c_core 106 | constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; 107 | constant CMD_START : std_logic_vector(2 downto 0) := "010"; 108 | constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; 109 | constant CMD_READ : std_logic_vector(2 downto 0) := "100"; 110 | constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; 111 | 112 | -- signals for i2c_core 113 | signal core_cmd : std_logic_vector(2 downto 0); 114 | signal core_ack, core_busy, core_txd, core_rxd : std_logic; 115 | 116 | -- signals for shift register 117 | signal sr : std_logic_vector(7 downto 0); -- 8bit shift register 118 | signal shift, ld : std_logic; 119 | 120 | -- signals for state machine 121 | signal go, host_ack : std_logic; 122 | begin 123 | 124 | -- hookup i2c core 125 | u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, 126 | core_txd, core_rxd, SCL, SDA); 127 | 128 | -- generate host-command-acknowledge 129 | cmd_ack <= host_ack; 130 | 131 | -- generate go-signal 132 | go <= (read or write) and not host_ack; 133 | 134 | -- assign Dout output to shift-register 135 | Dout <= sr; 136 | 137 | -- assign ack_out output to core_rxd (contains last received bit) 138 | ack_out <= core_rxd; 139 | 140 | -- generate shift register 141 | shift_register: process(clk) 142 | begin 143 | if (clk'event and clk = '1') then 144 | if (ld = '1') then 145 | sr <= din; 146 | elsif (shift = '1') then 147 | sr <= (sr(6 downto 0) & core_rxd); 148 | end if; 149 | end if; 150 | end process shift_register; 151 | 152 | -- 153 | -- state machine 154 | -- 155 | statemachine : block 156 | type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); 157 | signal state : states; 158 | signal dcnt : unsigned(2 downto 0); 159 | begin 160 | -- 161 | -- command interpreter, translate complex commands into simpler I2C commands 162 | -- 163 | nxt_state_decoder: process(clk, nReset, state, start, core_txd, core_cmd, 164 | go, read, core_ack, sr, ack_in, stop) 165 | variable nxt_state : states; 166 | variable idcnt : unsigned(2 downto 0); 167 | variable ihost_ack : std_logic; 168 | variable icore_cmd : std_logic_vector(2 downto 0); 169 | variable icore_txd : std_logic; 170 | variable ishift, iload : std_logic; 171 | begin 172 | -- 8 databits (1byte) of data to shift-in/out 173 | idcnt := dcnt; 174 | 175 | -- no acknowledge (until command complete) 176 | ihost_ack := '0'; 177 | 178 | icore_txd := core_txd; 179 | 180 | -- keep current command to i2c_core 181 | icore_cmd := core_cmd; 182 | 183 | -- no shifting or loading of shift-register 184 | ishift := '0'; 185 | iload := '0'; 186 | 187 | -- keep current state; 188 | nxt_state := state; 189 | case state is 190 | when st_idle => 191 | if (go = '1') then 192 | if (start = '1') then 193 | nxt_state := st_start; 194 | icore_cmd := CMD_START; 195 | elsif (read = '1') then 196 | nxt_state := st_read; 197 | icore_cmd := CMD_READ; 198 | idcnt := "111"; 199 | else 200 | nxt_state := st_write; 201 | icore_cmd := CMD_WRITE; 202 | idcnt := "111"; 203 | iload := '1'; 204 | end if; 205 | end if; 206 | 207 | when st_start => 208 | if (core_ack = '1') then 209 | if (read = '1') then 210 | nxt_state := st_read; 211 | icore_cmd := CMD_READ; 212 | idcnt := "111"; 213 | else 214 | nxt_state := st_write; 215 | icore_cmd := CMD_WRITE; 216 | idcnt := "111"; 217 | iload := '1'; 218 | end if; 219 | end if; 220 | 221 | when st_write => 222 | if (core_ack = '1') then 223 | idcnt := dcnt -1; -- count down Data_counter 224 | icore_txd := sr(7); 225 | if (dcnt = 0) then 226 | nxt_state := st_ack; 227 | icore_cmd := CMD_READ; 228 | else 229 | ishift := '1'; 230 | -- icore_txd := sr(7); 231 | end if; 232 | end if; 233 | 234 | when st_read => 235 | if (core_ack = '1') then 236 | idcnt := dcnt -1; -- count down Data_counter 237 | ishift := '1'; 238 | if (dcnt = 0) then 239 | nxt_state := st_ack; 240 | icore_cmd := CMD_WRITE; 241 | icore_txd := ack_in; 242 | end if; 243 | end if; 244 | 245 | when st_ack => 246 | if (core_ack = '1') then 247 | -- generate command acknowledge signal 248 | ihost_ack := '1'; 249 | 250 | -- Perform an additional shift, needed for 'read' 251 | --(store last received bit in shift register) 252 | ishift := '1'; 253 | 254 | -- check for stop; Should a STOP command be generated ? 255 | if (stop = '1') then 256 | nxt_state := st_stop; 257 | icore_cmd := CMD_STOP; 258 | else 259 | nxt_state := st_idle; 260 | icore_cmd := CMD_NOP; 261 | end if; 262 | end if; 263 | 264 | when st_stop => 265 | if (core_ack = '1') then 266 | nxt_state := st_idle; 267 | icore_cmd := CMD_NOP; 268 | end if; 269 | 270 | when others => -- illegal states 271 | nxt_state := st_idle; 272 | icore_cmd := CMD_NOP; 273 | end case; 274 | 275 | -- generate registers 276 | if (nReset = '0') then 277 | core_cmd <= CMD_NOP; 278 | core_txd <= '0'; 279 | 280 | shift <= '0'; 281 | ld <= '0'; 282 | 283 | dcnt <= "111"; 284 | host_ack <= '0'; 285 | 286 | state <= st_idle; 287 | elsif (clk'event and clk = '1') then 288 | if (ena = '1') then 289 | state <= nxt_state; 290 | 291 | dcnt <= idcnt; 292 | shift <= ishift; 293 | ld <= iload; 294 | 295 | core_cmd <= icore_cmd; 296 | core_txd <= icore_txd; 297 | 298 | host_ack <= ihost_ack; 299 | end if; 300 | end if; 301 | end process nxt_state_decoder; 302 | 303 | end block statemachine; 304 | 305 | end architecture structural; 306 | 307 | 308 | -- 309 | -- 310 | -- I2C Core 311 | -- 312 | -- Translate simple commands into SCL/SDA transitions 313 | -- Each command has 5 states, A/B/C/D/idle 314 | -- 315 | -- start: SCL ~~~~~~~~~~\____ 316 | -- SDA ~~~~~~~~\______ 317 | -- x | A | B | C | D | i 318 | -- 319 | -- repstart SCL ____/~~~~\___ 320 | -- SDA __/~~~\______ 321 | -- x | A | B | C | D | i 322 | -- 323 | -- stop SCL ____/~~~~~~~~ 324 | -- SDA ==\____/~~~~~ 325 | -- x | A | B | C | D | i 326 | -- 327 | --- write SCL ____/~~~~\____ 328 | -- SDA ==X=========X= 329 | -- x | A | B | C | D | i 330 | -- 331 | --- read SCL ____/~~~~\____ 332 | -- SDA XXXX=====XXXX 333 | -- x | A | B | C | D | i 334 | -- 335 | 336 | -- Timing: Normal mode Fast mode 337 | ----------------------------------------------------------------- 338 | -- Fscl 100KHz 400KHz 339 | -- Th_scl 4.0us 0.6us High period of SCL 340 | -- Tl_scl 4.7us 1.3us Low period of SCL 341 | -- Tsu:sta 4.7us 0.6us setup time for a repeated start condition 342 | -- Tsu:sto 4.0us 0.6us setup time for a stop conditon 343 | -- Tbuf 4.7us 1.3us Bus free time between a stop and start condition 344 | -- 345 | 346 | library ieee; 347 | use ieee.std_logic_1164.all; 348 | use ieee.std_logic_arith.all; 349 | 350 | entity i2c_core is 351 | port ( 352 | clk : in std_logic; 353 | nReset : in std_logic; 354 | 355 | clk_cnt : in unsigned(7 downto 0); 356 | 357 | cmd : in std_logic_vector(2 downto 0); 358 | cmd_ack : out std_logic; 359 | busy : out std_logic; 360 | 361 | Din : in std_logic; 362 | Dout : out std_logic; 363 | 364 | SCL : inout std_logic; 365 | SDA : inout std_logic 366 | ); 367 | end entity i2c_core; 368 | 369 | architecture structural of i2c_core is 370 | constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; 371 | constant CMD_START : std_logic_vector(2 downto 0) := "010"; 372 | constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; 373 | constant CMD_READ : std_logic_vector(2 downto 0) := "100"; 374 | constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; 375 | 376 | type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, 377 | rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); 378 | signal state : cmds; 379 | signal SDAo, SCLo : std_logic; 380 | signal txd : std_logic; 381 | signal clk_en, slave_wait :std_logic; 382 | signal cnt : unsigned(7 downto 0) := clk_cnt; 383 | begin 384 | -- whenever the slave is not ready it can delay the cycle by pulling SCL low 385 | slave_wait <= '1' when ((SCLo = '1') and (SCL = '0')) else '0'; 386 | 387 | -- generate clk enable signal 388 | gen_clken: process(clk, nReset) 389 | begin 390 | if (nReset = '0') then 391 | cnt <= (others => '0'); 392 | clk_en <= '1'; --'0'; 393 | elsif (clk'event and clk = '1') then 394 | if (cnt = 0) then 395 | clk_en <= '1'; 396 | cnt <= clk_cnt; 397 | else 398 | if (slave_wait = '0') then 399 | cnt <= cnt -1; 400 | end if; 401 | clk_en <= '0'; 402 | end if; 403 | end if; 404 | end process gen_clken; 405 | 406 | -- generate statemachine 407 | nxt_state_decoder : process (clk, nReset, state, cmd, SDA, txd, din) 408 | variable nxt_state : cmds; 409 | variable icmd_ack, ibusy, store_sda : std_logic; 410 | variable itxd : std_logic; 411 | begin 412 | 413 | nxt_state := state; 414 | 415 | icmd_ack := '0'; -- default no acknowledge 416 | ibusy := '1'; -- default busy 417 | 418 | store_sda := '0'; 419 | 420 | itxd := txd; 421 | 422 | case (state) is 423 | -- idle 424 | when idle => 425 | case cmd is 426 | when CMD_START => 427 | nxt_state := start_a; 428 | icmd_ack := '1'; -- command completed 429 | 430 | when CMD_STOP => 431 | nxt_state := stop_a; 432 | icmd_ack := '1'; -- command completed 433 | 434 | when CMD_WRITE => 435 | nxt_state := wr_a; 436 | icmd_ack := '1'; -- command completed 437 | itxd := Din; 438 | 439 | when CMD_READ => 440 | nxt_state := rd_a; 441 | icmd_ack := '1'; -- command completed 442 | 443 | when others => 444 | nxt_state := idle; 445 | -- don't acknowledge NOP command icmd_ack := '1'; -- command completed 446 | ibusy := '0'; 447 | end case; 448 | 449 | -- start 450 | when start_a => 451 | nxt_state := start_b; 452 | 453 | when start_b => 454 | nxt_state := start_c; 455 | 456 | when start_c => 457 | nxt_state := start_d; 458 | 459 | when start_d => 460 | nxt_state := idle; 461 | ibusy := '0'; -- not busy when idle 462 | 463 | 464 | -- stop 465 | when stop_a => 466 | nxt_state := stop_b; 467 | 468 | when stop_b => 469 | nxt_state := stop_c; 470 | 471 | when stop_c => 472 | -- nxt_state := stop_d; 473 | 474 | -- when stop_d => 475 | nxt_state := idle; 476 | ibusy := '0'; -- not busy when idle 477 | 478 | -- read 479 | when rd_a => 480 | nxt_state := rd_b; 481 | 482 | when rd_b => 483 | nxt_state := rd_c; 484 | 485 | when rd_c => 486 | nxt_state := rd_d; 487 | store_sda := '1'; 488 | 489 | when rd_d => 490 | nxt_state := idle; 491 | ibusy := '0'; -- not busy when idle 492 | 493 | -- write 494 | when wr_a => 495 | nxt_state := wr_b; 496 | 497 | when wr_b => 498 | nxt_state := wr_c; 499 | 500 | when wr_c => 501 | nxt_state := wr_d; 502 | 503 | when wr_d => 504 | nxt_state := idle; 505 | ibusy := '0'; -- not busy when idle 506 | 507 | end case; 508 | 509 | -- generate regs 510 | if (nReset = '0') then 511 | state <= idle; 512 | cmd_ack <= '0'; 513 | busy <= '0'; 514 | txd <= '0'; 515 | Dout <= '0'; 516 | elsif (clk'event and clk = '1') then 517 | if (clk_en = '1') then 518 | state <= nxt_state; 519 | busy <= ibusy; 520 | 521 | txd <= itxd; 522 | if (store_sda = '1') then 523 | Dout <= SDA; 524 | end if; 525 | end if; 526 | 527 | cmd_ack <= icmd_ack and clk_en; 528 | end if; 529 | end process nxt_state_decoder; 530 | 531 | -- 532 | -- convert states to SCL and SDA signals 533 | -- 534 | output_decoder: process (clk, nReset, state, SCLo, SDA, Din) 535 | variable iscl, isda : std_logic; 536 | begin 537 | case (state) is 538 | when idle => 539 | iscl := SCLo; -- keep SCL in same state 540 | isda := SDA; -- keep SDA in same state 541 | 542 | -- start 543 | when start_a => 544 | iscl := SCLo; -- keep SCL in same state (for repeated start) 545 | isda := '1'; -- set SDA high 546 | 547 | when start_b => 548 | iscl := '1'; -- set SCL high 549 | isda := '1'; -- keep SDA high 550 | 551 | when start_c => 552 | iscl := '1'; -- keep SCL high 553 | isda := '0'; -- sel SDA low 554 | 555 | when start_d => 556 | iscl := '0'; -- set SCL low 557 | isda := '0'; -- keep SDA low 558 | 559 | -- stop 560 | when stop_a => 561 | iscl := '0'; -- keep SCL disabled 562 | isda := '0'; -- set SDA low 563 | 564 | when stop_b => 565 | iscl := '1'; -- set SCL high 566 | isda := '0'; -- keep SDA low 567 | 568 | when stop_c => 569 | iscl := '1'; -- keep SCL high 570 | isda := '1'; -- set SDA high 571 | 572 | -- write 573 | when wr_a => 574 | iscl := '0'; -- keep SCL low 575 | -- isda := txd; -- set SDA 576 | isda := Din; 577 | 578 | when wr_b => 579 | iscl := '1'; -- set SCL high 580 | -- isda := txd; -- set SDA 581 | isda := Din; 582 | 583 | when wr_c => 584 | iscl := '1'; -- keep SCL high 585 | -- isda := txd; -- set SDA 586 | isda := Din; 587 | 588 | when wr_d => 589 | iscl := '0'; -- set SCL low 590 | -- isda := txd; -- set SDA 591 | isda := Din; 592 | 593 | -- read 594 | when rd_a => 595 | iscl := '0'; -- keep SCL low 596 | isda := '1'; -- tri-state SDA 597 | 598 | when rd_b => 599 | iscl := '1'; -- set SCL high 600 | isda := '1'; -- tri-state SDA 601 | 602 | when rd_c => 603 | iscl := '1'; -- keep SCL high 604 | isda := '1'; -- tri-state SDA 605 | 606 | when rd_d => 607 | iscl := '0'; -- set SCL low 608 | isda := '1'; -- tri-state SDA 609 | end case; 610 | 611 | -- generate registers 612 | if (nReset = '0') then 613 | SCLo <= '1'; 614 | SDAo <= '1'; 615 | elsif (clk'event and clk = '1') then 616 | if (clk_en = '1') then 617 | SCLo <= iscl; 618 | SDAo <= isda; 619 | end if; 620 | end if; 621 | end process output_decoder; 622 | 623 | -- since SCL is externally pulled-up convert a '1' to a 'Z'(tri-state) 624 | -- since SDA is externally pulled-up convert a '1' to a 'Z'(tri-state) 625 | SCL <= '0' when (SCLo = '0') else 'Z'; 626 | SDA <= '0' when (SDAo = '0') else 'Z'; 627 | -- SCL <= SCLo; 628 | -- SDA <= SDAo; 629 | 630 | end architecture structural; 631 | 632 | 633 | 634 | 635 | -------------------------------------------------------------------------------- /src/KAC_data.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- KAC_data.vhd 7 | -- 8 | -- Reads data from image sensor and stuffs it into a FIFO. The fifo cordinates 9 | -- with ram control to dump its contents to the SDRAM 10 | -- 11 | --********************************************************************************** 12 | 13 | library IEEE; 14 | use IEEE.std_logic_1164.all; 15 | use IEEE.numeric_std.all; 16 | use work.common.all; 17 | use work.comp_pckgs.all; 18 | 19 | 20 | ENTITY KAC_data IS 21 | 22 | PORT 23 | ( 24 | clk_50Mhz : in std_logic; 25 | clk_12_5Mhz : in std_logic; 26 | rst : in std_logic; 27 | 28 | -- Internal logic I/O 29 | rd_en : in std_logic; 30 | dout : out std_logic_vector(15 downto 0); 31 | dump_data_req : out std_logic; 32 | start_new_frame : out std_logic; 33 | init_cycle_complete : in std_logic; 34 | 35 | 36 | -- KAC-1310 I/O 37 | sof_KAC : in std_logic; --Start of frame 38 | vclk_KAC : in std_logic; --Start of line 39 | hclk_KAC : in std_logic; --valid pixel data 40 | pix_KAC : in std_logic_vector(9 downto 0) 41 | ); 42 | 43 | END KAC_data; 44 | 45 | ARCHITECTURE KAC_data_arch OF KAC_data IS 46 | 47 | -- input mux state machine 48 | subtype state is integer range 4 downto 0; 49 | SIGNAL current_state, next_state: state; 50 | 51 | -- dump_data_req and start_new_frame state machine 52 | subtype state_req is integer range 3 downto 0; 53 | SIGNAL current_state_req, next_state_req: state_req; 54 | 55 | 56 | signal din : std_logic_VECTOR(15 downto 0); 57 | signal wr_en : std_logic; 58 | signal full : std_logic; 59 | signal empty : std_logic; 60 | signal almost_full : std_logic; 61 | signal almost_empty : std_logic; 62 | signal wr_count : std_logic_VECTOR(3 downto 0); 63 | signal rd_count : std_logic_VECTOR(3 downto 0); 64 | signal not_rst : std_logic; 65 | signal toggle : std_logic; 66 | signal test_pattern : std_logic_vector(15 downto 0); 67 | signal pixmux_r : std_logic_vector(7 downto 0); 68 | signal pixmux_next : std_logic_vector(7 downto 0); 69 | signal dump_data_r : std_logic; 70 | signal dump_data_next : std_logic; 71 | 72 | signal os_hclk_KAC : std_logic; 73 | signal os_sof_KAC : std_logic; 74 | 75 | --signal col_count : integer range 1280 downto 0; 76 | --signal row_count : integer range 1024 downto 0; 77 | 78 | 79 | BEGIN 80 | 81 | not_rst <= not(rst); 82 | dump_data_req <= dump_data_r; 83 | 84 | 85 | 86 | 87 | -- Used to be sure the input data is going through all the buffers 88 | -- in order. 89 | -- Count values to simulate pixel input. To be removed 90 | input_test: process( hclk_KAC, rst) 91 | variable i : integer range 1310719 downto 0; 92 | begin 93 | if rst='0' then 94 | i := 0; 95 | 96 | elsif hclk_KAC'event and hclk_KAC='1' then 97 | i := i + 1; 98 | 99 | end if; 100 | 101 | --din <= std_logic_vector(to_unsigned(i, test_pattern'length)); 102 | 103 | end process input_test; 104 | 105 | -- Make The sof_KAC signal one 50mhz period long 106 | sof_oneshot: one_shot 107 | port map 108 | ( 109 | clk => clk_50Mhz, 110 | sig_in => sof_KAC, 111 | rst => rst, 112 | sig_out => os_sof_KAC 113 | 114 | ); 115 | 116 | 117 | --Coregen fifo built of distributed rams of depth 64. 118 | KAC_FIFO : asyn_fifo_distrib_64 119 | port map 120 | ( 121 | din => din, 122 | wr_en => wr_en, 123 | wr_clk => clk_50Mhz, 124 | rd_en => rd_en, 125 | rd_clk => clk_50Mhz, 126 | ainit => not_rst, 127 | dout => dout, 128 | full => full, 129 | empty => empty, 130 | almost_full => almost_full, 131 | almost_empty => almost_empty, 132 | wr_count => wr_count, 133 | rd_count => rd_count 134 | ); 135 | 136 | 137 | -- Determine when the fifo needs to dump into memory. Leave some extra 138 | -- space incase the memory can't respond right away. 139 | -- 140 | -- When SOF goes high it signals the start of a new frame. When this happens, 141 | -- make sure the fifo has cleared the last frame. When the fifo is done clearing 142 | -- Signal start_new_frame to the memory controller so it can start the next frame 143 | -- in a new memory block. 144 | -- 145 | -- At 12.5Hmz: 146 | -- From sof asserted to first hclk is >64 mclks default setting. (Table 39 KAC 147 | -- datasheet. During this time, I will empty the fifo. According to the scope 148 | -- this is 550ns. Not enough to dump the entire fifo. 149 | -- 150 | -- 151 | -- At 5Mhz: 152 | -- Hmmm.. I'll have more time to dump the fifo. 153 | 154 | ----------------------- DUMP DATA REQ AND START_NEW_FRAME -------- 155 | 156 | -- After alot of flusteration ... this works alot better if I register 157 | -- the dump_data_req signal since it's used async in the ram_control 158 | -- process. I'm so happy!!!! It works now 159 | 160 | ------------------------------------------------------------------ 161 | comb_state_change_req: process(current_state_req, rd_count, 162 | almost_empty, empty, sof_KAC, dump_data_r) is 163 | begin 164 | 165 | --default actions 166 | next_state_req <= current_state_req; 167 | start_new_frame <= '0'; 168 | 169 | if rd_count = x"2" then 170 | dump_data_next <= '1'; 171 | elsif almost_empty = '1' then 172 | dump_data_next <= '0'; 173 | else 174 | dump_data_next <= dump_data_r; 175 | end if; 176 | 177 | --State machine actions 178 | case current_state_req is 179 | when 0 => 180 | 181 | if sof_KAC = '1' then 182 | next_state_req <= 1; 183 | end if; 184 | 185 | when 1 => 186 | if almost_empty = '0' then 187 | dump_data_next <= '1'; 188 | 189 | else 190 | next_state_req <= 2; 191 | 192 | end if; 193 | 194 | when 2 => 195 | start_new_frame <= '1'; 196 | next_state_req <= 3; 197 | 198 | when 3 => 199 | if sof_KAC = '0' then 200 | next_state_req <= 0; 201 | end if; 202 | 203 | end case; 204 | end process comb_state_change_req; 205 | 206 | --Change state on clock 207 | update_req: process( clk_50Mhz, rst, next_state_req, dump_data_next) is 208 | begin 209 | if rst = '0' then 210 | current_state_req <= 0; 211 | dump_data_r <= '0'; 212 | 213 | elsif clk_50Mhz'event and clk_50Mhz='1' then 214 | current_state_req <= next_state_req; 215 | dump_data_r <= dump_data_next; 216 | 217 | end if; 218 | end process update_req; 219 | 220 | 221 | 222 | 223 | ------------------- PIXEL DATA PACKING ----------------------- 224 | 225 | comb_state_change: process(current_state, pix_KAC, pixmux_r, 226 | init_cycle_complete, hclk_KAC) is 227 | 228 | begin 229 | 230 | --default actions 231 | next_state <= current_state; 232 | wr_en <= '0'; 233 | din <= (others=>'0'); 234 | pixmux_next <= pixmux_r; 235 | 236 | case current_state is 237 | when 0 => 238 | if init_cycle_complete = '1' then 239 | next_state <= 1; 240 | 241 | end if; 242 | 243 | when 1 => 244 | if hclk_KAC = '1' then 245 | pixmux_next <= pix_KAC(9 downto 2); 246 | next_state <= 2; 247 | end if; 248 | 249 | when 2 => 250 | if hclk_KAC = '0' then 251 | next_state <= 3; 252 | end if; 253 | 254 | when 3 => 255 | if hclk_KAC = '1' then 256 | din <= pix_KAC(9 downto 2) & pixmux_r; 257 | wr_en <= '1'; 258 | next_state <= 4; 259 | end if; 260 | 261 | when 4 => 262 | if hclk_KAC <= '0' then 263 | next_state <= 1; 264 | end if; 265 | 266 | end case; 267 | end process comb_state_change; 268 | 269 | --Change state on clock 270 | update: process( clk_50Mhz, rst, next_state, pixmux_next) is 271 | begin 272 | if rst = '0' then 273 | current_state <= 0; 274 | pixmux_r <= (others=>'0'); 275 | elsif clk_50Mhz'event and clk_50Mhz='1' then 276 | current_state <= next_state; 277 | pixmux_r <= pixmux_next; 278 | end if; 279 | end process update; 280 | 281 | 282 | 283 | END KAC_data_arch; 284 | 285 | -------------------------------------------------------------------------------- /src/KAC_i2c.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- KAC_i2c.vhd 7 | -- 8 | -- Provides direct access to control registers in image sensor. SRAM like interface 9 | -- makes I2C interface transparent to MCSG. Adapted from Dallas 1621 interface 10 | -- by Richard Herveille OpenCores. 11 | -- 12 | --********************************************************************************** 13 | 14 | 15 | 16 | library ieee; 17 | use ieee.std_logic_1164.all; 18 | use ieee.std_logic_arith.all; 19 | use work.i2c.all; 20 | 21 | 22 | entity KAC_i2c is 23 | generic ( I2C_ADDR : std_logic_vector(6 downto 0) ); 24 | port ( 25 | clk : in std_logic; 26 | nReset : in std_logic; 27 | start_KAC : in std_logic; 28 | done_KAC : out std_logic; 29 | r_w_KAC : in std_logic; --0=read 1=write 30 | Addr_KAC : in std_logic_vector(7 downto 0); 31 | Data_KAC_in : in std_logic_vector(7 downto 0); 32 | Data_KAC_out: out std_logic_vector(7 downto 0); 33 | 34 | SCL : inout std_logic; 35 | SDA : inout std_logic 36 | ); 37 | end entity KAC_i2c; 38 | 39 | architecture KAC_i2c_arch of KAC_i2c is 40 | -- Remove the generic defining the constant 41 | constant SLAVE_ADDR : std_logic_vector(6 downto 0) := I2C_ADDR; 42 | constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(100, 8); --from 50Mhz 43 | 44 | signal cmd_ack : std_logic; 45 | signal D : std_logic_vector(7 downto 0); 46 | signal lack, store_dout : std_logic; 47 | 48 | signal start, read, write, ack, stop : std_logic; 49 | signal i2c_dout : std_logic_vector(7 downto 0); 50 | 51 | begin 52 | -- hookup I2C controller 53 | u1: simple_i2c 54 | port map ( clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset, 55 | read => read, write => write, start => start, stop => stop, 56 | ack_in => ack, cmd_ack => cmd_ack, Din => D, Dout => i2c_dout, 57 | ack_out => lack, SCL => SCL, SDA => SDA); 58 | 59 | init_statemachine : block 60 | type states is (i1, i2, i3, t1, t2, t3, t4, ack_wait_read, 61 | ack_wait_write, idle); 62 | signal state : states; 63 | begin 64 | -- There are a bunch of signals that should be in this sensitivity list, 65 | -- but when I added them, things stopped working. I'll just leave it alone. 66 | nxt_state_decoder: process(clk, nReset, state, start_KAC, r_w_KAC) 67 | variable nxt_state : states; 68 | variable iD : std_logic_vector(7 downto 0); 69 | variable ierr : std_logic; 70 | variable istart, iread, iwrite, iack, istop : std_logic; 71 | variable istore_dout : std_logic; 72 | variable wait_for_ack : std_logic; 73 | 74 | begin 75 | nxt_state := state; 76 | ierr := '0'; 77 | istore_dout := '0'; 78 | done_KAC <= '0'; 79 | 80 | istart := start; 81 | iread := read; 82 | iwrite := write; 83 | iack := ack; 84 | istop := stop; 85 | iD := D; 86 | 87 | case (state) is 88 | 89 | -- Write Sequence 90 | when i1 => -- send start condition, sent slave address + write 91 | nxt_state := i2; 92 | istart := '1'; 93 | iread := '0'; 94 | iwrite := '1'; 95 | iack := '0'; 96 | istop := '0'; 97 | iD := (slave_addr & '0'); -- write to slave (R/W = '0') 98 | 99 | when i2 => -- send reg addr 100 | if (cmd_ack = '1') then 101 | nxt_state := i3; 102 | 103 | istart := '0'; 104 | iread := '0'; 105 | iwrite := '1'; 106 | iack := '0'; 107 | istop := '0'; 108 | iD := Addr_KAC; 109 | end if; 110 | 111 | when i3 => -- send data to write there 112 | if (cmd_ack = '1') then 113 | nxt_state := ack_wait_write; 114 | 115 | istart := '0'; 116 | iread := '0'; 117 | iwrite := '1'; 118 | iack := '0'; 119 | istop := '1'; 120 | iD := Data_KAC_in; 121 | end if; 122 | 123 | 124 | -- Read Sequence 125 | when t1 => -- send start condition, sent slave address + write 126 | -- if (cmd_ack = '1') then 127 | nxt_state := t2; 128 | 129 | istart := '1'; 130 | iread := '0'; 131 | iwrite := '1'; 132 | iack := '0'; 133 | istop := '0'; 134 | iD := (slave_addr & '0'); -- write to slave (R/W = '0') 135 | -- end if; 136 | 137 | when t2 => -- send reg addr 138 | if (cmd_ack = '1') then 139 | nxt_state := t3; 140 | 141 | istart := '0'; 142 | iread := '0'; 143 | iwrite := '1'; 144 | iack := '0'; 145 | istop := '0'; 146 | iD := Addr_KAC; 147 | end if; 148 | 149 | -- send (repeated) start condition, send slave address + read 150 | when t3 => 151 | if (cmd_ack = '1') then 152 | nxt_state := t4; 153 | 154 | istart := '1'; 155 | iread := '0'; 156 | iwrite := '1'; 157 | iack := '0'; 158 | istop := '0'; 159 | iD := (slave_addr & '1'); -- read from slave (R/W = '1') 160 | end if; 161 | 162 | when t4 => 163 | if (cmd_ack = '1') then 164 | nxt_state := ack_wait_read; 165 | 166 | istart := '0'; 167 | iread := '1'; 168 | iwrite := '0'; 169 | iack := '1'; --ACK 170 | istop := '1'; 171 | --istore_dout := '1'; 172 | end if; 173 | 174 | when ack_wait_read => 175 | if (cmd_ack = '1') then 176 | nxt_state := idle; 177 | istart := '0'; 178 | iread := '0'; 179 | iwrite := '0'; 180 | iack := '0'; 181 | istop := '0'; 182 | iD := x"00"; 183 | done_KAC <= '1'; 184 | istore_dout := '1'; -- Capture the value read 185 | end if; 186 | 187 | when ack_wait_write => 188 | if (cmd_ack = '1') then 189 | nxt_state := idle; 190 | istart := '0'; 191 | iread := '0'; 192 | iwrite := '0'; 193 | iack := '0'; 194 | istop := '0'; 195 | iD := x"00"; 196 | done_KAC <= '1'; 197 | end if; 198 | 199 | 200 | when idle => 201 | if start_KAC = '1' then 202 | if r_w_KAC = '0' then 203 | nxt_state := t1; --do read 204 | else 205 | nxt_state := i1; --do write 206 | end if; 207 | end if; 208 | 209 | --safe idle conditions and done 210 | istart := '0'; 211 | iread := '0'; 212 | iwrite := '0'; 213 | iack := '0'; 214 | istop := '0'; 215 | iD := x"00"; 216 | done_KAC <= '1'; 217 | 218 | end case; 219 | 220 | 221 | 222 | -- genregs 223 | if (nReset = '0') then 224 | state <= idle; 225 | store_dout <= '0'; 226 | start <= '0'; 227 | read <= '0'; 228 | write <= '0'; 229 | ack <= '0'; 230 | stop <= '0'; 231 | D <= (others => '0'); 232 | wait_for_ack := '0'; 233 | elsif (clk'event and clk = '1') then 234 | state <= nxt_state; 235 | store_dout <= istore_dout; 236 | 237 | start <= istart; 238 | read <= iread; 239 | write <= iwrite; 240 | ack <= iack; 241 | stop <= istop; 242 | D <= iD; 243 | end if; 244 | end process nxt_state_decoder; 245 | end block init_statemachine; 246 | 247 | -- store temp 248 | gen_dout : process(clk) 249 | begin 250 | if (clk'event and clk = '1') then 251 | if (store_dout = '1') then 252 | Data_KAC_out <= i2c_dout; 253 | end if; 254 | end if; 255 | end process gen_dout; 256 | 257 | 258 | end architecture KAC_i2c_arch; 259 | 260 | 261 | -------------------------------------------------------------------------------- /src/LEDDecoder.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- LEDDecoder.vhd 7 | -- 8 | -- 9 | --********************************************************************************** 10 | 11 | 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | use IEEE.STD_LOGIC_ARITH.ALL; 15 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 16 | 17 | entity LEDDecoder is 18 | Port ( d : in std_logic_vector(3 downto 0); 19 | s : out std_logic_vector(6 downto 0)); 20 | end LEDDecoder; 21 | 22 | architecture Behavioral of LEDDecoder is 23 | 24 | begin 25 | 26 | s <= "1110111" when d=x"0" else 27 | "0010010" when d=x"1" else 28 | "1011101" when d=x"2" else 29 | "1011011" when d=x"3" else 30 | "0111010" when d=x"4" else 31 | "1101011" when d=x"5" else 32 | "1101111" when d=x"6" else 33 | "1010010" when d=x"7" else 34 | "1111111" when d=x"8" else 35 | "1111011" when d=x"9" else 36 | "1111110" when d=x"A" else 37 | "0101111" when d=x"B" else 38 | "0001101" when d=x"C" else 39 | "0011111" when d=x"D" else 40 | "1101101" when d=x"E" else 41 | "1101100"; 42 | 43 | end Behavioral; 44 | -------------------------------------------------------------------------------- /src/asyn_fifo_distrib.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------- 2 | -- This file is owned and controlled by Xilinx and must be used -- 3 | -- solely for design, simulation, implementation and creation of -- 4 | -- design files limited to Xilinx devices or technologies. Use -- 5 | -- with non-Xilinx devices or technologies is expressly prohibited -- 6 | -- and immediately terminates your license. -- 7 | -- -- 8 | -- Xilinx products are not intended for use in life support -- 9 | -- appliances, devices, or systems. Use in such applications are -- 10 | -- expressly prohibited. -- 11 | -- -- 12 | -- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. -- 13 | ---------------------------------------------------------------------- 14 | 15 | -- You must compile the wrapper file asyn_fifo_distrib.vhd when simulating 16 | -- the core, asyn_fifo_distrib. When compiling the wrapper file, be sure to 17 | -- reference the XilinxCoreLib VHDL simulation library. For detailed 18 | -- instructions, please refer to the "Coregen Users Guide". 19 | 20 | -- The synopsys directives "translate_off/translate_on" specified 21 | -- below are supported by XST, FPGA Express, Exemplar and Synplicity 22 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). 23 | 24 | -- synopsys translate_off 25 | LIBRARY ieee; 26 | USE ieee.std_logic_1164.ALL; 27 | 28 | Library XilinxCoreLib; 29 | ENTITY asyn_fifo_distrib IS 30 | port ( 31 | din: IN std_logic_VECTOR(15 downto 0); 32 | wr_en: IN std_logic; 33 | wr_clk: IN std_logic; 34 | rd_en: IN std_logic; 35 | rd_clk: IN std_logic; 36 | ainit: IN std_logic; 37 | dout: OUT std_logic_VECTOR(15 downto 0); 38 | full: OUT std_logic; 39 | empty: OUT std_logic; 40 | almost_full: OUT std_logic; 41 | almost_empty: OUT std_logic; 42 | wr_count: OUT std_logic_VECTOR(3 downto 0)); 43 | END asyn_fifo_distrib; 44 | 45 | ARCHITECTURE asyn_fifo_distrib_a OF asyn_fifo_distrib IS 46 | 47 | component wrapped_asyn_fifo_distrib 48 | port ( 49 | din: IN std_logic_VECTOR(15 downto 0); 50 | wr_en: IN std_logic; 51 | wr_clk: IN std_logic; 52 | rd_en: IN std_logic; 53 | rd_clk: IN std_logic; 54 | ainit: IN std_logic; 55 | dout: OUT std_logic_VECTOR(15 downto 0); 56 | full: OUT std_logic; 57 | empty: OUT std_logic; 58 | almost_full: OUT std_logic; 59 | almost_empty: OUT std_logic; 60 | wr_count: OUT std_logic_VECTOR(3 downto 0)); 61 | end component; 62 | 63 | -- Configuration specification 64 | for all : wrapped_asyn_fifo_distrib use entity XilinxCoreLib.async_fifo_v3_0(behavioral) 65 | generic map( 66 | c_wr_count_width => 4, 67 | c_has_rd_err => 0, 68 | c_data_width => 16, 69 | c_has_almost_full => 1, 70 | c_rd_err_low => 0, 71 | c_has_wr_ack => 0, 72 | c_wr_ack_low => 0, 73 | c_fifo_depth => 15, 74 | c_rd_count_width => 2, 75 | c_has_wr_err => 0, 76 | c_has_almost_empty => 1, 77 | c_rd_ack_low => 0, 78 | c_has_wr_count => 1, 79 | c_use_blockmem => 1, 80 | c_has_rd_ack => 0, 81 | c_has_rd_count => 0, 82 | c_wr_err_low => 0, 83 | c_enable_rlocs => 0); 84 | BEGIN 85 | 86 | U0 : wrapped_asyn_fifo_distrib 87 | port map ( 88 | din => din, 89 | wr_en => wr_en, 90 | wr_clk => wr_clk, 91 | rd_en => rd_en, 92 | rd_clk => rd_clk, 93 | ainit => ainit, 94 | dout => dout, 95 | full => full, 96 | empty => empty, 97 | almost_full => almost_full, 98 | almost_empty => almost_empty, 99 | wr_count => wr_count); 100 | END asyn_fifo_distrib_a; 101 | 102 | -- synopsys translate_on 103 | 104 | -------------------------------------------------------------------------------- /src/asyn_fifo_distrib_64.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------- 2 | -- This file is owned and controlled by Xilinx and must be used -- 3 | -- solely for design, simulation, implementation and creation of -- 4 | -- design files limited to Xilinx devices or technologies. Use -- 5 | -- with non-Xilinx devices or technologies is expressly prohibited -- 6 | -- and immediately terminates your license. -- 7 | -- -- 8 | -- Xilinx products are not intended for use in life support -- 9 | -- appliances, devices, or systems. Use in such applications are -- 10 | -- expressly prohibited. -- 11 | -- -- 12 | -- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. -- 13 | ---------------------------------------------------------------------- 14 | 15 | -- You must compile the wrapper file asyn_fifo_distrib_64.vhd when simulating 16 | -- the core, asyn_fifo_distrib_64. When compiling the wrapper file, be sure to 17 | -- reference the XilinxCoreLib VHDL simulation library. For detailed 18 | -- instructions, please refer to the "Coregen Users Guide". 19 | 20 | -- The synopsys directives "translate_off/translate_on" specified 21 | -- below are supported by XST, FPGA Express, Exemplar and Synplicity 22 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). 23 | 24 | -- synopsys translate_off 25 | LIBRARY ieee; 26 | USE ieee.std_logic_1164.ALL; 27 | 28 | Library XilinxCoreLib; 29 | ENTITY asyn_fifo_distrib_64 IS 30 | port ( 31 | din: IN std_logic_VECTOR(15 downto 0); 32 | wr_en: IN std_logic; 33 | wr_clk: IN std_logic; 34 | rd_en: IN std_logic; 35 | rd_clk: IN std_logic; 36 | ainit: IN std_logic; 37 | dout: OUT std_logic_VECTOR(15 downto 0); 38 | full: OUT std_logic; 39 | empty: OUT std_logic; 40 | almost_full: OUT std_logic; 41 | almost_empty: OUT std_logic; 42 | wr_count: OUT std_logic_VECTOR(3 downto 0); 43 | rd_count: OUT std_logic_VECTOR(3 downto 0)); 44 | END asyn_fifo_distrib_64; 45 | 46 | ARCHITECTURE asyn_fifo_distrib_64_a OF asyn_fifo_distrib_64 IS 47 | 48 | component wrapped_asyn_fifo_distrib_64 49 | port ( 50 | din: IN std_logic_VECTOR(15 downto 0); 51 | wr_en: IN std_logic; 52 | wr_clk: IN std_logic; 53 | rd_en: IN std_logic; 54 | rd_clk: IN std_logic; 55 | ainit: IN std_logic; 56 | dout: OUT std_logic_VECTOR(15 downto 0); 57 | full: OUT std_logic; 58 | empty: OUT std_logic; 59 | almost_full: OUT std_logic; 60 | almost_empty: OUT std_logic; 61 | wr_count: OUT std_logic_VECTOR(3 downto 0); 62 | rd_count: OUT std_logic_VECTOR(3 downto 0)); 63 | end component; 64 | 65 | -- Configuration specification 66 | for all : wrapped_asyn_fifo_distrib_64 use entity XilinxCoreLib.async_fifo_v3_0(behavioral) 67 | generic map( 68 | c_wr_count_width => 4, 69 | c_has_rd_err => 0, 70 | c_data_width => 16, 71 | c_has_almost_full => 1, 72 | c_rd_err_low => 0, 73 | c_has_wr_ack => 0, 74 | c_wr_ack_low => 0, 75 | c_fifo_depth => 63, 76 | c_rd_count_width => 4, 77 | c_has_wr_err => 0, 78 | c_has_almost_empty => 1, 79 | c_rd_ack_low => 0, 80 | c_has_wr_count => 1, 81 | c_use_blockmem => 0, 82 | c_has_rd_ack => 0, 83 | c_has_rd_count => 1, 84 | c_wr_err_low => 0, 85 | c_enable_rlocs => 0); 86 | BEGIN 87 | 88 | U0 : wrapped_asyn_fifo_distrib_64 89 | port map ( 90 | din => din, 91 | wr_en => wr_en, 92 | wr_clk => wr_clk, 93 | rd_en => rd_en, 94 | rd_clk => rd_clk, 95 | ainit => ainit, 96 | dout => dout, 97 | full => full, 98 | empty => empty, 99 | almost_full => almost_full, 100 | almost_empty => almost_empty, 101 | wr_count => wr_count, 102 | rd_count => rd_count); 103 | END asyn_fifo_distrib_64_a; 104 | 105 | -- synopsys translate_on 106 | 107 | -------------------------------------------------------------------------------- /src/block_ram_2kx16.edn: -------------------------------------------------------------------------------- 1 | (edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) 2 | (status (written (timeStamp 2002 3 8 12 36 48) 3 | (author "Xilinx, Inc.") 4 | (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 4.1i")))) 5 | (comment "This file is owned and controlled by Xilinx and must be used 6 | solely for design, simulation, implementation and creation of design files 7 | limited to Xilinx devices or technologies. Use with non-Xilinx devices or 8 | technologies is expressly prohibited and immediately terminates your license. 9 | Xilinx products are not intended for use in life support appliances, devices, 10 | or systems. Use in such applications are expressly prohibited. 11 | Copyright (C) 2001, Xilinx, Inc. All Rights Reserved.") 12 | (comment "Core parameters: ") 13 | (comment "c_sinit_value = 0 ") 14 | (comment "c_has_en = 0 ") 15 | (comment "c_reg_inputs = 0 ") 16 | (comment "c_has_limit_data_pitch = 0 ") 17 | (comment "c_has_rdy = 0 ") 18 | (comment "c_write_mode = 0 ") 19 | (comment "c_width = 16 ") 20 | (comment "c_has_nd = 0 ") 21 | (comment "c_has_we = 1 ") 22 | (comment "c_enable_rlocs = 0 ") 23 | (comment "c_has_rfd = 0 ") 24 | (comment "c_has_din = 1 ") 25 | (comment "c_pipe_stages = 0 ") 26 | (comment "c_family = virtex ") 27 | (comment "InstanceName = block_ram_2kx16 ") 28 | (comment "c_depth = 2047 ") 29 | (comment "c_has_default_data = 1 ") 30 | (comment "c_limit_data_pitch = 8 ") 31 | (comment "c_has_sinit = 1 ") 32 | (comment "c_mem_init_file = mif_file_16_1 ") 33 | (comment "c_default_data = 0 ") 34 | (comment "c_addr_width = 11 ") 35 | (external xilinxun (edifLevel 0) 36 | (technology (numberDefinition)) 37 | (cell VCC (cellType GENERIC) 38 | (view view_1 (viewType NETLIST) 39 | (interface 40 | (port P (direction OUTPUT)) 41 | ) 42 | ) 43 | ) 44 | (cell GND (cellType GENERIC) 45 | (view view_1 (viewType NETLIST) 46 | (interface 47 | (port G (direction OUTPUT)) 48 | ) 49 | ) 50 | ) 51 | (cell RAMB4_S2 (cellType GENERIC) 52 | (view view_1 (viewType NETLIST) 53 | (interface 54 | (port WE (direction INPUT)) 55 | (port EN (direction INPUT)) 56 | (port RST (direction INPUT)) 57 | (port CLK (direction INPUT)) 58 | (port (rename DI_0_ "DI<0>") (direction INPUT)) 59 | (port (rename DI_1_ "DI<1>") (direction INPUT)) 60 | (port (rename DO_0_ "DO<0>") (direction OUTPUT)) 61 | (port (rename DO_1_ "DO<1>") (direction OUTPUT)) 62 | (port (rename ADDR_0_ "ADDR<0>") (direction INPUT)) 63 | (port (rename ADDR_1_ "ADDR<1>") (direction INPUT)) 64 | (port (rename ADDR_2_ "ADDR<2>") (direction INPUT)) 65 | (port (rename ADDR_3_ "ADDR<3>") (direction INPUT)) 66 | (port (rename ADDR_4_ "ADDR<4>") (direction INPUT)) 67 | (port (rename ADDR_5_ "ADDR<5>") (direction INPUT)) 68 | (port (rename ADDR_6_ "ADDR<6>") (direction INPUT)) 69 | (port (rename ADDR_7_ "ADDR<7>") (direction INPUT)) 70 | (port (rename ADDR_8_ "ADDR<8>") (direction INPUT)) 71 | (port (rename ADDR_9_ "ADDR<9>") (direction INPUT)) 72 | (port (rename ADDR_10_ "ADDR<10>") (direction INPUT)) 73 | ) 74 | ) 75 | ) 76 | ) 77 | (library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time)))) 78 | (cell block_ram_2kx16 79 | (cellType GENERIC) (view view_1 (viewType NETLIST) 80 | (interface 81 | (port ( rename addr_10_ "addr(10)") (direction INPUT)) 82 | (port ( rename addr_9_ "addr(9)") (direction INPUT)) 83 | (port ( rename addr_8_ "addr(8)") (direction INPUT)) 84 | (port ( rename addr_7_ "addr(7)") (direction INPUT)) 85 | (port ( rename addr_6_ "addr(6)") (direction INPUT)) 86 | (port ( rename addr_5_ "addr(5)") (direction INPUT)) 87 | (port ( rename addr_4_ "addr(4)") (direction INPUT)) 88 | (port ( rename addr_3_ "addr(3)") (direction INPUT)) 89 | (port ( rename addr_2_ "addr(2)") (direction INPUT)) 90 | (port ( rename addr_1_ "addr(1)") (direction INPUT)) 91 | (port ( rename addr_0_ "addr(0)") (direction INPUT)) 92 | (port ( rename clk "clk") (direction INPUT)) 93 | (port ( rename din_15_ "din(15)") (direction INPUT)) 94 | (port ( rename din_14_ "din(14)") (direction INPUT)) 95 | (port ( rename din_13_ "din(13)") (direction INPUT)) 96 | (port ( rename din_12_ "din(12)") (direction INPUT)) 97 | (port ( rename din_11_ "din(11)") (direction INPUT)) 98 | (port ( rename din_10_ "din(10)") (direction INPUT)) 99 | (port ( rename din_9_ "din(9)") (direction INPUT)) 100 | (port ( rename din_8_ "din(8)") (direction INPUT)) 101 | (port ( rename din_7_ "din(7)") (direction INPUT)) 102 | (port ( rename din_6_ "din(6)") (direction INPUT)) 103 | (port ( rename din_5_ "din(5)") (direction INPUT)) 104 | (port ( rename din_4_ "din(4)") (direction INPUT)) 105 | (port ( rename din_3_ "din(3)") (direction INPUT)) 106 | (port ( rename din_2_ "din(2)") (direction INPUT)) 107 | (port ( rename din_1_ "din(1)") (direction INPUT)) 108 | (port ( rename din_0_ "din(0)") (direction INPUT)) 109 | (port ( rename sinit "sinit") (direction INPUT)) 110 | (port ( rename we "we") (direction INPUT)) 111 | (port ( rename dout_15_ "dout(15)") (direction OUTPUT)) 112 | (port ( rename dout_14_ "dout(14)") (direction OUTPUT)) 113 | (port ( rename dout_13_ "dout(13)") (direction OUTPUT)) 114 | (port ( rename dout_12_ "dout(12)") (direction OUTPUT)) 115 | (port ( rename dout_11_ "dout(11)") (direction OUTPUT)) 116 | (port ( rename dout_10_ "dout(10)") (direction OUTPUT)) 117 | (port ( rename dout_9_ "dout(9)") (direction OUTPUT)) 118 | (port ( rename dout_8_ "dout(8)") (direction OUTPUT)) 119 | (port ( rename dout_7_ "dout(7)") (direction OUTPUT)) 120 | (port ( rename dout_6_ "dout(6)") (direction OUTPUT)) 121 | (port ( rename dout_5_ "dout(5)") (direction OUTPUT)) 122 | (port ( rename dout_4_ "dout(4)") (direction OUTPUT)) 123 | (port ( rename dout_3_ "dout(3)") (direction OUTPUT)) 124 | (port ( rename dout_2_ "dout(2)") (direction OUTPUT)) 125 | (port ( rename dout_1_ "dout(1)") (direction OUTPUT)) 126 | (port ( rename dout_0_ "dout(0)") (direction OUTPUT)) 127 | ) 128 | (contents 129 | (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun)))) 130 | (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun)))) 131 | (instance B5 132 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 133 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 134 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 135 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 136 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 137 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 138 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 139 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 140 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 141 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 142 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 143 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 144 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 145 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 146 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 147 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 148 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 149 | ) 150 | (instance B9 151 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 152 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 153 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 154 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 155 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 156 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 157 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 158 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 159 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 160 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 161 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 162 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 163 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 164 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 165 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 166 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 167 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 168 | ) 169 | (instance B13 170 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 171 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 172 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 173 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 174 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 175 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 176 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 177 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 178 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 179 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 180 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 181 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 182 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 183 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 184 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 185 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 186 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 187 | ) 188 | (instance B17 189 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 190 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 191 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 192 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 193 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 194 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 195 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 196 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 197 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 198 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 199 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 200 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 201 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 202 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 203 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 204 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 205 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 206 | ) 207 | (instance B21 208 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 209 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 210 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 211 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 212 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 213 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 214 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 215 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 216 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 217 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 218 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 219 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 220 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 221 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 222 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 223 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 224 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 225 | ) 226 | (instance B25 227 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 228 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 229 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 230 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 231 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 232 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 233 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 234 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 235 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 236 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 237 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 238 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 239 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 240 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 241 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 242 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 243 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 244 | ) 245 | (instance B29 246 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 247 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 248 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 249 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 250 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 251 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 252 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 253 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 254 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 255 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 256 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 257 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 258 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 259 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 260 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 261 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 262 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 263 | ) 264 | (instance B33 265 | (viewRef view_1 (cellRef RAMB4_S2 (libraryRef xilinxun))) 266 | (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) 267 | (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) 268 | (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) 269 | (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) 270 | (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) 271 | (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) 272 | (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) 273 | (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) 274 | (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) 275 | (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) 276 | (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) 277 | (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) 278 | (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) 279 | (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) 280 | (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) 281 | (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) 282 | ) 283 | (net N1 284 | (joined 285 | (portRef P (instanceRef VCC)) 286 | (portRef EN (instanceRef B5)) 287 | (portRef EN (instanceRef B9)) 288 | (portRef EN (instanceRef B13)) 289 | (portRef EN (instanceRef B17)) 290 | (portRef EN (instanceRef B21)) 291 | (portRef EN (instanceRef B25)) 292 | (portRef EN (instanceRef B29)) 293 | (portRef EN (instanceRef B33)) 294 | ) 295 | ) 296 | (net (rename N115 "addr(10)") 297 | (joined 298 | (portRef addr_10_) 299 | (portRef ADDR_10_ (instanceRef B5)) 300 | (portRef ADDR_10_ (instanceRef B9)) 301 | (portRef ADDR_10_ (instanceRef B13)) 302 | (portRef ADDR_10_ (instanceRef B17)) 303 | (portRef ADDR_10_ (instanceRef B21)) 304 | (portRef ADDR_10_ (instanceRef B25)) 305 | (portRef ADDR_10_ (instanceRef B29)) 306 | (portRef ADDR_10_ (instanceRef B33)) 307 | ) 308 | ) 309 | (net (rename N116 "addr(9)") 310 | (joined 311 | (portRef addr_9_) 312 | (portRef ADDR_9_ (instanceRef B5)) 313 | (portRef ADDR_9_ (instanceRef B9)) 314 | (portRef ADDR_9_ (instanceRef B13)) 315 | (portRef ADDR_9_ (instanceRef B17)) 316 | (portRef ADDR_9_ (instanceRef B21)) 317 | (portRef ADDR_9_ (instanceRef B25)) 318 | (portRef ADDR_9_ (instanceRef B29)) 319 | (portRef ADDR_9_ (instanceRef B33)) 320 | ) 321 | ) 322 | (net (rename N117 "addr(8)") 323 | (joined 324 | (portRef addr_8_) 325 | (portRef ADDR_8_ (instanceRef B5)) 326 | (portRef ADDR_8_ (instanceRef B9)) 327 | (portRef ADDR_8_ (instanceRef B13)) 328 | (portRef ADDR_8_ (instanceRef B17)) 329 | (portRef ADDR_8_ (instanceRef B21)) 330 | (portRef ADDR_8_ (instanceRef B25)) 331 | (portRef ADDR_8_ (instanceRef B29)) 332 | (portRef ADDR_8_ (instanceRef B33)) 333 | ) 334 | ) 335 | (net (rename N118 "addr(7)") 336 | (joined 337 | (portRef addr_7_) 338 | (portRef ADDR_7_ (instanceRef B5)) 339 | (portRef ADDR_7_ (instanceRef B9)) 340 | (portRef ADDR_7_ (instanceRef B13)) 341 | (portRef ADDR_7_ (instanceRef B17)) 342 | (portRef ADDR_7_ (instanceRef B21)) 343 | (portRef ADDR_7_ (instanceRef B25)) 344 | (portRef ADDR_7_ (instanceRef B29)) 345 | (portRef ADDR_7_ (instanceRef B33)) 346 | ) 347 | ) 348 | (net (rename N119 "addr(6)") 349 | (joined 350 | (portRef addr_6_) 351 | (portRef ADDR_6_ (instanceRef B5)) 352 | (portRef ADDR_6_ (instanceRef B9)) 353 | (portRef ADDR_6_ (instanceRef B13)) 354 | (portRef ADDR_6_ (instanceRef B17)) 355 | (portRef ADDR_6_ (instanceRef B21)) 356 | (portRef ADDR_6_ (instanceRef B25)) 357 | (portRef ADDR_6_ (instanceRef B29)) 358 | (portRef ADDR_6_ (instanceRef B33)) 359 | ) 360 | ) 361 | (net (rename N120 "addr(5)") 362 | (joined 363 | (portRef addr_5_) 364 | (portRef ADDR_5_ (instanceRef B5)) 365 | (portRef ADDR_5_ (instanceRef B9)) 366 | (portRef ADDR_5_ (instanceRef B13)) 367 | (portRef ADDR_5_ (instanceRef B17)) 368 | (portRef ADDR_5_ (instanceRef B21)) 369 | (portRef ADDR_5_ (instanceRef B25)) 370 | (portRef ADDR_5_ (instanceRef B29)) 371 | (portRef ADDR_5_ (instanceRef B33)) 372 | ) 373 | ) 374 | (net (rename N121 "addr(4)") 375 | (joined 376 | (portRef addr_4_) 377 | (portRef ADDR_4_ (instanceRef B5)) 378 | (portRef ADDR_4_ (instanceRef B9)) 379 | (portRef ADDR_4_ (instanceRef B13)) 380 | (portRef ADDR_4_ (instanceRef B17)) 381 | (portRef ADDR_4_ (instanceRef B21)) 382 | (portRef ADDR_4_ (instanceRef B25)) 383 | (portRef ADDR_4_ (instanceRef B29)) 384 | (portRef ADDR_4_ (instanceRef B33)) 385 | ) 386 | ) 387 | (net (rename N122 "addr(3)") 388 | (joined 389 | (portRef addr_3_) 390 | (portRef ADDR_3_ (instanceRef B5)) 391 | (portRef ADDR_3_ (instanceRef B9)) 392 | (portRef ADDR_3_ (instanceRef B13)) 393 | (portRef ADDR_3_ (instanceRef B17)) 394 | (portRef ADDR_3_ (instanceRef B21)) 395 | (portRef ADDR_3_ (instanceRef B25)) 396 | (portRef ADDR_3_ (instanceRef B29)) 397 | (portRef ADDR_3_ (instanceRef B33)) 398 | ) 399 | ) 400 | (net (rename N123 "addr(2)") 401 | (joined 402 | (portRef addr_2_) 403 | (portRef ADDR_2_ (instanceRef B5)) 404 | (portRef ADDR_2_ (instanceRef B9)) 405 | (portRef ADDR_2_ (instanceRef B13)) 406 | (portRef ADDR_2_ (instanceRef B17)) 407 | (portRef ADDR_2_ (instanceRef B21)) 408 | (portRef ADDR_2_ (instanceRef B25)) 409 | (portRef ADDR_2_ (instanceRef B29)) 410 | (portRef ADDR_2_ (instanceRef B33)) 411 | ) 412 | ) 413 | (net (rename N124 "addr(1)") 414 | (joined 415 | (portRef addr_1_) 416 | (portRef ADDR_1_ (instanceRef B5)) 417 | (portRef ADDR_1_ (instanceRef B9)) 418 | (portRef ADDR_1_ (instanceRef B13)) 419 | (portRef ADDR_1_ (instanceRef B17)) 420 | (portRef ADDR_1_ (instanceRef B21)) 421 | (portRef ADDR_1_ (instanceRef B25)) 422 | (portRef ADDR_1_ (instanceRef B29)) 423 | (portRef ADDR_1_ (instanceRef B33)) 424 | ) 425 | ) 426 | (net (rename N125 "addr(0)") 427 | (joined 428 | (portRef addr_0_) 429 | (portRef ADDR_0_ (instanceRef B5)) 430 | (portRef ADDR_0_ (instanceRef B9)) 431 | (portRef ADDR_0_ (instanceRef B13)) 432 | (portRef ADDR_0_ (instanceRef B17)) 433 | (portRef ADDR_0_ (instanceRef B21)) 434 | (portRef ADDR_0_ (instanceRef B25)) 435 | (portRef ADDR_0_ (instanceRef B29)) 436 | (portRef ADDR_0_ (instanceRef B33)) 437 | ) 438 | ) 439 | (net (rename N126 "clk") 440 | (joined 441 | (portRef clk) 442 | (portRef CLK (instanceRef B5)) 443 | (portRef CLK (instanceRef B9)) 444 | (portRef CLK (instanceRef B13)) 445 | (portRef CLK (instanceRef B17)) 446 | (portRef CLK (instanceRef B21)) 447 | (portRef CLK (instanceRef B25)) 448 | (portRef CLK (instanceRef B29)) 449 | (portRef CLK (instanceRef B33)) 450 | ) 451 | ) 452 | (net (rename N127 "din(15)") 453 | (joined 454 | (portRef din_15_) 455 | (portRef DI_1_ (instanceRef B33)) 456 | ) 457 | ) 458 | (net (rename N128 "din(14)") 459 | (joined 460 | (portRef din_14_) 461 | (portRef DI_0_ (instanceRef B33)) 462 | ) 463 | ) 464 | (net (rename N129 "din(13)") 465 | (joined 466 | (portRef din_13_) 467 | (portRef DI_1_ (instanceRef B29)) 468 | ) 469 | ) 470 | (net (rename N130 "din(12)") 471 | (joined 472 | (portRef din_12_) 473 | (portRef DI_0_ (instanceRef B29)) 474 | ) 475 | ) 476 | (net (rename N131 "din(11)") 477 | (joined 478 | (portRef din_11_) 479 | (portRef DI_1_ (instanceRef B25)) 480 | ) 481 | ) 482 | (net (rename N132 "din(10)") 483 | (joined 484 | (portRef din_10_) 485 | (portRef DI_0_ (instanceRef B25)) 486 | ) 487 | ) 488 | (net (rename N133 "din(9)") 489 | (joined 490 | (portRef din_9_) 491 | (portRef DI_1_ (instanceRef B21)) 492 | ) 493 | ) 494 | (net (rename N134 "din(8)") 495 | (joined 496 | (portRef din_8_) 497 | (portRef DI_0_ (instanceRef B21)) 498 | ) 499 | ) 500 | (net (rename N135 "din(7)") 501 | (joined 502 | (portRef din_7_) 503 | (portRef DI_1_ (instanceRef B17)) 504 | ) 505 | ) 506 | (net (rename N136 "din(6)") 507 | (joined 508 | (portRef din_6_) 509 | (portRef DI_0_ (instanceRef B17)) 510 | ) 511 | ) 512 | (net (rename N137 "din(5)") 513 | (joined 514 | (portRef din_5_) 515 | (portRef DI_1_ (instanceRef B13)) 516 | ) 517 | ) 518 | (net (rename N138 "din(4)") 519 | (joined 520 | (portRef din_4_) 521 | (portRef DI_0_ (instanceRef B13)) 522 | ) 523 | ) 524 | (net (rename N139 "din(3)") 525 | (joined 526 | (portRef din_3_) 527 | (portRef DI_1_ (instanceRef B9)) 528 | ) 529 | ) 530 | (net (rename N140 "din(2)") 531 | (joined 532 | (portRef din_2_) 533 | (portRef DI_0_ (instanceRef B9)) 534 | ) 535 | ) 536 | (net (rename N141 "din(1)") 537 | (joined 538 | (portRef din_1_) 539 | (portRef DI_1_ (instanceRef B5)) 540 | ) 541 | ) 542 | (net (rename N142 "din(0)") 543 | (joined 544 | (portRef din_0_) 545 | (portRef DI_0_ (instanceRef B5)) 546 | ) 547 | ) 548 | (net (rename N143 "dout(15)") 549 | (joined 550 | (portRef dout_15_) 551 | (portRef DO_1_ (instanceRef B33)) 552 | ) 553 | ) 554 | (net (rename N144 "dout(14)") 555 | (joined 556 | (portRef dout_14_) 557 | (portRef DO_0_ (instanceRef B33)) 558 | ) 559 | ) 560 | (net (rename N145 "dout(13)") 561 | (joined 562 | (portRef dout_13_) 563 | (portRef DO_1_ (instanceRef B29)) 564 | ) 565 | ) 566 | (net (rename N146 "dout(12)") 567 | (joined 568 | (portRef dout_12_) 569 | (portRef DO_0_ (instanceRef B29)) 570 | ) 571 | ) 572 | (net (rename N147 "dout(11)") 573 | (joined 574 | (portRef dout_11_) 575 | (portRef DO_1_ (instanceRef B25)) 576 | ) 577 | ) 578 | (net (rename N148 "dout(10)") 579 | (joined 580 | (portRef dout_10_) 581 | (portRef DO_0_ (instanceRef B25)) 582 | ) 583 | ) 584 | (net (rename N149 "dout(9)") 585 | (joined 586 | (portRef dout_9_) 587 | (portRef DO_1_ (instanceRef B21)) 588 | ) 589 | ) 590 | (net (rename N150 "dout(8)") 591 | (joined 592 | (portRef dout_8_) 593 | (portRef DO_0_ (instanceRef B21)) 594 | ) 595 | ) 596 | (net (rename N151 "dout(7)") 597 | (joined 598 | (portRef dout_7_) 599 | (portRef DO_1_ (instanceRef B17)) 600 | ) 601 | ) 602 | (net (rename N152 "dout(6)") 603 | (joined 604 | (portRef dout_6_) 605 | (portRef DO_0_ (instanceRef B17)) 606 | ) 607 | ) 608 | (net (rename N153 "dout(5)") 609 | (joined 610 | (portRef dout_5_) 611 | (portRef DO_1_ (instanceRef B13)) 612 | ) 613 | ) 614 | (net (rename N154 "dout(4)") 615 | (joined 616 | (portRef dout_4_) 617 | (portRef DO_0_ (instanceRef B13)) 618 | ) 619 | ) 620 | (net (rename N155 "dout(3)") 621 | (joined 622 | (portRef dout_3_) 623 | (portRef DO_1_ (instanceRef B9)) 624 | ) 625 | ) 626 | (net (rename N156 "dout(2)") 627 | (joined 628 | (portRef dout_2_) 629 | (portRef DO_0_ (instanceRef B9)) 630 | ) 631 | ) 632 | (net (rename N157 "dout(1)") 633 | (joined 634 | (portRef dout_1_) 635 | (portRef DO_1_ (instanceRef B5)) 636 | ) 637 | ) 638 | (net (rename N158 "dout(0)") 639 | (joined 640 | (portRef dout_0_) 641 | (portRef DO_0_ (instanceRef B5)) 642 | ) 643 | ) 644 | (net (rename N163 "sinit") 645 | (joined 646 | (portRef sinit) 647 | (portRef RST (instanceRef B5)) 648 | (portRef RST (instanceRef B9)) 649 | (portRef RST (instanceRef B13)) 650 | (portRef RST (instanceRef B17)) 651 | (portRef RST (instanceRef B21)) 652 | (portRef RST (instanceRef B25)) 653 | (portRef RST (instanceRef B29)) 654 | (portRef RST (instanceRef B33)) 655 | ) 656 | ) 657 | (net (rename N164 "we") 658 | (joined 659 | (portRef we) 660 | (portRef WE (instanceRef B5)) 661 | (portRef WE (instanceRef B9)) 662 | (portRef WE (instanceRef B13)) 663 | (portRef WE (instanceRef B17)) 664 | (portRef WE (instanceRef B21)) 665 | (portRef WE (instanceRef B25)) 666 | (portRef WE (instanceRef B29)) 667 | (portRef WE (instanceRef B33)) 668 | ) 669 | ) 670 | )))) 671 | (design block_ram_2kx16 (cellRef block_ram_2kx16 (libraryRef test_lib)) 672 | (property PART (string "XCV100BG256") (owner "Xilinx"))) 673 | ) 674 | -------------------------------------------------------------------------------- /src/block_ram_2kx16.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------- 2 | -- This file is owned and controlled by Xilinx and must be used -- 3 | -- solely for design, simulation, implementation and creation of -- 4 | -- design files limited to Xilinx devices or technologies. Use -- 5 | -- with non-Xilinx devices or technologies is expressly prohibited -- 6 | -- and immediately terminates your license. -- 7 | -- -- 8 | -- Xilinx products are not intended for use in life support -- 9 | -- appliances, devices, or systems. Use in such applications are -- 10 | -- expressly prohibited. -- 11 | -- -- 12 | -- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. -- 13 | ---------------------------------------------------------------------- 14 | 15 | -- You must compile the wrapper file block_ram_2kx16.vhd when simulating 16 | -- the core, block_ram_2kx16. When compiling the wrapper file, be sure to 17 | -- reference the XilinxCoreLib VHDL simulation library. For detailed 18 | -- instructions, please refer to the "Coregen Users Guide". 19 | 20 | -- The synopsys directives "translate_off/translate_on" specified 21 | -- below are supported by XST, FPGA Express, Exemplar and Synplicity 22 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). 23 | 24 | -- synopsys translate_off 25 | LIBRARY ieee; 26 | USE ieee.std_logic_1164.ALL; 27 | 28 | Library XilinxCoreLib; 29 | ENTITY block_ram_2kx16 IS 30 | port ( 31 | addr: IN std_logic_VECTOR(10 downto 0); 32 | clk: IN std_logic; 33 | din: IN std_logic_VECTOR(15 downto 0); 34 | dout: OUT std_logic_VECTOR(15 downto 0); 35 | sinit: IN std_logic; 36 | we: IN std_logic); 37 | END block_ram_2kx16; 38 | 39 | ARCHITECTURE block_ram_2kx16_a OF block_ram_2kx16 IS 40 | 41 | component wrapped_block_ram_2kx16 42 | port ( 43 | addr: IN std_logic_VECTOR(10 downto 0); 44 | clk: IN std_logic; 45 | din: IN std_logic_VECTOR(15 downto 0); 46 | dout: OUT std_logic_VECTOR(15 downto 0); 47 | sinit: IN std_logic; 48 | we: IN std_logic); 49 | end component; 50 | 51 | -- Configuration specification 52 | for all : wrapped_block_ram_2kx16 use entity XilinxCoreLib.blkmemsp_v3_1(behavioral) 53 | generic map( 54 | c_reg_inputs => 0, 55 | c_addr_width => 11, 56 | c_has_sinit => 1, 57 | c_has_rdy => 0, 58 | c_width => 16, 59 | c_has_en => 0, 60 | c_mem_init_file => "mif_file_16_1", 61 | c_depth => 2047, 62 | c_has_nd => 0, 63 | c_has_default_data => 1, 64 | c_default_data => "0", 65 | c_limit_data_pitch => 8, 66 | c_pipe_stages => 0, 67 | c_has_rfd => 0, 68 | c_has_we => 1, 69 | c_sinit_value => "0", 70 | c_has_limit_data_pitch => 0, 71 | c_enable_rlocs => 0, 72 | c_has_din => 1, 73 | c_write_mode => 0); 74 | BEGIN 75 | 76 | U0 : wrapped_block_ram_2kx16 77 | port map ( 78 | addr => addr, 79 | clk => clk, 80 | din => din, 81 | dout => dout, 82 | sinit => sinit, 83 | we => we); 84 | END block_ram_2kx16_a; 85 | 86 | -- synopsys translate_on 87 | 88 | -------------------------------------------------------------------------------- /src/clock_generation.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- clock_generation.vhd 7 | -- 8 | 9 | -- Generate multiple frequency deskewed clocks using dlls. There's some problem if 10 | -- I hold the reset asserted while waiting for the dlls to to lock I can only upload 11 | -- exactly 4 words. Seems to work OK using the async rst instead of rst_int. 12 | 13 | -- I need to manually reset it after loading the code because the dlls haven't locked on yet. 14 | -- I need a way to hold everything reset until the dlls lock 15 | 16 | --********************************************************************************** 17 | 18 | 19 | library IEEE; 20 | use IEEE.std_logic_1164.all; 21 | use IEEE.numeric_std.all; 22 | use work.comp_pckgs.all; 23 | 24 | 25 | ENTITY clock_generation IS 26 | PORT 27 | ( 28 | bufclkin : in std_logic; 29 | rst_n : in std_logic; 30 | bufsclkfb : in std_logic; --feedback clock from sdram 31 | rst_int : out std_logic; 32 | clk_12_5Mhz : out std_logic; 33 | clk_50Mhz : out std_logic; 34 | clk_100Mhz : out std_logic; 35 | sclk : out std_logic 36 | ); 37 | 38 | END clock_generation; 39 | 40 | ARCHITECTURE clock_generation_arch OF clock_generation IS 41 | 42 | signal lock : std_logic; 43 | signal dllint_clk0 : std_logic; 44 | signal bufdllint_clk0 : std_logic; 45 | signal dllint_clk2x : std_logic; 46 | signal bufdllint_clk2x : std_logic; 47 | signal dllext_clk0 : std_logic; 48 | signal locked, lockint, lockext : std_logic; 49 | signal bufdllint_clkdv : std_logic; 50 | signal dllint_clkdv : std_logic; 51 | 52 | 53 | BEGIN 54 | 55 | -- generate an internal clock sync'ed to the master clock 56 | dllint: CLKDLL 57 | generic map 58 | ( CLKDV_DIVIDE => 10) 59 | port map 60 | ( 61 | CLKIN=>bufclkin, 62 | CLKFB=>bufdllint_clk0, 63 | CLK0=>dllint_clk0, 64 | RST=>'0', 65 | CLK90=>open, 66 | CLK180=>open, 67 | CLK270=>open, 68 | CLK2X=>dllint_clk2x, 69 | CLKDV=>dllint_clkdv, 70 | LOCKED=>lockint 71 | ); 72 | 73 | -- generate an external SDRAM clock sync'ed to the master clock 74 | dllext: CLKDLL 75 | port map 76 | ( 77 | CLKIN=>bufclkin, 78 | CLKFB=>bufsclkfb, 79 | CLK0=>dllext_clk0, 80 | RST=>'0', 81 | CLK90=>open, 82 | CLK180=>open, 83 | CLK270=>open, 84 | CLK2X=>open, 85 | CLKDV=>open, 86 | LOCKED=>lockext 87 | ); 88 | 89 | 90 | clkg: BUFG port map (I=>dllint_clk0, O=>bufdllint_clk0); 91 | clkg2x: BUFG port map(I=>dllint_clk2x, O=>bufdllint_clk2x); 92 | clkhalfx: BUFG port map(I=>dllint_clkdv, O=>bufdllint_clkdv); 93 | 94 | -- output the sync'ed SDRAM clock to the SDRAM 95 | sclk <= dllext_clk0; 96 | clk_12_5Mhz <= bufdllint_clkdv; 97 | clk_50Mhz <= bufdllint_clk0; -- SDRAM controller logic clock 98 | clk_100Mhz <= bufdllint_clk2x; -- doubled clock to other FPGA logic; 99 | locked <= lockint and lockext; -- indicate lock status of the DLLs 100 | 101 | 102 | -- synchronous reset. internal reset flag is set active by config. bitstream 103 | -- and then gets reset after DLL clocks start. 104 | process(bufclkin) 105 | begin 106 | if(bufclkin'event and bufclkin='1') then 107 | if locked='0' then 108 | rst_int <= '0'; -- keep in reset until DLLs start up 109 | else 110 | rst_int <= rst_n; -- else manually activate reset with pushbutton 111 | end if; 112 | end if; 113 | end process; 114 | 115 | 116 | END clock_generation_arch; 117 | 118 | 119 | 120 | 121 | 122 | -------------------------------------------------------------------------------- /src/clockdivider.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | ENTITY clockdivider IS 6 | GENERIC ( divide_by : natural ); 7 | PORT( 8 | clk, rst : in std_logic; 9 | slow_clk : out std_logic); 10 | END clockdivider; 11 | 12 | ARCHITECTURE clockdivider_arch OF clockdivider IS 13 | BEGIN 14 | 15 | counter : process(clk, rst) 16 | 17 | variable count : integer range divide_by-1 downto 0; --100kHz from 50Mhz 18 | variable toggle : std_logic; 19 | 20 | begin 21 | --defaults 22 | count := count; 23 | toggle := toggle; 24 | 25 | if rst = '0' then 26 | toggle := '0'; 27 | count := 0; 28 | elsif clk'event and clk = '1' then 29 | if count = divide_by-1 then 30 | count := 0; 31 | toggle := not(toggle); 32 | else 33 | count := count + 1; 34 | end if; 35 | end if; 36 | 37 | 38 | slow_clk <= toggle; 39 | 40 | 41 | end process counter; 42 | 43 | END clockdivider_arch; 44 | -------------------------------------------------------------------------------- /src/comp_pckgs.vhd: -------------------------------------------------------------------------------- 1 | --**************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- comp_pckgs.vhd 7 | -- 8 | -- Contains packages common and comp_pckgs. package common 9 | -- defines some constants and functions used in the design. 10 | -- comp_pckgs define components for entities in the desin 11 | -- so they can be instantiated and used. Was easier to keep them 12 | -- here in one place then spread them throughout the design 13 | -- by defining them in the architectures. 14 | 15 | --**************************************************************** 16 | 17 | library IEEE; 18 | use IEEE.std_logic_1164.all; 19 | use IEEE.numeric_std.all; 20 | 21 | package common is 22 | 23 | constant YES: std_logic := '1'; 24 | constant NO: std_logic := '0'; 25 | constant HI: std_logic := '1'; 26 | constant LO: std_logic := '0'; 27 | function log2(v: in natural) return natural; 28 | 29 | end package common; 30 | 31 | library IEEE; 32 | use IEEE.std_logic_1164.all; 33 | use IEEE.numeric_std.all; 34 | 35 | package body common is 36 | 37 | function log2(v: in natural) return natural is 38 | variable n: natural; 39 | variable logn: natural; 40 | begin 41 | n := 1; 42 | for i in 0 to 128 loop 43 | logn := i; 44 | exit when (n>=v); 45 | n := n * 2; 46 | end loop; 47 | return logn; 48 | end function log2; 49 | 50 | end package body common; 51 | 52 | 53 | 54 | library IEEE; 55 | use IEEE.std_logic_1164.all; 56 | use IEEE.numeric_std.all; 57 | 58 | 59 | package comp_pckgs is 60 | 61 | -- Xilinx specific components 62 | component IBUFG 63 | port( 64 | O: out std_ulogic; 65 | I: in std_ulogic 66 | ); 67 | end component; 68 | 69 | component BUFG 70 | port( 71 | O: out std_ulogic; 72 | I: in std_ulogic 73 | ); 74 | end component; 75 | 76 | component BUF 77 | port( 78 | O: out std_ulogic; 79 | I: in std_ulogic 80 | ); 81 | end component; 82 | 83 | component OBUF 84 | port( 85 | O: out std_ulogic; 86 | I: in std_ulogic 87 | ); 88 | end component; 89 | 90 | component IBUF 91 | port( 92 | O: out std_ulogic; 93 | I: in std_ulogic 94 | ); 95 | end component; 96 | 97 | component CLKDLL 98 | generic ( CLKDV_DIVIDE : natural := 2); 99 | port( 100 | CLKIN: in std_ulogic := '0'; 101 | CLKFB: in std_ulogic := '0'; 102 | RST: in std_ulogic := '0'; 103 | CLK0: out std_ulogic := '0'; 104 | CLK90: out std_ulogic := '0'; 105 | CLK180: out std_ulogic := '0'; 106 | CLK270: out std_ulogic := '0'; 107 | CLK2X: out std_ulogic := '0'; 108 | CLKDV: out std_ulogic := '0'; 109 | LOCKED: out std_ulogic := '0' 110 | ); 111 | end component; 112 | 113 | -- Entities defined by me 114 | component signal_debounce 115 | generic 116 | ( 117 | delay: natural := 4 -- must be a power of 2! 2, 4, 8, 16... 118 | ); 119 | 120 | PORT 121 | ( 122 | clk_50Mhz: in std_logic; 123 | sig_in: in std_logic; --in unbuffered from the parallel port 124 | rst: in std_logic; 125 | sig_out: out std_logic 126 | 127 | ); 128 | end component; 129 | 130 | component clock_generation 131 | PORT 132 | ( 133 | bufclkin : in std_logic; 134 | rst_n : in std_logic; 135 | bufsclkfb : in std_logic; --feedback clock from sdram 136 | rst_int : out std_logic; 137 | clk_12_5Mhz : out std_logic; 138 | clk_50Mhz : out std_logic; 139 | clk_100Mhz : out std_logic; 140 | sclk : out std_logic 141 | ); 142 | end component; 143 | 144 | component clockdivider 145 | GENERIC ( divide_by : natural ); 146 | PORT( 147 | clk, rst : in std_logic; 148 | slow_clk : out std_logic 149 | ); 150 | end component; 151 | 152 | component ms_delay 153 | PORT( 154 | clk, rst, start : in std_logic; 155 | delay_complete : out std_logic 156 | ); 157 | end component; 158 | 159 | 160 | component LEDDecoder 161 | Port ( d : in std_logic_vector(3 downto 0); 162 | s : out std_logic_vector(6 downto 0)); 163 | end component; 164 | 165 | component one_shot 166 | PORT 167 | ( 168 | clk: in std_logic; 169 | sig_in: in std_logic; --in unbuffered from the parallel port 170 | rst: in std_logic; 171 | sig_out: out std_logic 172 | 173 | ); 174 | end component; 175 | 176 | component master_control_signal_generator 177 | PORT 178 | ( 179 | clk_50Mhz: in std_logic; 180 | clk_12_5Mhz : in std_logic; 181 | clk_pp: in std_logic; 182 | rst: in std_logic; 183 | cmd: in std_logic_vector(5 downto 0); 184 | start_upload: out std_logic; 185 | abort_upload: out std_logic; 186 | start_addr: out std_logic_vector(22 downto 0); 187 | end_addr: out std_logic_vector(22 downto 0); 188 | init_cycle_complete: out std_logic; 189 | 190 | init_KAC : out std_logic; 191 | sync_KAC : out std_logic; -- out KAC sync pin 192 | start_KAC : out std_logic; 193 | done_KAC : in std_logic; 194 | r_w_KAC : out std_logic; -- 0=read 1=write 195 | Addr_KAC : out std_logic_vector(7 downto 0); 196 | Data_KAC_in : out std_logic_vector(7 downto 0); 197 | Data_KAC_out: in std_logic_vector(7 downto 0) 198 | 199 | ); 200 | end component; 201 | 202 | component ram_control 203 | PORT 204 | ( 205 | clk_50Mhz: in std_logic; 206 | rst: in std_logic; 207 | 208 | -- PP ram access. Control provided by MCSG 209 | pp_data_out : out std_logic_vector(15 downto 0); 210 | start_upload : in std_logic; 211 | abort_upload : in std_logic; 212 | start_addr_upload : in std_logic_vector(22 downto 0); 213 | end_addr_upload : in std_logic_vector(22 downto 0); 214 | pp_fifo_wr_en : out std_logic; 215 | pp_fifo_need_data : in std_logic; 216 | 217 | -- Internal logic I/O 218 | rd_en_KAC : out std_logic; 219 | dout_KAC : in std_logic_vector(15 downto 0); 220 | dump_data_req_KAC : in std_logic; 221 | start_new_frame : in std_logic; 222 | 223 | -- SDRAM side 224 | cke : out std_logic; -- clock-enable to SDRAM 225 | cs_n : out std_logic; -- chip-select to SDRAM 226 | ras_n : out std_logic; -- command input to SDRAM 227 | cas_n : out std_logic; -- command input to SDRAM 228 | we_n : out std_logic; -- command input to SDRAM 229 | ba : out unsigned(1 downto 0); -- SDRAM bank address bits 230 | sAddr : out unsigned(12-1 downto 0); -- SDRAM row/column address 231 | sData : inout unsigned(16-1 downto 0);-- SDRAM in/out databus 232 | dqmh : out std_logic; -- high databits I/O mask 233 | dqml : out std_logic -- low databits I/O mask 234 | 235 | ); 236 | end component; 237 | 238 | component pp_upload 239 | PORT 240 | ( 241 | clk_50Mhz: in std_logic; 242 | clk_pp: buffer std_logic; --debounced clk from pport 243 | rst: in std_logic; 244 | pps: out std_logic_vector(6 downto 3); 245 | ppd: in std_logic_vector(6 downto 0); 246 | upload_data: in std_logic_vector(15 downto 0); --input to fifo 247 | wr_en: in std_logic; 248 | need_data: out std_logic; --indicats fifo status, use to control wr_en 249 | start_upload : in std_logic; 250 | cmd: out std_logic_vector(5 downto 0) 251 | ); 252 | end component; 253 | 254 | -- EDIF pulled in during P&R. 255 | component block_ram_2kx16 256 | port ( 257 | addr: IN std_logic_VECTOR(10 downto 0); 258 | clk: IN std_logic; 259 | din: IN std_logic_VECTOR(15 downto 0); 260 | dout: OUT std_logic_VECTOR(15 downto 0); 261 | sinit: IN std_logic; 262 | we: IN std_logic); 263 | end component; 264 | 265 | -- This is using a block ram... some of the outputs are dangling... fix it 266 | -- Parallel port 267 | component asyn_fifo_distrib 268 | port ( 269 | din: IN std_logic_VECTOR(15 downto 0); 270 | wr_en: IN std_logic; 271 | wr_clk: IN std_logic; 272 | rd_en: IN std_logic; 273 | rd_clk: IN std_logic; 274 | ainit: IN std_logic; 275 | dout: OUT std_logic_VECTOR(15 downto 0); 276 | full: OUT std_logic; 277 | empty: OUT std_logic; 278 | almost_full: OUT std_logic; 279 | almost_empty: OUT std_logic; 280 | wr_count: OUT std_logic_VECTOR(3 downto 0)); 281 | end component; 282 | 283 | -- For KAC 284 | component asyn_fifo_distrib_64 285 | port ( 286 | din: IN std_logic_VECTOR(15 downto 0); 287 | wr_en: IN std_logic; 288 | wr_clk: IN std_logic; 289 | rd_en: IN std_logic; 290 | rd_clk: IN std_logic; 291 | ainit: IN std_logic; 292 | dout: OUT std_logic_VECTOR(15 downto 0); 293 | full: OUT std_logic; 294 | empty: OUT std_logic; 295 | almost_full: OUT std_logic; 296 | almost_empty: OUT std_logic; 297 | wr_count: OUT std_logic_VECTOR(3 downto 0); 298 | rd_count: OUT std_logic_VECTOR(3 downto 0)); 299 | end component; 300 | 301 | component KAC_i2c 302 | generic ( I2C_ADDR : std_logic_vector(6 downto 0) ); 303 | port ( 304 | clk : in std_logic; 305 | nReset : in std_logic; 306 | start_KAC : in std_logic; 307 | done_KAC : out std_logic; 308 | r_w_KAC : in std_logic; --0=read 1=write 309 | Addr_KAC : in std_logic_vector(7 downto 0); 310 | Data_KAC_in : in std_logic_vector(7 downto 0); 311 | Data_KAC_out: out std_logic_vector(7 downto 0); 312 | 313 | SCL : inout std_logic; 314 | SDA : inout std_logic 315 | ); 316 | end component; 317 | 318 | component KAC_data 319 | PORT 320 | ( 321 | clk_50Mhz : in std_logic; 322 | clk_12_5Mhz : in std_logic; 323 | rst : in std_logic; 324 | 325 | -- Internal logic I/O 326 | rd_en : in std_logic; 327 | dout : out std_logic_vector(15 downto 0); 328 | dump_data_req : out std_logic; 329 | start_new_frame : out std_logic; 330 | init_cycle_complete : in std_logic; 331 | 332 | -- KAC-1310 I/O 333 | sof_KAC : in std_logic; 334 | vclk_KAC : in std_logic; 335 | hclk_KAC : in std_logic; 336 | pix_KAC : in std_logic_vector(9 downto 0) 337 | ); 338 | 339 | END component; 340 | 341 | 342 | 343 | component sdramCntl 344 | generic( 345 | FREQ: natural := 50_000; -- operating frequency in KHz 346 | DATA_WIDTH: natural := 16; -- host & SDRAM data width 347 | HADDR_WIDTH: natural := 23; -- host-side address width 348 | SADDR_WIDTH: natural := 12 -- SDRAM-side address width 349 | ); 350 | port( 351 | clk : in std_logic; -- master clock 352 | 353 | -- host side 354 | rst : in std_logic; -- reset 355 | rd : in std_logic; -- read data 356 | wr : in std_logic; -- write data 357 | done : out std_logic; -- read/write op done 358 | hAddr : in unsigned(HADDR_WIDTH-1 downto 0); -- address from host 359 | hDIn : in unsigned(DATA_WIDTH-1 downto 0); -- data from host 360 | hDOut : out unsigned(DATA_WIDTH-1 downto 0); -- data to host 361 | sdramCntl_state: out std_logic_vector(3 downto 0); 362 | 363 | -- SDRAM side 364 | cke : out std_logic; -- clock-enable to SDRAM 365 | cs_n : out std_logic; -- chip-select to SDRAM 366 | ras_n : out std_logic; -- command input to SDRAM 367 | cas_n : out std_logic; -- command input to SDRAM 368 | we_n : out std_logic; -- command input to SDRAM 369 | ba : out unsigned(1 downto 0); -- SDRAM bank address bits 370 | sAddr : out unsigned(SADDR_WIDTH-1 downto 0); -- row/column address 371 | sData : inout unsigned(DATA_WIDTH-1 downto 0);-- SDRAM in/out databus 372 | dqmh : out std_logic; -- high databits I/O mask 373 | dqml : out std_logic -- low databits I/O mask 374 | ); 375 | end component; 376 | 377 | -- Used by test bench 378 | component digital_camera 379 | PORT 380 | ( 381 | -- Test Ports 382 | init_cycle_complete_test_port: out std_logic; 383 | 384 | -- XSA-100 MISC 385 | clkin : in std_logic; 386 | rst : in std_logic; 387 | s : out std_logic_vector(6 downto 0); -- Segments 388 | ce_n : out std_logic; -- Flash enable 389 | dips : in std_logic_vector(3 downto 0); -- 4 Dip switches 390 | pps : out std_logic_vector(6 downto 3); -- Status pins for upload 391 | ppd : in std_logic_vector(6 downto 0); -- For download 392 | 393 | -- XSA-100 SDRAM 394 | sclkfb : in std_logic; 395 | sclk : out std_logic; 396 | cke : out std_logic; -- clock-enable to SDRAM 397 | cs_n : out std_logic; -- chip-select to SDRAM 398 | ras_n : out std_logic; -- command input to SDRAM 399 | cas_n : out std_logic; -- command input to SDRAM 400 | we_n : out std_logic; -- command input to SDRAM 401 | ba : out unsigned(1 downto 0); -- SDRAM bank address bits 402 | sAddr : out unsigned(12-1 downto 0); -- SDRAM row/column address 403 | sData : inout unsigned(16-1 downto 0);-- SDRAM in/out databus 404 | dqmh : out std_logic; -- high databits I/O mask 405 | dqml : out std_logic; -- low databits I/O mask 406 | 407 | 408 | --KAC-1310 409 | mclk_KAC : out std_logic; 410 | init_KAC : out std_logic; 411 | -- sync_KAC : out std_logic; 412 | sof_KAC : in std_logic; --Start of frame 413 | vclk_KAC : in std_logic; --Start of line 414 | hclk_KAC : in std_logic; --Pixel clk 415 | pix_KAC : in std_logic_vector(9 downto 0); -- Pixel data 416 | scl : inout std_logic; 417 | sda : inout std_logic 418 | ); 419 | END component; 420 | 421 | end package comp_pckgs; 422 | -------------------------------------------------------------------------------- /src/digital_camera.ucf: -------------------------------------------------------------------------------- 1 | # Copyright 2013, Ryan Henderson 2 | #Misc clk and reset and fash enable 3 | NET "ce_n" LOC = "p41"; # Flash RAM chip-enable 4 | net "clkin" loc="p88"; 5 | net "rst" loc="p93"; 6 | 7 | #parallel port 8 | net "pps(6)" loc="p78"; 9 | net "pps(5)" loc="p28"; 10 | net "pps(4)" loc="p29"; 11 | net "pps(3)" loc="p40"; 12 | 13 | net "ppd(0)" loc="p50"; #don't comment this... it's important 14 | net "ppd(1)" loc="p48"; 15 | net "ppd(2)" loc="p42"; 16 | net "ppd(3)" loc="p47"; 17 | net "ppd(4)" loc="p65"; 18 | net "ppd(5)" loc="p51"; 19 | net "ppd(6)" loc="p58"; 20 | 21 | #LEDs 22 | net "s(0)" loc=p67; 23 | net "s(1)" loc=p39; 24 | net "s(2)" loc=p62; 25 | net "s(3)" loc=p60; 26 | net "s(4)" loc=p46; 27 | net "s(5)" loc=p57; 28 | net "s(6)" loc=p49; 29 | 30 | #switches 31 | NET "dips(0)" LOC = "p54"; #A 32 | NET "dips(1)" LOC = "p64"; 33 | NET "dips(2)" LOC = "p63"; 34 | NET "dips(3)" LOC = "p56"; 35 | 36 | 37 | #KAC-1310 sensor 38 | NET "sda" LOC = "p85"; 39 | NET "scl" LOC = "p84"; 40 | NET "mclk_KAC" LOC = "p83"; 41 | NET "init_KAC" LOC = "p77"; 42 | NET "hclk_KAC" LOC = "p18"; 43 | NET "sof_KAC" LOC = "p79"; #assign this too! 44 | #NET "sync_KAC" LOC = ""; #not needed 45 | #NET "vclk_KAC" LOC = "p19"; 46 | 47 | 48 | 49 | #Need to think of some better pin assignments 50 | NET "pix_KAC(0)" LOC = "p21"; 51 | NET "pix_KAC(1)" LOC = "p22"; 52 | NET "pix_KAC(2)" LOC = "p23"; 53 | NET "pix_KAC(3)" LOC = "p26"; 54 | NET "pix_KAC(4)" LOC = "p20"; 55 | NET "pix_KAC(5)" LOC = "p13"; 56 | NET "pix_KAC(6)" LOC = "p80"; 57 | NET "pix_KAC(7)" LOC = "p86"; 58 | NET "pix_KAC(8)" LOC = "p87"; 59 | NET "pix_KAC(9)" LOC = "p94"; 60 | 61 | 62 | 63 | #SDRAM 64 | NET "sclkfb" LOC = "p91"; # feedback SDRAM clock after PCB delays 65 | NET "sclk" LOC = "p129"; # clock to SDRAM 66 | net "cke" LOC = "p131"; # SDRAM clock enable 67 | net "cs_n" LOC = "p132"; # SDRAM chip-select 68 | net "ras_n" LOC = "p130"; 69 | net "cas_n" LOC = "p126"; 70 | net "we_n" LOC = "p123"; 71 | net "ba(0)" loc="p134"; 72 | net ba(1) loc=p137; 73 | net sAddr(0) loc=p141; 74 | net sAddr(1) loc=p4; 75 | net sAddr(2) loc=p6; 76 | net sAddr(3) loc=p10; 77 | net sAddr(4) loc=p11; 78 | net sAddr(5) loc=p7; 79 | net sAddr(6) loc=p5; 80 | net sAddr(7) loc=p3; 81 | net sAddr(8) loc=p140; 82 | net sAddr(9) loc=p138; 83 | net sAddr(10) loc=p139; 84 | net sAddr(11) loc=p136; 85 | net sData(0) loc=p95; 86 | net sData(1) loc=p99; 87 | net sData(2) loc=p101; 88 | net sData(3) loc=p103; 89 | net sData(4) loc=p113; 90 | net sData(5) loc=p115; 91 | net sData(6) loc=p117; 92 | net sData(7) loc=p120; 93 | net sData(8) loc=p121; 94 | net sData(9) loc=p118; 95 | net sData(10) loc=p116; 96 | net sData(11) loc=p114; 97 | net sData(12) loc=p112; 98 | net sData(13) loc=p102; 99 | net sData(14) loc=p100; 100 | net sData(15) loc=p96; 101 | net "dqmh" LOC = "p124"; 102 | net "dqml" LOC = "p122"; 103 | 104 | 105 | 106 | #block ram used for testing 107 | #INST "ram_control_01_notri_B5" INIT_00 = 000F4321EEED000C000B000A0009000800070006000500040003000200010000; 108 | #INST "ram_control_01_notri_B5" INIT_01 = 001F001E001D001C001B001A0019001800170016001500140013001200110010; 109 | #INST "ram_control_01_notri_B5" INIT_02 = 002F002E002D002C002B002A0029002800270026002500240023002200210020; 110 | #INST "ram_control_01_notri_B5" INIT_03 = 003F003E003D003C003B003A0039003800370036003500340033003200310030; 111 | #INST "ram_control_01_notri_B5" INIT_04 = 004F004E004D004C004B004A0049004800470046004500440043004200410040; 112 | #INST "ram_control_01_notri_B5" INIT_05 = 005F005E005D005C005B005A0059005800570056005500540053005200510050; 113 | #INST "ram_control_01_notri_B5" INIT_06 = 006F006E006D006C006B006A0069006800670066006500640063006200610060; 114 | #INST "ram_control_01_notri_B5" INIT_07 = 007F007E007D007C007B007A0079007800770076007500740073007200710070; 115 | #INST "ram_control_01_notri_B5" INIT_08 = 008F008E008D008C008B008A0089008800870086008500840083008200810080; 116 | #INST "ram_control_01_notri_B5" INIT_09 = 009F009E009D009C009B009A0099009800970096009500940093009200910090; 117 | #INST "ram_control_01_notri_B5" INIT_0A = 00AF00AE00AD00AC00AB00AA00A900A800A700A600A500A400A300A200A100A0; 118 | #INST "ram_control_01_notri_B5" INIT_0B = 00BF00BE00BD00BC00BB00BA00B900B800B700B600B500B400B300B200B100B0; 119 | #INST "ram_control_01_notri_B5" INIT_0C = 00CF00CE00CD00CC00CB00CA00C900C800C700C600C500C400C300C200C100C0; 120 | #INST "ram_control_01_notri_B5" INIT_0D = 00DF00DE00DD00DC00DB00DA00D900D800D700D600D500D400D300D200D100D0; 121 | #INST "ram_control_01_notri_B5" INIT_0E = 00EF00EE00ED00EC00EB00EA00E900E800E700E600E500E400E300E200E100E0; 122 | #INST "ram_control_01_notri_B5" INIT_0F = 00FF00FE00FD00FC00FB00FA00F900F800F700F600F500F400F300F200F100F0; 123 | 124 | -------------------------------------------------------------------------------- /src/digital_camera.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- digital_camera.vhd 7 | -- 8 | -- Top level file for the project 9 | -- 10 | -- ppd(7) is tied to program pin. 0 is clk 11 | 12 | --********************************************************************************** 13 | 14 | 15 | 16 | library ieee; 17 | use ieee.std_logic_1164.all; 18 | use ieee.numeric_std.all; 19 | use work.comp_pckgs.all; 20 | 21 | 22 | ENTITY digital_camera IS 23 | PORT( 24 | 25 | --Test Ports 26 | init_cycle_complete_test_port: out std_logic; 27 | 28 | -- XSA-100 MISC 29 | clkin : in std_logic; 30 | rst : in std_logic; 31 | s : out std_logic_vector(6 downto 0); -- Segments 32 | ce_n : out std_logic; -- Flash enable 33 | dips : in std_logic_vector(3 downto 0); -- 4 Dip switches 34 | pps : out std_logic_vector(6 downto 3); -- pport status pins for upload 35 | ppd : in std_logic_vector(6 downto 0); -- pport data pins for download 36 | 37 | -- XSA-100 SDRAM 38 | sclkfb : in std_logic; 39 | sclk : out std_logic; 40 | cke : out std_logic; -- clock-enable to SDRAM 41 | cs_n : out std_logic; -- chip-select to SDRAM 42 | ras_n : out std_logic; -- command input to SDRAM 43 | cas_n : out std_logic; -- command input to SDRAM 44 | we_n : out std_logic; -- command input to SDRAM 45 | ba : out unsigned(1 downto 0); -- SDRAM bank address bits 46 | sAddr : out unsigned(12-1 downto 0); -- SDRAM row/column address 47 | sData : inout unsigned(16-1 downto 0);-- SDRAM in/out databus 48 | dqmh : out std_logic; -- high databits I/O mask 49 | dqml : out std_logic; -- low databits I/O mask 50 | 51 | 52 | --KAC-1310 53 | mclk_KAC : out std_logic; 54 | init_KAC : out std_logic; 55 | --sync_KAC : out std_logic; --Can also be done through I2C. Save pins 56 | sof_KAC : in std_logic; 57 | vclk_KAC : in std_logic; 58 | hclk_KAC : in std_logic; 59 | pix_KAC : in std_logic_vector(9 downto 0); 60 | scl : inout std_logic; 61 | sda : inout std_logic 62 | 63 | 64 | 65 | ); 66 | END digital_camera; 67 | 68 | ARCHITECTURE digital_camera_arch OF digital_camera IS 69 | -- Signals arranged by who outputs them 70 | 71 | -- pport_01 72 | signal clk_pp : std_logic; 73 | signal cmd : std_logic_vector(5 downto 0); 74 | signal pp_fifo_need_data : std_logic; 75 | 76 | -- MCSG_01 77 | signal start_upload : std_logic; 78 | signal abort_upload : std_logic; 79 | signal start_addr_upload : std_logic_vector(22 downto 0); 80 | signal end_addr_upload : std_logic_vector(22 downto 0); 81 | signal start_KAC : std_logic; 82 | signal r_w_KAC : std_logic; 83 | signal Data_KAC_in : std_logic_vector(7 downto 0); 84 | signal Addr_KAC : std_logic_vector(7 downto 0); 85 | signal init_cycle_complete : std_logic; 86 | 87 | -- ram_control_0 88 | signal ram_to_pp_data : std_logic_vector(15 downto 0); 89 | signal pp_fifo_wr_en : std_logic; 90 | 91 | -- KAC_I2C_01 92 | signal done_KAC : std_logic; 93 | signal Data_KAC_out : std_logic_vector(7 downto 0); 94 | 95 | -- KAC_data 96 | signal rd_en_KAC : std_logic; 97 | signal dout_KAC : std_logic_vector(15 downto 0); 98 | signal dump_data_req_KAC : std_logic; 99 | signal start_new_frame : std_logic; 100 | 101 | -- Misc used by led decoder 102 | signal display_output : std_logic_vector(3 downto 0); 103 | 104 | -- inphase_clks 105 | signal rst_int : std_logic; 106 | signal clk_12_5Mhz : std_logic; 107 | signal clk_50Mhz : std_logic; 108 | signal clk_100Mhz : std_logic; 109 | 110 | -- IBUFGs 111 | signal bufclkin : std_logic; 112 | signal bufsclkfb : std_logic; 113 | signal bufhclk_KAC : std_logic; 114 | 115 | 116 | constant KAC_I2C_ADDR : std_logic_vector(6 downto 0) := "0110011"; 117 | constant DS1621_I2C_ADDR : std_logic_vector(6 downto 0) := "1001111"; 118 | 119 | 120 | BEGIN 121 | 122 | ce_n <= '1'; 123 | mclk_KAC <= clk_12_5Mhz; 124 | 125 | --test port for sim 126 | -- init_cycle_complete_test_port <= init_cycle_complete; -- for test bench 'z' 127 | init_cycle_complete_test_port <= 'Z' ; 128 | 129 | 130 | 131 | --SDRAM Test 132 | display_output <= "00" & pix_KAC(9 downto 8) when dips = "0111" else 133 | pix_KAC(7 downto 4) when dips = "1011" else 134 | pix_KAC(3 downto 0) when dips = "1101" else 135 | "0000"; 136 | 137 | 138 | -- Just so I can use pin 18 which is a clock input, I need to put it on a global 139 | -- buffer. 140 | ibufghclk: IBUFG port map(I=>hclk_KAC, O=>bufhclk_KAC); 141 | ibufclkin: IBUFG port map(I=>clkin, O=>bufclkin); 142 | ibufsclkfb: IBUFG port map(I=>sclkfb, O=>bufsclkfb); 143 | inphase_clks: clock_generation 144 | PORT MAP 145 | ( 146 | bufclkin => bufclkin, 147 | rst_n => rst, 148 | bufsclkfb => bufsclkfb, 149 | rst_int => rst_int, 150 | clk_12_5Mhz => clk_12_5Mhz, 151 | clk_50Mhz => clk_50Mhz, 152 | clk_100Mhz => clk_100Mhz, 153 | sclk => sclk 154 | ); 155 | 156 | see_somptin: LEDDecoder 157 | PORT MAP 158 | ( 159 | d => display_output, 160 | s => s 161 | ); 162 | 163 | -- Generate a 12.5Mhz clock for the image sensor. Do this division with a dll so it 164 | -- is not skewed. Moved skew from 4ns to 2ns 165 | -- generate_m_clk_KAC: clockdivider 166 | -- GENERIC MAP ( divide_by => 5) 167 | -- PORT MAP 168 | -- ( 169 | -- clk => clkin, 170 | -- rst => rst, 171 | -- slow_clk => clk_12_5Mhz 172 | -- ); 173 | -- 174 | -- clk_50Mhz <= clkin; 175 | -- sclk <= bufsclkfb; --clkin; 176 | -- bufhclk_KAC <= hclk_KAC; 177 | 178 | -- Control module. Generates control signals based on commands from pc 179 | -- Controls KAC_I2C_01 and pport_01 modules 180 | MCSG_01: master_control_signal_generator -- um, my names are getting a little out of hand 181 | port map 182 | ( 183 | 184 | clk_50Mhz => clk_50Mhz, -- in system clk 185 | clk_12_5Mhz => clk_12_5Mhz, -- in same as mclk 186 | clk_pp => clk_pp, -- in debounced clk from pport 187 | rst => rst, -- in push button reset 188 | cmd => cmd, -- in cmds from pp_upload 189 | start_upload => start_upload, -- out signal pp_upload to start 190 | abort_upload => abort_upload, -- out signal pp_upload to abort 191 | start_addr => start_addr_upload, -- out where in memory to start upload 192 | end_addr => end_addr_upload, -- out where in memory to stop 193 | init_cycle_complete => init_cycle_complete, -- out wait for sensor & sdram 194 | 195 | init_KAC => init_KAC, -- out resets image sensor 196 | --sync_KAC => sync_KAC, -- out KAC sync pin 197 | start_KAC => start_KAC, 198 | done_KAC => done_KAC, 199 | r_w_KAC => r_w_KAC, 200 | Addr_KAC => Addr_KAC, 201 | Data_KAC_in => Data_KAC_in, -- Data to send by i2c 202 | Data_KAC_out => Data_KAC_out -- Data back from i2c ... 203 | ); 204 | 205 | -- I2C interface tailored to read and write byte wide registers in the KAC 206 | -- device. 207 | KAC_I2C_01: KAC_i2c 208 | GENERIC MAP (I2C_ADDR => KAC_I2C_ADDR) 209 | PORT MAP 210 | ( 211 | clk => clk_50Mhz, -- in system clk 212 | nReset => rst, -- in push button reset 213 | start_KAC => start_KAC, -- in start I2C transfer 214 | done_KAC => done_KAC, -- out I2C transfer done 215 | r_w_KAC => r_w_KAC, -- in direction of transfer 0 read 1 write 216 | Addr_KAC => Addr_KAC, -- in Address of register in I2C device 217 | Data_KAC_in => Data_KAC_in, -- in data to write at addressed register 218 | Data_KAC_out => Data_KAC_out, -- out data read from addressed register 219 | SCL => SCL, -- inout I2C clock line 220 | SDA => SDA -- inout I2C data line 221 | ); 222 | 223 | -- KAC pixel reader and formatter 224 | KAC_data_01: KAC_data 225 | port map 226 | ( 227 | clk_50Mhz => clk_50Mhz, -- : in std_logic; 228 | clk_12_5Mhz => clk_12_5Mhz, -- : in std_logic; 229 | rst => rst, -- : in std_logic; 230 | 231 | -- Internal logic I/O 232 | rd_en => rd_en_KAC, -- : in std_logic; 233 | dout => dout_KAC, -- : out std_logic_vector(15 downto 0); 234 | dump_data_req => dump_data_req_KAC, -- : out std_logic; 235 | start_new_frame => start_new_frame, 236 | init_cycle_complete => init_cycle_complete, 237 | 238 | -- KAC-1310 I/O 239 | sof_KAC => sof_KAC, 240 | vclk_KAC => vclk_KAC, 241 | hclk_KAC => bufhclk_KAC, 242 | pix_KAC => pix_KAC -- : in std_logic_vector(9 downto 0) 243 | ); 244 | 245 | 246 | --PPort Module 247 | pport_01: pp_upload 248 | port map 249 | ( 250 | clk_50Mhz => clk_50Mhz, -- in system clk 251 | clk_pp => clk_pp, -- out debounced clk from pport 252 | rst => rst, -- in push button reset 253 | pps => pps, -- out parallel port status pins 254 | ppd => ppd, -- in parallel port data pins including non-debounced clock 255 | 256 | upload_data => ram_to_pp_data, -- in input to fifo 257 | cmd => cmd, -- out command from the pc to mcsg 258 | start_upload => start_upload, -- reset fifo on upload start 259 | wr_en => pp_fifo_wr_en, -- in control when to write to the fifo 260 | need_data => pp_fifo_need_data -- out flag that fifo is almost empty 261 | ); 262 | 263 | 264 | ram_control_01: ram_control 265 | PORT MAP 266 | ( 267 | clk_50Mhz => clk_50Mhz, -- : in std_logic; 268 | rst => rst, -- : in std_logic; 269 | 270 | -- PPort 271 | pp_data_out => ram_to_pp_data, -- : out ..._vector(15 downto 0); 272 | start_upload => start_upload, -- : in std_logic; 273 | abort_upload => abort_upload, -- : in std_logic; 274 | start_addr_upload => start_addr_upload, -- : in ..._vector(22 downto 0); 275 | end_addr_upload => end_addr_upload, -- : in ..._vector(22 downto 0); 276 | pp_fifo_wr_en => pp_fifo_wr_en, -- : out std_logic; 277 | pp_fifo_need_data => pp_fifo_need_data, -- : in std_logic; 278 | 279 | -- KAC_data 280 | rd_en_KAC => rd_en_KAC, -- : in std_logic; 281 | dout_KAC => dout_KAC, -- : out ..._vector(15 downto 0); 282 | dump_data_req_KAC => dump_data_req_KAC, -- : out std_logic; 283 | start_new_frame => start_new_frame, 284 | 285 | 286 | -- SDRAM Controller stuff 287 | 288 | cke => cke, -- out clock-enable to SDRAM 289 | cs_n => cs_n, -- out chip-select to SDRAM 290 | ras_n => ras_n, -- out command input to SDRAM 291 | cas_n => cas_n, -- out command input to SDRAM 292 | we_n => we_n, -- out command input to SDRAM 293 | ba => ba, -- out SDRAM bank address bits 294 | sAddr => sAddr, -- out SDRAM row/column address 295 | sData => sData, -- inout SDRAM in/out databus 296 | dqmh => dqmh, -- out high databits I/O mask 297 | dqml => dqml -- out low databits I/O mask 298 | ); 299 | 300 | 301 | 302 | END digital_camera_arch; 303 | -------------------------------------------------------------------------------- /src/digital_camera_tb.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- digital_camera_tb.vhd 7 | -- 8 | -- Test bench for camera top level 9 | -- Exercises image sensor data input and parallel port output 10 | 11 | --********************************************************************************** 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use IEEE.numeric_std.all; 17 | 18 | use WORK.comp_pckgs.all; 19 | 20 | 21 | entity digital_camera_tb is 22 | end digital_camera_tb; 23 | 24 | architecture digital_camera_tb_arch of digital_camera_tb is 25 | constant RST_ACTIVE : STD_LOGIC := '0'; 26 | constant CLK_PERIOD : time := 20 nS; 27 | constant PPD_CLK_PERIOD : time := 500 nS; --It's actually alot slower 28 | 29 | constant start_addr : unsigned(22 downto 0) := (others=>'0'); 30 | constant end_addr : unsigned(22 downto 0) := to_unsigned((128*10)/2, 23); 31 | 32 | -- Size of the picture is variable to cut down on simulation time 33 | constant NUM_ROWS : integer := 10; --1024 34 | constant NUM_COLS : integer := 128; --1280; 35 | 36 | -- Test Ports 37 | signal init_cycle_complete_test_port : std_logic; 38 | 39 | -- XSA-100 interface 40 | signal rst : std_logic; 41 | signal clk : std_logic; 42 | signal ce_n : std_logic; 43 | signal s : std_logic_vector(6 downto 0); 44 | signal dips : std_logic_vector(3 downto 0); 45 | signal pps : std_logic_vector(6 downto 3); 46 | signal ppd : std_logic_vector(6 downto 0); 47 | 48 | -- SDRAM interface 49 | signal cke : std_logic; -- SDRAM clock-enable 50 | signal cs_n : std_logic; -- SDRAM chip-select 51 | signal ras_n: std_logic; -- SDRAM RAS 52 | signal cas_n: std_logic; -- SDRAM CAS 53 | signal we_n : std_logic; -- SDRAM write-enable 54 | signal ba : unsigned( 1 downto 0); -- SDRAM bank-address 55 | signal sAddr: unsigned(11 downto 0); -- SDRAM address bus 56 | signal sData: unsigned(15 downto 0); -- data bus to SDRAM 57 | signal dqmh : std_logic; -- SDRAM DQMH 58 | signal dqml : std_logic; -- SDRAM DQML 59 | signal sclk : std_logic; 60 | 61 | -- KAC interface 62 | signal mclk_KAC : std_logic; 63 | signal init_KAC : std_logic; 64 | --signal sync_KAC : std_logic; 65 | signal sof_KAC : std_logic; --Start of frame 66 | signal vclk_KAC : std_logic; --Start of line 67 | signal hclk_KAC : std_logic; --valid pixel data 68 | 69 | signal pix_KAC : std_logic_vector(9 downto 0); 70 | 71 | signal scl : std_logic; 72 | signal sda : std_logic; 73 | 74 | -- pullup used for simulation only. Matches pullup.vhd 75 | component PULLUP 76 | port(v101: OUT std_logic); 77 | end component; 78 | 79 | 80 | 81 | begin 82 | 83 | DUT: digital_camera 84 | PORT MAP 85 | ( 86 | init_cycle_complete_test_port => init_cycle_complete_test_port, 87 | 88 | -- XSA-100 MISC 89 | clkin => clk, 90 | rst => rst, 91 | s => s, 92 | ce_n => ce_n, 93 | dips => dips, 94 | pps => pps, 95 | ppd => ppd, 96 | 97 | -- XSA-100 SDRAM 98 | sclkfb => sclk, --without the dlls, it's not even used 99 | sclk => sclk, 100 | cke => cke, 101 | cs_n => cs_n, 102 | ras_n => ras_n, 103 | cas_n => cas_n, 104 | we_n => we_n, 105 | ba => ba, 106 | sAddr => sAddr, 107 | sData => sData, 108 | dqmh => dqmh, 109 | dqml => dqml, 110 | 111 | 112 | --KAC-1310 113 | mclk_KAC => mclk_KAC, 114 | init_KAC => init_KAC, 115 | --sync_KAC => sync_KAC, 116 | sof_KAC => sof_KAC, 117 | vclk_KAC => vclk_KAC, 118 | hclk_KAC => hclk_KAC, 119 | pix_KAC => pix_KAC, 120 | scl => scl, 121 | sda => sda 122 | ); 123 | 124 | --Pull up the I2C lines for simulation 125 | v109: PULLUP 126 | port map(v101 => scl); 127 | 128 | v110: PULLUP 129 | port map(v101 => sda); 130 | 131 | 132 | 133 | 134 | CREATE_CLK: process 135 | variable i : integer := 0; 136 | begin 137 | if i <= 2 then 138 | i := i + 1; 139 | rst <= RST_ACTIVE; 140 | else 141 | rst <= not(RST_ACTIVE); 142 | end if; 143 | 144 | CLK <= '0'; 145 | wait for CLK_PERIOD/2; 146 | CLK <= '1'; 147 | wait for CLK_PERIOD/2; 148 | 149 | end process; 150 | 151 | 152 | 153 | sData <= "0000" & sAddr when we_n = '1' else (others=>'0'); 154 | 155 | video_sync_signals: process 156 | variable i : integer := 0; 157 | variable j : integer := 0; 158 | variable k : integer := 0; 159 | 160 | begin 161 | 162 | sof_KAC <= '0'; 163 | vclk_KAC <= '0'; 164 | hclk_KAC <= '0'; 165 | 166 | wait until rst /= RST_ACTIVE; 167 | wait until init_cycle_complete_test_port = '1'; -- 0 active 168 | 169 | loop 170 | sof_KAC <= '1'; 171 | 172 | -- 8 m_clk delay after sof till first vclk 173 | for i in 0 to 7 loop 174 | wait until mclk_KAC'event and mclk_KAC = '1'; 175 | end loop; 176 | 177 | for i in 0 to NUM_ROWS-1 loop 178 | vclk_KAC <= '1'; 179 | for i in 0 to 63 loop --vclk 0 after 64 mclk 180 | wait until mclk_KAC'event and mclk_KAC = '1'; 181 | end loop; 182 | vclk_KAC <= '0'; 183 | 184 | for j in 0 to NUM_COLS-1 loop 185 | wait until mclk_KAC'event and mclk_KAC = '1'; 186 | hclk_KAC <= '1'; 187 | wait until mclk_KAC'event and mclk_KAC = '0'; 188 | hclk_KAC <= '0'; 189 | end loop; 190 | sof_KAC <= '0'; --sof 0 after 1 row 191 | end loop; 192 | for k in 0 to 63 loop 193 | wait until mclk_KAC'event and mclk_KAC = '1'; 194 | end loop; 195 | 196 | end loop; 197 | 198 | wait; 199 | 200 | end process video_sync_signals; 201 | 202 | 203 | -- At the same time as the parallel port is uploading, do a transfer from 204 | -- the sensor to memory. Testing the memory arbitrator. 205 | KAC_pixel_generate: process 206 | variable i : integer := 0; 207 | begin 208 | 209 | if rst = RST_ACTIVE then 210 | pix_KAC <= (others=>'0'); 211 | i := 0; 212 | else 213 | wait until init_cycle_complete_test_port = '1'; 214 | 215 | pix_KAC <= std_logic_vector(to_unsigned(i, pix_KAC'length)); 216 | i := i + 1; 217 | end if; 218 | wait until hclk_KAC'event and hclk_KAC = '1'; 219 | 220 | end process KAC_pixel_generate; 221 | 222 | 223 | -- Simulate the pc parallel port connnection. Go through the steps to transfer 224 | -- data from start address to end address. 225 | pport_sdram_access: process 226 | variable i : integer := 0; 227 | begin 228 | dips <= (others=>'0'); 229 | ppd <= (others=>'0'); 230 | wait until rst = not(RST_ACTIVE); -- INVERSE OF RST_ACTIVE.. but not X or U 231 | wait until init_cycle_complete_test_port = '1'; 232 | 233 | loop 234 | 235 | -- Send upload command and toggle clock pin 236 | ppd <= "000001" & '0'; 237 | wait for PPD_CLK_PERIOD/2; 238 | ppd <= "000001" & '1'; 239 | wait for PPD_CLK_PERIOD/2; 240 | 241 | --Start address pad extra zero at top 242 | ppd <= std_logic_vector(start_addr(5 downto 0)) & '0'; 243 | wait for PPD_CLK_PERIOD/2; 244 | ppd <= std_logic_vector(start_addr(5 downto 0)) & '1'; 245 | wait for PPD_CLK_PERIOD/2; 246 | 247 | ppd <= std_logic_vector(start_addr(11 downto 6)) & '0'; 248 | wait for PPD_CLK_PERIOD/2; 249 | ppd <= std_logic_vector(start_addr(11 downto 6)) & '1'; 250 | wait for PPD_CLK_PERIOD/2; 251 | 252 | ppd <= std_logic_vector(start_addr(17 downto 12)) & '0'; 253 | wait for PPD_CLK_PERIOD/2; 254 | ppd <= std_logic_vector(start_addr(17 downto 12)) & '1'; 255 | wait for PPD_CLK_PERIOD/2; 256 | 257 | ppd <= '0' & std_logic_vector(start_addr(22 downto 18)) & '0'; 258 | wait for PPD_CLK_PERIOD/2; 259 | ppd <= '0' & std_logic_vector(start_addr(22 downto 18)) & '1'; 260 | wait for PPD_CLK_PERIOD/2; 261 | 262 | ppd <= std_logic_vector(end_addr(5 downto 0)) & '0'; 263 | wait for PPD_CLK_PERIOD/2; 264 | ppd <= std_logic_vector(end_addr(5 downto 0)) & '1'; 265 | wait for PPD_CLK_PERIOD/2; 266 | 267 | ppd <= std_logic_vector(end_addr(11 downto 6)) & '0'; 268 | wait for PPD_CLK_PERIOD/2; 269 | ppd <= std_logic_vector(end_addr(11 downto 6)) & '1'; 270 | wait for PPD_CLK_PERIOD/2; 271 | 272 | ppd <= std_logic_vector(end_addr(17 downto 12)) & '0'; 273 | wait for PPD_CLK_PERIOD/2; 274 | ppd <= std_logic_vector(end_addr(17 downto 12)) & '1'; 275 | wait for PPD_CLK_PERIOD/2; 276 | 277 | ppd <= '0' & std_logic_vector(end_addr(22 downto 18)) & '0'; 278 | wait for PPD_CLK_PERIOD/2; 279 | ppd <= '0' & std_logic_vector(end_addr(22 downto 18)) & '1'; 280 | 281 | --Generate some clocks on ppd(0) to upload the data 282 | --Go for length of data. figure this, don't hard code it. 283 | for i in 0 to to_integer(end_addr-start_addr)*2 loop 284 | wait for PPD_CLK_PERIOD/2; 285 | ppd <= "000000" & '0'; 286 | wait for PPD_CLK_PERIOD/2; 287 | ppd <= "000000" & '1'; 288 | end loop; 289 | 290 | 291 | wait for PPD_CLK_PERIOD; 292 | --ppd <= "000000" & '0'; 293 | 294 | end loop; 295 | 296 | wait; --make sure to end it 297 | end process; 298 | 299 | 300 | 301 | 302 | end digital_camera_tb_arch; 303 | -------------------------------------------------------------------------------- /src/master_control_signal_generator.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- master_control_signal_generator.vhd aka MCSG 7 | -- 8 | -- Recv's commands from pport. Controls other components. Startup delay. 9 | -- 10 | --********************************************************************************** 11 | 12 | 13 | library IEEE; 14 | use IEEE.std_logic_1164.all; 15 | use IEEE.numeric_std.all; 16 | use WORK.common.all; 17 | use work.comp_pckgs.all; 18 | 19 | ENTITY master_control_signal_generator IS 20 | PORT 21 | ( 22 | clk_50Mhz: in std_logic; 23 | clk_12_5Mhz : in std_logic; 24 | clk_pp: in std_logic; 25 | rst: in std_logic; 26 | cmd: in std_logic_vector(5 downto 0); 27 | start_upload: out std_logic; 28 | abort_upload: out std_logic; 29 | start_addr: out std_logic_vector(22 downto 0); 30 | end_addr: out std_logic_vector(22 downto 0); 31 | init_cycle_complete: out std_logic; 32 | 33 | init_KAC : out std_logic; 34 | sync_KAC : out std_logic; -- out KAC sync pin 35 | start_KAC : out std_logic; 36 | done_KAC : in std_logic; 37 | r_w_KAC : out std_logic; -- 0=read 1=write 38 | Addr_KAC : out std_logic_vector(7 downto 0); 39 | Data_KAC_in : out std_logic_vector(7 downto 0); 40 | Data_KAC_out: in std_logic_vector(7 downto 0) 41 | 42 | ); 43 | 44 | END master_control_signal_generator; 45 | 46 | ARCHITECTURE MCSG_arch OF master_control_signal_generator IS 47 | 48 | --KAC Signals 49 | --States to control KAC via I2C 50 | subtype state_KAC is integer range 3 downto 0; 51 | signal current_state_KAC, next_state_KAC: state_KAC; 52 | 53 | signal init_cycle_complete_r : std_logic; 54 | signal delay_start : std_logic; 55 | signal delay_complete : std_logic; 56 | 57 | --PP signals 58 | -- States to read commands from pc 59 | subtype state is integer range 15 downto 0; 60 | signal current_state, next_state: state; 61 | 62 | signal start_addr_r, start_addr_next: std_logic_vector(22 downto 0); 63 | signal end_addr_r, end_addr_next: std_logic_vector(22 downto 0); 64 | signal start_upload_sig, abort_upload_sig: std_logic; 65 | 66 | --Names for Parallel port commands 67 | constant NOP: std_logic_vector(5 downto 0) := "000000"; 68 | constant STARTUPLOAD: std_logic_vector(5 downto 0) := "000001"; 69 | constant ABORTUPLOAD: std_logic_vector(5 downto 0) := "000010"; 70 | 71 | constant READ : std_logic := '0'; 72 | constant WRITE : std_logic := '1'; 73 | 74 | 75 | 76 | BEGIN 77 | 78 | init_cycle_complete <= init_cycle_complete_r; 79 | 80 | --KAC I2C stuff 81 | sync_KAC <= '0'; -- out KAC sync pin 82 | Start_KAC <= '1' when init_cycle_complete_r = '1' else '0'; 83 | r_w_KAC <= READ; 84 | Addr_KAC <= x"0F"; 85 | Data_KAC_in <= x"55"; 86 | 87 | 88 | --PP 89 | start_addr <= start_addr_r; 90 | end_addr <= end_addr_r; 91 | 92 | --signal oneshots. The commands are coming in off the parallel port so this state 93 | --machine is controlled with that clock. The problem is, the start_upload and abort_upload 94 | --signals to the memory controller will not match the 50MHz clock. If they are high 95 | --for one state here, then they would be high for thousands of 50Mhz clk cycles. The one 96 | --shot makes them just go high for 1 50MHz cycle. 97 | start_upload_oneshot: one_shot 98 | port map 99 | ( 100 | CLK => clk_50Mhz, 101 | RST => rst, 102 | sig_in => start_upload_sig, 103 | sig_out => start_upload 104 | ); 105 | 106 | abort_upload_oneshot: one_shot 107 | port map 108 | ( 109 | CLK => clk_50Mhz, 110 | RST => rst, 111 | sig_in => abort_upload_sig, 112 | sig_out => abort_upload 113 | ); 114 | 115 | wait_for_KAC_to_init: ms_delay 116 | PORT MAP 117 | ( 118 | clk => clk_12_5Mhz, 119 | rst => rst, 120 | start => delay_start, --also starts on reset 121 | delay_complete => delay_complete 122 | ); 123 | 124 | 125 | ------------------------------------------------------------------------------------ 126 | -- PC command reader 127 | -- this is a huge state machine that can easily be reduced down. 128 | -- States 1 - 9 could all be one state. The bit order for start and end addr look 129 | -- a little funny but it's a right shift that makes the host software a little 130 | -- easier. 131 | 132 | pc_command_reader: process(current_state, cmd, start_addr_r, end_addr_r) is 133 | begin 134 | 135 | --default actions 136 | next_state <= current_state; 137 | start_addr_next <= start_addr_r; 138 | end_addr_next <= end_addr_r; 139 | start_upload_sig <= '0'; 140 | abort_upload_sig <= '0'; 141 | 142 | case current_state is 143 | when 0 => --NOP 144 | if cmd = STARTUPLOAD then 145 | next_state <= 1; 146 | elsif cmd = ABORTUPLOAD then 147 | next_state <= 10; 148 | else 149 | next_state <= 0; 150 | end if; 151 | 152 | when 1 => --Start Upload 153 | start_addr_next(5 downto 0) <= cmd; 154 | next_state <= 2; 155 | 156 | when 2 => --Load start addr 157 | start_addr_next(11 downto 6) <= cmd; 158 | next_state <= 3; 159 | 160 | when 3 => 161 | start_addr_next(17 downto 12) <= cmd; 162 | next_state <= 4; 163 | 164 | when 4 => 165 | start_addr_next(22 downto 18) <= cmd(4 downto 0); 166 | next_state <= 5; 167 | 168 | when 5 => 169 | end_addr_next(5 downto 0) <= cmd; 170 | next_state <= 6; 171 | 172 | when 6 => 173 | end_addr_next(11 downto 6) <= cmd; 174 | next_state <= 7; 175 | 176 | when 7 => 177 | end_addr_next(17 downto 12) <= cmd; 178 | next_state <= 8; 179 | 180 | when 8 => 181 | end_addr_next(22 downto 18) <= cmd(4 downto 0); 182 | next_state <= 9; 183 | 184 | when 9 => -- Could also branch to any other action 185 | start_upload_sig <= '1'; 186 | if cmd = STARTUPLOAD then 187 | next_state <= 1; 188 | elsif cmd = ABORTUPLOAD then 189 | next_state <= 10; 190 | else 191 | next_state <= 0; 192 | end if; 193 | 194 | 195 | when 10 => 196 | abort_upload_sig <= '1'; 197 | start_addr_next <= (others=>'0'); 198 | end_addr_next <= (others=>'0'); 199 | next_state <= 0; 200 | 201 | when others => 202 | next_state <= 0; 203 | 204 | end case; 205 | end process pc_command_reader; 206 | 207 | 208 | --Change state on clock 209 | state_reg: process( clk_pp, rst ) is 210 | begin 211 | if rst = '0' then 212 | current_state <= 0; 213 | start_addr_r <= (others=>'0'); 214 | end_addr_r <= (others=>'0'); 215 | elsif clk_pp'event and clk_pp='1' then 216 | --Update state and registers 217 | current_state <= next_state; 218 | start_addr_r <= start_addr_next; 219 | end_addr_r <= end_addr_next; 220 | end if; 221 | end process state_reg; 222 | 223 | 224 | 225 | ------------------------------------------------------------------------------------ 226 | -- KAC control 227 | -- Cycle the init pulse on powerup. 228 | -- 0 then 1 then wait 1ms then 0 and init_cycle_complete 229 | -- is asserted until reset. 230 | -- Also, SDRAM needs 200us of delay for startup 231 | 232 | 233 | KAC_Control: process(current_state_KAC, delay_complete) is 234 | begin 235 | 236 | --default actions 237 | next_state_KAC <= current_state_KAC; 238 | delay_start <= '0'; 239 | init_cycle_complete_r <= '0'; 240 | init_KAC <= '0'; --'0' Active '1' standby mode 241 | 242 | case current_state_KAC is 243 | when 0 => 244 | next_state_KAC <= 1; 245 | init_KAC <= '1'; 246 | 247 | when 1 => 248 | delay_start <= '1'; 249 | init_KAC <= '1'; 250 | 251 | if delay_complete = '1' then 252 | next_state_KAC <= 2; 253 | end if; 254 | 255 | when 2 => 256 | delay_start <= '1'; 257 | 258 | if delay_complete = '1' then 259 | next_state_KAC <= 3; 260 | end if; 261 | 262 | when 3 => 263 | init_cycle_complete_r <= '1'; 264 | 265 | 266 | 267 | end case; 268 | end process KAC_Control; 269 | 270 | 271 | --Change state on clock 272 | KAC_state_update: process( clk_12_5Mhz, rst ) is 273 | begin 274 | if rst = '0' then 275 | current_state_KAC <= 0; 276 | elsif clk_12_5Mhz'event and clk_12_5Mhz='1' then 277 | current_state_KAC <= next_state_KAC; 278 | end if; 279 | end process KAC_state_update; 280 | 281 | 282 | 283 | 284 | 285 | END MCSG_arch; 286 | 287 | 288 | 289 | -------------------------------------------------------------------------------- /src/ms_delay.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- ms_delay.vhd 7 | -- 8 | -- Used by MCSG for startup delay. Actually 320us, needs to be increased 9 | -- 10 | --********************************************************************************** 11 | 12 | library ieee; 13 | use ieee.std_logic_1164.all; 14 | use ieee.numeric_std.all; 15 | 16 | 17 | ENTITY ms_delay IS 18 | PORT( 19 | clk, rst, start : in std_logic; 20 | delay_complete : out std_logic); 21 | END ms_delay; 22 | 23 | ARCHITECTURE ms_delay_arch OF ms_delay IS 24 | BEGIN 25 | 26 | counter : process(clk, rst, start) 27 | 28 | variable count : integer range 800 downto 0; 29 | 30 | begin 31 | --defaults 32 | count := count; 33 | 34 | if rst = '0' or start = '0' then 35 | count := 0; 36 | delay_complete <= '0'; 37 | elsif clk'event and clk = '1' then 38 | if count = 800 then 39 | delay_complete <= '1'; 40 | count := 0; 41 | else 42 | count := count + 1; 43 | delay_complete <= '0'; 44 | end if; 45 | end if; 46 | 47 | 48 | end process counter; 49 | 50 | END ms_delay_arch; 51 | -------------------------------------------------------------------------------- /src/one_shot.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- one_shot.vhd 7 | -- 8 | -- Reduces when a positive edge is detected on the input signal, a 1 clock long 9 | -- high is output on sig_out. 10 | -- 11 | --********************************************************************************** 12 | 13 | 14 | 15 | library IEEE; 16 | use IEEE.std_logic_1164.all; 17 | use IEEE.numeric_std.all; 18 | 19 | 20 | ENTITY one_shot IS 21 | PORT 22 | ( 23 | clk: in std_logic; 24 | sig_in: in std_logic; 25 | rst: in std_logic; 26 | sig_out: out std_logic 27 | 28 | ); 29 | 30 | END one_shot; 31 | 32 | ARCHITECTURE one_shot_arch OF one_shot IS 33 | 34 | 35 | subtype state is integer range 2 downto 0; 36 | SIGNAL current_state, next_state: state; 37 | 38 | 39 | 40 | BEGIN 41 | 42 | 43 | comb_state_change: process(current_state, sig_in) is 44 | begin 45 | 46 | --default actions 47 | next_state <= current_state; 48 | 49 | case current_state is 50 | when 0 => 51 | sig_out <= '0'; 52 | if sig_in = '1' then 53 | next_state <= 1; 54 | end if; 55 | when 1 => 56 | sig_out <= '1'; 57 | next_state <= 2; 58 | 59 | when 2 => 60 | sig_out <= '0'; 61 | if sig_in = '0' then 62 | next_state <= 0; 63 | end if; 64 | 65 | end case; 66 | end process comb_state_change; 67 | 68 | 69 | --Change state on clock 70 | state_reg: process( clk, rst ) is 71 | begin 72 | if rst = '0' then 73 | current_state <= 0; 74 | elsif clk'event and clk='1' then 75 | current_state <= next_state; 76 | end if; 77 | end process state_reg; 78 | 79 | 80 | END one_shot_arch; 81 | 82 | 83 | 84 | -------------------------------------------------------------------------------- /src/pp_upload.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- pp_upload.vhd 7 | -- 8 | -- 9 | -- Transfers data from sdram to host PC. Uses a FIFO for a buffer. 10 | -- 11 | -- Interface to pc parallel port 12 | -- Uploads nibbles at a time through pp status pins. 13 | -- Low nibble when clk_db is low, high nibble when clk_db is high. 14 | -- There was some noise on the parallel port d0 clk pin so a debounce circuit was 15 | -- added. This makes it ignore false clocks caused by bounce, but it also adds a 16 | -- nominal amount of delay. 17 | -- This module is a little difficult because there are two clocks to deal with. 18 | -- The 50Mhz from the control module and the randomly ~50k to 200khz from the pport. 19 | -- The pport clk will pause for any amount of time at any moment as windows is 20 | -- multitasking. 21 | 22 | --********************************************************************************** 23 | 24 | 25 | 26 | library IEEE; 27 | use IEEE.std_logic_1164.all; 28 | use IEEE.numeric_std.all; 29 | use work.common.all; 30 | use work.comp_pckgs.all; 31 | 32 | 33 | ENTITY pp_upload IS 34 | 35 | PORT 36 | ( 37 | clk_50Mhz: in std_logic; 38 | clk_pp: buffer std_logic; --debounced clk from pport 39 | rst: in std_logic; 40 | pps: out std_logic_vector(6 downto 3); 41 | ppd: in std_logic_vector(6 downto 0); 42 | upload_data: in std_logic_vector(15 downto 0); 43 | wr_en: in std_logic; 44 | need_data: out std_logic; --Fifo status. set on fifo empty, cleared on full 45 | start_upload : in std_logic; 46 | cmd: out std_logic_vector(5 downto 0) 47 | ); 48 | 49 | END pp_upload; 50 | 51 | ARCHITECTURE pp_upload_arch OF pp_upload IS 52 | 53 | 54 | signal data_out : std_logic_vector(15 downto 0); --output of fifo 55 | signal cmd_r: std_logic_vector(5 downto 0); -- Command sent to MCSG 56 | signal full: std_logic; 57 | signal empty: std_logic; 58 | signal almost_full: std_logic; 59 | signal almost_empty: std_logic; 60 | signal wr_count: std_logic_vector(3 downto 0); 61 | signal upper_lower_byte: std_logic; --Toggle high / low half of fifo output 62 | signal rd_en: std_logic; 63 | signal not_clk_pp_sig : std_logic; -- make signal globally static 64 | signal clk_pp_sig : std_logic; 65 | signal ainit : std_logic; 66 | 67 | BEGIN 68 | 69 | not_clk_pp_sig <= not(clk_pp); 70 | ainit <= not(rst) or start_upload; --Active high reset 71 | 72 | 73 | --Debounce 74 | clk_debounce_01: signal_debounce 75 | generic map 76 | ( delay => 8 ) --8*(1/50Mhz) = 160ns 77 | port map 78 | ( clk_50Mhz => clk_50Mhz, 79 | sig_in => ppd(0), 80 | rst => rst, 81 | sig_out => clk_pp_sig 82 | ); 83 | 84 | -- clk_pp <= clk_pp_sig; 85 | buffet: buf port map(I => clk_pp_sig, O => clk_pp); 86 | 87 | 88 | pp_fifo : asyn_fifo_distrib 89 | port map ( 90 | din => upload_data, --memory 91 | wr_en => wr_en, --control 92 | wr_clk => clk_50Mhz, --fast clk. 93 | rd_en => rd_en, 94 | rd_clk => not_clk_pp_sig, --Odd, but works 95 | ainit => ainit, --active high to reset changed from just rst 96 | dout => data_out, --to pport 97 | full => full, --signals to control 98 | empty => empty, 99 | almost_full => almost_full, 100 | almost_empty => almost_empty, 101 | wr_count => wr_count 102 | ); 103 | 104 | --If there's anything in the fifo (not empty) enable read. not(empty) /= full 105 | --load fifo on 1 to 0 transition of pp_clk 106 | rd_en <= not(empty) and not(upper_lower_byte); 107 | 108 | --data_out <= x"4321"; -- To test byte ordere 109 | 110 | -- send to a signal first so I can also send pps to the seven segments 111 | -- The order here is a little interesting. Makes it come out on right on 112 | -- the other end data_out <= x"4321"; will appear in the data file on the 113 | -- other end as 21 43 in byte addresses 114 | -- 0 and 1. 115 | pps_mux: pps <= (others=>'0') when rst = '0' else 116 | data_out(3 downto 0) when clk_pp='0' and upper_lower_byte = '0' else 117 | data_out(15 downto 12) when clk_pp='1' and upper_lower_byte = '0' else 118 | data_out(11 downto 8) when clk_pp='0' and upper_lower_byte = '1' else 119 | data_out(7 downto 4); 120 | 121 | 122 | --signal to other modules the command that's coming from the host pc. 123 | cmd <= cmd_r; 124 | 125 | --read ppd pins and move them into the cmd reg. 126 | --Generate address for rom. move that to control module. Generate 127 | --cmd valid signal. 128 | process(clk_pp, ppd, rst, start_upload, upper_lower_byte) is 129 | begin 130 | if rst='0' then 131 | cmd_r <= (others=>'0'); 132 | upper_lower_byte <= '0'; 133 | elsif clk_pp'event and clk_pp='1' then 134 | cmd_r <= ppd(6 downto 1); 135 | upper_lower_byte <= not(upper_lower_byte) and not(start_upload); 136 | 137 | end if; 138 | end process; 139 | 140 | 141 | --output need data signal, a flag indicating fifo status. set on fifo empty, 142 | --cleared on full 143 | 144 | --I can use the full and almost full flags because they are asserted on the 145 | --clk_50Mhz edges. I can't use the empty and almost empty because they are 146 | --asserted on the clk_pp (slow clk) edges. If I use them, then the counter 147 | --will jump ahead when the fifo is empty but the signals don't say so yet. 148 | --the wr_count is off of the clock on the write side, the 50Mhz, so it's safe 149 | --to use. 150 | 151 | need_data_flag_generate: 152 | process(clk_50Mhz, rst) is 153 | begin 154 | if rst='0' then 155 | need_data <= '0'; 156 | elsif clk_50Mhz'event and clk_50Mhz='1' then 157 | if wr_count <= x"3" then 158 | need_data <= '1'; --dff it 159 | elsif wr_count >= x"b" then --delay to shut off the data 160 | need_data <= '0'; 161 | end if; 162 | end if; 163 | end process need_data_flag_generate; 164 | 165 | 166 | END pp_upload_arch; 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | -------------------------------------------------------------------------------- /src/pullup.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- pullup.vhd 7 | -- 8 | -- Used in testbench to pull up I2C lines 9 | 10 | --********************************************************************************** 11 | 12 | 13 | library IEEE; 14 | use IEEE.std_logic_1164.all; 15 | use IEEE.std_logic_arith.all; 16 | 17 | 18 | entity PULLUP is 19 | port(v101: OUT std_logic); 20 | end PULLUP; 21 | 22 | architecture archPULLUP of PULLUP is 23 | 24 | 25 | begin 26 | v101 <= 'H'; 27 | 28 | end archPULLUP; 29 | -------------------------------------------------------------------------------- /src/ram_control.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- ram_control.vhd 7 | -- 8 | -- 9 | -- Memory arbitrator. Handle access to memory. Control the FIFOs in other modules 10 | -- Incorporates SDRAM controller. 11 | 12 | --********************************************************************************** 13 | 14 | 15 | 16 | library IEEE; 17 | use IEEE.std_logic_1164.all; 18 | use IEEE.numeric_std.all; 19 | use work.common.all; 20 | use work.comp_pckgs.all; 21 | 22 | ENTITY ram_control IS 23 | 24 | PORT 25 | ( 26 | clk_50Mhz: in std_logic; 27 | rst: in std_logic; 28 | 29 | -- PP RAM access. Control provided by MCSG 30 | pp_data_out : out std_logic_vector(15 downto 0); 31 | start_upload : in std_logic; 32 | abort_upload : in std_logic; 33 | start_addr_upload : in std_logic_vector(22 downto 0); 34 | end_addr_upload : in std_logic_vector(22 downto 0); 35 | pp_fifo_wr_en : out std_logic; 36 | pp_fifo_need_data : in std_logic; 37 | 38 | -- KAC RAM access 39 | rd_en_KAC : out std_logic; 40 | dout_KAC : in std_logic_vector(15 downto 0); 41 | dump_data_req_KAC : in std_logic; 42 | start_new_frame : in std_logic; 43 | 44 | 45 | -- SDRAM side 46 | cke: out std_logic; -- clock-enable to SDRAM 47 | cs_n: out std_logic; -- chip-select to SDRAM 48 | ras_n: out std_logic; -- command input to SDRAM 49 | cas_n: out std_logic; -- command input to SDRAM 50 | we_n: out std_logic; -- command input to SDRAM 51 | ba: out unsigned(1 downto 0); -- SDRAM bank address bits 52 | sAddr: out unsigned(12-1 downto 0); -- SDRAM row/column address 53 | sData: inout unsigned(16-1 downto 0); -- SDRAM in/out databus 54 | dqmh: out std_logic; -- high databits I/O mask 55 | dqml: out std_logic -- low databits I/O mask 56 | 57 | ); 58 | 59 | END ram_control; 60 | 61 | ARCHITECTURE ram_control_arch OF ram_control IS 62 | 63 | -- Constants 64 | constant HRES : natural := 1280; 65 | constant VRES : natural := 1024; 66 | 67 | --Flags pport, misc 68 | signal uploading : std_logic; 69 | signal pp_addr_pointer : unsigned(19 downto 0); 70 | signal pp_ram_page : unsigned(2 downto 0); --Current readout page 71 | 72 | signal ram_page_full : unsigned(2 downto 0); --Complete frame 73 | signal ram_addr : unsigned(22 downto 0); 74 | 75 | type semaphore is (NOBODY, KAC, PPORT); 76 | signal SDRAM_used_by : semaphore; 77 | 78 | --KAC signals 79 | signal addr_ptr_KAC : unsigned(19 downto 0); 80 | signal ram_page_KAC : unsigned(2 downto 0); --Current writeout page 81 | 82 | 83 | --SDRAM Signals and constants 84 | signal rd, rd_next : std_logic; 85 | signal wr : std_logic; 86 | signal done : std_logic; 87 | signal hDOut : unsigned(16-1 downto 0); -- Type conversion 88 | signal sdramCntl_state : std_logic_vector(3 downto 0); 89 | 90 | BEGIN 91 | 92 | pp_fifo_wr_en <= '1' when done = '1' and rd = '1' else '0'; 93 | rd_en_KAC <= '1' when done = '1' and wr = '1' else '0'; 94 | 95 | pp_data_out <= std_logic_vector(hDOut); --Conversions are fun! 96 | 97 | -- The rd_en for the KAC_data fifo also can enable the write for the memory. 98 | -- Data in: Enable KAC_data fifo read and RAM Write 99 | -- Data out: Enable PP_Fifo write and RAM read 100 | 101 | -- B5 : block_ram_2kx16 102 | -- port map 103 | -- ( 104 | -- addr => std_logic_vector(ram_addr(10 downto 0)), 105 | -- clk => clk_50Mhz, 106 | -- sinit => not_rst, 107 | -- din => dout_KAC, 108 | -- dout => pp_data_out, 109 | -- we => rd_en_KAC_sig 110 | -- ); 111 | 112 | 113 | 114 | -- SDRAM memory controller module 115 | u1: sdramCntl 116 | generic map( 117 | FREQ => 50_000, -- 50 MHz operation 118 | DATA_WIDTH => 16, 119 | HADDR_WIDTH => 23, 120 | SADDR_WIDTH => 12 121 | ) 122 | port map( 123 | clk => clk_50Mhz, -- master clock 124 | rst => rst, -- active high reset 125 | rd => rd, -- SDRAM read control 126 | wr => wr, -- SDRAM write control 127 | done => done, -- SDRAM memory read/write done indicator 128 | hAddr => ram_addr, -- host-side address from memory tester 129 | hDIn => unsigned(dout_KAC), -- Data into sdram controller 130 | hDOut => hDOut, -- data from SDRAM 131 | sdramCntl_state => sdramCntl_state, -- (for testing) 132 | cke => cke, -- SDRAM clock enable 133 | cs_n => cs_n, -- SDRAM chip-select 134 | ras_n => ras_n, -- SDRAM RAS 135 | cas_n => cas_n, -- SDRAM CAS 136 | we_n => we_n, -- SDRAM write-enable 137 | ba => ba, -- SDRAM bank address 138 | sAddr => sAddr, -- SDRAM address 139 | sData => sData, -- SDRAM databus 140 | dqmh => dqmh, -- SDRAM DQMH 141 | dqml => dqml -- SDRAM DQML 142 | ); 143 | 144 | 145 | -- Determine which address to use for ram 146 | ram_addr <= (others=>'0') when rst = '0' else 147 | ram_page_KAC & addr_ptr_KAC when wr = '1' else 148 | pp_ram_page & pp_addr_pointer; 149 | 150 | 151 | -- Page the memory to prevent over writing 152 | ram_page: process (rst, clk_50Mhz, start_new_frame, ram_page_full, pp_ram_page, 153 | ram_page_KAC, start_upload ) is 154 | 155 | --Do I need to make a temp variable for the swap? NOPE! 156 | begin 157 | 158 | if rst = '0' then 159 | ram_page_KAC <= "000"; 160 | ram_page_full <= "001"; 161 | pp_ram_page <= "010"; 162 | 163 | elsif clk_50Mhz'event and clk_50Mhz = '1' then 164 | 165 | -- They both could happen in the same 50Mhz clock. unlikely, 166 | -- but possible 167 | if start_new_frame = '1' and start_upload = '1' then 168 | pp_ram_page <= ram_page_KAC; 169 | 170 | elsif start_new_frame = '1' then 171 | ram_page_full <= ram_page_KAC; 172 | ram_page_KAC <= ram_page_full; 173 | 174 | elsif start_upload = '1' then 175 | pp_ram_page <= ram_page_full; 176 | ram_page_full <= pp_ram_page; 177 | 178 | end if; 179 | 180 | end if; 181 | 182 | end process ram_page; 183 | 184 | 185 | 186 | -- Control access to the SDRAM with a semaphore. When a FIFO request action, 187 | -- respond by locking control of the memory, or waiting. If memory is 188 | -- available, signal the fifo to start transfering, and set SDRAM control 189 | -- bits rd and wr. 190 | sem_control: process(clk_50Mhz, rst, SDRAM_used_by, pp_fifo_need_data, 191 | dump_data_req_KAC, uploading, addr_ptr_KAC) is 192 | begin 193 | if rst='0' then 194 | rd_next <= '0'; 195 | rd <= '0'; 196 | SDRAM_used_by <= NOBODY; 197 | wr <= '0'; 198 | 199 | else 200 | 201 | --take semaphore 202 | if pp_fifo_need_data = '1' and uploading = '1' 203 | and (SDRAM_used_by = NOBODY or SDRAM_used_by = PPORT) then 204 | 205 | SDRAM_used_by <= PPORT; 206 | rd_next <= '1'; --SDRAM read 207 | 208 | elsif dump_data_req_KAC = '1' 209 | and (SDRAM_used_by = NOBODY or SDRAM_used_by = KAC) then 210 | 211 | SDRAM_used_by <= KAC; 212 | wr <= '1'; 213 | 214 | else 215 | 216 | -- Default values if not specified below 217 | -- Done with transfer, release control of memory 218 | -- or it's not needed 219 | rd_next <= '0'; 220 | wr <= '0'; 221 | SDRAM_used_by <= NOBODY; 222 | 223 | end if; 224 | 225 | -- Delay the pp_fifo_wr_en signal by one clock to account for delay 226 | if clk_50Mhz'event and clk_50Mhz = '1' then 227 | rd <= rd_next; 228 | end if; 229 | 230 | end if; 231 | end process sem_control; 232 | 233 | -- Control the KAC address pointer. Reset it when a new frame is signaled. 234 | -- Only increment it once after a write is completed. Prevent writing into 235 | -- next frame if there is no new frame signal 236 | KAC_fifo_empty: process(clk_50Mhz, rst, start_new_frame, wr, done, 237 | addr_ptr_KAC ) is 238 | begin 239 | if rst='0' then 240 | addr_ptr_KAC <= (others=>'0'); 241 | 242 | elsif clk_50Mhz'event and clk_50Mhz='1' then 243 | if start_new_frame = '1' then 244 | addr_ptr_KAC <= (others=>'0'); 245 | elsif wr = '1' and done = '1' then 246 | if addr_ptr_KAC < 655360 then -- Don't wrap around 247 | addr_ptr_KAC <= addr_ptr_KAC + 1; 248 | 249 | end if; 250 | 251 | end if; 252 | end if; 253 | 254 | end process KAC_fifo_empty; 255 | 256 | -- When the fifo needs data, check to see if memory is available, then set the 257 | -- write flag and start clocking data at the fifo until it lowers need_data. 258 | -- Update process to add new sdram stuff. Control how the address for the pport 259 | -- is set 260 | pp_fifo_fill: process(clk_50Mhz, rst, pp_fifo_need_data, start_upload, 261 | abort_upload, start_addr_upload, end_addr_upload, pp_addr_pointer) is 262 | begin 263 | if rst='0' then 264 | pp_addr_pointer <= (others=>'0'); 265 | uploading <= '0'; 266 | 267 | else 268 | 269 | --clocked events 270 | if clk_50Mhz'event and clk_50Mhz='1' then 271 | if start_upload = '1' then 272 | uploading <= '1'; 273 | pp_addr_pointer <= unsigned(start_addr_upload(19 downto 0)); 274 | 275 | elsif abort_upload = '1' or pp_addr_pointer > 276 | unsigned(end_addr_upload(19 downto 0)) then 277 | uploading <= '0'; 278 | pp_addr_pointer <= (others=>'0'); 279 | 280 | -- Inc on done signal generated by sdram 281 | elsif rd = '1' and done = '1' then 282 | pp_addr_pointer <= pp_addr_pointer + 1; 283 | 284 | end if; 285 | 286 | 287 | end if; 288 | end if; 289 | end process pp_fifo_fill; 290 | 291 | END ram_control_arch; 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | -------------------------------------------------------------------------------- /src/sdramcntl.vhd: -------------------------------------------------------------------------------- 1 | --********************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- sdramcntl.vhd 7 | -- 8 | -- Written by D. Vanden Bout, Xess Corp. 9 | -- 10 | -- Simplifies the SDRAM on the XSA-100 board to a SRAM like interface. Handles init 11 | -- bank switching and refresh. Instantiated by ram control. Slightly modified 12 | 13 | --********************************************************************************** 14 | 15 | 16 | library IEEE; 17 | use IEEE.std_logic_1164.all; 18 | use IEEE.numeric_std.all; 19 | use WORK.common.all; 20 | 21 | entity sdramCntl is 22 | generic( 23 | FREQ: natural := 50_000; -- operating frequency in KHz 24 | DATA_WIDTH: natural := 16; -- host & SDRAM data width 25 | HADDR_WIDTH: natural := 23; -- host-side address width 26 | SADDR_WIDTH: natural := 12 -- SDRAM-side address width 27 | ); 28 | port( 29 | clk: in std_logic; -- master clock 30 | 31 | -- host side 32 | rst: in std_logic; -- reset 33 | rd: in std_logic; -- read data 34 | wr: in std_logic; -- write data 35 | done: out std_logic; -- read/write op done 36 | hAddr: in unsigned(HADDR_WIDTH-1 downto 0); -- address from host 37 | hDIn: in unsigned(DATA_WIDTH-1 downto 0); -- data from host 38 | hDOut: out unsigned(DATA_WIDTH-1 downto 0); -- data to host 39 | sdramCntl_state: out std_logic_vector(3 downto 0); 40 | 41 | -- SDRAM side 42 | cke: out std_logic; -- clock-enable to SDRAM 43 | cs_n: out std_logic; -- chip-select to SDRAM 44 | ras_n: out std_logic; -- command input to SDRAM 45 | cas_n: out std_logic; -- command input to SDRAM 46 | we_n: out std_logic; -- command input to SDRAM 47 | ba: out unsigned(1 downto 0); -- SDRAM bank address bits 48 | sAddr: out unsigned(SADDR_WIDTH-1 downto 0); -- row/column address 49 | sData: inout unsigned(DATA_WIDTH-1 downto 0); -- in/out databus 50 | dqmh: out std_logic; -- high databits I/O mask 51 | dqml: out std_logic -- low databits I/O mask 52 | ); 53 | end sdramCntl; 54 | 55 | 56 | 57 | architecture arch of sdramCntl is 58 | 59 | -- constants 60 | constant NRows: natural := 4096; -- number of rows in SDRAM 61 | constant NCols: natural := 512; -- number of columns in SDRAM 62 | constant ColCmdPos: natural := 10; -- position of command bit in SDRAM column address 63 | constant Tinit: natural := 200; -- min initialization interval (us) 64 | constant Tras: natural := 45; -- min interval between active to precharge commands (ns) 65 | constant Trc: natural := 67; -- min interval between active to active commands (ns) 66 | constant Trcd: natural := 20; -- min interval between active and R/W commands (ns) 67 | constant Tref: natural := 64_000_000; -- maximum refresh interval (ns) 68 | constant Trfc: natural := 66; -- duration of refresh operation (ns) 69 | constant Trp: natural := 20; -- min precharge command duration (ns) 70 | constant Twr: natural := 15; -- write recovery time (ns) 71 | constant Ccas: natural := 3; -- CAS latency (cycles) 72 | constant Cmrd: natural := 3; -- mode register setup time (cycles) 73 | constant RfshCycles: natural := 8; -- number of refresh cycles needed to init RAM 74 | 75 | constant ROW_LEN: natural := log2(NRows); -- number of row address bits 76 | constant COL_LEN: natural := log2(NCols); -- number of column address bits 77 | constant NORM: natural := 1_000_000; -- normalize ns * KHz 78 | constant INIT_CYCLES: natural := 1 + ((Tinit * FREQ) / 1000); -- SDRMA power-on initialization interval 79 | constant RAS_CYCLES: natural := 1 + ((Tras * FREQ) / NORM); -- active-to-precharge interval 80 | constant RC_CYCLES: natural := 1 + ((Trc * FREQ) / NORM); -- active-to-active interval 81 | constant RCD_CYCLES: natural := 1 + ((Trcd * FREQ) / NORM); -- active-to-R/W interval 82 | constant REF_CYCLES: natural := 1 + (((Tref/NROWS) * FREQ) / NORM); -- interval between row refreshes 83 | constant RFC_CYCLES: natural := 1 + ((Trfc * FREQ) / NORM); -- refresh operation interval 84 | constant RP_CYCLES: natural := 1 + ((Trp * FREQ) / NORM); -- precharge operation interval 85 | constant WR_CYCLES: natural := 1 + ((Twr * FREQ) / NORM); -- write recovery time 86 | 87 | -- states of the SDRAM controller state machine 88 | type cntlState is ( 89 | INITWAIT, -- initialization - waiting for power-on initialization to complete 90 | INITPCHG, -- initialization - doing precharge of banks 91 | INITSETMODE, -- initialization - set SDRAM mode 92 | INITRFSH, -- initialization - do refreshes 93 | REFRESH, -- refresh a row of the SDRAM 94 | RW, -- wait for read/write operations to SDRAM 95 | RDDONE, -- indicate that the SDRAM read is done 96 | WRDONE, -- indicate that the SDRAM write is done 97 | ACTIVATE -- open a row of the SDRAM for reading/writing 98 | ); 99 | signal state_r, state_next: cntlState; -- state register and next state 100 | 101 | constant AUTO_PCHG_ON: std_logic := '1'; -- set sAddr(10) to this value to auto-precharge the bank 102 | constant AUTO_PCHG_OFF: std_logic := '0'; -- set sAddr(10) to this value to disable auto-precharge 103 | constant ALL_BANKS: std_logic := '1'; -- set sAddr(10) to this value to select all banks 104 | constant ACTIVE_BANK: std_logic := '0'; -- set sAddr(10) to this value to select only the active bank 105 | signal bank: unsigned(ba'range); 106 | signal row: unsigned(ROW_LEN - 1 downto 0); 107 | signal col: unsigned(COL_LEN - 1 downto 0); 108 | signal col_tmp: unsigned(sAddr'high-1 downto sAddr'low); 109 | signal changeRow: std_logic; 110 | signal dirOut: std_logic; -- high when driving data to SDRAM 111 | 112 | -- registers 113 | signal activeBank_r, activeBank_next: unsigned(bank'range); -- currently active SDRAM bank 114 | signal activeRow_r, activeRow_next: unsigned(row'range); -- currently active SDRAM row 115 | signal inactiveFlag_r, inactiveFlag_next: std_logic; -- 1 when all SDRAM rows are inactive 116 | signal initFlag_r, initFlag_next: std_logic; -- 1 when initializing SDRAM 117 | signal doRfshFlag_r, doRfshFlag_next: std_logic; -- 1 when a row refresh operation is required 118 | signal wrFlag_r, wrFlag_next: std_logic; -- 1 when writing data to SDRAM 119 | signal rdFlag_r, rdFlag_next: std_logic; -- 1 when reading data from SDRAM 120 | signal rfshCntr_r, rfshCntr_next: unsigned(log2(RfshCycles+1)-1 downto 0); -- counts initialization refreshes 121 | 122 | -- timer registers that count down times for various SDRAM operations 123 | signal timer_r, timer_next: unsigned(log2(INIT_CYCLES+1)-1 downto 0); -- current SDRAM op time 124 | signal rasTimer_r, rasTimer_next: unsigned(log2(RAS_CYCLES+1)-1 downto 0); -- active-to-precharge time 125 | signal wrTimer_r, wrTimer_next: unsigned(log2(WR_CYCLES+1)-1 downto 0); -- write-to-precharge time 126 | signal refTimer_r, refTimer_next: unsigned(log2(REF_CYCLES+1)-1 downto 0); -- time between row refreshes 127 | 128 | -- SDRAM commands 129 | subtype sdramCmd is unsigned(5 downto 0); 130 | -- cmd = (cs_n,ras_n,cas_n,we_n,dqmh,dqml) 131 | constant NOP_CMD: sdramCmd := "011100"; 132 | constant ACTIVE_CMD: sdramCmd := "001100"; 133 | constant READ_CMD: sdramCmd := "010100"; 134 | constant WRITE_CMD: sdramCmd := "010000"; 135 | constant PCHG_CMD: sdramCmd := "001011"; 136 | constant MODE_CMD: sdramCmd := "000011"; 137 | constant RFSH_CMD: sdramCmd := "000111"; 138 | signal cmd: sdramCmd; 139 | 140 | -- SDRAM mode register 141 | subtype sdramMode is unsigned(11 downto 0); 142 | constant MODE: sdramMode := "00" & "0" & "00" & "011" & "0" & "000"; 143 | 144 | signal logic0 : std_logic; 145 | 146 | begin 147 | 148 | logic0 <= '0'; 149 | 150 | 151 | hDOut <= sData(hDOut'range); -- connect SDRAM data bus to host data bus 152 | sData <= hDIn(sData'range) when dirOut='1' else (others=>'Z'); -- connect host data bus to SDRAM data bus 153 | 154 | combinatorial: process(rd,wr,hAddr,hDIn,state_r,bank,row,col,changeRow, 155 | activeBank_r,activeRow_r,initFlag_r,doRfshFlag_r,rdFlag_r,wrFlag_r, 156 | rfshCntr_r,timer_r,rasTimer_r,wrTimer_r,refTimer_r,cmd,col_tmp,inactiveFlag_r) 157 | begin 158 | -- attach bits in command to SDRAM control signals 159 | (cs_n,ras_n,cas_n,we_n,dqmh,dqml) <= cmd; 160 | 161 | -- get bank, row, column from host address 162 | bank <= hAddr(bank'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN); 163 | row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN); 164 | col <= hAddr(COL_LEN - 1 downto 0); 165 | -- extend column (if needed) until it is as large as the (SDRAM address bus - 1) 166 | col_tmp <= (others=>'0'); -- set it to all zeroes 167 | col_tmp(col'range) <= col; -- write column into the lower bits 168 | 169 | -- default operations 170 | cke <= YES; -- enable SDRAM clock input 171 | cmd <= NOP_CMD; -- set SDRAM command to no-operation 172 | if initFlag_r = YES then 173 | cs_n <= HI; 174 | dqml <= HI; 175 | dqmh <= HI; 176 | end if; 177 | done <= NO; -- pending SDRAM operation is not done 178 | ba <= bank; -- set SDRAM bank address bits 179 | -- set SDRAM address to column with interspersed command bit 180 | sAddr(ColCmdPos-1 downto 0) <= col_tmp(ColCmdPos-1 downto 0); 181 | sAddr(sAddr'high downto ColCmdPos+1) <= col_tmp(col_tmp'high downto ColCmdPos); 182 | sAddr(ColCmdPos) <= AUTO_PCHG_OFF; -- set command bit to disable auto-precharge 183 | dirOut <= NO; 184 | 185 | -- default register updates 186 | state_next <= state_r; 187 | inactiveFlag_next <= inactiveFlag_r; 188 | activeBank_next <= activeBank_r; 189 | activeRow_next <= activeRow_r; 190 | initFlag_next <= initFlag_r; 191 | doRfshFlag_next <= doRfshFlag_r; 192 | rdFlag_next <= rdFlag_r; 193 | wrFlag_next <= wrFlag_r; 194 | rfshCntr_next <= rfshCntr_r; 195 | 196 | -- update timers 197 | if timer_r /= TO_UNSIGNED(0,timer_r'length) then 198 | timer_next <= timer_r - 1; 199 | else 200 | timer_next <= timer_r; 201 | end if; 202 | 203 | if rasTimer_r /= TO_UNSIGNED(0,rasTimer_r'length) then 204 | rasTimer_next <= rasTimer_r - 1; 205 | else 206 | rasTimer_next <= rasTimer_r; 207 | end if; 208 | 209 | if wrTimer_r /= TO_UNSIGNED(0,wrTimer_r'length) then 210 | wrTimer_next <= wrTimer_r - 1; 211 | else 212 | wrTimer_next <= wrTimer_r; 213 | end if; 214 | 215 | if refTimer_r /= TO_UNSIGNED(0,refTimer_r'length) then 216 | refTimer_next <= refTimer_r - 1; 217 | else 218 | -- on timeout, reload the timer with the interval between row refreshes 219 | -- and set the flag that indicates a refresh operation is needed. 220 | refTimer_next <= TO_UNSIGNED(REF_CYCLES,refTimer_next'length); 221 | doRfshFlag_next <= YES; 222 | end if; 223 | 224 | -- determine if another row or bank in the SDRAM is being addressed 225 | if row /= activeRow_r or bank /= activeBank_r or inactiveFlag_r = YES then 226 | changeRow <= YES; 227 | else 228 | changeRow <= NO; 229 | end if; 230 | 231 | -- ***** compute next state and outputs ***** 232 | 233 | -- SDRAM initialization 234 | if state_r = INITWAIT then 235 | -- initiate wait for SDRAM power-on initialization 236 | -- timer_next <= TO_UNSIGNED(INIT_CYCLES,timer_next'length); -- set timer for init interval 237 | cs_n <= HI; 238 | dqml <= HI; 239 | dqmh <= HI; 240 | initFlag_next <= YES; -- indicate initialization is in progress 241 | if timer_r = TO_UNSIGNED(0,timer_r'length) then 242 | state_next <= INITPCHG; -- precharge SDRAM after power-on initialization 243 | end if; 244 | sdramCntl_state <= "0001"; 245 | 246 | -- don't do anything if the previous operation has not completed yet. 247 | -- Place this before anything else so operations in the previous state 248 | -- complete before any operations in the new state are executed. 249 | elsif timer_r /= TO_UNSIGNED(0,timer_r'length) then 250 | sdramCntl_state <= "0000"; 251 | 252 | elsif state_r = INITPCHG then 253 | cmd <= PCHG_CMD; -- initiate precharge of the SDRAM 254 | sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks 255 | timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation 256 | -- now setup the counter for the number of refresh ops needed during initialization 257 | rfshCntr_next <= TO_UNSIGNED(RfshCycles,rfshCntr_next'length); 258 | state_next <= INITRFSH; -- perform refresh ops after setting the mode 259 | sdramCntl_state <= "0010"; 260 | elsif state_r = INITRFSH then 261 | -- refresh the SDRAM a number of times during initialization 262 | if rfshCntr_r /= TO_UNSIGNED(0,rfshCntr_r'length) then 263 | -- do a refresh operation if the counter is not zero yet 264 | cmd <= RFSH_CMD; -- refresh command goes to SDRAM 265 | timer_next <= TO_UNSIGNED(RFC_CYCLES,timer_next'length); -- refresh operation interval 266 | rfshCntr_next <= rfshCntr_r - 1; -- decrement refresh operation counter 267 | state_next <= INITRFSH; -- return to this state while counter is non-zero 268 | else 269 | -- refresh op counter reaches zero, so set the operating mode of the SDRAM 270 | state_next <= INITSETMODE; 271 | end if; 272 | sdramCntl_state <= "0100"; 273 | elsif state_r = INITSETMODE then 274 | -- set the mode register in the SDRAM 275 | cmd <= MODE_CMD; -- initiate loading of mode register in the SDRAM 276 | sAddr <= MODE; -- output mode register bits onto the SDRAM address bits 277 | timer_next <= TO_UNSIGNED(Cmrd,timer_next'length); -- set timer for this operation 278 | state_next <= RW; -- process read/write operations after initialization is done 279 | initFlag_next <= NO; -- reset flag since initialization is done 280 | sdramCntl_state <= "0011"; 281 | 282 | -- refresh a row of the SDRAM when the refresh timer hits zero and sets the flag 283 | -- and the SDRAM is no longer being initialized or read/written. 284 | -- Place this before the RW state so the host can't block refreshes by doing 285 | -- continuous read/write operations. 286 | elsif doRfshFlag_r = YES and initFlag_r = NO and wrFlag_r = NO and rdFlag_r = NO then 287 | if rasTimer_r = TO_UNSIGNED(0,rasTimer_r'length) and wrTimer_r = TO_UNSIGNED(0,wrTimer_r'length) then 288 | doRfshFlag_next <= NO; -- reset the flag that initiates a refresh operation 289 | cmd <= PCHG_CMD; -- initiate precharge of the SDRAM 290 | sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks 291 | timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation 292 | inactiveFlag_next <= YES; -- all rows are inactive after a precharge operation 293 | state_next <= REFRESH; -- refresh the SDRAM after the precharge 294 | end if; 295 | sdramCntl_state <= "0101"; 296 | elsif state_r = REFRESH then 297 | cmd <= RFSH_CMD; -- refresh command goes to SDRAM 298 | timer_next <= TO_UNSIGNED(RFC_CYCLES,timer_next'length); -- refresh operation interval 299 | -- after refresh is done, resume writing or reading the SDRAM if in progress 300 | state_next <= RW; 301 | sdramCntl_state <= "0110"; 302 | 303 | -- do nothing but wait for read or write operations 304 | elsif state_r = RW then 305 | if rd = YES then 306 | -- the host has initiated a read operation 307 | rdFlag_next <= YES; -- set flag to indicate a read operation is in progress 308 | -- if a different row or bank is being read, then precharge the SDRAM and activate the new row 309 | if changeRow = YES then 310 | -- wait for any row activations or writes to finish before doing a precharge 311 | if rasTimer_r = TO_UNSIGNED(0,rasTimer_r'length) and wrTimer_r = TO_UNSIGNED(0,wrTimer_r'length) then 312 | cmd <= PCHG_CMD; -- initiate precharge of the SDRAM 313 | sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks 314 | timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation 315 | inactiveFlag_next <= YES; -- all rows are inactive after a precharge operation 316 | state_next <= ACTIVATE; -- activate the new row after the precharge is done 317 | end if; 318 | -- read from the currently active row 319 | else 320 | cmd <= READ_CMD; -- initiate a read of the SDRAM 321 | timer_next <= TO_UNSIGNED(Ccas,timer_next'length); -- setup timer for read access 322 | state_next <= RDDONE; -- read the data from SDRAM after the access time 323 | end if; 324 | sdramCntl_state <= "0111"; 325 | elsif wr = YES then 326 | -- the host has initiated a write operation 327 | -- if a different row or bank is being written, then precharge the SDRAM and activate the new row 328 | if changeRow = YES then 329 | wrFlag_next <= YES; -- set flag to indicate a write operation is in progress 330 | -- wait for any row activations or writes to finish before doing a precharge 331 | if rasTimer_r = TO_UNSIGNED(0,rasTimer_r'length) and wrTimer_r = TO_UNSIGNED(0,wrTimer_r'length) then 332 | cmd <= PCHG_CMD; -- initiate precharge of the SDRAM 333 | sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks 334 | timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation 335 | inactiveFlag_next <= YES; -- all rows are inactive after a precharge operation 336 | state_next <= ACTIVATE; -- activate the new row after the precharge is done 337 | end if; 338 | -- write to the currently active row 339 | else 340 | cmd <= WRITE_CMD; -- initiate the write operation 341 | dirOut <= YES; 342 | -- set timer so precharge doesn't occur too soon after write operation 343 | wrTimer_next <= TO_UNSIGNED(WR_CYCLES,wrTimer_next'length); 344 | state_next <= WRDONE; -- go back and wait for another read/write operation 345 | end if; 346 | sdramCntl_state <= "1000"; 347 | else 348 | null; -- no read or write operation, so do nothing 349 | sdramCntl_state <= "1001"; 350 | end if; 351 | 352 | -- enter this state when the data read from the SDRAM is available 353 | elsif state_r = RDDONE then 354 | rdFlag_next <= NO; -- set flag to indicate the read operation is over 355 | done <= YES; -- tell the host that the data is ready 356 | state_next <= RW; -- go back and do another read/write operation 357 | sdramCntl_state <= "1010"; 358 | 359 | -- enter this state when the data is written to the SDRAM 360 | elsif state_r = WRDONE then 361 | dirOut <= YES; 362 | wrFlag_next <= NO; -- set flag to indicate the write operation is over 363 | done <= YES; -- tell the host that the data is ready 364 | state_next <= RW; -- go back and do another read/write operation 365 | sdramCntl_state <= "1011"; 366 | 367 | -- activate a row of the SDRAM 368 | elsif state_r = ACTIVATE then 369 | cmd <= ACTIVE_CMD; -- initiate the SDRAM activation operation 370 | sAddr <= (others=>'0'); -- output the address for the row that will be activated 371 | sAddr(row'range) <= row; 372 | activeBank_next <= bank; -- remember the active SDRAM row 373 | activeRow_next <= row; -- remember the active SDRAM bank 374 | inactiveFlag_next <= NO; -- the SDRAM is no longer inactive 375 | rasTimer_next <= TO_UNSIGNED(RCD_CYCLES,rasTimer_next'length); 376 | timer_next <= TO_UNSIGNED(RCD_CYCLES,timer_next'length); 377 | state_next <= RW; -- go back and do the read/write operation that caused this activation 378 | sdramCntl_state <= "1100"; 379 | 380 | -- no operation 381 | else 382 | null; 383 | sdramCntl_state <= "1101"; 384 | 385 | end if; 386 | 387 | end process combinatorial; 388 | 389 | 390 | -- update registers on the rising clock edge 391 | update: process(clk) 392 | begin 393 | if clk'event and clk='1' then 394 | if rst = NO then 395 | state_r <= INITWAIT; 396 | activeBank_r <= (others=>'0'); 397 | activeRow_r <= (others=>'0'); 398 | inactiveFlag_r <= YES; 399 | initFlag_r <= YES; 400 | doRfshFlag_r <= NO; 401 | rdFlag_r <= NO; 402 | wrFlag_r <= NO; 403 | rfshCntr_r <= TO_UNSIGNED(0,rfshCntr_r'length); 404 | timer_r <= TO_UNSIGNED(INIT_CYCLES,timer_r'length); 405 | refTimer_r <= TO_UNSIGNED(REF_CYCLES,refTimer_r'length); 406 | rasTimer_r <= TO_UNSIGNED(0,rasTimer_r'length); 407 | wrTimer_r <= TO_UNSIGNED(0,wrTimer_r'length); 408 | else 409 | state_r <= state_next; 410 | activeBank_r <= activeBank_next; 411 | activeRow_r <= activeRow_next; 412 | inactiveFlag_r <= inactiveFlag_next; 413 | initFlag_r <= initFlag_next; 414 | doRfshFlag_r <= doRfshFlag_next; 415 | rdFlag_r <= rdFlag_next; 416 | wrFlag_r <= wrFlag_next; 417 | rfshCntr_r <= rfshCntr_next; 418 | timer_r <= timer_next; 419 | refTimer_r <= refTimer_next; 420 | rasTimer_r <= rasTimer_next; 421 | wrTimer_r <= wrTimer_next; 422 | end if; 423 | end if; 424 | end process update; 425 | 426 | end arch; 427 | -------------------------------------------------------------------------------- /src/signal_debounce.vhd: -------------------------------------------------------------------------------- 1 | --****************************************************************************** 2 | 3 | -- Copyright 2013, Ryan Henderson 4 | -- CMOS digital camera controller and frame capture device 5 | -- 6 | -- signal_debounce.vhd 7 | -- 8 | -- Debounce circuit to reduce false triggering from switch bounce 9 | -- or other problems. Generic delay for number of clocks to wait 10 | -- for bounces to stop. The size of the delay counter is adjusted 11 | -- based off this generic delay. State machine that requires x clocks 12 | -- to occur after a state changes, before it can change states again. 13 | 14 | -- modelsim is giving an error during simulation about vector 15 | -- truncation numberic_std.to_unsigned 16 | 17 | --****************************************************************************** 18 | 19 | 20 | 21 | library IEEE; 22 | use IEEE.std_logic_1164.all; 23 | use IEEE.numeric_std.all; 24 | use WORK.common.all; 25 | 26 | ENTITY signal_debounce IS 27 | generic 28 | ( 29 | delay: natural := 4 -- must be a power of 2! 2, 4, 8, 16... 30 | ); 31 | 32 | PORT 33 | ( 34 | clk_50Mhz: in std_logic; 35 | sig_in: in std_logic; --in unbuffered from the parallel port 36 | rst: in std_logic; 37 | sig_out: out std_logic 38 | 39 | ); 40 | 41 | END signal_debounce; 42 | 43 | ARCHITECTURE signal_debounce_arch OF signal_debounce IS 44 | 45 | 46 | subtype state is integer range 1 downto 0; 47 | SIGNAL current_state, next_state: state; 48 | SIGNAL start, done: std_logic; 49 | 50 | --used to wait for bounce to settle 51 | SIGNAL state_time: unsigned (log2(delay)-1 downto 0); 52 | 53 | 54 | BEGIN 55 | 56 | 57 | comb_state_change: process(current_state, done, sig_in) is 58 | begin 59 | 60 | --default actions 61 | next_state <= current_state; 62 | 63 | case current_state is 64 | --stay in this state until the timer has expired, and 65 | --sig_in has changed to a 1 66 | when 0 => 67 | state_time <= TO_UNSIGNED(delay, state_time'length); 68 | if done = '1' and sig_in = '0' then 69 | next_state <= 1; 70 | else 71 | start <= '1'; 72 | next_state <= 0; 73 | end if; 74 | 75 | --stay in this state until the timer has expired, and 76 | --sig_in has changed to a 0 77 | when 1 => 78 | state_time <= TO_UNSIGNED(delay, state_time'length); 79 | if done = '1' and sig_in = '1' then 80 | next_state <= 0; 81 | else 82 | start <= '1'; 83 | next_state <= 1; 84 | end if; 85 | end case; 86 | end process comb_state_change; 87 | 88 | 89 | --Change state on clock 90 | state_reg: process( clk_50Mhz, rst ) is 91 | begin 92 | if rst = '0' then 93 | current_state <= 0; 94 | elsif clk_50Mhz'event and clk_50Mhz='1' then 95 | current_state <= next_state; 96 | end if; 97 | end process state_reg; 98 | 99 | --Time to wait in each state 100 | state_timer: process(start, clk_50Mhz, rst) is 101 | VARIABLE counter: unsigned (log2(delay)-1 downto 0); 102 | begin 103 | 104 | if rst = '0' then 105 | counter := (others=>'0'); 106 | done <= '0'; 107 | elsif clk_50Mhz'event and clk_50Mhz='1' then 108 | if start='1' then 109 | counter := (counter+1); 110 | if counter = state_time then -- 111 | done <= '1'; 112 | counter := (others=>'0'); 113 | else 114 | done <= '0'; 115 | end if; 116 | else 117 | done <= '0'; 118 | end if; 119 | end if; 120 | end process state_timer; 121 | 122 | --Use the states to encode the output 123 | sig_out <= '0' when current_state = 1 else 124 | '1'; 125 | 126 | 127 | END signal_debounce_arch; 128 | 129 | 130 | 131 | --------------------------------------------------------------------------------