├── .gitignore ├── FastFrame.wvproj ├── .template ├── User ├── ch32v20x_it.h ├── system_ch32v20x.h ├── ch32v20x_it.c ├── ch32v20x_conf.h ├── audio.h ├── fastFrame.h └── main.cpp ├── Peripheral ├── inc │ ├── ch32v20x_crc.h │ ├── ch32v20x_wwdg.h │ ├── ch32v20x_misc.h │ ├── ch32v20x_iwdg.h │ ├── ch32v20x_opa.h │ ├── ch32v20x_dbgmcu.h │ ├── ch32v20x_pwr.h │ ├── ch32v20x_rtc.h │ ├── ch32v20x_exti.h │ ├── ch32v20x_bkp.h │ ├── ch32v20x_flash.h │ ├── ch32v20x_usart.h │ ├── ch32v20x_dma.h │ ├── ch32v20x_spi.h │ └── ch32v20x_gpio.h └── src │ ├── ch32v20x_opa.c │ ├── ch32v20x_crc.c │ ├── ch32v20x_dbgmcu.c │ ├── ch32v20x_iwdg.c │ ├── ch32v20x_wwdg.c │ ├── ch32v20x_misc.c │ ├── ch32v20x_exti.c │ ├── ch32v20x_bkp.c │ └── ch32v20x_pwr.c ├── Debug ├── debug.h └── debug.c ├── Ld └── Link.ld ├── FastFrame.launch ├── Core ├── core_riscv.c └── core_riscv.h └── Startup ├── startup_ch32v20x_D6.S ├── startup_ch32v20x_D8.S └── startup_ch32v20x_D8W.S /.gitignore: -------------------------------------------------------------------------------- 1 | .project 2 | .cproject 3 | obj 4 | .settings -------------------------------------------------------------------------------- /FastFrame.wvproj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bitluni/MagnetMatrix/HEAD/FastFrame.wvproj -------------------------------------------------------------------------------- /.template: -------------------------------------------------------------------------------- 1 | Vendor=WCH 2 | Toolchain=RISC-V 3 | Series=CH32V208 4 | RTOS=NoneOS 5 | MCU=CH32V208WBU6 6 | Link=WCH-Link 7 | PeripheralVersion==1.7 8 | Description==Website: http://www.wch.cn/products/CH32V208.html?\nROM(byte): 160K, SRAM(byte): 32K, CHIP PINS: 68, GPIO PORTS: 54.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. 9 | Mcu Type=CH32V20x 10 | Address=0x08000000 11 | Target Path=obj\FastFrame.hex 12 | CLKSpeed=1 13 | DebugInterfaceMode=-1 14 | Erase All=true 15 | Program=true 16 | Verify=true 17 | Reset=true 18 | SDIPrintf=false 19 | -------------------------------------------------------------------------------- /User/ch32v20x_it.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_it.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains the headers of the interrupt handlers. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __CH32V20x_IT_H 13 | #define __CH32V20x_IT_H 14 | 15 | #include "debug.h" 16 | 17 | 18 | #endif /* __CH32V20x_IT_H */ 19 | 20 | 21 | -------------------------------------------------------------------------------- /User/system_ch32v20x.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : system_ch32v20x.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : CH32V20x Device Peripheral Access Layer System Header File. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __SYSTEM_ch32v20x_H 13 | #define __SYSTEM_ch32v20x_H 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ 20 | 21 | /* System_Exported_Functions */ 22 | extern void SystemInit(void); 23 | extern void SystemCoreClockUpdate(void); 24 | 25 | #ifdef __cplusplus 26 | } 27 | #endif 28 | 29 | #endif /*__CH32V20x_SYSTEM_H */ 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_crc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_crc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * CRC firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_CRC_H 14 | #define __CH32V20x_CRC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | void CRC_ResetDR(void); 23 | uint32_t CRC_CalcCRC(uint32_t Data); 24 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 25 | uint32_t CRC_GetCRC(void); 26 | void CRC_SetIDRegister(uint8_t IDValue); 27 | uint8_t CRC_GetIDRegister(void); 28 | 29 | #ifdef __cplusplus 30 | } 31 | #endif 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /User/ch32v20x_it.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_it.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : Main Interrupt Service Routines. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_it.h" 13 | 14 | void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 15 | void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 16 | 17 | /********************************************************************* 18 | * @fn NMI_Handler 19 | * 20 | * @brief This function handles NMI exception. 21 | * 22 | * @return none 23 | */ 24 | void NMI_Handler(void) 25 | { 26 | } 27 | 28 | /********************************************************************* 29 | * @fn HardFault_Handler 30 | * 31 | * @brief This function handles Hard Fault exception. 32 | * 33 | * @return none 34 | */ 35 | void HardFault_Handler(void) 36 | { 37 | while (1) 38 | { 39 | } 40 | } 41 | 42 | 43 | -------------------------------------------------------------------------------- /User/ch32v20x_conf.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_conf.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : Library configuration file. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __CH32V20x_CONF_H 13 | #define __CH32V20x_CONF_H 14 | 15 | #include "ch32v20x_adc.h" 16 | #include "ch32v20x_bkp.h" 17 | #include "ch32v20x_can.h" 18 | #include "ch32v20x_crc.h" 19 | #include "ch32v20x_dbgmcu.h" 20 | #include "ch32v20x_dma.h" 21 | #include "ch32v20x_exti.h" 22 | #include "ch32v20x_flash.h" 23 | #include "ch32v20x_gpio.h" 24 | #include "ch32v20x_i2c.h" 25 | #include "ch32v20x_iwdg.h" 26 | #include "ch32v20x_pwr.h" 27 | #include "ch32v20x_rcc.h" 28 | #include "ch32v20x_rtc.h" 29 | #include "ch32v20x_spi.h" 30 | #include "ch32v20x_tim.h" 31 | #include "ch32v20x_usart.h" 32 | #include "ch32v20x_wwdg.h" 33 | #include "ch32v20x_it.h" 34 | #include "ch32v20x_misc.h" 35 | 36 | 37 | #endif /* __CH32V20x_CONF_H */ 38 | 39 | 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /Debug/debug.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : debug.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for UART 7 | * Printf , Delay functions. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __DEBUG_H 14 | #define __DEBUG_H 15 | 16 | #include "stdio.h" 17 | #include "ch32v20x.h" 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | /* UART Printf Definition */ 24 | #define DEBUG_UART1 1 25 | #define DEBUG_UART2 2 26 | #define DEBUG_UART3 3 27 | 28 | /* DEBUG UATR Definition */ 29 | #ifndef DEBUG 30 | #define DEBUG DEBUG_UART1 31 | #endif 32 | 33 | void Delay_Init(void); 34 | void Delay_Us(uint32_t n); 35 | void Delay_Ms(uint32_t n); 36 | void USART_Printf_Init(uint32_t baudrate); 37 | 38 | #if(DEBUG) 39 | #define PRINT(format, ...) printf(format, ##__VA_ARGS__) 40 | #else 41 | #define PRINT(X...) 42 | #endif 43 | 44 | #ifdef __cplusplus 45 | } 46 | #endif 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_wwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_wwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the WWDG 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_WWDG_H 14 | #define __CH32V20x_WWDG_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* WWDG_Prescaler */ 23 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 24 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 25 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 26 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 27 | 28 | void WWDG_DeInit(void); 29 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 30 | void WWDG_SetWindowValue(uint8_t WindowValue); 31 | void WWDG_EnableIT(void); 32 | void WWDG_SetCounter(uint8_t Counter); 33 | void WWDG_Enable(uint8_t Counter); 34 | FlagStatus WWDG_GetFlagStatus(void); 35 | void WWDG_ClearFlag(void); 36 | 37 | #ifdef __cplusplus 38 | } 39 | #endif 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_misc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_misc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * miscellaneous firmware library functions. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_MISC_H 14 | #define __CH32V20x_MISC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* NVIC Init Structure definition */ 23 | typedef struct 24 | { 25 | uint8_t NVIC_IRQChannel; 26 | uint8_t NVIC_IRQChannelPreemptionPriority; 27 | uint8_t NVIC_IRQChannelSubPriority; 28 | FunctionalState NVIC_IRQChannelCmd; 29 | } NVIC_InitTypeDef; 30 | 31 | /* Preemption_Priority_Group */ 32 | #define NVIC_PriorityGroup_0 ((uint32_t)0x00) 33 | #define NVIC_PriorityGroup_1 ((uint32_t)0x01) 34 | #define NVIC_PriorityGroup_2 ((uint32_t)0x02) 35 | #define NVIC_PriorityGroup_3 ((uint32_t)0x03) 36 | #define NVIC_PriorityGroup_4 ((uint32_t)0x04) 37 | 38 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 39 | void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_iwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_iwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * IWDG firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_IWDG_H 14 | #define __CH32V20x_IWDG_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* IWDG_WriteAccess */ 23 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 24 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 25 | 26 | /* IWDG_prescaler */ 27 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 28 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 29 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 30 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 31 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 32 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 33 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 34 | 35 | /* IWDG_Flag */ 36 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 37 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 38 | 39 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 40 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 41 | void IWDG_SetReload(uint16_t Reload); 42 | void IWDG_ReloadCounter(void); 43 | void IWDG_Enable(void); 44 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_opa.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_opa.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * OPA firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_OPA_H 14 | #define __CH32V20x_OPA_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | #define OPA_PSEL_OFFSET 3 23 | #define OPA_NSEL_OFFSET 2 24 | #define OPA_MODE_OFFSET 1 25 | 26 | /* OPA member enumeration */ 27 | typedef enum 28 | { 29 | OPA1 = 0, 30 | OPA2, 31 | OPA3, 32 | OPA4 33 | } OPA_Num_TypeDef; 34 | 35 | /* OPA PSEL enumeration */ 36 | typedef enum 37 | { 38 | CHP0 = 0, 39 | CHP1 40 | } OPA_PSEL_TypeDef; 41 | 42 | /* OPA NSEL enumeration */ 43 | typedef enum 44 | { 45 | CHN0 = 0, 46 | CHN1 47 | } OPA_NSEL_TypeDef; 48 | 49 | /* OPA out channel enumeration */ 50 | typedef enum 51 | { 52 | OUT_IO_OUT0 = 0, 53 | OUT_IO_OUT1 54 | } OPA_Mode_TypeDef; 55 | 56 | /* OPA Init Structure definition */ 57 | typedef struct 58 | { 59 | OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ 60 | OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ 61 | OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ 62 | OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ 63 | } OPA_InitTypeDef; 64 | 65 | void OPA_DeInit(void); 66 | void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); 67 | void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); 68 | void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif 73 | 74 | #endif 75 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_dbgmcu.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * DBGMCU firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_DBGMCU_H 14 | #define __CH32V20x_DBGMCU_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 23 | #define DBGMCU_STOP ((uint32_t)0x00000002) 24 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 25 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 26 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 27 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) 28 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) 29 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) 30 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) 31 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) 32 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) 33 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) 34 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) 35 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) 36 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) 37 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) 38 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 39 | #define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) 40 | #define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) 41 | 42 | uint32_t DBGMCU_GetREVID(void); 43 | uint32_t DBGMCU_GetDEVID(void); 44 | uint32_t __get_DEBUG_CR(void); 45 | void __set_DEBUG_CR(uint32_t value); 46 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_pwr.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_pwr.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the PWR 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_PWR_H 14 | #define __CH32V20x_PWR_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* PVD_detection_level */ 23 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 24 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 25 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 26 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 27 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 28 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 29 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 30 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 31 | 32 | /* Regulator_state_is_STOP_mode */ 33 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 34 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 35 | 36 | /* STOP_mode_entry */ 37 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 38 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 39 | 40 | /* PWR_Flag */ 41 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 42 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 43 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 44 | 45 | void PWR_DeInit(void); 46 | void PWR_BackupAccessCmd(FunctionalState NewState); 47 | void PWR_PVDCmd(FunctionalState NewState); 48 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 49 | void PWR_WakeUpPinCmd(FunctionalState NewState); 50 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 51 | void PWR_EnterSTANDBYMode(void); 52 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 53 | void PWR_ClearFlag(uint32_t PWR_FLAG); 54 | void PWR_EnterSTANDBYMode_RAM(void); 55 | void PWR_EnterSTANDBYMode_RAM_LV(void); 56 | void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); 57 | void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); 58 | void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif 65 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_opa.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_opa.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the OPA firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_opa.h" 13 | 14 | #define OPA_MASK ((uint32_t)0x000F) 15 | #define OPA_Total_NUM 4 16 | 17 | /********************************************************************* 18 | * @fn OPA_DeInit 19 | * 20 | * @brief Deinitializes the OPA peripheral registers to their default 21 | * reset values. 22 | * 23 | * @return none 24 | */ 25 | void OPA_DeInit(void) 26 | { 27 | OPA->CR = 0; 28 | } 29 | 30 | /********************************************************************* 31 | * @fn OPA_Init 32 | * 33 | * @brief Initializes the OPA peripheral according to the specified 34 | * parameters in the OPA_InitStruct. 35 | * 36 | * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure 37 | * 38 | * @return none 39 | */ 40 | void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) 41 | { 42 | uint32_t tmp = 0; 43 | tmp = OPA->CR; 44 | tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); 45 | tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); 46 | OPA->CR = tmp; 47 | } 48 | 49 | /********************************************************************* 50 | * @fn OPA_StructInit 51 | * 52 | * @brief Fills each OPA_StructInit member with its reset value. 53 | * 54 | * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure 55 | * 56 | * @return none 57 | */ 58 | void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) 59 | { 60 | OPA_InitStruct->Mode = OUT_IO_OUT1; 61 | OPA_InitStruct->PSEL = CHP0; 62 | OPA_InitStruct->NSEL = CHN0; 63 | OPA_InitStruct->OPA_NUM = OPA1; 64 | } 65 | 66 | /********************************************************************* 67 | * @fn OPA_Cmd 68 | * 69 | * @brief Enables or disables the specified OPA peripheral. 70 | * 71 | * @param OPA_NUM - Select OPA 72 | * NewState - ENABLE or DISABLE. 73 | * 74 | * @return none 75 | */ 76 | void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) 77 | { 78 | if(NewState == ENABLE) 79 | { 80 | OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); 81 | } 82 | else 83 | { 84 | OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); 85 | } 86 | } 87 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_crc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_crc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the CRC firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_crc.h" 13 | 14 | /********************************************************************* 15 | * @fn CRC_ResetDR 16 | * 17 | * @brief Resets the CRC Data register (DR). 18 | * 19 | * @return none 20 | */ 21 | void CRC_ResetDR(void) 22 | { 23 | CRC->CTLR = CRC_CTLR_RESET; 24 | } 25 | 26 | /********************************************************************* 27 | * @fn CRC_CalcCRC 28 | * 29 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 30 | * 31 | * @param Data - data word(32-bit) to compute its CRC. 32 | * 33 | * @return 32-bit CRC. 34 | */ 35 | uint32_t CRC_CalcCRC(uint32_t Data) 36 | { 37 | CRC->DATAR = Data; 38 | 39 | return (CRC->DATAR); 40 | } 41 | 42 | /********************************************************************* 43 | * @fn CRC_CalcBlockCRC 44 | * 45 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 46 | * 47 | * @param pBuffer - pointer to the buffer containing the data to be computed. 48 | * BufferLength - length of the buffer to be computed. 49 | * 50 | * @return 32-bit CRC. 51 | */ 52 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 53 | { 54 | uint32_t index = 0; 55 | 56 | for(index = 0; index < BufferLength; index++){ 57 | CRC->DATAR = pBuffer[index]; 58 | } 59 | 60 | return (CRC->DATAR); 61 | } 62 | 63 | /********************************************************************* 64 | * @fn CRC_GetCRC 65 | * 66 | * @brief Returns the current CRC value. 67 | * 68 | * @return 32-bit CRC. 69 | */ 70 | uint32_t CRC_GetCRC(void) 71 | { 72 | return (CRC->DATAR); 73 | } 74 | 75 | /********************************************************************* 76 | * @fn CRC_SetIDRegister 77 | * 78 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 79 | * 80 | * @param IDValue - 8-bit value to be stored in the ID register. 81 | * 82 | * @return none 83 | */ 84 | void CRC_SetIDRegister(uint8_t IDValue) 85 | { 86 | CRC->IDATAR = IDValue; 87 | } 88 | 89 | /********************************************************************* 90 | * @fn CRC_GetIDRegister 91 | * 92 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register. 93 | * 94 | * @return 8-bit value of the ID register. 95 | */ 96 | uint8_t CRC_GetIDRegister(void) 97 | { 98 | return (CRC->IDATAR); 99 | } 100 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_rtc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_rtc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the RTC 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_RTC_H 14 | #define __CH32V20x_RTC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | typedef enum 23 | { 24 | Level_32 = 2, 25 | Level_64, 26 | Level_128, 27 | 28 | } Cali_LevelTypeDef; 29 | 30 | /* RTC_interrupts_define */ 31 | #define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ 32 | #define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ 33 | #define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ 34 | 35 | /* RTC_interrupts_flags */ 36 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ 37 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ 38 | #define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ 39 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ 40 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ 41 | 42 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 43 | #define RB_OSC32K_HTUNE (0x1FE0) 44 | #define RB_OSC32K_LTUNE (0x1F) 45 | 46 | #define RB_OSC_CAL_HALT (0x80) 47 | #define RB_OSC_CAL_EN (0x02) 48 | #define RB_OSC_CAL_INT_EN (0x01) 49 | 50 | #define RB_OSC_CAL_OV_CNT (0xFF) 51 | 52 | #define RB_OSC_CAL_IF_END (1 << 15) 53 | #define RB_OSC_CAL_CNT_OV (1 << 14) 54 | #define RB_OSC_CAL_CNT (0x3FFF) 55 | 56 | #define RB_CAL_LP_EN (1 << 6) 57 | #define RB_CAL_WKUP_EN (1 << 5) 58 | #define RB_OSC_HALT_MD (1 << 4) 59 | #define RB_OSC_CNT_VLU (0x0F) 60 | 61 | 62 | #ifdef CLK_OSC32K 63 | #if ( CLK_OSC32K == 1 ) 64 | #define CAB_LSIFQ 32000 65 | #else 66 | #define CAB_LSIFQ 32768 67 | #endif 68 | #else 69 | #define CAB_LSIFQ 32000 70 | #endif 71 | #endif 72 | 73 | 74 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 75 | void RTC_EnterConfigMode(void); 76 | void RTC_ExitConfigMode(void); 77 | uint32_t RTC_GetCounter(void); 78 | void RTC_SetCounter(uint32_t CounterValue); 79 | void RTC_SetPrescaler(uint32_t PrescalerValue); 80 | void RTC_SetAlarm(uint32_t AlarmValue); 81 | uint32_t RTC_GetDivider(void); 82 | void RTC_WaitForLastTask(void); 83 | void RTC_WaitForSynchro(void); 84 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 85 | void RTC_ClearFlag(uint16_t RTC_FLAG); 86 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 87 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 88 | 89 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 90 | void Calibration_LSI(Cali_LevelTypeDef cali_Lv); 91 | 92 | #endif 93 | 94 | #ifdef __cplusplus 95 | } 96 | #endif 97 | 98 | #endif 99 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_dbgmcu.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the DBGMCU firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_dbgmcu.h" 13 | 14 | #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) 15 | 16 | /********************************************************************* 17 | * @fn DBGMCU_GetREVID 18 | * 19 | * @brief Returns the device revision identifier. 20 | * 21 | * @return Revision identifier. 22 | */ 23 | uint32_t DBGMCU_GetREVID(void) 24 | { 25 | return ((*(uint32_t *)0x1FFFF704) >> 16); 26 | } 27 | 28 | /********************************************************************* 29 | * @fn DBGMCU_GetDEVID 30 | * 31 | * @brief Returns the device identifier. 32 | * 33 | * @return Device identifier. 34 | */ 35 | uint32_t DBGMCU_GetDEVID(void) 36 | { 37 | return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); 38 | } 39 | 40 | /********************************************************************* 41 | * @fn __get_DEBUG_CR 42 | * 43 | * @brief Return the DEBUGE Control Register 44 | * 45 | * @return DEBUGE Control value 46 | */ 47 | uint32_t __get_DEBUG_CR(void) 48 | { 49 | uint32_t result; 50 | 51 | __asm volatile("csrr %0,""0x7C0" : "=r"(result)); 52 | return (result); 53 | } 54 | 55 | /********************************************************************* 56 | * @fn __set_DEBUG_CR 57 | * 58 | * @brief Set the DEBUGE Control Register 59 | * 60 | * @param value - set DEBUGE Control value 61 | * 62 | * @return none 63 | */ 64 | void __set_DEBUG_CR(uint32_t value) 65 | { 66 | __asm volatile("csrw 0x7C0, %0" : : "r"(value)); 67 | } 68 | 69 | 70 | /********************************************************************* 71 | * @fn DBGMCU_Config 72 | * 73 | * @brief Configures the specified peripheral and low power mode behavior 74 | * when the MCU under Debug mode. 75 | * 76 | * @param DBGMCU_Periph - specifies the peripheral and low power mode. 77 | * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted 78 | * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted 79 | * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted 80 | * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted 81 | * NewState - ENABLE or DISABLE. 82 | * 83 | * @return none 84 | */ 85 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 86 | { 87 | uint32_t val; 88 | 89 | if(NewState != DISABLE) 90 | { 91 | __set_DEBUG_CR(DBGMCU_Periph); 92 | } 93 | else 94 | { 95 | val = __get_DEBUG_CR(); 96 | val &= ~(uint32_t)DBGMCU_Periph; 97 | __set_DEBUG_CR(val); 98 | } 99 | 100 | } 101 | -------------------------------------------------------------------------------- /User/audio.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | s16 Calibrattion_Val = 0; 4 | 5 | void ADC_Function_Init(void) 6 | { 7 | ADC_InitTypeDef ADC_InitStructure = {0}; 8 | GPIO_InitTypeDef GPIO_InitStructure = {0}; 9 | 10 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 11 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); 12 | RCC_ADCCLKConfig(RCC_PCLK2_Div8); 13 | 14 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; 15 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; 16 | GPIO_Init(GPIOA, &GPIO_InitStructure); 17 | 18 | ADC_DeInit(ADC1); 19 | ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; 20 | ADC_InitStructure.ADC_ScanConvMode = DISABLE; 21 | ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; 22 | ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; 23 | ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; 24 | ADC_InitStructure.ADC_NbrOfChannel = 1; 25 | ADC_Init(ADC1, &ADC_InitStructure); 26 | 27 | ADC_DMACmd(ADC1, ENABLE); 28 | ADC_Cmd(ADC1, ENABLE); 29 | 30 | ADC_BufferCmd(ADC1, DISABLE); //disable buffer 31 | ADC_ResetCalibration(ADC1); 32 | while(ADC_GetResetCalibrationStatus(ADC1)); 33 | ADC_StartCalibration(ADC1); 34 | while(ADC_GetCalibrationStatus(ADC1)); 35 | Calibrattion_Val = Get_CalibrationValue(ADC1); 36 | } 37 | 38 | u16 Get_ADC_Val(u8 ch) 39 | { 40 | u16 val; 41 | 42 | ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5); 43 | ADC_SoftwareStartConvCmd(ADC1, ENABLE); 44 | 45 | while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC)); 46 | val = ADC_GetConversionValue(ADC1); 47 | 48 | return val; 49 | } 50 | 51 | void DMA_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsize) 52 | { 53 | DMA_InitTypeDef DMA_InitStructure = {0}; 54 | 55 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); 56 | 57 | DMA_DeInit(DMA_CHx); 58 | DMA_InitStructure.DMA_PeripheralBaseAddr = ppadr; 59 | DMA_InitStructure.DMA_MemoryBaseAddr = memadr; 60 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; 61 | DMA_InitStructure.DMA_BufferSize = bufsize; 62 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 63 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 64 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; 65 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; 66 | DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; 67 | DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; 68 | DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; 69 | DMA_Init(DMA_CHx, &DMA_InitStructure); 70 | } 71 | 72 | u16 Get_ConversionVal(s16 val) 73 | { 74 | if((val + Calibrattion_Val) < 0 || val==0) 75 | return 0; 76 | if((Calibrattion_Val + val) > 4095||val==4095) 77 | return 4095; 78 | return (val + Calibrattion_Val); 79 | } 80 | 81 | int recordSamples(int sampleCount, uint16_t *samples) 82 | { 83 | u16 i; 84 | SystemCoreClockUpdate(); 85 | Delay_Init(); 86 | ADC_Function_Init(); 87 | DMA_Tx_Init(DMA1_Channel1, (u32)&ADC1->RDATAR, (u32)samples, sampleCount); 88 | DMA_Cmd(DMA1_Channel1, ENABLE); 89 | ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_239Cycles5); 90 | ADC_SoftwareStartConvCmd(ADC1, ENABLE); 91 | Delay_Ms(2000); 92 | ADC_SoftwareStartConvCmd(ADC1, DISABLE); 93 | } 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | -------------------------------------------------------------------------------- /Ld/Link.ld: -------------------------------------------------------------------------------- 1 | ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } -------------------------------------------------------------------------------- /User/fastFrame.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | const int xres = 8; 4 | const int yres = 8; 5 | const int colorBits = 12; 6 | const int colorCount = 1 << colorBits; 7 | const int colorMax = colorCount - 1; 8 | unsigned short frameBuffer[yres][xres][3]; 9 | volatile unsigned long portFrameBuffer[colorBits][yres]; 10 | const int minTicksPerSubframe = 37; 11 | //const int minTicksPerSubframe = 128; 12 | 13 | #include "rick.h" 14 | 15 | void pix(int x, int y, int r, int g, int b) 16 | { 17 | frameBuffer[y][x][0] = r; 18 | frameBuffer[y][x][1] = g; 19 | frameBuffer[y][x][2] = b; 20 | } 21 | 22 | void convertFrameBuffer(unsigned short *frameBuffer, int bitShift = 0) 23 | { 24 | for(int bit = 0; bit < colorBits; bit++) 25 | for(int y = 0; y < yres; y++) 26 | { 27 | int r = 0; 28 | int g = 0; 29 | int b = 0; 30 | for(int x = 0; x < xres; x++) 31 | { 32 | r |= ((frameBuffer[((y * xres) + x) * 3 + 0] >> (bit + bitShift)) & 1) << x; 33 | g |= ((frameBuffer[((y * xres) + x) * 3 + 1] >> (bit + bitShift)) & 1) << x; 34 | b |= ((frameBuffer[((y * xres) + x) * 3 + 2] >> (bit + bitShift)) & 1) << x; 35 | } 36 | portFrameBuffer[bit][y] = (b << 16) | (r << 8) | g; 37 | } 38 | } 39 | 40 | void copyPortFrameBuffer(const unsigned long *f, int sourceBits = 8, int bitShift = 0) 41 | { 42 | for(int i = 0; i < sourceBits * yres; i++) 43 | ((unsigned long *)portFrameBuffer[bitShift])[i] = f[i]; 44 | for(int i = 0; i < bitShift * yres; i++) 45 | ((unsigned long *)portFrameBuffer[0])[i] = 0; 46 | for(int i = 0; i < (colorBits - bitShift - sourceBits) * yres; i++) 47 | ((unsigned long *)portFrameBuffer[bitShift + sourceBits])[i] = 0; 48 | } 49 | 50 | volatile int subFrame = 0; 51 | volatile int frame = 0; 52 | 53 | void __attribute__((interrupt("WCH-Interrupt-fast"))) SystickIntSubframe_(void) //not optimized 54 | { 55 | subFrame++; 56 | SysTick->SR = 0; 57 | static int y = 0; 58 | static int bit = 0; 59 | unsigned long ports = portFrameBuffer[bit][y]; 60 | GPIOB->OUTDR = ports & 0xffff; 61 | GPIOC->OUTDR = (256 << y) | (ports >> 16); 62 | SysTick->CMP = minTicksPerSubframe << bit; 63 | y++; 64 | if(y == yres) 65 | { 66 | y = 0; 67 | bit++; 68 | if(bit == colorBits) 69 | { 70 | bit = 0; 71 | frame++; 72 | } 73 | } 74 | } 75 | 76 | void __attribute__((interrupt("WCH-Interrupt-fast"))) SystickIntSubframe(void) 77 | { 78 | static int y = 0; 79 | static int bit = 0; 80 | static unsigned short *p = (unsigned short*)portFrameBuffer[0]; 81 | SysTick->CMP = minTicksPerSubframe << bit; 82 | subFrame++; 83 | SysTick->SR = 0; 84 | GPIOB->OUTDR = *(p++); 85 | GPIOC->OUTDR = (256 << y) | *(p++); 86 | //GPIOC->BCR = (0b11111111 << 8); 87 | if(y == yres - 1) 88 | { 89 | y = 0; 90 | if(bit == colorBits - 1) 91 | { 92 | frame++; 93 | bit = 0; 94 | p = (unsigned short*)portFrameBuffer[0]; 95 | } 96 | else 97 | bit++; 98 | } 99 | else 100 | y++; 101 | } 102 | 103 | void initSystick() 104 | { 105 | NVIC_SetPriority(SysTicK_IRQn, 1); 106 | SetVTFIRQ((u32)SystickIntSubframe, SysTicK_IRQn, 0, ENABLE); 107 | NVIC_EnableIRQ(SysTicK_IRQn); 108 | 109 | SysTick->SR = 0; 110 | SysTick->CNT = 0; 111 | SysTick->CMP = minTicksPerSubframe; 112 | SysTick->CTLR = 1 | //enable 113 | 2 | //interrupt enable 114 | 4 | //HCLK as source 115 | 15; //restart counting 116 | } 117 | 118 | void initFastFrame() 119 | { 120 | //R B08-B15 121 | //G B00-B07 122 | //B C00-C08 123 | //ROW C08-C15 124 | GPIO_InitTypeDef GPIO_InitStructure = {0}; 125 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 126 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 127 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); 128 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); 129 | for(int i = 0; i < 16; i++) 130 | { 131 | GPIO_InitStructure.GPIO_Pin = 1 << i; 132 | GPIO_Init(GPIOB, &GPIO_InitStructure); 133 | GPIO_Init(GPIOC, &GPIO_InitStructure); 134 | } 135 | initSystick(); 136 | } 137 | 138 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_iwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_iwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the IWDG firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_iwdg.h" 13 | 14 | /* CTLR register bit mask */ 15 | #define CTLR_KEY_Reload ((uint16_t)0xAAAA) 16 | #define CTLR_KEY_Enable ((uint16_t)0xCCCC) 17 | 18 | /********************************************************************* 19 | * @fn IWDG_WriteAccessCmd 20 | * 21 | * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. 22 | * 23 | * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and 24 | * IWDG_RLDR registers. 25 | * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and 26 | * IWDG_RLDR registers. 27 | * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR 28 | * and IWDG_RLDR registers. 29 | * 30 | * @return none 31 | */ 32 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 33 | { 34 | IWDG->CTLR = IWDG_WriteAccess; 35 | } 36 | 37 | /********************************************************************* 38 | * @fn IWDG_SetPrescaler 39 | * 40 | * @brief Sets IWDG Prescaler value. 41 | * 42 | * @param IWDG_Prescaler - specifies the IWDG Prescaler value. 43 | * IWDG_Prescaler_4 - IWDG prescaler set to 4. 44 | * IWDG_Prescaler_8 - IWDG prescaler set to 8. 45 | * IWDG_Prescaler_16 - IWDG prescaler set to 16. 46 | * IWDG_Prescaler_32 - IWDG prescaler set to 32. 47 | * IWDG_Prescaler_64 - IWDG prescaler set to 64. 48 | * IWDG_Prescaler_128 - IWDG prescaler set to 128. 49 | * IWDG_Prescaler_256 - IWDG prescaler set to 256. 50 | * 51 | * @return none 52 | */ 53 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 54 | { 55 | IWDG->PSCR = IWDG_Prescaler; 56 | } 57 | 58 | /********************************************************************* 59 | * @fn IWDG_SetReload 60 | * 61 | * @brief Sets IWDG Reload value. 62 | * 63 | * @param Reload - specifies the IWDG Reload value. 64 | * This parameter must be a number between 0 and 0x0FFF. 65 | * 66 | * @return none 67 | */ 68 | void IWDG_SetReload(uint16_t Reload) 69 | { 70 | IWDG->RLDR = Reload; 71 | } 72 | 73 | /********************************************************************* 74 | * @fn IWDG_ReloadCounter 75 | * 76 | * @brief Reloads IWDG counter with value defined in the reload register. 77 | * 78 | * @return none 79 | */ 80 | void IWDG_ReloadCounter(void) 81 | { 82 | IWDG->CTLR = CTLR_KEY_Reload; 83 | } 84 | 85 | /********************************************************************* 86 | * @fn IWDG_Enable 87 | * 88 | * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). 89 | * 90 | * @return none 91 | */ 92 | void IWDG_Enable(void) 93 | { 94 | IWDG->CTLR = CTLR_KEY_Enable; 95 | } 96 | 97 | /********************************************************************* 98 | * @fn IWDG_GetFlagStatus 99 | * 100 | * @brief Checks whether the specified IWDG flag is set or not. 101 | * 102 | * @param IWDG_FLAG - specifies the flag to check. 103 | * IWDG_FLAG_PVU - Prescaler Value Update on going. 104 | * IWDG_FLAG_RVU - Reload Value Update on going. 105 | * 106 | * @return none 107 | */ 108 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 109 | { 110 | FlagStatus bitstatus = RESET; 111 | 112 | if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) 113 | { 114 | bitstatus = SET; 115 | } 116 | else 117 | { 118 | bitstatus = RESET; 119 | } 120 | 121 | return bitstatus; 122 | } 123 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_exti.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_exti.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * EXTI firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_EXTI_H 14 | #define __CH32V20x_EXTI_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* EXTI mode enumeration */ 23 | typedef enum 24 | { 25 | EXTI_Mode_Interrupt = 0x00, 26 | EXTI_Mode_Event = 0x04 27 | } EXTIMode_TypeDef; 28 | 29 | /* EXTI Trigger enumeration */ 30 | typedef enum 31 | { 32 | EXTI_Trigger_Rising = 0x08, 33 | EXTI_Trigger_Falling = 0x0C, 34 | EXTI_Trigger_Rising_Falling = 0x10 35 | } EXTITrigger_TypeDef; 36 | 37 | /* EXTI Init Structure definition */ 38 | typedef struct 39 | { 40 | uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. 41 | This parameter can be any combination of @ref EXTI_Lines */ 42 | 43 | EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. 44 | This parameter can be a value of @ref EXTIMode_TypeDef */ 45 | 46 | EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. 47 | This parameter can be a value of @ref EXTIMode_TypeDef */ 48 | 49 | FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. 50 | This parameter can be set either to ENABLE or DISABLE */ 51 | } EXTI_InitTypeDef; 52 | 53 | /* EXTI_Lines */ 54 | #define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ 55 | #define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ 56 | #define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ 57 | #define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ 58 | #define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ 59 | #define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ 60 | #define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ 61 | #define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ 62 | #define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ 63 | #define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ 64 | #define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ 65 | #define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ 66 | #define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ 67 | #define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ 68 | #define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ 69 | #define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ 70 | #define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ 71 | #define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ 72 | #define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \ 73 | Wakeup from suspend event */ 74 | #define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ 75 | #define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ 76 | 77 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 78 | #define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */ 79 | 80 | #endif 81 | 82 | void EXTI_DeInit(void); 83 | void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); 84 | void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); 85 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 86 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 87 | void EXTI_ClearFlag(uint32_t EXTI_Line); 88 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 89 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif 96 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_wwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_wwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the WWDG firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_wwdg.h" 13 | #include "ch32v20x_rcc.h" 14 | 15 | /* CTLR register bit mask */ 16 | #define CTLR_WDGA_Set ((uint32_t)0x00000080) 17 | 18 | /* CFGR register bit mask */ 19 | #define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 20 | #define CFGR_W_Mask ((uint32_t)0xFFFFFF80) 21 | #define BIT_Mask ((uint8_t)0x7F) 22 | 23 | /********************************************************************* 24 | * @fn WWDG_DeInit 25 | * 26 | * @brief Deinitializes the WWDG peripheral registers to their default reset values 27 | * 28 | * @return none 29 | */ 30 | void WWDG_DeInit(void) 31 | { 32 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 33 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 34 | } 35 | 36 | /********************************************************************* 37 | * @fn WWDG_SetPrescaler 38 | * 39 | * @brief Sets the WWDG Prescaler 40 | * 41 | * @param WWDG_Prescaler - specifies the WWDG Prescaler 42 | * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 43 | * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 44 | * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 45 | * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 46 | * 47 | * @return none 48 | */ 49 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 50 | { 51 | uint32_t tmpreg = 0; 52 | tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; 53 | tmpreg |= WWDG_Prescaler; 54 | WWDG->CFGR = tmpreg; 55 | } 56 | 57 | /********************************************************************* 58 | * @fn WWDG_SetWindowValue 59 | * 60 | * @brief Sets the WWDG window value 61 | * 62 | * @param WindowValue - specifies the window value to be compared to the 63 | * downcounter,which must be lower than 0x80 64 | * 65 | * @return none 66 | */ 67 | void WWDG_SetWindowValue(uint8_t WindowValue) 68 | { 69 | __IO uint32_t tmpreg = 0; 70 | 71 | tmpreg = WWDG->CFGR & CFGR_W_Mask; 72 | 73 | tmpreg |= WindowValue & (uint32_t)BIT_Mask; 74 | 75 | WWDG->CFGR = tmpreg; 76 | } 77 | 78 | /********************************************************************* 79 | * @fn WWDG_EnableIT 80 | * 81 | * @brief Enables the WWDG Early Wakeup interrupt(EWI) 82 | * 83 | * @return none 84 | */ 85 | void WWDG_EnableIT(void) 86 | { 87 | WWDG->CFGR |= (1 << 9); 88 | } 89 | 90 | /********************************************************************* 91 | * @fn WWDG_SetCounter 92 | * 93 | * @brief Sets the WWDG counter value 94 | * 95 | * @param Counter - specifies the watchdog counter value,which must be a 96 | * number between 0x40 and 0x7F 97 | * 98 | * @return none 99 | */ 100 | void WWDG_SetCounter(uint8_t Counter) 101 | { 102 | WWDG->CTLR = Counter & BIT_Mask; 103 | } 104 | 105 | /********************************************************************* 106 | * @fn WWDG_Enable 107 | * 108 | * @brief Enables WWDG and load the counter value 109 | * 110 | * @param Counter - specifies the watchdog counter value,which must be a 111 | * number between 0x40 and 0x7F 112 | * @return none 113 | */ 114 | void WWDG_Enable(uint8_t Counter) 115 | { 116 | WWDG->CTLR = CTLR_WDGA_Set | Counter; 117 | } 118 | 119 | /********************************************************************* 120 | * @fn WWDG_GetFlagStatus 121 | * 122 | * @brief Checks whether the Early Wakeup interrupt flag is set or not 123 | * 124 | * @return The new state of the Early Wakeup interrupt flag (SET or RESET) 125 | */ 126 | FlagStatus WWDG_GetFlagStatus(void) 127 | { 128 | return (FlagStatus)(WWDG->STATR); 129 | } 130 | 131 | /********************************************************************* 132 | * @fn WWDG_ClearFlag 133 | * 134 | * @brief Clears Early Wakeup interrupt flag 135 | * 136 | * @return none 137 | */ 138 | void WWDG_ClearFlag(void) 139 | { 140 | WWDG->STATR = (uint32_t)RESET; 141 | } 142 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_bkp.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_bkp.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * BKP firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_BKP_H 14 | #define __CH32V20x_BKP_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* Tamper_Pin_active_level */ 23 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 24 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 25 | 26 | /* RTC_output_source_to_output_on_the_Tamper_pin */ 27 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 28 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 29 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 30 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 31 | 32 | /* Data_Backup_Register */ 33 | #define BKP_DR1 ((uint16_t)0x0004) 34 | #define BKP_DR2 ((uint16_t)0x0008) 35 | #define BKP_DR3 ((uint16_t)0x000C) 36 | #define BKP_DR4 ((uint16_t)0x0010) 37 | #define BKP_DR5 ((uint16_t)0x0014) 38 | #define BKP_DR6 ((uint16_t)0x0018) 39 | #define BKP_DR7 ((uint16_t)0x001C) 40 | #define BKP_DR8 ((uint16_t)0x0020) 41 | #define BKP_DR9 ((uint16_t)0x0024) 42 | #define BKP_DR10 ((uint16_t)0x0028) 43 | #define BKP_DR11 ((uint16_t)0x0040) 44 | #define BKP_DR12 ((uint16_t)0x0044) 45 | #define BKP_DR13 ((uint16_t)0x0048) 46 | #define BKP_DR14 ((uint16_t)0x004C) 47 | #define BKP_DR15 ((uint16_t)0x0050) 48 | #define BKP_DR16 ((uint16_t)0x0054) 49 | #define BKP_DR17 ((uint16_t)0x0058) 50 | #define BKP_DR18 ((uint16_t)0x005C) 51 | #define BKP_DR19 ((uint16_t)0x0060) 52 | #define BKP_DR20 ((uint16_t)0x0064) 53 | #define BKP_DR21 ((uint16_t)0x0068) 54 | #define BKP_DR22 ((uint16_t)0x006C) 55 | #define BKP_DR23 ((uint16_t)0x0070) 56 | #define BKP_DR24 ((uint16_t)0x0074) 57 | #define BKP_DR25 ((uint16_t)0x0078) 58 | #define BKP_DR26 ((uint16_t)0x007C) 59 | #define BKP_DR27 ((uint16_t)0x0080) 60 | #define BKP_DR28 ((uint16_t)0x0084) 61 | #define BKP_DR29 ((uint16_t)0x0088) 62 | #define BKP_DR30 ((uint16_t)0x008C) 63 | #define BKP_DR31 ((uint16_t)0x0090) 64 | #define BKP_DR32 ((uint16_t)0x0094) 65 | #define BKP_DR33 ((uint16_t)0x0098) 66 | #define BKP_DR34 ((uint16_t)0x009C) 67 | #define BKP_DR35 ((uint16_t)0x00A0) 68 | #define BKP_DR36 ((uint16_t)0x00A4) 69 | #define BKP_DR37 ((uint16_t)0x00A8) 70 | #define BKP_DR38 ((uint16_t)0x00AC) 71 | #define BKP_DR39 ((uint16_t)0x00B0) 72 | #define BKP_DR40 ((uint16_t)0x00B4) 73 | #define BKP_DR41 ((uint16_t)0x00B8) 74 | #define BKP_DR42 ((uint16_t)0x00BC) 75 | 76 | void BKP_DeInit(void); 77 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 78 | void BKP_TamperPinCmd(FunctionalState NewState); 79 | void BKP_ITConfig(FunctionalState NewState); 80 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 81 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 82 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 83 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 84 | FlagStatus BKP_GetFlagStatus(void); 85 | void BKP_ClearFlag(void); 86 | ITStatus BKP_GetITStatus(void); 87 | void BKP_ClearITPendingBit(void); 88 | 89 | #ifdef __cplusplus 90 | } 91 | #endif 92 | 93 | #endif 94 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_misc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_misc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the miscellaneous firmware functions . 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_misc.h" 13 | 14 | __IO uint32_t NVIC_Priority_Group = 0; 15 | 16 | /********************************************************************* 17 | * @fn NVIC_PriorityGroupConfig 18 | * 19 | * @brief Configures the priority grouping - pre-emption priority and subpriority. 20 | * 21 | * @param NVIC_PriorityGroup - specifies the priority grouping bits length. 22 | * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority 23 | * 4 bits for subpriority 24 | * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority 25 | * 3 bits for subpriority 26 | * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority 27 | * 2 bits for subpriority 28 | * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority 29 | * 1 bits for subpriority 30 | * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority 31 | * 0 bits for subpriority 32 | * 33 | * @return none 34 | */ 35 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 36 | { 37 | NVIC_Priority_Group = NVIC_PriorityGroup; 38 | } 39 | 40 | /********************************************************************* 41 | * @fn NVIC_Init 42 | * 43 | * @brief Initializes the NVIC peripheral according to the specified parameters in 44 | * the NVIC_InitStruct. 45 | * 46 | * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the 47 | * configuration information for the specified NVIC peripheral. 48 | * 49 | * @return none 50 | */ 51 | void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) 52 | { 53 | uint8_t tmppre = 0; 54 | 55 | if(NVIC_Priority_Group == NVIC_PriorityGroup_0) 56 | { 57 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); 58 | } 59 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) 60 | { 61 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) 62 | { 63 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 64 | } 65 | else 66 | { 67 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 68 | } 69 | } 70 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) 71 | { 72 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) 73 | { 74 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 75 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 76 | } 77 | else 78 | { 79 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); 80 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 81 | } 82 | } 83 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) 84 | { 85 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) 86 | { 87 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 88 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 89 | } 90 | else 91 | { 92 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); 93 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 94 | } 95 | } 96 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) 97 | { 98 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); 99 | } 100 | 101 | if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 102 | { 103 | NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 104 | } 105 | else 106 | { 107 | NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 108 | } 109 | } 110 | -------------------------------------------------------------------------------- /FastFrame.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_exti.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_exti.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the EXTI firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_exti.h" 13 | 14 | /* No interrupt selected */ 15 | #define EXTI_LINENONE ((uint32_t)0x00000) 16 | 17 | /********************************************************************* 18 | * @fn EXTI_DeInit 19 | * 20 | * @brief Deinitializes the EXTI peripheral registers to their default 21 | * reset values. 22 | * 23 | * @return none. 24 | */ 25 | void EXTI_DeInit(void) 26 | { 27 | EXTI->INTENR = 0x00000000; 28 | EXTI->EVENR = 0x00000000; 29 | EXTI->RTENR = 0x00000000; 30 | EXTI->FTENR = 0x00000000; 31 | EXTI->INTFR = 0x000FFFFF; 32 | } 33 | 34 | /********************************************************************* 35 | * @fn EXTI_Init 36 | * 37 | * @brief Initializes the EXTI peripheral according to the specified 38 | * parameters in the EXTI_InitStruct. 39 | * 40 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure 41 | * 42 | * @return none. 43 | */ 44 | void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) 45 | { 46 | uint32_t tmp = 0; 47 | 48 | tmp = (uint32_t)EXTI_BASE; 49 | if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) 50 | { 51 | EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; 52 | EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; 53 | tmp += EXTI_InitStruct->EXTI_Mode; 54 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 55 | EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; 56 | EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; 57 | if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 58 | { 59 | EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; 60 | EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; 61 | } 62 | else 63 | { 64 | tmp = (uint32_t)EXTI_BASE; 65 | tmp += EXTI_InitStruct->EXTI_Trigger; 66 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 67 | } 68 | } 69 | else 70 | { 71 | tmp += EXTI_InitStruct->EXTI_Mode; 72 | *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; 73 | } 74 | } 75 | 76 | /********************************************************************* 77 | * @fn EXTI_StructInit 78 | * 79 | * @brief Fills each EXTI_InitStruct member with its reset value. 80 | * 81 | * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure 82 | * 83 | * @return none. 84 | */ 85 | void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) 86 | { 87 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 88 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 89 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 90 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 91 | } 92 | 93 | /********************************************************************* 94 | * @fn EXTI_GenerateSWInterrupt 95 | * 96 | * @brief Generates a Software interrupt. 97 | * 98 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 99 | * 100 | * @return none. 101 | */ 102 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 103 | { 104 | EXTI->SWIEVR |= EXTI_Line; 105 | } 106 | 107 | /********************************************************************* 108 | * @fn EXTI_GetFlagStatus 109 | * 110 | * @brief Checks whether the specified EXTI line flag is set or not. 111 | * 112 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 113 | * 114 | * @return The new state of EXTI_Line (SET or RESET). 115 | */ 116 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 117 | { 118 | FlagStatus bitstatus = RESET; 119 | if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) 120 | { 121 | bitstatus = SET; 122 | } 123 | else 124 | { 125 | bitstatus = RESET; 126 | } 127 | return bitstatus; 128 | } 129 | 130 | /********************************************************************* 131 | * @fn EXTI_ClearFlag 132 | * 133 | * @brief Clears the EXTI's line pending flags. 134 | * 135 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 136 | * 137 | * @return None 138 | */ 139 | void EXTI_ClearFlag(uint32_t EXTI_Line) 140 | { 141 | EXTI->INTFR = EXTI_Line; 142 | } 143 | 144 | /********************************************************************* 145 | * @fn EXTI_GetITStatus 146 | * 147 | * @brief Checks whether the specified EXTI line is asserted or not. 148 | * 149 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 150 | * 151 | * @return The new state of EXTI_Line (SET or RESET). 152 | */ 153 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 154 | { 155 | ITStatus bitstatus = RESET; 156 | uint32_t enablestatus = 0; 157 | 158 | enablestatus = EXTI->INTENR & EXTI_Line; 159 | if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 160 | { 161 | bitstatus = SET; 162 | } 163 | else 164 | { 165 | bitstatus = RESET; 166 | } 167 | return bitstatus; 168 | } 169 | 170 | /********************************************************************* 171 | * @fn EXTI_ClearITPendingBit 172 | * 173 | * @brief Clears the EXTI's line pending bits. 174 | * 175 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 176 | * 177 | * @return none 178 | */ 179 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 180 | { 181 | EXTI->INTFR = EXTI_Line; 182 | } 183 | -------------------------------------------------------------------------------- /Debug/debug.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : debug.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for UART 7 | * Printf , Delay functions. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #include "debug.h" 14 | 15 | static uint8_t p_us = 0; 16 | static uint16_t p_ms = 0; 17 | /********************************************************************* 18 | * @fn Delay_Init 19 | * 20 | * @brief Initializes Delay Funcation. 21 | * 22 | * @return none 23 | */ 24 | void Delay_Init(void) 25 | { 26 | p_us = SystemCoreClock / 8000000; 27 | p_ms = (uint16_t)p_us * 1000; 28 | } 29 | 30 | /********************************************************************* 31 | * @fn Delay_Us 32 | * 33 | * @brief Microsecond Delay Time. 34 | * 35 | * @param n - Microsecond number. 36 | * 37 | * @return None 38 | */ 39 | void Delay_Us(uint32_t n) 40 | { 41 | uint32_t i; 42 | 43 | SysTick->SR &= ~(1 << 0); 44 | i = (uint32_t)n * p_us; 45 | 46 | SysTick->CMP = i; 47 | SysTick->CTLR |= (1 << 4); 48 | SysTick->CTLR |= (1 << 5) | (1 << 0); 49 | 50 | while((SysTick->SR & (1 << 0)) != (1 << 0)); 51 | SysTick->CTLR &= ~(1 << 0); 52 | } 53 | 54 | /********************************************************************* 55 | * @fn Delay_Ms 56 | * 57 | * @brief Millisecond Delay Time. 58 | * 59 | * @param n - Millisecond number. 60 | * 61 | * @return None 62 | */ 63 | void Delay_Ms(uint32_t n) 64 | { 65 | uint32_t i; 66 | 67 | SysTick->SR &= ~(1 << 0); 68 | i = (uint32_t)n * p_ms; 69 | 70 | SysTick->CMP = i; 71 | SysTick->CTLR |= (1 << 4); 72 | SysTick->CTLR |= (1 << 5) | (1 << 0); 73 | 74 | while((SysTick->SR & (1 << 0)) != (1 << 0)); 75 | SysTick->CTLR &= ~(1 << 0); 76 | } 77 | 78 | /********************************************************************* 79 | * @fn USART_Printf_Init 80 | * 81 | * @brief Initializes the USARTx peripheral. 82 | * 83 | * @param baudrate - USART communication baud rate. 84 | * 85 | * @return None 86 | */ 87 | void USART_Printf_Init(uint32_t baudrate) 88 | { 89 | GPIO_InitTypeDef GPIO_InitStructure; 90 | USART_InitTypeDef USART_InitStructure; 91 | 92 | #if(DEBUG == DEBUG_UART1) 93 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); 94 | 95 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; 96 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 97 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 98 | GPIO_Init(GPIOA, &GPIO_InitStructure); 99 | 100 | #elif(DEBUG == DEBUG_UART2) 101 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); 102 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 103 | 104 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 105 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 106 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 107 | GPIO_Init(GPIOA, &GPIO_InitStructure); 108 | 109 | #elif(DEBUG == DEBUG_UART3) 110 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); 111 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); 112 | 113 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 114 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 115 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 116 | GPIO_Init(GPIOB, &GPIO_InitStructure); 117 | 118 | #endif 119 | 120 | USART_InitStructure.USART_BaudRate = baudrate; 121 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 122 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 123 | USART_InitStructure.USART_Parity = USART_Parity_No; 124 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 125 | USART_InitStructure.USART_Mode = USART_Mode_Tx; 126 | 127 | #if(DEBUG == DEBUG_UART1) 128 | USART_Init(USART1, &USART_InitStructure); 129 | USART_Cmd(USART1, ENABLE); 130 | 131 | #elif(DEBUG == DEBUG_UART2) 132 | USART_Init(USART2, &USART_InitStructure); 133 | USART_Cmd(USART2, ENABLE); 134 | 135 | #elif(DEBUG == DEBUG_UART3) 136 | USART_Init(USART3, &USART_InitStructure); 137 | USART_Cmd(USART3, ENABLE); 138 | 139 | #endif 140 | } 141 | 142 | /********************************************************************* 143 | * @fn _write 144 | * 145 | * @brief Support Printf Function 146 | * 147 | * @param *buf - UART send Data. 148 | * size - Data length 149 | * 150 | * @return size: Data length 151 | */ 152 | __attribute__((used)) 153 | int _write(int fd, char *buf, int size) 154 | { 155 | int i; 156 | 157 | for(i = 0; i < size; i++){ 158 | #if(DEBUG == DEBUG_UART1) 159 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); 160 | USART_SendData(USART1, *buf++); 161 | #elif(DEBUG == DEBUG_UART2) 162 | while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); 163 | USART_SendData(USART2, *buf++); 164 | #elif(DEBUG == DEBUG_UART3) 165 | while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); 166 | USART_SendData(USART3, *buf++); 167 | #endif 168 | } 169 | 170 | return size; 171 | } 172 | 173 | /********************************************************************* 174 | * @fn _sbrk 175 | * 176 | * @brief Change the spatial position of data segment. 177 | * 178 | * @return size: Data length 179 | */ 180 | void *_sbrk(ptrdiff_t incr) 181 | { 182 | extern char _end[]; 183 | extern char _heap_end[]; 184 | static char *curbrk = _end; 185 | 186 | if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) 187 | return NULL - 1; 188 | 189 | curbrk += incr; 190 | return curbrk - incr; 191 | } 192 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_bkp.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_bkp.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the BKP firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_bkp.h" 13 | #include "ch32v20x_rcc.h" 14 | 15 | /* BKP registers bit mask */ 16 | 17 | /* OCTLR register bit mask */ 18 | #define OCTLR_CAL_MASK ((uint16_t)0xFF80) 19 | #define OCTLR_MASK ((uint16_t)0xFC7F) 20 | 21 | /********************************************************************* 22 | * @fn BKP_DeInit 23 | * 24 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 25 | * 26 | * @return none 27 | */ 28 | void BKP_DeInit(void) 29 | { 30 | RCC_BackupResetCmd(ENABLE); 31 | RCC_BackupResetCmd(DISABLE); 32 | } 33 | 34 | /********************************************************************* 35 | * @fn BKP_TamperPinLevelConfig 36 | * 37 | * @brief Configures the Tamper Pin active level. 38 | * 39 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 40 | * BKP_TamperPinLevel_High - Tamper pin active on high level. 41 | * BKP_TamperPinLevel_Low - Tamper pin active on low level. 42 | * 43 | * @return none 44 | */ 45 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 46 | { 47 | if(BKP_TamperPinLevel) 48 | { 49 | BKP->TPCTLR |= (1 << 1); 50 | } 51 | else 52 | { 53 | BKP->TPCTLR &= ~(1 << 1); 54 | } 55 | } 56 | 57 | /********************************************************************* 58 | * @fn BKP_TamperPinCmd 59 | * 60 | * @brief Enables or disables the Tamper Pin activation. 61 | * 62 | * @param NewState - ENABLE or DISABLE. 63 | * 64 | * @return none 65 | */ 66 | void BKP_TamperPinCmd(FunctionalState NewState) 67 | { 68 | if(NewState) 69 | { 70 | BKP->TPCTLR |= (1 << 0); 71 | } 72 | else 73 | { 74 | BKP->TPCTLR &= ~(1 << 0); 75 | } 76 | } 77 | 78 | /********************************************************************* 79 | * @fn BKP_ITConfig 80 | * 81 | * @brief Enables or disables the Tamper Pin Interrupt. 82 | * 83 | * @param NewState - ENABLE or DISABLE. 84 | * 85 | * @return none 86 | */ 87 | void BKP_ITConfig(FunctionalState NewState) 88 | { 89 | if(NewState) 90 | { 91 | BKP->TPCSR |= (1 << 2); 92 | } 93 | else 94 | { 95 | BKP->TPCSR &= ~(1 << 2); 96 | } 97 | } 98 | 99 | /********************************************************************* 100 | * @fn BKP_RTCOutputConfig 101 | * 102 | * @brief Select the RTC output source to output on the Tamper pin. 103 | * 104 | * @param BKP_RTCOutputSource - specifies the RTC output source. 105 | * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. 106 | * BKP_RTCOutputSource_CalibClock - output the RTC clock with 107 | * frequency divided by 64 on the Tamper pin. 108 | * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal 109 | * on the Tamper pin. 110 | * BKP_RTCOutputSource_Second - output the RTC Second pulse 111 | * signal on the Tamper pin. 112 | * 113 | * @return none 114 | */ 115 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 116 | { 117 | uint16_t tmpreg = 0; 118 | 119 | tmpreg = BKP->OCTLR; 120 | tmpreg &= OCTLR_MASK; 121 | tmpreg |= BKP_RTCOutputSource; 122 | BKP->OCTLR = tmpreg; 123 | } 124 | 125 | /********************************************************************* 126 | * @fn BKP_SetRTCCalibrationValue 127 | * 128 | * @brief Sets RTC Clock Calibration value. 129 | * 130 | * @param CalibrationValue - specifies the RTC Clock Calibration value. 131 | * This parameter must be a number between 0 and 0x1F. 132 | * 133 | * @return none 134 | */ 135 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 136 | { 137 | uint16_t tmpreg = 0; 138 | 139 | tmpreg = BKP->OCTLR; 140 | tmpreg &= OCTLR_CAL_MASK; 141 | tmpreg |= CalibrationValue; 142 | BKP->OCTLR = tmpreg; 143 | } 144 | 145 | /********************************************************************* 146 | * @fn BKP_WriteBackupRegister 147 | * 148 | * @brief Writes user data to the specified Data Backup Register. 149 | * 150 | * @param BKP_DR - specifies the Data Backup Register. 151 | * Data - data to write. 152 | * 153 | * @return none 154 | */ 155 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 156 | { 157 | __IO uint32_t tmp = 0; 158 | 159 | tmp = (uint32_t)BKP_BASE; 160 | tmp += BKP_DR; 161 | *(__IO uint32_t *)tmp = Data; 162 | } 163 | 164 | /********************************************************************* 165 | * @fn BKP_ReadBackupRegister 166 | * 167 | * @brief Reads data from the specified Data Backup Register. 168 | * 169 | * @param BKP_DR - specifies the Data Backup Register. 170 | * This parameter can be BKP_DRx where x=[1, 42]. 171 | * 172 | * @return none 173 | */ 174 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 175 | { 176 | __IO uint32_t tmp = 0; 177 | 178 | tmp = (uint32_t)BKP_BASE; 179 | tmp += BKP_DR; 180 | 181 | return (*(__IO uint16_t *)tmp); 182 | } 183 | 184 | /********************************************************************* 185 | * @fn BKP_GetFlagStatus 186 | * 187 | * @brief Checks whether the Tamper Pin Event flag is set or not. 188 | * 189 | * @return FlagStatus - SET or RESET. 190 | */ 191 | FlagStatus BKP_GetFlagStatus(void) 192 | { 193 | if(BKP->TPCSR & (1 << 8)) 194 | { 195 | return SET; 196 | } 197 | else 198 | { 199 | return RESET; 200 | } 201 | } 202 | 203 | /********************************************************************* 204 | * @fn BKP_ClearFlag 205 | * 206 | * @brief Clears Tamper Pin Event pending flag. 207 | * 208 | * @return none 209 | */ 210 | void BKP_ClearFlag(void) 211 | { 212 | BKP->TPCSR |= BKP_CTE; 213 | } 214 | 215 | /********************************************************************* 216 | * @fn BKP_GetITStatus 217 | * 218 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 219 | * 220 | * @return ITStatus - SET or RESET. 221 | */ 222 | ITStatus BKP_GetITStatus(void) 223 | { 224 | if(BKP->TPCSR & (1 << 9)) 225 | { 226 | return SET; 227 | } 228 | else 229 | { 230 | return RESET; 231 | } 232 | } 233 | 234 | /********************************************************************* 235 | * @fn BKP_ClearITPendingBit 236 | * 237 | * @brief Clears Tamper Pin Interrupt pending bit. 238 | * 239 | * @return none 240 | */ 241 | void BKP_ClearITPendingBit(void) 242 | { 243 | BKP->TPCSR |= BKP_CTI; 244 | } 245 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_flash.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_flash.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the FLASH 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_FLASH_H 14 | #define __CH32V20x_FLASH_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* FLASH Status */ 23 | typedef enum 24 | { 25 | FLASH_BUSY = 1, 26 | FLASH_ERROR_PG, 27 | FLASH_ERROR_WRP, 28 | FLASH_COMPLETE, 29 | FLASH_TIMEOUT 30 | } FLASH_Status; 31 | 32 | /* Write Protect */ 33 | #define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ 34 | #define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ 35 | #define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ 36 | #define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ 37 | #define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ 38 | #define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ 39 | #define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ 40 | #define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ 41 | #define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ 42 | #define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ 43 | #define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ 44 | #define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ 45 | #define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ 46 | #define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ 47 | #define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ 48 | #define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ 49 | #define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ 50 | #define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ 51 | #define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ 52 | #define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ 53 | #define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ 54 | #define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ 55 | #define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ 56 | #define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ 57 | #define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ 58 | #define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ 59 | #define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ 60 | #define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ 61 | #define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ 62 | #define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ 63 | #define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ 64 | #define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ 65 | 66 | #define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ 67 | 68 | /* Option_Bytes_IWatchdog */ 69 | #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ 70 | #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ 71 | 72 | /* Option_Bytes_nRST_STOP */ 73 | #define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ 74 | #define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ 75 | 76 | /* Option_Bytes_nRST_STDBY */ 77 | #define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ 78 | #define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ 79 | 80 | /* FLASH_Interrupts */ 81 | #define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ 82 | #define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ 83 | #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ 84 | #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ 85 | 86 | /* FLASH_Flags */ 87 | #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ 88 | #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ 89 | #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ 90 | #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ 91 | 92 | #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ 93 | #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ 94 | #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ 95 | 96 | /* FLASH_Access_CLK */ 97 | #define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */ 98 | #define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */ 99 | 100 | /*Functions used for all devices*/ 101 | void FLASH_Unlock(void); 102 | void FLASH_Lock(void); 103 | FLASH_Status FLASH_ErasePage(uint32_t Page_Address); 104 | FLASH_Status FLASH_EraseAllPages(void); 105 | FLASH_Status FLASH_EraseOptionBytes(void); 106 | FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); 107 | FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); 108 | FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); 109 | FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); 110 | FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); 111 | FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); 112 | uint32_t FLASH_GetUserOptionByte(void); 113 | uint32_t FLASH_GetWriteProtectionOptionByte(void); 114 | FlagStatus FLASH_GetReadOutProtectionStatus(void); 115 | void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); 116 | FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); 117 | void FLASH_ClearFlag(uint32_t FLASH_FLAG); 118 | FLASH_Status FLASH_GetStatus(void); 119 | FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); 120 | void FLASH_Unlock_Fast(void); 121 | void FLASH_Lock_Fast(void); 122 | void FLASH_ErasePage_Fast(uint32_t Page_Address); 123 | void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); 124 | void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); 125 | void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf); 126 | void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); 127 | void FLASH_Enhance_Mode(FunctionalState NewState); 128 | 129 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 130 | void FLASH_GetMACAddress(uint8_t *Buffer); 131 | #endif 132 | 133 | /* New function used for all devices */ 134 | void FLASH_UnlockBank1(void); 135 | void FLASH_LockBank1(void); 136 | FLASH_Status FLASH_EraseAllBank1Pages(void); 137 | FLASH_Status FLASH_GetBank1Status(void); 138 | FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); 139 | 140 | #ifdef __cplusplus 141 | } 142 | #endif 143 | 144 | #endif 145 | -------------------------------------------------------------------------------- /Core/core_riscv.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : core_riscv.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : RISC-V Core Peripheral Access Layer Source File 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | /* define compiler specific symbols */ 15 | #if defined ( __CC_ARM ) 16 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ 17 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 18 | 19 | #elif defined ( __ICCARM__ ) 20 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ 21 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ 22 | 23 | #elif defined ( __GNUC__ ) 24 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ 25 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ 26 | 27 | #elif defined ( __TASKING__ ) 28 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 29 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 30 | 31 | #endif 32 | 33 | 34 | 35 | /********************************************************************* 36 | * @fn __get_MSTATUS 37 | * 38 | * @brief Return the Machine Status Register 39 | * 40 | * @return mstatus value 41 | */ 42 | uint32_t __get_MSTATUS(void) 43 | { 44 | uint32_t result; 45 | 46 | __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); 47 | return (result); 48 | } 49 | 50 | /********************************************************************* 51 | * @fn __set_MSTATUS 52 | * 53 | * @brief Set the Machine Status Register 54 | * 55 | * @param value - set mstatus value 56 | * 57 | * @return none 58 | */ 59 | void __set_MSTATUS(uint32_t value) 60 | { 61 | __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); 62 | } 63 | 64 | /********************************************************************* 65 | * @fn __get_MISA 66 | * 67 | * @brief Return the Machine ISA Register 68 | * 69 | * @return misa value 70 | */ 71 | uint32_t __get_MISA(void) 72 | { 73 | uint32_t result; 74 | 75 | __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); 76 | return (result); 77 | } 78 | 79 | /********************************************************************* 80 | * @fn __set_MISA 81 | * 82 | * @brief Set the Machine ISA Register 83 | * 84 | * @param value - set misa value 85 | * 86 | * @return none 87 | */ 88 | void __set_MISA(uint32_t value) 89 | { 90 | __ASM volatile ("csrw misa, %0" : : "r" (value) ); 91 | } 92 | 93 | 94 | /********************************************************************* 95 | * @fn __get_MTVEC 96 | * 97 | * @brief Return the Machine Trap-Vector Base-Address Register 98 | * 99 | * @return mtvec value 100 | */ 101 | uint32_t __get_MTVEC(void) 102 | { 103 | uint32_t result; 104 | 105 | __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); 106 | return (result); 107 | } 108 | 109 | /********************************************************************* 110 | * @fn __set_MTVEC 111 | * 112 | * @brief Set the Machine Trap-Vector Base-Address Register 113 | * 114 | * @param value - set mtvec value 115 | * 116 | * @return none 117 | */ 118 | void __set_MTVEC(uint32_t value) 119 | { 120 | __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); 121 | } 122 | 123 | /********************************************************************* 124 | * @fn __get_MSCRATCH 125 | * 126 | * @brief Return the Machine Seratch Register 127 | * 128 | * @return mscratch value 129 | */ 130 | uint32_t __get_MSCRATCH(void) 131 | { 132 | uint32_t result; 133 | 134 | __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); 135 | return (result); 136 | } 137 | 138 | /********************************************************************* 139 | * @fn __set_MSCRATCH 140 | * 141 | * @brief Set the Machine Seratch Register 142 | * 143 | * @param value - set mscratch value 144 | * 145 | * @return none 146 | */ 147 | void __set_MSCRATCH(uint32_t value) 148 | { 149 | __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); 150 | } 151 | 152 | /********************************************************************* 153 | * @fn __get_MEPC 154 | * 155 | * @brief Return the Machine Exception Program Register 156 | * 157 | * @return mepc value 158 | */ 159 | uint32_t __get_MEPC(void) 160 | { 161 | uint32_t result; 162 | 163 | __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); 164 | return (result); 165 | } 166 | 167 | /********************************************************************* 168 | * @fn __set_MEPC 169 | * 170 | * @brief Set the Machine Exception Program Register 171 | * 172 | * @return mepc value 173 | */ 174 | void __set_MEPC(uint32_t value) 175 | { 176 | __ASM volatile ("csrw mepc, %0" : : "r" (value) ); 177 | } 178 | 179 | /********************************************************************* 180 | * @fn __get_MCAUSE 181 | * 182 | * @brief Return the Machine Cause Register 183 | * 184 | * @return mcause value 185 | */ 186 | uint32_t __get_MCAUSE(void) 187 | { 188 | uint32_t result; 189 | 190 | __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); 191 | return (result); 192 | } 193 | 194 | /********************************************************************* 195 | * @fn __set_MEPC 196 | * 197 | * @brief Set the Machine Cause Register 198 | * 199 | * @return mcause value 200 | */ 201 | void __set_MCAUSE(uint32_t value) 202 | { 203 | __ASM volatile ("csrw mcause, %0" : : "r" (value) ); 204 | } 205 | 206 | /********************************************************************* 207 | * @fn __get_MTVAL 208 | * 209 | * @brief Return the Machine Trap Value Register 210 | * 211 | * @return mtval value 212 | */ 213 | uint32_t __get_MTVAL(void) 214 | { 215 | uint32_t result; 216 | 217 | __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); 218 | return (result); 219 | } 220 | 221 | /********************************************************************* 222 | * @fn __set_MTVAL 223 | * 224 | * @brief Set the Machine Trap Value Register 225 | * 226 | * @return mtval value 227 | */ 228 | void __set_MTVAL(uint32_t value) 229 | { 230 | __ASM volatile ("csrw mtval, %0" : : "r" (value) ); 231 | } 232 | 233 | /********************************************************************* 234 | * @fn __get_MVENDORID 235 | * 236 | * @brief Return Vendor ID Register 237 | * 238 | * @return mvendorid value 239 | */ 240 | uint32_t __get_MVENDORID(void) 241 | { 242 | uint32_t result; 243 | 244 | __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); 245 | return (result); 246 | } 247 | 248 | /********************************************************************* 249 | * @fn __get_MARCHID 250 | * 251 | * @brief Return Machine Architecture ID Register 252 | * 253 | * @return marchid value 254 | */ 255 | uint32_t __get_MARCHID(void) 256 | { 257 | uint32_t result; 258 | 259 | __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); 260 | return (result); 261 | } 262 | 263 | /********************************************************************* 264 | * @fn __get_MIMPID 265 | * 266 | * @brief Return Machine Implementation ID Register 267 | * 268 | * @return mimpid value 269 | */ 270 | uint32_t __get_MIMPID(void) 271 | { 272 | uint32_t result; 273 | 274 | __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); 275 | return (result); 276 | } 277 | 278 | /********************************************************************* 279 | * @fn __get_MHARTID 280 | * 281 | * @brief Return Hart ID Register 282 | * 283 | * @return mhartid value 284 | */ 285 | uint32_t __get_MHARTID(void) 286 | { 287 | uint32_t result; 288 | 289 | __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); 290 | return (result); 291 | } 292 | 293 | /********************************************************************* 294 | * @fn __get_SP 295 | * 296 | * @brief Return SP Register 297 | * 298 | * @return SP value 299 | */ 300 | uint32_t __get_SP(void) 301 | { 302 | uint32_t result; 303 | 304 | __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); 305 | return (result); 306 | } 307 | 308 | -------------------------------------------------------------------------------- /User/main.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include "debug.h" 3 | #include "fastFrame.h" 4 | 5 | void initRainbow() 6 | { 7 | int rainbowScale = colorCount / xres; 8 | for(int y = 0; y < yres; y++) 9 | for(int x = 0; x < xres; x++) 10 | { 11 | int r = (x) * rainbowScale; 12 | int g = (y) * rainbowScale; 13 | int b = (7-x) * rainbowScale; 14 | pix(x, y, r, g, b); 15 | } 16 | 17 | } 18 | 19 | void drawSides(int sides = 0b1111) 20 | { 21 | int f = (frame >> 2) & 7; 22 | int f1 = (f - 1) & 7; 23 | int f2 = (f + 1) & 7; 24 | if(sides & 4) 25 | { 26 | pix(f, 0, 0, colorMax, 0); 27 | pix(f1, 0, 0, colorMax, 0); 28 | pix(f2, 0, 0, 0, colorMax); 29 | } 30 | if(sides & 1) 31 | { 32 | pix(0, 7 - f, 0, colorMax, 0); 33 | pix(0, 7 - f1, 0, colorMax, 0); 34 | pix(0, 7 - f2, 0, 0, colorMax); 35 | } 36 | if(sides & 2) 37 | { 38 | pix(7 - f, 7, 0, colorMax, 0); 39 | pix(7 - f1, 7, 0, colorMax, 0); 40 | pix(7 - f2, 7, 0, 0, colorMax); 41 | } 42 | if(sides & 8) 43 | { 44 | pix(7, f, 0, colorMax, 0); 45 | pix(7, f1, 0, colorMax, 0); 46 | pix(7, f2, 0, 0, colorMax); 47 | } 48 | } 49 | 50 | void fillFrame(int r = 0, int g = 0, int b = 0) 51 | { 52 | for(int y = 0; y < yres; y++) 53 | for(int x = 0; x < xres; x++) 54 | pix(x, y, r, g, b); 55 | } 56 | 57 | void initGrey() 58 | { 59 | for(int y = 0; y < yres; y++) 60 | for(int x = 0; x < xres; x++) 61 | pix(x, y, 1 << (colorBits - 1), 1 << (colorBits - 1), 1 << (colorBits - 1)); 62 | } 63 | 64 | 65 | const int buttonPins[] = {2, 3, 4, 5, 6}; 66 | 67 | void initButtons() 68 | { 69 | GPIO_InitTypeDef GPIO_InitStructure = {0}; 70 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 71 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 72 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); 73 | for(int i = 0; i < 5; i++) 74 | { 75 | GPIO_InitStructure.GPIO_Pin = 1 << buttonPins[i]; 76 | GPIO_Init(GPIOD, &GPIO_InitStructure); 77 | } 78 | } 79 | 80 | bool getButton(int b) 81 | { 82 | if(GPIO_ReadInputDataBit(GPIOD, 1 << buttonPins[b])) 83 | return false; 84 | return true; 85 | } 86 | 87 | void initSound() 88 | { 89 | GPIO_InitTypeDef GPIO_InitStructure = {0}; 90 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 91 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 92 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 93 | GPIO_InitStructure.GPIO_Pin = 1 << 15; 94 | GPIO_Init(GPIOA, &GPIO_InitStructure); 95 | } 96 | 97 | // left bottom up right 98 | int IOPins[4][2] = {{0, 1}, {7, 8}, {5, 6}, {9, 10}}; 99 | 100 | void initIO() 101 | { 102 | GPIO_InitTypeDef GPIO_InitStructure = {0}; 103 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 104 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 105 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 106 | for(int i = 0; i < 4; i++) 107 | { 108 | GPIO_InitStructure.GPIO_Pin = 1 << IOPins[i][0]; 109 | GPIO_Init(GPIOA, &GPIO_InitStructure); 110 | GPIO_WriteBit(GPIOA, 1 << IOPins[i][0], Bit_RESET); 111 | } 112 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 113 | for(int i = 0; i < 4; i++) 114 | { 115 | GPIO_InitStructure.GPIO_Pin = 1 << IOPins[i][1]; 116 | GPIO_Init(GPIOA, &GPIO_InitStructure); 117 | } 118 | } 119 | 120 | int IOstate(int ioIndex) 121 | { 122 | if(GPIO_ReadInputDataBit(GPIOA, 1 << IOPins[ioIndex][1])) 123 | return 1; 124 | return 0; 125 | } 126 | /* 127 | const unsigned char smiley[16][16][3] = { 128 | {{95, 129, 183}, {90, 125, 180}, {95, 129, 182}, {89, 125, 179}, {93, 127, 181}, {92, 126, 181}, {88, 122, 178}, {95, 128, 182}, {92, 126, 181}, {88, 123, 178}, {95, 129, 182}, {89, 125, 179}, {95, 129, 182}, {92, 126, 182}, {97, 131, 184}, {97, 130, 183}, }, 129 | {{102, 134, 185}, {93, 127, 181}, {99, 132, 184}, {91, 125, 179}, {73, 103, 149}, {7, 22, 49}, {14, 13, 0}, {18, 15, 0}, {18, 15, 0}, {14, 13, 0}, {8, 23, 49}, {72, 102, 149}, {92, 126, 181}, {100, 133, 184}, {97, 130, 183}, {100, 132, 184}, }, 130 | {{97, 130, 182}, {106, 137, 187}, {92, 126, 181}, {28, 49, 82}, {16, 13, 0}, {124, 100, 0}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {125, 100, 0}, {17, 14, 0}, {26, 47, 82}, {102, 134, 185}, {99, 132, 184}, {107, 139, 188}, }, 131 | {{103, 135, 185}, {100, 132, 183}, {29, 49, 82}, {33, 26, 0}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {193, 157, 9}, {33, 26, 0}, {27, 47, 81}, {110, 141, 188}, {101, 132, 184}, }, 132 | {{111, 141, 188}, {79, 107, 151}, {13, 11, 0}, {76, 61, 0}, {45, 36, 0}, {139, 111, 0}, {193, 157, 9}, {193, 157, 9}, {159, 128, 0}, {77, 62, 4}, {51, 40, 0}, {96, 76, 0}, {193, 157, 9}, {17, 14, 0}, {74, 103, 148}, {111, 141, 188}, }, 133 | {{104, 135, 184}, {11, 25, 47}, {43, 33, 0}, {245, 245, 245}, {11, 9, 10}, {11, 8, 0}, {193, 157, 9}, {193, 157, 9}, {68, 55, 7}, {252, 252, 252}, {37, 36, 36}, {2, 1, 0}, {169, 136, 0}, {125, 100, 0}, {13, 26, 47}, {111, 141, 187}, }, 134 | {{119, 147, 191}, {15, 14, 0}, {89, 76, 27}, {255, 255, 255}, {238, 238, 238}, {73, 69, 56}, {193, 157, 9}, {193, 157, 9}, {79, 74, 58}, {255, 255, 255}, {247, 247, 247}, {138, 137, 138}, {105, 85, 0}, {193, 157, 9}, {15, 14, 0}, {113, 143, 188}, }, 135 | {{111, 141, 187}, {18, 15, 0}, {91, 73, 0}, {74, 60, 0}, {74, 60, 0}, {72, 57, 0}, {193, 157, 9}, {193, 157, 9}, {66, 53, 0}, {68, 54, 0}, {69, 55, 0}, {60, 47, 0}, {159, 128, 0}, {193, 157, 9}, {18, 15, 0}, {117, 147, 191}, }, 136 | {{116, 146, 189}, {18, 15, 0}, {152, 122, 0}, {79, 63, 0}, {79, 63, 0}, {79, 63, 0}, {79, 63, 0}, {79, 63, 0}, {79, 63, 0}, {79, 63, 0}, {79, 63, 0}, {88, 70, 0}, {193, 157, 9}, {193, 157, 9}, {18, 15, 0}, {126, 154, 195}, }, 137 | {{131, 159, 197}, {17, 15, 0}, {180, 145, 2}, {10, 3, 0}, {3, 0, 1}, {3, 0, 1}, {3, 0, 1}, {3, 0, 1}, {3, 0, 1}, {3, 0, 1}, {3, 0, 1}, {3, 0, 1}, {162, 130, 0}, {193, 157, 9}, {15, 14, 0}, {116, 145, 189}, }, 138 | {{71, 107, 172}, {3, 20, 51}, {125, 100, 0}, {43, 31, 0}, {6, 0, 2}, {6, 0, 2}, {6, 0, 2}, {6, 0, 2}, {6, 0, 2}, {6, 0, 2}, {6, 0, 2}, {3, 0, 1}, {162, 130, 0}, {125, 100, 0}, {5, 21, 50}, {88, 123, 179}, }, 139 | {{71, 108, 172}, {47, 81, 141}, {16, 13, 0}, {162, 130, 0}, {6, 0, 1}, {6, 0, 2}, {6, 0, 2}, {59, 0, 25}, {108, 33, 66}, {92, 11, 46}, {9, 0, 4}, {15, 8, 0}, {193, 157, 9}, {16, 13, 0}, {50, 84, 142}, {66, 103, 170}, }, 140 | {{95, 128, 182}, {95, 128, 182}, {21, 42, 82}, {32, 25, 0}, {97, 77, 0}, {6, 0, 2}, {49, 0, 21}, {167, 102, 132}, {167, 102, 132}, {123, 67, 93}, {33, 14, 0}, {153, 122, 0}, {32, 26, 0}, {22, 44, 82}, {83, 117, 176}, {91, 125, 179}, }, 141 | {{95, 128, 180}, {105, 135, 184}, {109, 139, 186}, {30, 49, 82}, {16, 13, 0}, {89, 71, 0}, {49, 37, 0}, {54, 31, 0}, {47, 31, 0}, {66, 52, 0}, {117, 94, 0}, {16, 13, 0}, {32, 51, 82}, {103, 134, 184}, {120, 149, 192}, {111, 142, 187}, }, 142 | {{141, 166, 201}, {114, 144, 187}, {128, 156, 195}, {118, 147, 189}, {90, 115, 153}, {15, 27, 46}, {16, 14, 0}, {18, 15, 0}, {18, 15, 0}, {16, 15, 0}, {15, 27, 46}, {94, 119, 155}, {117, 145, 188}, {138, 164, 199}, {119, 147, 189}, {123, 151, 192}, }, 143 | {{139, 164, 199}, {165, 186, 212}, {135, 160, 197}, {152, 175, 205}, {143, 168, 200}, {138, 164, 198}, {132, 158, 195}, {150, 173, 204}, {130, 156, 194}, {141, 166, 199}, {142, 166, 199}, {147, 171, 203}, {156, 179, 207}, {138, 164, 198}, {160, 182, 210}, {165, 186, 212}, }, 144 | };*/ 145 | 146 | /*void drawSmiley(int x0, int y0) 147 | { 148 | for(int y = 0; y < 8; y++) 149 | for(int x = 0; x < 8; x++) 150 | pix(x, y, smiley[y0 + y][x0 + x][0] << 4, smiley[y0 + y][x0 + x][1] << 4, smiley[y0 + y][x0 + x][2] << 4); 151 | }*/ 152 | 153 | volatile int mode = 02; 154 | int main(void) 155 | { 156 | initRainbow(); 157 | initButtons(); 158 | initSound(); 159 | initIO(); 160 | initFastFrame(); 161 | //drawSmiley(8, 0); 162 | 163 | while(1) 164 | { 165 | static int bitShift = 3; 166 | if(getButton(0)) 167 | { 168 | initRainbow(); 169 | mode = 0; 170 | } 171 | if(getButton(1)) 172 | { 173 | mode = 1; 174 | } 175 | if(getButton(2)) 176 | { 177 | mode = 2; 178 | } 179 | if(getButton(4)) 180 | { 181 | fillFrame(0, 0, 0); 182 | mode = 3; 183 | } 184 | if(colorBits > 8 && getButton(3) && ((frame & 63) == 0)) bitShift = (bitShift + 1) % (colorBits - 8); 185 | // if(getButton(4)) 186 | //GPIOA->OUTDR ^= ((subFrame >> 8) & 1) << 15; 187 | int f = frame; 188 | while (f == frame) 189 | { 190 | }; 191 | static int sides = 0; 192 | switch(mode) 193 | { 194 | case 0: 195 | convertFrameBuffer(frameBuffer[0][0], (colorBits - 8) - bitShift - 1); 196 | break; 197 | case 1: 198 | copyPortFrameBuffer(anim[(frame >> 2) % frameCount][0], 8, bitShift); 199 | break; 200 | case 2: 201 | convertFrameBuffer(frameBuffer[0][0], (colorBits - 8) - bitShift - 1); 202 | fillFrame(0, 0, 0); 203 | drawSides(sides); 204 | break; 205 | case 3: 206 | fillFrame(0, 0, 0); 207 | for(int i = 0; i < 4; i++) 208 | { 209 | if(GPIOA->INDR & (1 << IOPins[i][0])) pix(i, 0, colorMax, colorMax, colorMax); 210 | if(GPIOA->INDR & (1 << IOPins[i][1])) pix(i, 1, colorMax, colorMax, colorMax); 211 | } 212 | convertFrameBuffer(frameBuffer[0][0], (colorBits - 8) - bitShift - 1); 213 | break; 214 | } 215 | sides = 0; 216 | if(IOstate(0)) 217 | sides |= 1; 218 | if(IOstate(1)) 219 | sides |= 2; 220 | if(IOstate(2)) 221 | sides |= 4; 222 | if(IOstate(3)) 223 | sides |= 8; 224 | } 225 | } 226 | 227 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_usart.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_usart.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * USART firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_USART_H 14 | #define __CH32V20x_USART_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* USART Init Structure definition */ 23 | typedef struct 24 | { 25 | uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. 26 | The baud rate is computed using the following formula: 27 | - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) 28 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ 29 | 30 | uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. 31 | This parameter can be a value of @ref USART_Word_Length */ 32 | 33 | uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. 34 | This parameter can be a value of @ref USART_Stop_Bits */ 35 | 36 | uint16_t USART_Parity; /* Specifies the parity mode. 37 | This parameter can be a value of @ref USART_Parity 38 | @note When parity is enabled, the computed parity is inserted 39 | at the MSB position of the transmitted data (9th bit when 40 | the word length is set to 9 data bits; 8th bit when the 41 | word length is set to 8 data bits). */ 42 | 43 | uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. 44 | This parameter can be a value of @ref USART_Mode */ 45 | 46 | uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled 47 | or disabled. 48 | This parameter can be a value of @ref USART_Hardware_Flow_Control */ 49 | } USART_InitTypeDef; 50 | 51 | /* USART Clock Init Structure definition */ 52 | typedef struct 53 | { 54 | uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. 55 | This parameter can be a value of @ref USART_Clock */ 56 | 57 | uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. 58 | This parameter can be a value of @ref USART_Clock_Polarity */ 59 | 60 | uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. 61 | This parameter can be a value of @ref USART_Clock_Phase */ 62 | 63 | uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted 64 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. 65 | This parameter can be a value of @ref USART_Last_Bit */ 66 | } USART_ClockInitTypeDef; 67 | 68 | /* USART_Word_Length */ 69 | #define USART_WordLength_8b ((uint16_t)0x0000) 70 | #define USART_WordLength_9b ((uint16_t)0x1000) 71 | 72 | /* USART_Stop_Bits */ 73 | #define USART_StopBits_1 ((uint16_t)0x0000) 74 | #define USART_StopBits_0_5 ((uint16_t)0x1000) 75 | #define USART_StopBits_2 ((uint16_t)0x2000) 76 | #define USART_StopBits_1_5 ((uint16_t)0x3000) 77 | 78 | /* USART_Parity */ 79 | #define USART_Parity_No ((uint16_t)0x0000) 80 | #define USART_Parity_Even ((uint16_t)0x0400) 81 | #define USART_Parity_Odd ((uint16_t)0x0600) 82 | 83 | /* USART_Mode */ 84 | #define USART_Mode_Rx ((uint16_t)0x0004) 85 | #define USART_Mode_Tx ((uint16_t)0x0008) 86 | 87 | /* USART_Hardware_Flow_Control */ 88 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000) 89 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) 90 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) 91 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) 92 | 93 | /* USART_Clock */ 94 | #define USART_Clock_Disable ((uint16_t)0x0000) 95 | #define USART_Clock_Enable ((uint16_t)0x0800) 96 | 97 | /* USART_Clock_Polarity */ 98 | #define USART_CPOL_Low ((uint16_t)0x0000) 99 | #define USART_CPOL_High ((uint16_t)0x0400) 100 | 101 | /* USART_Clock_Phase */ 102 | #define USART_CPHA_1Edge ((uint16_t)0x0000) 103 | #define USART_CPHA_2Edge ((uint16_t)0x0200) 104 | 105 | /* USART_Last_Bit */ 106 | #define USART_LastBit_Disable ((uint16_t)0x0000) 107 | #define USART_LastBit_Enable ((uint16_t)0x0100) 108 | 109 | /* USART_Interrupt_definition */ 110 | #define USART_IT_PE ((uint16_t)0x0028) 111 | #define USART_IT_TXE ((uint16_t)0x0727) 112 | #define USART_IT_TC ((uint16_t)0x0626) 113 | #define USART_IT_RXNE ((uint16_t)0x0525) 114 | #define USART_IT_ORE_RX ((uint16_t)0x0325) 115 | #define USART_IT_IDLE ((uint16_t)0x0424) 116 | #define USART_IT_LBD ((uint16_t)0x0846) 117 | #define USART_IT_CTS ((uint16_t)0x096A) 118 | #define USART_IT_ERR ((uint16_t)0x0060) 119 | #define USART_IT_ORE_ER ((uint16_t)0x0360) 120 | #define USART_IT_NE ((uint16_t)0x0260) 121 | #define USART_IT_FE ((uint16_t)0x0160) 122 | 123 | #define USART_IT_ORE USART_IT_ORE_ER 124 | 125 | /* USART_DMA_Requests */ 126 | #define USART_DMAReq_Tx ((uint16_t)0x0080) 127 | #define USART_DMAReq_Rx ((uint16_t)0x0040) 128 | 129 | /* USART_WakeUp_methods */ 130 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000) 131 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800) 132 | 133 | /* USART_LIN_Break_Detection_Length */ 134 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) 135 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) 136 | 137 | /* USART_IrDA_Low_Power */ 138 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004) 139 | #define USART_IrDAMode_Normal ((uint16_t)0x0000) 140 | 141 | /* USART_Flags */ 142 | #define USART_FLAG_CTS ((uint16_t)0x0200) 143 | #define USART_FLAG_LBD ((uint16_t)0x0100) 144 | #define USART_FLAG_TXE ((uint16_t)0x0080) 145 | #define USART_FLAG_TC ((uint16_t)0x0040) 146 | #define USART_FLAG_RXNE ((uint16_t)0x0020) 147 | #define USART_FLAG_IDLE ((uint16_t)0x0010) 148 | #define USART_FLAG_ORE ((uint16_t)0x0008) 149 | #define USART_FLAG_NE ((uint16_t)0x0004) 150 | #define USART_FLAG_FE ((uint16_t)0x0002) 151 | #define USART_FLAG_PE ((uint16_t)0x0001) 152 | 153 | void USART_DeInit(USART_TypeDef *USARTx); 154 | void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); 155 | void USART_StructInit(USART_InitTypeDef *USART_InitStruct); 156 | void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); 157 | void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); 158 | void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); 159 | void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); 160 | void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); 161 | void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); 162 | void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); 163 | void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); 164 | void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); 165 | void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); 166 | void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); 167 | uint16_t USART_ReceiveData(USART_TypeDef *USARTx); 168 | void USART_SendBreak(USART_TypeDef *USARTx); 169 | void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); 170 | void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); 171 | void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); 172 | void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); 173 | void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); 174 | void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); 175 | void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); 176 | void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); 177 | void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); 178 | FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); 179 | void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); 180 | ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); 181 | void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); 182 | 183 | #ifdef __cplusplus 184 | } 185 | #endif 186 | 187 | #endif 188 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_dma.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_dma.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * DMA firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_DMA_H 14 | #define __CH32V20x_DMA_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* DMA Init structure definition */ 23 | typedef struct 24 | { 25 | uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ 26 | 27 | uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ 28 | 29 | uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. 30 | This parameter can be a value of @ref DMA_data_transfer_direction */ 31 | 32 | uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. 33 | The data unit is equal to the configuration set in DMA_PeripheralDataSize 34 | or DMA_MemoryDataSize members depending in the transfer direction. */ 35 | 36 | uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. 37 | This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 38 | 39 | uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. 40 | This parameter can be a value of @ref DMA_memory_incremented_mode */ 41 | 42 | uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. 43 | This parameter can be a value of @ref DMA_peripheral_data_size */ 44 | 45 | uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. 46 | This parameter can be a value of @ref DMA_memory_data_size */ 47 | 48 | uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. 49 | This parameter can be a value of @ref DMA_circular_normal_mode. 50 | @note: The circular buffer mode cannot be used if the memory-to-memory 51 | data transfer is configured on the selected Channel */ 52 | 53 | uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. 54 | This parameter can be a value of @ref DMA_priority_level */ 55 | 56 | uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. 57 | This parameter can be a value of @ref DMA_memory_to_memory */ 58 | } DMA_InitTypeDef; 59 | 60 | /* DMA_data_transfer_direction */ 61 | #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) 62 | #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) 63 | 64 | /* DMA_peripheral_incremented_mode */ 65 | #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) 66 | #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 67 | 68 | /* DMA_memory_incremented_mode */ 69 | #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) 70 | #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 71 | 72 | /* DMA_peripheral_data_size */ 73 | #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 74 | #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) 75 | #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) 76 | 77 | /* DMA_memory_data_size */ 78 | #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 79 | #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) 80 | #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) 81 | 82 | /* DMA_circular_normal_mode */ 83 | #define DMA_Mode_Circular ((uint32_t)0x00000020) 84 | #define DMA_Mode_Normal ((uint32_t)0x00000000) 85 | 86 | /* DMA_priority_level */ 87 | #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) 88 | #define DMA_Priority_High ((uint32_t)0x00002000) 89 | #define DMA_Priority_Medium ((uint32_t)0x00001000) 90 | #define DMA_Priority_Low ((uint32_t)0x00000000) 91 | 92 | /* DMA_memory_to_memory */ 93 | #define DMA_M2M_Enable ((uint32_t)0x00004000) 94 | #define DMA_M2M_Disable ((uint32_t)0x00000000) 95 | 96 | /* DMA_interrupts_definition */ 97 | #define DMA_IT_TC ((uint32_t)0x00000002) 98 | #define DMA_IT_HT ((uint32_t)0x00000004) 99 | #define DMA_IT_TE ((uint32_t)0x00000008) 100 | 101 | #define DMA1_IT_GL1 ((uint32_t)0x00000001) 102 | #define DMA1_IT_TC1 ((uint32_t)0x00000002) 103 | #define DMA1_IT_HT1 ((uint32_t)0x00000004) 104 | #define DMA1_IT_TE1 ((uint32_t)0x00000008) 105 | #define DMA1_IT_GL2 ((uint32_t)0x00000010) 106 | #define DMA1_IT_TC2 ((uint32_t)0x00000020) 107 | #define DMA1_IT_HT2 ((uint32_t)0x00000040) 108 | #define DMA1_IT_TE2 ((uint32_t)0x00000080) 109 | #define DMA1_IT_GL3 ((uint32_t)0x00000100) 110 | #define DMA1_IT_TC3 ((uint32_t)0x00000200) 111 | #define DMA1_IT_HT3 ((uint32_t)0x00000400) 112 | #define DMA1_IT_TE3 ((uint32_t)0x00000800) 113 | #define DMA1_IT_GL4 ((uint32_t)0x00001000) 114 | #define DMA1_IT_TC4 ((uint32_t)0x00002000) 115 | #define DMA1_IT_HT4 ((uint32_t)0x00004000) 116 | #define DMA1_IT_TE4 ((uint32_t)0x00008000) 117 | #define DMA1_IT_GL5 ((uint32_t)0x00010000) 118 | #define DMA1_IT_TC5 ((uint32_t)0x00020000) 119 | #define DMA1_IT_HT5 ((uint32_t)0x00040000) 120 | #define DMA1_IT_TE5 ((uint32_t)0x00080000) 121 | #define DMA1_IT_GL6 ((uint32_t)0x00100000) 122 | #define DMA1_IT_TC6 ((uint32_t)0x00200000) 123 | #define DMA1_IT_HT6 ((uint32_t)0x00400000) 124 | #define DMA1_IT_TE6 ((uint32_t)0x00800000) 125 | #define DMA1_IT_GL7 ((uint32_t)0x01000000) 126 | #define DMA1_IT_TC7 ((uint32_t)0x02000000) 127 | #define DMA1_IT_HT7 ((uint32_t)0x04000000) 128 | #define DMA1_IT_TE7 ((uint32_t)0x08000000) 129 | #define DMA1_IT_GL8 ((uint32_t)0x10000000) 130 | #define DMA1_IT_TC8 ((uint32_t)0x20000000) 131 | #define DMA1_IT_HT8 ((uint32_t)0x40000000) 132 | #define DMA1_IT_TE8 ((uint32_t)0x80000000) 133 | 134 | /* DMA_flags_definition */ 135 | #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) 136 | #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) 137 | #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) 138 | #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) 139 | #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) 140 | #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) 141 | #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) 142 | #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) 143 | #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) 144 | #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) 145 | #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) 146 | #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) 147 | #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) 148 | #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) 149 | #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) 150 | #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) 151 | #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) 152 | #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) 153 | #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) 154 | #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) 155 | #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) 156 | #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) 157 | #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) 158 | #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) 159 | #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) 160 | #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) 161 | #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) 162 | #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) 163 | #define DMA1_FLAG_GL8 ((uint32_t)0x10000000) 164 | #define DMA1_FLAG_TC8 ((uint32_t)0x20000000) 165 | #define DMA1_FLAG_HT8 ((uint32_t)0x40000000) 166 | #define DMA1_FLAG_TE8 ((uint32_t)0x80000000) 167 | 168 | void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); 169 | void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); 170 | void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); 171 | void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); 172 | void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); 173 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); 174 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); 175 | FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); 176 | void DMA_ClearFlag(uint32_t DMAy_FLAG); 177 | ITStatus DMA_GetITStatus(uint32_t DMAy_IT); 178 | void DMA_ClearITPendingBit(uint32_t DMAy_IT); 179 | 180 | #ifdef __cplusplus 181 | } 182 | #endif 183 | 184 | #endif 185 | -------------------------------------------------------------------------------- /Startup/startup_ch32v20x_D6.S: -------------------------------------------------------------------------------- 1 | ;/********************************** (C) COPYRIGHT ******************************* 2 | ;* File Name : startup_ch32v20x_D6.s 3 | ;* Author : WCH 4 | ;* Version : V1.0.0 5 | ;* Date : 2021/06/06 6 | ;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8 7 | ;* vector table for eclipse toolchain. 8 | ;********************************************************************************* 9 | ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | ;* Attention: This software (modified or not) and binary are used for 11 | ;* microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | 14 | .section .init,"ax",@progbits 15 | .global _start 16 | .align 1 17 | _start: 18 | j handle_reset 19 | .word 0x00000013 20 | .word 0x00000013 21 | .word 0x00000013 22 | .word 0x00000013 23 | .word 0x00000013 24 | .word 0x00000013 25 | .word 0x00000013 26 | .word 0x00000013 27 | .word 0x00000013 28 | .word 0x00000013 29 | .word 0x00000013 30 | .word 0x00000013 31 | .word 0x00100073 32 | .section .vector,"ax",@progbits 33 | .align 1 34 | _vector_base: 35 | .option norvc; 36 | .word _start 37 | .word 0 38 | .word NMI_Handler /* NMI */ 39 | .word HardFault_Handler /* Hard Fault */ 40 | .word 0 41 | .word Ecall_M_Mode_Handler /* Ecall M Mode */ 42 | .word 0 43 | .word 0 44 | .word Ecall_U_Mode_Handler /* Ecall U Mode */ 45 | .word Break_Point_Handler /* Break Point */ 46 | .word 0 47 | .word 0 48 | .word SysTick_Handler /* SysTick */ 49 | .word 0 50 | .word SW_Handler /* SW */ 51 | .word 0 52 | /* External Interrupts */ 53 | .word WWDG_IRQHandler /* Window Watchdog */ 54 | .word PVD_IRQHandler /* PVD through EXTI Line detect */ 55 | .word TAMPER_IRQHandler /* TAMPER */ 56 | .word RTC_IRQHandler /* RTC */ 57 | .word FLASH_IRQHandler /* Flash */ 58 | .word RCC_IRQHandler /* RCC */ 59 | .word EXTI0_IRQHandler /* EXTI Line 0 */ 60 | .word EXTI1_IRQHandler /* EXTI Line 1 */ 61 | .word EXTI2_IRQHandler /* EXTI Line 2 */ 62 | .word EXTI3_IRQHandler /* EXTI Line 3 */ 63 | .word EXTI4_IRQHandler /* EXTI Line 4 */ 64 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 65 | .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 66 | .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 67 | .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 68 | .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 69 | .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 70 | .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 71 | .word ADC1_2_IRQHandler /* ADC1_2 */ 72 | .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 73 | .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 74 | .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 75 | .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 76 | .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 77 | .word TIM1_BRK_IRQHandler /* TIM1 Break */ 78 | .word TIM1_UP_IRQHandler /* TIM1 Update */ 79 | .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 80 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 81 | .word TIM2_IRQHandler /* TIM2 */ 82 | .word TIM3_IRQHandler /* TIM3 */ 83 | .word TIM4_IRQHandler /* TIM4 */ 84 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 85 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 86 | .word I2C2_EV_IRQHandler /* I2C2 Event */ 87 | .word I2C2_ER_IRQHandler /* I2C2 Error */ 88 | .word SPI1_IRQHandler /* SPI1 */ 89 | .word SPI2_IRQHandler /* SPI2 */ 90 | .word USART1_IRQHandler /* USART1 */ 91 | .word USART2_IRQHandler /* USART2 */ 92 | .word USART3_IRQHandler /* USART3 */ 93 | .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 94 | .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 95 | .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ 96 | .word USBHD_IRQHandler /* USBHD Break */ 97 | .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ 98 | .word UART4_IRQHandler /* UART4 */ 99 | .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 100 | 101 | .option rvc; 102 | 103 | .section .text.vector_handler, "ax", @progbits 104 | .weak NMI_Handler /* NMI */ 105 | .weak HardFault_Handler /* Hard Fault */ 106 | .weak Ecall_M_Mode_Handler /* Ecall M Mode */ 107 | .weak Ecall_U_Mode_Handler /* Ecall U Mode */ 108 | .weak Break_Point_Handler /* Break Point */ 109 | .weak SysTick_Handler /* SysTick */ 110 | .weak SW_Handler /* SW */ 111 | .weak WWDG_IRQHandler /* Window Watchdog */ 112 | .weak PVD_IRQHandler /* PVD through EXTI Line detect */ 113 | .weak TAMPER_IRQHandler /* TAMPER */ 114 | .weak RTC_IRQHandler /* RTC */ 115 | .weak FLASH_IRQHandler /* Flash */ 116 | .weak RCC_IRQHandler /* RCC */ 117 | .weak EXTI0_IRQHandler /* EXTI Line 0 */ 118 | .weak EXTI1_IRQHandler /* EXTI Line 1 */ 119 | .weak EXTI2_IRQHandler /* EXTI Line 2 */ 120 | .weak EXTI3_IRQHandler /* EXTI Line 3 */ 121 | .weak EXTI4_IRQHandler /* EXTI Line 4 */ 122 | .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 123 | .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 124 | .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 125 | .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 126 | .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 127 | .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 128 | .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 129 | .weak ADC1_2_IRQHandler /* ADC1_2 */ 130 | .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 131 | .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 132 | .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ 133 | .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ 134 | .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 135 | .weak TIM1_BRK_IRQHandler /* TIM1 Break */ 136 | .weak TIM1_UP_IRQHandler /* TIM1 Update */ 137 | .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 138 | .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 139 | .weak TIM2_IRQHandler /* TIM2 */ 140 | .weak TIM3_IRQHandler /* TIM3 */ 141 | .weak TIM4_IRQHandler /* TIM4 */ 142 | .weak I2C1_EV_IRQHandler /* I2C1 Event */ 143 | .weak I2C1_ER_IRQHandler /* I2C1 Error */ 144 | .weak I2C2_EV_IRQHandler /* I2C2 Event */ 145 | .weak I2C2_ER_IRQHandler /* I2C2 Error */ 146 | .weak SPI1_IRQHandler /* SPI1 */ 147 | .weak SPI2_IRQHandler /* SPI2 */ 148 | .weak USART1_IRQHandler /* USART1 */ 149 | .weak USART2_IRQHandler /* USART2 */ 150 | .weak USART3_IRQHandler /* USART3 */ 151 | .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 152 | .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 153 | .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ 154 | .weak USBHD_IRQHandler /* USBHD */ 155 | .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ 156 | .weak UART4_IRQHandler /* UART4 */ 157 | .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 158 | 159 | NMI_Handler: 1: j 1b 160 | HardFault_Handler: 1: j 1b 161 | Ecall_M_Mode_Handler: 1: j 1b 162 | Ecall_U_Mode_Handler: 1: j 1b 163 | Break_Point_Handler: 1: j 1b 164 | SysTick_Handler: 1: j 1b 165 | SW_Handler: 1: j 1b 166 | WWDG_IRQHandler: 1: j 1b 167 | PVD_IRQHandler: 1: j 1b 168 | TAMPER_IRQHandler: 1: j 1b 169 | RTC_IRQHandler: 1: j 1b 170 | FLASH_IRQHandler: 1: j 1b 171 | RCC_IRQHandler: 1: j 1b 172 | EXTI0_IRQHandler: 1: j 1b 173 | EXTI1_IRQHandler: 1: j 1b 174 | EXTI2_IRQHandler: 1: j 1b 175 | EXTI3_IRQHandler: 1: j 1b 176 | EXTI4_IRQHandler: 1: j 1b 177 | DMA1_Channel1_IRQHandler: 1: j 1b 178 | DMA1_Channel2_IRQHandler: 1: j 1b 179 | DMA1_Channel3_IRQHandler: 1: j 1b 180 | DMA1_Channel4_IRQHandler: 1: j 1b 181 | DMA1_Channel5_IRQHandler: 1: j 1b 182 | DMA1_Channel6_IRQHandler: 1: j 1b 183 | DMA1_Channel7_IRQHandler: 1: j 1b 184 | ADC1_2_IRQHandler: 1: j 1b 185 | USB_HP_CAN1_TX_IRQHandler: 1: j 1b 186 | USB_LP_CAN1_RX0_IRQHandler: 1: j 1b 187 | CAN1_RX1_IRQHandler: 1: j 1b 188 | CAN1_SCE_IRQHandler: 1: j 1b 189 | EXTI9_5_IRQHandler: 1: j 1b 190 | TIM1_BRK_IRQHandler: 1: j 1b 191 | TIM1_UP_IRQHandler: 1: j 1b 192 | TIM1_TRG_COM_IRQHandler: 1: j 1b 193 | TIM1_CC_IRQHandler: 1: j 1b 194 | TIM2_IRQHandler: 1: j 1b 195 | TIM3_IRQHandler: 1: j 1b 196 | TIM4_IRQHandler: 1: j 1b 197 | I2C1_EV_IRQHandler: 1: j 1b 198 | I2C1_ER_IRQHandler: 1: j 1b 199 | I2C2_EV_IRQHandler: 1: j 1b 200 | I2C2_ER_IRQHandler: 1: j 1b 201 | SPI1_IRQHandler: 1: j 1b 202 | SPI2_IRQHandler: 1: j 1b 203 | USART1_IRQHandler: 1: j 1b 204 | USART2_IRQHandler: 1: j 1b 205 | USART3_IRQHandler: 1: j 1b 206 | EXTI15_10_IRQHandler: 1: j 1b 207 | RTCAlarm_IRQHandler: 1: j 1b 208 | USBWakeUp_IRQHandler: 1: j 1b 209 | USBHD_IRQHandler: 1: j 1b 210 | USBHDWakeUp_IRQHandler: 1: j 1b 211 | UART4_IRQHandler: 1: j 1b 212 | DMA1_Channel8_IRQHandler: 1: j 1b 213 | 214 | .section .text.handle_reset,"ax",@progbits 215 | .weak handle_reset 216 | .align 1 217 | handle_reset: 218 | .option push 219 | .option norelax 220 | la gp, __global_pointer$ 221 | .option pop 222 | 1: 223 | la sp, _eusrstack 224 | 2: 225 | /* Load data section from flash to RAM */ 226 | la a0, _data_lma 227 | la a1, _data_vma 228 | la a2, _edata 229 | bgeu a1, a2, 2f 230 | 1: 231 | lw t0, (a0) 232 | sw t0, (a1) 233 | addi a0, a0, 4 234 | addi a1, a1, 4 235 | bltu a1, a2, 1b 236 | 2: 237 | /* Clear bss section */ 238 | la a0, _sbss 239 | la a1, _ebss 240 | bgeu a0, a1, 2f 241 | 1: 242 | sw zero, (a0) 243 | addi a0, a0, 4 244 | bltu a0, a1, 1b 245 | 2: 246 | li t0, 0x1f 247 | csrw 0xbc0, t0 248 | 249 | /* Enable nested and hardware stack */ 250 | li t0, 0x3 251 | csrw 0x804, t0 252 | 253 | /* Enable interrupt */ 254 | li t0, 0x88 255 | csrs mstatus, t0 256 | 257 | la t0, _vector_base 258 | ori t0, t0, 3 259 | csrw mtvec, t0 260 | 261 | jal SystemInit 262 | la t0, main 263 | csrw mepc, t0 264 | mret 265 | 266 | 267 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_spi.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_spi.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * SPI firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_SPI_H 14 | #define __CH32V20x_SPI_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* SPI Init structure definition */ 23 | typedef struct 24 | { 25 | uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. 26 | This parameter can be a value of @ref SPI_data_direction */ 27 | 28 | uint16_t SPI_Mode; /* Specifies the SPI operating mode. 29 | This parameter can be a value of @ref SPI_mode */ 30 | 31 | uint16_t SPI_DataSize; /* Specifies the SPI data size. 32 | This parameter can be a value of @ref SPI_data_size */ 33 | 34 | uint16_t SPI_CPOL; /* Specifies the serial clock steady state. 35 | This parameter can be a value of @ref SPI_Clock_Polarity */ 36 | 37 | uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. 38 | This parameter can be a value of @ref SPI_Clock_Phase */ 39 | 40 | uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by 41 | hardware (NSS pin) or by software using the SSI bit. 42 | This parameter can be a value of @ref SPI_Slave_Select_management */ 43 | 44 | uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be 45 | used to configure the transmit and receive SCK clock. 46 | This parameter can be a value of @ref SPI_BaudRate_Prescaler. 47 | @note The communication clock is derived from the master 48 | clock. The slave clock does not need to be set. */ 49 | 50 | uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. 51 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 52 | 53 | uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ 54 | } SPI_InitTypeDef; 55 | 56 | /* I2S Init structure definition */ 57 | typedef struct 58 | { 59 | uint16_t I2S_Mode; /* Specifies the I2S operating mode. 60 | This parameter can be a value of @ref I2S_Mode */ 61 | 62 | uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. 63 | This parameter can be a value of @ref I2S_Standard */ 64 | 65 | uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. 66 | This parameter can be a value of @ref I2S_Data_Format */ 67 | 68 | uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. 69 | This parameter can be a value of @ref I2S_MCLK_Output */ 70 | 71 | uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. 72 | This parameter can be a value of @ref I2S_Audio_Frequency */ 73 | 74 | uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. 75 | This parameter can be a value of @ref I2S_Clock_Polarity */ 76 | } I2S_InitTypeDef; 77 | 78 | /* SPI_data_direction */ 79 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 80 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 81 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 82 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 83 | 84 | /* SPI_mode */ 85 | #define SPI_Mode_Master ((uint16_t)0x0104) 86 | #define SPI_Mode_Slave ((uint16_t)0x0000) 87 | 88 | /* SPI_data_size */ 89 | #define SPI_DataSize_16b ((uint16_t)0x0800) 90 | #define SPI_DataSize_8b ((uint16_t)0x0000) 91 | 92 | /* SPI_Clock_Polarity */ 93 | #define SPI_CPOL_Low ((uint16_t)0x0000) 94 | #define SPI_CPOL_High ((uint16_t)0x0002) 95 | 96 | /* SPI_Clock_Phase */ 97 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) 98 | #define SPI_CPHA_2Edge ((uint16_t)0x0001) 99 | 100 | /* SPI_Slave_Select_management */ 101 | #define SPI_NSS_Soft ((uint16_t)0x0200) 102 | #define SPI_NSS_Hard ((uint16_t)0x0000) 103 | 104 | /* SPI_BaudRate_Prescaler */ 105 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 106 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 107 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 108 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 109 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 110 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 111 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 112 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 113 | 114 | /* SPI_MSB_LSB_transmission */ 115 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) 116 | #define SPI_FirstBit_LSB ((uint16_t)0x0080) 117 | 118 | /* I2S_Mode */ 119 | #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 120 | #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 121 | #define I2S_Mode_MasterTx ((uint16_t)0x0200) 122 | #define I2S_Mode_MasterRx ((uint16_t)0x0300) 123 | 124 | /* I2S_Standard */ 125 | #define I2S_Standard_Phillips ((uint16_t)0x0000) 126 | #define I2S_Standard_MSB ((uint16_t)0x0010) 127 | #define I2S_Standard_LSB ((uint16_t)0x0020) 128 | #define I2S_Standard_PCMShort ((uint16_t)0x0030) 129 | #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 130 | 131 | /* I2S_Data_Format */ 132 | #define I2S_DataFormat_16b ((uint16_t)0x0000) 133 | #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 134 | #define I2S_DataFormat_24b ((uint16_t)0x0003) 135 | #define I2S_DataFormat_32b ((uint16_t)0x0005) 136 | 137 | /* I2S_MCLK_Output */ 138 | #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 139 | #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 140 | 141 | /* I2S_Audio_Frequency */ 142 | #define I2S_AudioFreq_192k ((uint32_t)192000) 143 | #define I2S_AudioFreq_96k ((uint32_t)96000) 144 | #define I2S_AudioFreq_48k ((uint32_t)48000) 145 | #define I2S_AudioFreq_44k ((uint32_t)44100) 146 | #define I2S_AudioFreq_32k ((uint32_t)32000) 147 | #define I2S_AudioFreq_22k ((uint32_t)22050) 148 | #define I2S_AudioFreq_16k ((uint32_t)16000) 149 | #define I2S_AudioFreq_11k ((uint32_t)11025) 150 | #define I2S_AudioFreq_8k ((uint32_t)8000) 151 | #define I2S_AudioFreq_Default ((uint32_t)2) 152 | 153 | /* I2S_Clock_Polarity */ 154 | #define I2S_CPOL_Low ((uint16_t)0x0000) 155 | #define I2S_CPOL_High ((uint16_t)0x0008) 156 | 157 | /* SPI_I2S_DMA_transfer_requests */ 158 | #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 159 | #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 160 | 161 | /* SPI_NSS_internal_software_management */ 162 | #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 163 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 164 | 165 | /* SPI_CRC_Transmit_Receive */ 166 | #define SPI_CRC_Tx ((uint8_t)0x00) 167 | #define SPI_CRC_Rx ((uint8_t)0x01) 168 | 169 | /* SPI_direction_transmit_receive */ 170 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) 171 | #define SPI_Direction_Tx ((uint16_t)0x4000) 172 | 173 | /* SPI_I2S_interrupts_definition */ 174 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) 175 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 176 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) 177 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) 178 | #define SPI_IT_MODF ((uint8_t)0x55) 179 | #define SPI_IT_CRCERR ((uint8_t)0x54) 180 | #define I2S_IT_UDR ((uint8_t)0x53) 181 | 182 | /* SPI_I2S_flags_definition */ 183 | #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 184 | #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 185 | #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 186 | #define I2S_FLAG_UDR ((uint16_t)0x0008) 187 | #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 188 | #define SPI_FLAG_MODF ((uint16_t)0x0020) 189 | #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 190 | #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 191 | 192 | void SPI_I2S_DeInit(SPI_TypeDef *SPIx); 193 | void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); 194 | void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct); 195 | void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); 196 | void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct); 197 | void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); 198 | void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); 199 | void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 200 | void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 201 | void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); 202 | uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); 203 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); 204 | void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); 205 | void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); 206 | void SPI_TransmitCRC(SPI_TypeDef *SPIx); 207 | void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); 208 | uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); 209 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); 210 | void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); 211 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); 212 | void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); 213 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); 214 | void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); 215 | 216 | #ifdef __cplusplus 217 | } 218 | #endif 219 | 220 | #endif 221 | -------------------------------------------------------------------------------- /Startup/startup_ch32v20x_D8.S: -------------------------------------------------------------------------------- 1 | ;/********************************** (C) COPYRIGHT ******************************* 2 | ;* File Name : startup_ch32v20x_D8.s 3 | ;* Author : WCH 4 | ;* Version : V1.0.0 5 | ;* Date : 2021/06/06 6 | ;* Description : CH32V203RB 7 | ;* vector table for eclipse toolchain. 8 | ;********************************************************************************* 9 | ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | ;* Attention: This software (modified or not) and binary are used for 11 | ;* microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | 14 | .section .init,"ax",@progbits 15 | .global _start 16 | .align 1 17 | _start: 18 | j handle_reset 19 | .word 0x00000013 20 | .word 0x00000013 21 | .word 0x00000013 22 | .word 0x00000013 23 | .word 0x00000013 24 | .word 0x00000013 25 | .word 0x00000013 26 | .word 0x00000013 27 | .word 0x00000013 28 | .word 0x00000013 29 | .word 0x00000013 30 | .word 0x00000013 31 | .word 0x00100073 32 | .section .vector,"ax",@progbits 33 | .align 1 34 | _vector_base: 35 | .option norvc; 36 | .word _start 37 | .word 0 38 | .word NMI_Handler /* NMI */ 39 | .word HardFault_Handler /* Hard Fault */ 40 | .word 0 41 | .word Ecall_M_Mode_Handler /* Ecall M Mode */ 42 | .word 0 43 | .word 0 44 | .word Ecall_U_Mode_Handler /* Ecall U Mode */ 45 | .word Break_Point_Handler /* Break Point */ 46 | .word 0 47 | .word 0 48 | .word SysTick_Handler /* SysTick */ 49 | .word 0 50 | .word SW_Handler /* SW */ 51 | .word 0 52 | /* External Interrupts */ 53 | .word WWDG_IRQHandler /* Window Watchdog */ 54 | .word PVD_IRQHandler /* PVD through EXTI Line detect */ 55 | .word TAMPER_IRQHandler /* TAMPER */ 56 | .word RTC_IRQHandler /* RTC */ 57 | .word FLASH_IRQHandler /* Flash */ 58 | .word RCC_IRQHandler /* RCC */ 59 | .word EXTI0_IRQHandler /* EXTI Line 0 */ 60 | .word EXTI1_IRQHandler /* EXTI Line 1 */ 61 | .word EXTI2_IRQHandler /* EXTI Line 2 */ 62 | .word EXTI3_IRQHandler /* EXTI Line 3 */ 63 | .word EXTI4_IRQHandler /* EXTI Line 4 */ 64 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 65 | .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 66 | .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 67 | .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 68 | .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 69 | .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 70 | .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 71 | .word ADC1_2_IRQHandler /* ADC1_2 */ 72 | .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 73 | .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 74 | .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 75 | .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 76 | .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 77 | .word TIM1_BRK_IRQHandler /* TIM1 Break */ 78 | .word TIM1_UP_IRQHandler /* TIM1 Update */ 79 | .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 80 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 81 | .word TIM2_IRQHandler /* TIM2 */ 82 | .word TIM3_IRQHandler /* TIM3 */ 83 | .word TIM4_IRQHandler /* TIM4 */ 84 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 85 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 86 | .word I2C2_EV_IRQHandler /* I2C2 Event */ 87 | .word I2C2_ER_IRQHandler /* I2C2 Error */ 88 | .word SPI1_IRQHandler /* SPI1 */ 89 | .word SPI2_IRQHandler /* SPI2 */ 90 | .word USART1_IRQHandler /* USART1 */ 91 | .word USART2_IRQHandler /* USART2 */ 92 | .word USART3_IRQHandler /* USART3 */ 93 | .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 94 | .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 95 | .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ 96 | .word USBHD_IRQHandler /* USBHD Break */ 97 | .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ 98 | .word ETH_IRQHandler /* ETH global */ 99 | .word ETHWakeUp_IRQHandler /* ETH Wake up */ 100 | .word 0 /* BLE BB */ 101 | .word 0 /* BLE LLE */ 102 | .word TIM5_IRQHandler /* TIM5 */ 103 | .word UART4_IRQHandler /* UART4 */ 104 | .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 105 | .word OSC32KCal_IRQHandler /* OSC32KCal */ 106 | .word OSCWakeUp_IRQHandler /* OSC Wake Up */ 107 | 108 | .option rvc; 109 | 110 | .section .text.vector_handler, "ax", @progbits 111 | .weak NMI_Handler /* NMI */ 112 | .weak HardFault_Handler /* Hard Fault */ 113 | .weak Ecall_M_Mode_Handler /* Ecall M Mode */ 114 | .weak Ecall_U_Mode_Handler /* Ecall U Mode */ 115 | .weak Break_Point_Handler /* Break Point */ 116 | .weak SysTick_Handler /* SysTick */ 117 | .weak SW_Handler /* SW */ 118 | .weak WWDG_IRQHandler /* Window Watchdog */ 119 | .weak PVD_IRQHandler /* PVD through EXTI Line detect */ 120 | .weak TAMPER_IRQHandler /* TAMPER */ 121 | .weak RTC_IRQHandler /* RTC */ 122 | .weak FLASH_IRQHandler /* Flash */ 123 | .weak RCC_IRQHandler /* RCC */ 124 | .weak EXTI0_IRQHandler /* EXTI Line 0 */ 125 | .weak EXTI1_IRQHandler /* EXTI Line 1 */ 126 | .weak EXTI2_IRQHandler /* EXTI Line 2 */ 127 | .weak EXTI3_IRQHandler /* EXTI Line 3 */ 128 | .weak EXTI4_IRQHandler /* EXTI Line 4 */ 129 | .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 130 | .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 131 | .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 132 | .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 133 | .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 134 | .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 135 | .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 136 | .weak ADC1_2_IRQHandler /* ADC1_2 */ 137 | .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 138 | .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 139 | .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ 140 | .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ 141 | .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 142 | .weak TIM1_BRK_IRQHandler /* TIM1 Break */ 143 | .weak TIM1_UP_IRQHandler /* TIM1 Update */ 144 | .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 145 | .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 146 | .weak TIM2_IRQHandler /* TIM2 */ 147 | .weak TIM3_IRQHandler /* TIM3 */ 148 | .weak TIM4_IRQHandler /* TIM4 */ 149 | .weak I2C1_EV_IRQHandler /* I2C1 Event */ 150 | .weak I2C1_ER_IRQHandler /* I2C1 Error */ 151 | .weak I2C2_EV_IRQHandler /* I2C2 Event */ 152 | .weak I2C2_ER_IRQHandler /* I2C2 Error */ 153 | .weak SPI1_IRQHandler /* SPI1 */ 154 | .weak SPI2_IRQHandler /* SPI2 */ 155 | .weak USART1_IRQHandler /* USART1 */ 156 | .weak USART2_IRQHandler /* USART2 */ 157 | .weak USART3_IRQHandler /* USART3 */ 158 | .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 159 | .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 160 | .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ 161 | .weak USBHD_IRQHandler /* USBHD */ 162 | .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ 163 | .weak ETH_IRQHandler /* ETH global */ 164 | .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ 165 | .weak TIM5_IRQHandler /* TIM5 */ 166 | .weak UART4_IRQHandler /* UART4 */ 167 | .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 168 | .weak OSC32KCal_IRQHandler /* OSC32 KCal */ 169 | .weak OSCWakeUp_IRQHandler /* OSC Wake Up */ 170 | 171 | NMI_Handler: 1: j 1b 172 | HardFault_Handler: 1: j 1b 173 | Ecall_M_Mode_Handler: 1: j 1b 174 | Ecall_U_Mode_Handler: 1: j 1b 175 | Break_Point_Handler: 1: j 1b 176 | SysTick_Handler: 1: j 1b 177 | SW_Handler: 1: j 1b 178 | WWDG_IRQHandler: 1: j 1b 179 | PVD_IRQHandler: 1: j 1b 180 | TAMPER_IRQHandler: 1: j 1b 181 | RTC_IRQHandler: 1: j 1b 182 | FLASH_IRQHandler: 1: j 1b 183 | RCC_IRQHandler: 1: j 1b 184 | EXTI0_IRQHandler: 1: j 1b 185 | EXTI1_IRQHandler: 1: j 1b 186 | EXTI2_IRQHandler: 1: j 1b 187 | EXTI3_IRQHandler: 1: j 1b 188 | EXTI4_IRQHandler: 1: j 1b 189 | DMA1_Channel1_IRQHandler: 1: j 1b 190 | DMA1_Channel2_IRQHandler: 1: j 1b 191 | DMA1_Channel3_IRQHandler: 1: j 1b 192 | DMA1_Channel4_IRQHandler: 1: j 1b 193 | DMA1_Channel5_IRQHandler: 1: j 1b 194 | DMA1_Channel6_IRQHandler: 1: j 1b 195 | DMA1_Channel7_IRQHandler: 1: j 1b 196 | ADC1_2_IRQHandler: 1: j 1b 197 | USB_HP_CAN1_TX_IRQHandler: 1: j 1b 198 | USB_LP_CAN1_RX0_IRQHandler: 1: j 1b 199 | CAN1_RX1_IRQHandler: 1: j 1b 200 | CAN1_SCE_IRQHandler: 1: j 1b 201 | EXTI9_5_IRQHandler: 1: j 1b 202 | TIM1_BRK_IRQHandler: 1: j 1b 203 | TIM1_UP_IRQHandler: 1: j 1b 204 | TIM1_TRG_COM_IRQHandler: 1: j 1b 205 | TIM1_CC_IRQHandler: 1: j 1b 206 | TIM2_IRQHandler: 1: j 1b 207 | TIM3_IRQHandler: 1: j 1b 208 | TIM4_IRQHandler: 1: j 1b 209 | I2C1_EV_IRQHandler: 1: j 1b 210 | I2C1_ER_IRQHandler: 1: j 1b 211 | I2C2_EV_IRQHandler: 1: j 1b 212 | I2C2_ER_IRQHandler: 1: j 1b 213 | SPI1_IRQHandler: 1: j 1b 214 | SPI2_IRQHandler: 1: j 1b 215 | USART1_IRQHandler: 1: j 1b 216 | USART2_IRQHandler: 1: j 1b 217 | USART3_IRQHandler: 1: j 1b 218 | EXTI15_10_IRQHandler: 1: j 1b 219 | RTCAlarm_IRQHandler: 1: j 1b 220 | USBWakeUp_IRQHandler: 1: j 1b 221 | USBHD_IRQHandler: 1: j 1b 222 | USBHDWakeUp_IRQHandler: 1: j 1b 223 | ETH_IRQHandler: 1: j 1b 224 | ETHWakeUp_IRQHandler: 1: j 1b 225 | TIM5_IRQHandler: 1: j 1b 226 | OSC32KCal_IRQHandler: 1: j 1b 227 | OSCWakeUp_IRQHandler: 1: j 1b 228 | UART4_IRQHandler: 1: j 1b 229 | DMA1_Channel8_IRQHandler: 1: j 1b 230 | 231 | .section .text.handle_reset,"ax",@progbits 232 | .weak handle_reset 233 | .align 1 234 | handle_reset: 235 | .option push 236 | .option norelax 237 | la gp, __global_pointer$ 238 | .option pop 239 | 1: 240 | la sp, _eusrstack 241 | 2: 242 | /* Load data section from flash to RAM */ 243 | la a0, _data_lma 244 | la a1, _data_vma 245 | la a2, _edata 246 | bgeu a1, a2, 2f 247 | 1: 248 | lw t0, (a0) 249 | sw t0, (a1) 250 | addi a0, a0, 4 251 | addi a1, a1, 4 252 | bltu a1, a2, 1b 253 | 2: 254 | /* Clear bss section */ 255 | la a0, _sbss 256 | la a1, _ebss 257 | bgeu a0, a1, 2f 258 | 1: 259 | sw zero, (a0) 260 | addi a0, a0, 4 261 | bltu a0, a1, 1b 262 | 2: 263 | li t0, 0x1f 264 | csrw 0xbc0, t0 265 | 266 | /* Enable nested and hardware stack */ 267 | li t0, 0x3 268 | csrw 0x804, t0 269 | 270 | /* Enable interrupt */ 271 | li t0, 0x88 272 | csrs mstatus, t0 273 | 274 | la t0, _vector_base 275 | ori t0, t0, 3 276 | csrw mtvec, t0 277 | 278 | jal SystemInit 279 | la t0, main 280 | csrw mepc, t0 281 | mret 282 | -------------------------------------------------------------------------------- /Core/core_riscv.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : core_riscv.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : RISC-V Core Peripheral Access Layer Header File for CH32V20x 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __CORE_RISCV_H__ 13 | #define __CORE_RISCV_H__ 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | /* IO definitions */ 20 | #ifdef __cplusplus 21 | #define __I volatile /*!< defines 'read only' permissions */ 22 | #else 23 | #define __I volatile const /*!< defines 'read only' permissions */ 24 | #endif 25 | #define __O volatile /*!< defines 'write only' permissions */ 26 | #define __IO volatile /*!< defines 'read / write' permissions */ 27 | 28 | /* Standard Peripheral Library old types (maintained for legacy purpose) */ 29 | typedef __I uint64_t vuc64; /* Read Only */ 30 | typedef __I uint32_t vuc32; /* Read Only */ 31 | typedef __I uint16_t vuc16; /* Read Only */ 32 | typedef __I uint8_t vuc8; /* Read Only */ 33 | 34 | typedef const uint64_t uc64; /* Read Only */ 35 | typedef const uint32_t uc32; /* Read Only */ 36 | typedef const uint16_t uc16; /* Read Only */ 37 | typedef const uint8_t uc8; /* Read Only */ 38 | 39 | typedef __I int64_t vsc64; /* Read Only */ 40 | typedef __I int32_t vsc32; /* Read Only */ 41 | typedef __I int16_t vsc16; /* Read Only */ 42 | typedef __I int8_t vsc8; /* Read Only */ 43 | 44 | typedef const int64_t sc64; /* Read Only */ 45 | typedef const int32_t sc32; /* Read Only */ 46 | typedef const int16_t sc16; /* Read Only */ 47 | typedef const int8_t sc8; /* Read Only */ 48 | 49 | typedef __IO uint64_t vu64; 50 | typedef __IO uint32_t vu32; 51 | typedef __IO uint16_t vu16; 52 | typedef __IO uint8_t vu8; 53 | 54 | typedef uint64_t u64; 55 | typedef uint32_t u32; 56 | typedef uint16_t u16; 57 | typedef uint8_t u8; 58 | 59 | typedef __IO int64_t vs64; 60 | typedef __IO int32_t vs32; 61 | typedef __IO int16_t vs16; 62 | typedef __IO int8_t vs8; 63 | 64 | typedef int64_t s64; 65 | typedef int32_t s32; 66 | typedef int16_t s16; 67 | typedef int8_t s8; 68 | 69 | typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; 70 | 71 | typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 72 | 73 | typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 74 | 75 | #define RV_STATIC_INLINE static inline 76 | 77 | /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ 78 | typedef struct{ 79 | __I uint32_t ISR[8]; 80 | __I uint32_t IPR[8]; 81 | __IO uint32_t ITHRESDR; 82 | __IO uint32_t RESERVED; 83 | __IO uint32_t CFGR; 84 | __I uint32_t GISR; 85 | __IO uint8_t VTFIDR[4]; 86 | uint8_t RESERVED0[12]; 87 | __IO uint32_t VTFADDR[4]; 88 | uint8_t RESERVED1[0x90]; 89 | __O uint32_t IENR[8]; 90 | uint8_t RESERVED2[0x60]; 91 | __O uint32_t IRER[8]; 92 | uint8_t RESERVED3[0x60]; 93 | __O uint32_t IPSR[8]; 94 | uint8_t RESERVED4[0x60]; 95 | __O uint32_t IPRR[8]; 96 | uint8_t RESERVED5[0x60]; 97 | __IO uint32_t IACTR[8]; 98 | uint8_t RESERVED6[0xE0]; 99 | __IO uint8_t IPRIOR[256]; 100 | uint8_t RESERVED7[0x810]; 101 | __IO uint32_t SCTLR; 102 | }PFIC_Type; 103 | 104 | /* memory mapped structure for SysTick */ 105 | typedef struct 106 | { 107 | __IO u32 CTLR; 108 | __IO u32 SR; 109 | __IO u64 CNT; 110 | __IO u64 CMP; 111 | }SysTick_Type; 112 | 113 | 114 | #define PFIC ((PFIC_Type *) 0xE000E000 ) 115 | #define NVIC PFIC 116 | #define NVIC_KEY1 ((uint32_t)0xFA050000) 117 | #define NVIC_KEY2 ((uint32_t)0xBCAF0000) 118 | #define NVIC_KEY3 ((uint32_t)0xBEEF0000) 119 | 120 | #define SysTick ((SysTick_Type *) 0xE000F000) 121 | 122 | 123 | /********************************************************************* 124 | * @fn __enable_irq 125 | * 126 | * @brief Enable Global Interrupt 127 | * 128 | * @return none 129 | */ 130 | RV_STATIC_INLINE void __enable_irq() 131 | { 132 | __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); 133 | } 134 | 135 | /********************************************************************* 136 | * @fn __disable_irq 137 | * 138 | * @brief Disable Global Interrupt 139 | * 140 | * @return none 141 | */ 142 | RV_STATIC_INLINE void __disable_irq() 143 | { 144 | __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); 145 | } 146 | 147 | /********************************************************************* 148 | * @fn __NOP 149 | * 150 | * @brief nop 151 | * 152 | * @return none 153 | */ 154 | RV_STATIC_INLINE void __NOP() 155 | { 156 | __asm volatile ("nop"); 157 | } 158 | 159 | /********************************************************************* 160 | * @fn NVIC_EnableIRQ 161 | * 162 | * @brief Disable Interrupt 163 | * 164 | * @param IRQn - Interrupt Numbers 165 | * 166 | * @return none 167 | */ 168 | RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 169 | { 170 | NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 171 | } 172 | 173 | /********************************************************************* 174 | * @fn NVIC_DisableIRQ 175 | * 176 | * @brief Disable Interrupt 177 | * 178 | * @param IRQn - Interrupt Numbers 179 | * 180 | * @return none 181 | */ 182 | RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 183 | { 184 | NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 185 | } 186 | 187 | /********************************************************************* 188 | * @fn NVIC_GetStatusIRQ 189 | * 190 | * @brief Get Interrupt Enable State 191 | * 192 | * @param IRQn - Interrupt Numbers 193 | * 194 | * @return 1 - 1: Interrupt Pending Enable 195 | * 0 - Interrupt Pending Disable 196 | */ 197 | RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) 198 | { 199 | return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 200 | } 201 | 202 | /********************************************************************* 203 | * @fn NVIC_GetPendingIRQ 204 | * 205 | * @brief Get Interrupt Pending State 206 | * 207 | * @param IRQn - Interrupt Numbers 208 | * 209 | * @return 1 - 1: Interrupt Pending Enable 210 | * 0 - Interrupt Pending Disable 211 | */ 212 | RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 213 | { 214 | return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 215 | } 216 | 217 | /********************************************************************* 218 | * @fn NVIC_SetPendingIRQ 219 | * 220 | * @brief Set Interrupt Pending 221 | * 222 | * @param IRQn - Interrupt Numbers 223 | * 224 | * @return none 225 | */ 226 | RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 227 | { 228 | NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 229 | } 230 | 231 | /********************************************************************* 232 | * @fn NVIC_ClearPendingIRQ 233 | * 234 | * @brief Clear Interrupt Pending 235 | * 236 | * @param IRQn - Interrupt Numbers 237 | * 238 | * @return none 239 | */ 240 | RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 241 | { 242 | NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 243 | } 244 | 245 | /********************************************************************* 246 | * @fn NVIC_GetActive 247 | * 248 | * @brief Get Interrupt Active State 249 | * 250 | * @param IRQn - Interrupt Numbers 251 | * 252 | * @return 1 - Interrupt Active 253 | * 0 - Interrupt No Active 254 | */ 255 | RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 256 | { 257 | return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 258 | } 259 | 260 | /********************************************************************* 261 | * @fn NVIC_SetPriority 262 | * 263 | * @brief Set Interrupt Priority 264 | * 265 | * @param IRQn - Interrupt Numbers 266 | * priority: bit7 - pre-emption priority 267 | * bit6-bit4 - subpriority 268 | * 269 | * @return none 270 | */ 271 | RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) 272 | { 273 | NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; 274 | } 275 | 276 | /********************************************************************* 277 | * @fn __WFI 278 | * 279 | * @brief Wait for Interrupt 280 | * 281 | * @return none 282 | */ 283 | __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) 284 | { 285 | NVIC->SCTLR &= ~(1<<3); // wfi 286 | asm volatile ("wfi"); 287 | } 288 | 289 | /********************************************************************* 290 | * @fn __WFE 291 | * 292 | * @brief Wait for Events 293 | * 294 | * @return none 295 | */ 296 | __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) 297 | { 298 | uint32_t t; 299 | 300 | t = NVIC->SCTLR; 301 | NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) 302 | NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); 303 | asm volatile ("wfi"); 304 | asm volatile ("wfi"); 305 | } 306 | 307 | /********************************************************************* 308 | * @fn SetVTFIRQ 309 | * 310 | * @brief Set VTF Interrupt 311 | * 312 | * @param addr - VTF interrupt service function base address. 313 | * IRQn - Interrupt Numbers 314 | * num - VTF Interrupt Numbers 315 | * NewState - DISABLE or ENABLE 316 | * 317 | * @return none 318 | */ 319 | RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ 320 | if(num > 3) return ; 321 | 322 | if (NewState != DISABLE) 323 | { 324 | NVIC->VTFIDR[num] = IRQn; 325 | NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); 326 | } 327 | else{ 328 | NVIC->VTFIDR[num] = IRQn; 329 | NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); 330 | } 331 | } 332 | 333 | /********************************************************************* 334 | * @fn NVIC_SystemReset 335 | * 336 | * @brief Initiate a system reset request 337 | * 338 | * @return none 339 | */ 340 | RV_STATIC_INLINE void NVIC_SystemReset(void) 341 | { 342 | NVIC->CFGR = NVIC_KEY3|(1<<7); 343 | } 344 | 345 | 346 | 347 | /* Core_Exported_Functions */ 348 | extern uint32_t __get_MSTATUS(void); 349 | extern void __set_MSTATUS(uint32_t value); 350 | extern uint32_t __get_MISA(void); 351 | extern void __set_MISA(uint32_t value); 352 | extern uint32_t __get_MTVEC(void); 353 | extern void __set_MTVEC(uint32_t value); 354 | extern uint32_t __get_MSCRATCH(void); 355 | extern void __set_MSCRATCH(uint32_t value); 356 | extern uint32_t __get_MEPC(void); 357 | extern void __set_MEPC(uint32_t value); 358 | extern uint32_t __get_MCAUSE(void); 359 | extern void __set_MCAUSE(uint32_t value); 360 | extern uint32_t __get_MTVAL(void); 361 | extern void __set_MTVAL(uint32_t value); 362 | extern uint32_t __get_MVENDORID(void); 363 | extern uint32_t __get_MARCHID(void); 364 | extern uint32_t __get_MIMPID(void); 365 | extern uint32_t __get_MHARTID(void); 366 | extern uint32_t __get_SP(void); 367 | 368 | #ifdef __cplusplus 369 | } 370 | #endif 371 | 372 | #endif 373 | 374 | 375 | 376 | 377 | 378 | -------------------------------------------------------------------------------- /Startup/startup_ch32v20x_D8W.S: -------------------------------------------------------------------------------- 1 | ;/********************************** (C) COPYRIGHT ******************************* 2 | ;* File Name : startup_ch32v20x_D8W.s 3 | ;* Author : WCH 4 | ;* Version : V1.0.0 5 | ;* Date : 2021/06/06 6 | ;* Description : CH32V208x 7 | ;* vector table for eclipse toolchain. 8 | ;********************************************************************************* 9 | ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | ;* Attention: This software (modified or not) and binary are used for 11 | ;* microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | 14 | .section .init,"ax",@progbits 15 | .global _start 16 | .align 1 17 | _start: 18 | j handle_reset 19 | .word 0x00000013 20 | .word 0x00000013 21 | .word 0x00000013 22 | .word 0x00000013 23 | .word 0x00000013 24 | .word 0x00000013 25 | .word 0x00000013 26 | .word 0x00000013 27 | .word 0x00000013 28 | .word 0x00000013 29 | .word 0x00000013 30 | .word 0x00000013 31 | .word 0x00100073 32 | .section .vector,"ax",@progbits 33 | .align 1 34 | _vector_base: 35 | .option norvc; 36 | .word _start 37 | .word 0 38 | .word NMI_Handler /* NMI */ 39 | .word HardFault_Handler /* Hard Fault */ 40 | .word 0 41 | .word Ecall_M_Mode_Handler /* Ecall M Mode */ 42 | .word 0 43 | .word 0 44 | .word Ecall_U_Mode_Handler /* Ecall U Mode */ 45 | .word Break_Point_Handler /* Break Point */ 46 | .word 0 47 | .word 0 48 | .word SysTick_Handler /* SysTick */ 49 | .word 0 50 | .word SW_Handler /* SW */ 51 | .word 0 52 | /* External Interrupts */ 53 | .word WWDG_IRQHandler /* Window Watchdog */ 54 | .word PVD_IRQHandler /* PVD through EXTI Line detect */ 55 | .word TAMPER_IRQHandler /* TAMPER */ 56 | .word RTC_IRQHandler /* RTC */ 57 | .word FLASH_IRQHandler /* Flash */ 58 | .word RCC_IRQHandler /* RCC */ 59 | .word EXTI0_IRQHandler /* EXTI Line 0 */ 60 | .word EXTI1_IRQHandler /* EXTI Line 1 */ 61 | .word EXTI2_IRQHandler /* EXTI Line 2 */ 62 | .word EXTI3_IRQHandler /* EXTI Line 3 */ 63 | .word EXTI4_IRQHandler /* EXTI Line 4 */ 64 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 65 | .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 66 | .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 67 | .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 68 | .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 69 | .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 70 | .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 71 | .word ADC1_2_IRQHandler /* ADC1_2 */ 72 | .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 73 | .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 74 | .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 75 | .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 76 | .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 77 | .word TIM1_BRK_IRQHandler /* TIM1 Break */ 78 | .word TIM1_UP_IRQHandler /* TIM1 Update */ 79 | .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 80 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 81 | .word TIM2_IRQHandler /* TIM2 */ 82 | .word TIM3_IRQHandler /* TIM3 */ 83 | .word TIM4_IRQHandler /* TIM4 */ 84 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 85 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 86 | .word I2C2_EV_IRQHandler /* I2C2 Event */ 87 | .word I2C2_ER_IRQHandler /* I2C2 Error */ 88 | .word SPI1_IRQHandler /* SPI1 */ 89 | .word SPI2_IRQHandler /* SPI2 */ 90 | .word USART1_IRQHandler /* USART1 */ 91 | .word USART2_IRQHandler /* USART2 */ 92 | .word USART3_IRQHandler /* USART3 */ 93 | .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 94 | .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 95 | .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ 96 | .word USBHD_IRQHandler /* USBHD Break */ 97 | .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ 98 | .word ETH_IRQHandler /* ETH global */ 99 | .word ETHWakeUp_IRQHandler /* ETH Wake up */ 100 | .word BB_IRQHandler /* BLE BB */ 101 | .word LLE_IRQHandler /* BLE LLE */ 102 | .word TIM5_IRQHandler /* TIM5 */ 103 | .word UART4_IRQHandler /* UART4 */ 104 | .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 105 | .word OSC32KCal_IRQHandler /* OSC32KCal */ 106 | .word OSCWakeUp_IRQHandler /* OSC Wake Up */ 107 | 108 | .option rvc; 109 | 110 | .section .text.vector_handler, "ax", @progbits 111 | .weak NMI_Handler /* NMI */ 112 | .weak HardFault_Handler /* Hard Fault */ 113 | .weak Ecall_M_Mode_Handler /* Ecall M Mode */ 114 | .weak Ecall_U_Mode_Handler /* Ecall U Mode */ 115 | .weak Break_Point_Handler /* Break Point */ 116 | .weak SysTick_Handler /* SysTick */ 117 | .weak SW_Handler /* SW */ 118 | .weak WWDG_IRQHandler /* Window Watchdog */ 119 | .weak PVD_IRQHandler /* PVD through EXTI Line detect */ 120 | .weak TAMPER_IRQHandler /* TAMPER */ 121 | .weak RTC_IRQHandler /* RTC */ 122 | .weak FLASH_IRQHandler /* Flash */ 123 | .weak RCC_IRQHandler /* RCC */ 124 | .weak EXTI0_IRQHandler /* EXTI Line 0 */ 125 | .weak EXTI1_IRQHandler /* EXTI Line 1 */ 126 | .weak EXTI2_IRQHandler /* EXTI Line 2 */ 127 | .weak EXTI3_IRQHandler /* EXTI Line 3 */ 128 | .weak EXTI4_IRQHandler /* EXTI Line 4 */ 129 | .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 130 | .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 131 | .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 132 | .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 133 | .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 134 | .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 135 | .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 136 | .weak ADC1_2_IRQHandler /* ADC1_2 */ 137 | .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 138 | .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 139 | .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ 140 | .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ 141 | .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 142 | .weak TIM1_BRK_IRQHandler /* TIM1 Break */ 143 | .weak TIM1_UP_IRQHandler /* TIM1 Update */ 144 | .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 145 | .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 146 | .weak TIM2_IRQHandler /* TIM2 */ 147 | .weak TIM3_IRQHandler /* TIM3 */ 148 | .weak TIM4_IRQHandler /* TIM4 */ 149 | .weak I2C1_EV_IRQHandler /* I2C1 Event */ 150 | .weak I2C1_ER_IRQHandler /* I2C1 Error */ 151 | .weak I2C2_EV_IRQHandler /* I2C2 Event */ 152 | .weak I2C2_ER_IRQHandler /* I2C2 Error */ 153 | .weak SPI1_IRQHandler /* SPI1 */ 154 | .weak SPI2_IRQHandler /* SPI2 */ 155 | .weak USART1_IRQHandler /* USART1 */ 156 | .weak USART2_IRQHandler /* USART2 */ 157 | .weak USART3_IRQHandler /* USART3 */ 158 | .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 159 | .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 160 | .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ 161 | .weak USBHD_IRQHandler /* USBHD */ 162 | .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ 163 | .weak ETH_IRQHandler /* ETH global */ 164 | .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ 165 | .weak BB_IRQHandler /* BLE BB */ 166 | .weak LLE_IRQHandler /* BLE LLE */ 167 | .weak TIM5_IRQHandler /* TIM5 */ 168 | .weak UART4_IRQHandler /* UART4 */ 169 | .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 170 | .weak OSC32KCal_IRQHandler /* OSC32 KCal */ 171 | .weak OSCWakeUp_IRQHandler /* OSC Wake Up */ 172 | 173 | NMI_Handler: 1: j 1b 174 | HardFault_Handler: 1: j 1b 175 | Ecall_M_Mode_Handler: 1: j 1b 176 | Ecall_U_Mode_Handler: 1: j 1b 177 | Break_Point_Handler: 1: j 1b 178 | SysTick_Handler: 1: j 1b 179 | SW_Handler: 1: j 1b 180 | WWDG_IRQHandler: 1: j 1b 181 | PVD_IRQHandler: 1: j 1b 182 | TAMPER_IRQHandler: 1: j 1b 183 | RTC_IRQHandler: 1: j 1b 184 | FLASH_IRQHandler: 1: j 1b 185 | RCC_IRQHandler: 1: j 1b 186 | EXTI0_IRQHandler: 1: j 1b 187 | EXTI1_IRQHandler: 1: j 1b 188 | EXTI2_IRQHandler: 1: j 1b 189 | EXTI3_IRQHandler: 1: j 1b 190 | EXTI4_IRQHandler: 1: j 1b 191 | DMA1_Channel1_IRQHandler: 1: j 1b 192 | DMA1_Channel2_IRQHandler: 1: j 1b 193 | DMA1_Channel3_IRQHandler: 1: j 1b 194 | DMA1_Channel4_IRQHandler: 1: j 1b 195 | DMA1_Channel5_IRQHandler: 1: j 1b 196 | DMA1_Channel6_IRQHandler: 1: j 1b 197 | DMA1_Channel7_IRQHandler: 1: j 1b 198 | ADC1_2_IRQHandler: 1: j 1b 199 | USB_HP_CAN1_TX_IRQHandler: 1: j 1b 200 | USB_LP_CAN1_RX0_IRQHandler: 1: j 1b 201 | CAN1_RX1_IRQHandler: 1: j 1b 202 | CAN1_SCE_IRQHandler: 1: j 1b 203 | EXTI9_5_IRQHandler: 1: j 1b 204 | TIM1_BRK_IRQHandler: 1: j 1b 205 | TIM1_UP_IRQHandler: 1: j 1b 206 | TIM1_TRG_COM_IRQHandler: 1: j 1b 207 | TIM1_CC_IRQHandler: 1: j 1b 208 | TIM2_IRQHandler: 1: j 1b 209 | TIM3_IRQHandler: 1: j 1b 210 | TIM4_IRQHandler: 1: j 1b 211 | I2C1_EV_IRQHandler: 1: j 1b 212 | I2C1_ER_IRQHandler: 1: j 1b 213 | I2C2_EV_IRQHandler: 1: j 1b 214 | I2C2_ER_IRQHandler: 1: j 1b 215 | SPI1_IRQHandler: 1: j 1b 216 | SPI2_IRQHandler: 1: j 1b 217 | USART1_IRQHandler: 1: j 1b 218 | USART2_IRQHandler: 1: j 1b 219 | USART3_IRQHandler: 1: j 1b 220 | EXTI15_10_IRQHandler: 1: j 1b 221 | RTCAlarm_IRQHandler: 1: j 1b 222 | USBWakeUp_IRQHandler: 1: j 1b 223 | USBHD_IRQHandler: 1: j 1b 224 | USBHDWakeUp_IRQHandler: 1: j 1b 225 | ETH_IRQHandler: 1: j 1b 226 | ETHWakeUp_IRQHandler: 1: j 1b 227 | BB_IRQHandler: 1: j 1b 228 | LLE_IRQHandler: 1: j 1b 229 | TIM5_IRQHandler: 1: j 1b 230 | UART4_IRQHandler: 1: j 1b 231 | DMA1_Channel8_IRQHandler: 1: j 1b 232 | OSC32KCal_IRQHandler: 1: j 1b 233 | OSCWakeUp_IRQHandler: 1: j 1b 234 | 235 | .section .text.handle_reset,"ax",@progbits 236 | .weak handle_reset 237 | .align 1 238 | handle_reset: 239 | .option push 240 | .option norelax 241 | la gp, __global_pointer$ 242 | .option pop 243 | 1: 244 | la sp, _eusrstack 245 | 2: 246 | /* Load data section from flash to RAM */ 247 | la a0, _data_lma 248 | la a1, _data_vma 249 | la a2, _edata 250 | bgeu a1, a2, 2f 251 | 1: 252 | lw t0, (a0) 253 | sw t0, (a1) 254 | addi a0, a0, 4 255 | addi a1, a1, 4 256 | bltu a1, a2, 1b 257 | 2: 258 | /* Clear bss section */ 259 | la a0, _sbss 260 | la a1, _ebss 261 | bgeu a0, a1, 2f 262 | 1: 263 | sw zero, (a0) 264 | addi a0, a0, 4 265 | bltu a0, a1, 1b 266 | 2: 267 | li t0, 0x1f 268 | csrw 0xbc0, t0 269 | 270 | /* Enable nested and hardware stack */ 271 | li t0, 0x3 272 | csrw 0x804, t0 273 | 274 | /* Enable interrupt */ 275 | li t0, 0x88 276 | csrs mstatus, t0 277 | 278 | la t0, _vector_base 279 | ori t0, t0, 3 280 | csrw mtvec, t0 281 | 282 | jal SystemInit 283 | la t0, main 284 | csrw mepc, t0 285 | mret 286 | 287 | 288 | -------------------------------------------------------------------------------- /Peripheral/inc/ch32v20x_gpio.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_gpio.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * GPIO firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_GPIO_H 14 | #define __CH32V20x_GPIO_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* Output Maximum frequency selection */ 23 | typedef enum 24 | { 25 | GPIO_Speed_10MHz = 1, 26 | GPIO_Speed_2MHz, 27 | GPIO_Speed_50MHz 28 | } GPIOSpeed_TypeDef; 29 | 30 | /* Configuration Mode enumeration */ 31 | typedef enum 32 | { 33 | GPIO_Mode_AIN = 0x0, 34 | GPIO_Mode_IN_FLOATING = 0x04, 35 | GPIO_Mode_IPD = 0x28, 36 | GPIO_Mode_IPU = 0x48, 37 | GPIO_Mode_Out_OD = 0x14, 38 | GPIO_Mode_Out_PP = 0x10, 39 | GPIO_Mode_AF_OD = 0x1C, 40 | GPIO_Mode_AF_PP = 0x18 41 | } GPIOMode_TypeDef; 42 | 43 | /* GPIO Init structure definition */ 44 | typedef struct 45 | { 46 | uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. 47 | This parameter can be any value of @ref GPIO_pins_define */ 48 | 49 | GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. 50 | This parameter can be a value of @ref GPIOSpeed_TypeDef */ 51 | 52 | GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. 53 | This parameter can be a value of @ref GPIOMode_TypeDef */ 54 | } GPIO_InitTypeDef; 55 | 56 | /* Bit_SET and Bit_RESET enumeration */ 57 | typedef enum 58 | { 59 | Bit_RESET = 0, 60 | Bit_SET 61 | } BitAction; 62 | 63 | /* GPIO_pins_define */ 64 | #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ 65 | #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ 66 | #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ 67 | #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ 68 | #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ 69 | #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ 70 | #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ 71 | #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ 72 | #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ 73 | #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ 74 | #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ 75 | #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ 76 | #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ 77 | #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ 78 | #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ 79 | #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ 80 | #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ 81 | 82 | /* GPIO_Remap_define */ 83 | /* PCFR1 */ 84 | #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ 85 | #define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ 86 | #define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ 87 | #define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ 88 | #define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ 89 | #define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ 90 | #define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ 91 | #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ 92 | #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ 93 | #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ 94 | #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ 95 | #define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ 96 | #define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ 97 | #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ 98 | #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ 99 | #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ 100 | #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ 101 | #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ 102 | #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ 103 | #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ 104 | #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ 105 | #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ 106 | #define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ 107 | #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ 108 | #define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ 109 | #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ 110 | #define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ 111 | #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ 112 | to TIM2 Internal Trigger 1 for calibration \ 113 | (only for Connectivity line devices) */ 114 | #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ 115 | 116 | /* PCFR2 */ 117 | #define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ 118 | #define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ 119 | #define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ 120 | #define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ 121 | #define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ 122 | #define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ 123 | #define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ 124 | #define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ 125 | #define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ 126 | #define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ 127 | #define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ 128 | #define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ 129 | #define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ 130 | #define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ 131 | #define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ 132 | #define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ 133 | #define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ 134 | 135 | /* GPIO_Port_Sources */ 136 | #define GPIO_PortSourceGPIOA ((uint8_t)0x00) 137 | #define GPIO_PortSourceGPIOB ((uint8_t)0x01) 138 | #define GPIO_PortSourceGPIOC ((uint8_t)0x02) 139 | #define GPIO_PortSourceGPIOD ((uint8_t)0x03) 140 | #define GPIO_PortSourceGPIOE ((uint8_t)0x04) 141 | #define GPIO_PortSourceGPIOF ((uint8_t)0x05) 142 | #define GPIO_PortSourceGPIOG ((uint8_t)0x06) 143 | 144 | /* GPIO_Pin_sources */ 145 | #define GPIO_PinSource0 ((uint8_t)0x00) 146 | #define GPIO_PinSource1 ((uint8_t)0x01) 147 | #define GPIO_PinSource2 ((uint8_t)0x02) 148 | #define GPIO_PinSource3 ((uint8_t)0x03) 149 | #define GPIO_PinSource4 ((uint8_t)0x04) 150 | #define GPIO_PinSource5 ((uint8_t)0x05) 151 | #define GPIO_PinSource6 ((uint8_t)0x06) 152 | #define GPIO_PinSource7 ((uint8_t)0x07) 153 | #define GPIO_PinSource8 ((uint8_t)0x08) 154 | #define GPIO_PinSource9 ((uint8_t)0x09) 155 | #define GPIO_PinSource10 ((uint8_t)0x0A) 156 | #define GPIO_PinSource11 ((uint8_t)0x0B) 157 | #define GPIO_PinSource12 ((uint8_t)0x0C) 158 | #define GPIO_PinSource13 ((uint8_t)0x0D) 159 | #define GPIO_PinSource14 ((uint8_t)0x0E) 160 | #define GPIO_PinSource15 ((uint8_t)0x0F) 161 | 162 | /* Ethernet_Media_Interface */ 163 | #define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) 164 | #define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) 165 | 166 | void GPIO_DeInit(GPIO_TypeDef *GPIOx); 167 | void GPIO_AFIODeInit(void); 168 | void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); 169 | void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); 170 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 171 | uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); 172 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 173 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); 174 | void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 175 | void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 176 | void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); 177 | void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); 178 | void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 179 | void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 180 | void GPIO_EventOutputCmd(FunctionalState NewState); 181 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); 182 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 183 | void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); 184 | 185 | #ifdef __cplusplus 186 | } 187 | #endif 188 | 189 | #endif 190 | -------------------------------------------------------------------------------- /Peripheral/src/ch32v20x_pwr.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_pwr.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the PWR firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_pwr.h" 13 | #include "ch32v20x_rcc.h" 14 | 15 | /* PWR registers bit mask */ 16 | /* CTLR register bit mask */ 17 | #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) 18 | #define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) 19 | 20 | /********************************************************************* 21 | * @fn PWR_DeInit 22 | * 23 | * @brief Deinitializes the PWR peripheral registers to their default 24 | * reset values. 25 | * 26 | * @return none 27 | */ 28 | void PWR_DeInit(void) 29 | { 30 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 31 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 32 | } 33 | 34 | /********************************************************************* 35 | * @fn PWR_BackupAccessCmd 36 | * 37 | * @brief Enables or disables access to the RTC and backup registers. 38 | * 39 | * @param NewState - new state of the access to the RTC and backup registers, 40 | * This parameter can be: ENABLE or DISABLE. 41 | * 42 | * @return none 43 | */ 44 | void PWR_BackupAccessCmd(FunctionalState NewState) 45 | { 46 | if(NewState) 47 | { 48 | PWR->CTLR |= (1 << 8); 49 | } 50 | else 51 | { 52 | PWR->CTLR &= ~(1 << 8); 53 | } 54 | } 55 | 56 | /********************************************************************* 57 | * @fn PWR_PVDCmd 58 | * 59 | * @brief Enables or disables the Power Voltage Detector(PVD). 60 | * 61 | * @param NewState - new state of the PVD(ENABLE or DISABLE). 62 | * 63 | * @return none 64 | */ 65 | void PWR_PVDCmd(FunctionalState NewState) 66 | { 67 | if(NewState) 68 | { 69 | PWR->CTLR |= (1 << 4); 70 | } 71 | else 72 | { 73 | PWR->CTLR &= ~(1 << 4); 74 | } 75 | } 76 | 77 | /********************************************************************* 78 | * @fn PWR_PVDLevelConfig 79 | * 80 | * @brief Configures the voltage threshold detected by the Power Voltage 81 | * Detector(PVD). 82 | * 83 | * @param PWR_PVDLevel - specifies the PVD detection level 84 | * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V 85 | * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V 86 | * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V 87 | * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V 88 | * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V 89 | * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V 90 | * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V 91 | * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V 92 | * 93 | * @return none 94 | */ 95 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 96 | { 97 | uint32_t tmpreg = 0; 98 | tmpreg = PWR->CTLR; 99 | tmpreg &= CTLR_PLS_MASK; 100 | tmpreg |= PWR_PVDLevel; 101 | PWR->CTLR = tmpreg; 102 | } 103 | 104 | /********************************************************************* 105 | * @fn PWR_WakeUpPinCmd 106 | * 107 | * @brief Enables or disables the WakeUp Pin functionality. 108 | * 109 | * @param NewState - new state of the WakeUp Pin functionality 110 | * (ENABLE or DISABLE). 111 | * 112 | * @return none 113 | */ 114 | void PWR_WakeUpPinCmd(FunctionalState NewState) 115 | { 116 | if(NewState) 117 | { 118 | PWR->CSR |= (1 << 8); 119 | } 120 | else 121 | { 122 | PWR->CSR &= ~(1 << 8); 123 | } 124 | } 125 | 126 | /********************************************************************* 127 | * @fn PWR_EnterSTOPMode 128 | * 129 | * @brief Enters STOP mode. 130 | * 131 | * @param PWR_Regulator - specifies the regulator state in STOP mode. 132 | * PWR_Regulator_ON - STOP mode with regulator ON 133 | * PWR_Regulator_LowPower - STOP mode with regulator in low power mode 134 | * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. 135 | * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction 136 | * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction 137 | * 138 | * @return none 139 | */ 140 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 141 | { 142 | uint32_t tmpreg = 0; 143 | tmpreg = PWR->CTLR; 144 | tmpreg &= CTLR_DS_MASK; 145 | tmpreg |= PWR_Regulator; 146 | PWR->CTLR = tmpreg; 147 | 148 | NVIC->SCTLR |= (1 << 2); 149 | 150 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 151 | { 152 | __WFI(); 153 | } 154 | else 155 | { 156 | __WFE(); 157 | } 158 | 159 | NVIC->SCTLR &= ~(1 << 2); 160 | } 161 | 162 | /********************************************************************* 163 | * @fn PWR_EnterSTANDBYMode 164 | * 165 | * @brief Enters STANDBY mode. 166 | * 167 | * @return none 168 | */ 169 | void PWR_EnterSTANDBYMode(void) 170 | { 171 | PWR->CTLR |= PWR_CTLR_CWUF; 172 | PWR->CTLR |= PWR_CTLR_PDDS; 173 | NVIC->SCTLR |= (1 << 2); 174 | 175 | __WFI(); 176 | } 177 | 178 | /********************************************************************* 179 | * @fn PWR_GetFlagStatus 180 | * 181 | * @brief Checks whether the specified PWR flag is set or not. 182 | * 183 | * @param PWR_FLAG - specifies the flag to check. 184 | * PWR_FLAG_WU - Wake Up flag 185 | * PWR_FLAG_SB - StandBy flag 186 | * PWR_FLAG_PVDO - PVD Output 187 | * 188 | * @return none 189 | */ 190 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 191 | { 192 | FlagStatus bitstatus = RESET; 193 | 194 | if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 195 | { 196 | bitstatus = SET; 197 | } 198 | else 199 | { 200 | bitstatus = RESET; 201 | } 202 | return bitstatus; 203 | } 204 | 205 | /********************************************************************* 206 | * @fn PWR_ClearFlag 207 | * 208 | * @brief Clears the PWR's pending flags. 209 | * 210 | * @param PWR_FLAG - specifies the flag to clear. 211 | * PWR_FLAG_WU - Wake Up flag 212 | * PWR_FLAG_SB - StandBy flag 213 | * 214 | * @return none 215 | */ 216 | void PWR_ClearFlag(uint32_t PWR_FLAG) 217 | { 218 | PWR->CTLR |= PWR_FLAG << 2; 219 | } 220 | 221 | /********************************************************************* 222 | * @fn PWR_EnterSTANDBYMode_RAM 223 | * 224 | * @brief Enters STANDBY mode with RAM data retention function on. 225 | * 226 | * @return none 227 | */ 228 | void PWR_EnterSTANDBYMode_RAM(void) 229 | { 230 | uint32_t tmpreg = 0; 231 | tmpreg = PWR->CTLR; 232 | 233 | tmpreg |= PWR_CTLR_CWUF; 234 | tmpreg |= PWR_CTLR_PDDS; 235 | 236 | #if defined (CH32V20x_D8) || defined (CH32V20x_D8W) 237 | //2K+30K in standby w power. 238 | tmpreg |= (0x1 << 16) | (0x1 << 17); 239 | #else 240 | //RAM in standby power. 241 | tmpreg |= ( ( uint32_t )1 << 16 ); 242 | 243 | #endif 244 | 245 | PWR->CTLR = tmpreg; 246 | 247 | NVIC->SCTLR |= (1 << 2); 248 | 249 | __WFI(); 250 | } 251 | 252 | /********************************************************************* 253 | * @fn PWR_EnterSTANDBYMode_RAM_LV 254 | * 255 | * @brief Enters STANDBY mode with RAM data retention function and LV mode on. 256 | * 257 | * @return none 258 | */ 259 | void PWR_EnterSTANDBYMode_RAM_LV(void) 260 | { 261 | uint32_t tmpreg = 0; 262 | tmpreg = PWR->CTLR; 263 | 264 | tmpreg |= PWR_CTLR_CWUF; 265 | tmpreg |= PWR_CTLR_PDDS; 266 | 267 | #if defined (CH32V20x_D8) || defined (CH32V20x_D8W) 268 | //2K+30K in standby power. 269 | tmpreg |= (0x1 << 16) | (0x1 << 17); 270 | //2K+30K in standby LV . 271 | tmpreg |= (0x1 << 20); 272 | #else 273 | //RAM in standby power. 274 | tmpreg |= ( ( uint32_t )1 << 16 ); 275 | //RAM in standby LV . 276 | tmpreg |= ( ( uint32_t )1 << 20 ); 277 | 278 | #endif 279 | 280 | PWR->CTLR = tmpreg; 281 | 282 | NVIC->SCTLR |= (1 << 2); 283 | 284 | __WFI(); 285 | } 286 | 287 | /********************************************************************* 288 | * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN 289 | * 290 | * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). 291 | * 292 | * @return none 293 | */ 294 | void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) 295 | { 296 | uint32_t tmpreg = 0; 297 | tmpreg = PWR->CTLR; 298 | 299 | tmpreg |= PWR_CTLR_CWUF; 300 | tmpreg |= PWR_CTLR_PDDS; 301 | 302 | #if defined (CH32V20x_D8) || defined (CH32V20x_D8W) 303 | //2K+30K in standby power (VBAT Enable). 304 | tmpreg |= (0x1 << 18) | (0x1 << 19); 305 | #else 306 | //RAM in standby w power. 307 | tmpreg |= ( ( uint32_t )1 << 18 ); 308 | 309 | #endif 310 | 311 | PWR->CTLR = tmpreg; 312 | 313 | NVIC->SCTLR |= (1 << 2); 314 | 315 | __WFI(); 316 | } 317 | 318 | /********************************************************************* 319 | * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN 320 | * 321 | * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). 322 | * 323 | * @return none 324 | */ 325 | void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) 326 | { 327 | uint32_t tmpreg = 0; 328 | tmpreg = PWR->CTLR; 329 | 330 | tmpreg |= PWR_CTLR_CWUF; 331 | tmpreg |= PWR_CTLR_PDDS; 332 | 333 | #if defined (CH32V20x_D8) || defined (CH32V20x_D8W) 334 | //2K+30K in standby power (VBAT Enable). 335 | tmpreg |= (0x1 << 18) | (0x1 << 19); 336 | //2K+30K in standby LV . 337 | tmpreg |= (0x1 << 20); 338 | #else 339 | //RAM in standby w power. 340 | tmpreg |= ( ( uint32_t )1 << 18 ); 341 | //RAM in standby LV . 342 | tmpreg |= ( ( uint32_t )1 << 20 ); 343 | 344 | #endif 345 | 346 | PWR->CTLR = tmpreg; 347 | 348 | NVIC->SCTLR |= (1 << 2); 349 | 350 | __WFI(); 351 | } 352 | 353 | 354 | /********************************************************************* 355 | * @fn PWR_EnterSTOPMode_RAM_LV 356 | * 357 | * @brief Enters STOP mode with RAM data retention function and LV mode on. 358 | * 359 | * @param PWR_Regulator - specifies the regulator state in STOP mode. 360 | * PWR_Regulator_ON - STOP mode with regulator ON 361 | * PWR_Regulator_LowPower - STOP mode with regulator in low power mode 362 | * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. 363 | * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction 364 | * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction 365 | * 366 | * @return none 367 | */ 368 | void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 369 | { 370 | uint32_t tmpreg = 0; 371 | tmpreg = PWR->CTLR; 372 | tmpreg &= CTLR_DS_MASK; 373 | tmpreg |= PWR_Regulator; 374 | 375 | #if defined (CH32V20x_D8) || defined (CH32V20x_D8W) 376 | //2K+30K in standby power. 377 | tmpreg |= (0x1 << 16) | (0x1 << 17); 378 | //2K+30K in standby LV . 379 | tmpreg |= (0x1 << 20); 380 | #else 381 | //RAM in standby power. 382 | tmpreg |= ( ( uint32_t )1 << 16 ); 383 | //RAM in standby LV . 384 | tmpreg |= ( ( uint32_t )1 << 20 ); 385 | 386 | #endif 387 | 388 | PWR->CTLR = tmpreg; 389 | 390 | NVIC->SCTLR |= (1 << 2); 391 | 392 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 393 | { 394 | __WFI(); 395 | } 396 | else 397 | { 398 | __WFE(); 399 | } 400 | 401 | NVIC->SCTLR &= ~(1 << 2); 402 | } 403 | --------------------------------------------------------------------------------