├── LICENSE ├── Makefile ├── README.md ├── ch552.h ├── cli.js ├── package-lock.json ├── package.json ├── usbjtag.bin ├── usbjtag.c └── usbjtag.js /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2020, blueskull 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | all: 2 | sdcc -mmcs51 --xram-size 0x0400 --xram-loc 0x0000 --code-size 0x3800 usbjtag.c -o usbjtag.hex 3 | objcopy -I ihex -O binary usbjtag.hex usbjtag.bin 4 | -@rm -rf *.asm *.lst *.rel *.rst *.sym *.lk *.map *.mem *.hex 5 | 6 | flash: all 7 | ./cli.js write mcu usbjtag.bin -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # CH552-JTAG 2 | USB-JTAG Adapter Using CH552 3 | 4 | (C) Bo Gao, 2020~2022 5 | 6 | MCU C code and PC JaveScript code licensed under BSD 3-clause. 7 | 8 | JavaScript code usbjtag.js and cli.js licensed under BSD 3-clause, created based on Gowin TN653 document (discontinued, now merged into UG290). 9 | 10 | This project aims to provide a low cost USB to JTAG adapter for various chips, in this case, Gowin FPGAs. 11 | 12 | The MCU handles low level TMS, TDI, TDO shifting in bitbang mode and TDI shifting in SPI mode. 13 | 14 | Double buffering is added to accelerate data transfer, as well as programmable and pin-selectable clock output. 15 | 16 | The above are needed for certain timing-critical and clock-critical operations, such as flash programming for certain Gowin parts. 17 | 18 | MCU firmware compilation: use the supplied makefile, you will need SDCC installed. 19 | 20 | JavaScript CLI: refer to the built-in help "./cli.js", you will need libusb and a few Node.JS packages installed, run "npm i" to install all packages. 21 | 22 | Zadig is needed to install libusb driver manually on Windows. Look for USB-JTA device and install libusb for it. 23 | 24 | UDEV rules need to be added to grant non-root users access to the device. 25 | 26 | The current version has NOT been tested on Windows or macOS, and is only tested on Linux 5.11. Use at your own risk on untested platforms. -------------------------------------------------------------------------------- /ch552.h: -------------------------------------------------------------------------------- 1 | /* 2 | CH552 USB MCU SDCC Header File 3 | 4 | Copyright (c) 2020, Bo Gao <7zlaser@gmail.com> 5 | Rewritten and simplified from Blinkinlabs's ch554_sdcc project. 6 | 7 | Redistribution and use in source and binary forms, with or without modification, 8 | are permitted provided that the following conditions are met: 9 | 10 | 1. Redistributions of source code must retain the above copyright notice, this list of 11 | conditions and the following disclaimer. 12 | 2. Redistributions in binary form must reproduce the above copyright notice, this list 13 | of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 3. Neither the name of the copyright holder nor the names of its contributors may be 16 | used to endorse or promote products derived from this software without specific 17 | prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 20 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 | OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 22 | SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 23 | EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE 27 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | */ 29 | 30 | #ifndef __CH552_H__ 31 | #define __CH552_H__ 32 | 33 | #include 34 | #include 35 | 36 | // System SFRs 37 | SFR(PSW, 0xD0); 38 | SBIT(CY, 0xD0, 7); 39 | SBIT(AC, 0xD0, 6); 40 | SBIT(F0, 0xD0, 5); 41 | SBIT(RS1, 0xD0, 4); 42 | SBIT(RS0, 0xD0, 3); 43 | SBIT(OV, 0xD0, 2); 44 | SBIT(F1, 0xD0, 1); 45 | SBIT(P, 0xD0, 0); 46 | SFR(ACC, 0xE0); 47 | SFR(B, 0xF0); 48 | SFR(SP, 0x81); 49 | SFR(DPL, 0x82); 50 | SFR(DPH, 0x83); 51 | SFR(SAFE_MOD, 0xA1); 52 | SFR(GLOBAL_CFG, 0xB1); 53 | SFR(PCON, 0x87); 54 | SFR(CLOCK_CFG, 0xB9); 55 | SFR(WAKE_CTRL, 0xA9); 56 | SFR(RESET_KEEP, 0xFE); 57 | SFR(WDOG_COUNT, 0xFF); 58 | 59 | // Interrupt SFRs 60 | SFR(IE, 0xA8); 61 | SBIT(EA, 0xA8, 7); 62 | SBIT(E_DIS, 0xA8, 6); 63 | SBIT(ET2, 0xA8, 5); 64 | SBIT(ES, 0xA8, 4); 65 | SBIT(ET1, 0xA8, 3); 66 | SBIT(EX1, 0xA8, 2); 67 | SBIT(ET0, 0xA8, 1); 68 | SBIT(EX0, 0xA8, 0); 69 | SFR(IP, 0xB8); 70 | SBIT(PH_FLAG, 0xB8, 7); 71 | SBIT(PL_FLAG, 0xB8, 6); 72 | SBIT(PT2, 0xB8, 5); 73 | SBIT(PS, 0xB8, 4); 74 | SBIT(PT1, 0xB8, 3); 75 | SBIT(PX1, 0xB8, 2); 76 | SBIT(PT0, 0xB8, 1); 77 | SBIT(PX0, 0xB8, 0); 78 | SFR(IE_EX, 0xE8); 79 | SBIT(IE_WDOG, 0xE8, 7); 80 | SBIT(IE_GPIO, 0xE8, 6); 81 | SBIT(IE_PWMX, 0xE8, 5); 82 | SBIT(IE_UART1, 0xE8, 4); 83 | SBIT(IE_ADC, 0xE8, 3); 84 | SBIT(IE_USB, 0xE8, 2); 85 | SBIT(IE_TKEY, 0xE8, 1); 86 | SBIT(IE_SPI0, 0xE8, 0); 87 | SFR(IP_EX, 0xE9); 88 | SFR(GPIO_IE, 0xC7); 89 | 90 | //Flash SFRs 91 | SFR16(ROM_ADDR, 0x84); 92 | SFR(ROM_ADDR_L, 0x84); 93 | SFR(ROM_ADDR_H, 0x85); 94 | SFR16(ROM_DATA, 0x8E); 95 | SFR(ROM_DATA_L, 0x8E); 96 | SFR(ROM_DATA_H, 0x8F); 97 | SFR(ROM_CTRL, 0x86); 98 | 99 | // Port SFRs 100 | SFR(P1, 0x90); 101 | SBIT(P10, 0x90, 0); 102 | SBIT(P11, 0x90, 1); 103 | SBIT(P12, 0x90, 2); 104 | SBIT(P13, 0x90, 3); 105 | SBIT(P14, 0x90, 4); 106 | SBIT(P15, 0x90, 5); 107 | SBIT(P16, 0x90, 6); 108 | SBIT(P17, 0x90, 7); 109 | SFR(P1_MOD_OC, 0x92); 110 | SFR(P1_DIR_PU, 0x93); 111 | SFR(P2, 0xA0); 112 | SFR(P3, 0xB0); 113 | SBIT(P30, 0xB0, 0); 114 | SBIT(P31, 0xB0, 1); 115 | SBIT(P32, 0xB0, 2); 116 | SBIT(P33, 0xB0, 3); 117 | SBIT(P34, 0xB0, 4); 118 | SBIT(P35, 0xB0, 5); 119 | SBIT(P36, 0xB0, 6); 120 | SBIT(P37, 0xB0, 7); 121 | SFR(P3_MOD_OC, 0x96); 122 | SFR(P3_DIR_PU, 0x97); 123 | SFR(PIN_FUNC, 0xC6); 124 | SFR(XBUS_AUX, 0xA2); 125 | 126 | // Timer0/1 SFRs 127 | SFR(TCON,0x88); 128 | SBIT(TF1, 0x88, 7); 129 | SBIT(TR1, 0x88, 6); 130 | SBIT(TF0, 0x88, 5); 131 | SBIT(TR0, 0x88, 4); 132 | SBIT(IE1, 0x88, 3); 133 | SBIT(IT1, 0x88, 2); 134 | SBIT(IE0, 0x88, 1); 135 | SBIT(IT0, 0x88, 0); 136 | SFR(TMOD,0x89); 137 | SFR(TL0,0x8A); 138 | SFR(TL1,0x8B); 139 | SFR(TH0,0x8C); 140 | SFR(TH1,0x8D); 141 | 142 | // Timer2 SFRs 143 | SFR(T2CON, 0xC8); 144 | SBIT(TF2, 0xC8, 7); 145 | SBIT(CAP1F, 0xC8, 7); 146 | SBIT(EXF2, 0xC8, 6); 147 | SBIT(RCLK, 0xC8, 5); 148 | SBIT(TCLK, 0xC8, 4); 149 | SBIT(EXEN2, 0xC8, 3); 150 | SBIT(TR2, 0xC8, 2); 151 | SBIT(C_T2, 0xC8, 1); 152 | SBIT(CP_RL2, 0xC8, 0); 153 | SFR(T2MOD, 0xC9); 154 | SFR16(RCAP2, 0xCA); 155 | SFR(RCAP2L, 0xCA); 156 | SFR(RCAP2H, 0xCB); 157 | SFR16(T2COUNT, 0xCC); 158 | SFR(TL2, 0xCC); 159 | SFR(TH2, 0xCD); 160 | SFR16(T2CAP1, 0xCE); 161 | SFR(T2CAP1L, 0xCE); 162 | SFR(T2CAP1H, 0xCF); 163 | 164 | // PWM SFRs 165 | SFR(PWM_DATA2, 0x9B); 166 | SFR(PWM_DATA1, 0x9C); 167 | SFR(PWM_CTRL, 0x9D); 168 | SFR(PWM_CK_SE, 0x9E); 169 | 170 | // UART0 SFRs 171 | SFR(SCON, 0x98); 172 | SBIT(SM0, 0x98, 7); 173 | SBIT(SM0, 0x98, 7); 174 | SBIT(SM1, 0x98, 6); 175 | SBIT(SM2, 0x98, 5); 176 | SBIT(REN, 0x98, 4); 177 | SBIT(TB8, 0x98, 3); 178 | SBIT(RB8, 0x98, 2); 179 | SBIT(TI, 0x98, 1); 180 | SBIT(RI, 0x98, 0); 181 | SFR(SBUF, 0x99); 182 | 183 | // UART1 SFRs 184 | SFR(SCON1, 0xC0); 185 | SBIT(U1SM0, 0xC0, 7); 186 | SBIT(U1SMOD, 0xC0, 5); 187 | SBIT(U1REN, 0xC0, 4); 188 | SBIT(U1TB8, 0xC0, 3); 189 | SBIT(U1RB8, 0xC0, 2); 190 | SBIT(U1TI, 0xC0, 1); 191 | SBIT(U1RI, 0xC0, 0); 192 | SFR(SBUF1, 0xC1); 193 | SFR(SBAUD1, 0xC2); 194 | 195 | // SPI SFRs 196 | SFR(SPI0_STAT, 0xF8); 197 | SBIT(S0_FST_ACT, 0xF8, 7); 198 | SBIT(S0_IF_OV, 0xF8, 6); 199 | SBIT(S0_IF_FIRST, 0xF8, 5); 200 | SBIT(S0_IF_BYTE, 0xF8, 4); 201 | SBIT(S0_FREE, 0xF8, 3); 202 | SBIT(S0_T_FIFO, 0xF8, 2); 203 | SBIT(S0_R_FIFO, 0xF8, 0); 204 | SFR(SPI0_DATA, 0xF9); 205 | SFR(SPI0_CTRL, 0xFA); 206 | SFR(SPI0_CK_SE, 0xFB); 207 | SFR(SPI0_SETUP, 0xFC); 208 | 209 | // ADC SFRs 210 | SFR(ADC_CTRL, 0x80); 211 | SBIT(CMPO, 0x80, 7); 212 | SBIT(CMP_IF, 0x80, 6); 213 | SBIT(ADC_IF, 0x80, 5); 214 | SBIT(ADC_START, 0x80, 4); 215 | SBIT(CMP_CHAN, 0x80, 3); 216 | SBIT(ADC_CHAN1, 0x80, 1); 217 | SBIT(ADC_CHAN0, 0x80, 0); 218 | SFR(ADC_CFG, 0x9A); 219 | SFR(ADC_DATA, 0x9F); 220 | 221 | // Touch SFRs 222 | SFR(TKEY_CTRL, 0xC3); 223 | SFR16(TKEY_DAT, 0xC4); 224 | SFR(TKEY_DATL, 0xC4); 225 | SFR(TKEY_DATH, 0xC5); 226 | 227 | // USB SFRs 228 | SFR(USB_C_CTRL, 0x91); 229 | SFR(USB_CTRL, 0xE2); 230 | SFR(UDEV_CTRL, 0xD1); 231 | SFR(USB_DEV_AD, 0xE3); 232 | SFR(USB_MIS_ST, 0xDA); 233 | SFR(USB_RX_LEN, 0xDB); 234 | SFR(USB_INT_EN, 0xE1); 235 | SFR(USB_INT_FG, 0xD8); 236 | SBIT(U_IS_NAK, 0xD8, 7); 237 | SBIT(U_TOG_OK, 0xD8, 6); 238 | SBIT(U_SIE_FREE, 0xD8, 5); 239 | SBIT(UIF_FIFO_OV, 0xD8, 4); 240 | SBIT(UIF_HST_SOF, 0xD8, 3); 241 | SBIT(UIF_SUSPEND, 0xD8, 2); 242 | SBIT(UIF_TRANSFER, 0xD8, 1); 243 | SBIT(UIF_DETECT, 0xD8, 0); 244 | SBIT(UIF_BUS_RST, 0xD8, 0); 245 | SFR(USB_INT_ST, 0xD9); 246 | SFR(UEP4_1_MOD, 0xEA); 247 | SFR(UEP2_3_MOD, 0xEB); 248 | SFR(UEP0_CTRL, 0xDC); 249 | SFR(UEP0_T_LEN, 0xDD); 250 | SFR(UEP1_CTRL, 0xD2); 251 | SFR(UEP1_T_LEN, 0xD3); 252 | SFR(UEP2_CTRL, 0xD4); 253 | SFR(UEP2_T_LEN, 0xD5); 254 | SFR(UEP3_CTRL, 0xD6); 255 | SFR(UEP3_T_LEN, 0xD7); 256 | SFR(UEP4_CTRL, 0xDE); 257 | SFR(UEP4_T_LEN, 0xDF); 258 | SFR16(UEP0_DMA, 0xEC); 259 | SFR(UEP0_DMA_L, 0xEC); 260 | SFR(UEP0_DMA_H, 0xED); 261 | SFR16(UEP1_DMA, 0xEE); 262 | SFR(UEP1_DMA_L, 0xEE); 263 | SFR(UEP1_DMA_H, 0xEF); 264 | SFR16(UEP2_DMA, 0xE4); 265 | SFR(UEP2_DMA_L, 0xE4); 266 | SFR(UEP2_DMA_H, 0xE5); 267 | SFR16(UEP3_DMA, 0xE6); 268 | SFR(UEP3_DMA_L, 0xE6); 269 | SFR(UEP3_DMA_H, 0xE7); 270 | 271 | // Interrupt vectors 272 | #define INT_NO_INT0 0 273 | #define INT_NO_TMR0 1 274 | #define INT_NO_INT1 2 275 | #define INT_NO_TMR1 3 276 | #define INT_NO_UART0 4 277 | #define INT_NO_TMR2 5 278 | #define INT_NO_SPI0 6 279 | #define INT_NO_TKEY 7 280 | #define INT_NO_USB 8 281 | #define INT_NO_ADC 9 282 | #define INT_NO_UART1 10 283 | #define INT_NO_PWMX 11 284 | #define INT_NO_GPIO 12 285 | #define INT_NO_WDOG 13 286 | 287 | #endif -------------------------------------------------------------------------------- /cli.js: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env node 2 | 3 | // Copyright (c) 2020-2021, Bo Gao <7zlaser@gmail.com> 4 | 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | 8 | // 1. Redistributions of source code must retain the above copyright notice, this list of 9 | // conditions and the following disclaimer. 10 | // 2. Redistributions in binary form must reproduce the above copyright notice, this list 11 | // of conditions and the following disclaimer in the documentation 12 | // and/or other materials provided with the distribution. 13 | // 3. Neither the name of the copyright holder nor the names of its contributors may be 14 | // used to endorse or promote products derived from this software without specific 15 | // prior written permission. 16 | 17 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 18 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 20 | // SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 | // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 | // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 | // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE 25 | // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | 27 | const util=require("util"); 28 | const exec=util.promisify(require("child_process").exec); 29 | const UsbJtag=require("./usbjtag"); 30 | const jtag=new UsbJtag; 31 | 32 | async function cliOpen() { 33 | try {await jtag.open();} catch(e) {console.log(e); process.exit(-1);} 34 | process.on("SIGINT", ()=> {jtag.close();}); 35 | } 36 | 37 | function cliClose(ret) {jtag.close(); process.exit(ret);} 38 | 39 | function cliHelp() { 40 | const name=__filename.slice(__dirname.length+1); 41 | console.log("USBJTAG for Gowin GW1NZ FPGAs\nUsage:"); 42 | console.log(` node ${name} read `); 43 | console.log(` node ${name} write `); 44 | console.log(" *: SPI bytes are space separated and SPI transactions are 's' splitted.") 45 | console.log("Copyright (c) 2020-2021, Bo Gao, licensed under BSD 3-clause license."); 46 | } 47 | 48 | async function cliRead(dest) { 49 | try { 50 | if(dest=="ctl") {await cliOpen(); console.log("CTL: "+("0"+(await jtag.mcuReadReg(0)).toString(16)).slice(-2)); cliClose(0);} 51 | else if(dest=="ctl_rom") {await cliOpen(); console.log("CTL_ROM: "+("0"+(await jtag.mcuReadReg(1)).toString(16)).slice(-2)); cliClose(0);} 52 | else if(dest=="vbus") {await cliOpen(); console.log("VBUS: "+(await jtag.mcuReadVbus()).toFixed(2)+"V"); cliClose(0);} 53 | else if(dest=="sn") {await cliOpen(); console.log("SN: "+await jtag.mcuReadSn()); cliClose(0);} 54 | else cliHelp(); 55 | } 56 | catch(e) {console.log(e); cliClose(-1);} 57 | } 58 | 59 | async function cliWrite(dest, val) { 60 | try { 61 | if(dest=="ctl") {await cliOpen(); await jtag.mcuWriteReg(parseInt(val, 16), 0); cliClose(0);} 62 | else if(dest=="ctl_rom") {await cliOpen(); await jtag.mcuWriteReg(parseInt(val, 16), 1); cliClose(0);} 63 | else if(dest=="sn") {await cliOpen(); await jtag.mcuWriteSn(val); cliClose(0);} 64 | else if(dest=="sram") { 65 | await cliOpen(); 66 | await jtag.fpgaRstPwr(); 67 | await jtag.fpgaRstTap(); // Reset FPGA 68 | await jtag.fpgaRstSram(); 69 | console.log("JTAG ID: "+await jtag.fpgaReadId()); // Read ID 70 | const tStart=process.hrtime(); // Start timing 71 | const len=await jtag.fpgaWriteSram(val); // Program SRAM 72 | const tProg=process.hrtime(tStart); 73 | const tProgMs=tProg[0]*1000+tProg[1]/1000000; 74 | const cfgDone=await jtag.fpgaReadCdn(); // Check CDONE status 75 | console.log(`CDONE status: ${cfgDone?"success":"fail"}\nFile size: ${(len/1024).toFixed(2)} KiB\nElapsed time: ${tProgMs.toFixed(2)} ms\nAverage bitrate: ${(len/125/tProgMs).toFixed(2)} Mbps`); 76 | if(!cfgDone) throw("Error: SRAM bitstream corrupted."); 77 | cliClose(0); 78 | } 79 | else if(dest=="flash") { 80 | await cliOpen(); 81 | await jtag.fpgaRstCfg(); 82 | await jtag.fpgaRstTap(); // Reset FPGA 83 | await jtag.fpgaRstSram(); 84 | console.log("JTAG ID: "+await jtag.fpgaReadId()); // Read ID 85 | const tStart=process.hrtime(); // Start timing 86 | const len=await jtag.fpgaWriteFlash(val); // Program flash 87 | const tProg=process.hrtime(tStart); 88 | const tProgMs=tProg[0]*1000+tProg[1]/1000000; 89 | const cfgDone=await jtag.fpgaReadCdn(); // Check CDONE status 90 | console.log(`CDONE status: ${cfgDone?"success":"fail"}\nFile size: ${(len/1024).toFixed(2)} KiB\nElapsed time: ${tProgMs.toFixed(2)} ms\nAverage bitrate: ${(len/125/tProgMs).toFixed(2)} Mbps`); 91 | if(!cfgDone) throw("Error: Flash bitstream corrupted."); 92 | cliClose(0); 93 | } 94 | else if(dest=="mcu") { 95 | await cliOpen(); 96 | const ctl=await jtag.mcuReadReg(1); 97 | const sn=await jtag.mcuReadSn(); 98 | await jtag.mcuRstIsp(); 99 | jtag.close(); 100 | await util.promisify((t, f)=>setTimeout(f, t))(1000); 101 | console.log((await exec(`python -m ch55xtool -r -f ${val}`)).stdout); 102 | await util.promisify((t, f)=>setTimeout(f, t))(1000); 103 | try {await jtag.open();} catch(e) {console.log(e); process.exit(-1);} 104 | await jtag.mcuWriteReg(ctl, 1); 105 | await jtag.mcuWriteSn(sn); 106 | cliClose(0); 107 | } 108 | } 109 | catch(e) {console.log(e); cliClose(-1);} 110 | } 111 | 112 | async function cliWriteSpi(val) { 113 | let opened=false; 114 | try { 115 | let tx=[]; 116 | let rx=[]; 117 | let txStr=[]; 118 | let rxStr=[]; 119 | let grpCount=0; 120 | const hexRe=/^[0-9a-fA-F]{1,2}$/; 121 | for(let i=0; i=5) { 148 | if(argc==5 && argv[2]=="write" && argv[3]!="spi") await cliWrite(argv[3], argv[4]); // Write register or file 149 | else if(argv[2]=="write" && argv[3]=="spi") await cliWriteSpi(argv.slice(4, argv.length), false); // Write SPI 150 | else {cliHelp(); process.exit(-1);} 151 | } 152 | } 153 | 154 | main(); -------------------------------------------------------------------------------- /package-lock.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "usbjtag", 3 | "version": "1.0.0", 4 | "lockfileVersion": 2, 5 | "requires": true, 6 | "packages": { 7 | "": { 8 | "name": "usbjtag", 9 | "version": "1.0.0", 10 | "license": "ISC", 11 | "dependencies": { 12 | "csv": "^5.5.3", 13 | "usb": "^1.7.2" 14 | } 15 | }, 16 | "node_modules/ansi-regex": { 17 | "version": "2.1.1", 18 | "resolved": "https://registry.npmjs.org/ansi-regex/-/ansi-regex-2.1.1.tgz", 19 | "integrity": "sha1-w7M6te42DYbg5ijwRorn7yfWVN8=", 20 | "engines": { 21 | "node": ">=0.10.0" 22 | } 23 | }, 24 | "node_modules/aproba": { 25 | "version": "1.2.0", 26 | "resolved": "https://registry.npmjs.org/aproba/-/aproba-1.2.0.tgz", 27 | "integrity": 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-------------------------------------------------------------------------------- /package.json: -------------------------------------------------------------------------------- 1 | { 2 | "dependencies": { 3 | "csv": "^5.5.3", 4 | "usb": "^1.7.2" 5 | }, 6 | "name": "usbjtag", 7 | "version": "1.0.0", 8 | "main": "index.js", 9 | "scripts": { 10 | "cli": "node cli.js", 11 | "dpt": "node dpt.js" 12 | }, 13 | "author": "", 14 | "license": "ISC", 15 | "description": "" 16 | } 17 | -------------------------------------------------------------------------------- /usbjtag.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/blueskull/CH552-JTAG/0f8b8bdb98882a2454559f50f0f138560c636d0e/usbjtag.bin -------------------------------------------------------------------------------- /usbjtag.c: -------------------------------------------------------------------------------- 1 | /* 2 | CH552 USB-JTAG Adapter for PicoGate 3 | 4 | Copyright (c) 2020-2021, Bo Gao <7zlaser@gmail.com> 5 | 6 | Redistribution and use in source and binary forms, with or without modification, 7 | are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this list of 10 | conditions and the following disclaimer. 11 | 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 | of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 3. Neither the name of the copyright holder nor the names of its contributors may be 15 | used to endorse or promote products derived from this software without specific 16 | prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 19 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 | OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 21 | SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 | EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE 26 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | */ 28 | 29 | #include 30 | #include 31 | #include "ch552.h" 32 | 33 | // MCU pin map 34 | #define VIS P11 // VBUS SNS/CH552 ADC CH0 35 | #define TDI P15 // GW1NZ TDI/CH552 MOSI 36 | #define TDO P16 // GW1NZ TDO/CH552 MISO 37 | #define TCK P17 // GW1NZ TCK/CH552 SCK 38 | #define TMS P30 // GW1NZ TMS/CH552 NCS_N 39 | #define JEN P31 // GW1NZ JTAGEN_N 40 | #define URS P32 // GW1NZ USRRST_N 41 | #define SDA P33 // SLG46580 I2C SDA 42 | #define SCL P34 // SLG46580 I2C SCL 43 | // #define SCL P15 44 | // #define SDA P16 45 | 46 | // Helper macros 47 | #define pin_mode(p, n, m, v) {p##_MOD_OC=(m==0 || m==1)?p##_MOD_OC&~(1<*slen?*slen:len; for(i=0;ilen) buf_ep0[0]=len;} 61 | #define usb_tx(l) {UEP2_T_LEN=l; UEP2_CTRL&=~0x02;} 62 | #define usb_ret(v) {while(UEP2_T_LEN); buf_ep2[0]=v; usb_tx(1)} 63 | #define i2c_tx(b) {for(i=8;i>0;) {SDA=b&(1<<--i); udelay(5); SCL=1; udelay(5); SCL=0;} SDA=1; udelay(5); SCL=1; udelay(5); SCL=0;} 64 | 65 | // USB descriptors 66 | __code uint8_t desc_dev[]={0x12, 0x01, 0x00, 0x02, 0xff, 0xff, 0xff, 0x40, // USB2.0, vendor device, 64 bytes 67 | 0xa0, 0x20, 0x09, 0x42, 0x00, 0x01, // VID: 0x20a0, PID: 0x4209, V1.0 68 | 0x01, 0x02, 0x00, 0x01}; // Strings 69 | __code uint8_t desc_cfg[]={0x09, 0x02, 0x20, 0x00, 0x01, 0x01, 0x00, 0x80, 0x64, // Bus powered, 100mA 70 | 0x09, 0x04, 0x00, 0x00, 0x02, 0xff, 0xff, 0xff, 0x00, // 2 endpoints, vendor interface 71 | 0x07, 0x05, 0x01, 0x02, 0x40, 0x00, 0x00, // EP1 OUT, bulk, 64 bytes 72 | 0x07, 0x05, 0x82, 0x02, 0x40, 0x00, 0x00}; // EP2 IN, bulk, 64 bytes 73 | __code uint8_t desc_lng[]={0x04, 0x03, 0x09, 0x04}; // en-US 74 | __code uint8_t desc_ven[]={0x12, 0x03, 'B', 0, 'o', 0, '\'', 0, 's', 0, ' ', 0, 'L', 0, 'a', 0, 'b', 0}; 75 | __code uint8_t desc_pro[]={0x12, 0x03, 'U', 0, 'S', 0, 'B', 0, '-', 0, 'J', 0, 'T', 0, 'A', 0, 'G', 0}; 76 | 77 | // Endpoint buffers 78 | __xdata __at (0x0000) uint8_t buf_ep0[64]; 79 | __xdata __at (0x0080) uint8_t buf_ep1[2][64]; 80 | __xdata __at (0x0040) uint8_t buf_ep2[64]; 81 | uint8_t len_ep1[2], idx_r_ep1; 82 | #define buf_ep1_r buf_ep1[idx_r_ep1] 83 | #define buf_ep1_w buf_ep1[1-idx_r_ep1] 84 | #define len_ep1_r len_ep1[idx_r_ep1] 85 | #define len_ep1_w len_ep1[1-idx_r_ep1] 86 | 87 | // Delay functions 88 | void udelay(uint8_t us) {while(us--) {SAFE_MOD++; SAFE_MOD++; SAFE_MOD++;}} 89 | void mdelay(uint8_t ms) {while(ms--) {udelay(250); udelay(250); udelay(250); udelay(242);}} 90 | 91 | // PMU and CLKOUT functions 92 | void pmu_write(uint8_t val) {uint8_t i; SDA=0; udelay(5); SCL=0; i2c_tx(0x10) i2c_tx(0xf4) i2c_tx(val) SDA=0; udelay(5); SCL=1; udelay(5); SDA=1;} 93 | void clk_on(uint8_t div, uint8_t jtag) {if(jtag) {PIN_FUNC&=~0x01; pin_mode(P1, 4, 3, 1) pin_mode(P1, 7, 0, 0) pin_mode(P1, 0, 1, 0)} else {PIN_FUNC|=0x01; pin_mode(P1, 0, 0, 0) pin_mode(P1, 7, 1, 0) pin_mode(P1, 4, 1, 0)} RCAP2=0xffff-div; T2MOD=0xc2; T2CON=0x04;} 94 | void clk_off(void) {pin_mode(P1, 0, 0, 0) pin_mode(P1, 7, 1, 0) pin_mode(P1, 4, 3, 1) T2CON=0x00; T2MOD=0x00; RCAP2=0x00;} 95 | 96 | // Write or read control byte 97 | uint8_t ctl_write(uint8_t mask, uint8_t opr, uint8_t val) 98 | { 99 | static uint8_t ctl_byte=0x00; 100 | if(mask==0x00 && opr==0x01 && ctl_byte&0x01) {URS=0; pmu_write(pmu_byte); udelay(250); pmu_write(pmu_byte|0x08); mdelay(40); URS=1; return 0;} // Reset FPGA 101 | if(mask==0x00 && opr==0x02 && ctl_byte&0x01) {URS=0; udelay(250); URS=1; return 0;} // Reset user logic 102 | if(mask==0x00 && opr==0x03 && ctl_byte&0x01) {if(val) clk_on(3, 1); else if(ctl_byte&0x04) clk_on((ctl_byte&0x08)?0:7, 0); else clk_off(); return 0;} // Pulse TCK RTI clock 103 | if(mask==0x00 && opr==0x04) {if(val) {ADC_CFG=0x08; pmu_write(pmu_byte|0x10);} else {ADC_CFG=0x00; pmu_write(pmu_byte&~0x10);} return 0;} // Enable Vbus divider 104 | if(mask==0x00) return ctl_byte; // No special operation and no bit mask defined 105 | if(ctl_byte&0x80) return ctl_byte; // CFG_LOCK 106 | uint8_t ctl_old=ctl_byte; 107 | ctl_byte=ctl_byte&(val|~mask)|(mask&val); 108 | if(ctl_byte&0x04 && ctl_byte&0x01) clk_on((ctl_byte&0x08)?0:7, 0); // Enable clock 109 | if(!(ctl_byte&0x04) || !(ctl_byte&0x01)) clk_off(); // Disable clock 110 | if((ctl_old^ctl_byte)&0x01) // Power status changed 111 | { 112 | URS=0; pmu_write(0x00); mdelay(10); pmu_write(0x08); URS=1; // Power status change, power off first 113 | if(ctl_byte&0x01) {URS=0; pmu_write(pmu_byte); mdelay(5); pmu_write(pmu_byte|0x08); mdelay(40); URS=1;} // Power on 114 | } 115 | return ctl_byte; 116 | } 117 | 118 | // Read data flash 119 | void rom_read(uint8_t add, uint8_t *buf, uint8_t len) 120 | { 121 | uint8_t i; 122 | ROM_ADDR_H=0xc0; 123 | for(i=0;i=8) {spi_tx8 len-=8;} while(len--) {spi_tx} XBUS_AUX=0x00; // Transfer data 142 | if(!jtag) TMS=1; 143 | SPI0_CTRL=0x02; // Disable SPI 144 | } 145 | 146 | // SPI write and read bytes 147 | void spi_write_read(uint8_t __xdata *obuf, uint8_t __xdata *ibuf, uint8_t len, uint8_t jtag) 148 | { 149 | SPI0_CTRL=0x60; // Enable SPI 150 | JEN=!jtag; if(!jtag) TMS=0; // Manipulate IOs 151 | XBUS_AUX=0x00; SAFE_MOD=obuf[0]; XBUS_AUX=0x01; SAFE_MOD=ibuf[0]; XBUS_AUX=0x04; // Populate DPTRs 152 | while(len>=8) {spi_rx8 obuf+=8; len-=8;} while(len--) {spi_rx} XBUS_AUX=0x00; // Transfer data 153 | if(!jtag) TMS=1; 154 | SPI0_CTRL=0x02; // Disable SPI 155 | } 156 | 157 | // JTAG write bytes 158 | void jtag_write(uint8_t __xdata *mbuf, uint8_t __xdata *obuf, uint8_t len) 159 | { 160 | uint8_t i, tms, tdi; 161 | JEN=0; 162 | for(i=0;i>1), len>>1); err=0;} else err=1;} // JTAG write 196 | else if(*arg==0x01) {if(!(len&1)) {while(UEP2_T_LEN); jtag_write_read(dat, dat+(len>>1), buf_ep2, len>>1); usb_tx(len>>1); err=0;} else err=1;} // JTAG write and read 197 | else if(*arg==0x02) {spi_write(dat, len, 1); err=0;} 198 | else if(*arg==0x03) {while(UEP2_T_LEN); spi_write_read(dat, buf_ep2, len, 1); usb_tx(len); err=0;} 199 | else err=1; 200 | else if(*cmd==0x02 && len) // SPI operation, must have a data payload 201 | if(*arg==0x00) {spi_write(dat, len, 0); err=0;} 202 | else if(*arg==0x01) {while(UEP2_T_LEN); spi_write_read(dat, buf_ep2, len, 0); usb_tx(len); err=0;} 203 | else err=1; 204 | else err=1; 205 | } 206 | 207 | // EP0 setup handler 208 | void usb_setup(uint8_t *scode, uint8_t *slen, uint8_t *config) 209 | { 210 | uint8_t len, i; 211 | UEP0_CTRL&=~0x01; // NAK next 212 | if(USB_RX_LEN!=8) goto ep0_stall; 213 | *slen=buf_ep0[6]; 214 | if(buf_ep0[7]) *slen=64; 215 | len=0; 216 | *scode=buf_ep0[1]; 217 | if((buf_ep0[0]&0x60)==0) // Standard request 218 | if(*scode==0x06) // Get descriptor 219 | { 220 | if(buf_ep0[3]==0x01) usb_txdesc(desc_dev) // Device descriptor 221 | else if(buf_ep0[3]==0x02) usb_txdesc(desc_cfg) // Config descriptor 222 | else if(buf_ep0[3]==0x03) // String descriptors 223 | { 224 | if(buf_ep0[2]==0x00) {usb_txdesc(desc_lng) buf_ep0[0]=len;} 225 | else if(buf_ep0[2]==0x01) usb_txstr(desc_ven) 226 | else if(buf_ep0[2]==0x02) usb_txstr(desc_pro) 227 | else goto ep0_stall; 228 | } 229 | else goto ep0_stall; 230 | } 231 | else if(*scode==0x05) *slen=buf_ep0[2]; // Set address 232 | else if(*scode==0x08) {buf_ep0[0]=*config; len=*slen?1:0;} // Get config 233 | else if(*scode==0x09) *config=buf_ep0[2]; // Set config 234 | else if(*scode==0x0a) {buf_ep0[0]=0x00; len=*slen?1:0;} // Get interface 235 | else if(*scode==0x00) // Get status 236 | { 237 | if(buf_ep0[0]==0x82 && buf_ep0[4]==0x01) buf_ep0[0]=(UEP1_CTRL&0x0c)==0x0c?1:0; // Get EP1 OUT stall 238 | else if(buf_ep0[0]==0x82 && buf_ep0[4]==0x82) buf_ep0[0]=(UEP2_CTRL&0x03)==0x03?1:0; // Get EP2 IN stall 239 | else buf_ep0[0]=0; 240 | buf_ep0[1]=0; len=*slen>2?2:*slen; 241 | } 242 | else if(buf_ep0[0]==0x02 && *scode==0x03) // Set feature 243 | if(buf_ep0[4]==0x01) UEP1_CTRL|=0x0c; // Set EP1 OUT stall 244 | else if(buf_ep0[4]==0x82) UEP2_CTRL|=0x03; // Set EP2 IN stall 245 | else goto ep0_stall; 246 | else if(buf_ep0[0]==0x02 && *scode==0x01) // Clear feature 247 | if(buf_ep0[4]==0x01) UEP1_CTRL=UEP1_CTRL&~0x8c; // Reset EP1 OUT stall 248 | else if(buf_ep0[4]==0x82) UEP2_CTRL=UEP2_CTRL&~0x43; // Reset EP2 IN stall 249 | else goto ep0_stall; 250 | else goto ep0_stall; 251 | else {ep0_stall: *slen=*scode=0x00; UEP0_CTRL=0x03; return;} 252 | UEP0_T_LEN=len; UEP0_CTRL=0xc0; // Transmit as DATA1 253 | } 254 | 255 | // USB interrupt handler 256 | void usb_isr(void) __interrupt(INT_NO_USB) __using(1) 257 | { 258 | static uint8_t scode=0, slen=0, config=0; 259 | uint8_t token; 260 | if(UIF_TRANSFER) // Transfer done 261 | { 262 | token=USB_INT_ST&0x3f; 263 | if(token==0x01 && U_TOG_OK) {if(len_ep1_r) UEP1_CTRL|=0x08; len_ep1_w=USB_RX_LEN; idx_r_ep1=1-idx_r_ep1; UEP1_DMA=(uint16_t)buf_ep1_w;} // EP1 OUT 264 | else if(token==0x22 && U_TOG_OK) {UEP2_T_LEN=0; UEP2_CTRL|=0x02;} // EP2 IN 265 | else if(token==0x30) usb_setup(&scode, &slen, &config); // EP0 setup 266 | else if(token==0x20) {if(scode==0x05) USB_DEV_AD=slen; UEP0_T_LEN=0; UEP0_CTRL=0x02;} // EP0 IN 267 | else if(token==0x00) UEP0_CTRL=0x02; // EP0 OUT 268 | UIF_TRANSFER=0; 269 | } 270 | else if(UIF_BUS_RST) // Bus reset 271 | { 272 | UEP0_CTRL=0x02; // Reset EP0 IN/OUT 273 | UEP1_CTRL=0x13; idx_r_ep1=1; UEP1_DMA=(uint16_t)buf_ep1_w; len_ep1_r=len_ep1_w=0; // Reset EP1 OUT 274 | UEP2_CTRL=0x1e; UEP2_DMA=(uint16_t)buf_ep2; UEP2_T_LEN=0; // Reset EP2 IN 275 | USB_DEV_AD=0x00; scode=slen=config=0; USB_INT_FG=0xff; // Reset address and states 276 | } 277 | else USB_INT_FG=0xff; 278 | } 279 | 280 | // Entry point 281 | void main(void) 282 | { 283 | uint8_t rom; 284 | uint8_t __xdata *buf; 285 | uint8_t *len; 286 | SAFE_MOD=0x55; SAFE_MOD=0xaa; CLOCK_CFG=CLOCK_CFG&~0x07|0x05; SAFE_MOD=0x00; // Initialize clock at 16 MHz 287 | pin_mode(P1, 0, 0, 0) pin_mode(P1, 1, 0, 0) pin_mode(P1, 4, 3, 1) pin_mode(P1, 5, 1, 0) pin_mode(P1, 6, 0, 0) pin_mode(P1, 7, 1, 0) // Initialize P1 288 | pin_mode(P3, 0, 1, 1) pin_mode(P3, 1, 1, 1) pin_mode(P3, 2, 1, 1) pin_mode(P3, 3, 3, 1) pin_mode(P3, 4, 1, 1) // Initialize P3 289 | //pin_mode(P1, 5, 1, 1) pin_mode(P1, 6, 3, 1) 290 | rom_read(0x00, &rom, 1); if(rom==0xff) {rom=0x0f; rom_write(0x00, &rom, 1);} ctl_write(0xff, 0x00, rom); // Populate control byte 291 | SPI0_CK_SE=2; // Initialize SPI at 8 MHz 292 | IE_USB=0; USB_CTRL=0x00; // Reset USB 293 | UEP0_CTRL=0x02; UEP0_DMA=(uint16_t)buf_ep0; // Configure EP0 IN/OUT 294 | UEP4_1_MOD=0x80; UEP1_CTRL=0x13; idx_r_ep1=1; UEP1_DMA=(uint16_t)buf_ep1_w; len_ep1_r=len_ep1_w=0; // Configure EP1 OUT 295 | UEP2_3_MOD=0x04; UEP2_CTRL=0x1e; UEP2_DMA=(uint16_t)buf_ep2; UEP2_T_LEN=0; // Configure EP2 IN 296 | USB_DEV_AD=0x00; UDEV_CTRL=0x08; USB_CTRL=0x29; UDEV_CTRL|=0x01; USB_INT_FG=0xff; USB_INT_EN=0x03; IE_USB=1; EA=1; // Initialize USB 297 | while(1) {while(!len_ep1_r); EA=0; buf=buf_ep1_r; len=&len_ep1_r; EA=1; usb_parse(buf, *len); *len=0; UEP1_CTRL&=~0x08;} // Poll data and ACK on next request 298 | } -------------------------------------------------------------------------------- /usbjtag.js: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020-2021, Bo Gao <7zlaser@gmail.com> 2 | 3 | // Redistribution and use in source and binary forms, with or without modification, 4 | // are permitted provided that the following conditions are met: 5 | 6 | // 1. Redistributions of source code must retain the above copyright notice, this list of 7 | // conditions and the following disclaimer. 8 | // 2. Redistributions in binary form must reproduce the above copyright notice, this list 9 | // of conditions and the following disclaimer in the documentation 10 | // and/or other materials provided with the distribution. 11 | // 3. Neither the name of the copyright holder nor the names of its contributors may be 12 | // used to endorse or promote products derived from this software without specific 13 | // prior written permission. 14 | 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 16 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 18 | // SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 | // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 | // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 | // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE 23 | // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | 25 | const usb=require("usb"); 26 | const util=require('util'); 27 | const fs=require("fs"); 28 | 29 | class UsbJtag { 30 | // Private members 31 | #rx; 32 | #tx; 33 | 34 | // Find and open device, initialize endpoints 35 | async open() { 36 | // Find device 37 | this.dev=usb.findByIds(0x20a0, 0x4209); 38 | if(!this.dev) throw("Error: cannot find USB device."); 39 | // Open and configure device 40 | try { 41 | this.dev.open(true); 42 | this.dev.interfaces[0].claim(); 43 | const rxe=this.dev.interfaces[0].endpoint(0x82); 44 | const txe=this.dev.interfaces[0].endpoint(0x01); 45 | rxe.timeout=100; 46 | txe.timeout=100; 47 | // Promisify callback functions 48 | this.rx=util.promisify(rxe.transfer).bind(rxe); 49 | this.tx=util.promisify(txe.transfer).bind(txe); 50 | } 51 | catch(e) {throw("Error: failed to open USB device.");} 52 | // Flush input buffer 53 | try {await this.rx(64);} catch(e) {;} 54 | } 55 | 56 | // Close device 57 | close() {this.dev.close();} 58 | 59 | // Read bytes from device 60 | async usbRead() {return await this.rx(64);} 61 | 62 | // Write bytes to device 63 | async usbWrite(cmd, arg, dat=[]) {return await this.tx([cmd, arg, ...dat]);} 64 | 65 | // Write bytes to then read bytes from device 66 | async usbCall(cmd, arg, dat=[], len=-1) { 67 | await this.usbWrite(cmd, arg, dat); 68 | const ret=await this.usbRead(); 69 | if(len>=0 && ret.length!=len) throw("Error: invalid response length."); 70 | return ret; 71 | } 72 | 73 | // Hard reset FPGA, opcode 0x00, 0x00, 0x00 74 | async fpgaRstPwr() {await this.usbWrite(0x00, 0x00, [0x00]);} 75 | 76 | // User reset FPGA, opcode 0x00, 0x00, 0x01 77 | async fpgaRstUsr() {await this.usbWrite(0x00, 0x00, [0x01]);} 78 | 79 | // Read control byte, opcode 0x00, 0x01 80 | async mcuReadReg(rom) { 81 | if(rom) return (await this.usbCall(0x00, 0x01, [0x01], 1))[0]; 82 | return (await this.usbCall(0x00, 0x01, [0x00], 1))[0]; 83 | } 84 | 85 | // Write control bytes, opcode 0x00, 0x02 86 | async mcuWriteReg(val, rom) { 87 | if(rom) await this.usbWrite(0x00, 0x02, [0x01, val]); 88 | await this.usbWrite(0x00, 0x02, [0x00, val]); 89 | } 90 | 91 | // Read USB bus voltage, opcode 0x00, 0x03 92 | async mcuReadVbus() {return (await this.usbCall(0x00, 0x03, [], 1))[0]*0.0258;} 93 | 94 | // Delay ms plus us, opcode 0x00, 0x04, 0x00 95 | async mcuDelay(ms, us) { 96 | if(ms<0 || ms>255 || us<0 || us>255) throw("Error: value out of bound."); 97 | await this.usbWrite(0x00, 0x04, [0x00, ms, us]); 98 | } 99 | 100 | // Read error status, opcode 0x00, 0x05 101 | async mcuReadErr() {return (await this.usbCall(0x00, 0x05, [], 1))[0];} 102 | 103 | // Read serial number, opcode 0x00, 0xfd 104 | async mcuReadSn() {return String.fromCharCode.apply(null, await this.usbCall(0x00, 0xfd, [], 16)).replace(/\0/g, "");} 105 | 106 | // Write serial number, opcode 0x00, 0xfe 107 | async mcuWriteSn(val) { 108 | if(val.length<1 || val.length>16) throw("Error: invalid input length."); 109 | await this.usbWrite(0x00, 0xfe, val.split("").map((c)=> {return c.charCodeAt()})); 110 | } 111 | 112 | // Reset into ISP mode, opcode 0x00, 0xff 113 | async mcuRstIsp() {try {await this.usbWrite(0x00, 0xff);} catch(e) {;}} 114 | 115 | // JTAG write, opcode 0x01, 0x00/0x02 116 | async fpgaWriteJtag(tms, tdi, fast=false) { 117 | if(fast) { 118 | if(tdi.length<1 || tdi.length>62) throw("Error: invalid input length."); 119 | await this.usbWrite(0x01, 0x02, tdi); 120 | } 121 | else { 122 | if(tdi.length<1 || tdi.length>31 || tdi.length!=tms.length) throw("Error: invalid input length."); 123 | await this.usbWrite(0x01, 0x00, [...tms, ...tdi]); 124 | } 125 | } 126 | 127 | // JTAG write and read, opcode 0x01, 0x01/0x03 128 | async fpgaCallJtag(tms, tdi, fast=false) { 129 | if(fast) { 130 | if(tdi.length<1 || tdi.length>62) throw("Error: invalid input length."); 131 | return await this.usbCall(0x01, 0x03, tdi, tdi.length); 132 | } 133 | else { 134 | if(tdi.length<1 || tdi.length>31 || tdi.length!=tms.length) throw("Error: invalid input length."); 135 | return await this.usbCall(0x01, 0x01, [...tms, ...tdi], tdi.length); 136 | } 137 | } 138 | 139 | // JTAG pulse TCK, opcode 0x00, 0x04, 0x01 140 | async fpgaPulseJtag(ms, us) { 141 | if(ms<0 || ms>255 || us<0 || us>255) throw("Error: value out of bound."); 142 | await this.usbWrite(0x00, 0x04, [0x01, ms, us]); 143 | } 144 | 145 | // SPI write, opcode 0x02, 0x00 146 | async fpgaWriteSpi(dat) { 147 | if(dat.length<1 || dat.length>62) throw("Error: invalid input length."); 148 | await this.usbWrite(0x02, 0x00, dat); 149 | } 150 | 151 | // SPI write and read, opcode 0x02, 0x01 152 | async fpgaCallSpi(dat) { 153 | if(dat.length<1 || dat.length>62) throw("Error: invalid input length."); 154 | return await this.usbCall(0x02, 0x01, dat, dat.length); 155 | } 156 | 157 | // Reset TAP 158 | async fpgaRstTap() {await this.fpgaWriteJtag([0xff], [0x00]);} 159 | 160 | // Send JTAG command 161 | async fpgaWriteCmd(cmd) {await this.fpgaWriteJtag([0x30, 0x80, 0x01], [0x00, cmd&0xff, 0x00]);} 162 | 163 | // Read JTAG register 164 | async fpgaReadReg(reg) { 165 | await this.fpgaWriteCmd(reg); 166 | return (await this.fpgaCallJtag([0x20, 0x00, 0x00, 0x00, 0x80, 0x01], [0x00, 0x00, 0x00, 0x00, 0x00, 0x00])).reverse().slice(1, 5); 167 | } 168 | 169 | // Read FPGA ID 170 | async fpgaReadId() {return Array.from(await this.fpgaReadReg(0x11), (b)=> {return ("0"+b.toString(16)).slice(-2);}).join("");} 171 | 172 | // Read FPGA CDONE status 173 | async fpgaReadCdn() {return ((await this.fpgaReadReg(0x41))[2]&0x20)?true:false;} 174 | 175 | // FPGA reset SRAM 176 | async fpgaRstSram() { 177 | await this.fpgaWriteCmd(0x15); 178 | await this.fpgaWriteCmd(0x05); 179 | await this.fpgaWriteCmd(0x02); 180 | await this.mcuDelay(10, 0); 181 | await this.fpgaWriteCmd(0x09); 182 | await this.fpgaWriteCmd(0x3a); 183 | await this.fpgaWriteCmd(0x02); 184 | } 185 | 186 | // FPGA program SRAM 187 | async fpgaWriteSram(filename) { 188 | await this.fpgaWriteCmd(0x15); 189 | await this.fpgaWriteCmd(0x12); 190 | await this.fpgaWriteCmd(0x17); 191 | await this.fpgaWriteJtag([0x20], [0x00]); // Shift-DR 192 | const buf=await fs.promises.readFile(filename); 193 | if(!buf) throw("Error: cannot read input file."); 194 | const len=buf.length; 195 | for(let i=0;i62?62+i:len); 197 | await this.fpgaWriteJtag([], [...chunk], true); 198 | } 199 | await this.fpgaWriteJtag([0x03], [0x00]); // Idle 200 | await this.fpgaWriteCmd(0x3a); 201 | await this.fpgaWriteCmd(0x02); 202 | return len; 203 | } 204 | 205 | // FPGA program flash 206 | async fpgaWriteFlash(filename) { 207 | throw("Error: function not implemented."); 208 | } 209 | } 210 | 211 | module.exports=UsbJtag; --------------------------------------------------------------------------------