├── McuConnectPlc
├── plc_app.c
└── plc_app.h
├── STM32F10x_StdPeriph_Driver
├── inc
│ ├── misc.h
│ ├── stm32f10x_adc.h
│ ├── stm32f10x_bkp.h
│ ├── stm32f10x_can.h
│ ├── stm32f10x_cec.h
│ ├── stm32f10x_crc.h
│ ├── stm32f10x_dac.h
│ ├── stm32f10x_dbgmcu.h
│ ├── stm32f10x_dma.h
│ ├── stm32f10x_exti.h
│ ├── stm32f10x_flash.h
│ ├── stm32f10x_fsmc.h
│ ├── stm32f10x_gpio.h
│ ├── stm32f10x_i2c.h
│ ├── stm32f10x_iwdg.h
│ ├── stm32f10x_pwr.h
│ ├── stm32f10x_rcc.h
│ ├── stm32f10x_rtc.h
│ ├── stm32f10x_sdio.h
│ ├── stm32f10x_spi.h
│ ├── stm32f10x_tim.h
│ ├── stm32f10x_usart.h
│ └── stm32f10x_wwdg.h
└── src
│ ├── misc.c
│ ├── stm32f10x_adc.c
│ ├── stm32f10x_bkp.c
│ ├── stm32f10x_can.c
│ ├── stm32f10x_cec.c
│ ├── stm32f10x_crc.c
│ ├── stm32f10x_dac.c
│ ├── stm32f10x_dbgmcu.c
│ ├── stm32f10x_dma.c
│ ├── stm32f10x_exti.c
│ ├── stm32f10x_flash.c
│ ├── stm32f10x_fsmc.c
│ ├── stm32f10x_gpio.c
│ ├── stm32f10x_i2c.c
│ ├── stm32f10x_iwdg.c
│ ├── stm32f10x_pwr.c
│ ├── stm32f10x_rcc.c
│ ├── stm32f10x_rtc.c
│ ├── stm32f10x_sdio.c
│ ├── stm32f10x_spi.c
│ ├── stm32f10x_tim.c
│ ├── stm32f10x_usart.c
│ └── stm32f10x_wwdg.c
├── core_cm3.c
├── doc
├── 21.txt
├── FX1N PLC强制 ONOFF 的地址.txt
├── FX2N-32MR-001通信协议.txt
├── ourdev_543668.xls
├── 三菱代码解析.txt
├── 三菱指令.TXT
├── 写参数.TXT
├── 写程10.TXT
├── 写程序.TXT
├── 写空白程序.TXT
├── 寄存器位(点)元件地址(按地址排）.TXT
└── 新建 文本文档.txt
├── fault_test.c
├── mcu
├── NVIC.c
├── NVIC.h
├── RCC.c
├── RCC.h
├── RTC.c
├── RTC.h
├── UsartDma.c
├── UsartDma.h
├── main.c
├── stm32f10x.h
├── stm32f10x_conf.h
├── stm32f10x_it.c
├── stm32f10x_it.h
├── system_stm32f10x.c
├── system_stm32f10x.h
├── usart1.c
└── usart1.h
├── plc
├── Instructions.c
├── Instructions.h
├── PLC_CONF.H
├── PLC_Comm.c
├── PLC_DataOperating.c
├── PLC_Other.C
├── PLC_PUBLIC.C
├── PLC_PUBLIC.H
├── PLC_ProgTest.c
├── PLC_RUN.C
├── PLC_RUN.H
├── PLC_STL.C
└── data.c
├── startup_stm32f10x_hd.s
└── stm32f10x_flash.icf
/McuConnectPlc/plc_app.c:
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https://raw.githubusercontent.com/bomingfeng/Fx2N/492c286dce868a5dae4615c4156a080a6fdb83df/McuConnectPlc/plc_app.c
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/McuConnectPlc/plc_app.h:
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https://raw.githubusercontent.com/bomingfeng/Fx2N/492c286dce868a5dae4615c4156a080a6fdb83df/McuConnectPlc/plc_app.h
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/STM32F10x_StdPeriph_Driver/inc/misc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file misc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the miscellaneous
8 | * firmware library functions (add-on to CMSIS functions).
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __MISC_H
25 | #define __MISC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup MISC
39 | * @{
40 | */
41 |
42 | /** @defgroup MISC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief NVIC Init Structure definition
48 | */
49 |
50 | typedef struct
51 | {
52 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
53 | This parameter can be a value of @ref IRQn_Type
54 | (For the complete STM32 Devices IRQ Channels list, please
55 | refer to stm32f10x.h file) */
56 |
57 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
58 | specified in NVIC_IRQChannel. This parameter can be a value
59 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */
60 |
61 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
62 | in NVIC_IRQChannel. This parameter can be a value
63 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */
64 |
65 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
66 | will be enabled or disabled.
67 | This parameter can be set either to ENABLE or DISABLE */
68 | } NVIC_InitTypeDef;
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup NVIC_Priority_Table
75 | * @{
76 | */
77 |
78 | /**
79 | @code
80 | The table below gives the allowed values of the pre-emption priority and subpriority according
81 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
82 | ============================================================================================================================
83 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
84 | ============================================================================================================================
85 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
86 | | | | 4 bits for subpriority
87 | ----------------------------------------------------------------------------------------------------------------------------
88 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
89 | | | | 3 bits for subpriority
90 | ----------------------------------------------------------------------------------------------------------------------------
91 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
92 | | | | 2 bits for subpriority
93 | ----------------------------------------------------------------------------------------------------------------------------
94 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
95 | | | | 1 bits for subpriority
96 | ----------------------------------------------------------------------------------------------------------------------------
97 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
98 | | | | 0 bits for subpriority
99 | ============================================================================================================================
100 | @endcode
101 | */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /** @defgroup MISC_Exported_Constants
108 | * @{
109 | */
110 |
111 | /** @defgroup Vector_Table_Base
112 | * @{
113 | */
114 |
115 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
116 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
117 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
118 | ((VECTTAB) == NVIC_VectTab_FLASH))
119 | /**
120 | * @}
121 | */
122 |
123 | /** @defgroup System_Low_Power
124 | * @{
125 | */
126 |
127 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
128 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
129 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
130 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
131 | ((LP) == NVIC_LP_SLEEPDEEP) || \
132 | ((LP) == NVIC_LP_SLEEPONEXIT))
133 | /**
134 | * @}
135 | */
136 |
137 | /** @defgroup Preemption_Priority_Group
138 | * @{
139 | */
140 |
141 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
142 | 4 bits for subpriority */
143 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
144 | 3 bits for subpriority */
145 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
146 | 2 bits for subpriority */
147 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
148 | 1 bits for subpriority */
149 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
150 | 0 bits for subpriority */
151 |
152 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
153 | ((GROUP) == NVIC_PriorityGroup_1) || \
154 | ((GROUP) == NVIC_PriorityGroup_2) || \
155 | ((GROUP) == NVIC_PriorityGroup_3) || \
156 | ((GROUP) == NVIC_PriorityGroup_4))
157 |
158 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
159 |
160 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
161 |
162 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
163 |
164 | /**
165 | * @}
166 | */
167 |
168 | /** @defgroup SysTick_clock_source
169 | * @{
170 | */
171 |
172 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
173 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
174 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
175 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
176 | /**
177 | * @}
178 | */
179 |
180 | /**
181 | * @}
182 | */
183 |
184 | /** @defgroup MISC_Exported_Macros
185 | * @{
186 | */
187 |
188 | /**
189 | * @}
190 | */
191 |
192 | /** @defgroup MISC_Exported_Functions
193 | * @{
194 | */
195 |
196 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
197 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
198 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
199 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
200 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
201 |
202 | #ifdef __cplusplus
203 | }
204 | #endif
205 |
206 | #endif /* __MISC_H */
207 |
208 | /**
209 | * @}
210 | */
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /**
217 | * @}
218 | */
219 |
220 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
221 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_bkp.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the BKP firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_BKP_H
25 | #define __STM32F10x_BKP_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup BKP
39 | * @{
40 | */
41 |
42 | /** @defgroup BKP_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup BKP_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup Tamper_Pin_active_level
55 | * @{
56 | */
57 |
58 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000)
59 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
60 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
61 | ((LEVEL) == BKP_TamperPinLevel_Low))
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
67 | * @{
68 | */
69 |
70 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000)
71 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
72 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
73 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
74 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
75 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
76 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
77 | ((SOURCE) == BKP_RTCOutputSource_Second))
78 | /**
79 | * @}
80 | */
81 |
82 | /** @defgroup Data_Backup_Register
83 | * @{
84 | */
85 |
86 | #define BKP_DR1 ((uint16_t)0x0004)
87 | #define BKP_DR2 ((uint16_t)0x0008)
88 | #define BKP_DR3 ((uint16_t)0x000C)
89 | #define BKP_DR4 ((uint16_t)0x0010)
90 | #define BKP_DR5 ((uint16_t)0x0014)
91 | #define BKP_DR6 ((uint16_t)0x0018)
92 | #define BKP_DR7 ((uint16_t)0x001C)
93 | #define BKP_DR8 ((uint16_t)0x0020)
94 | #define BKP_DR9 ((uint16_t)0x0024)
95 | #define BKP_DR10 ((uint16_t)0x0028)
96 | #define BKP_DR11 ((uint16_t)0x0040)
97 | #define BKP_DR12 ((uint16_t)0x0044)
98 | #define BKP_DR13 ((uint16_t)0x0048)
99 | #define BKP_DR14 ((uint16_t)0x004C)
100 | #define BKP_DR15 ((uint16_t)0x0050)
101 | #define BKP_DR16 ((uint16_t)0x0054)
102 | #define BKP_DR17 ((uint16_t)0x0058)
103 | #define BKP_DR18 ((uint16_t)0x005C)
104 | #define BKP_DR19 ((uint16_t)0x0060)
105 | #define BKP_DR20 ((uint16_t)0x0064)
106 | #define BKP_DR21 ((uint16_t)0x0068)
107 | #define BKP_DR22 ((uint16_t)0x006C)
108 | #define BKP_DR23 ((uint16_t)0x0070)
109 | #define BKP_DR24 ((uint16_t)0x0074)
110 | #define BKP_DR25 ((uint16_t)0x0078)
111 | #define BKP_DR26 ((uint16_t)0x007C)
112 | #define BKP_DR27 ((uint16_t)0x0080)
113 | #define BKP_DR28 ((uint16_t)0x0084)
114 | #define BKP_DR29 ((uint16_t)0x0088)
115 | #define BKP_DR30 ((uint16_t)0x008C)
116 | #define BKP_DR31 ((uint16_t)0x0090)
117 | #define BKP_DR32 ((uint16_t)0x0094)
118 | #define BKP_DR33 ((uint16_t)0x0098)
119 | #define BKP_DR34 ((uint16_t)0x009C)
120 | #define BKP_DR35 ((uint16_t)0x00A0)
121 | #define BKP_DR36 ((uint16_t)0x00A4)
122 | #define BKP_DR37 ((uint16_t)0x00A8)
123 | #define BKP_DR38 ((uint16_t)0x00AC)
124 | #define BKP_DR39 ((uint16_t)0x00B0)
125 | #define BKP_DR40 ((uint16_t)0x00B4)
126 | #define BKP_DR41 ((uint16_t)0x00B8)
127 | #define BKP_DR42 ((uint16_t)0x00BC)
128 |
129 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
130 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
131 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
132 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
133 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
134 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
135 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
136 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
137 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
138 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
139 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
140 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
141 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
142 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
143 |
144 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
145 | /**
146 | * @}
147 | */
148 |
149 | /**
150 | * @}
151 | */
152 |
153 | /** @defgroup BKP_Exported_Macros
154 | * @{
155 | */
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /** @defgroup BKP_Exported_Functions
162 | * @{
163 | */
164 |
165 | void BKP_DeInit(void);
166 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
167 | void BKP_TamperPinCmd(FunctionalState NewState);
168 | void BKP_ITConfig(FunctionalState NewState);
169 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
170 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
171 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
172 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
173 | FlagStatus BKP_GetFlagStatus(void);
174 | void BKP_ClearFlag(void);
175 | ITStatus BKP_GetITStatus(void);
176 | void BKP_ClearITPendingBit(void);
177 |
178 | #ifdef __cplusplus
179 | }
180 | #endif
181 |
182 | #endif /* __STM32F10x_BKP_H */
183 | /**
184 | * @}
185 | */
186 |
187 | /**
188 | * @}
189 | */
190 |
191 | /**
192 | * @}
193 | */
194 |
195 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
196 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_cec.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the CEC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_CEC_H
25 | #define __STM32F10x_CEC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup CEC
39 | * @{
40 | */
41 |
42 |
43 | /** @defgroup CEC_Exported_Types
44 | * @{
45 | */
46 |
47 | /**
48 | * @brief CEC Init structure definition
49 | */
50 | typedef struct
51 | {
52 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
53 | This parameter can be a value of @ref CEC_BitTiming_Mode */
54 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
55 | This parameter can be a value of @ref CEC_BitPeriod_Mode */
56 | }CEC_InitTypeDef;
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /** @defgroup CEC_Exported_Constants
63 | * @{
64 | */
65 |
66 | /** @defgroup CEC_BitTiming_Mode
67 | * @{
68 | */
69 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
70 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
71 |
72 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
73 | ((MODE) == CEC_BitTimingErrFreeMode))
74 | /**
75 | * @}
76 | */
77 |
78 | /** @defgroup CEC_BitPeriod_Mode
79 | * @{
80 | */
81 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
82 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
83 |
84 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
85 | ((MODE) == CEC_BitPeriodFlexibleMode))
86 | /**
87 | * @}
88 | */
89 |
90 |
91 | /** @defgroup CEC_interrupts_definition
92 | * @{
93 | */
94 | #define CEC_IT_TERR CEC_CSR_TERR
95 | #define CEC_IT_TBTRF CEC_CSR_TBTRF
96 | #define CEC_IT_RERR CEC_CSR_RERR
97 | #define CEC_IT_RBTF CEC_CSR_RBTF
98 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
99 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
100 | /**
101 | * @}
102 | */
103 |
104 |
105 | /** @defgroup CEC_Own_Address
106 | * @{
107 | */
108 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
109 | /**
110 | * @}
111 | */
112 |
113 | /** @defgroup CEC_Prescaler
114 | * @{
115 | */
116 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
117 |
118 | /**
119 | * @}
120 | */
121 |
122 | /** @defgroup CEC_flags_definition
123 | * @{
124 | */
125 |
126 | /**
127 | * @brief ESR register flags
128 | */
129 | #define CEC_FLAG_BTE ((uint32_t)0x10010000)
130 | #define CEC_FLAG_BPE ((uint32_t)0x10020000)
131 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
132 | #define CEC_FLAG_SBE ((uint32_t)0x10080000)
133 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000)
134 | #define CEC_FLAG_LINE ((uint32_t)0x10200000)
135 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
136 |
137 | /**
138 | * @brief CSR register flags
139 | */
140 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002)
141 | #define CEC_FLAG_TERR ((uint32_t)0x00000004)
142 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
143 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010)
144 | #define CEC_FLAG_REOM ((uint32_t)0x00000020)
145 | #define CEC_FLAG_RERR ((uint32_t)0x00000040)
146 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080)
147 |
148 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
149 |
150 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
151 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
152 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
153 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
154 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
155 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
156 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
157 |
158 | /**
159 | * @}
160 | */
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /** @defgroup CEC_Exported_Macros
167 | * @{
168 | */
169 |
170 | /**
171 | * @}
172 | */
173 |
174 | /** @defgroup CEC_Exported_Functions
175 | * @{
176 | */
177 | void CEC_DeInit(void);
178 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
179 | void CEC_Cmd(FunctionalState NewState);
180 | void CEC_ITConfig(FunctionalState NewState);
181 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
182 | void CEC_SetPrescaler(uint16_t CEC_Prescaler);
183 | void CEC_SendDataByte(uint8_t Data);
184 | uint8_t CEC_ReceiveDataByte(void);
185 | void CEC_StartOfMessage(void);
186 | void CEC_EndOfMessageCmd(FunctionalState NewState);
187 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
188 | void CEC_ClearFlag(uint32_t CEC_FLAG);
189 | ITStatus CEC_GetITStatus(uint8_t CEC_IT);
190 | void CEC_ClearITPendingBit(uint16_t CEC_IT);
191 |
192 | #ifdef __cplusplus
193 | }
194 | #endif
195 |
196 | #endif /* __STM32F10x_CEC_H */
197 |
198 | /**
199 | * @}
200 | */
201 |
202 | /**
203 | * @}
204 | */
205 |
206 | /**
207 | * @}
208 | */
209 |
210 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
211 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the CRC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_CRC_H
25 | #define __STM32F10x_CRC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup CRC
39 | * @{
40 | */
41 |
42 | /** @defgroup CRC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup CRC_Exported_Constants
51 | * @{
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup CRC_Exported_Macros
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup CRC_Exported_Functions
67 | * @{
68 | */
69 |
70 | void CRC_ResetDR(void);
71 | uint32_t CRC_CalcCRC(uint32_t Data);
72 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
73 | uint32_t CRC_GetCRC(void);
74 | void CRC_SetIDRegister(uint8_t IDValue);
75 | uint8_t CRC_GetIDRegister(void);
76 |
77 | #ifdef __cplusplus
78 | }
79 | #endif
80 |
81 | #endif /* __STM32F10x_CRC_H */
82 | /**
83 | * @}
84 | */
85 |
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
95 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dac.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the DAC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_DAC_H
25 | #define __STM32F10x_DAC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup DAC
39 | * @{
40 | */
41 |
42 | /** @defgroup DAC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief DAC Init structure definition
48 | */
49 |
50 | typedef struct
51 | {
52 | uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
53 | This parameter can be a value of @ref DAC_trigger_selection */
54 |
55 | uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
56 | are generated, or whether no wave is generated.
57 | This parameter can be a value of @ref DAC_wave_generation */
58 |
59 | uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
60 | the maximum amplitude triangle generation for the DAC channel.
61 | This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
62 |
63 | uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
64 | This parameter can be a value of @ref DAC_output_buffer */
65 | }DAC_InitTypeDef;
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /** @defgroup DAC_Exported_Constants
72 | * @{
73 | */
74 |
75 | /** @defgroup DAC_trigger_selection
76 | * @{
77 | */
78 |
79 | #define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
80 | has been loaded, and not by external trigger */
81 | #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
82 | #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
83 | only in High-density devices*/
84 | #define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
85 | only in Connectivity line, Medium-density and Low-density Value Line devices */
86 | #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
87 | #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
88 | #define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
89 | only in Medium-density and Low-density Value Line devices*/
90 | #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
91 | #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
92 | #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
93 | #define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
94 |
95 | #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
96 | ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
97 | ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
98 | ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
99 | ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
100 | ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
101 | ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
102 | ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
103 | ((TRIGGER) == DAC_Trigger_Software))
104 |
105 | /**
106 | * @}
107 | */
108 |
109 | /** @defgroup DAC_wave_generation
110 | * @{
111 | */
112 |
113 | #define DAC_WaveGeneration_None ((uint32_t)0x00000000)
114 | #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
115 | #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
116 | #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
117 | ((WAVE) == DAC_WaveGeneration_Noise) || \
118 | ((WAVE) == DAC_WaveGeneration_Triangle))
119 | /**
120 | * @}
121 | */
122 |
123 | /** @defgroup DAC_lfsrunmask_triangleamplitude
124 | * @{
125 | */
126 |
127 | #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
128 | #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
129 | #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
130 | #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
131 | #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
132 | #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
133 | #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
134 | #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
135 | #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
136 | #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
137 | #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
138 | #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
139 | #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
140 | #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
141 | #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
142 | #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
143 | #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
144 | #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
145 | #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
146 | #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
147 | #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
148 | #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
149 | #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
150 | #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
151 |
152 | #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
153 | ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
154 | ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
155 | ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
156 | ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
157 | ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
158 | ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
159 | ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
160 | ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
161 | ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
162 | ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
163 | ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
164 | ((VALUE) == DAC_TriangleAmplitude_1) || \
165 | ((VALUE) == DAC_TriangleAmplitude_3) || \
166 | ((VALUE) == DAC_TriangleAmplitude_7) || \
167 | ((VALUE) == DAC_TriangleAmplitude_15) || \
168 | ((VALUE) == DAC_TriangleAmplitude_31) || \
169 | ((VALUE) == DAC_TriangleAmplitude_63) || \
170 | ((VALUE) == DAC_TriangleAmplitude_127) || \
171 | ((VALUE) == DAC_TriangleAmplitude_255) || \
172 | ((VALUE) == DAC_TriangleAmplitude_511) || \
173 | ((VALUE) == DAC_TriangleAmplitude_1023) || \
174 | ((VALUE) == DAC_TriangleAmplitude_2047) || \
175 | ((VALUE) == DAC_TriangleAmplitude_4095))
176 | /**
177 | * @}
178 | */
179 |
180 | /** @defgroup DAC_output_buffer
181 | * @{
182 | */
183 |
184 | #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
185 | #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
186 | #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
187 | ((STATE) == DAC_OutputBuffer_Disable))
188 | /**
189 | * @}
190 | */
191 |
192 | /** @defgroup DAC_Channel_selection
193 | * @{
194 | */
195 |
196 | #define DAC_Channel_1 ((uint32_t)0x00000000)
197 | #define DAC_Channel_2 ((uint32_t)0x00000010)
198 | #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
199 | ((CHANNEL) == DAC_Channel_2))
200 | /**
201 | * @}
202 | */
203 |
204 | /** @defgroup DAC_data_alignment
205 | * @{
206 | */
207 |
208 | #define DAC_Align_12b_R ((uint32_t)0x00000000)
209 | #define DAC_Align_12b_L ((uint32_t)0x00000004)
210 | #define DAC_Align_8b_R ((uint32_t)0x00000008)
211 | #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
212 | ((ALIGN) == DAC_Align_12b_L) || \
213 | ((ALIGN) == DAC_Align_8b_R))
214 | /**
215 | * @}
216 | */
217 |
218 | /** @defgroup DAC_wave_generation
219 | * @{
220 | */
221 |
222 | #define DAC_Wave_Noise ((uint32_t)0x00000040)
223 | #define DAC_Wave_Triangle ((uint32_t)0x00000080)
224 | #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
225 | ((WAVE) == DAC_Wave_Triangle))
226 | /**
227 | * @}
228 | */
229 |
230 | /** @defgroup DAC_data
231 | * @{
232 | */
233 |
234 | #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
235 | /**
236 | * @}
237 | */
238 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
239 | /** @defgroup DAC_interrupts_definition
240 | * @{
241 | */
242 |
243 | #define DAC_IT_DMAUDR ((uint32_t)0x00002000)
244 | #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
245 |
246 | /**
247 | * @}
248 | */
249 |
250 | /** @defgroup DAC_flags_definition
251 | * @{
252 | */
253 |
254 | #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
255 | #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
256 |
257 | /**
258 | * @}
259 | */
260 | #endif
261 |
262 | /**
263 | * @}
264 | */
265 |
266 | /** @defgroup DAC_Exported_Macros
267 | * @{
268 | */
269 |
270 | /**
271 | * @}
272 | */
273 |
274 | /** @defgroup DAC_Exported_Functions
275 | * @{
276 | */
277 |
278 | void DAC_DeInit(void);
279 | void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
280 | void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
281 | void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
282 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
283 | void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
284 | #endif
285 | void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
286 | void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
287 | void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
288 | void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
289 | void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
290 | void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
291 | void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
292 | uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
293 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
294 | FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
295 | void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
296 | ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
297 | void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
298 | #endif
299 |
300 | #ifdef __cplusplus
301 | }
302 | #endif
303 |
304 | #endif /*__STM32F10x_DAC_H */
305 | /**
306 | * @}
307 | */
308 |
309 | /**
310 | * @}
311 | */
312 |
313 | /**
314 | * @}
315 | */
316 |
317 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
318 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the DBGMCU
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_DBGMCU_H
25 | #define __STM32F10x_DBGMCU_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup DBGMCU
39 | * @{
40 | */
41 |
42 | /** @defgroup DBGMCU_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup DBGMCU_Exported_Constants
51 | * @{
52 | */
53 |
54 | #define DBGMCU_SLEEP ((uint32_t)0x00000001)
55 | #define DBGMCU_STOP ((uint32_t)0x00000002)
56 | #define DBGMCU_STANDBY ((uint32_t)0x00000004)
57 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
58 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
59 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
60 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
61 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
62 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
63 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
64 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
65 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
66 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
67 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
68 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
69 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
70 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
71 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
72 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
73 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
74 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
75 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
76 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
77 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
78 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
79 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
80 |
81 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
82 | /**
83 | * @}
84 | */
85 |
86 | /** @defgroup DBGMCU_Exported_Macros
87 | * @{
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /** @defgroup DBGMCU_Exported_Functions
95 | * @{
96 | */
97 |
98 | uint32_t DBGMCU_GetREVID(void);
99 | uint32_t DBGMCU_GetDEVID(void);
100 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
101 |
102 | #ifdef __cplusplus
103 | }
104 | #endif
105 |
106 | #endif /* __STM32F10x_DBGMCU_H */
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
120 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_exti.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the EXTI firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_EXTI_H
25 | #define __STM32F10x_EXTI_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup EXTI
39 | * @{
40 | */
41 |
42 | /** @defgroup EXTI_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief EXTI mode enumeration
48 | */
49 |
50 | typedef enum
51 | {
52 | EXTI_Mode_Interrupt = 0x00,
53 | EXTI_Mode_Event = 0x04
54 | }EXTIMode_TypeDef;
55 |
56 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
57 |
58 | /**
59 | * @brief EXTI Trigger enumeration
60 | */
61 |
62 | typedef enum
63 | {
64 | EXTI_Trigger_Rising = 0x08,
65 | EXTI_Trigger_Falling = 0x0C,
66 | EXTI_Trigger_Rising_Falling = 0x10
67 | }EXTITrigger_TypeDef;
68 |
69 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
70 | ((TRIGGER) == EXTI_Trigger_Falling) || \
71 | ((TRIGGER) == EXTI_Trigger_Rising_Falling))
72 | /**
73 | * @brief EXTI Init Structure definition
74 | */
75 |
76 | typedef struct
77 | {
78 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
79 | This parameter can be any combination of @ref EXTI_Lines */
80 |
81 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
82 | This parameter can be a value of @ref EXTIMode_TypeDef */
83 |
84 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
85 | This parameter can be a value of @ref EXTIMode_TypeDef */
86 |
87 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
88 | This parameter can be set either to ENABLE or DISABLE */
89 | }EXTI_InitTypeDef;
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup EXTI_Exported_Constants
96 | * @{
97 | */
98 |
99 | /** @defgroup EXTI_Lines
100 | * @{
101 | */
102 |
103 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
104 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
105 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
106 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
107 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
108 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
109 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
110 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
111 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
112 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
113 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
114 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
115 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
116 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
117 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
118 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
119 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
120 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
121 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
122 | Wakeup from suspend event */
123 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
124 |
125 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
126 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
127 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
128 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
129 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
130 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
131 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
132 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
133 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
134 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
135 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
136 |
137 |
138 | /**
139 | * @}
140 | */
141 |
142 | /**
143 | * @}
144 | */
145 |
146 | /** @defgroup EXTI_Exported_Macros
147 | * @{
148 | */
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /** @defgroup EXTI_Exported_Functions
155 | * @{
156 | */
157 |
158 | void EXTI_DeInit(void);
159 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
160 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
161 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
162 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
163 | void EXTI_ClearFlag(uint32_t EXTI_Line);
164 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
165 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
166 |
167 | #ifdef __cplusplus
168 | }
169 | #endif
170 |
171 | #endif /* __STM32F10x_EXTI_H */
172 | /**
173 | * @}
174 | */
175 |
176 | /**
177 | * @}
178 | */
179 |
180 | /**
181 | * @}
182 | */
183 |
184 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
185 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the IWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_IWDG_H
25 | #define __STM32F10x_IWDG_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup IWDG
39 | * @{
40 | */
41 |
42 | /** @defgroup IWDG_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup IWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup IWDG_WriteAccess
55 | * @{
56 | */
57 |
58 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
59 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
61 | ((ACCESS) == IWDG_WriteAccess_Disable))
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup IWDG_prescaler
67 | * @{
68 | */
69 |
70 | #define IWDG_Prescaler_4 ((uint8_t)0x00)
71 | #define IWDG_Prescaler_8 ((uint8_t)0x01)
72 | #define IWDG_Prescaler_16 ((uint8_t)0x02)
73 | #define IWDG_Prescaler_32 ((uint8_t)0x03)
74 | #define IWDG_Prescaler_64 ((uint8_t)0x04)
75 | #define IWDG_Prescaler_128 ((uint8_t)0x05)
76 | #define IWDG_Prescaler_256 ((uint8_t)0x06)
77 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
78 | ((PRESCALER) == IWDG_Prescaler_8) || \
79 | ((PRESCALER) == IWDG_Prescaler_16) || \
80 | ((PRESCALER) == IWDG_Prescaler_32) || \
81 | ((PRESCALER) == IWDG_Prescaler_64) || \
82 | ((PRESCALER) == IWDG_Prescaler_128)|| \
83 | ((PRESCALER) == IWDG_Prescaler_256))
84 | /**
85 | * @}
86 | */
87 |
88 | /** @defgroup IWDG_Flag
89 | * @{
90 | */
91 |
92 | #define IWDG_FLAG_PVU ((uint16_t)0x0001)
93 | #define IWDG_FLAG_RVU ((uint16_t)0x0002)
94 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
95 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
96 | /**
97 | * @}
98 | */
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | /** @defgroup IWDG_Exported_Macros
105 | * @{
106 | */
107 |
108 | /**
109 | * @}
110 | */
111 |
112 | /** @defgroup IWDG_Exported_Functions
113 | * @{
114 | */
115 |
116 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
117 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
118 | void IWDG_SetReload(uint16_t Reload);
119 | void IWDG_ReloadCounter(void);
120 | void IWDG_Enable(void);
121 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
122 |
123 | #ifdef __cplusplus
124 | }
125 | #endif
126 |
127 | #endif /* __STM32F10x_IWDG_H */
128 | /**
129 | * @}
130 | */
131 |
132 | /**
133 | * @}
134 | */
135 |
136 | /**
137 | * @}
138 | */
139 |
140 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
141 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_pwr.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the PWR firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_PWR_H
25 | #define __STM32F10x_PWR_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup PWR
39 | * @{
40 | */
41 |
42 | /** @defgroup PWR_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup PWR_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup PVD_detection_level
55 | * @{
56 | */
57 |
58 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
59 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
60 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
61 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
62 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
63 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
64 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
65 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
66 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
67 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
68 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
69 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup Regulator_state_is_STOP_mode
75 | * @{
76 | */
77 |
78 | #define PWR_Regulator_ON ((uint32_t)0x00000000)
79 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001)
80 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
81 | ((REGULATOR) == PWR_Regulator_LowPower))
82 | /**
83 | * @}
84 | */
85 |
86 | /** @defgroup STOP_mode_entry
87 | * @{
88 | */
89 |
90 | #define PWR_STOPEntry_WFI ((uint8_t)0x01)
91 | #define PWR_STOPEntry_WFE ((uint8_t)0x02)
92 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /** @defgroup PWR_Flag
99 | * @{
100 | */
101 |
102 | #define PWR_FLAG_WU ((uint32_t)0x00000001)
103 | #define PWR_FLAG_SB ((uint32_t)0x00000002)
104 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
105 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
106 | ((FLAG) == PWR_FLAG_PVDO))
107 |
108 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
109 | /**
110 | * @}
111 | */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /** @defgroup PWR_Exported_Macros
118 | * @{
119 | */
120 |
121 | /**
122 | * @}
123 | */
124 |
125 | /** @defgroup PWR_Exported_Functions
126 | * @{
127 | */
128 |
129 | void PWR_DeInit(void);
130 | void PWR_BackupAccessCmd(FunctionalState NewState);
131 | void PWR_PVDCmd(FunctionalState NewState);
132 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
133 | void PWR_WakeUpPinCmd(FunctionalState NewState);
134 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
135 | void PWR_EnterSTANDBYMode(void);
136 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
137 | void PWR_ClearFlag(uint32_t PWR_FLAG);
138 |
139 | #ifdef __cplusplus
140 | }
141 | #endif
142 |
143 | #endif /* __STM32F10x_PWR_H */
144 | /**
145 | * @}
146 | */
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /**
153 | * @}
154 | */
155 |
156 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
157 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_rtc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the RTC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_RTC_H
25 | #define __STM32F10x_RTC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup RTC
39 | * @{
40 | */
41 |
42 | /** @defgroup RTC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup RTC_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup RTC_interrupts_define
55 | * @{
56 | */
57 |
58 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
59 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
60 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
61 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
62 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
63 | ((IT) == RTC_IT_SEC))
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup RTC_interrupts_flags
69 | * @{
70 | */
71 |
72 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
73 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
74 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
75 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
76 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
77 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
78 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
79 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
80 | ((FLAG) == RTC_FLAG_SEC))
81 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /**
88 | * @}
89 | */
90 |
91 | /** @defgroup RTC_Exported_Macros
92 | * @{
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | /** @defgroup RTC_Exported_Functions
100 | * @{
101 | */
102 |
103 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
104 | void RTC_EnterConfigMode(void);
105 | void RTC_ExitConfigMode(void);
106 | uint32_t RTC_GetCounter(void);
107 | void RTC_SetCounter(uint32_t CounterValue);
108 | void RTC_SetPrescaler(uint32_t PrescalerValue);
109 | void RTC_SetAlarm(uint32_t AlarmValue);
110 | uint32_t RTC_GetDivider(void);
111 | void RTC_WaitForLastTask(void);
112 | void RTC_WaitForSynchro(void);
113 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
114 | void RTC_ClearFlag(uint16_t RTC_FLAG);
115 | ITStatus RTC_GetITStatus(uint16_t RTC_IT);
116 | void RTC_ClearITPendingBit(uint16_t RTC_IT);
117 |
118 | #ifdef __cplusplus
119 | }
120 | #endif
121 |
122 | #endif /* __STM32F10x_RTC_H */
123 | /**
124 | * @}
125 | */
126 |
127 | /**
128 | * @}
129 | */
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
136 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_usart.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the USART
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_USART_H
25 | #define __STM32F10x_USART_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup USART
39 | * @{
40 | */
41 |
42 | /** @defgroup USART_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief USART Init Structure definition
48 | */
49 |
50 | typedef struct
51 | {
52 | uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
53 | The baud rate is computed using the following formula:
54 | - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
55 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
56 |
57 | uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
58 | This parameter can be a value of @ref USART_Word_Length */
59 |
60 | uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
61 | This parameter can be a value of @ref USART_Stop_Bits */
62 |
63 | uint16_t USART_Parity; /*!< Specifies the parity mode.
64 | This parameter can be a value of @ref USART_Parity
65 | @note When parity is enabled, the computed parity is inserted
66 | at the MSB position of the transmitted data (9th bit when
67 | the word length is set to 9 data bits; 8th bit when the
68 | word length is set to 8 data bits). */
69 |
70 | uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
71 | This parameter can be a value of @ref USART_Mode */
72 |
73 | uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
74 | or disabled.
75 | This parameter can be a value of @ref USART_Hardware_Flow_Control */
76 | } USART_InitTypeDef;
77 |
78 | /**
79 | * @brief USART Clock Init Structure definition
80 | */
81 |
82 | typedef struct
83 | {
84 |
85 | uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
86 | This parameter can be a value of @ref USART_Clock */
87 |
88 | uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
89 | This parameter can be a value of @ref USART_Clock_Polarity */
90 |
91 | uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
92 | This parameter can be a value of @ref USART_Clock_Phase */
93 |
94 | uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
95 | data bit (MSB) has to be output on the SCLK pin in synchronous mode.
96 | This parameter can be a value of @ref USART_Last_Bit */
97 | } USART_ClockInitTypeDef;
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup USART_Exported_Constants
104 | * @{
105 | */
106 |
107 | #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
108 | ((PERIPH) == USART2) || \
109 | ((PERIPH) == USART3) || \
110 | ((PERIPH) == UART4) || \
111 | ((PERIPH) == UART5))
112 |
113 | #define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
114 | ((PERIPH) == USART2) || \
115 | ((PERIPH) == USART3))
116 |
117 | #define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
118 | ((PERIPH) == USART2) || \
119 | ((PERIPH) == USART3) || \
120 | ((PERIPH) == UART4))
121 | /** @defgroup USART_Word_Length
122 | * @{
123 | */
124 |
125 | #define USART_WordLength_8b ((uint16_t)0x0000)
126 | #define USART_WordLength_9b ((uint16_t)0x1000)
127 |
128 | #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
129 | ((LENGTH) == USART_WordLength_9b))
130 | /**
131 | * @}
132 | */
133 |
134 | /** @defgroup USART_Stop_Bits
135 | * @{
136 | */
137 |
138 | #define USART_StopBits_1 ((uint16_t)0x0000)
139 | #define USART_StopBits_0_5 ((uint16_t)0x1000)
140 | #define USART_StopBits_2 ((uint16_t)0x2000)
141 | #define USART_StopBits_1_5 ((uint16_t)0x3000)
142 | #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
143 | ((STOPBITS) == USART_StopBits_0_5) || \
144 | ((STOPBITS) == USART_StopBits_2) || \
145 | ((STOPBITS) == USART_StopBits_1_5))
146 | /**
147 | * @}
148 | */
149 |
150 | /** @defgroup USART_Parity
151 | * @{
152 | */
153 |
154 | #define USART_Parity_No ((uint16_t)0x0000)
155 | #define USART_Parity_Even ((uint16_t)0x0400)
156 | #define USART_Parity_Odd ((uint16_t)0x0600)
157 | #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
158 | ((PARITY) == USART_Parity_Even) || \
159 | ((PARITY) == USART_Parity_Odd))
160 | /**
161 | * @}
162 | */
163 |
164 | /** @defgroup USART_Mode
165 | * @{
166 | */
167 |
168 | #define USART_Mode_Rx ((uint16_t)0x0004)
169 | #define USART_Mode_Tx ((uint16_t)0x0008)
170 | #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
171 | /**
172 | * @}
173 | */
174 |
175 | /** @defgroup USART_Hardware_Flow_Control
176 | * @{
177 | */
178 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000)
179 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
180 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
181 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
182 | #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
183 | (((CONTROL) == USART_HardwareFlowControl_None) || \
184 | ((CONTROL) == USART_HardwareFlowControl_RTS) || \
185 | ((CONTROL) == USART_HardwareFlowControl_CTS) || \
186 | ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
187 | /**
188 | * @}
189 | */
190 |
191 | /** @defgroup USART_Clock
192 | * @{
193 | */
194 | #define USART_Clock_Disable ((uint16_t)0x0000)
195 | #define USART_Clock_Enable ((uint16_t)0x0800)
196 | #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
197 | ((CLOCK) == USART_Clock_Enable))
198 | /**
199 | * @}
200 | */
201 |
202 | /** @defgroup USART_Clock_Polarity
203 | * @{
204 | */
205 |
206 | #define USART_CPOL_Low ((uint16_t)0x0000)
207 | #define USART_CPOL_High ((uint16_t)0x0400)
208 | #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
209 |
210 | /**
211 | * @}
212 | */
213 |
214 | /** @defgroup USART_Clock_Phase
215 | * @{
216 | */
217 |
218 | #define USART_CPHA_1Edge ((uint16_t)0x0000)
219 | #define USART_CPHA_2Edge ((uint16_t)0x0200)
220 | #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
221 |
222 | /**
223 | * @}
224 | */
225 |
226 | /** @defgroup USART_Last_Bit
227 | * @{
228 | */
229 |
230 | #define USART_LastBit_Disable ((uint16_t)0x0000)
231 | #define USART_LastBit_Enable ((uint16_t)0x0100)
232 | #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
233 | ((LASTBIT) == USART_LastBit_Enable))
234 | /**
235 | * @}
236 | */
237 |
238 | /** @defgroup USART_Interrupt_definition
239 | * @{
240 | */
241 |
242 | #define USART_IT_PE ((uint16_t)0x0028)
243 | #define USART_IT_TXE ((uint16_t)0x0727)
244 | #define USART_IT_TC ((uint16_t)0x0626)
245 | #define USART_IT_RXNE ((uint16_t)0x0525)
246 | #define USART_IT_IDLE ((uint16_t)0x0424)
247 | #define USART_IT_LBD ((uint16_t)0x0846)
248 | #define USART_IT_CTS ((uint16_t)0x096A)
249 | #define USART_IT_ERR ((uint16_t)0x0060)
250 | #define USART_IT_ORE ((uint16_t)0x0360)
251 | #define USART_IT_NE ((uint16_t)0x0260)
252 | #define USART_IT_FE ((uint16_t)0x0160)
253 | #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
254 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
255 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
256 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
257 | #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
258 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
259 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
260 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
261 | ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
262 | #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
263 | ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
264 | /**
265 | * @}
266 | */
267 |
268 | /** @defgroup USART_DMA_Requests
269 | * @{
270 | */
271 |
272 | #define USART_DMAReq_Tx ((uint16_t)0x0080)
273 | #define USART_DMAReq_Rx ((uint16_t)0x0040)
274 | #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
275 |
276 | /**
277 | * @}
278 | */
279 |
280 | /** @defgroup USART_WakeUp_methods
281 | * @{
282 | */
283 |
284 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000)
285 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800)
286 | #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
287 | ((WAKEUP) == USART_WakeUp_AddressMark))
288 | /**
289 | * @}
290 | */
291 |
292 | /** @defgroup USART_LIN_Break_Detection_Length
293 | * @{
294 | */
295 |
296 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
297 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
298 | #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
299 | (((LENGTH) == USART_LINBreakDetectLength_10b) || \
300 | ((LENGTH) == USART_LINBreakDetectLength_11b))
301 | /**
302 | * @}
303 | */
304 |
305 | /** @defgroup USART_IrDA_Low_Power
306 | * @{
307 | */
308 |
309 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004)
310 | #define USART_IrDAMode_Normal ((uint16_t)0x0000)
311 | #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
312 | ((MODE) == USART_IrDAMode_Normal))
313 | /**
314 | * @}
315 | */
316 |
317 | /** @defgroup USART_Flags
318 | * @{
319 | */
320 |
321 | #define USART_FLAG_CTS ((uint16_t)0x0200)
322 | #define USART_FLAG_LBD ((uint16_t)0x0100)
323 | #define USART_FLAG_TXE ((uint16_t)0x0080)
324 | #define USART_FLAG_TC ((uint16_t)0x0040)
325 | #define USART_FLAG_RXNE ((uint16_t)0x0020)
326 | #define USART_FLAG_IDLE ((uint16_t)0x0010)
327 | #define USART_FLAG_ORE ((uint16_t)0x0008)
328 | #define USART_FLAG_NE ((uint16_t)0x0004)
329 | #define USART_FLAG_FE ((uint16_t)0x0002)
330 | #define USART_FLAG_PE ((uint16_t)0x0001)
331 | #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
332 | ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
333 | ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
334 | ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
335 | ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
336 |
337 | #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
338 | #define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
339 | ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
340 | || ((USART_FLAG) != USART_FLAG_CTS))
341 | #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
342 | #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
343 | #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
344 |
345 | /**
346 | * @}
347 | */
348 |
349 | /**
350 | * @}
351 | */
352 |
353 | /** @defgroup USART_Exported_Macros
354 | * @{
355 | */
356 |
357 | /**
358 | * @}
359 | */
360 |
361 | /** @defgroup USART_Exported_Functions
362 | * @{
363 | */
364 |
365 | void USART_DeInit(USART_TypeDef* USARTx);
366 | void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
367 | void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
368 | void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
369 | void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
370 | void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
371 | void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
372 | void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
373 | void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
374 | void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
375 | void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
376 | void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
377 | void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
378 | void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
379 | uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
380 | void USART_SendBreak(USART_TypeDef* USARTx);
381 | void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
382 | void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
383 | void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
384 | void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
385 | void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
386 | void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
387 | void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
388 | void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
389 | void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
390 | FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
391 | void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
392 | ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
393 | void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
394 |
395 | #ifdef __cplusplus
396 | }
397 | #endif
398 |
399 | #endif /* __STM32F10x_USART_H */
400 | /**
401 | * @}
402 | */
403 |
404 | /**
405 | * @}
406 | */
407 |
408 | /**
409 | * @}
410 | */
411 |
412 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
413 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the WWDG firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_WWDG_H
25 | #define __STM32F10x_WWDG_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup WWDG
39 | * @{
40 | */
41 |
42 | /** @defgroup WWDG_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup WWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup WWDG_Prescaler
55 | * @{
56 | */
57 |
58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
63 | ((PRESCALER) == WWDG_Prescaler_2) || \
64 | ((PRESCALER) == WWDG_Prescaler_4) || \
65 | ((PRESCALER) == WWDG_Prescaler_8))
66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /** @defgroup WWDG_Exported_Macros
78 | * @{
79 | */
80 | /**
81 | * @}
82 | */
83 |
84 | /** @defgroup WWDG_Exported_Functions
85 | * @{
86 | */
87 |
88 | void WWDG_DeInit(void);
89 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
90 | void WWDG_SetWindowValue(uint8_t WindowValue);
91 | void WWDG_EnableIT(void);
92 | void WWDG_SetCounter(uint8_t Counter);
93 | void WWDG_Enable(uint8_t Counter);
94 | FlagStatus WWDG_GetFlagStatus(void);
95 | void WWDG_ClearFlag(void);
96 |
97 | #ifdef __cplusplus
98 | }
99 | #endif
100 |
101 | #endif /* __STM32F10x_WWDG_H */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
116 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/src/misc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file misc.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the miscellaneous firmware functions (add-on
8 | * to CMSIS functions).
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Includes ------------------------------------------------------------------*/
24 | #include "misc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup MISC
31 | * @brief MISC driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup MISC_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup MISC_Private_Defines
44 | * @{
45 | */
46 |
47 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
48 | /**
49 | * @}
50 | */
51 |
52 | /** @defgroup MISC_Private_Macros
53 | * @{
54 | */
55 |
56 | /**
57 | * @}
58 | */
59 |
60 | /** @defgroup MISC_Private_Variables
61 | * @{
62 | */
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup MISC_Private_FunctionPrototypes
69 | * @{
70 | */
71 |
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup MISC_Private_Functions
77 | * @{
78 | */
79 |
80 | /**
81 | * @brief Configures the priority grouping: pre-emption priority and subpriority.
82 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
83 | * This parameter can be one of the following values:
84 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
85 | * 4 bits for subpriority
86 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
87 | * 3 bits for subpriority
88 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
89 | * 2 bits for subpriority
90 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
91 | * 1 bits for subpriority
92 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
93 | * 0 bits for subpriority
94 | * @retval None
95 | */
96 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
97 | {
98 | /* Check the parameters */
99 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
100 |
101 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
102 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
103 | }
104 |
105 | /**
106 | * @brief Initializes the NVIC peripheral according to the specified
107 | * parameters in the NVIC_InitStruct.
108 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
109 | * the configuration information for the specified NVIC peripheral.
110 | * @retval None
111 | */
112 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
113 | {
114 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
115 |
116 | /* Check the parameters */
117 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
118 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
119 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
120 |
121 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
122 | {
123 | /* Compute the Corresponding IRQ Priority --------------------------------*/
124 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
125 | tmppre = (0x4 - tmppriority);
126 | tmpsub = tmpsub >> tmppriority;
127 |
128 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
129 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
130 | tmppriority = tmppriority << 0x04;
131 |
132 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
133 |
134 | /* Enable the Selected IRQ Channels --------------------------------------*/
135 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
136 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
137 | }
138 | else
139 | {
140 | /* Disable the Selected IRQ Channels -------------------------------------*/
141 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
143 | }
144 | }
145 |
146 | /**
147 | * @brief Sets the vector table location and Offset.
148 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
149 | * This parameter can be one of the following values:
150 | * @arg NVIC_VectTab_RAM
151 | * @arg NVIC_VectTab_FLASH
152 | * @param Offset: Vector Table base offset field. This value must be a multiple
153 | * of 0x200.
154 | * @retval None
155 | */
156 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
157 | {
158 | /* Check the parameters */
159 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
160 | assert_param(IS_NVIC_OFFSET(Offset));
161 |
162 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
163 | }
164 |
165 | /**
166 | * @brief Selects the condition for the system to enter low power mode.
167 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
168 | * This parameter can be one of the following values:
169 | * @arg NVIC_LP_SEVONPEND
170 | * @arg NVIC_LP_SLEEPDEEP
171 | * @arg NVIC_LP_SLEEPONEXIT
172 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
173 | * @retval None
174 | */
175 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
176 | {
177 | /* Check the parameters */
178 | assert_param(IS_NVIC_LP(LowPowerMode));
179 | assert_param(IS_FUNCTIONAL_STATE(NewState));
180 |
181 | if (NewState != DISABLE)
182 | {
183 | SCB->SCR |= LowPowerMode;
184 | }
185 | else
186 | {
187 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
188 | }
189 | }
190 |
191 | /**
192 | * @brief Configures the SysTick clock source.
193 | * @param SysTick_CLKSource: specifies the SysTick clock source.
194 | * This parameter can be one of the following values:
195 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
196 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
197 | * @retval None
198 | */
199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
200 | {
201 | /* Check the parameters */
202 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
203 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
204 | {
205 | SysTick->CTRL |= SysTick_CLKSource_HCLK;
206 | }
207 | else
208 | {
209 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
210 | }
211 | }
212 |
213 | /**
214 | * @}
215 | */
216 |
217 | /**
218 | * @}
219 | */
220 |
221 | /**
222 | * @}
223 | */
224 |
225 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
226 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_bkp.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the BKP firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_bkp.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup BKP
31 | * @brief BKP driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup BKP_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup BKP_Private_Defines
44 | * @{
45 | */
46 |
47 | /* ------------ BKP registers bit address in the alias region --------------- */
48 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
49 |
50 | /* --- CR Register ----*/
51 |
52 | /* Alias word address of TPAL bit */
53 | #define CR_OFFSET (BKP_OFFSET + 0x30)
54 | #define TPAL_BitNumber 0x01
55 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
56 |
57 | /* Alias word address of TPE bit */
58 | #define TPE_BitNumber 0x00
59 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
60 |
61 | /* --- CSR Register ---*/
62 |
63 | /* Alias word address of TPIE bit */
64 | #define CSR_OFFSET (BKP_OFFSET + 0x34)
65 | #define TPIE_BitNumber 0x02
66 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
67 |
68 | /* Alias word address of TIF bit */
69 | #define TIF_BitNumber 0x09
70 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
71 |
72 | /* Alias word address of TEF bit */
73 | #define TEF_BitNumber 0x08
74 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
75 |
76 | /* ---------------------- BKP registers bit mask ------------------------ */
77 |
78 | /* RTCCR register bit mask */
79 | #define RTCCR_CAL_MASK ((uint16_t)0xFF80)
80 | #define RTCCR_MASK ((uint16_t)0xFC7F)
81 |
82 | /**
83 | * @}
84 | */
85 |
86 |
87 | /** @defgroup BKP_Private_Macros
88 | * @{
89 | */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup BKP_Private_Variables
96 | * @{
97 | */
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup BKP_Private_FunctionPrototypes
104 | * @{
105 | */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /** @defgroup BKP_Private_Functions
112 | * @{
113 | */
114 |
115 | /**
116 | * @brief Deinitializes the BKP peripheral registers to their default reset values.
117 | * @param None
118 | * @retval None
119 | */
120 | void BKP_DeInit(void)
121 | {
122 | RCC_BackupResetCmd(ENABLE);
123 | RCC_BackupResetCmd(DISABLE);
124 | }
125 |
126 | /**
127 | * @brief Configures the Tamper Pin active level.
128 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
129 | * This parameter can be one of the following values:
130 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
131 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
132 | * @retval None
133 | */
134 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
135 | {
136 | /* Check the parameters */
137 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
138 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
139 | }
140 |
141 | /**
142 | * @brief Enables or disables the Tamper Pin activation.
143 | * @param NewState: new state of the Tamper Pin activation.
144 | * This parameter can be: ENABLE or DISABLE.
145 | * @retval None
146 | */
147 | void BKP_TamperPinCmd(FunctionalState NewState)
148 | {
149 | /* Check the parameters */
150 | assert_param(IS_FUNCTIONAL_STATE(NewState));
151 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
152 | }
153 |
154 | /**
155 | * @brief Enables or disables the Tamper Pin Interrupt.
156 | * @param NewState: new state of the Tamper Pin Interrupt.
157 | * This parameter can be: ENABLE or DISABLE.
158 | * @retval None
159 | */
160 | void BKP_ITConfig(FunctionalState NewState)
161 | {
162 | /* Check the parameters */
163 | assert_param(IS_FUNCTIONAL_STATE(NewState));
164 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
165 | }
166 |
167 | /**
168 | * @brief Select the RTC output source to output on the Tamper pin.
169 | * @param BKP_RTCOutputSource: specifies the RTC output source.
170 | * This parameter can be one of the following values:
171 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
172 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
173 | * divided by 64 on the Tamper pin.
174 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
175 | * the Tamper pin.
176 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
177 | * the Tamper pin.
178 | * @retval None
179 | */
180 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
181 | {
182 | uint16_t tmpreg = 0;
183 | /* Check the parameters */
184 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
185 | tmpreg = BKP->RTCCR;
186 | /* Clear CCO, ASOE and ASOS bits */
187 | tmpreg &= RTCCR_MASK;
188 |
189 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
190 | tmpreg |= BKP_RTCOutputSource;
191 | /* Store the new value */
192 | BKP->RTCCR = tmpreg;
193 | }
194 |
195 | /**
196 | * @brief Sets RTC Clock Calibration value.
197 | * @param CalibrationValue: specifies the RTC Clock Calibration value.
198 | * This parameter must be a number between 0 and 0x7F.
199 | * @retval None
200 | */
201 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
202 | {
203 | uint16_t tmpreg = 0;
204 | /* Check the parameters */
205 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
206 | tmpreg = BKP->RTCCR;
207 | /* Clear CAL[6:0] bits */
208 | tmpreg &= RTCCR_CAL_MASK;
209 | /* Set CAL[6:0] bits according to CalibrationValue value */
210 | tmpreg |= CalibrationValue;
211 | /* Store the new value */
212 | BKP->RTCCR = tmpreg;
213 | }
214 |
215 | /**
216 | * @brief Writes user data to the specified Data Backup Register.
217 | * @param BKP_DR: specifies the Data Backup Register.
218 | * This parameter can be BKP_DRx where x:[1, 42]
219 | * @param Data: data to write
220 | * @retval None
221 | */
222 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
223 | {
224 | __IO uint32_t tmp = 0;
225 |
226 | /* Check the parameters */
227 | assert_param(IS_BKP_DR(BKP_DR));
228 |
229 | tmp = (uint32_t)BKP_BASE;
230 | tmp += BKP_DR;
231 |
232 | *(__IO uint32_t *) tmp = Data;
233 | }
234 |
235 | /**
236 | * @brief Reads data from the specified Data Backup Register.
237 | * @param BKP_DR: specifies the Data Backup Register.
238 | * This parameter can be BKP_DRx where x:[1, 42]
239 | * @retval The content of the specified Data Backup Register
240 | */
241 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
242 | {
243 | __IO uint32_t tmp = 0;
244 |
245 | /* Check the parameters */
246 | assert_param(IS_BKP_DR(BKP_DR));
247 |
248 | tmp = (uint32_t)BKP_BASE;
249 | tmp += BKP_DR;
250 |
251 | return (*(__IO uint16_t *) tmp);
252 | }
253 |
254 | /**
255 | * @brief Checks whether the Tamper Pin Event flag is set or not.
256 | * @param None
257 | * @retval The new state of the Tamper Pin Event flag (SET or RESET).
258 | */
259 | FlagStatus BKP_GetFlagStatus(void)
260 | {
261 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
262 | }
263 |
264 | /**
265 | * @brief Clears Tamper Pin Event pending flag.
266 | * @param None
267 | * @retval None
268 | */
269 | void BKP_ClearFlag(void)
270 | {
271 | /* Set CTE bit to clear Tamper Pin Event flag */
272 | BKP->CSR |= BKP_CSR_CTE;
273 | }
274 |
275 | /**
276 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
277 | * @param None
278 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
279 | */
280 | ITStatus BKP_GetITStatus(void)
281 | {
282 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
283 | }
284 |
285 | /**
286 | * @brief Clears Tamper Pin Interrupt pending bit.
287 | * @param None
288 | * @retval None
289 | */
290 | void BKP_ClearITPendingBit(void)
291 | {
292 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
293 | BKP->CSR |= BKP_CSR_CTI;
294 | }
295 |
296 | /**
297 | * @}
298 | */
299 |
300 | /**
301 | * @}
302 | */
303 |
304 | /**
305 | * @}
306 | */
307 |
308 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
309 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_cec.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the CEC firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_cec.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup CEC
31 | * @brief CEC driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup CEC_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 |
44 | /** @defgroup CEC_Private_Defines
45 | * @{
46 | */
47 |
48 | /* ------------ CEC registers bit address in the alias region ----------- */
49 | #define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
50 |
51 | /* --- CFGR Register ---*/
52 |
53 | /* Alias word address of PE bit */
54 | #define CFGR_OFFSET (CEC_OFFSET + 0x00)
55 | #define PE_BitNumber 0x00
56 | #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
57 |
58 | /* Alias word address of IE bit */
59 | #define IE_BitNumber 0x01
60 | #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
61 |
62 | /* --- CSR Register ---*/
63 |
64 | /* Alias word address of TSOM bit */
65 | #define CSR_OFFSET (CEC_OFFSET + 0x10)
66 | #define TSOM_BitNumber 0x00
67 | #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
68 |
69 | /* Alias word address of TEOM bit */
70 | #define TEOM_BitNumber 0x01
71 | #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
72 |
73 | #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
74 | #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
75 |
76 | /**
77 | * @}
78 | */
79 |
80 |
81 | /** @defgroup CEC_Private_Macros
82 | * @{
83 | */
84 |
85 | /**
86 | * @}
87 | */
88 |
89 |
90 | /** @defgroup CEC_Private_Variables
91 | * @{
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 |
99 | /** @defgroup CEC_Private_FunctionPrototypes
100 | * @{
101 | */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 |
108 | /** @defgroup CEC_Private_Functions
109 | * @{
110 | */
111 |
112 | /**
113 | * @brief Deinitializes the CEC peripheral registers to their default reset
114 | * values.
115 | * @param None
116 | * @retval None
117 | */
118 | void CEC_DeInit(void)
119 | {
120 | /* Enable CEC reset state */
121 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
122 | /* Release CEC from reset state */
123 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
124 | }
125 |
126 |
127 | /**
128 | * @brief Initializes the CEC peripheral according to the specified
129 | * parameters in the CEC_InitStruct.
130 | * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
131 | * contains the configuration information for the specified
132 | * CEC peripheral.
133 | * @retval None
134 | */
135 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
136 | {
137 | uint16_t tmpreg = 0;
138 |
139 | /* Check the parameters */
140 | assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
141 | assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
142 |
143 | /*---------------------------- CEC CFGR Configuration -----------------*/
144 | /* Get the CEC CFGR value */
145 | tmpreg = CEC->CFGR;
146 |
147 | /* Clear BTEM and BPEM bits */
148 | tmpreg &= CFGR_CLEAR_Mask;
149 |
150 | /* Configure CEC: Bit Timing Error and Bit Period Error */
151 | tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
152 |
153 | /* Write to CEC CFGR register*/
154 | CEC->CFGR = tmpreg;
155 |
156 | }
157 |
158 | /**
159 | * @brief Enables or disables the specified CEC peripheral.
160 | * @param NewState: new state of the CEC peripheral.
161 | * This parameter can be: ENABLE or DISABLE.
162 | * @retval None
163 | */
164 | void CEC_Cmd(FunctionalState NewState)
165 | {
166 | /* Check the parameters */
167 | assert_param(IS_FUNCTIONAL_STATE(NewState));
168 |
169 | *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
170 |
171 | if(NewState == DISABLE)
172 | {
173 | /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
174 | while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
175 | {
176 | }
177 | }
178 | }
179 |
180 | /**
181 | * @brief Enables or disables the CEC interrupt.
182 | * @param NewState: new state of the CEC interrupt.
183 | * This parameter can be: ENABLE or DISABLE.
184 | * @retval None
185 | */
186 | void CEC_ITConfig(FunctionalState NewState)
187 | {
188 | /* Check the parameters */
189 | assert_param(IS_FUNCTIONAL_STATE(NewState));
190 |
191 | *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
192 | }
193 |
194 | /**
195 | * @brief Defines the Own Address of the CEC device.
196 | * @param CEC_OwnAddress: The CEC own address
197 | * @retval None
198 | */
199 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
200 | {
201 | /* Check the parameters */
202 | assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
203 |
204 | /* Set the CEC own address */
205 | CEC->OAR = CEC_OwnAddress;
206 | }
207 |
208 | /**
209 | * @brief Sets the CEC prescaler value.
210 | * @param CEC_Prescaler: CEC prescaler new value
211 | * @retval None
212 | */
213 | void CEC_SetPrescaler(uint16_t CEC_Prescaler)
214 | {
215 | /* Check the parameters */
216 | assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
217 |
218 | /* Set the Prescaler value*/
219 | CEC->PRES = CEC_Prescaler;
220 | }
221 |
222 | /**
223 | * @brief Transmits single data through the CEC peripheral.
224 | * @param Data: the data to transmit.
225 | * @retval None
226 | */
227 | void CEC_SendDataByte(uint8_t Data)
228 | {
229 | /* Transmit Data */
230 | CEC->TXD = Data ;
231 | }
232 |
233 |
234 | /**
235 | * @brief Returns the most recent received data by the CEC peripheral.
236 | * @param None
237 | * @retval The received data.
238 | */
239 | uint8_t CEC_ReceiveDataByte(void)
240 | {
241 | /* Receive Data */
242 | return (uint8_t)(CEC->RXD);
243 | }
244 |
245 | /**
246 | * @brief Starts a new message.
247 | * @param None
248 | * @retval None
249 | */
250 | void CEC_StartOfMessage(void)
251 | {
252 | /* Starts of new message */
253 | *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
254 | }
255 |
256 | /**
257 | * @brief Transmits message with or without an EOM bit.
258 | * @param NewState: new state of the CEC Tx End Of Message.
259 | * This parameter can be: ENABLE or DISABLE.
260 | * @retval None
261 | */
262 | void CEC_EndOfMessageCmd(FunctionalState NewState)
263 | {
264 | /* Check the parameters */
265 | assert_param(IS_FUNCTIONAL_STATE(NewState));
266 |
267 | /* The data byte will be transmitted with or without an EOM bit*/
268 | *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
269 | }
270 |
271 | /**
272 | * @brief Gets the CEC flag status
273 | * @param CEC_FLAG: specifies the CEC flag to check.
274 | * This parameter can be one of the following values:
275 | * @arg CEC_FLAG_BTE: Bit Timing Error
276 | * @arg CEC_FLAG_BPE: Bit Period Error
277 | * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
278 | * @arg CEC_FLAG_SBE: Start Bit Error
279 | * @arg CEC_FLAG_ACKE: Block Acknowledge Error
280 | * @arg CEC_FLAG_LINE: Line Error
281 | * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
282 | * @arg CEC_FLAG_TEOM: Tx End Of Message
283 | * @arg CEC_FLAG_TERR: Tx Error
284 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
285 | * @arg CEC_FLAG_RSOM: Rx Start Of Message
286 | * @arg CEC_FLAG_REOM: Rx End Of Message
287 | * @arg CEC_FLAG_RERR: Rx Error
288 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
289 | * @retval The new state of CEC_FLAG (SET or RESET)
290 | */
291 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
292 | {
293 | FlagStatus bitstatus = RESET;
294 | uint32_t cecreg = 0, cecbase = 0;
295 |
296 | /* Check the parameters */
297 | assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
298 |
299 | /* Get the CEC peripheral base address */
300 | cecbase = (uint32_t)(CEC_BASE);
301 |
302 | /* Read flag register index */
303 | cecreg = CEC_FLAG >> 28;
304 |
305 | /* Get bit[23:0] of the flag */
306 | CEC_FLAG &= FLAG_Mask;
307 |
308 | if(cecreg != 0)
309 | {
310 | /* Flag in CEC ESR Register */
311 | CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
312 |
313 | /* Get the CEC ESR register address */
314 | cecbase += 0xC;
315 | }
316 | else
317 | {
318 | /* Get the CEC CSR register address */
319 | cecbase += 0x10;
320 | }
321 |
322 | if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
323 | {
324 | /* CEC_FLAG is set */
325 | bitstatus = SET;
326 | }
327 | else
328 | {
329 | /* CEC_FLAG is reset */
330 | bitstatus = RESET;
331 | }
332 |
333 | /* Return the CEC_FLAG status */
334 | return bitstatus;
335 | }
336 |
337 | /**
338 | * @brief Clears the CEC's pending flags.
339 | * @param CEC_FLAG: specifies the flag to clear.
340 | * This parameter can be any combination of the following values:
341 | * @arg CEC_FLAG_TERR: Tx Error
342 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
343 | * @arg CEC_FLAG_RSOM: Rx Start Of Message
344 | * @arg CEC_FLAG_REOM: Rx End Of Message
345 | * @arg CEC_FLAG_RERR: Rx Error
346 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
347 | * @retval None
348 | */
349 | void CEC_ClearFlag(uint32_t CEC_FLAG)
350 | {
351 | uint32_t tmp = 0x0;
352 |
353 | /* Check the parameters */
354 | assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
355 |
356 | tmp = CEC->CSR & 0x2;
357 |
358 | /* Clear the selected CEC flags */
359 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
360 | }
361 |
362 | /**
363 | * @brief Checks whether the specified CEC interrupt has occurred or not.
364 | * @param CEC_IT: specifies the CEC interrupt source to check.
365 | * This parameter can be one of the following values:
366 | * @arg CEC_IT_TERR: Tx Error
367 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished
368 | * @arg CEC_IT_RERR: Rx Error
369 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished
370 | * @retval The new state of CEC_IT (SET or RESET).
371 | */
372 | ITStatus CEC_GetITStatus(uint8_t CEC_IT)
373 | {
374 | ITStatus bitstatus = RESET;
375 | uint32_t enablestatus = 0;
376 |
377 | /* Check the parameters */
378 | assert_param(IS_CEC_GET_IT(CEC_IT));
379 |
380 | /* Get the CEC IT enable bit status */
381 | enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
382 |
383 | /* Check the status of the specified CEC interrupt */
384 | if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
385 | {
386 | /* CEC_IT is set */
387 | bitstatus = SET;
388 | }
389 | else
390 | {
391 | /* CEC_IT is reset */
392 | bitstatus = RESET;
393 | }
394 | /* Return the CEC_IT status */
395 | return bitstatus;
396 | }
397 |
398 | /**
399 | * @brief Clears the CEC's interrupt pending bits.
400 | * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
401 | * This parameter can be any combination of the following values:
402 | * @arg CEC_IT_TERR: Tx Error
403 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished
404 | * @arg CEC_IT_RERR: Rx Error
405 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished
406 | * @retval None
407 | */
408 | void CEC_ClearITPendingBit(uint16_t CEC_IT)
409 | {
410 | uint32_t tmp = 0x0;
411 |
412 | /* Check the parameters */
413 | assert_param(IS_CEC_GET_IT(CEC_IT));
414 |
415 | tmp = CEC->CSR & 0x2;
416 |
417 | /* Clear the selected CEC interrupt pending bits */
418 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
419 | }
420 |
421 | /**
422 | * @}
423 | */
424 |
425 | /**
426 | * @}
427 | */
428 |
429 | /**
430 | * @}
431 | */
432 |
433 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
434 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the CRC firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_crc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup CRC
30 | * @brief CRC driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup CRC_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup CRC_Private_Defines
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup CRC_Private_Macros
51 | * @{
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup CRC_Private_Variables
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup CRC_Private_FunctionPrototypes
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup CRC_Private_Functions
75 | * @{
76 | */
77 |
78 | /**
79 | * @brief Resets the CRC Data register (DR).
80 | * @param None
81 | * @retval None
82 | */
83 | void CRC_ResetDR(void)
84 | {
85 | /* Reset CRC generator */
86 | CRC->CR = CRC_CR_RESET;
87 | }
88 |
89 | /**
90 | * @brief Computes the 32-bit CRC of a given data word(32-bit).
91 | * @param Data: data word(32-bit) to compute its CRC
92 | * @retval 32-bit CRC
93 | */
94 | uint32_t CRC_CalcCRC(uint32_t Data)
95 | {
96 | CRC->DR = Data;
97 |
98 | return (CRC->DR);
99 | }
100 |
101 | /**
102 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
103 | * @param pBuffer: pointer to the buffer containing the data to be computed
104 | * @param BufferLength: length of the buffer to be computed
105 | * @retval 32-bit CRC
106 | */
107 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
108 | {
109 | uint32_t index = 0;
110 |
111 | for(index = 0; index < BufferLength; index++)
112 | {
113 | CRC->DR = pBuffer[index];
114 | }
115 | return (CRC->DR);
116 | }
117 |
118 | /**
119 | * @brief Returns the current CRC value.
120 | * @param None
121 | * @retval 32-bit CRC
122 | */
123 | uint32_t CRC_GetCRC(void)
124 | {
125 | return (CRC->DR);
126 | }
127 |
128 | /**
129 | * @brief Stores a 8-bit data in the Independent Data(ID) register.
130 | * @param IDValue: 8-bit value to be stored in the ID register
131 | * @retval None
132 | */
133 | void CRC_SetIDRegister(uint8_t IDValue)
134 | {
135 | CRC->IDR = IDValue;
136 | }
137 |
138 | /**
139 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register
140 | * @param None
141 | * @retval 8-bit value of the ID register
142 | */
143 | uint8_t CRC_GetIDRegister(void)
144 | {
145 | return (CRC->IDR);
146 | }
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /**
153 | * @}
154 | */
155 |
156 | /**
157 | * @}
158 | */
159 |
160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
161 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the DBGMCU firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_dbgmcu.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup DBGMCU
30 | * @brief DBGMCU driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup DBGMCU_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup DBGMCU_Private_Defines
43 | * @{
44 | */
45 |
46 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
47 | /**
48 | * @}
49 | */
50 |
51 | /** @defgroup DBGMCU_Private_Macros
52 | * @{
53 | */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @defgroup DBGMCU_Private_Variables
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup DBGMCU_Private_FunctionPrototypes
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @defgroup DBGMCU_Private_Functions
76 | * @{
77 | */
78 |
79 | /**
80 | * @brief Returns the device revision identifier.
81 | * @param None
82 | * @retval Device revision identifier
83 | */
84 | uint32_t DBGMCU_GetREVID(void)
85 | {
86 | return(DBGMCU->IDCODE >> 16);
87 | }
88 |
89 | /**
90 | * @brief Returns the device identifier.
91 | * @param None
92 | * @retval Device identifier
93 | */
94 | uint32_t DBGMCU_GetDEVID(void)
95 | {
96 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
97 | }
98 |
99 | /**
100 | * @brief Configures the specified peripheral and low power mode behavior
101 | * when the MCU under Debug mode.
102 | * @param DBGMCU_Periph: specifies the peripheral and low power mode.
103 | * This parameter can be any combination of the following values:
104 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
105 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
106 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
107 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
108 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
109 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
110 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
111 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
112 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
113 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
114 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
115 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
116 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
117 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
118 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
119 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
120 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
121 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
122 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
123 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
124 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
125 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
126 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
127 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
128 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
129 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
130 | * @param NewState: new state of the specified peripheral in Debug mode.
131 | * This parameter can be: ENABLE or DISABLE.
132 | * @retval None
133 | */
134 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
135 | {
136 | /* Check the parameters */
137 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
138 | assert_param(IS_FUNCTIONAL_STATE(NewState));
139 |
140 | if (NewState != DISABLE)
141 | {
142 | DBGMCU->CR |= DBGMCU_Periph;
143 | }
144 | else
145 | {
146 | DBGMCU->CR &= ~DBGMCU_Periph;
147 | }
148 | }
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /**
155 | * @}
156 | */
157 |
158 | /**
159 | * @}
160 | */
161 |
162 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
163 |
--------------------------------------------------------------------------------
/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_exti.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the EXTI firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_exti.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup EXTI
30 | * @brief EXTI driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup EXTI_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup EXTI_Private_Defines
43 | * @{
44 | */
45 |
46 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
47 |
48 | /**
49 | * @}
50 | */
51 |
52 | /** @defgroup EXTI_Private_Macros
53 | * @{
54 | */
55 |
56 | /**
57 | * @}
58 | */
59 |
60 | /** @defgroup EXTI_Private_Variables
61 | * @{
62 | */
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup EXTI_Private_FunctionPrototypes
69 | * @{
70 | */
71 |
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup EXTI_Private_Functions
77 | * @{
78 | */
79 |
80 | /**
81 | * @brief Deinitializes the EXTI peripheral registers to their default reset values.
82 | * @param None
83 | * @retval None
84 | */
85 | void EXTI_DeInit(void)
86 | {
87 | EXTI->IMR = 0x00000000;
88 | EXTI->EMR = 0x00000000;
89 | EXTI->RTSR = 0x00000000;
90 | EXTI->FTSR = 0x00000000;
91 | EXTI->PR = 0x000FFFFF;
92 | }
93 |
94 | /**
95 | * @brief Initializes the EXTI peripheral according to the specified
96 | * parameters in the EXTI_InitStruct.
97 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
98 | * that contains the configuration information for the EXTI peripheral.
99 | * @retval None
100 | */
101 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
102 | {
103 | uint32_t tmp = 0;
104 |
105 | /* Check the parameters */
106 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
107 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
108 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
109 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
110 |
111 | tmp = (uint32_t)EXTI_BASE;
112 |
113 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
114 | {
115 | /* Clear EXTI line configuration */
116 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
117 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
118 |
119 | tmp += EXTI_InitStruct->EXTI_Mode;
120 |
121 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
122 |
123 | /* Clear Rising Falling edge configuration */
124 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
125 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
126 |
127 | /* Select the trigger for the selected external interrupts */
128 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
129 | {
130 | /* Rising Falling edge */
131 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
132 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
133 | }
134 | else
135 | {
136 | tmp = (uint32_t)EXTI_BASE;
137 | tmp += EXTI_InitStruct->EXTI_Trigger;
138 |
139 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
140 | }
141 | }
142 | else
143 | {
144 | tmp += EXTI_InitStruct->EXTI_Mode;
145 |
146 | /* Disable the selected external lines */
147 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
148 | }
149 | }
150 |
151 | /**
152 | * @brief Fills each EXTI_InitStruct member with its reset value.
153 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
154 | * be initialized.
155 | * @retval None
156 | */
157 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
158 | {
159 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
160 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
161 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
162 | EXTI_InitStruct->EXTI_LineCmd = DISABLE;
163 | }
164 |
165 | /**
166 | * @brief Generates a Software interrupt.
167 | * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
168 | * This parameter can be any combination of EXTI_Linex where x can be (0..19).
169 | * @retval None
170 | */
171 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
172 | {
173 | /* Check the parameters */
174 | assert_param(IS_EXTI_LINE(EXTI_Line));
175 |
176 | EXTI->SWIER |= EXTI_Line;
177 | }
178 |
179 | /**
180 | * @brief Checks whether the specified EXTI line flag is set or not.
181 | * @param EXTI_Line: specifies the EXTI line flag to check.
182 | * This parameter can be:
183 | * @arg EXTI_Linex: External interrupt line x where x(0..19)
184 | * @retval The new state of EXTI_Line (SET or RESET).
185 | */
186 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
187 | {
188 | FlagStatus bitstatus = RESET;
189 | /* Check the parameters */
190 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
191 |
192 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
193 | {
194 | bitstatus = SET;
195 | }
196 | else
197 | {
198 | bitstatus = RESET;
199 | }
200 | return bitstatus;
201 | }
202 |
203 | /**
204 | * @brief Clears the EXTI's line pending flags.
205 | * @param EXTI_Line: specifies the EXTI lines flags to clear.
206 | * This parameter can be any combination of EXTI_Linex where x can be (0..19).
207 | * @retval None
208 | */
209 | void EXTI_ClearFlag(uint32_t EXTI_Line)
210 | {
211 | /* Check the parameters */
212 | assert_param(IS_EXTI_LINE(EXTI_Line));
213 |
214 | EXTI->PR = EXTI_Line;
215 | }
216 |
217 | /**
218 | * @brief Checks whether the specified EXTI line is asserted or not.
219 | * @param EXTI_Line: specifies the EXTI line to check.
220 | * This parameter can be:
221 | * @arg EXTI_Linex: External interrupt line x where x(0..19)
222 | * @retval The new state of EXTI_Line (SET or RESET).
223 | */
224 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
225 | {
226 | ITStatus bitstatus = RESET;
227 | uint32_t enablestatus = 0;
228 | /* Check the parameters */
229 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
230 |
231 | enablestatus = EXTI->IMR & EXTI_Line;
232 | if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
233 | {
234 | bitstatus = SET;
235 | }
236 | else
237 | {
238 | bitstatus = RESET;
239 | }
240 | return bitstatus;
241 | }
242 |
243 | /**
244 | * @brief Clears the EXTI's line pending bits.
245 | * @param EXTI_Line: specifies the EXTI lines to clear.
246 | * This parameter can be any combination of EXTI_Linex where x can be (0..19).
247 | * @retval None
248 | */
249 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
250 | {
251 | /* Check the parameters */
252 | assert_param(IS_EXTI_LINE(EXTI_Line));
253 |
254 | EXTI->PR = EXTI_Line;
255 | }
256 |
257 | /**
258 | * @}
259 | */
260 |
261 | /**
262 | * @}
263 | */
264 |
265 | /**
266 | * @}
267 | */
268 |
269 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
270 |
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/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c:
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/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c:
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https://raw.githubusercontent.com/bomingfeng/Fx2N/492c286dce868a5dae4615c4156a080a6fdb83df/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
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/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the IWDG firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_iwdg.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup IWDG
30 | * @brief IWDG driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup IWDG_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup IWDG_Private_Defines
43 | * @{
44 | */
45 |
46 | /* ---------------------- IWDG registers bit mask ----------------------------*/
47 |
48 | /* KR register bit mask */
49 | #define KR_KEY_Reload ((uint16_t)0xAAAA)
50 | #define KR_KEY_Enable ((uint16_t)0xCCCC)
51 |
52 | /**
53 | * @}
54 | */
55 |
56 | /** @defgroup IWDG_Private_Macros
57 | * @{
58 | */
59 |
60 | /**
61 | * @}
62 | */
63 |
64 | /** @defgroup IWDG_Private_Variables
65 | * @{
66 | */
67 |
68 | /**
69 | * @}
70 | */
71 |
72 | /** @defgroup IWDG_Private_FunctionPrototypes
73 | * @{
74 | */
75 |
76 | /**
77 | * @}
78 | */
79 |
80 | /** @defgroup IWDG_Private_Functions
81 | * @{
82 | */
83 |
84 | /**
85 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
86 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
87 | * This parameter can be one of the following values:
88 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
89 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
90 | * @retval None
91 | */
92 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
93 | {
94 | /* Check the parameters */
95 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
96 | IWDG->KR = IWDG_WriteAccess;
97 | }
98 |
99 | /**
100 | * @brief Sets IWDG Prescaler value.
101 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
102 | * This parameter can be one of the following values:
103 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
104 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
105 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
106 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
107 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
108 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
109 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
110 | * @retval None
111 | */
112 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
113 | {
114 | /* Check the parameters */
115 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
116 | IWDG->PR = IWDG_Prescaler;
117 | }
118 |
119 | /**
120 | * @brief Sets IWDG Reload value.
121 | * @param Reload: specifies the IWDG Reload value.
122 | * This parameter must be a number between 0 and 0x0FFF.
123 | * @retval None
124 | */
125 | void IWDG_SetReload(uint16_t Reload)
126 | {
127 | /* Check the parameters */
128 | assert_param(IS_IWDG_RELOAD(Reload));
129 | IWDG->RLR = Reload;
130 | }
131 |
132 | /**
133 | * @brief Reloads IWDG counter with value defined in the reload register
134 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
135 | * @param None
136 | * @retval None
137 | */
138 | void IWDG_ReloadCounter(void)
139 | {
140 | IWDG->KR = KR_KEY_Reload;
141 | }
142 |
143 | /**
144 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
145 | * @param None
146 | * @retval None
147 | */
148 | void IWDG_Enable(void)
149 | {
150 | IWDG->KR = KR_KEY_Enable;
151 | }
152 |
153 | /**
154 | * @brief Checks whether the specified IWDG flag is set or not.
155 | * @param IWDG_FLAG: specifies the flag to check.
156 | * This parameter can be one of the following values:
157 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
158 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
159 | * @retval The new state of IWDG_FLAG (SET or RESET).
160 | */
161 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
162 | {
163 | FlagStatus bitstatus = RESET;
164 | /* Check the parameters */
165 | assert_param(IS_IWDG_FLAG(IWDG_FLAG));
166 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
167 | {
168 | bitstatus = SET;
169 | }
170 | else
171 | {
172 | bitstatus = RESET;
173 | }
174 | /* Return the flag status */
175 | return bitstatus;
176 | }
177 |
178 | /**
179 | * @}
180 | */
181 |
182 | /**
183 | * @}
184 | */
185 |
186 | /**
187 | * @}
188 | */
189 |
190 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
191 |
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/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_pwr.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the PWR firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_pwr.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup PWR
31 | * @brief PWR driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup PWR_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup PWR_Private_Defines
44 | * @{
45 | */
46 |
47 | /* --------- PWR registers bit address in the alias region ---------- */
48 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
49 |
50 | /* --- CR Register ---*/
51 |
52 | /* Alias word address of DBP bit */
53 | #define CR_OFFSET (PWR_OFFSET + 0x00)
54 | #define DBP_BitNumber 0x08
55 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
56 |
57 | /* Alias word address of PVDE bit */
58 | #define PVDE_BitNumber 0x04
59 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
60 |
61 | /* --- CSR Register ---*/
62 |
63 | /* Alias word address of EWUP bit */
64 | #define CSR_OFFSET (PWR_OFFSET + 0x04)
65 | #define EWUP_BitNumber 0x08
66 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
67 |
68 | /* ------------------ PWR registers bit mask ------------------------ */
69 |
70 | /* CR register bit mask */
71 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
72 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
73 |
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /** @defgroup PWR_Private_Macros
80 | * @{
81 | */
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /** @defgroup PWR_Private_Variables
88 | * @{
89 | */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup PWR_Private_FunctionPrototypes
96 | * @{
97 | */
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup PWR_Private_Functions
104 | * @{
105 | */
106 |
107 | /**
108 | * @brief Deinitializes the PWR peripheral registers to their default reset values.
109 | * @param None
110 | * @retval None
111 | */
112 | void PWR_DeInit(void)
113 | {
114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
115 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
116 | }
117 |
118 | /**
119 | * @brief Enables or disables access to the RTC and backup registers.
120 | * @param NewState: new state of the access to the RTC and backup registers.
121 | * This parameter can be: ENABLE or DISABLE.
122 | * @retval None
123 | */
124 | void PWR_BackupAccessCmd(FunctionalState NewState)
125 | {
126 | /* Check the parameters */
127 | assert_param(IS_FUNCTIONAL_STATE(NewState));
128 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
129 | }
130 |
131 | /**
132 | * @brief Enables or disables the Power Voltage Detector(PVD).
133 | * @param NewState: new state of the PVD.
134 | * This parameter can be: ENABLE or DISABLE.
135 | * @retval None
136 | */
137 | void PWR_PVDCmd(FunctionalState NewState)
138 | {
139 | /* Check the parameters */
140 | assert_param(IS_FUNCTIONAL_STATE(NewState));
141 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
142 | }
143 |
144 | /**
145 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
146 | * @param PWR_PVDLevel: specifies the PVD detection level
147 | * This parameter can be one of the following values:
148 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
149 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
150 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
151 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
152 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
153 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
154 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
155 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
156 | * @retval None
157 | */
158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
159 | {
160 | uint32_t tmpreg = 0;
161 | /* Check the parameters */
162 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
163 | tmpreg = PWR->CR;
164 | /* Clear PLS[7:5] bits */
165 | tmpreg &= CR_PLS_MASK;
166 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */
167 | tmpreg |= PWR_PVDLevel;
168 | /* Store the new value */
169 | PWR->CR = tmpreg;
170 | }
171 |
172 | /**
173 | * @brief Enables or disables the WakeUp Pin functionality.
174 | * @param NewState: new state of the WakeUp Pin functionality.
175 | * This parameter can be: ENABLE or DISABLE.
176 | * @retval None
177 | */
178 | void PWR_WakeUpPinCmd(FunctionalState NewState)
179 | {
180 | /* Check the parameters */
181 | assert_param(IS_FUNCTIONAL_STATE(NewState));
182 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
183 | }
184 |
185 | /**
186 | * @brief Enters STOP mode.
187 | * @param PWR_Regulator: specifies the regulator state in STOP mode.
188 | * This parameter can be one of the following values:
189 | * @arg PWR_Regulator_ON: STOP mode with regulator ON
190 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
191 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
192 | * This parameter can be one of the following values:
193 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
194 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
195 | * @retval None
196 | */
197 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
198 | {
199 | uint32_t tmpreg = 0;
200 | /* Check the parameters */
201 | assert_param(IS_PWR_REGULATOR(PWR_Regulator));
202 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
203 |
204 | /* Select the regulator state in STOP mode ---------------------------------*/
205 | tmpreg = PWR->CR;
206 | /* Clear PDDS and LPDS bits */
207 | tmpreg &= CR_DS_MASK;
208 | /* Set LPDS bit according to PWR_Regulator value */
209 | tmpreg |= PWR_Regulator;
210 | /* Store the new value */
211 | PWR->CR = tmpreg;
212 | /* Set SLEEPDEEP bit of Cortex System Control Register */
213 | SCB->SCR |= SCB_SCR_SLEEPDEEP;
214 |
215 | /* Select STOP mode entry --------------------------------------------------*/
216 | if(PWR_STOPEntry == PWR_STOPEntry_WFI)
217 | {
218 | /* Request Wait For Interrupt */
219 | __WFI();
220 | }
221 | else
222 | {
223 | /* Request Wait For Event */
224 | __WFE();
225 | }
226 |
227 | /* Reset SLEEPDEEP bit of Cortex System Control Register */
228 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
229 | }
230 |
231 | /**
232 | * @brief Enters STANDBY mode.
233 | * @param None
234 | * @retval None
235 | */
236 | void PWR_EnterSTANDBYMode(void)
237 | {
238 | /* Clear Wake-up flag */
239 | PWR->CR |= PWR_CR_CWUF;
240 | /* Select STANDBY mode */
241 | PWR->CR |= PWR_CR_PDDS;
242 | /* Set SLEEPDEEP bit of Cortex System Control Register */
243 | SCB->SCR |= SCB_SCR_SLEEPDEEP;
244 | /* This option is used to ensure that store operations are completed */
245 | #if defined ( __CC_ARM )
246 | __force_stores();
247 | #endif
248 | /* Request Wait For Interrupt */
249 | __WFI();
250 | }
251 |
252 | /**
253 | * @brief Checks whether the specified PWR flag is set or not.
254 | * @param PWR_FLAG: specifies the flag to check.
255 | * This parameter can be one of the following values:
256 | * @arg PWR_FLAG_WU: Wake Up flag
257 | * @arg PWR_FLAG_SB: StandBy flag
258 | * @arg PWR_FLAG_PVDO: PVD Output
259 | * @retval The new state of PWR_FLAG (SET or RESET).
260 | */
261 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
262 | {
263 | FlagStatus bitstatus = RESET;
264 | /* Check the parameters */
265 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
266 |
267 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
268 | {
269 | bitstatus = SET;
270 | }
271 | else
272 | {
273 | bitstatus = RESET;
274 | }
275 | /* Return the flag status */
276 | return bitstatus;
277 | }
278 |
279 | /**
280 | * @brief Clears the PWR's pending flags.
281 | * @param PWR_FLAG: specifies the flag to clear.
282 | * This parameter can be one of the following values:
283 | * @arg PWR_FLAG_WU: Wake Up flag
284 | * @arg PWR_FLAG_SB: StandBy flag
285 | * @retval None
286 | */
287 | void PWR_ClearFlag(uint32_t PWR_FLAG)
288 | {
289 | /* Check the parameters */
290 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
291 |
292 | PWR->CR |= PWR_FLAG << 2;
293 | }
294 |
295 | /**
296 | * @}
297 | */
298 |
299 | /**
300 | * @}
301 | */
302 |
303 | /**
304 | * @}
305 | */
306 |
307 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
308 |
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/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_rtc.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the RTC firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_rtc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup RTC
30 | * @brief RTC driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup RTC_Private_TypesDefinitions
35 | * @{
36 | */
37 | /**
38 | * @}
39 | */
40 |
41 | /** @defgroup RTC_Private_Defines
42 | * @{
43 | */
44 | #define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
45 | #define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
46 |
47 | /**
48 | * @}
49 | */
50 |
51 | /** @defgroup RTC_Private_Macros
52 | * @{
53 | */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @defgroup RTC_Private_Variables
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup RTC_Private_FunctionPrototypes
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @defgroup RTC_Private_Functions
76 | * @{
77 | */
78 |
79 | /**
80 | * @brief Enables or disables the specified RTC interrupts.
81 | * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
82 | * This parameter can be any combination of the following values:
83 | * @arg RTC_IT_OW: Overflow interrupt
84 | * @arg RTC_IT_ALR: Alarm interrupt
85 | * @arg RTC_IT_SEC: Second interrupt
86 | * @param NewState: new state of the specified RTC interrupts.
87 | * This parameter can be: ENABLE or DISABLE.
88 | * @retval None
89 | */
90 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
91 | {
92 | /* Check the parameters */
93 | assert_param(IS_RTC_IT(RTC_IT));
94 | assert_param(IS_FUNCTIONAL_STATE(NewState));
95 |
96 | if (NewState != DISABLE)
97 | {
98 | RTC->CRH |= RTC_IT;
99 | }
100 | else
101 | {
102 | RTC->CRH &= (uint16_t)~RTC_IT;
103 | }
104 | }
105 |
106 | /**
107 | * @brief Enters the RTC configuration mode.
108 | * @param None
109 | * @retval None
110 | */
111 | void RTC_EnterConfigMode(void)
112 | {
113 | /* Set the CNF flag to enter in the Configuration Mode */
114 | RTC->CRL |= RTC_CRL_CNF;
115 | }
116 |
117 | /**
118 | * @brief Exits from the RTC configuration mode.
119 | * @param None
120 | * @retval None
121 | */
122 | void RTC_ExitConfigMode(void)
123 | {
124 | /* Reset the CNF flag to exit from the Configuration Mode */
125 | RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
126 | }
127 |
128 | /**
129 | * @brief Gets the RTC counter value.
130 | * @param None
131 | * @retval RTC counter value.
132 | */
133 | uint32_t RTC_GetCounter(void)
134 | {
135 | uint16_t tmp = 0;
136 | tmp = RTC->CNTL;
137 | return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
138 | }
139 |
140 | /**
141 | * @brief Sets the RTC counter value.
142 | * @param CounterValue: RTC counter new value.
143 | * @retval None
144 | */
145 | void RTC_SetCounter(uint32_t CounterValue)
146 | {
147 | RTC_EnterConfigMode();
148 | /* Set RTC COUNTER MSB word */
149 | RTC->CNTH = CounterValue >> 16;
150 | /* Set RTC COUNTER LSB word */
151 | RTC->CNTL = (CounterValue & RTC_LSB_MASK);
152 | RTC_ExitConfigMode();
153 | }
154 |
155 | /**
156 | * @brief Sets the RTC prescaler value.
157 | * @param PrescalerValue: RTC prescaler new value.
158 | * @retval None
159 | */
160 | void RTC_SetPrescaler(uint32_t PrescalerValue)
161 | {
162 | /* Check the parameters */
163 | assert_param(IS_RTC_PRESCALER(PrescalerValue));
164 |
165 | RTC_EnterConfigMode();
166 | /* Set RTC PRESCALER MSB word */
167 | RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
168 | /* Set RTC PRESCALER LSB word */
169 | RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
170 | RTC_ExitConfigMode();
171 | }
172 |
173 | /**
174 | * @brief Sets the RTC alarm value.
175 | * @param AlarmValue: RTC alarm new value.
176 | * @retval None
177 | */
178 | void RTC_SetAlarm(uint32_t AlarmValue)
179 | {
180 | RTC_EnterConfigMode();
181 | /* Set the ALARM MSB word */
182 | RTC->ALRH = AlarmValue >> 16;
183 | /* Set the ALARM LSB word */
184 | RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
185 | RTC_ExitConfigMode();
186 | }
187 |
188 | /**
189 | * @brief Gets the RTC divider value.
190 | * @param None
191 | * @retval RTC Divider value.
192 | */
193 | uint32_t RTC_GetDivider(void)
194 | {
195 | uint32_t tmp = 0x00;
196 | tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
197 | tmp |= RTC->DIVL;
198 | return tmp;
199 | }
200 |
201 | /**
202 | * @brief Waits until last write operation on RTC registers has finished.
203 | * @note This function must be called before any write to RTC registers.
204 | * @param None
205 | * @retval None
206 | */
207 | void RTC_WaitForLastTask(void)
208 | {
209 | /* Loop until RTOFF flag is set */
210 | while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
211 | {
212 | }
213 | }
214 |
215 | /**
216 | * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
217 | * are synchronized with RTC APB clock.
218 | * @note This function must be called before any read operation after an APB reset
219 | * or an APB clock stop.
220 | * @param None
221 | * @retval None
222 | */
223 | void RTC_WaitForSynchro(void)
224 | {
225 | /* Clear RSF flag */
226 | RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
227 | /* Loop until RSF flag is set */
228 | while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
229 | {
230 | }
231 | }
232 |
233 | /**
234 | * @brief Checks whether the specified RTC flag is set or not.
235 | * @param RTC_FLAG: specifies the flag to check.
236 | * This parameter can be one the following values:
237 | * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
238 | * @arg RTC_FLAG_RSF: Registers Synchronized flag
239 | * @arg RTC_FLAG_OW: Overflow flag
240 | * @arg RTC_FLAG_ALR: Alarm flag
241 | * @arg RTC_FLAG_SEC: Second flag
242 | * @retval The new state of RTC_FLAG (SET or RESET).
243 | */
244 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
245 | {
246 | FlagStatus bitstatus = RESET;
247 |
248 | /* Check the parameters */
249 | assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
250 |
251 | if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
252 | {
253 | bitstatus = SET;
254 | }
255 | else
256 | {
257 | bitstatus = RESET;
258 | }
259 | return bitstatus;
260 | }
261 |
262 | /**
263 | * @brief Clears the RTC's pending flags.
264 | * @param RTC_FLAG: specifies the flag to clear.
265 | * This parameter can be any combination of the following values:
266 | * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
267 | * an APB reset or an APB Clock stop.
268 | * @arg RTC_FLAG_OW: Overflow flag
269 | * @arg RTC_FLAG_ALR: Alarm flag
270 | * @arg RTC_FLAG_SEC: Second flag
271 | * @retval None
272 | */
273 | void RTC_ClearFlag(uint16_t RTC_FLAG)
274 | {
275 | /* Check the parameters */
276 | assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
277 |
278 | /* Clear the corresponding RTC flag */
279 | RTC->CRL &= (uint16_t)~RTC_FLAG;
280 | }
281 |
282 | /**
283 | * @brief Checks whether the specified RTC interrupt has occurred or not.
284 | * @param RTC_IT: specifies the RTC interrupts sources to check.
285 | * This parameter can be one of the following values:
286 | * @arg RTC_IT_OW: Overflow interrupt
287 | * @arg RTC_IT_ALR: Alarm interrupt
288 | * @arg RTC_IT_SEC: Second interrupt
289 | * @retval The new state of the RTC_IT (SET or RESET).
290 | */
291 | ITStatus RTC_GetITStatus(uint16_t RTC_IT)
292 | {
293 | ITStatus bitstatus = RESET;
294 | /* Check the parameters */
295 | assert_param(IS_RTC_GET_IT(RTC_IT));
296 |
297 | bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
298 | if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
299 | {
300 | bitstatus = SET;
301 | }
302 | else
303 | {
304 | bitstatus = RESET;
305 | }
306 | return bitstatus;
307 | }
308 |
309 | /**
310 | * @brief Clears the RTC's interrupt pending bits.
311 | * @param RTC_IT: specifies the interrupt pending bit to clear.
312 | * This parameter can be any combination of the following values:
313 | * @arg RTC_IT_OW: Overflow interrupt
314 | * @arg RTC_IT_ALR: Alarm interrupt
315 | * @arg RTC_IT_SEC: Second interrupt
316 | * @retval None
317 | */
318 | void RTC_ClearITPendingBit(uint16_t RTC_IT)
319 | {
320 | /* Check the parameters */
321 | assert_param(IS_RTC_IT(RTC_IT));
322 |
323 | /* Clear the corresponding RTC pending bit */
324 | RTC->CRL &= (uint16_t)~RTC_IT;
325 | }
326 |
327 | /**
328 | * @}
329 | */
330 |
331 | /**
332 | * @}
333 | */
334 |
335 | /**
336 | * @}
337 | */
338 |
339 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
340 |
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/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the WWDG firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_wwdg.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup WWDG
31 | * @brief WWDG driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup WWDG_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup WWDG_Private_Defines
44 | * @{
45 | */
46 |
47 | /* ----------- WWDG registers bit address in the alias region ----------- */
48 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
49 |
50 | /* Alias word address of EWI bit */
51 | #define CFR_OFFSET (WWDG_OFFSET + 0x04)
52 | #define EWI_BitNumber 0x09
53 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
54 |
55 | /* --------------------- WWDG registers bit mask ------------------------ */
56 |
57 | /* CR register bit mask */
58 | #define CR_WDGA_Set ((uint32_t)0x00000080)
59 |
60 | /* CFR register bit mask */
61 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
62 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80)
63 | #define BIT_Mask ((uint8_t)0x7F)
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | /** @defgroup WWDG_Private_Macros
70 | * @{
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /** @defgroup WWDG_Private_Variables
78 | * @{
79 | */
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /** @defgroup WWDG_Private_FunctionPrototypes
86 | * @{
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /** @defgroup WWDG_Private_Functions
94 | * @{
95 | */
96 |
97 | /**
98 | * @brief Deinitializes the WWDG peripheral registers to their default reset values.
99 | * @param None
100 | * @retval None
101 | */
102 | void WWDG_DeInit(void)
103 | {
104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
105 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
106 | }
107 |
108 | /**
109 | * @brief Sets the WWDG Prescaler.
110 | * @param WWDG_Prescaler: specifies the WWDG Prescaler.
111 | * This parameter can be one of the following values:
112 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
113 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
114 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
115 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
116 | * @retval None
117 | */
118 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
119 | {
120 | uint32_t tmpreg = 0;
121 | /* Check the parameters */
122 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
123 | /* Clear WDGTB[1:0] bits */
124 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
125 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
126 | tmpreg |= WWDG_Prescaler;
127 | /* Store the new value */
128 | WWDG->CFR = tmpreg;
129 | }
130 |
131 | /**
132 | * @brief Sets the WWDG window value.
133 | * @param WindowValue: specifies the window value to be compared to the downcounter.
134 | * This parameter value must be lower than 0x80.
135 | * @retval None
136 | */
137 | void WWDG_SetWindowValue(uint8_t WindowValue)
138 | {
139 | __IO uint32_t tmpreg = 0;
140 |
141 | /* Check the parameters */
142 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
143 | /* Clear W[6:0] bits */
144 |
145 | tmpreg = WWDG->CFR & CFR_W_Mask;
146 |
147 | /* Set W[6:0] bits according to WindowValue value */
148 | tmpreg |= WindowValue & (uint32_t) BIT_Mask;
149 |
150 | /* Store the new value */
151 | WWDG->CFR = tmpreg;
152 | }
153 |
154 | /**
155 | * @brief Enables the WWDG Early Wakeup interrupt(EWI).
156 | * @param None
157 | * @retval None
158 | */
159 | void WWDG_EnableIT(void)
160 | {
161 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
162 | }
163 |
164 | /**
165 | * @brief Sets the WWDG counter value.
166 | * @param Counter: specifies the watchdog counter value.
167 | * This parameter must be a number between 0x40 and 0x7F.
168 | * @retval None
169 | */
170 | void WWDG_SetCounter(uint8_t Counter)
171 | {
172 | /* Check the parameters */
173 | assert_param(IS_WWDG_COUNTER(Counter));
174 | /* Write to T[6:0] bits to configure the counter value, no need to do
175 | a read-modify-write; writing a 0 to WDGA bit does nothing */
176 | WWDG->CR = Counter & BIT_Mask;
177 | }
178 |
179 | /**
180 | * @brief Enables WWDG and load the counter value.
181 | * @param Counter: specifies the watchdog counter value.
182 | * This parameter must be a number between 0x40 and 0x7F.
183 | * @retval None
184 | */
185 | void WWDG_Enable(uint8_t Counter)
186 | {
187 | /* Check the parameters */
188 | assert_param(IS_WWDG_COUNTER(Counter));
189 | WWDG->CR = CR_WDGA_Set | Counter;
190 | }
191 |
192 | /**
193 | * @brief Checks whether the Early Wakeup interrupt flag is set or not.
194 | * @param None
195 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
196 | */
197 | FlagStatus WWDG_GetFlagStatus(void)
198 | {
199 | return (FlagStatus)(WWDG->SR);
200 | }
201 |
202 | /**
203 | * @brief Clears Early Wakeup interrupt flag.
204 | * @param None
205 | * @retval None
206 | */
207 | void WWDG_ClearFlag(void)
208 | {
209 | WWDG->SR = (uint32_t)RESET;
210 | }
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /**
217 | * @}
218 | */
219 |
220 | /**
221 | * @}
222 | */
223 |
224 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
225 |
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34 | 165790 16:39:42.924 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 03
35 | 165791 16:39:42.924 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 37
36 | 165792 16:39:42.924 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 34
37 | 165793 16:39:42.924 0.00193460 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
38 | 165794 16:39:42.924 0.00236483 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
39 | 165795 16:39:42.924 0.00195639 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
40 | 165796 16:39:42.924 0.00156277 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
41 | 165797 16:39:42.934 0.00000531 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
42 | 165798 16:39:42.934 0.00196813 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 13, Data: 02 45 30 30 30 45 30 36 30 32 03 45 35
43 | 165799 16:39:42.934 0.05125847 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 02
44 | 165800 16:39:42.984 0.00000587 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 31
45 | 165801 16:39:42.984 0.00000391 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
46 | 165802 16:39:42.984 0.00000363 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
47 | 165803 16:39:42.984 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
48 | 165804 16:39:42.984 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 03
49 | 165805 16:39:42.984 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 43
50 | 165806 16:39:42.984 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 34
51 | 165807 16:39:42.984 0.00200137 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
52 | 165808 16:39:42.984 0.00191309 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
53 | 165809 16:39:42.984 0.00158735 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
54 | 165810 16:39:42.984 0.00172564 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
55 | 165811 16:39:42.994 0.00000503 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
56 | 165812 16:39:42.994 0.00194103 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 13, Data: 02 45 30 31 38 30 30 38 30 38 03 45 31
57 | 165813 16:39:42.994 0.05851666 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 02
58 | 165814 16:39:43.054 0.00000475 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
59 | 165815 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
60 | 165816 16:39:43.054 0.00000279 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
61 | 165817 16:39:43.054 0.00000223 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
62 | 165818 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
63 | 165819 16:39:43.054 0.00000223 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
64 | 165820 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
65 | 165821 16:39:43.054 0.00000223 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
66 | 165822 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
67 | 165823 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
68 | 165824 16:39:43.054 0.00000223 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
69 | 165825 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
70 | 165826 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
71 | 165827 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
72 | 165828 16:39:43.054 0.00000279 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 32
73 | 165829 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
74 | 165830 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 03
75 | 165831 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 31
76 | 165832 16:39:43.054 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 33
77 | 165833 16:39:43.054 0.00181252 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
78 | 165834 16:39:43.054 0.00197651 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
79 | 165835 16:39:43.054 0.00194243 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
80 | 165836 16:39:43.054 0.00197846 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
81 | 165837 16:39:43.054 0.00000363 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
82 | 165838 16:39:43.054 0.00166194 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 13, Data: 02 45 30 30 30 45 43 43 30 32 03 30 35
83 | 165839 16:39:43.064 0.05104084 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 02
84 | 165840 16:39:43.114 0.00000587 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 31
85 | 165841 16:39:43.114 0.00000363 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
86 | 165842 16:39:43.114 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
87 | 165843 16:39:43.114 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 30
88 | 165844 16:39:43.114 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 03
89 | 165845 16:39:43.114 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 43
90 | 165846 16:39:43.114 0.00000307 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 34
91 | 165847 16:39:43.114 0.00189493 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
92 | 165848 16:39:43.114 0.00189018 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
93 | 165849 16:39:43.114 0.00194941 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
94 | 165850 16:39:43.114 0.00215027 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
95 | 165851 16:39:43.124 0.00000503 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
96 | 165852 16:39:43.124 0.13202851 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 141, Data: 02 45 31 31 38 30 30 30 34 30 31 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30 32 30
97 | 165853 16:39:43.254 0.04408940 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 06
98 | 165854 16:39:43.295 0.00183459 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
99 | 165855 16:39:43.295 0.00210530 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
100 | 165856 16:39:43.305 0.00195304 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
101 | 165857 16:39:43.305 0.00197679 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
102 | 165858 16:39:43.305 0.00000363 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
103 | 165859 16:39:43.305 0.04461154 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 69, Data: 02 45 31 31 38 30 34 30 31 43 39 30 30 31 46 45 30 33 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
104 | 165860 16:39:43.345 0.05806017 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 06
105 | 165861 16:39:43.405 0.00191309 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
106 | 165862 16:39:43.405 0.00195472 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
107 | 165863 16:39:43.415 0.00196338 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
108 | 165864 16:39:43.415 0.00197735 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
109 | 165865 16:39:43.415 0.00000335 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
110 | 165866 16:39:43.415 0.00206060 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 5, Data: 02 42 03 34 35
111 | 165867 16:39:43.415 0.02960181 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 06
112 | 165868 16:39:43.445 0.00784932 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
113 | 165869 16:39:43.455 0.00197595 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
114 | 165870 16:39:43.455 0.00197204 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
115 | 165871 16:39:43.455 0.00209915 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
116 | 165872 16:39:43.465 0.00000335 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
117 | 165873 16:39:43.465 0.00204579 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 11, Data: 02 30 30 45 30 32 30 32 03 36 43
118 | 165874 16:39:43.465 0.04403129 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 02
119 | 165875 16:39:43.505 0.00000419 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 46
120 | 165876 16:39:43.505 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 36
121 | 165877 16:39:43.505 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 35
122 | 165878 16:39:43.505 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 45
123 | 165879 16:39:43.505 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 03
124 | 165880 16:39:43.505 0.00000251 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 46
125 | 165881 16:39:43.505 0.00000279 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 39
126 | 165882 16:39:43.515 0.00304173 Gppw.exe IOCTL_SERIAL_CLR_DTR COM9 SUCCESS
127 | 165883 16:39:43.515 0.00197539 Gppw.exe IOCTL_SERIAL_CLR_RTS COM9 SUCCESS
128 | 165884 16:39:43.515 0.00197371 Gppw.exe IOCTL_SERIAL_SET_DTR COM9 SUCCESS
129 | 165885 16:39:43.515 0.00198908 Gppw.exe IOCTL_SERIAL_SET_RTS COM9 SUCCESS
130 | 165886 16:39:43.515 0.00000307 Gppw.exe IOCTL_SERIAL_PURGE COM9 SUCCESS Purge: TXCLEAR RXCLEAR
131 | 165887 16:39:43.515 0.00212317 Gppw.exe IRP_MJ_WRITE COM9 SUCCESS Length: 11, Data: 02 30 30 45 43 41 30 32 03 38 45
132 | 165888 16:39:43.525 0.04334350 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 02
133 | 165889 16:39:43.565 0.00000615 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 46
134 | 165890 16:39:43.565 0.00000391 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 36
135 | 165891 16:39:43.565 0.00000391 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 35
136 | 165892 16:39:43.565 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 45
137 | 165893 16:39:43.565 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 03
138 | 165894 16:39:43.565 0.00000335 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 46
139 | 165895 16:39:43.575 0.00000587 Gppw.exe IRP_MJ_READ COM9 SUCCESS Length: 1, Data: 39
140 |
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/doc/寄存器位(点)元件地址(按地址排）.TXT:
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/doc/新建 文本文档.txt:
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/fault_test.c:
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1 | /*
2 | * fault_test.c
3 | *
4 | * Created on: 2016/12/25
5 | * Author: Armink
6 | */
7 |
8 | #include
9 |
10 | void fault_test_by_unalign(void) {
11 | volatile int * SCB_CCR = (volatile int *) 0xE000ED14; // SCB->CCR
12 | volatile int * p;
13 | volatile int value;
14 |
15 | *SCB_CCR |= (1 << 3); /* bit3: UNALIGN_TRP. */
16 |
17 | p = (int *) 0x00;
18 | value = *p;
19 | printf("addr:0x%02X value:0x%08X\r\n", (int) p, value);
20 |
21 | p = (int *) 0x04;
22 | value = *p;
23 | printf("addr:0x%02X value:0x%08X\r\n", (int) p, value);
24 |
25 | p = (int *) 0x03;
26 | value = *p;
27 | printf("addr:0x%02X value:0x%08X\r\n", (int) p, value);
28 | }
29 |
30 | void fault_test_by_div0(void) {
31 | volatile int * SCB_CCR = (volatile int *) 0xE000ED14; // SCB->CCR
32 | int x, y, z;
33 |
34 | *SCB_CCR |= (1 << 4); /* bit4: DIV_0_TRP. */
35 |
36 | x = 10;
37 | y = 0;
38 | z = x / y;
39 | printf("z:%d\n", z);
40 | }
41 |
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/mcu/NVIC.c:
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/mcu/NVIC.h:
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1 | #ifndef __NVIC_H
2 | #define __NVIC_H
3 |
4 | #include "stm32f10x.h"
5 |
6 | void NVIC_Configuration(void);
7 |
8 | #endif /* __USART1_H */
9 |
10 |
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/mcu/RCC.c:
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/mcu/RCC.h:
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1 | #ifndef __RCC_H
2 | #define __RCC_H
3 |
4 | #include "stm32f10x.h"
5 |
6 | void RCC_Config(void);
7 |
8 | #endif /* __USART1_H */
9 |
10 |
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/mcu/RTC.c:
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/mcu/RTC.h:
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1 | #ifndef __RTC_H
2 | #define __RTC_H
3 |
4 |
5 | #include "stm32f10x.h"
6 |
7 | void RTC_Configuration(void);
8 |
9 | #endif /* __XXX_H */
10 |
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/mcu/UsartDma.c:
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/mcu/main.c:
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1 | /**
2 | ******************************************************************************
3 | * @file FLASH/Program/main.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief Main program body
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "RCC.h"
24 | #include "NVIC.h"
25 | #include "usart1.h"
26 | #include "rtc.h"
27 | #include "plc_app.H"
28 |
29 | //#include "PLC_PUBLIC.H"
30 |
31 | /* Private function prototypes -----------------------------------------------*/
32 |
33 | /**
34 | * @brief Main program
35 | * @param None
36 | * @retval None
37 | */
38 | int main(void)
39 | {
40 | /*!< At this stage the microcontroller clock setting is already configured,
41 | this is done through SystemInit() function which is called from startup
42 | file (startup_stm32f10x_xx.s) before to branch to application main.
43 | To reconfigure the default setting of SystemInit() function, refer to
44 | system_stm32f10x.c file
45 | */
46 |
47 | /* System Clocks Configuration */
48 | RCC_Config();
49 |
50 | /* Enable the LSI OSC */
51 | RCC_LSICmd(ENABLE);
52 | /* Wait till LSI is ready */
53 | while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET)
54 | {}
55 | /* NVIC configuration */
56 | NVIC_Configuration();
57 |
58 | SysTick_Config(72000000 / 1000);
59 |
60 | plc_main();
61 | }
62 |
63 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
64 |
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/mcu/stm32f10x.h:
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/mcu/stm32f10x_conf.h:
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1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_CONF_H
24 | #define __STM32F10x_CONF_H
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
28 | #include "stm32f10x_adc.h"
29 | #include "stm32f10x_bkp.h"
30 | #include "stm32f10x_can.h"
31 | #include "stm32f10x_cec.h"
32 | #include "stm32f10x_crc.h"
33 | #include "stm32f10x_dac.h"
34 | #include "stm32f10x_dbgmcu.h"
35 | #include "stm32f10x_dma.h"
36 | #include "stm32f10x_exti.h"
37 | #include "stm32f10x_flash.h"
38 | #include "stm32f10x_fsmc.h"
39 | #include "stm32f10x_gpio.h"
40 | #include "stm32f10x_i2c.h"
41 | #include "stm32f10x_iwdg.h"
42 | #include "stm32f10x_pwr.h"
43 | #include "stm32f10x_rcc.h"
44 | #include "stm32f10x_rtc.h"
45 | #include "stm32f10x_sdio.h"
46 | #include "stm32f10x_spi.h"
47 | #include "stm32f10x_tim.h"
48 | #include "stm32f10x_usart.h"
49 | #include "stm32f10x_wwdg.h"
50 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
51 |
52 | /* Exported types ------------------------------------------------------------*/
53 | /* Exported constants --------------------------------------------------------*/
54 | /* Uncomment the line below to expanse the "assert_param" macro in the
55 | Standard Peripheral Library drivers code */
56 | /* #define USE_FULL_ASSERT 1 */
57 |
58 | /* Exported macro ------------------------------------------------------------*/
59 | #ifdef USE_FULL_ASSERT
60 |
61 | /**
62 | * @brief The assert_param macro is used for function's parameters check.
63 | * @param expr: If expr is false, it calls assert_failed function which reports
64 | * the name of the source file and the source line number of the call
65 | * that failed. If expr is true, it returns no value.
66 | * @retval None
67 | */
68 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
69 | /* Exported functions ------------------------------------------------------- */
70 | void assert_failed(uint8_t* file, uint32_t line);
71 | #else
72 | #define assert_param(expr) ((void)0)
73 | #endif /* USE_FULL_ASSERT */
74 |
75 | #endif /* __STM32F10x_CONF_H */
76 |
77 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
78 |
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/mcu/stm32f10x_it.c:
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1 | /**
2 | ******************************************************************************
3 | * @file USART/Interrupt/stm32f10x_it.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief Main Interrupt Service Routines.
8 | * This file provides template for all exceptions handler and peripherals
9 | * interrupt service routine.
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
15 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
16 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
17 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
18 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 | *
20 | * © COPYRIGHT 2011 STMicroelectronics
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes ------------------------------------------------------------------*/
25 | #include "stm32f10x_it.h"
26 |
27 | /** @addtogroup STM32F10x_StdPeriph_Examples
28 | * @{
29 | */
30 |
31 | /** @addtogroup USART_Interrupt
32 | * @{
33 | */
34 |
35 |
36 |
37 | /* Private function prototypes -----------------------------------------------*/
38 | /* Private functions ---------------------------------------------------------*/
39 |
40 | /******************************************************************************/
41 | /* Cortex-M3 Processor Exceptions Handlers */
42 | /******************************************************************************/
43 |
44 | /**
45 | * @brief This function handles NMI exception.
46 | * @param None
47 | * @retval None
48 | */
49 | void NMI_Handler(void)
50 | {
51 | }
52 |
53 |
54 | /**
55 | * @brief This function handles Memory Manage exception.
56 | * @param None
57 | * @retval None
58 | */
59 | void MemManage_Handler(void)
60 | {
61 | /* Go to infinite loop when Memory Manage exception occurs */
62 | while (1)
63 | {
64 | }
65 | }
66 |
67 | /**
68 | * @brief This function handles Bus Fault exception.
69 | * @param None
70 | * @retval None
71 | */
72 | void BusFault_Handler(void)
73 | {
74 | /* Go to infinite loop when Bus Fault exception occurs */
75 | while (1)
76 | {
77 | }
78 | }
79 |
80 | /**
81 | * @brief This function handles Usage Fault exception.
82 | * @param None
83 | * @retval None
84 | */
85 | void UsageFault_Handler(void)
86 | {
87 | /* Go to infinite loop when Usage Fault exception occurs */
88 | while (1)
89 | {
90 | }
91 | }
92 |
93 | /**
94 | * @brief This function handles SVCall exception.
95 | * @param None
96 | * @retval None
97 | */
98 | void SVC_Handler(void)
99 | {
100 | }
101 |
102 | /**
103 | * @brief This function handles Debug Monitor exception.
104 | * @param None
105 | * @retval None
106 | */
107 | void DebugMon_Handler(void)
108 | {
109 | }
110 |
111 | /**
112 | * @brief This function handles PendSV_Handler exception.
113 | * @param None
114 | * @retval None
115 | */
116 | void PendSV_Handler(void)
117 | {
118 | }
119 |
120 |
121 |
122 | /******************************************************************************/
123 | /* STM32F10x Peripherals Interrupt Handlers */
124 | /******************************************************************************/
125 |
126 | /**
127 | * @brief This function handles USARTy global interrupt request.
128 | * @param None
129 | * @retval None
130 | */
131 |
132 |
133 |
134 | /******************************************************************************/
135 | /* STM32F10x Peripherals Interrupt Handlers */
136 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
137 | /* available peripheral interrupt handler's name please refer to the startup */
138 | /* file (startup_stm32f10x_xx.s). */
139 | /******************************************************************************/
140 |
141 | /**
142 | * @brief This function handles PPP interrupt request.
143 | * @param None
144 | * @retval None
145 | */
146 | /*void PPP_IRQHandler(void)
147 | {
148 | }*/
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /**
155 | * @}
156 | */
157 |
158 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
159 |
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/mcu/stm32f10x_it.h:
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1 | /**
2 | ******************************************************************************
3 | * @file USART/Interrupt/stm32f10x_it.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief This file contains the headers of the interrupt handlers.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_IT_H
24 | #define __STM32F10x_IT_H
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "stm32f10x.h"
28 |
29 | /* Exported types ------------------------------------------------------------*/
30 | /* Exported constants --------------------------------------------------------*/
31 | /* Exported macro ------------------------------------------------------------*/
32 | /* Exported functions ------------------------------------------------------- */
33 |
34 | void NMI_Handler(void);
35 | void HardFault_Handler(void);
36 | void MemManage_Handler(void);
37 | void BusFault_Handler(void);
38 | void UsageFault_Handler(void);
39 | void SVC_Handler(void);
40 | void DebugMon_Handler(void);
41 | void PendSV_Handler(void);
42 |
43 | void USART3_IRQHandler(void);
44 |
45 | #endif /* __STM32F10x_IT_H */
46 |
47 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
48 |
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/mcu/system_stm32f10x.h:
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1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f10x.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /** @addtogroup CMSIS
23 | * @{
24 | */
25 |
26 | /** @addtogroup stm32f10x_system
27 | * @{
28 | */
29 |
30 | /**
31 | * @brief Define to prevent recursive inclusion
32 | */
33 | #ifndef __SYSTEM_STM32F10X_H
34 | #define __SYSTEM_STM32F10X_H
35 |
36 | #ifdef __cplusplus
37 | extern "C" {
38 | #endif
39 |
40 | /** @addtogroup STM32F10x_System_Includes
41 | * @{
42 | */
43 |
44 | /**
45 | * @}
46 | */
47 |
48 |
49 | /** @addtogroup STM32F10x_System_Exported_types
50 | * @{
51 | */
52 |
53 |
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @addtogroup STM32F10x_System_Exported_Constants
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @addtogroup STM32F10x_System_Exported_Macros
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @addtogroup STM32F10x_System_Exported_Functions
76 | * @{
77 | */
78 |
79 | extern void SystemInit(void);
80 | extern void SystemCoreClockUpdate(void);
81 | /**
82 | * @}
83 | */
84 |
85 | #ifdef __cplusplus
86 | }
87 | #endif
88 |
89 | #endif /*__SYSTEM_STM32F10X_H */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
99 |
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/mcu/usart1.h:
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1 | #ifndef __USART1_H
2 | #define __USART1_H
3 |
4 | #include "stm32f10x.h"
5 | #include
6 |
7 | void USB2Serial_Init(uint8_t BaudRate);
8 | static char *itoa(int value, char *string, int radix);
9 | void USART1_printf(USART_TypeDef* USARTx, uint8_t *Data,...);
10 | uint8_t USART_Scanf(uint32_t value);
11 |
12 | #endif /* __USART1_H */
13 |
14 |
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/plc/Instructions.h:
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1 | #ifndef __instructions_H
2 | #define __instructions_H
3 |
4 | #include "PLC_PUBLIC.H"
5 |
6 | void anb(void); //0xFFF8
7 | void orb(void); //0xFFF9
8 |
9 |
10 | #endif //instructions
11 |
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/plc/PLC_Other.C:
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/plc/PLC_ProgTest.c:
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/plc/PLC_RUN.H:
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1 | #include "PLC_PUBLIC.H"
2 | #ifndef PLC_RUN_H
3 | #define PLC_RUN_H
4 | extern void PLC_END_PROG(void);
5 |
6 | #endif
7 |
8 |
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/plc/PLC_STL.C:
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/startup_stm32f10x_hd.s:
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1 | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
2 | ;* File Name : startup_stm32f10x_hd.s
3 | ;* Author : MCD Application Team
4 | ;* Version : V3.5.0
5 | ;* Date : 11-March-2011
6 | ;* Description : STM32F10x High Density Devices vector table for EWARM
7 | ;* toolchain.
8 | ;* This module performs:
9 | ;* - Set the initial SP
10 | ;* - Configure the clock system and the external SRAM
11 | ;* mounted on STM3210E-EVAL board to be used as data
12 | ;* memory (optional, to be enabled by user)
13 | ;* - Set the initial PC == __iar_program_start,
14 | ;* - Set the vector table entries with the exceptions ISR address,
15 | ;* After Reset the Cortex-M3 processor is in Thread mode,
16 | ;* priority is Privileged, and the Stack is set to Main.
17 | ;********************************************************************************
18 | ;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
19 | ;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
20 | ;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
21 | ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
22 | ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
23 | ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
24 | ;*******************************************************************************
25 | ;
26 | ;
27 | ; The modules in this file are included in the libraries, and may be replaced
28 | ; by any user-defined modules that define the PUBLIC symbol _program_start or
29 | ; a user defined start symbol.
30 | ; To override the cstartup defined in the library, simply add your modified
31 | ; version to the workbench project.
32 | ;
33 | ; The vector table is normally located at address 0.
34 | ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
35 | ; The name "__vector_table" has special meaning for C-SPY:
36 | ; it is where the SP start value is found, and the NVIC vector
37 | ; table register (VTOR) is initialized to this address if != 0.
38 | ;
39 | ; Cortex-M version
40 | ;
41 |
42 | MODULE ?cstartup
43 |
44 | ;; Forward declaration of sections.
45 | SECTION CSTACK:DATA:NOROOT(3)
46 |
47 | SECTION .intvec:CODE:NOROOT(2)
48 |
49 | EXTERN __iar_program_start;;main;;
50 | EXTERN SystemInit
51 | PUBLIC __vector_table
52 |
53 | DATA
54 |
55 | __vector_table
56 | DCD sfe(CSTACK)
57 | DCD Reset_Handler ; Reset Handler
58 | DCD NMI_Handler ; NMI Handler
59 | DCD HardFault_Handler ; Hard Fault Handler
60 | DCD MemManage_Handler ; MPU Fault Handler
61 | DCD BusFault_Handler ; Bus Fault Handler
62 | DCD UsageFault_Handler ; Usage Fault Handler
63 | DCD 0 ; Reserved
64 | DCD 0 ; Reserved
65 | DCD 0 ; Reserved
66 | DCD 0 ; Reserved
67 | DCD SVC_Handler ; SVCall Handler
68 | DCD DebugMon_Handler ; Debug Monitor Handler
69 | DCD 0 ; Reserved
70 | DCD PendSV_Handler ; PendSV Handler
71 | DCD SysTick_Handler ; SysTick Handler
72 |
73 | ; External Interrupts
74 | DCD WWDG_IRQHandler ; Window Watchdog
75 | DCD PVD_IRQHandler ; PVD through EXTI Line detect
76 | DCD TAMPER_IRQHandler ; Tamper
77 | DCD RTC_IRQHandler ; RTC
78 | DCD FLASH_IRQHandler ; Flash
79 | DCD RCC_IRQHandler ; RCC
80 | DCD EXTI0_IRQHandler ; EXTI Line 0
81 | DCD EXTI1_IRQHandler ; EXTI Line 1
82 | DCD EXTI2_IRQHandler ; EXTI Line 2
83 | DCD EXTI3_IRQHandler ; EXTI Line 3
84 | DCD EXTI4_IRQHandler ; EXTI Line 4
85 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
86 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
87 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
88 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
89 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
90 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
91 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
92 | DCD ADC1_2_IRQHandler ; ADC1 & ADC2
93 | DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
94 | DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
95 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1
96 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE
97 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
98 | DCD TIM1_BRK_IRQHandler ; TIM1 Break
99 | DCD TIM1_UP_IRQHandler ; TIM1 Update
100 | DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
101 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
102 | DCD TIM2_IRQHandler ; TIM2
103 | DCD TIM3_IRQHandler ; TIM3
104 | DCD TIM4_IRQHandler ; TIM4
105 | DCD I2C1_EV_IRQHandler ; I2C1 Event
106 | DCD I2C1_ER_IRQHandler ; I2C1 Error
107 | DCD I2C2_EV_IRQHandler ; I2C2 Event
108 | DCD I2C2_ER_IRQHandler ; I2C2 Error
109 | DCD SPI1_IRQHandler ; SPI1
110 | DCD SPI2_IRQHandler ; SPI2
111 | DCD USART1_IRQHandler ; USART1
112 | DCD USART2_IRQHandler ; USART2
113 | DCD USART3_IRQHandler ; USART3
114 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
115 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
116 | DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
117 | DCD TIM8_BRK_IRQHandler ; TIM8 Break
118 | DCD TIM8_UP_IRQHandler ; TIM8 Update
119 | DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
120 | DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
121 | DCD ADC3_IRQHandler ; ADC3
122 | DCD FSMC_IRQHandler ; FSMC
123 | DCD SDIO_IRQHandler ; SDIO
124 | DCD TIM5_IRQHandler ; TIM5
125 | DCD SPI3_IRQHandler ; SPI3
126 | DCD UART4_IRQHandler ; UART4
127 | DCD UART5_IRQHandler ; UART5
128 | DCD TIM6_IRQHandler ; TIM6
129 | DCD TIM7_IRQHandler ; TIM7
130 | DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
131 | DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
132 | DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
133 | DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
134 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
135 | ;;
136 | ;; Default interrupt handlers.
137 | ;;
138 | THUMB
139 |
140 | PUBWEAK Reset_Handler
141 | SECTION .text:CODE:REORDER(2)
142 | Reset_Handler
143 | LDR R0, =SystemInit
144 | BLX R0
145 | LDR R0, =__iar_program_start;;=main;;
146 | BX R0
147 |
148 | PUBWEAK NMI_Handler
149 | SECTION .text:CODE:REORDER(1)
150 | NMI_Handler
151 | B NMI_Handler
152 |
153 | PUBWEAK HardFault_Handler
154 | SECTION .text:CODE:REORDER(1)
155 | HardFault_Handler
156 | B HardFault_Handler
157 |
158 | PUBWEAK MemManage_Handler
159 | SECTION .text:CODE:REORDER(1)
160 | MemManage_Handler
161 | B MemManage_Handler
162 |
163 | PUBWEAK BusFault_Handler
164 | SECTION .text:CODE:REORDER(1)
165 | BusFault_Handler
166 | B BusFault_Handler
167 |
168 | PUBWEAK UsageFault_Handler
169 | SECTION .text:CODE:REORDER(1)
170 | UsageFault_Handler
171 | B UsageFault_Handler
172 |
173 | PUBWEAK SVC_Handler
174 | SECTION .text:CODE:REORDER(1)
175 | SVC_Handler
176 | B SVC_Handler
177 |
178 | PUBWEAK DebugMon_Handler
179 | SECTION .text:CODE:REORDER(1)
180 | DebugMon_Handler
181 | B DebugMon_Handler
182 |
183 | PUBWEAK PendSV_Handler
184 | SECTION .text:CODE:REORDER(1)
185 | PendSV_Handler
186 | B PendSV_Handler
187 |
188 | PUBWEAK SysTick_Handler
189 | SECTION .text:CODE:REORDER(1)
190 | SysTick_Handler
191 | B SysTick_Handler
192 |
193 | PUBWEAK WWDG_IRQHandler
194 | SECTION .text:CODE:REORDER(1)
195 | WWDG_IRQHandler
196 | B WWDG_IRQHandler
197 |
198 | PUBWEAK PVD_IRQHandler
199 | SECTION .text:CODE:REORDER(1)
200 | PVD_IRQHandler
201 | B PVD_IRQHandler
202 |
203 | PUBWEAK TAMPER_IRQHandler
204 | SECTION .text:CODE:REORDER(1)
205 | TAMPER_IRQHandler
206 | B TAMPER_IRQHandler
207 |
208 | PUBWEAK RTC_IRQHandler
209 | SECTION .text:CODE:REORDER(1)
210 | RTC_IRQHandler
211 | B RTC_IRQHandler
212 |
213 | PUBWEAK FLASH_IRQHandler
214 | SECTION .text:CODE:REORDER(1)
215 | FLASH_IRQHandler
216 | B FLASH_IRQHandler
217 |
218 | PUBWEAK RCC_IRQHandler
219 | SECTION .text:CODE:REORDER(1)
220 | RCC_IRQHandler
221 | B RCC_IRQHandler
222 |
223 | PUBWEAK EXTI0_IRQHandler
224 | SECTION .text:CODE:REORDER(1)
225 | EXTI0_IRQHandler
226 | B EXTI0_IRQHandler
227 |
228 | PUBWEAK EXTI1_IRQHandler
229 | SECTION .text:CODE:REORDER(1)
230 | EXTI1_IRQHandler
231 | B EXTI1_IRQHandler
232 |
233 | PUBWEAK EXTI2_IRQHandler
234 | SECTION .text:CODE:REORDER(1)
235 | EXTI2_IRQHandler
236 | B EXTI2_IRQHandler
237 |
238 | PUBWEAK EXTI3_IRQHandler
239 | SECTION .text:CODE:REORDER(1)
240 | EXTI3_IRQHandler
241 | B EXTI3_IRQHandler
242 |
243 | PUBWEAK EXTI4_IRQHandler
244 | SECTION .text:CODE:REORDER(1)
245 | EXTI4_IRQHandler
246 | B EXTI4_IRQHandler
247 |
248 | PUBWEAK DMA1_Channel1_IRQHandler
249 | SECTION .text:CODE:REORDER(1)
250 | DMA1_Channel1_IRQHandler
251 | B DMA1_Channel1_IRQHandler
252 |
253 | PUBWEAK DMA1_Channel2_IRQHandler
254 | SECTION .text:CODE:REORDER(1)
255 | DMA1_Channel2_IRQHandler
256 | B DMA1_Channel2_IRQHandler
257 |
258 | PUBWEAK DMA1_Channel3_IRQHandler
259 | SECTION .text:CODE:REORDER(1)
260 | DMA1_Channel3_IRQHandler
261 | B DMA1_Channel3_IRQHandler
262 |
263 | PUBWEAK DMA1_Channel4_IRQHandler
264 | SECTION .text:CODE:REORDER(1)
265 | DMA1_Channel4_IRQHandler
266 | B DMA1_Channel4_IRQHandler
267 |
268 | PUBWEAK DMA1_Channel5_IRQHandler
269 | SECTION .text:CODE:REORDER(1)
270 | DMA1_Channel5_IRQHandler
271 | B DMA1_Channel5_IRQHandler
272 |
273 | PUBWEAK DMA1_Channel6_IRQHandler
274 | SECTION .text:CODE:REORDER(1)
275 | DMA1_Channel6_IRQHandler
276 | B DMA1_Channel6_IRQHandler
277 |
278 | PUBWEAK DMA1_Channel7_IRQHandler
279 | SECTION .text:CODE:REORDER(1)
280 | DMA1_Channel7_IRQHandler
281 | B DMA1_Channel7_IRQHandler
282 |
283 | PUBWEAK ADC1_2_IRQHandler
284 | SECTION .text:CODE:REORDER(1)
285 | ADC1_2_IRQHandler
286 | B ADC1_2_IRQHandler
287 |
288 | PUBWEAK USB_HP_CAN1_TX_IRQHandler
289 | SECTION .text:CODE:REORDER(1)
290 | USB_HP_CAN1_TX_IRQHandler
291 | B USB_HP_CAN1_TX_IRQHandler
292 |
293 | PUBWEAK USB_LP_CAN1_RX0_IRQHandler
294 | SECTION .text:CODE:REORDER(1)
295 | USB_LP_CAN1_RX0_IRQHandler
296 | B USB_LP_CAN1_RX0_IRQHandler
297 |
298 | PUBWEAK CAN1_RX1_IRQHandler
299 | SECTION .text:CODE:REORDER(1)
300 | CAN1_RX1_IRQHandler
301 | B CAN1_RX1_IRQHandler
302 |
303 | PUBWEAK CAN1_SCE_IRQHandler
304 | SECTION .text:CODE:REORDER(1)
305 | CAN1_SCE_IRQHandler
306 | B CAN1_SCE_IRQHandler
307 |
308 | PUBWEAK EXTI9_5_IRQHandler
309 | SECTION .text:CODE:REORDER(1)
310 | EXTI9_5_IRQHandler
311 | B EXTI9_5_IRQHandler
312 |
313 | PUBWEAK TIM1_BRK_IRQHandler
314 | SECTION .text:CODE:REORDER(1)
315 | TIM1_BRK_IRQHandler
316 | B TIM1_BRK_IRQHandler
317 |
318 | PUBWEAK TIM1_UP_IRQHandler
319 | SECTION .text:CODE:REORDER(1)
320 | TIM1_UP_IRQHandler
321 | B TIM1_UP_IRQHandler
322 |
323 | PUBWEAK TIM1_TRG_COM_IRQHandler
324 | SECTION .text:CODE:REORDER(1)
325 | TIM1_TRG_COM_IRQHandler
326 | B TIM1_TRG_COM_IRQHandler
327 |
328 | PUBWEAK TIM1_CC_IRQHandler
329 | SECTION .text:CODE:REORDER(1)
330 | TIM1_CC_IRQHandler
331 | B TIM1_CC_IRQHandler
332 |
333 | PUBWEAK TIM2_IRQHandler
334 | SECTION .text:CODE:REORDER(1)
335 | TIM2_IRQHandler
336 | B TIM2_IRQHandler
337 |
338 | PUBWEAK TIM3_IRQHandler
339 | SECTION .text:CODE:REORDER(1)
340 | TIM3_IRQHandler
341 | B TIM3_IRQHandler
342 |
343 | PUBWEAK TIM4_IRQHandler
344 | SECTION .text:CODE:REORDER(1)
345 | TIM4_IRQHandler
346 | B TIM4_IRQHandler
347 |
348 | PUBWEAK I2C1_EV_IRQHandler
349 | SECTION .text:CODE:REORDER(1)
350 | I2C1_EV_IRQHandler
351 | B I2C1_EV_IRQHandler
352 |
353 | PUBWEAK I2C1_ER_IRQHandler
354 | SECTION .text:CODE:REORDER(1)
355 | I2C1_ER_IRQHandler
356 | B I2C1_ER_IRQHandler
357 |
358 | PUBWEAK I2C2_EV_IRQHandler
359 | SECTION .text:CODE:REORDER(1)
360 | I2C2_EV_IRQHandler
361 | B I2C2_EV_IRQHandler
362 |
363 | PUBWEAK I2C2_ER_IRQHandler
364 | SECTION .text:CODE:REORDER(1)
365 | I2C2_ER_IRQHandler
366 | B I2C2_ER_IRQHandler
367 |
368 | PUBWEAK SPI1_IRQHandler
369 | SECTION .text:CODE:REORDER(1)
370 | SPI1_IRQHandler
371 | B SPI1_IRQHandler
372 |
373 | PUBWEAK SPI2_IRQHandler
374 | SECTION .text:CODE:REORDER(1)
375 | SPI2_IRQHandler
376 | B SPI2_IRQHandler
377 |
378 | PUBWEAK USART1_IRQHandler
379 | SECTION .text:CODE:REORDER(1)
380 | USART1_IRQHandler
381 | B USART1_IRQHandler
382 |
383 | PUBWEAK USART2_IRQHandler
384 | SECTION .text:CODE:REORDER(1)
385 | USART2_IRQHandler
386 | B USART2_IRQHandler
387 |
388 | PUBWEAK USART3_IRQHandler
389 | SECTION .text:CODE:REORDER(1)
390 | USART3_IRQHandler
391 | B USART3_IRQHandler
392 |
393 | PUBWEAK EXTI15_10_IRQHandler
394 | SECTION .text:CODE:REORDER(1)
395 | EXTI15_10_IRQHandler
396 | B EXTI15_10_IRQHandler
397 |
398 | PUBWEAK RTCAlarm_IRQHandler
399 | SECTION .text:CODE:REORDER(1)
400 | RTCAlarm_IRQHandler
401 | B RTCAlarm_IRQHandler
402 |
403 | PUBWEAK USBWakeUp_IRQHandler
404 | SECTION .text:CODE:REORDER(1)
405 | USBWakeUp_IRQHandler
406 | B USBWakeUp_IRQHandler
407 |
408 | PUBWEAK TIM8_BRK_IRQHandler
409 | SECTION .text:CODE:REORDER(1)
410 | TIM8_BRK_IRQHandler
411 | B TIM8_BRK_IRQHandler
412 |
413 | PUBWEAK TIM8_UP_IRQHandler
414 | SECTION .text:CODE:REORDER(1)
415 | TIM8_UP_IRQHandler
416 | B TIM8_UP_IRQHandler
417 |
418 | PUBWEAK TIM8_TRG_COM_IRQHandler
419 | SECTION .text:CODE:REORDER(1)
420 | TIM8_TRG_COM_IRQHandler
421 | B TIM8_TRG_COM_IRQHandler
422 |
423 | PUBWEAK TIM8_CC_IRQHandler
424 | SECTION .text:CODE:REORDER(1)
425 | TIM8_CC_IRQHandler
426 | B TIM8_CC_IRQHandler
427 |
428 | PUBWEAK ADC3_IRQHandler
429 | SECTION .text:CODE:REORDER(1)
430 | ADC3_IRQHandler
431 | B ADC3_IRQHandler
432 |
433 | PUBWEAK FSMC_IRQHandler
434 | SECTION .text:CODE:REORDER(1)
435 | FSMC_IRQHandler
436 | B FSMC_IRQHandler
437 |
438 | PUBWEAK SDIO_IRQHandler
439 | SECTION .text:CODE:REORDER(1)
440 | SDIO_IRQHandler
441 | B SDIO_IRQHandler
442 |
443 | PUBWEAK TIM5_IRQHandler
444 | SECTION .text:CODE:REORDER(1)
445 | TIM5_IRQHandler
446 | B TIM5_IRQHandler
447 |
448 | PUBWEAK SPI3_IRQHandler
449 | SECTION .text:CODE:REORDER(1)
450 | SPI3_IRQHandler
451 | B SPI3_IRQHandler
452 |
453 | PUBWEAK UART4_IRQHandler
454 | SECTION .text:CODE:REORDER(1)
455 | UART4_IRQHandler
456 | B UART4_IRQHandler
457 |
458 | PUBWEAK UART5_IRQHandler
459 | SECTION .text:CODE:REORDER(1)
460 | UART5_IRQHandler
461 | B UART5_IRQHandler
462 |
463 | PUBWEAK TIM6_IRQHandler
464 | SECTION .text:CODE:REORDER(1)
465 | TIM6_IRQHandler
466 | B TIM6_IRQHandler
467 |
468 | PUBWEAK TIM7_IRQHandler
469 | SECTION .text:CODE:REORDER(1)
470 | TIM7_IRQHandler
471 | B TIM7_IRQHandler
472 |
473 | PUBWEAK DMA2_Channel1_IRQHandler
474 | SECTION .text:CODE:REORDER(1)
475 | DMA2_Channel1_IRQHandler
476 | B DMA2_Channel1_IRQHandler
477 |
478 | PUBWEAK DMA2_Channel2_IRQHandler
479 | SECTION .text:CODE:REORDER(1)
480 | DMA2_Channel2_IRQHandler
481 | B DMA2_Channel2_IRQHandler
482 |
483 | PUBWEAK DMA2_Channel3_IRQHandler
484 | SECTION .text:CODE:REORDER(1)
485 | DMA2_Channel3_IRQHandler
486 | B DMA2_Channel3_IRQHandler
487 |
488 | PUBWEAK DMA2_Channel4_5_IRQHandler
489 | SECTION .text:CODE:REORDER(1)
490 | DMA2_Channel4_5_IRQHandler
491 | B DMA2_Channel4_5_IRQHandler
492 |
493 |
494 | END
495 |
496 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
497 |
--------------------------------------------------------------------------------
/stm32f10x_flash.icf:
--------------------------------------------------------------------------------
1 | /*###ICF### Section handled by ICF editor, don't touch! ****/
2 | /*-Editor annotation file-*/
3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
4 | /*-Specials-*/
5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000;
6 | /*-Memory Regions-*/
7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
8 | define symbol __ICFEDIT_region_ROM_end__ = 0x080377FF;
9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
11 | /*-Sizes-*/
12 | define symbol __ICFEDIT_size_cstack__ = 0x400;
13 | define symbol __ICFEDIT_size_heap__ = 0x200;
14 | /**** End of ICF editor section. ###ICF###*/
15 |
16 |
17 | define memory mem with size = 4G;
18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
20 |
21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
23 |
24 | initialize by copy { readwrite };
25 | do not initialize { section .noinit };
26 |
27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
28 |
29 | place in ROM_region { readonly };
30 | place in RAM_region { readwrite,
31 | block CSTACK, block HEAP };
--------------------------------------------------------------------------------