├── .gitattributes ├── 1_Verilog ├── 1. Fibonacci │ ├── Fibonacci.png │ ├── Fibonacci.v │ ├── README.md │ ├── RTL Schematic.png │ ├── Simulation Output.png │ ├── Synthesis Schematic.png │ └── tb_Fibonacci.v ├── 10.FSM_with_3 │ ├── FSM3.png │ ├── FSM_3.v │ ├── Simulation.png │ ├── Synth.pdf │ └── fsm_3_sim.v ├── 11.Posedge_trigger_D_FF_using_mux │ ├── 21052025.png │ ├── Screenshot 2025-05-21 073726.png │ └── neg.png ├── 12.NBAvsBA │ ├── Screenshot 2025-06-06 054941.png │ ├── Screenshot 2025-06-06 055055.png │ ├── Screenshot 2025-06-06 055226.png │ ├── Screenshot 2025-06-06 055400.png │ ├── Screenshot 2025-06-06 055522.png │ ├── Screenshot 2025-06-06 055636.png │ ├── Screenshot 2025-06-06 060058.png │ ├── Screenshot 2025-06-06 060842.png │ ├── Screenshot 2025-06-06 064955.png │ ├── Screenshot 2025-06-06 071427.png │ └── Untitled.png ├── 13.Q1 │ └── Q1.png ├── 14.Q2 │ └── 962025.png ├── 15.Q3 │ ├── 10625.png │ └── Question.png ├── 16.Q4 │ ├── 11062025.png │ └── Question.png ├── 17.Q5 │ ├── 12062025.png │ └── Question1.png ├── 18.Q6 │ ├── 13062025.png │ └── Question1.png ├── 19.Q7 │ ├── 14062025.png │ └── Question1.png ├── 2. Logical_Effort.png ├── 20.Q8 │ └── 15062025.png ├── 21.Q9 │ ├── 16062025.png │ ├── Question.png │ ├── Simulation.png │ ├── seq1.v │ └── tb.v ├── 22.Q10 │ ├── 18062025.png │ └── Question.png ├── 23.Q11 │ ├── 19062025.png │ └── Question.png ├── 24.Q12 │ ├── 20062025.png │ └── Question.png ├── 25.Q13 │ ├── 21062025.png │ └── Question.png ├── 26.Q14 │ ├── 22062025.png │ ├── FSM_2.v │ ├── Question.pdf │ └── Schematic.pdf ├── 27.Q15 │ ├── 23062025.png │ ├── Equation.v │ ├── Question.png │ ├── RCA.v │ ├── Simulation Result .png │ ├── Synthesis_Result.png │ ├── fa.v │ ├── ha.v │ └── tb_Equation.v ├── 28.Q16 │ ├── 24062025.png │ └── Question.png ├── 29.Q17 │ ├── 06072025.png │ └── Two_Complement_Xor │ │ ├── Two_Complement_Xor.cache │ │ ├── sim │ │ │ └── ssm.db │ │ └── wt │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── xsim.wdf │ │ ├── Two_Complement_Xor.hw │ │ └── Two_Complement_Xor.lpr │ │ ├── Two_Complement_Xor.ip_user_files │ │ └── README.txt │ │ ├── Two_Complement_Xor.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── exor_p.dcp │ │ │ ├── exor_p.tcl │ │ │ ├── exor_p.vds │ │ │ ├── exor_p_utilization_synth.pb │ │ │ ├── exor_p_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ ├── Two_Complement_Xor.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ └── xsim │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── elaborate.bat │ │ │ ├── elaborate.log │ │ │ ├── glbl.v │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── two_tb.tcl │ │ │ ├── two_tb_behav.wdb │ │ │ ├── two_tb_vlog.prj │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── two_tb_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── TempBreakPointFile.txt │ │ │ │ ├── obj │ │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ │ ├── xsim_1.c │ │ │ │ │ └── xsim_1.win64.obj │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rlx │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimSettings.ini │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsimk.exe │ │ │ │ └── xsimkernel.log │ │ │ └── xil_defaultlib │ │ │ │ ├── exor_p.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── ha.sdb │ │ │ │ ├── two_tb.sdb │ │ │ │ └── xil_defaultlib.rlx │ │ │ ├── xsim.ini │ │ │ ├── xvlog.log │ │ │ └── xvlog.pb │ │ ├── Two_Complement_Xor.srcs │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── two_tb.v │ │ └── sources_1 │ │ │ └── new │ │ │ ├── exor.v │ │ │ └── ha.v │ │ └── Two_Complement_Xor.xpr ├── 3. Prob1 │ ├── RTL_Schematic.png │ ├── Sequence.png │ ├── Simulation_Result.png │ ├── Synthesis_Schematic.png │ ├── prob1.v │ ├── question.v │ └── tb_prob1.v ├── 30.Q18 │ ├── 07072025.png │ └── Question.png ├── 31.Q19 │ ├── 08072025.png │ └── Question.png ├── 32.Q20 │ ├── 09072025.png │ └── Question.png ├── 33.Q21 │ └── 10072025.png ├── 4.Prob2 │ ├── RTL_Schematic.png │ ├── Sequence2.png │ ├── Simulation_Resul.png │ ├── Synthesis_Schematic.png │ ├── sequence_by_4.v │ └── tb_seq_4.v ├── 5.Prob3 │ ├── Monitor_Result.v │ ├── Readme.txt │ ├── Schematic.pdf │ ├── Simulation.png │ ├── seq3.v │ └── test_seq3.v ├── 6.FSM for 2'complement │ ├── 2's Complement FSM.png │ ├── RTL_Schematic.pdf │ ├── Readme.txt │ ├── Simulation_Result.png │ ├── Synth_Schematic.pdf │ ├── tb_twocomp.v │ └── twos_comp.v ├── 7.Highest_Positions_of_Number │ ├── Highest_Number_Positions.png │ ├── MSB_3.v │ ├── Pe8x3.v │ ├── RTL_Schematic.pdf │ ├── Readme.txt │ ├── Simulation Result.png │ ├── Synth_Schematic.pdf │ ├── decoder3x8.v │ └── tb_msb3.v ├── 8.Counter_FSM │ ├── FSM1.png │ ├── Simulation Result.png │ ├── Synth_Schematic.png │ ├── fsm_counter.v │ ├── my_fsm_0.svg │ └── tb.v └── 9.Highest_Number_FSM │ ├── FSM2.png │ ├── FSM_1.v │ ├── Simulation_Result.png │ ├── Synth_Result.png │ ├── my_fsm_0.svg │ └── test_FSM1.v └── README.md /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bpvsr/2_Interview_Questions/HEAD/.gitattributes -------------------------------------------------------------------------------- /1_Verilog/1. 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