├── LICENSE ├── README.md ├── _config.yml ├── hdl ├── dsa_single.v └── dsa_two.v ├── img ├── Single Stage Delta-Sigma DAC.png └── Two Stages Delta Sigma.png └── papers ├── Design_and_FPGA_Implementation_of_a_2nd_Order_Adap.pdf ├── IJEIT1412201404_29.pdf ├── cicsyn-PahvMMLCKR.pdf ├── latice_delta_sigma.pdf └── magnesetal2003.pdf /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/README.md -------------------------------------------------------------------------------- /_config.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/_config.yml -------------------------------------------------------------------------------- /hdl/dsa_single.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/hdl/dsa_single.v -------------------------------------------------------------------------------- /hdl/dsa_two.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/hdl/dsa_two.v -------------------------------------------------------------------------------- /img/Single Stage Delta-Sigma DAC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/img/Single Stage Delta-Sigma DAC.png -------------------------------------------------------------------------------- /img/Two Stages Delta Sigma.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/img/Two Stages Delta Sigma.png -------------------------------------------------------------------------------- /papers/Design_and_FPGA_Implementation_of_a_2nd_Order_Adap.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/papers/Design_and_FPGA_Implementation_of_a_2nd_Order_Adap.pdf -------------------------------------------------------------------------------- /papers/IJEIT1412201404_29.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/papers/IJEIT1412201404_29.pdf -------------------------------------------------------------------------------- /papers/cicsyn-PahvMMLCKR.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/papers/cicsyn-PahvMMLCKR.pdf -------------------------------------------------------------------------------- /papers/latice_delta_sigma.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/papers/latice_delta_sigma.pdf -------------------------------------------------------------------------------- /papers/magnesetal2003.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/briansune/Delta-Sigma-DAC-Verilog/HEAD/papers/magnesetal2003.pdf --------------------------------------------------------------------------------