├── .gitignore ├── LICENSE.md ├── README.md ├── TODO.md ├── ccs_configs └── 28335ModbusCSettings.xml ├── contrib ├── DSP2833x │ ├── DSP2833x_common │ │ ├── cmd │ │ │ ├── 28332_RAM_lnk.cmd │ │ │ ├── 28334_RAM_lnk.cmd │ │ │ ├── 28335_RAM_lnk.cmd │ │ │ ├── F28332.cmd │ │ │ ├── F28334.cmd │ │ │ └── F28335.cmd │ │ ├── gel │ │ │ ├── ccsv4 │ │ │ │ ├── f28232.gel │ │ │ │ ├── f28234.gel │ │ │ │ ├── f28235.gel │ │ │ │ ├── f28332.gel │ │ │ │ ├── f28334.gel │ │ │ │ └── f28335.gel │ │ │ ├── f28232.gel │ │ │ ├── f28234.gel │ │ │ ├── f28235.gel │ │ │ ├── f28332.gel │ │ │ ├── f28334.gel │ │ │ └── f28335.gel │ │ ├── include │ │ │ ├── DSP2833x_DefaultISR.h │ │ │ ├── DSP2833x_Dma_defines.h │ │ │ ├── DSP2833x_Examples.h │ │ │ ├── DSP2833x_GlobalPrototypes.h │ │ │ ├── DSP2833x_I2C_defines.h │ │ │ ├── DSP2833x_SWPrioritizedIsrLevels.h │ │ │ ├── DSP2833x_ePwm_defines.h │ │ │ ├── DSP28x_Project.h │ │ │ ├── IQmathLib.h │ │ │ ├── SFO.h │ │ │ └── SFO_V5.h │ │ ├── lib │ │ │ ├── IQmath.lib │ │ │ ├── IQmath_fpu32.lib │ │ │ ├── SFO_TI_Build.lib │ │ │ ├── SFO_TI_Build_V5.lib │ │ │ ├── SFO_TI_Build_V5B.lib │ │ │ ├── SFO_TI_Build_V5B_fpu.lib │ │ │ ├── SFO_TI_Build_V5_fpu.lib │ │ │ └── SFO_TI_Build_fpu.lib │ │ └── source │ │ │ ├── DSP2833x_ADC_cal.asm │ │ │ ├── DSP2833x_Adc.c │ │ │ ├── DSP2833x_CSMPasswords.asm │ │ │ ├── DSP2833x_CodeStartBranch.asm │ │ │ ├── DSP2833x_CpuTimers.c │ │ │ ├── DSP2833x_DBGIER.asm │ │ │ ├── DSP2833x_DMA.c │ │ │ ├── DSP2833x_DefaultIsr.c │ │ │ ├── DSP2833x_DisInt.asm │ │ │ ├── DSP2833x_ECan.c │ │ │ ├── DSP2833x_ECap.c │ │ │ ├── DSP2833x_EPwm.c │ │ │ ├── DSP2833x_EQep.c │ │ │ ├── DSP2833x_Gpio.c │ │ │ ├── DSP2833x_I2C.c │ │ │ ├── DSP2833x_McBSP.c │ │ │ ├── DSP2833x_MemCopy.c │ │ │ ├── DSP2833x_PieCtrl.c │ │ │ ├── DSP2833x_PieVect.c │ │ │ ├── DSP2833x_SWPrioritizedDefaultIsr.c │ │ │ ├── DSP2833x_SWPrioritizedPieVect.c │ │ │ ├── DSP2833x_Sci.c │ │ │ ├── DSP2833x_Spi.c │ │ │ ├── DSP2833x_SysCtrl.c │ │ │ ├── DSP2833x_Xintf.c │ │ │ └── DSP2833x_usDelay.asm │ └── DSP2833x_headers │ │ ├── cmd │ │ ├── DSP2833x_Headers_BIOS.cmd │ │ └── DSP2833x_Headers_nonBIOS.cmd │ │ ├── gel │ │ ├── DSP2833x_DualMap_EPWM.gel │ │ └── DSP2833x_Peripheral.gel │ │ ├── include │ │ ├── DSP2833x_Adc.h │ │ ├── DSP2833x_CpuTimers.h │ │ ├── DSP2833x_DMA.h │ │ ├── DSP2833x_DevEmu.h │ │ ├── DSP2833x_Device.h │ │ ├── DSP2833x_ECan.h │ │ ├── DSP2833x_ECap.h │ │ ├── DSP2833x_EPwm.h │ │ ├── DSP2833x_EQep.h │ │ ├── DSP2833x_Gpio.h │ │ ├── DSP2833x_I2c.h │ │ ├── DSP2833x_McBSP.h │ │ ├── DSP2833x_PieCtrl.h │ │ ├── DSP2833x_PieVect.h │ │ ├── DSP2833x_Sci.h │ │ ├── DSP2833x_Spi.h │ │ ├── DSP2833x_SysCtrl.h │ │ ├── DSP2833x_XIntrupt.h │ │ └── DSP2833x_Xintf.h │ │ └── source │ │ └── DSP2833x_GlobalVariableDefs.c ├── dspProfiling │ ├── Profiling.c │ └── Profiling.h └── modbus │ ├── Crc.c │ ├── ModbusData.c │ ├── ModbusDataHandler.c │ ├── ModbusDataMap.c │ ├── ModbusSlave.c │ ├── include │ ├── Crc.h │ ├── DataTypes.h │ ├── Log.h │ ├── ModbusData.h │ ├── ModbusDataHandler.h │ ├── ModbusDataMap.h │ ├── ModbusDataMapTests.h │ ├── ModbusDefinitions.h │ ├── ModbusSettings.h │ ├── ModbusSlave.h │ ├── Serial.h │ └── Timer.h │ └── plataform │ └── DSP2833x │ ├── Serial.c │ ├── Timer.c │ └── include │ ├── DSP2833x_CpuTimers.h │ └── DSP2833x_Sci.h ├── makeCCSv3.bat ├── makeCCSv3.sh ├── src ├── 28335_RAM_lnk.cmd ├── DSP2833x_ADC_cal.asm ├── DSP2833x_CodeStartBranch.asm ├── DSP2833x_DefaultIsr.c ├── DSP2833x_GlobalVariableDefs.c ├── DSP2833x_Headers_nonBIOS.cmd ├── DSP2833x_SysCtrl.c ├── DSP2833x_usDelay.asm └── main.c └── tests ├── README.md ├── unit-test-client ├── unit-test-client.c └── unit-test.h /.gitignore: -------------------------------------------------------------------------------- 1 | *.pydevproject 2 | .metadata 3 | .ccsproject 4 | .project 5 | .gradle 6 | bin/ 7 | tmp/ 8 | *.tmp 9 | *.bak 10 | *.swp 11 | *~.nib 12 | local.properties 13 | .settings/ 14 | Debug/ 15 | .loadpath 16 | *~ 17 | 18 | # External tool builders 19 | .externalToolBuilders/ 20 | 21 | # Locally stored "Eclipse launch configurations" 22 | *.launch 23 | 24 | # CDT-specific 25 | .cproject 26 | 27 | # PDT-specific 28 | .buildpath 29 | 30 | # sbteclipse plugin 31 | .target 32 | 33 | # TeXlipse plugin 34 | .texlipse 35 | 36 | # CCSv3 Output folder 37 | CCSv3/ 38 | CCSv3.zip 39 | 40 | # Project Specific 41 | ModbusDataMap*.h 42 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 28335ModbusSlave 2 | ================ 3 | 4 | MODBUS implementation for F28335 DSP. This was developed by Bruno Luiz (@brunoluiz) to a project for TRACTEBEL in partnership with CERTI Foundation. 5 | 6 | Installing 7 | ========== 8 | 9 | Structure 10 | --------- 11 | All modbus implementation are at ```contrib/modbus``` folder. We suggest you to put all your code at source folder. 12 | 13 | If you need any DSP2833x header file you can find it at ```contrib/DSP2833x``` 14 | 15 | Include paths 16 | ------------- 17 | If you use Code Composer 4 (or later), import the C/C++ Project Settings from ```ccs_configs/28335ModbusCSettings.xml``` file. 18 | 19 | Another way to include the right paths is changing the "Include Options". At CCS 6.x you have to go to Project Settings (ALT+ENTER), then Build ``` C200 Compiler ``` Include Options. You've to include the following paths: 20 | 21 | * ```contrib/modbus/include``` 22 | * ```contrib/modbus/plataform/ DSP2833x/include``` 23 | * ```contrib/DSP2833x/DSP2833x_common/include``` 24 | * ```contrib/DSP2833x/DSP2833x_headers/include``` 25 | 26 | If your project uses custom DSP2833x headers/files you don't need the two last paths. 27 | 28 | Don't forget to exclude from compilation the ```contrib/dspProfiling``` and ```contrib/DSP2833x``` (right mouse click ``` Exclude from Build). 29 | 30 | Code Composers 3 or ealier versions 31 | ----------------------------------- 32 | If you use CodeComposer v3.x or earlier, probably your directory structure uses PROJECT/Source and PROJECT/Include to control the src and header files. To make it more easier for your use, you can run makeCSSv3.bat (or makeCSSv3.sh if you use Linux) to create a folder with the same structure of CCSv3. 33 | 34 | At the batch file you can configure a different folder (CCSv3OutputDir), but the default action is create a "CCSv3" folder at the MODBUS root folder. If you don't have the serial and timer headers from Texas, I suggest you to enable their copy process changing the "CopySerialTimerHeader" variable. 35 | 36 | Implementing 37 | ============ 38 | 39 | Normally this code will be implemented at ```main.c``` 40 | 41 | 1. Include the ModbusSlave.h header 42 | 2. Change the configuration files: 43 | a. ```ModbusSettings.h```: baudrate, parity, debug modes, buffer size (the max size of a frame)... 44 | b. ```Serial.c``` & ```Timer.c```: if your CLOCK or LSPCLK are different from 150 e 37500000, change those files 45 | 3. Declare the modbus object with ```ModbusSlave mb;``` 46 | 4. Initialize modbus object with ```mb = construct_ModbusSlave();``` 47 | 5. At some loop, call modbus object with ```mb.loopStates(&mb);``` 48 | 49 | Using memory map 50 | ================ 51 | 52 | To use the memory map you will need to change the ```ModbusDataMap.h``` file with the variables that you want. 53 | 54 | Don't forget that coils/inputs are Uint8 values! By default, the holding registers are meant to be 32 bits (long or float). If you want to use 16 bits variables you can enable that disabling MB_32_BITS_REGISTERS on ```ModbusSettings.h```. 55 | 56 | Observation: the data map is specified at ```ModbusDataMap.h``` but if you want to hold different data maps and just change them before compile the code, you can change the ```MB_DATA_MAP``` constant at ```ModbusSettings.h```. By default it is ```ModbusDataMap.h```. 57 | -------------------------------------------------------------------------------- /TODO.md: -------------------------------------------------------------------------------- 1 | - Check why Modbus Data maps are not changing (need a make clean before anything) 2 | - Comment the code 3 | - Build a better documentation (explaining the lifecycle) 4 | -------------------------------------------------------------------------------- /ccs_configs/28335ModbusCSettings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 |
4 | 5 | /${ProjName}/contrib/DSP2833x/DSP2833x_common/include 6 | /${ProjName}/contrib/DSP2833x/DSP2833x_headers/include 7 | /${ProjName}/contrib/modbus/plataform/DSP2833x/include 8 | /${ProjName}/contrib/modbus/include 9 | c:/ti/ccsv6/tools/compiler/c2000_6.2.7/include 10 | 11 | 12 | 13 | /${ProjName}/contrib/DSP2833x/DSP2833x_common/include 14 | /${ProjName}/contrib/DSP2833x/DSP2833x_headers/include 15 | /${ProjName}/contrib/modbus/plataform/DSP2833x/include 16 | /${ProjName}/contrib/modbus/include 17 | c:/ti/ccsv6/tools/compiler/c2000_6.2.7/include 18 | 19 | 20 | 21 | /${ProjName}/contrib/DSP2833x/DSP2833x_common/include 22 | /${ProjName}/contrib/DSP2833x/DSP2833x_headers/include 23 | /${ProjName}/contrib/modbus/plataform/DSP2833x/include 24 | /${ProjName}/contrib/modbus/include 25 | c:/ti/ccsv6/tools/compiler/c2000_6.2.7/include 26 | 27 | 28 | 29 | /${ProjName}/contrib/DSP2833x/DSP2833x_common/include 30 | /${ProjName}/contrib/DSP2833x/DSP2833x_headers/include 31 | /${ProjName}/contrib/modbus/plataform/DSP2833x/include 32 | /${ProjName}/contrib/modbus/include 33 | c:/ti/ccsv6/tools/compiler/c2000_6.2.7/include 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 |
46 |
47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 |
69 | 70 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/cmd/28332_RAM_lnk.cmd: -------------------------------------------------------------------------------- 1 | /* 2 | // TI File $Revision: /main/10 $ 3 | // Checkin $Date: April 15, 2009 09:57:22 $ 4 | //########################################################################### 5 | // 6 | // FILE: 28332_RAM_lnk.cmd 7 | // 8 | // TITLE: Linker Command File For 28332 examples that run out of RAM 9 | // 10 | // This ONLY includes all SARAM blocks on the 28332 device. 11 | // This does not include flash or OTP. 12 | // 13 | // Keep in mind that L0 and L1 are protected by the code 14 | // security module. 15 | // 16 | // What this means is in most cases you will want to move to 17 | // another memory map file which has more memory defined. 18 | // 19 | //########################################################################### 20 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 21 | // $Release Date: August 4, 2009 $ 22 | //########################################################################### 23 | */ 24 | 25 | /* ====================================================== 26 | // For Code Composer Studio V2.2 and later 27 | // --------------------------------------- 28 | // In addition to this memory linker command file, 29 | // add the header linker command file directly to the project. 30 | // The header linker command file is required to link the 31 | // peripheral structures to the proper locations within 32 | // the memory map. 33 | // 34 | // The header linker files are found in \DSP2833x_Headers\cmd 35 | // 36 | // For BIOS applications add: DSP2833x_Headers_BIOS.cmd 37 | // For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd 38 | ========================================================= */ 39 | 40 | /* ====================================================== 41 | // For Code Composer Studio prior to V2.2 42 | // -------------------------------------- 43 | // 1) Use one of the following -l statements to include the 44 | // header linker command file in the project. The header linker 45 | // file is required to link the peripheral structures to the proper 46 | // locations within the memory map */ 47 | 48 | /* Uncomment this line to include file only for non-BIOS applications */ 49 | /* -l DSP2833x_Headers_nonBIOS.cmd */ 50 | 51 | /* Uncomment this line to include file only for BIOS applications */ 52 | /* -l DSP2833x_Headers_BIOS.cmd */ 53 | 54 | /* 2) In your project add the path to \DSP2833x_headers\cmd to the 55 | library search path under project->build options, linker tab, 56 | library search path (-i). 57 | /*========================================================= */ 58 | 59 | /* Define the memory block start/length for the F28332 60 | PAGE 0 will be used to organize program sections 61 | PAGE 1 will be used to organize data sections 62 | 63 | Notes: 64 | Memory blocks on F28332 are uniform (ie same 65 | physical memory) in both PAGE 0 and PAGE 1. 66 | That is the same memory region should not be 67 | defined for both PAGE 0 and PAGE 1. 68 | Doing so will result in corruption of program 69 | and/or data. 70 | 71 | L0/L1/L2 and L3 memory blocks are mirrored - that is 72 | they can be accessed in high memory or low memory. 73 | For simplicity only one instance is used in this 74 | linker file. 75 | 76 | Contiguous SARAM memory blocks can be combined 77 | if required to create a larger memory block. 78 | */ 79 | 80 | 81 | MEMORY 82 | { 83 | PAGE 0 : 84 | /* BEGIN is used for the "boot to SARAM" bootloader mode */ 85 | 86 | BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ 87 | RAMM0 : origin = 0x000050, length = 0x0003B0 88 | 89 | RAML0 : origin = 0x008000, length = 0x001000 90 | RAML1 : origin = 0x009000, length = 0x001000 91 | RAML2 : origin = 0x00A000, length = 0x001000 92 | RAML3 : origin = 0x00B000, length = 0x001000 93 | ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ 94 | CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ 95 | CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ 96 | ADC_CAL : origin = 0x380080, length = 0x000009 97 | RESET : origin = 0x3FFFC0, length = 0x000002 98 | IQTABLES : origin = 0x3FE000, length = 0x000b50 99 | IQTABLES2 : origin = 0x3FEB50, length = 0x00008c 100 | FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 101 | BOOTROM : origin = 0x3FF27C, length = 0x000D44 102 | 103 | 104 | 105 | 106 | PAGE 1 : 107 | /* BOOT_RSVD is used by the boot ROM for stack. */ 108 | /* This section is only reserved to keep the BOOT ROM from */ 109 | /* corrupting this area during the debug process */ 110 | 111 | BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ 112 | RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ 113 | RAML4 : origin = 0x00C000, length = 0x001000 114 | RAML5 : origin = 0x00D000, length = 0x001000 115 | ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ 116 | } 117 | 118 | 119 | SECTIONS 120 | { 121 | /* Setup for "boot to SARAM" mode: 122 | The codestart section (found in DSP28_CodeStartBranch.asm) 123 | re-directs execution to the start of user code. */ 124 | codestart : > BEGIN, PAGE = 0 125 | ramfuncs : > RAML0, PAGE = 0 126 | .text : > RAML1, PAGE = 0 127 | .cinit : > RAML0, PAGE = 0 128 | .pinit : > RAML0, PAGE = 0 129 | .switch : > RAML0, PAGE = 0 130 | 131 | .stack : > RAMM1, PAGE = 1 132 | .ebss : > RAML4, PAGE = 1 133 | .econst : > RAML5, PAGE = 1 134 | .esysmem : > RAMM1, PAGE = 1 135 | 136 | IQmath : > RAML1, PAGE = 0 137 | IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD 138 | 139 | /* Uncomment the section below if calling the IQNexp() or IQexp() 140 | functions from the IQMath.lib library in order to utilize the 141 | relevant IQ Math table in Boot ROM (This saves space and Boot ROM 142 | is 1 wait-state). If this section is not uncommented, IQmathTables2 143 | will be loaded into other memory (SARAM, Flash, etc.) and will take 144 | up space, but 0 wait-state is possible. 145 | */ 146 | /* 147 | IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 148 | { 149 | 150 | IQmath.lib (IQmathTablesRam) 151 | 152 | } 153 | */ 154 | 155 | FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 156 | 157 | DMARAML4 : > RAML4, PAGE = 1 158 | DMARAML5 : > RAML5, PAGE = 1 159 | 160 | ZONE7DATA : > ZONE7B, PAGE = 1 161 | 162 | 163 | .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ 164 | csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ 165 | csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ 166 | 167 | /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ 168 | .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD 169 | 170 | 171 | } 172 | 173 | /* 174 | //=========================================================================== 175 | // End of file. 176 | //=========================================================================== 177 | */ 178 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/DSP2833x_DefaultISR.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:45:37 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_DefaultIsr.h 6 | // 7 | // TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_DEFAULT_ISR_H 15 | #define DSP2833x_DEFAULT_ISR_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | 22 | //--------------------------------------------------------------------------- 23 | // Default Interrupt Service Routine Declarations: 24 | // 25 | // The following function prototypes are for the 26 | // default ISR routines used with the default PIE vector table. 27 | // This default vector table is found in the DSP2833x_PieVect.h 28 | // file. 29 | // 30 | 31 | // Non-Peripheral Interrupts: 32 | interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 33 | interrupt void INT14_ISR(void); // CPU-Timer2 34 | interrupt void DATALOG_ISR(void); // Datalogging interrupt 35 | interrupt void RTOSINT_ISR(void); // RTOS interrupt 36 | interrupt void EMUINT_ISR(void); // Emulation interrupt 37 | interrupt void NMI_ISR(void); // Non-maskable interrupt 38 | interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP 39 | interrupt void USER1_ISR(void); // User Defined trap 1 40 | interrupt void USER2_ISR(void); // User Defined trap 2 41 | interrupt void USER3_ISR(void); // User Defined trap 3 42 | interrupt void USER4_ISR(void); // User Defined trap 4 43 | interrupt void USER5_ISR(void); // User Defined trap 5 44 | interrupt void USER6_ISR(void); // User Defined trap 6 45 | interrupt void USER7_ISR(void); // User Defined trap 7 46 | interrupt void USER8_ISR(void); // User Defined trap 8 47 | interrupt void USER9_ISR(void); // User Defined trap 9 48 | interrupt void USER10_ISR(void); // User Defined trap 10 49 | interrupt void USER11_ISR(void); // User Defined trap 11 50 | interrupt void USER12_ISR(void); // User Defined trap 12 51 | 52 | // Group 1 PIE Interrupt Service Routines: 53 | interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR 54 | interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR 55 | interrupt void XINT1_ISR(void); // External interrupt 1 56 | interrupt void XINT2_ISR(void); // External interrupt 2 57 | interrupt void ADCINT_ISR(void); // ADC 58 | interrupt void TINT0_ISR(void); // Timer 0 59 | interrupt void WAKEINT_ISR(void); // WD 60 | 61 | // Group 2 PIE Interrupt Service Routines: 62 | interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 63 | interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 64 | interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 65 | interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 66 | interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 67 | interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 68 | 69 | // Group 3 PIE Interrupt Service Routines: 70 | interrupt void EPWM1_INT_ISR(void); // EPWM-1 71 | interrupt void EPWM2_INT_ISR(void); // EPWM-2 72 | interrupt void EPWM3_INT_ISR(void); // EPWM-3 73 | interrupt void EPWM4_INT_ISR(void); // EPWM-4 74 | interrupt void EPWM5_INT_ISR(void); // EPWM-5 75 | interrupt void EPWM6_INT_ISR(void); // EPWM-6 76 | 77 | // Group 4 PIE Interrupt Service Routines: 78 | interrupt void ECAP1_INT_ISR(void); // ECAP-1 79 | interrupt void ECAP2_INT_ISR(void); // ECAP-2 80 | interrupt void ECAP3_INT_ISR(void); // ECAP-3 81 | interrupt void ECAP4_INT_ISR(void); // ECAP-4 82 | interrupt void ECAP5_INT_ISR(void); // ECAP-5 83 | interrupt void ECAP6_INT_ISR(void); // ECAP-6 84 | 85 | // Group 5 PIE Interrupt Service Routines: 86 | interrupt void EQEP1_INT_ISR(void); // EQEP-1 87 | interrupt void EQEP2_INT_ISR(void); // EQEP-2 88 | 89 | // Group 6 PIE Interrupt Service Routines: 90 | interrupt void SPIRXINTA_ISR(void); // SPI-A 91 | interrupt void SPITXINTA_ISR(void); // SPI-A 92 | interrupt void MRINTA_ISR(void); // McBSP-A 93 | interrupt void MXINTA_ISR(void); // McBSP-A 94 | interrupt void MRINTB_ISR(void); // McBSP-B 95 | interrupt void MXINTB_ISR(void); // McBSP-B 96 | 97 | // Group 7 PIE Interrupt Service Routines: 98 | interrupt void DINTCH1_ISR(void); // DMA-Channel 1 99 | interrupt void DINTCH2_ISR(void); // DMA-Channel 2 100 | interrupt void DINTCH3_ISR(void); // DMA-Channel 3 101 | interrupt void DINTCH4_ISR(void); // DMA-Channel 4 102 | interrupt void DINTCH5_ISR(void); // DMA-Channel 5 103 | interrupt void DINTCH6_ISR(void); // DMA-Channel 6 104 | 105 | // Group 8 PIE Interrupt Service Routines: 106 | interrupt void I2CINT1A_ISR(void); // I2C-A 107 | interrupt void I2CINT2A_ISR(void); // I2C-A 108 | interrupt void SCIRXINTC_ISR(void); // SCI-C 109 | interrupt void SCITXINTC_ISR(void); // SCI-C 110 | 111 | // Group 9 PIE Interrupt Service Routines: 112 | interrupt void SCIRXINTA_ISR(void); // SCI-A 113 | interrupt void SCITXINTA_ISR(void); // SCI-A 114 | interrupt void SCIRXINTB_ISR(void); // SCI-B 115 | interrupt void SCITXINTB_ISR(void); // SCI-B 116 | interrupt void ECAN0INTA_ISR(void); // eCAN-A 117 | interrupt void ECAN1INTA_ISR(void); // eCAN-A 118 | interrupt void ECAN0INTB_ISR(void); // eCAN-B 119 | interrupt void ECAN1INTB_ISR(void); // eCAN-B 120 | 121 | // Group 10 PIE Interrupt Service Routines: 122 | 123 | // Group 11 PIE Interrupt Service Routines: 124 | 125 | // Group 12 PIE Interrupt Service Routines: 126 | interrupt void XINT3_ISR(void); // External interrupt 3 127 | interrupt void XINT4_ISR(void); // External interrupt 4 128 | interrupt void XINT5_ISR(void); // External interrupt 5 129 | interrupt void XINT6_ISR(void); // External interrupt 6 130 | interrupt void XINT7_ISR(void); // External interrupt 7 131 | interrupt void LVF_ISR(void); // Latched overflow flag 132 | interrupt void LUF_ISR(void); // Latched underflow flag 133 | 134 | // Catch-all for Reserved Locations For testing purposes: 135 | interrupt void PIE_RESERVED(void); // Reserved for test 136 | interrupt void rsvd_ISR(void); // for test 137 | interrupt void INT_NOTUSED_ISR(void); // for unused interrupts 138 | 139 | #ifdef __cplusplus 140 | } 141 | #endif /* extern "C" */ 142 | 143 | #endif // end of DSP2833x_DEFAULT_ISR_H definition 144 | 145 | //=========================================================================== 146 | // End of file. 147 | //=========================================================================== 148 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/DSP2833x_Dma_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: August 14, 2007 16:32:29 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Dma_defines.h 6 | // 7 | // TITLE: #defines used in DMA examples 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_DMA_DEFINES_H 15 | #define DSP2833x_DMA_DEFINES_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | // MODE 23 | //========================== 24 | // PERINTSEL bits 25 | #define DMA_SEQ1INT 1 26 | #define DMA_SEQ2INT 2 27 | #define DMA_XINT1 3 28 | #define DMA_XINT2 4 29 | #define DMA_XINT3 5 30 | #define DMA_XINT4 6 31 | #define DMA_XINT5 7 32 | #define DMA_XINT6 8 33 | #define DMA_XINT7 9 34 | #define DMA_XINT13 10 35 | #define DMA_TINT0 11 36 | #define DMA_TINT1 12 37 | #define DMA_TINT2 13 38 | #define DMA_MXEVTA 14 39 | #define DMA_MREVTA 15 40 | #define DMA_MXREVTB 16 41 | #define DMA_MREVTB 17 42 | // OVERINTE bit 43 | #define OVRFLOW_DISABLE 0x0 44 | #define OVEFLOW_ENABLE 0x1 45 | // PERINTE bit 46 | #define PERINT_DISABLE 0x0 47 | #define PERINT_ENABLE 0x1 48 | // CHINTMODE bits 49 | #define CHINT_BEGIN 0x0 50 | #define CHINT_END 0x1 51 | // ONESHOT bits 52 | #define ONESHOT_DISABLE 0x0 53 | #define ONESHOT_ENABLE 0x1 54 | // CONTINOUS bit 55 | #define CONT_DISABLE 0x0 56 | #define CONT_ENABLE 0x1 57 | // SYNCE bit 58 | #define SYNC_DISABLE 0x0 59 | #define SYNC_ENABLE 0x1 60 | // SYNCSEL bit 61 | #define SYNC_SRC 0x0 62 | #define SYNC_DST 0x1 63 | // DATASIZE bit 64 | #define SIXTEEN_BIT 0x0 65 | #define THIRTYTWO_BIT 0x1 66 | // CHINTE bit 67 | #define CHINT_DISABLE 0x0 68 | #define CHINT_ENABLE 0x1 69 | 70 | 71 | 72 | 73 | #ifdef __cplusplus 74 | } 75 | #endif /* extern "C" */ 76 | 77 | #endif // - end of DSP2833x_EPWM_DEFINES_H 78 | 79 | //=========================================================================== 80 | // End of file. 81 | //=========================================================================== 82 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/DSP2833x_Examples.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/9 $ 2 | // Checkin $Date: July 2, 2008 14:31:12 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Examples.h 6 | // 7 | // TITLE: DSP2833x Device Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_EXAMPLES_H 15 | #define DSP2833x_EXAMPLES_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | /*----------------------------------------------------------------------------- 24 | Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. 25 | -----------------------------------------------------------------------------*/ 26 | //#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT 27 | //#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT 28 | #define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT 29 | //#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT 30 | 31 | #define DSP28_PLLCR 10 32 | //#define DSP28_PLLCR 9 33 | //#define DSP28_PLLCR 8 34 | //#define DSP28_PLLCR 7 35 | //#define DSP28_PLLCR 6 36 | //#define DSP28_PLLCR 5 37 | //#define DSP28_PLLCR 4 38 | //#define DSP28_PLLCR 3 39 | //#define DSP28_PLLCR 2 40 | //#define DSP28_PLLCR 1 41 | //#define DSP28_PLLCR 0 // PLL is bypassed in this mode 42 | //---------------------------------------------------------------------------- 43 | 44 | 45 | /*----------------------------------------------------------------------------- 46 | Specify the clock rate of the CPU (SYSCLKOUT) in nS. 47 | 48 | Take into account the input clock frequency and the PLL multiplier 49 | selected in step 1. 50 | 51 | Use one of the values provided, or define your own. 52 | The trailing L is required tells the compiler to treat 53 | the number as a 64-bit value. 54 | 55 | Only one statement should be uncommented. 56 | 57 | Example 1:150 MHz devices: 58 | CLKIN is a 30MHz crystal. 59 | 60 | In step 1 the user specified PLLCR = 0xA for a 61 | 150Mhz CPU clock (SYSCLKOUT = 150MHz). 62 | 63 | In this case, the CPU_RATE will be 6.667L 64 | Uncomment the line: #define CPU_RATE 6.667L 65 | 66 | Example 2: 100 MHz devices: 67 | CLKIN is a 20MHz crystal. 68 | 69 | In step 1 the user specified PLLCR = 0xA for a 70 | 100Mhz CPU clock (SYSCLKOUT = 100MHz). 71 | 72 | In this case, the CPU_RATE will be 10.000L 73 | Uncomment the line: #define CPU_RATE 10.000L 74 | -----------------------------------------------------------------------------*/ 75 | #define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) 76 | //#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) 77 | //#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) 78 | //#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) 79 | //#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) 80 | //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) 81 | //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) 82 | //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) 83 | //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) 84 | //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) 85 | //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) 86 | 87 | //---------------------------------------------------------------------------- 88 | 89 | /*----------------------------------------------------------------------------- 90 | Target device (in DSP2833x_Device.h) determines CPU frequency 91 | (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz 92 | (for 28332). User does not have to change anything here. 93 | -----------------------------------------------------------------------------*/ 94 | #if DSP28_28332 // DSP28_28332 device only 95 | #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) 96 | #define CPU_FRQ_150MHZ 0 97 | #else 98 | #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 99 | #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT 100 | #endif 101 | 102 | 103 | //--------------------------------------------------------------------------- 104 | // Include Example Header Files: 105 | // 106 | 107 | #include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the 108 | // .c files. 109 | 110 | #include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples. 111 | #include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. 112 | #include "DSP2833x_I2C_defines.h" // Macros used for I2C examples. 113 | 114 | #define PARTNO_28335 0xEF 115 | #define PARTNO_28334 0xEE 116 | #define PARTNO_28332 0xED 117 | #define PARTNO_28235 0xE8 118 | #define PARTNO_28234 0xE7 119 | #define PARTNO_28232 0xE6 120 | 121 | 122 | // Include files not used with DSP/BIOS 123 | #ifndef DSP28_BIOS 124 | #include "DSP2833x_DefaultISR.h" 125 | #endif 126 | 127 | 128 | // DO NOT MODIFY THIS LINE. 129 | #define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) 130 | 131 | 132 | #ifdef __cplusplus 133 | } 134 | #endif /* extern "C" */ 135 | 136 | #endif // end of DSP2833x_EXAMPLES_H definition 137 | 138 | 139 | //=========================================================================== 140 | // End of file. 141 | //=========================================================================== 142 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/DSP2833x_I2C_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: April 16, 2008 17:16:47 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_I2cExample.h 6 | // 7 | // TITLE: 2833x I2C Example Code Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_I2C_DEFINES_H 15 | #define DSP2833x_I2C_DEFINES_H 16 | 17 | //-------------------------------------------- 18 | // Defines 19 | //-------------------------------------------- 20 | 21 | // Error Messages 22 | #define I2C_ERROR 0xFFFF 23 | #define I2C_ARB_LOST_ERROR 0x0001 24 | #define I2C_NACK_ERROR 0x0002 25 | #define I2C_BUS_BUSY_ERROR 0x1000 26 | #define I2C_STP_NOT_READY_ERROR 0x5555 27 | #define I2C_NO_FLAGS 0xAAAA 28 | #define I2C_SUCCESS 0x0000 29 | 30 | // Clear Status Flags 31 | #define I2C_CLR_AL_BIT 0x0001 32 | #define I2C_CLR_NACK_BIT 0x0002 33 | #define I2C_CLR_ARDY_BIT 0x0004 34 | #define I2C_CLR_RRDY_BIT 0x0008 35 | #define I2C_CLR_SCD_BIT 0x0020 36 | 37 | // Interrupt Source Messages 38 | #define I2C_NO_ISRC 0x0000 39 | #define I2C_ARB_ISRC 0x0001 40 | #define I2C_NACK_ISRC 0x0002 41 | #define I2C_ARDY_ISRC 0x0003 42 | #define I2C_RX_ISRC 0x0004 43 | #define I2C_TX_ISRC 0x0005 44 | #define I2C_SCD_ISRC 0x0006 45 | #define I2C_AAS_ISRC 0x0007 46 | 47 | // I2CMSG structure defines 48 | #define I2C_NO_STOP 0 49 | #define I2C_YES_STOP 1 50 | #define I2C_RECEIVE 0 51 | #define I2C_TRANSMIT 1 52 | #define I2C_MAX_BUFFER_SIZE 16 53 | 54 | // I2C Slave State defines 55 | #define I2C_NOTSLAVE 0 56 | #define I2C_ADDR_AS_SLAVE 1 57 | #define I2C_ST_MSG_READY 2 58 | 59 | // I2C Slave Receiver messages defines 60 | #define I2C_SND_MSG1 1 61 | #define I2C_SND_MSG2 2 62 | 63 | // I2C State defines 64 | #define I2C_IDLE 0 65 | #define I2C_SLAVE_RECEIVER 1 66 | #define I2C_SLAVE_TRANSMITTER 2 67 | #define I2C_MASTER_RECEIVER 3 68 | #define I2C_MASTER_TRANSMITTER 4 69 | 70 | // I2C Message Commands for I2CMSG struct 71 | #define I2C_MSGSTAT_INACTIVE 0x0000 72 | #define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 73 | #define I2C_MSGSTAT_WRITE_BUSY 0x0011 74 | #define I2C_MSGSTAT_SEND_NOSTOP 0x0020 75 | #define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 76 | #define I2C_MSGSTAT_RESTART 0x0022 77 | #define I2C_MSGSTAT_READ_BUSY 0x0023 78 | 79 | // Generic defines 80 | #define I2C_TRUE 1 81 | #define I2C_FALSE 0 82 | #define I2C_YES 1 83 | #define I2C_NO 0 84 | #define I2C_DUMMY_BYTE 0 85 | 86 | 87 | //-------------------------------------------- 88 | // Structures 89 | //-------------------------------------------- 90 | 91 | // I2C Message Structure 92 | struct I2CMSG { 93 | Uint16 MsgStatus; // Word stating what state msg is in: 94 | // I2C_MSGCMD_INACTIVE = do not send msg 95 | // I2C_MSGCMD_BUSY = msg start has been sent, 96 | // awaiting stop 97 | // I2C_MSGCMD_SEND_WITHSTOP = command to send 98 | // master trans msg complete with a stop bit 99 | // I2C_MSGCMD_SEND_NOSTOP = command to send 100 | // master trans msg without the stop bit 101 | // I2C_MSGCMD_RESTART = command to send a restart 102 | // as a master receiver with a stop bit 103 | Uint16 SlaveAddress; // I2C address of slave msg is intended for 104 | Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) 105 | Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte) 106 | Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte) 107 | Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that 108 | // MAX_BUFFER_SIZE can be is 16 due to 109 | // the FIFO's 110 | }; 111 | 112 | 113 | #endif // end of DSP2833x_I2C_DEFINES_H definition 114 | 115 | //=========================================================================== 116 | // End of file. 117 | //=========================================================================== 118 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/DSP2833x_ePwm_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:45:39 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_EPwm_defines.h 6 | // 7 | // TITLE: #defines used in ePWM examples examples 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_EPWM_DEFINES_H 15 | #define DSP2833x_EPWM_DEFINES_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | // TBCTL (Time-Base Control) 23 | //========================== 24 | // CTRMODE bits 25 | #define TB_COUNT_UP 0x0 26 | #define TB_COUNT_DOWN 0x1 27 | #define TB_COUNT_UPDOWN 0x2 28 | #define TB_FREEZE 0x3 29 | // PHSEN bit 30 | #define TB_DISABLE 0x0 31 | #define TB_ENABLE 0x1 32 | // PRDLD bit 33 | #define TB_SHADOW 0x0 34 | #define TB_IMMEDIATE 0x1 35 | // SYNCOSEL bits 36 | #define TB_SYNC_IN 0x0 37 | #define TB_CTR_ZERO 0x1 38 | #define TB_CTR_CMPB 0x2 39 | #define TB_SYNC_DISABLE 0x3 40 | // HSPCLKDIV and CLKDIV bits 41 | #define TB_DIV1 0x0 42 | #define TB_DIV2 0x1 43 | #define TB_DIV4 0x2 44 | // PHSDIR bit 45 | #define TB_DOWN 0x0 46 | #define TB_UP 0x1 47 | 48 | // CMPCTL (Compare Control) 49 | //========================== 50 | // LOADAMODE and LOADBMODE bits 51 | #define CC_CTR_ZERO 0x0 52 | #define CC_CTR_PRD 0x1 53 | #define CC_CTR_ZERO_PRD 0x2 54 | #define CC_LD_DISABLE 0x3 55 | // SHDWAMODE and SHDWBMODE bits 56 | #define CC_SHADOW 0x0 57 | #define CC_IMMEDIATE 0x1 58 | 59 | // AQCTLA and AQCTLB (Action Qualifier Control) 60 | //============================================= 61 | // ZRO, PRD, CAU, CAD, CBU, CBD bits 62 | #define AQ_NO_ACTION 0x0 63 | #define AQ_CLEAR 0x1 64 | #define AQ_SET 0x2 65 | #define AQ_TOGGLE 0x3 66 | 67 | // DBCTL (Dead-Band Control) 68 | //========================== 69 | // OUT MODE bits 70 | #define DB_DISABLE 0x0 71 | #define DBA_ENABLE 0x1 72 | #define DBB_ENABLE 0x2 73 | #define DB_FULL_ENABLE 0x3 74 | // POLSEL bits 75 | #define DB_ACTV_HI 0x0 76 | #define DB_ACTV_LOC 0x1 77 | #define DB_ACTV_HIC 0x2 78 | #define DB_ACTV_LO 0x3 79 | // IN MODE 80 | #define DBA_ALL 0x0 81 | #define DBB_RED_DBA_FED 0x1 82 | #define DBA_RED_DBB_FED 0x2 83 | #define DBB_ALL 0x3 84 | 85 | // CHPCTL (chopper control) 86 | //========================== 87 | // CHPEN bit 88 | #define CHP_DISABLE 0x0 89 | #define CHP_ENABLE 0x1 90 | // CHPFREQ bits 91 | #define CHP_DIV1 0x0 92 | #define CHP_DIV2 0x1 93 | #define CHP_DIV3 0x2 94 | #define CHP_DIV4 0x3 95 | #define CHP_DIV5 0x4 96 | #define CHP_DIV6 0x5 97 | #define CHP_DIV7 0x6 98 | #define CHP_DIV8 0x7 99 | // CHPDUTY bits 100 | #define CHP1_8TH 0x0 101 | #define CHP2_8TH 0x1 102 | #define CHP3_8TH 0x2 103 | #define CHP4_8TH 0x3 104 | #define CHP5_8TH 0x4 105 | #define CHP6_8TH 0x5 106 | #define CHP7_8TH 0x6 107 | 108 | // TZSEL (Trip Zone Select) 109 | //========================== 110 | // CBCn and OSHTn bits 111 | #define TZ_DISABLE 0x0 112 | #define TZ_ENABLE 0x1 113 | 114 | // TZCTL (Trip Zone Control) 115 | //========================== 116 | // TZA and TZB bits 117 | #define TZ_HIZ 0x0 118 | #define TZ_FORCE_HI 0x1 119 | #define TZ_FORCE_LO 0x2 120 | #define TZ_NO_CHANGE 0x3 121 | 122 | // ETSEL (Event Trigger Select) 123 | //============================= 124 | #define ET_CTR_ZERO 0x1 125 | #define ET_CTR_PRD 0x2 126 | #define ET_CTRU_CMPA 0x4 127 | #define ET_CTRD_CMPA 0x5 128 | #define ET_CTRU_CMPB 0x6 129 | #define ET_CTRD_CMPB 0x7 130 | 131 | // ETPS (Event Trigger Pre-scale) 132 | //=============================== 133 | // INTPRD, SOCAPRD, SOCBPRD bits 134 | #define ET_DISABLE 0x0 135 | #define ET_1ST 0x1 136 | #define ET_2ND 0x2 137 | #define ET_3RD 0x3 138 | 139 | 140 | //-------------------------------- 141 | // HRPWM (High Resolution PWM) 142 | //================================ 143 | // HRCNFG 144 | #define HR_Disable 0x0 145 | #define HR_REP 0x1 146 | #define HR_FEP 0x2 147 | #define HR_BEP 0x3 148 | 149 | #define HR_CMP 0x0 150 | #define HR_PHS 0x1 151 | 152 | #define HR_CTR_ZERO 0x0 153 | #define HR_CTR_PRD 0x1 154 | 155 | 156 | #ifdef __cplusplus 157 | } 158 | #endif /* extern "C" */ 159 | 160 | #endif // - end of DSP2833x_EPWM_DEFINES_H 161 | 162 | //=========================================================================== 163 | // End of file. 164 | //=========================================================================== 165 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/DSP28x_Project.h: -------------------------------------------------------------------------------- 1 | 2 | // TI File $Revision: /main/1 $ 3 | // Checkin $Date: April 22, 2008 14:35:56 $ 4 | //########################################################################### 5 | // 6 | // FILE: DSP28x_Project.h 7 | // 8 | // TITLE: DSP28x Project Headerfile and Examples Include File 9 | // 10 | //########################################################################### 11 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 12 | // $Release Date: August 4, 2009 $ 13 | //########################################################################### 14 | 15 | #ifndef DSP28x_PROJECT_H 16 | #define DSP28x_PROJECT_H 17 | 18 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 19 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 20 | 21 | #endif // end of DSP28x_PROJECT_H definition 22 | 23 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/SFO.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: SFO.H 4 | // 5 | // TITLE: Scale Factor Optimizer Library Interface Header 6 | // 7 | // 8 | //########################################################################### 9 | // 10 | // Ver | dd mmm yyyy | Who | Description of changes 11 | // =====|=============|======|=============================================== 12 | // 0.01| 09 Jan 2004 | TI | New module 13 | //########################################################################### 14 | 15 | 16 | //============================================================================ 17 | // Description: This header provides the function call interface 18 | // for the scale factor optimizer for the 'F2833x. 19 | //============================================================================ 20 | 21 | 22 | //============================================================================ 23 | // Multiple include Guard 24 | //============================================================================ 25 | #ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___ 26 | #define __4090522384024n8273240x3438jx43087401r34ru32r0___ 27 | 28 | //============================================================================ 29 | // C++ namespace 30 | //============================================================================ 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | 36 | //============================================================================ 37 | // Function prototypes for MEP SFO 38 | //============================================================================ 39 | void SFO_MepEn(int nEpwmModule); 40 | void SFO_MepDis(int nEpwmModule); 41 | 42 | //============================================================================ 43 | // Multiple include Guard 44 | //============================================================================ 45 | #endif // End: Multiple include Guard 46 | 47 | //============================================================================ 48 | // C++ namespace 49 | //============================================================================ 50 | #ifdef __cplusplus 51 | } 52 | #endif /* extern "C" */ 53 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/include/SFO_V5.h: -------------------------------------------------------------------------------- 1 | 2 | //########################################################################### 3 | // 4 | // FILE: SFO_V5.H 5 | // 6 | // TITLE: Scale Factor Optimizer Library V5 Interface Header 7 | // 8 | // 9 | //########################################################################### 10 | // 11 | // Ver | dd mmm yyyy | Who | Description of changes 12 | // =====|=============|======|=============================================== 13 | // 0.01| 09 Jan 2004 | TI | New module 14 | // 0.02| 22 Jun 2007 | TI | New version (V5) with support for more channels 15 | //########################################################################### 16 | 17 | 18 | //============================================================================ 19 | // Description: This header provides the function call interface 20 | // for the scale factor optimizer V5. For more 21 | // information on the SFO function usage and 22 | // limitations, see the HRPWM Reference Guide 23 | // (spru924) on the TI website. 24 | //============================================================================ 25 | 26 | 27 | //============================================================================ 28 | // Multiple include Guard 29 | //============================================================================ 30 | #ifndef _SFO_V5_H 31 | #define _SFO_V5_H 32 | 33 | //============================================================================ 34 | // C++ namespace 35 | //============================================================================ 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | //============================================================================ 41 | // USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1 42 | //============================================================================ 43 | #define PWM_CH 7 // Equal # of HRPWM channels PLUS 1 44 | // i.e. PWM_CH is 7 for 6 channels, 5 for 4 channels etc. 45 | 46 | //============================================================================ 47 | // Function prototypes for MEP SFO 48 | //============================================================================ 49 | 50 | int SFO_MepEn_V5(int nEpwmModule); // MEP-Enable V5 Calibration Function 51 | int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5 Calibration Function 52 | 53 | //============================================================================ 54 | // Useful Defines when Using SFO Functions 55 | //============================================================================ 56 | #define SFO_INCOMPLETE 0 57 | #define SFO_COMPLETE 1 58 | #define SFO_OUTRANGE_ERROR 2 59 | 60 | //============================================================================ 61 | // Multiple include Guard 62 | //============================================================================ 63 | #endif // End: Multiple include Guard 64 | 65 | //============================================================================ 66 | // C++ namespace 67 | //============================================================================ 68 | #ifdef __cplusplus 69 | } 70 | #endif /* extern "C" */ 71 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/IQmath.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/IQmath.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/IQmath_fpu32.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/IQmath_fpu32.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5B.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5B.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5B_fpu.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_V5_fpu.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_fpu.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/brunoluiz/28335ModbusSlave/fcd667766fceb7e83c13579c613a4cfc3ee0d120/contrib/DSP2833x/DSP2833x_common/lib/SFO_TI_Build_fpu.lib -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_ADC_cal.asm: -------------------------------------------------------------------------------- 1 | ;; TI File $Revision: /main/1 $ 2 | ;; Checkin $Date: July 30, 2007 10:29:23 $ 3 | ;;########################################################################### 4 | ;; 5 | ;; FILE: ADC_cal.asm 6 | ;; 7 | ;; TITLE: 2833x Boot Rom ADC Cal routine. 8 | ;; 9 | ;; Functions: 10 | ;; 11 | ;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers 12 | ;; Notes: 13 | ;; 14 | ;;########################################################################### 15 | ;; $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 16 | ;; $Release Date: August 4, 2009 $ 17 | ;;########################################################################### 18 | 19 | .def _ADC_cal 20 | .asg "0x711C", ADCREFSEL_LOC 21 | 22 | ;----------------------------------------------- 23 | ; _ADC_cal 24 | ;----------------------------------------------- 25 | ;----------------------------------------------- 26 | ; This is the ADC cal routine.This routine is programmed into 27 | ; reserved memory by the factory. 0xAAAA and 0xBBBB are place- 28 | ; holders for calibration data. 29 | ;The actual values programmed by TI are device specific. 30 | ; 31 | ; This function assumes that the clocks have been 32 | ; enabled to the ADC module. 33 | ;----------------------------------------------- 34 | 35 | .sect ".adc_cal" 36 | 37 | _ADC_cal 38 | MOVW DP, #ADCREFSEL_LOC >> 6 39 | MOV @28, #0xAAAA ; actual value may not be 0xAAAA 40 | MOV @29, #0xBBBB ; actual value may not be 0xBBBB 41 | LRETR 42 | ;eof ---------- 43 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_Adc.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/5 $ 2 | // Checkin $Date: October 23, 2007 13:34:09 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Adc.c 6 | // 7 | // TITLE: DSP2833x ADC Initialization & Support Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | #define ADC_usDELAY 5000L 18 | 19 | //--------------------------------------------------------------------------- 20 | // InitAdc: 21 | //--------------------------------------------------------------------------- 22 | // This function initializes ADC to a known state. 23 | // 24 | void InitAdc(void) 25 | { 26 | extern void DSP28x_usDelay(Uint32 Count); 27 | 28 | 29 | // *IMPORTANT* 30 | // The ADC_cal function, which copies the ADC calibration values from TI reserved 31 | // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the 32 | // Boot ROM. If the boot ROM code is bypassed during the debug process, the 33 | // following function MUST be called for the ADC to function according 34 | // to specification. The clocks to the ADC MUST be enabled before calling this 35 | // function. 36 | // See the device data manual and/or the ADC Reference 37 | // Manual for more information. 38 | 39 | EALLOW; 40 | SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; 41 | ADC_cal(); 42 | EDIS; 43 | 44 | 45 | 46 | 47 | // To powerup the ADC the ADCENCLK bit should be set first to enable 48 | // clocks, followed by powering up the bandgap, reference circuitry, and ADC core. 49 | // Before the first conversion is performed a 5ms delay must be observed 50 | // after power up to give all analog circuits time to power up and settle 51 | 52 | // Please note that for the delay function below to operate correctly the 53 | // CPU_RATE define statement in the DSP2833x_Examples.h file must 54 | // contain the correct CPU clock period in nanoseconds. 55 | 56 | AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits 57 | DELAY_US(ADC_usDELAY); // Delay before converting ADC channels 58 | } 59 | 60 | //=========================================================================== 61 | // End of file. 62 | //=========================================================================== 63 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_CSMPasswords.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/3 $ 2 | ;// Checkin $Date: June 26, 2007 16:41:07 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_CSMPasswords.asm 6 | ;// 7 | ;// TITLE: DSP2833x Code Security Module Passwords. 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// This file is used to specify password values to 12 | ;// program into the CSM password locations in Flash 13 | ;// at 0x33FFF8 - 0x33FFFF. 14 | ;// 15 | ;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are 16 | ;// all programmed to 0x0000 17 | ;// 18 | ;//########################################################################### 19 | ;// 20 | ;// Original source based on D.A. 21 | ;// 22 | ;// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 23 | ;// $Release Date: August 4, 2009 $ 24 | ;//########################################################################### 25 | 26 | ; The "csmpasswords" section contains the actual CSM passwords that will be 27 | ; linked and programmed into to the CSM password locations (PWL) in flash. 28 | ; These passwords must be known in order to unlock the CSM module. 29 | ; All 0xFFFF's (erased) is the default value for the password locations (PWL). 30 | 31 | ; It is recommended that all passwords be left as 0xFFFF during code 32 | ; development. Passwords of 0xFFFF do not activate code security and dummy 33 | ; reads of the CSM PWL registers is all that is required to unlock the CSM. 34 | ; When code development is complete, modify the passwords to activate the 35 | ; code security module. 36 | 37 | .sect "csmpasswds" 38 | 39 | .int 0xFFFF ;PWL0 (LSW of 128-bit password) 40 | .int 0xFFFF ;PWL1 41 | .int 0xFFFF ;PWL2 42 | .int 0xFFFF ;PWL3 43 | .int 0xFFFF ;PWL4 44 | .int 0xFFFF ;PWL5 45 | .int 0xFFFF ;PWL6 46 | .int 0xFFFF ;PWL7 (MSW of 128-bit password) 47 | 48 | ;---------------------------------------------------------------------- 49 | 50 | ; For code security operation, all addresses between 0x33FF80 and 51 | ; 0X33fff5 cannot be used as program code or data. These locations 52 | ; must be programmed to 0x0000 when the code security password locations 53 | ; (PWL) are programmed. If security is not a concern, then these addresses 54 | ; can be used for code or data. 55 | 56 | ; The section "csm_rsvd" can be used to program these locations to 0x0000. 57 | 58 | .sect "csm_rsvd" 59 | .loop (33FFF5h - 33FF80h + 1) 60 | .int 0x0000 61 | .endloop 62 | 63 | ;//=========================================================================== 64 | ;// End of file. 65 | ;//=========================================================================== 66 | 67 | 68 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:45:55 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_CodeStartBranch.asm 6 | ;// 7 | ;// TITLE: Branch for redirecting code execution after boot. 8 | ;// 9 | ;// For these examples, code_start is the first code that is executed after 10 | ;// exiting the boot ROM code. 11 | ;// 12 | ;// The codestart section in the linker cmd file is used to physically place 13 | ;// this code at the correct memory location. This section should be placed 14 | ;// at the location the BOOT ROM will re-direct the code to. For example, 15 | ;// for boot to FLASH this code will be located at 0x3f7ff6. 16 | ;// 17 | ;// In addition, the example DSP2833x projects are setup such that the codegen 18 | ;// entry point is also set to the code_start label. This is done by linker 19 | ;// option -e in the project build options. When the debugger loads the code, 20 | ;// it will automatically set the PC to the "entry point" address indicated by 21 | ;// the -e linker option. In this case the debugger is simply assigning the PC, 22 | ;// it is not the same as a full reset of the device. 23 | ;// 24 | ;// The compiler may warn that the entry point for the project is other then 25 | ;// _c_init00. _c_init00 is the C environment setup and is run before 26 | ;// main() is entered. The code_start code will re-direct the execution 27 | ;// to _c_init00 and thus there is no worry and this warning can be ignored. 28 | ;// 29 | ;//########################################################################### 30 | ;// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 31 | ;// $Release Date: August 4, 2009 $ 32 | ;//########################################################################### 33 | 34 | 35 | *********************************************************************** 36 | 37 | WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 38 | 39 | .ref _c_int00 40 | .global code_start 41 | 42 | *********************************************************************** 43 | * Function: codestart section 44 | * 45 | * Description: Branch to code starting point 46 | *********************************************************************** 47 | 48 | .sect "codestart" 49 | 50 | code_start: 51 | .if WD_DISABLE == 1 52 | LB wd_disable ;Branch to watchdog disable code 53 | .else 54 | LB _c_int00 ;Branch to start of boot.asm in RTS library 55 | .endif 56 | 57 | ;end codestart section 58 | 59 | 60 | *********************************************************************** 61 | * Function: wd_disable 62 | * 63 | * Description: Disables the watchdog timer 64 | *********************************************************************** 65 | .if WD_DISABLE == 1 66 | 67 | .text 68 | wd_disable: 69 | SETC OBJMODE ;Set OBJMODE for 28x object code 70 | EALLOW ;Enable EALLOW protected register access 71 | MOVZ DP, #7029h>>6 ;Set data page for WDCR register 72 | MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD 73 | EDIS ;Disable EALLOW protected register access 74 | LB _c_int00 ;Branch to start of boot.asm in RTS library 75 | 76 | .endif 77 | 78 | ;end wd_disable 79 | 80 | 81 | 82 | .end 83 | 84 | ;//=========================================================================== 85 | ;// End of file. 86 | ;//=========================================================================== 87 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_CpuTimers.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: July 9, 2009 10:51:59 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_CpuTimers.c 6 | // 7 | // TITLE: CPU 32-bit Timers Initialization & Support Functions. 8 | // 9 | // NOTES: CpuTimer2 is reserved for use with DSP BIOS and 10 | // other realtime operating systems. 11 | // 12 | // Do not use these this timer in your application if you ever plan 13 | // on integrating DSP-BIOS or another realtime OS. 14 | // 15 | //########################################################################### 16 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 17 | // $Release Date: August 4, 2009 $ 18 | //########################################################################### 19 | 20 | #include "DSP2833x_Device.h" // Headerfile Include File 21 | #include "DSP2833x_Examples.h" // Examples Include File 22 | 23 | struct CPUTIMER_VARS CpuTimer0; 24 | 25 | // When using DSP BIOS & other RTOS, comment out CPU Timer 2 code. 26 | struct CPUTIMER_VARS CpuTimer1; 27 | struct CPUTIMER_VARS CpuTimer2; 28 | 29 | //--------------------------------------------------------------------------- 30 | // InitCpuTimers: 31 | //--------------------------------------------------------------------------- 32 | // This function initializes all three CPU timers to a known state. 33 | // 34 | void InitCpuTimers(void) 35 | { 36 | // CPU Timer 0 37 | // Initialize address pointers to respective timer registers: 38 | CpuTimer0.RegsAddr = &CpuTimer0Regs; 39 | // Initialize timer period to maximum: 40 | CpuTimer0Regs.PRD.all = 0xFFFFFFFF; 41 | // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): 42 | CpuTimer0Regs.TPR.all = 0; 43 | CpuTimer0Regs.TPRH.all = 0; 44 | // Make sure timer is stopped: 45 | CpuTimer0Regs.TCR.bit.TSS = 1; 46 | // Reload all counter register with period value: 47 | CpuTimer0Regs.TCR.bit.TRB = 1; 48 | // Reset interrupt counters: 49 | CpuTimer0.InterruptCount = 0; 50 | 51 | 52 | // CpuTimer2 is reserved for DSP BIOS & other RTOS 53 | // Do not use this timer if you ever plan on integrating 54 | // DSP-BIOS or another realtime OS. 55 | 56 | // Initialize address pointers to respective timer registers: 57 | CpuTimer1.RegsAddr = &CpuTimer1Regs; 58 | CpuTimer2.RegsAddr = &CpuTimer2Regs; 59 | // Initialize timer period to maximum: 60 | CpuTimer1Regs.PRD.all = 0xFFFFFFFF; 61 | CpuTimer2Regs.PRD.all = 0xFFFFFFFF; 62 | // Make sure timers are stopped: 63 | CpuTimer1Regs.TCR.bit.TSS = 1; 64 | CpuTimer2Regs.TCR.bit.TSS = 1; 65 | // Reload all counter register with period value: 66 | CpuTimer1Regs.TCR.bit.TRB = 1; 67 | CpuTimer2Regs.TCR.bit.TRB = 1; 68 | // Reset interrupt counters: 69 | CpuTimer1.InterruptCount = 0; 70 | CpuTimer2.InterruptCount = 0; 71 | 72 | } 73 | 74 | //--------------------------------------------------------------------------- 75 | // ConfigCpuTimer: 76 | //--------------------------------------------------------------------------- 77 | // This function initializes the selected timer to the period specified 78 | // by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz" 79 | // and the period in "uSeconds". The timer is held in the stopped state 80 | // after configuration. 81 | // 82 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) 83 | { 84 | Uint32 temp; 85 | 86 | // Initialize timer period: 87 | Timer->CPUFreqInMHz = Freq; 88 | Timer->PeriodInUSec = Period; 89 | temp = (long) (Freq * Period); 90 | Timer->RegsAddr->PRD.all = temp; 91 | 92 | // Set pre-scale counter to divide by 1 (SYSCLKOUT): 93 | Timer->RegsAddr->TPR.all = 0; 94 | Timer->RegsAddr->TPRH.all = 0; 95 | 96 | // Initialize timer control register: 97 | Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer 98 | Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer 99 | Timer->RegsAddr->TCR.bit.SOFT = 1; 100 | Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run 101 | Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt 102 | 103 | // Reset interrupt counter: 104 | Timer->InterruptCount = 0; 105 | } 106 | 107 | //=========================================================================== 108 | // End of file. 109 | //=========================================================================== 110 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_DBGIER.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:46:03 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_DBGIER.asm 6 | ;// 7 | ;// TITLE: Set the DBGIER register 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// Function to set the DBGIER register (for realtime emulation). 12 | ;// Function Prototype: void SetDBGIER(Uint16) 13 | ;// Useage: SetDBGIER(value); 14 | ;// Input Parameters: Uint16 value = value to put in DBGIER register. 15 | ;// Return Value: none 16 | ;// 17 | ;//########################################################################### 18 | ;// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 19 | ;// $Release Date: August 4, 2009 $ 20 | ;//########################################################################### 21 | .global _SetDBGIER 22 | .text 23 | 24 | _SetDBGIER: 25 | MOV *SP++,AL 26 | POP DBGIER 27 | LRETR 28 | 29 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_DisInt.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:46:09 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_DisInt.asm 6 | ;// 7 | ;// TITLE: Disable and Restore INTM and DBGM 8 | ;// 9 | ;// Function Prototypes: 10 | ;// 11 | ;// Uint16 DSP28x_DisableInt(); 12 | ;// and void DSP28x_RestoreInt(Uint16 Stat0); 13 | ;// 14 | ;// Usage: 15 | ;// 16 | ;// DSP28x_DisableInt() sets both the INTM and DBGM 17 | ;// bits to disable maskable interrupts. Before doing 18 | ;// this, the current value of ST1 is stored on the stack 19 | ;// so that the values can be restored later. The value 20 | ;// of ST1 before the masks are set is returned to the 21 | ;// user in AL. This is then used to restore their state 22 | ;// via the DSP28x_RestoreInt(Uint16 ST1) function. 23 | ;// 24 | ;// Example 25 | ;// 26 | ;// Uint16 StatusReg1 27 | ;// StatusReg1 = DSP28x_DisableInt(); 28 | ;// 29 | ;// ... May also want to disable INTM here 30 | ;// 31 | ;// ... code here 32 | ;// 33 | ;// DSP28x_RestoreInt(StatusReg1); 34 | ;// 35 | ;// ... Restore INTM enable 36 | ;// 37 | ;//########################################################################### 38 | ;// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 39 | ;// $Release Date: August 4, 2009 $ 40 | ;//########################################################################### 41 | 42 | 43 | 44 | 45 | .def _DSP28x_DisableInt 46 | .def _DSP28x_RestoreInt 47 | 48 | 49 | _DSP28x_DisableInt: 50 | PUSH ST1 51 | SETC INTM,DBGM 52 | MOV AL, *--SP 53 | LRETR 54 | 55 | _DSP28x_RestoreInt: 56 | MOV *SP++, AL 57 | POP ST1 58 | LRETR 59 | 60 | 61 | ;//=========================================================================== 62 | ;// End of file. 63 | ;//=========================================================================== 64 | 65 | 66 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_EQep.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/3 $ 2 | // Checkin $Date: July 27, 2007 11:55:20 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_EQep.c 6 | // 7 | // TITLE: DSP2833x eQEP Initialization & Support Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitEQep: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the eQEP(s) to a known state. 21 | // 22 | void InitEQep(void) 23 | { 24 | // Initialize eQEP1/2 25 | 26 | //tbd... 27 | 28 | } 29 | 30 | //--------------------------------------------------------------------------- 31 | // Example: InitEQepGpio: 32 | //--------------------------------------------------------------------------- 33 | // This function initializes GPIO pins to function as eQEP pins 34 | // 35 | // Each GPIO pin can be configured as a GPIO pin or up to 3 different 36 | // peripheral functional pins. By default all pins come up as GPIO 37 | // inputs after reset. 38 | // 39 | // Caution: 40 | // For each eQEP peripheral 41 | // Only one GPIO pin should be enabled for EQEPxA operation. 42 | // Only one GPIO pin should be enabled for EQEPxB operation. 43 | // Only one GPIO pin should be enabled for EQEPxS operation. 44 | // Only one GPIO pin should be enabled for EQEPxI operation. 45 | // Comment out other unwanted lines. 46 | 47 | void InitEQepGpio() 48 | { 49 | #if DSP28_EQEP1 50 | InitEQep1Gpio(); 51 | #endif // endif DSP28_EQEP1 52 | #if DSP28_EQEP2 53 | InitEQep2Gpio(); 54 | #endif // endif DSP28_EQEP2 55 | } 56 | 57 | #if DSP28_EQEP1 58 | void InitEQep1Gpio(void) 59 | { 60 | EALLOW; 61 | 62 | /* Enable internal pull-up for the selected pins */ 63 | // Pull-ups can be enabled or disabled by the user. 64 | // This will enable the pullups for the specified pins. 65 | // Comment out other unwanted lines. 66 | 67 | GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A) 68 | GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B) 69 | GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S) 70 | GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I) 71 | 72 | // GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A) 73 | // GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B) 74 | // GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S) 75 | // GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I) 76 | 77 | 78 | // Inputs are synchronized to SYSCLKOUT by default. 79 | // Comment out other unwanted lines. 80 | 81 | GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A) 82 | GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B) 83 | GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S) 84 | GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I) 85 | 86 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync to SYSCLKOUT GPIO50 (EQEP1A) 87 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync to SYSCLKOUT GPIO51 (EQEP1B) 88 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync to SYSCLKOUT GPIO52 (EQEP1S) 89 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync to SYSCLKOUT GPIO53 (EQEP1I) 90 | 91 | /* Configure eQEP-1 pins using GPIO regs*/ 92 | // This specifies which of the possible GPIO pins will be eQEP1 functional pins. 93 | // Comment out other unwanted lines. 94 | 95 | GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A 96 | GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B 97 | GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S 98 | GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I 99 | 100 | // GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A 101 | // GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B 102 | // GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S 103 | // GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I 104 | 105 | 106 | EDIS; 107 | } 108 | #endif // if DSP28_EQEP1 109 | 110 | 111 | 112 | #if DSP28_EQEP2 113 | void InitEQep2Gpio(void) 114 | { 115 | EALLOW; 116 | 117 | /* Enable internal pull-up for the selected pins */ 118 | // Pull-ups can be enabled or disabled by the user. 119 | // This will enable the pullups for the specified pins. 120 | // Comment out other unwanted lines. 121 | 122 | GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A) 123 | GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B) 124 | GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I) 125 | GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S) 126 | 127 | // Inputs are synchronized to SYSCLKOUT by default. 128 | // Comment out other unwanted lines. 129 | 130 | GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A) 131 | GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B) 132 | GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I) 133 | GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S) 134 | 135 | /* Configure eQEP-2 pins using GPIO regs*/ 136 | // This specifies which of the possible GPIO pins will be eQEP2 functional pins. 137 | // Comment out other unwanted lines. 138 | 139 | GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A 140 | GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B 141 | GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I 142 | GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S 143 | 144 | 145 | EDIS; 146 | } 147 | #endif // endif DSP28_EQEP2 148 | 149 | 150 | 151 | 152 | //=========================================================================== 153 | // End of file. 154 | //=========================================================================== 155 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_Gpio.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:25 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Gpio.c 6 | // 7 | // TITLE: DSP2833x General Purpose I/O Initialization & Support Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitGpio: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the Gpio to a known (default) state. 21 | // 22 | // For more details on configuring GPIO's as peripheral functions, 23 | // refer to the individual peripheral examples and/or GPIO setup example. 24 | void InitGpio(void) 25 | { 26 | EALLOW; 27 | 28 | // Each GPIO pin can be: 29 | // a) a GPIO input/output 30 | // b) peripheral function 1 31 | // c) peripheral function 2 32 | // d) peripheral function 3 33 | // By default, all are GPIO Inputs 34 | GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 35 | GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 36 | GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39 37 | GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63 38 | GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 39 | GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 40 | 41 | GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs 42 | GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs 43 | GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs 44 | 45 | // Each input can have different qualification 46 | // a) input synchronized to SYSCLKOUT 47 | // b) input qualified by a sampling window 48 | // c) input sent asynchronously (valid for peripheral inputs only) 49 | GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT 50 | GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT 51 | GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT 52 | GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT 53 | 54 | // Pull-ups can be enabled or disabled. 55 | GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31 56 | GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63 57 | GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79 58 | 59 | //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31 60 | //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34 61 | //GpioCtrlRegs.GPCPUD.all = 0xFFFF // Pullup's disabled GPIO64-GPIO79 62 | 63 | EDIS; 64 | 65 | } 66 | 67 | //=========================================================================== 68 | // End of file. 69 | //=========================================================================== 70 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_I2C.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:27 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_I2C.c 6 | // 7 | // TITLE: DSP2833x SCI Initialization & Support Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitI2C: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the I2C to a known state. 21 | // 22 | void InitI2C(void) 23 | { 24 | // Initialize I2C-A: 25 | 26 | //tbd... 27 | } 28 | 29 | //--------------------------------------------------------------------------- 30 | // Example: InitI2CGpio: 31 | //--------------------------------------------------------------------------- 32 | // This function initializes GPIO pins to function as I2C pins 33 | // 34 | // Each GPIO pin can be configured as a GPIO pin or up to 3 different 35 | // peripheral functional pins. By default all pins come up as GPIO 36 | // inputs after reset. 37 | // 38 | // Caution: 39 | // Only one GPIO pin should be enabled for SDAA operation. 40 | // Only one GPIO pin shoudl be enabled for SCLA operation. 41 | // Comment out other unwanted lines. 42 | 43 | void InitI2CGpio() 44 | { 45 | 46 | EALLOW; 47 | /* Enable internal pull-up for the selected pins */ 48 | // Pull-ups can be enabled or disabled disabled by the user. 49 | // This will enable the pullups for the specified pins. 50 | // Comment out other unwanted lines. 51 | 52 | GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) 53 | GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) 54 | 55 | /* Set qualification for selected pins to asynch only */ 56 | // This will select asynch (no qualification) for the selected pins. 57 | // Comment out other unwanted lines. 58 | 59 | GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) 60 | GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) 61 | 62 | /* Configure SCI pins using GPIO regs*/ 63 | // This specifies which of the possible GPIO pins will be I2C functional pins. 64 | // Comment out other unwanted lines. 65 | 66 | GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation 67 | GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation 68 | 69 | EDIS; 70 | } 71 | 72 | 73 | 74 | //=========================================================================== 75 | // End of file. 76 | //=========================================================================== 77 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_MemCopy.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:33 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_MemCopy.c 6 | // 7 | // TITLE: Memory Copy Utility 8 | // 9 | // ASSUMPTIONS: 10 | // 11 | // 12 | // 13 | // DESCRIPTION: 14 | // 15 | // This function will copy the specified memory contents from 16 | // one location to another. 17 | // 18 | // Uint16 *SourceAddr Pointer to the first word to be moved 19 | // SourceAddr < SourceEndAddr 20 | // Uint16* SourceEndAddr Pointer to the last word to be moved 21 | // Uint16* DestAddr Pointer to the first destination word 22 | // 23 | // No checks are made for invalid memory locations or that the 24 | // end address is > then the first start address. 25 | // 26 | // 27 | //########################################################################### 28 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 29 | // $Release Date: August 4, 2009 $ 30 | //########################################################################### 31 | 32 | #include "DSP2833x_Device.h" 33 | 34 | void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) 35 | { 36 | while(SourceAddr < SourceEndAddr) 37 | { 38 | *DestAddr++ = *SourceAddr++; 39 | } 40 | return; 41 | } 42 | 43 | //=========================================================================== 44 | // End of file. 45 | //=========================================================================== 46 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_PieCtrl.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:35 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_PieCtrl.c 6 | // 7 | // TITLE: DSP2833x Device PIE Control Register Initialization Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitPieCtrl: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the PIE control registers to a known state. 21 | // 22 | void InitPieCtrl(void) 23 | { 24 | // Disable Interrupts at the CPU level: 25 | DINT; 26 | 27 | // Disable the PIE 28 | PieCtrlRegs.PIECTRL.bit.ENPIE = 0; 29 | 30 | // Clear all PIEIER registers: 31 | PieCtrlRegs.PIEIER1.all = 0; 32 | PieCtrlRegs.PIEIER2.all = 0; 33 | PieCtrlRegs.PIEIER3.all = 0; 34 | PieCtrlRegs.PIEIER4.all = 0; 35 | PieCtrlRegs.PIEIER5.all = 0; 36 | PieCtrlRegs.PIEIER6.all = 0; 37 | PieCtrlRegs.PIEIER7.all = 0; 38 | PieCtrlRegs.PIEIER8.all = 0; 39 | PieCtrlRegs.PIEIER9.all = 0; 40 | PieCtrlRegs.PIEIER10.all = 0; 41 | PieCtrlRegs.PIEIER11.all = 0; 42 | PieCtrlRegs.PIEIER12.all = 0; 43 | 44 | // Clear all PIEIFR registers: 45 | PieCtrlRegs.PIEIFR1.all = 0; 46 | PieCtrlRegs.PIEIFR2.all = 0; 47 | PieCtrlRegs.PIEIFR3.all = 0; 48 | PieCtrlRegs.PIEIFR4.all = 0; 49 | PieCtrlRegs.PIEIFR5.all = 0; 50 | PieCtrlRegs.PIEIFR6.all = 0; 51 | PieCtrlRegs.PIEIFR7.all = 0; 52 | PieCtrlRegs.PIEIFR8.all = 0; 53 | PieCtrlRegs.PIEIFR9.all = 0; 54 | PieCtrlRegs.PIEIFR10.all = 0; 55 | PieCtrlRegs.PIEIFR11.all = 0; 56 | PieCtrlRegs.PIEIFR12.all = 0; 57 | 58 | 59 | } 60 | 61 | //--------------------------------------------------------------------------- 62 | // EnableInterrupts: 63 | //--------------------------------------------------------------------------- 64 | // This function enables the PIE module and CPU interrupts 65 | // 66 | void EnableInterrupts() 67 | { 68 | 69 | // Enable the PIE 70 | PieCtrlRegs.PIECTRL.bit.ENPIE = 1; 71 | 72 | // Enables PIE to drive a pulse into the CPU 73 | PieCtrlRegs.PIEACK.all = 0xFFFF; 74 | 75 | // Enable Interrupts at the CPU level 76 | EINT; 77 | 78 | } 79 | 80 | 81 | //=========================================================================== 82 | // End of file. 83 | //=========================================================================== 84 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_Sci.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: March 1, 2007 16:06:07 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Sci.c 6 | // 7 | // TITLE: DSP2833x SCI Initialization & Support Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitSci: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the SCI(s) to a known state. 21 | // 22 | void InitSci(void) 23 | { 24 | // Initialize SCI-A: 25 | 26 | //tbd... 27 | 28 | 29 | // Initialize SCI-B: 30 | 31 | //tbd... 32 | 33 | // Initialize SCI-C: 34 | 35 | //tbd... 36 | } 37 | 38 | //--------------------------------------------------------------------------- 39 | // Example: InitSciGpio: 40 | //--------------------------------------------------------------------------- 41 | // This function initializes GPIO pins to function as SCI pins 42 | // 43 | // Each GPIO pin can be configured as a GPIO pin or up to 3 different 44 | // peripheral functional pins. By default all pins come up as GPIO 45 | // inputs after reset. 46 | // 47 | // Caution: 48 | // Only one GPIO pin should be enabled for SCITXDA/B operation. 49 | // Only one GPIO pin shoudl be enabled for SCIRXDA/B operation. 50 | // Comment out other unwanted lines. 51 | 52 | void InitSciGpio() 53 | { 54 | InitSciaGpio(); 55 | #if DSP28_SCIB 56 | InitScibGpio(); 57 | #endif // if DSP28_SCIB 58 | #if DSP28_SCIC 59 | InitScicGpio(); 60 | #endif // if DSP28_SCIC 61 | } 62 | 63 | void InitSciaGpio() 64 | { 65 | EALLOW; 66 | 67 | /* Enable internal pull-up for the selected pins */ 68 | // Pull-ups can be enabled or disabled disabled by the user. 69 | // This will enable the pullups for the specified pins. 70 | 71 | GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) 72 | GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) 73 | 74 | /* Set qualification for selected pins to asynch only */ 75 | // Inputs are synchronized to SYSCLKOUT by default. 76 | // This will select asynch (no qualification) for the selected pins. 77 | 78 | GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) 79 | 80 | /* Configure SCI-A pins using GPIO regs*/ 81 | // This specifies which of the possible GPIO pins will be SCI functional pins. 82 | 83 | GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation 84 | GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation 85 | 86 | EDIS; 87 | } 88 | 89 | #if DSP28_SCIB 90 | void InitScibGpio() 91 | { 92 | EALLOW; 93 | 94 | /* Enable internal pull-up for the selected pins */ 95 | // Pull-ups can be enabled or disabled disabled by the user. 96 | // This will enable the pullups for the specified pins. 97 | // Comment out other unwanted lines. 98 | 99 | // GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB) 100 | // GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB) 101 | GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB) 102 | // GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB) 103 | 104 | 105 | // GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB) 106 | // GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB) 107 | GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB) 108 | // GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB) 109 | 110 | /* Set qualification for selected pins to asynch only */ 111 | // This will select asynch (no qualification) for the selected pins. 112 | // Comment out other unwanted lines. 113 | 114 | // GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB) 115 | // GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB) 116 | GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB) 117 | // GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB) 118 | 119 | /* Configure SCI-B pins using GPIO regs*/ 120 | // This specifies which of the possible GPIO pins will be SCI functional pins. 121 | // Comment out other unwanted lines. 122 | 123 | // GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation 124 | // GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation 125 | GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation 126 | // GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation 127 | 128 | // GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation 129 | // GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation 130 | GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation 131 | // GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation 132 | 133 | EDIS; 134 | } 135 | #endif // if DSP28_SCIB 136 | 137 | #if DSP28_SCIC 138 | void InitScicGpio() 139 | { 140 | EALLOW; 141 | 142 | /* Enable internal pull-up for the selected pins */ 143 | // Pull-ups can be enabled or disabled disabled by the user. 144 | // This will enable the pullups for the specified pins. 145 | 146 | GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC) 147 | GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC) 148 | 149 | /* Set qualification for selected pins to asynch only */ 150 | // Inputs are synchronized to SYSCLKOUT by default. 151 | // This will select asynch (no qualification) for the selected pins. 152 | 153 | GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC) 154 | 155 | /* Configure SCI-C pins using GPIO regs*/ 156 | // This specifies which of the possible GPIO pins will be SCI functional pins. 157 | 158 | GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 for SCIRXDC operation 159 | GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 for SCITXDC operation 160 | 161 | EDIS; 162 | } 163 | #endif // if DSP28_SCIC 164 | 165 | 166 | //=========================================================================== 167 | // End of file. 168 | //=========================================================================== 169 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_Spi.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:44 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Spi.c 6 | // 7 | // TITLE: DSP2833x SPI Initialization & Support Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitSPI: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the SPI(s) to a known state. 21 | // 22 | void InitSpi(void) 23 | { 24 | // Initialize SPI-A/B/C/D 25 | 26 | //tbd... 27 | 28 | } 29 | 30 | //--------------------------------------------------------------------------- 31 | // Example: InitSpiGpio: 32 | //--------------------------------------------------------------------------- 33 | // This function initializes GPIO pins to function as SPI pins 34 | // 35 | // Each GPIO pin can be configured as a GPIO pin or up to 3 different 36 | // peripheral functional pins. By default all pins come up as GPIO 37 | // inputs after reset. 38 | // 39 | // Caution: 40 | // For each SPI peripheral 41 | // Only one GPIO pin should be enabled for SPISOMO operation. 42 | // Only one GPIO pin should be enabled for SPISOMI operation. 43 | // Only one GPIO pin should be enabled for SPICLKA operation. 44 | // Only one GPIO pin should be enabled for SPISTEA operation. 45 | // Comment out other unwanted lines. 46 | 47 | void InitSpiGpio() 48 | { 49 | 50 | InitSpiaGpio(); 51 | } 52 | 53 | void InitSpiaGpio() 54 | { 55 | 56 | EALLOW; 57 | /* Enable internal pull-up for the selected pins */ 58 | // Pull-ups can be enabled or disabled by the user. 59 | // This will enable the pullups for the specified pins. 60 | // Comment out other unwanted lines. 61 | 62 | GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) 63 | GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) 64 | GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) 65 | GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) 66 | 67 | 68 | // GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA) 69 | // GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA) 70 | // GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA) 71 | // GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA) 72 | 73 | /* Set qualification for selected pins to asynch only */ 74 | // This will select asynch (no qualification) for the selected pins. 75 | // Comment out other unwanted lines. 76 | 77 | GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) 78 | GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) 79 | GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) 80 | GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) 81 | 82 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) 83 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) 84 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) 85 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) 86 | 87 | 88 | /* Configure SPI-A pins using GPIO regs*/ 89 | // This specifies which of the possible GPIO pins will be SPI functional pins. 90 | // Comment out other unwanted lines. 91 | 92 | GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA 93 | GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA 94 | GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA 95 | GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA 96 | 97 | // GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA 98 | // GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA 99 | // GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA 100 | // GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA 101 | 102 | EDIS; 103 | } 104 | 105 | //=========================================================================== 106 | // End of file. 107 | //=========================================================================== 108 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_common/source/DSP2833x_usDelay.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/4 $ 2 | ;// Checkin $Date: July 30, 2007 10:28:57 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_usDelay.asm 6 | ;// 7 | ;// TITLE: Simple delay function 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// This is a simple delay function that can be used to insert a specified 12 | ;// delay into code. 13 | ;// 14 | ;// This function is only accurate if executed from internal zero-waitstate 15 | ;// SARAM. If it is executed from waitstate memory then the delay will be 16 | ;// longer then specified. 17 | ;// 18 | ;// To use this function: 19 | ;// 20 | ;// 1 - update the CPU clock speed in the DSP2833x_Examples.h 21 | ;// file. For example: 22 | ;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed 23 | ;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed 24 | ;// 25 | ;// 2 - Call this function by using the DELAY_US(A) macro 26 | ;// that is defined in the DSP2833x_Examples.h file. This macro 27 | ;// will convert the number of microseconds specified 28 | ;// into a loop count for use with this function. 29 | ;// This count will be based on the CPU frequency you specify. 30 | ;// 31 | ;// 3 - For the most accurate delay 32 | ;// - Execute this function in 0 waitstate RAM. 33 | ;// - Disable interrupts before calling the function 34 | ;// If you do not disable interrupts, then think of 35 | ;// this as an "at least" delay function as the actual 36 | ;// delay may be longer. 37 | ;// 38 | ;// The C assembly call from the DELAY_US(time) macro will 39 | ;// look as follows: 40 | ;// 41 | ;// extern void Delay(long LoopCount); 42 | ;// 43 | ;// MOV AL,#LowLoopCount 44 | ;// MOV AH,#HighLoopCount 45 | ;// LCR _Delay 46 | ;// 47 | ;// Or as follows (if count is less then 16-bits): 48 | ;// 49 | ;// MOV ACC,#LoopCount 50 | ;// LCR _Delay 51 | ;// 52 | ;// 53 | ;//########################################################################### 54 | ;// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 55 | ;// $Release Date: August 4, 2009 $ 56 | ;//########################################################################### 57 | 58 | .def _DSP28x_usDelay 59 | .sect "ramfuncs" 60 | 61 | .global __DSP28x_usDelay 62 | _DSP28x_usDelay: 63 | SUB ACC,#1 64 | BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 65 | LRETR 66 | 67 | ;There is a 9/10 cycle overhead and each loop 68 | ;takes five cycles. The LoopCount is given by 69 | ;the following formula: 70 | ; DELAY_CPU_CYCLES = 9 + 5*LoopCount 71 | ; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 72 | ; The macro DELAY_US(A) performs this calculation for you 73 | ; 74 | ;//=========================================================================== 75 | ;// End of file. 76 | ;//=========================================================================== 77 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/gel/DSP2833x_Peripheral.gel: -------------------------------------------------------------------------------- 1 | /* 2 | /* TI File $Revision: /main/7 $ */ 3 | /* Checkin $Date: June 2, 2008 11:12:27 $ */ 4 | /******************************************************************* */ 5 | /* File: DSP2833x_peripheral.gel */ 6 | /* Description: Adds '2833x registers to the GEL menu in */ 7 | /* Code Composer Studio using the structures defined in the DSP2833x */ 8 | /* header files. The user must have the symbols (.out file) */ 9 | /* loaded from a project using the DSP28 structures in order for */ 10 | /* these menu items to work. If symbols are not loaded, the */ 11 | /* watch window will report "Identifier not found." */ 12 | /* 13 | //##################################################################### 14 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 15 | // $Release Date: August 4, 2009 $ 16 | //##################################################################### 17 | */ 18 | 19 | /* Add a space line to the GEL menu */ 20 | menuitem "____________________________________"; 21 | hotmenu _() {} 22 | 23 | menuitem "Watch DSP2833x Peripheral Structures"; 24 | 25 | hotmenu All_Peripherals_Regs() 26 | { 27 | GEL_WatchAdd("AdcRegs"); 28 | GEL_WatchAdd("AdcMirror"); 29 | GEL_WatchAdd("CsmRegs"); 30 | GEL_WatchAdd("CsmPwl"); 31 | GEL_WatchAdd("CpuTimer0Regs"); 32 | GEL_WatchAdd("CpuTimer1Regs"); 33 | GEL_WatchAdd("CpuTimer2Regs"); 34 | GEL_WatchAdd("DevEmuRegs"); 35 | GEL_WatchAdd("DmaRegs"); 36 | GEL_WatchAdd("ECanaRegs"); 37 | GEL_WatchAdd("ECanaMboxes"); 38 | GEL_WatchAdd("ECanaLAMRegs"); 39 | GEL_WatchAdd("ECanaMOTSRegs"); 40 | GEL_WatchAdd("ECanbRegs"); 41 | GEL_WatchAdd("ECanbMboxes"); 42 | GEL_WatchAdd("ECanbLAMRegs"); 43 | GEL_WatchAdd("ECanbMOTSRegs"); 44 | GEL_WatchAdd("EPwm1Regs"); 45 | GEL_WatchAdd("EPwm2Regs"); 46 | GEL_WatchAdd("EPwm3Regs"); 47 | GEL_WatchAdd("EPwm4Regs"); 48 | GEL_WatchAdd("EPwm5Regs"); 49 | GEL_WatchAdd("EPwm6Regs"); 50 | GEL_WatchAdd("ECap1Regs"); 51 | GEL_WatchAdd("ECap2Regs"); 52 | GEL_WatchAdd("ECap3Regs"); 53 | GEL_WatchAdd("ECap4Regs"); 54 | GEL_WatchAdd("ECap5Regs"); 55 | GEL_WatchAdd("ECap6Regs"); 56 | GEL_WatchAdd("EQep1Regs"); 57 | GEL_WatchAdd("EQep2Regs"); 58 | GEL_WatchAdd("FlashRegs"); 59 | GEL_WatchAdd("XIntruptRegs"); 60 | GEL_WatchAdd("FlashRegs"); 61 | GEL_WatchAdd("GpioCtrlRegs"); 62 | GEL_WatchAdd("GpioDataRegs"); 63 | GEL_WatchAdd("GpioIntRegs"); 64 | GEL_WatchAdd("I2caRegs"); 65 | GEL_WatchAdd("McbspaRegs"); 66 | GEL_WatchAdd("McbspbRegs"); 67 | GEL_WatchAdd("PartIdRegs"); 68 | GEL_WatchAdd("PieCtrlRegs"); 69 | GEL_WatchAdd("PieVectTable"); 70 | GEL_WatchAdd("SciaRegs"); 71 | GEL_WatchAdd("ScibRegs"); 72 | GEL_WatchAdd("ScicRegs"); 73 | GEL_WatchAdd("SpiaRegs"); 74 | GEL_WatchAdd("SysCtrlRegs"); 75 | GEL_WatchAdd("XintfRegs"); 76 | } 77 | hotmenu _______________________() {} 78 | hotmenu ADC_Regs() 79 | { 80 | GEL_WatchAdd("AdcRegs"); 81 | GEL_WatchAdd("AdcMirror"); 82 | } 83 | hotmenu Code_Security_Module_Regs() 84 | { 85 | GEL_WatchAdd("CsmRegs"); 86 | GEL_WatchAdd("CsmPwl"); 87 | } 88 | hotmenu CPU_Timer0_Regs() 89 | { 90 | GEL_WatchAdd("CpuTimer0Regs"); 91 | } 92 | hotmenu CPU_Timer1_Regs() 93 | { 94 | GEL_WatchAdd("CpuTimer1Regs"); 95 | } 96 | hotmenu CPU_Timer2_Regs() 97 | { 98 | GEL_WatchAdd("CpuTimer2Regs"); 99 | } 100 | hotmenu Device_Emulation_Regs() 101 | { 102 | GEL_WatchAdd("DevEmuRegs"); 103 | } 104 | hotmenu DMA_Regs() 105 | { 106 | GEL_WatchAdd("DMARegs"); 107 | } 108 | hotmenu eCANA_Regs() 109 | { 110 | GEL_WatchAdd("ECanaRegs"); 111 | GEL_WatchAdd("ECanaMboxes"); 112 | GEL_WatchAdd("ECanaLAMRegs"); 113 | GEL_WatchAdd("ECanaMOTSRegs"); 114 | } 115 | hotmenu eCANB_Regs() 116 | { 117 | GEL_WatchAdd("ECanbRegs"); 118 | GEL_WatchAdd("ECanbMboxes"); 119 | GEL_WatchAdd("ECanbLAMRegs"); 120 | GEL_WatchAdd("ECanbMOTSRegs"); 121 | } 122 | hotmenu EPWM1_Regs() 123 | { 124 | GEL_WatchAdd("EPwm1Regs"); 125 | } 126 | hotmenu EPWM2_Regs() 127 | { 128 | GEL_WatchAdd("EPwm2Regs"); 129 | } 130 | hotmenu EPWM3_Regs() 131 | { 132 | GEL_WatchAdd("EPwm3Regs"); 133 | } 134 | hotmenu EPWM4_Regs() 135 | { 136 | GEL_WatchAdd("EPwm4Regs"); 137 | } 138 | hotmenu EPWM5_Regs() 139 | { 140 | GEL_WatchAdd("EPwm5Regs"); 141 | } 142 | hotmenu EPWM6_Regs() 143 | { 144 | GEL_WatchAdd("EPwm6Regs"); 145 | } 146 | hotmenu ECAP1_Regs() 147 | { 148 | GEL_WatchAdd("ECap1Regs"); 149 | } 150 | hotmenu ECAP2_Regs() 151 | { 152 | GEL_WatchAdd("ECap2Regs"); 153 | } 154 | hotmenu ECAP3_Regs() 155 | { 156 | GEL_WatchAdd("ECap3Regs"); 157 | } 158 | hotmenu ECAP4_Regs() 159 | { 160 | GEL_WatchAdd("ECap4Regs"); 161 | } 162 | hotmenu ECAP5_Regs() 163 | { 164 | GEL_WatchAdd("ECap5Regs"); 165 | } 166 | hotmenu ECAP6_Regs() 167 | { 168 | GEL_WatchAdd("ECap6Regs"); 169 | } 170 | hotmenu EQEP1_Regs() 171 | { 172 | GEL_WatchAdd("EQep1Regs"); 173 | } 174 | hotmenu EQEP2_Regs() 175 | { 176 | GEL_WatchAdd("EQep2Regs"); 177 | } 178 | hotmenu External_Interface_Regs() 179 | { 180 | GEL_WatchAdd("XintfRegs"); 181 | } 182 | hotmenu External_Interrupt_Regs() 183 | { 184 | GEL_WatchAdd("XIntruptRegs"); 185 | } 186 | hotmenu Flash_and_OTP_Regs() 187 | { 188 | GEL_WatchAdd("FlashRegs"); 189 | } 190 | hotmenu GPIO_CTRL_Regs() 191 | { 192 | GEL_WatchAdd("GpioCtrlRegs"); 193 | } 194 | hotmenu GPIO_DATA_Regs() 195 | { 196 | GEL_WatchAdd("GpioDataRegs"); 197 | } 198 | hotmenu GPIO_INT_Regs() 199 | { 200 | GEL_WatchAdd("GpioIntRegs"); 201 | } 202 | hotmenu I2CA_Regs() 203 | { 204 | GEL_WatchAdd("I2caRegs"); 205 | } 206 | hotmenu McBSPA_Regs() 207 | { 208 | GEL_WatchAdd("McbspaRegs"); 209 | } 210 | hotmenu McBSPB_Regs() 211 | { 212 | GEL_WatchAdd("McbspbRegs"); 213 | } 214 | hotmenu PartId_Regs() 215 | { 216 | GEL_WatchAdd("PartIdRegs"); 217 | } 218 | hotmenu PIE_Control_Regs() 219 | { 220 | GEL_WatchAdd("PieCtrlRegs"); 221 | } 222 | hotmenu SCIA_Regs() 223 | { 224 | GEL_WatchAdd("SciaRegs"); 225 | } 226 | hotmenu SCIB_Regs() 227 | { 228 | GEL_WatchAdd("ScibRegs"); 229 | } 230 | hotmenu SPIA_Regs() 231 | { 232 | GEL_WatchAdd("SpiaRegs"); 233 | } 234 | hotmenu System_and_Control_Regs() 235 | { 236 | GEL_WatchAdd("SysCtrlRegs"); 237 | } 238 | 239 | 240 | 241 | /* 242 | //=========================================================================== 243 | // End of file. 244 | //=========================================================================== 245 | */ 246 | 247 | 248 | 249 | 250 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_CpuTimers.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: March 20, 2007 15:33:42 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_CpuTimers.h 6 | // 7 | // TITLE: DSP2833x CPU 32-bit Timers Register Definitions. 8 | // 9 | // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and 10 | // other realtime operating systems. 11 | // 12 | // Do not use these two timers in your application if you ever plan 13 | // on integrating DSP-BIOS or another realtime OS. 14 | // 15 | // For this reason, comment out the code to manipulate these two timers 16 | // if using DSP-BIOS or another realtime OS. 17 | // 18 | //########################################################################### 19 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 20 | // $Release Date: August 4, 2009 $ 21 | //########################################################################### 22 | 23 | #ifndef DSP2833x_CPU_TIMERS_H 24 | #define DSP2833x_CPU_TIMERS_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | //--------------------------------------------------------------------------- 31 | // CPU Timer Register Bit Definitions: 32 | // 33 | // 34 | // TCR: Control register bit definitions: 35 | struct TCR_BITS { // bits description 36 | Uint16 rsvd1:4; // 3:0 reserved 37 | Uint16 TSS:1; // 4 Timer Start/Stop 38 | Uint16 TRB:1; // 5 Timer reload 39 | Uint16 rsvd2:4; // 9:6 reserved 40 | Uint16 SOFT:1; // 10 Emulation modes 41 | Uint16 FREE:1; // 11 42 | Uint16 rsvd3:2; // 12:13 reserved 43 | Uint16 TIE:1; // 14 Output enable 44 | Uint16 TIF:1; // 15 Interrupt flag 45 | }; 46 | 47 | union TCR_REG { 48 | Uint16 all; 49 | struct TCR_BITS bit; 50 | }; 51 | 52 | // TPR: Pre-scale low bit definitions: 53 | struct TPR_BITS { // bits description 54 | Uint16 TDDR:8; // 7:0 Divide-down low 55 | Uint16 PSC:8; // 15:8 Prescale counter low 56 | }; 57 | 58 | union TPR_REG { 59 | Uint16 all; 60 | struct TPR_BITS bit; 61 | }; 62 | 63 | // TPRH: Pre-scale high bit definitions: 64 | struct TPRH_BITS { // bits description 65 | Uint16 TDDRH:8; // 7:0 Divide-down high 66 | Uint16 PSCH:8; // 15:8 Prescale counter high 67 | }; 68 | 69 | union TPRH_REG { 70 | Uint16 all; 71 | struct TPRH_BITS bit; 72 | }; 73 | 74 | // TIM, TIMH: Timer register definitions: 75 | struct TIM_REG { 76 | Uint16 LSW; 77 | Uint16 MSW; 78 | }; 79 | 80 | union TIM_GROUP { 81 | Uint32 all; 82 | struct TIM_REG half; 83 | }; 84 | 85 | // PRD, PRDH: Period register definitions: 86 | struct PRD_REG { 87 | Uint16 LSW; 88 | Uint16 MSW; 89 | }; 90 | 91 | union PRD_GROUP { 92 | Uint32 all; 93 | struct PRD_REG half; 94 | }; 95 | 96 | //--------------------------------------------------------------------------- 97 | // CPU Timer Register File: 98 | // 99 | struct CPUTIMER_REGS { 100 | union TIM_GROUP TIM; // Timer counter register 101 | union PRD_GROUP PRD; // Period register 102 | union TCR_REG TCR; // Timer control register 103 | Uint16 rsvd1; // reserved 104 | union TPR_REG TPR; // Timer pre-scale low 105 | union TPRH_REG TPRH; // Timer pre-scale high 106 | }; 107 | 108 | //--------------------------------------------------------------------------- 109 | // CPU Timer Support Variables: 110 | // 111 | struct CPUTIMER_VARS { 112 | volatile struct CPUTIMER_REGS *RegsAddr; 113 | Uint32 InterruptCount; 114 | float CPUFreqInMHz; 115 | float PeriodInUSec; 116 | }; 117 | 118 | //--------------------------------------------------------------------------- 119 | // Function prototypes and external definitions: 120 | // 121 | void InitCpuTimers(void); 122 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 123 | 124 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 125 | extern struct CPUTIMER_VARS CpuTimer0; 126 | 127 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS 128 | extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 129 | extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 130 | 131 | extern struct CPUTIMER_VARS CpuTimer1; 132 | extern struct CPUTIMER_VARS CpuTimer2; 133 | 134 | //--------------------------------------------------------------------------- 135 | // Usefull Timer Operations: 136 | // 137 | // Start Timer: 138 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 139 | 140 | // Stop Timer: 141 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 142 | 143 | // Reload Timer With period Value: 144 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 145 | 146 | // Read 32-Bit Timer Value: 147 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 148 | 149 | // Read 32-Bit Period Value: 150 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 151 | 152 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 153 | // Do not use these two timers if you ever plan on integrating 154 | // DSP-BIOS or another realtime OS. 155 | // 156 | // For this reason, comment out the code to manipulate these two timers 157 | // if using DSP-BIOS or another realtime OS. 158 | 159 | // Start Timer: 160 | #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 161 | #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 162 | 163 | 164 | // Stop Timer: 165 | #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 166 | #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 167 | 168 | // Reload Timer With period Value: 169 | #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 170 | #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 171 | 172 | // Read 32-Bit Timer Value: 173 | #define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 174 | #define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 175 | 176 | // Read 32-Bit Period Value: 177 | #define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 178 | #define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 179 | 180 | 181 | #ifdef __cplusplus 182 | } 183 | #endif /* extern "C" */ 184 | 185 | #endif // end of DSP2833x_CPU_TIMERS_H definition 186 | 187 | 188 | //=========================================================================== 189 | // End of file. 190 | //=========================================================================== 191 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_DevEmu.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: April 15, 2009 10:05:17 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_DevEmu.h 6 | // 7 | // TITLE: DSP2833x Device Emulation Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_DEV_EMU_H 15 | #define DSP2833x_DEV_EMU_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | //--------------------------------------------------------------------------- 22 | // Device Emulation Register Bit Definitions: 23 | // 24 | // Device Configuration Register Bit Definitions 25 | struct DEVICECNF_BITS { // bits description 26 | Uint16 rsvd1:3; // 2:0 reserved 27 | Uint16 VMAPS:1; // 3 VMAP Status 28 | Uint16 rsvd2:1; // 4 reserved 29 | Uint16 XRSn:1; // 5 XRSn Signal Status 30 | Uint16 rsvd3:10; // 15:6 31 | Uint16 rsvd4:3; // 18:16 32 | Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection 33 | Uint16 rsvd5:7; // 26:20 reserved 34 | Uint16 TRSTN:1; // 27 Status of TRSTn signal 35 | Uint16 rsvd6:4; // 31:28 reserved 36 | }; 37 | 38 | union DEVICECNF_REG { 39 | Uint32 all; 40 | struct DEVICECNF_BITS bit; 41 | }; 42 | 43 | // CLASSID 44 | struct CLASSID_BITS { // bits description 45 | Uint16 CLASSNO:8; // 7:0 Class Number 46 | Uint16 PARTTYPE:8; // 15:8 Part Type 47 | }; 48 | 49 | union CLASSID_REG { 50 | Uint16 all; 51 | struct CLASSID_BITS bit; 52 | }; 53 | 54 | struct DEV_EMU_REGS { 55 | union DEVICECNF_REG DEVICECNF; // device configuration 56 | union CLASSID_REG CLASSID; // Class ID 57 | Uint16 REVID; // Device ID 58 | Uint16 PROTSTART; // Write-Read protection start 59 | Uint16 PROTRANGE; // Write-Read protection range 60 | Uint16 rsvd2[202]; 61 | }; 62 | 63 | // PARTID 64 | struct PARTID_BITS { // bits description 65 | Uint16 PARTNO:8; // 7:0 Part Number 66 | Uint16 PARTTYPE:8; // 15:8 Part Type 67 | }; 68 | 69 | union PARTID_REG { 70 | Uint16 all; 71 | struct PARTID_BITS bit; 72 | }; 73 | 74 | struct PARTID_REGS { 75 | union PARTID_REG PARTID; // Part ID 76 | }; 77 | 78 | 79 | 80 | //--------------------------------------------------------------------------- 81 | // Device Emulation Register References & Function Declarations: 82 | // 83 | extern volatile struct DEV_EMU_REGS DevEmuRegs; 84 | extern volatile struct PARTID_REGS PartIdRegs; 85 | 86 | #ifdef __cplusplus 87 | } 88 | #endif /* extern "C" */ 89 | 90 | #endif // end of DSP2833x_DEV_EMU_H definition 91 | 92 | //=========================================================================== 93 | // End of file. 94 | //=========================================================================== 95 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_Device.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/5 $ 2 | // Checkin $Date: January 22, 2008 16:55:35 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Device.h 6 | // 7 | // TITLE: DSP2833x Device Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_DEVICE_H 15 | #define DSP2833x_DEVICE_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | #define TARGET 1 24 | //--------------------------------------------------------------------------- 25 | // User To Select Target Device: 26 | 27 | #define DSP28_28335 TARGET // Selects '28335/'28235 28 | #define DSP28_28334 0 // Selects '28334/'28234 29 | #define DSP28_28332 0 // Selects '28332/'28232 30 | 31 | 32 | //--------------------------------------------------------------------------- 33 | // Common CPU Definitions: 34 | // 35 | 36 | extern cregister volatile unsigned int IFR; 37 | extern cregister volatile unsigned int IER; 38 | 39 | #define EINT asm(" clrc INTM") 40 | #define DINT asm(" setc INTM") 41 | #define ERTM asm(" clrc DBGM") 42 | #define DRTM asm(" setc DBGM") 43 | #define EALLOW asm(" EALLOW") 44 | #define EDIS asm(" EDIS") 45 | #define ESTOP0 asm(" ESTOP0") 46 | 47 | #define M_INT1 0x0001 48 | #define M_INT2 0x0002 49 | #define M_INT3 0x0004 50 | #define M_INT4 0x0008 51 | #define M_INT5 0x0010 52 | #define M_INT6 0x0020 53 | #define M_INT7 0x0040 54 | #define M_INT8 0x0080 55 | #define M_INT9 0x0100 56 | #define M_INT10 0x0200 57 | #define M_INT11 0x0400 58 | #define M_INT12 0x0800 59 | #define M_INT13 0x1000 60 | #define M_INT14 0x2000 61 | #define M_DLOG 0x4000 62 | #define M_RTOS 0x8000 63 | 64 | #define BIT0 0x0001 65 | #define BIT1 0x0002 66 | #define BIT2 0x0004 67 | #define BIT3 0x0008 68 | #define BIT4 0x0010 69 | #define BIT5 0x0020 70 | #define BIT6 0x0040 71 | #define BIT7 0x0080 72 | #define BIT8 0x0100 73 | #define BIT9 0x0200 74 | #define BIT10 0x0400 75 | #define BIT11 0x0800 76 | #define BIT12 0x1000 77 | #define BIT13 0x2000 78 | #define BIT14 0x4000 79 | #define BIT15 0x8000 80 | 81 | 82 | 83 | //--------------------------------------------------------------------------- 84 | // For Portability, User Is Recommended To Use Following Data Type Size 85 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 86 | // 87 | 88 | #ifndef DSP28_DATA_TYPES 89 | #define DSP28_DATA_TYPES 90 | typedef int int16; 91 | typedef long int32; 92 | typedef long long int64; 93 | typedef unsigned int Uint16; 94 | typedef unsigned long Uint32; 95 | typedef unsigned long long Uint64; 96 | typedef float float32; 97 | typedef long double float64; 98 | #endif 99 | 100 | 101 | //--------------------------------------------------------------------------- 102 | // Include All Peripheral Header Files: 103 | // 104 | 105 | #include "DSP2833x_Adc.h" // ADC Registers 106 | #include "DSP2833x_DevEmu.h" // Device Emulation Registers 107 | #include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers 108 | #include "DSP2833x_ECan.h" // Enhanced eCAN Registers 109 | #include "DSP2833x_ECap.h" // Enhanced Capture 110 | #include "DSP2833x_DMA.h" // DMA Registers 111 | #include "DSP2833x_EPwm.h" // Enhanced PWM 112 | #include "DSP2833x_EQep.h" // Enhanced QEP 113 | #include "DSP2833x_Gpio.h" // General Purpose I/O Registers 114 | #include "DSP2833x_I2c.h" // I2C Registers 115 | #include "DSP2833x_McBSP.h" // McBSP 116 | #include "DSP2833x_PieCtrl.h" // PIE Control Registers 117 | #include "DSP2833x_PieVect.h" // PIE Vector Table 118 | #include "DSP2833x_Spi.h" // SPI Registers 119 | #include "DSP2833x_Sci.h" // SCI Registers 120 | #include "DSP2833x_SysCtrl.h" // System Control/Power Modes 121 | #include "DSP2833x_XIntrupt.h" // External Interrupts 122 | #include "DSP2833x_Xintf.h" // XINTF External Interface 123 | 124 | #if DSP28_28335 125 | #define DSP28_EPWM1 1 126 | #define DSP28_EPWM2 1 127 | #define DSP28_EPWM3 1 128 | #define DSP28_EPWM4 1 129 | #define DSP28_EPWM5 1 130 | #define DSP28_EPWM6 1 131 | #define DSP28_ECAP1 1 132 | #define DSP28_ECAP2 1 133 | #define DSP28_ECAP3 1 134 | #define DSP28_ECAP4 1 135 | #define DSP28_ECAP5 1 136 | #define DSP28_ECAP6 1 137 | #define DSP28_EQEP1 1 138 | #define DSP28_EQEP2 1 139 | #define DSP28_ECANA 1 140 | #define DSP28_ECANB 1 141 | #define DSP28_MCBSPA 1 142 | #define DSP28_MCBSPB 1 143 | #define DSP28_SPIA 1 144 | #define DSP28_SCIA 1 145 | #define DSP28_SCIB 0 146 | #define DSP28_SCIC 0 147 | #define DSP28_I2CA 1 148 | #endif // end DSP28_28335 149 | 150 | #if DSP28_28334 151 | #define DSP28_EPWM1 1 152 | #define DSP28_EPWM2 1 153 | #define DSP28_EPWM3 1 154 | #define DSP28_EPWM4 1 155 | #define DSP28_EPWM5 1 156 | #define DSP28_EPWM6 1 157 | #define DSP28_ECAP1 1 158 | #define DSP28_ECAP2 1 159 | #define DSP28_ECAP3 1 160 | #define DSP28_ECAP4 1 161 | #define DSP28_ECAP5 0 162 | #define DSP28_ECAP6 0 163 | #define DSP28_EQEP1 1 164 | #define DSP28_EQEP2 1 165 | #define DSP28_ECANA 1 166 | #define DSP28_ECANB 1 167 | #define DSP28_MCBSPA 1 168 | #define DSP28_MCBSPB 1 169 | #define DSP28_SPIA 1 170 | #define DSP28_SCIA 1 171 | #define DSP28_SCIB 1 172 | #define DSP28_SCIC 1 173 | #define DSP28_I2CA 1 174 | #endif // end DSP28_28334 175 | 176 | #if DSP28_28332 177 | #define DSP28_EPWM1 1 178 | #define DSP28_EPWM2 1 179 | #define DSP28_EPWM3 1 180 | #define DSP28_EPWM4 1 181 | #define DSP28_EPWM5 1 182 | #define DSP28_EPWM6 1 183 | #define DSP28_ECAP1 1 184 | #define DSP28_ECAP2 1 185 | #define DSP28_ECAP3 1 186 | #define DSP28_ECAP4 1 187 | #define DSP28_ECAP5 0 188 | #define DSP28_ECAP6 0 189 | #define DSP28_EQEP1 1 190 | #define DSP28_EQEP2 1 191 | #define DSP28_ECANA 1 192 | #define DSP28_ECANB 1 193 | #define DSP28_MCBSPA 1 194 | #define DSP28_MCBSPB 0 195 | #define DSP28_SPIA 1 196 | #define DSP28_SCIA 1 197 | #define DSP28_SCIB 1 198 | #define DSP28_SCIC 0 199 | #define DSP28_I2CA 1 200 | #endif // end DSP28_28332 201 | 202 | #ifdef __cplusplus 203 | } 204 | #endif /* extern "C" */ 205 | 206 | #endif // end of DSP2833x_DEVICE_H definition 207 | 208 | 209 | //=========================================================================== 210 | // End of file. 211 | //=========================================================================== 212 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_ECap.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:52:07 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_ECap.h 6 | // 7 | // TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_ECAP_H 15 | #define DSP2833x_ECAP_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //---------------------------------------------------- 23 | // Capture control register 1 bit definitions */ 24 | struct ECCTL1_BITS { // bits description 25 | Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select 26 | Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 27 | Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select 28 | Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 29 | Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select 30 | Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 31 | Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select 32 | Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 33 | Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event 34 | Uint16 PRESCALE:5; // 13:9 Event Filter prescale select 35 | Uint16 FREE_SOFT:2; // 15:14 Emulation mode 36 | }; 37 | 38 | union ECCTL1_REG { 39 | Uint16 all; 40 | struct ECCTL1_BITS bit; 41 | }; 42 | 43 | 44 | // In V1.1 the STOPVALUE bit field was changed to 45 | // STOP_WRAP. This correlated to a silicon change from 46 | // F2833x Rev 0 to Rev A. 47 | //---------------------------------------------------- 48 | // Capture control register 2 bit definitions */ 49 | struct ECCTL2_BITS { // bits description 50 | Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot 51 | Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous 52 | Uint16 REARM:1; // 3 One-shot re-arm 53 | Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop 54 | Uint16 SYNCI_EN:1; // 5 Counter sync-in select 55 | Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode 56 | Uint16 SWSYNC:1; // 8 SW forced counter sync 57 | Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select 58 | Uint16 APWMPOL:1; // 10 APWM output polarity select 59 | Uint16 rsvd1:5; // 15:11 60 | }; 61 | 62 | 63 | union ECCTL2_REG { 64 | Uint16 all; 65 | struct ECCTL2_BITS bit; 66 | }; 67 | 68 | 69 | //---------------------------------------------------- 70 | // ECAP interrupt enable register bit definitions */ 71 | struct ECEINT_BITS { // bits description 72 | Uint16 rsvd1:1; // 0 reserved 73 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable 74 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable 75 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable 76 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable 77 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable 78 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable 79 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable 80 | Uint16 rsvd2:8; // 15:8 reserved 81 | }; 82 | 83 | 84 | union ECEINT_REG { 85 | Uint16 all; 86 | struct ECEINT_BITS bit; 87 | }; 88 | 89 | //---------------------------------------------------- 90 | // ECAP interrupt flag register bit definitions */ 91 | struct ECFLG_BITS { // bits description 92 | Uint16 INT:1; // 0 Global Flag 93 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag 94 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag 95 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag 96 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag 97 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag 98 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag 99 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag 100 | Uint16 rsvd2:8; // 15:8 reserved 101 | }; 102 | 103 | 104 | union ECFLG_REG { 105 | Uint16 all; 106 | struct ECFLG_BITS bit; 107 | }; 108 | 109 | 110 | //---------------------------------------------------- 111 | 112 | struct ECAP_REGS { 113 | Uint32 TSCTR; // Time stamp counter 114 | Uint32 CTRPHS; // Counter phase 115 | Uint32 CAP1; // Capture 1 116 | Uint32 CAP2; // Capture 2 117 | Uint32 CAP3; // Capture 3 118 | Uint32 CAP4; // Capture 4 119 | Uint16 rsvd1[8]; // reserved 120 | union ECCTL1_REG ECCTL1; // Capture Control Reg 1 121 | union ECCTL2_REG ECCTL2; // Capture Control Reg 2 122 | union ECEINT_REG ECEINT; // ECAP interrupt enable 123 | union ECFLG_REG ECFLG; // ECAP interrupt flags 124 | union ECFLG_REG ECCLR; // ECAP interrupt clear 125 | union ECEINT_REG ECFRC; // ECAP interrupt force 126 | Uint16 rsvd2[6]; // reserved 127 | }; 128 | 129 | 130 | 131 | 132 | //--------------------------------------------------------------------------- 133 | // GPI/O External References & Function Declarations: 134 | // 135 | extern volatile struct ECAP_REGS ECap1Regs; 136 | extern volatile struct ECAP_REGS ECap2Regs; 137 | extern volatile struct ECAP_REGS ECap3Regs; 138 | extern volatile struct ECAP_REGS ECap4Regs; 139 | extern volatile struct ECAP_REGS ECap5Regs; 140 | extern volatile struct ECAP_REGS ECap6Regs; 141 | 142 | 143 | #ifdef __cplusplus 144 | } 145 | #endif /* extern "C" */ 146 | 147 | #endif // end of DSP2833x_ECAP_H definition 148 | 149 | //=========================================================================== 150 | // End of file. 151 | //=========================================================================== 152 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_I2c.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: March 22, 2007 10:40:22 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_I2c.h 6 | // 7 | // TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module 8 | // Register Bit Definitions. 9 | // 10 | //########################################################################### 11 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 12 | // $Release Date: August 4, 2009 $ 13 | //########################################################################### 14 | 15 | #ifndef DSP2833x_I2C_H 16 | #define DSP2833x_I2C_H 17 | 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | 24 | //---------------------------------------------------- 25 | // I2C interrupt vector register bit definitions */ 26 | struct I2CISRC_BITS { // bits description 27 | Uint16 INTCODE:3; // 2:0 Interrupt code 28 | Uint16 rsvd1:13; // 15:3 reserved 29 | }; 30 | 31 | union I2CISRC_REG { 32 | Uint16 all; 33 | struct I2CISRC_BITS bit; 34 | }; 35 | 36 | //---------------------------------------------------- 37 | // I2C interrupt mask register bit definitions */ 38 | struct I2CIER_BITS { // bits description 39 | Uint16 ARBL:1; // 0 Arbitration lost interrupt 40 | Uint16 NACK:1; // 1 No ack interrupt 41 | Uint16 ARDY:1; // 2 Register access ready interrupt 42 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 43 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 44 | Uint16 SCD:1; // 5 Stop condition detection 45 | Uint16 AAS:1; // 6 Address as slave 46 | Uint16 rsvd:9; // 15:7 reserved 47 | }; 48 | 49 | union I2CIER_REG { 50 | Uint16 all; 51 | struct I2CIER_BITS bit; 52 | }; 53 | 54 | //---------------------------------------------------- 55 | // I2C status register bit definitions */ 56 | struct I2CSTR_BITS { // bits description 57 | Uint16 ARBL:1; // 0 Arbitration lost interrupt 58 | Uint16 NACK:1; // 1 No ack interrupt 59 | Uint16 ARDY:1; // 2 Register access ready interrupt 60 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 61 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 62 | Uint16 SCD:1; // 5 Stop condition detection 63 | Uint16 rsvd1:2; // 7:6 reserved 64 | Uint16 AD0:1; // 8 Address Zero 65 | Uint16 AAS:1; // 9 Address as slave 66 | Uint16 XSMT:1; // 10 XMIT shift empty 67 | Uint16 RSFULL:1; // 11 Recieve shift full 68 | Uint16 BB:1; // 12 Bus busy 69 | Uint16 NACKSNT:1; // 13 A no ack sent 70 | Uint16 SDIR:1; // 14 Slave direction 71 | Uint16 rsvd2:1; // 15 reserved 72 | }; 73 | 74 | union I2CSTR_REG { 75 | Uint16 all; 76 | struct I2CSTR_BITS bit; 77 | }; 78 | 79 | 80 | //---------------------------------------------------- 81 | // I2C mode control register bit definitions */ 82 | struct I2CMDR_BITS { // bits description 83 | Uint16 BC:3; // 2:0 Bit count 84 | Uint16 FDF:1; // 3 Free data format 85 | Uint16 STB:1; // 4 Start byte 86 | Uint16 IRS:1; // 5 I2C Reset not 87 | Uint16 DLB:1; // 6 Digital loopback 88 | Uint16 RM:1; // 7 Repeat mode 89 | Uint16 XA:1; // 8 Expand address 90 | Uint16 TRX:1; // 9 Transmitter/reciever 91 | Uint16 MST:1; // 10 Master/slave 92 | Uint16 STP:1; // 11 Stop condition 93 | Uint16 rsvd1:1; // 12 reserved 94 | Uint16 STT:1; // 13 Start condition 95 | Uint16 FREE:1; // 14 Emulation mode 96 | Uint16 NACKMOD:1; // 15 No Ack mode 97 | }; 98 | 99 | union I2CMDR_REG { 100 | Uint16 all; 101 | struct I2CMDR_BITS bit; 102 | }; 103 | 104 | //---------------------------------------------------- 105 | // I2C pre-scaler register bit definitions */ 106 | struct I2CPSC_BITS { // bits description 107 | Uint16 IPSC:8; // 7:0 pre-scaler 108 | Uint16 rsvd1:8; // 15:8 reserved 109 | }; 110 | 111 | 112 | union I2CPSC_REG { 113 | Uint16 all; 114 | struct I2CPSC_BITS bit; 115 | }; 116 | 117 | 118 | //---------------------------------------------------- 119 | // TX FIFO control register bit definitions */ 120 | struct I2CFFTX_BITS { // bits description 121 | Uint16 TXFFIL:5; // 4:0 FIFO interrupt level 122 | Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable 123 | Uint16 TXFFINTCLR:1; // 6 FIFO clear 124 | Uint16 TXFFINT:1; // 7 FIFO interrupt flag 125 | Uint16 TXFFST:5; // 12:8 FIFO level status 126 | Uint16 TXFFRST:1; // 13 FIFO reset 127 | Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs 128 | Uint16 rsvd1:1; // 15 reserved 129 | 130 | }; 131 | 132 | union I2CFFTX_REG { 133 | Uint16 all; 134 | struct I2CFFTX_BITS bit; 135 | }; 136 | 137 | //---------------------------------------------------- 138 | // RX FIFO control register bit definitions */ 139 | struct I2CFFRX_BITS { // bits description 140 | Uint16 RXFFIL:5; // 4:0 FIFO interrupt level 141 | Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable 142 | Uint16 RXFFINTCLR:1; // 6 FIFO clear 143 | Uint16 RXFFINT:1; // 7 FIFO interrupt flag 144 | Uint16 RXFFST:5; // 12:8 FIFO level 145 | Uint16 RXFFRST:1; // 13 FIFO reset 146 | Uint16 rsvd1:2; // 15:14 reserved 147 | }; 148 | 149 | union I2CFFRX_REG { 150 | Uint16 all; 151 | struct I2CFFRX_BITS bit; 152 | }; 153 | 154 | 155 | //---------------------------------------------------- 156 | 157 | struct I2C_REGS { 158 | Uint16 I2COAR; // Own address register 159 | union I2CIER_REG I2CIER; // Interrupt enable 160 | union I2CSTR_REG I2CSTR; // Interrupt status 161 | Uint16 I2CCLKL; // Clock divider low 162 | Uint16 I2CCLKH; // Clock divider high 163 | Uint16 I2CCNT; // Data count 164 | Uint16 I2CDRR; // Data recieve 165 | Uint16 I2CSAR; // Slave address 166 | Uint16 I2CDXR; // Data transmit 167 | union I2CMDR_REG I2CMDR; // Mode 168 | union I2CISRC_REG I2CISRC; // Interrupt source 169 | Uint16 rsvd1; // reserved 170 | union I2CPSC_REG I2CPSC; // Pre-scaler 171 | Uint16 rsvd2[19]; // reserved 172 | union I2CFFTX_REG I2CFFTX; // Transmit FIFO 173 | union I2CFFRX_REG I2CFFRX; // Recieve FIFO 174 | }; 175 | 176 | 177 | 178 | 179 | //--------------------------------------------------------------------------- 180 | // External References & Function Declarations: 181 | // 182 | extern volatile struct I2C_REGS I2caRegs; 183 | 184 | 185 | #ifdef __cplusplus 186 | } 187 | #endif /* extern "C" */ 188 | 189 | #endif // end of DSP2833x_I2C_H definition 190 | 191 | //=========================================================================== 192 | // End of file. 193 | //=========================================================================== 194 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_PieCtrl.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:52:24 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_PieCtrl.h 6 | // 7 | // TITLE: DSP2833x Device PIE Control Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | 15 | #ifndef DSP2833x_PIE_CTRL_H 16 | #define DSP2833x_PIE_CTRL_H 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | // PIE Control Register Bit Definitions: 24 | // 25 | // PIECTRL: Register bit definitions: 26 | struct PIECTRL_BITS { // bits description 27 | Uint16 ENPIE:1; // 0 Enable PIE block 28 | Uint16 PIEVECT:15; // 15:1 Fetched vector address 29 | }; 30 | 31 | union PIECTRL_REG { 32 | Uint16 all; 33 | struct PIECTRL_BITS bit; 34 | }; 35 | 36 | // PIEIER: Register bit definitions: 37 | struct PIEIER_BITS { // bits description 38 | Uint16 INTx1:1; // 0 INTx.1 39 | Uint16 INTx2:1; // 1 INTx.2 40 | Uint16 INTx3:1; // 2 INTx.3 41 | Uint16 INTx4:1; // 3 INTx.4 42 | Uint16 INTx5:1; // 4 INTx.5 43 | Uint16 INTx6:1; // 5 INTx.6 44 | Uint16 INTx7:1; // 6 INTx.7 45 | Uint16 INTx8:1; // 7 INTx.8 46 | Uint16 rsvd:8; // 15:8 reserved 47 | }; 48 | 49 | union PIEIER_REG { 50 | Uint16 all; 51 | struct PIEIER_BITS bit; 52 | }; 53 | 54 | // PIEIFR: Register bit definitions: 55 | struct PIEIFR_BITS { // bits description 56 | Uint16 INTx1:1; // 0 INTx.1 57 | Uint16 INTx2:1; // 1 INTx.2 58 | Uint16 INTx3:1; // 2 INTx.3 59 | Uint16 INTx4:1; // 3 INTx.4 60 | Uint16 INTx5:1; // 4 INTx.5 61 | Uint16 INTx6:1; // 5 INTx.6 62 | Uint16 INTx7:1; // 6 INTx.7 63 | Uint16 INTx8:1; // 7 INTx.8 64 | Uint16 rsvd:8; // 15:8 reserved 65 | }; 66 | 67 | union PIEIFR_REG { 68 | Uint16 all; 69 | struct PIEIFR_BITS bit; 70 | }; 71 | 72 | // PIEACK: Register bit definitions: 73 | struct PIEACK_BITS { // bits description 74 | Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 75 | Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 76 | Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 77 | Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 78 | Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 79 | Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 80 | Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 81 | Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 82 | Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 83 | Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 84 | Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 85 | Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 86 | Uint16 rsvd:4; // 15:12 reserved 87 | }; 88 | 89 | union PIEACK_REG { 90 | Uint16 all; 91 | struct PIEACK_BITS bit; 92 | }; 93 | 94 | //--------------------------------------------------------------------------- 95 | // PIE Control Register File: 96 | // 97 | struct PIE_CTRL_REGS { 98 | union PIECTRL_REG PIECTRL; // PIE control register 99 | union PIEACK_REG PIEACK; // PIE acknowledge 100 | union PIEIER_REG PIEIER1; // PIE int1 IER register 101 | union PIEIFR_REG PIEIFR1; // PIE int1 IFR register 102 | union PIEIER_REG PIEIER2; // PIE INT2 IER register 103 | union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register 104 | union PIEIER_REG PIEIER3; // PIE INT3 IER register 105 | union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register 106 | union PIEIER_REG PIEIER4; // PIE INT4 IER register 107 | union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register 108 | union PIEIER_REG PIEIER5; // PIE INT5 IER register 109 | union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register 110 | union PIEIER_REG PIEIER6; // PIE INT6 IER register 111 | union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register 112 | union PIEIER_REG PIEIER7; // PIE INT7 IER register 113 | union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register 114 | union PIEIER_REG PIEIER8; // PIE INT8 IER register 115 | union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register 116 | union PIEIER_REG PIEIER9; // PIE INT9 IER register 117 | union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register 118 | union PIEIER_REG PIEIER10; // PIE int10 IER register 119 | union PIEIFR_REG PIEIFR10; // PIE int10 IFR register 120 | union PIEIER_REG PIEIER11; // PIE int11 IER register 121 | union PIEIFR_REG PIEIFR11; // PIE int11 IFR register 122 | union PIEIER_REG PIEIER12; // PIE int12 IER register 123 | union PIEIFR_REG PIEIFR12; // PIE int12 IFR register 124 | }; 125 | 126 | #define PIEACK_GROUP1 0x0001 127 | #define PIEACK_GROUP2 0x0002 128 | #define PIEACK_GROUP3 0x0004 129 | #define PIEACK_GROUP4 0x0008 130 | #define PIEACK_GROUP5 0x0010 131 | #define PIEACK_GROUP6 0x0020 132 | #define PIEACK_GROUP7 0x0040 133 | #define PIEACK_GROUP8 0x0080 134 | #define PIEACK_GROUP9 0x0100 135 | #define PIEACK_GROUP10 0x0200 136 | #define PIEACK_GROUP11 0x0400 137 | #define PIEACK_GROUP12 0x0800 138 | 139 | //--------------------------------------------------------------------------- 140 | // PIE Control Registers External References & Function Declarations: 141 | // 142 | extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 143 | 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif /* extern "C" */ 148 | 149 | #endif // end of DSP2833x_PIE_CTRL_H definition 150 | 151 | //=========================================================================== 152 | // End of file. 153 | //=========================================================================== 154 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_PieVect.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: March 16, 2007 09:00:21 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_PieVect.h 6 | // 7 | // TITLE: DSP2833x Devices PIE Vector Table Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_PIE_VECT_H 15 | #define DSP2833x_PIE_VECT_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | //--------------------------------------------------------------------------- 24 | // PIE Interrupt Vector Table Definition: 25 | // 26 | // Create a user type called PINT (pointer to interrupt): 27 | 28 | typedef interrupt void(*PINT)(void); 29 | 30 | // Define Vector Table: 31 | struct PIE_VECT_TABLE { 32 | 33 | // Reset is never fetched from this table. 34 | // It will always be fetched from 0x3FFFC0 in 35 | // boot ROM 36 | 37 | PINT PIE1_RESERVED; 38 | PINT PIE2_RESERVED; 39 | PINT PIE3_RESERVED; 40 | PINT PIE4_RESERVED; 41 | PINT PIE5_RESERVED; 42 | PINT PIE6_RESERVED; 43 | PINT PIE7_RESERVED; 44 | PINT PIE8_RESERVED; 45 | PINT PIE9_RESERVED; 46 | PINT PIE10_RESERVED; 47 | PINT PIE11_RESERVED; 48 | PINT PIE12_RESERVED; 49 | PINT PIE13_RESERVED; 50 | 51 | // Non-Peripheral Interrupts: 52 | PINT XINT13; // XINT13 / CPU-Timer1 53 | PINT TINT2; // CPU-Timer2 54 | PINT DATALOG; // Datalogging interrupt 55 | PINT RTOSINT; // RTOS interrupt 56 | PINT EMUINT; // Emulation interrupt 57 | PINT XNMI; // Non-maskable interrupt 58 | PINT ILLEGAL; // Illegal operation TRAP 59 | PINT USER1; // User Defined trap 1 60 | PINT USER2; // User Defined trap 2 61 | PINT USER3; // User Defined trap 3 62 | PINT USER4; // User Defined trap 4 63 | PINT USER5; // User Defined trap 5 64 | PINT USER6; // User Defined trap 6 65 | PINT USER7; // User Defined trap 7 66 | PINT USER8; // User Defined trap 8 67 | PINT USER9; // User Defined trap 9 68 | PINT USER10; // User Defined trap 10 69 | PINT USER11; // User Defined trap 11 70 | PINT USER12; // User Defined trap 12 71 | 72 | // Group 1 PIE Peripheral Vectors: 73 | PINT SEQ1INT; 74 | PINT SEQ2INT; 75 | PINT rsvd1_3; 76 | PINT XINT1; 77 | PINT XINT2; 78 | PINT ADCINT; // ADC 79 | PINT TINT0; // Timer 0 80 | PINT WAKEINT; // WD 81 | 82 | // Group 2 PIE Peripheral Vectors: 83 | PINT EPWM1_TZINT; // EPWM-1 84 | PINT EPWM2_TZINT; // EPWM-2 85 | PINT EPWM3_TZINT; // EPWM-3 86 | PINT EPWM4_TZINT; // EPWM-4 87 | PINT EPWM5_TZINT; // EPWM-5 88 | PINT EPWM6_TZINT; // EPWM-6 89 | PINT rsvd2_7; 90 | PINT rsvd2_8; 91 | 92 | // Group 3 PIE Peripheral Vectors: 93 | PINT EPWM1_INT; // EPWM-1 94 | PINT EPWM2_INT; // EPWM-2 95 | PINT EPWM3_INT; // EPWM-3 96 | PINT EPWM4_INT; // EPWM-4 97 | PINT EPWM5_INT; // EPWM-5 98 | PINT EPWM6_INT; // EPWM-6 99 | PINT rsvd3_7; 100 | PINT rsvd3_8; 101 | 102 | // Group 4 PIE Peripheral Vectors: 103 | PINT ECAP1_INT; // ECAP-1 104 | PINT ECAP2_INT; // ECAP-2 105 | PINT ECAP3_INT; // ECAP-3 106 | PINT ECAP4_INT; // ECAP-4 107 | PINT ECAP5_INT; // ECAP-5 108 | PINT ECAP6_INT; // ECAP-6 109 | PINT rsvd4_7; 110 | PINT rsvd4_8; 111 | 112 | // Group 5 PIE Peripheral Vectors: 113 | PINT EQEP1_INT; // EQEP-1 114 | PINT EQEP2_INT; // EQEP-2 115 | PINT rsvd5_3; 116 | PINT rsvd5_4; 117 | PINT rsvd5_5; 118 | PINT rsvd5_6; 119 | PINT rsvd5_7; 120 | PINT rsvd5_8; 121 | 122 | // Group 6 PIE Peripheral Vectors: 123 | PINT SPIRXINTA; // SPI-A 124 | PINT SPITXINTA; // SPI-A 125 | PINT MRINTB; // McBSP-B 126 | PINT MXINTB; // McBSP-B 127 | PINT MRINTA; // McBSP-A 128 | PINT MXINTA; // McBSP-A 129 | PINT rsvd6_7; 130 | PINT rsvd6_8; 131 | 132 | // Group 7 PIE Peripheral Vectors: 133 | PINT DINTCH1; // DMA 134 | PINT DINTCH2; // DMA 135 | PINT DINTCH3; // DMA 136 | PINT DINTCH4; // DMA 137 | PINT DINTCH5; // DMA 138 | PINT DINTCH6; // DMA 139 | PINT rsvd7_7; 140 | PINT rsvd7_8; 141 | 142 | // Group 8 PIE Peripheral Vectors: 143 | PINT I2CINT1A; // I2C-A 144 | PINT I2CINT2A; // I2C-A 145 | PINT rsvd8_3; 146 | PINT rsvd8_4; 147 | PINT SCIRXINTC; // SCI-C 148 | PINT SCITXINTC; // SCI-C 149 | PINT rsvd8_7; 150 | PINT rsvd8_8; 151 | 152 | // Group 9 PIE Peripheral Vectors: 153 | PINT SCIRXINTA; // SCI-A 154 | PINT SCITXINTA; // SCI-A 155 | PINT SCIRXINTB; // SCI-B 156 | PINT SCITXINTB; // SCI-B 157 | PINT ECAN0INTA; // eCAN-A 158 | PINT ECAN1INTA; // eCAN-A 159 | PINT ECAN0INTB; // eCAN-B 160 | PINT ECAN1INTB; // eCAN-B 161 | 162 | // Group 10 PIE Peripheral Vectors: 163 | PINT rsvd10_1; 164 | PINT rsvd10_2; 165 | PINT rsvd10_3; 166 | PINT rsvd10_4; 167 | PINT rsvd10_5; 168 | PINT rsvd10_6; 169 | PINT rsvd10_7; 170 | PINT rsvd10_8; 171 | 172 | // Group 11 PIE Peripheral Vectors: 173 | PINT rsvd11_1; 174 | PINT rsvd11_2; 175 | PINT rsvd11_3; 176 | PINT rsvd11_4; 177 | PINT rsvd11_5; 178 | PINT rsvd11_6; 179 | PINT rsvd11_7; 180 | PINT rsvd11_8; 181 | 182 | // Group 12 PIE Peripheral Vectors: 183 | PINT XINT3; // External interrupt 184 | PINT XINT4; 185 | PINT XINT5; 186 | PINT XINT6; 187 | PINT XINT7; 188 | PINT rsvd12_6; 189 | PINT LVF; // Latched overflow 190 | PINT LUF; // Latched underflow 191 | }; 192 | 193 | //--------------------------------------------------------------------------- 194 | // PIE Interrupt Vector Table External References & Function Declarations: 195 | // 196 | extern struct PIE_VECT_TABLE PieVectTable; 197 | 198 | 199 | #ifdef __cplusplus 200 | } 201 | #endif /* extern "C" */ 202 | 203 | #endif // end of DSP2833x_PIE_VECT_H definition 204 | 205 | //=========================================================================== 206 | // End of file. 207 | //=========================================================================== 208 | 209 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_Spi.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/3 $ 2 | // Checkin $Date: April 17, 2008 11:08:27 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Spi.h 6 | // 7 | // TITLE: DSP2833x Device SPI Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_SPI_H 15 | #define DSP2833x_SPI_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | //--------------------------------------------------------------------------- 24 | // SPI Individual Register Bit Definitions: 25 | // 26 | // SPI FIFO Transmit register bit definitions: 27 | struct SPIFFTX_BITS { // bit description 28 | Uint16 TXFFIL:5; // 4:0 Interrupt level 29 | Uint16 TXFFIENA:1; // 5 Interrupt enable 30 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 31 | Uint16 TXFFINT:1; // 7 INT flag 32 | Uint16 TXFFST:5; // 12:8 FIFO status 33 | Uint16 TXFIFO:1; // 13 FIFO reset 34 | Uint16 SPIFFENA:1; // 14 Enhancement enable 35 | Uint16 SPIRST:1; // 15 Reset SPI 36 | }; 37 | 38 | union SPIFFTX_REG { 39 | Uint16 all; 40 | struct SPIFFTX_BITS bit; 41 | }; 42 | 43 | //-------------------------------------------- 44 | // SPI FIFO recieve register bit definitions: 45 | // 46 | // 47 | struct SPIFFRX_BITS { // bits description 48 | Uint16 RXFFIL:5; // 4:0 Interrupt level 49 | Uint16 RXFFIENA:1; // 5 Interrupt enable 50 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 51 | Uint16 RXFFINT:1; // 7 INT flag 52 | Uint16 RXFFST:5; // 12:8 FIFO status 53 | Uint16 RXFIFORESET:1; // 13 FIFO reset 54 | Uint16 RXFFOVFCLR:1; // 14 Clear overflow 55 | Uint16 RXFFOVF:1; // 15 FIFO overflow 56 | 57 | }; 58 | 59 | union SPIFFRX_REG { 60 | Uint16 all; 61 | struct SPIFFRX_BITS bit; 62 | }; 63 | 64 | //-------------------------------------------- 65 | // SPI FIFO control register bit definitions: 66 | // 67 | // 68 | struct SPIFFCT_BITS { // bits description 69 | Uint16 TXDLY:8; // 7:0 FIFO transmit delay 70 | Uint16 rsvd:8; // 15:8 reserved 71 | }; 72 | 73 | union SPIFFCT_REG { 74 | Uint16 all; 75 | struct SPIFFCT_BITS bit; 76 | }; 77 | 78 | //--------------------------------------------- 79 | // SPI configuration register bit definitions: 80 | // 81 | // 82 | struct SPICCR_BITS { // bits description 83 | Uint16 SPICHAR:4; // 3:0 Character length control 84 | Uint16 SPILBK:1; // 4 Loop-back enable/disable 85 | Uint16 rsvd1:1; // 5 reserved 86 | Uint16 CLKPOLARITY:1; // 6 Clock polarity 87 | Uint16 SPISWRESET:1; // 7 SPI SW Reset 88 | Uint16 rsvd2:8; // 15:8 reserved 89 | }; 90 | 91 | union SPICCR_REG { 92 | Uint16 all; 93 | struct SPICCR_BITS bit; 94 | }; 95 | 96 | //------------------------------------------------- 97 | // SPI operation control register bit definitions: 98 | // 99 | // 100 | struct SPICTL_BITS { // bits description 101 | Uint16 SPIINTENA:1; // 0 Interrupt enable 102 | Uint16 TALK:1; // 1 Master/Slave transmit enable 103 | Uint16 MASTER_SLAVE:1; // 2 Network control mode 104 | Uint16 CLK_PHASE:1; // 3 Clock phase select 105 | Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable 106 | Uint16 rsvd:11; // 15:5 reserved 107 | }; 108 | 109 | union SPICTL_REG { 110 | Uint16 all; 111 | struct SPICTL_BITS bit; 112 | }; 113 | 114 | //-------------------------------------- 115 | // SPI status register bit definitions: 116 | // 117 | // 118 | struct SPISTS_BITS { // bits description 119 | Uint16 rsvd1:5; // 4:0 reserved 120 | Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag 121 | Uint16 INT_FLAG:1; // 6 SPI interrupt flag 122 | Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag 123 | Uint16 rsvd2:8; // 15:8 reserved 124 | }; 125 | 126 | union SPISTS_REG { 127 | Uint16 all; 128 | struct SPISTS_BITS bit; 129 | }; 130 | 131 | //------------------------------------------------ 132 | // SPI priority control register bit definitions: 133 | // 134 | // 135 | struct SPIPRI_BITS { // bits description 136 | Uint16 rsvd1:4; // 3:0 reserved 137 | Uint16 FREE:1; // 4 Free emulation mode control 138 | Uint16 SOFT:1; // 5 Soft emulation mode control 139 | Uint16 rsvd2:1; // 6 reserved 140 | Uint16 rsvd3:9; // 15:7 reserved 141 | }; 142 | 143 | union SPIPRI_REG { 144 | Uint16 all; 145 | struct SPIPRI_BITS bit; 146 | }; 147 | 148 | //--------------------------------------------------------------------------- 149 | // SPI Register File: 150 | // 151 | struct SPI_REGS { 152 | union SPICCR_REG SPICCR; // Configuration register 153 | union SPICTL_REG SPICTL; // Operation control register 154 | union SPISTS_REG SPISTS; // Status register 155 | Uint16 rsvd1; // reserved 156 | Uint16 SPIBRR; // Baud Rate 157 | Uint16 rsvd2; // reserved 158 | Uint16 SPIRXEMU; // Emulation buffer 159 | Uint16 SPIRXBUF; // Serial input buffer 160 | Uint16 SPITXBUF; // Serial output buffer 161 | Uint16 SPIDAT; // Serial data 162 | union SPIFFTX_REG SPIFFTX; // FIFO transmit register 163 | union SPIFFRX_REG SPIFFRX; // FIFO recieve register 164 | union SPIFFCT_REG SPIFFCT; // FIFO control register 165 | Uint16 rsvd3[2]; // reserved 166 | union SPIPRI_REG SPIPRI; // FIFO Priority control 167 | }; 168 | 169 | //--------------------------------------------------------------------------- 170 | // SPI External References & Function Declarations: 171 | // 172 | extern volatile struct SPI_REGS SpiaRegs; 173 | 174 | #ifdef __cplusplus 175 | } 176 | #endif /* extern "C" */ 177 | 178 | #endif // end of DSP2833x_SPI_H definition 179 | 180 | //=========================================================================== 181 | // End of file. 182 | //=========================================================================== 183 | 184 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_XIntrupt.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:52:39 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_XIntrupt.h 6 | // 7 | // TITLE: DSP2833x Device External Interrupt Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_XINTRUPT_H 15 | #define DSP2833x_XINTRUPT_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | 24 | struct XINTCR_BITS { 25 | Uint16 ENABLE:1; // 0 enable/disable 26 | Uint16 rsvd1:1; // 1 reserved 27 | Uint16 POLARITY:2; // 3:2 pos/neg, both triggered 28 | Uint16 rsvd2:12; //15:4 reserved 29 | }; 30 | 31 | union XINTCR_REG { 32 | Uint16 all; 33 | struct XINTCR_BITS bit; 34 | }; 35 | 36 | struct XNMICR_BITS { 37 | Uint16 ENABLE:1; // 0 enable/disable 38 | Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 39 | Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered 40 | Uint16 rsvd2:12; // 15:4 reserved 41 | }; 42 | 43 | union XNMICR_REG { 44 | Uint16 all; 45 | struct XNMICR_BITS bit; 46 | }; 47 | 48 | 49 | 50 | 51 | //--------------------------------------------------------------------------- 52 | // External Interrupt Register File: 53 | // 54 | struct XINTRUPT_REGS { 55 | union XINTCR_REG XINT1CR; 56 | union XINTCR_REG XINT2CR; 57 | union XINTCR_REG XINT3CR; 58 | union XINTCR_REG XINT4CR; 59 | union XINTCR_REG XINT5CR; 60 | union XINTCR_REG XINT6CR; 61 | union XINTCR_REG XINT7CR; 62 | union XNMICR_REG XNMICR; 63 | Uint16 XINT1CTR; 64 | Uint16 XINT2CTR; 65 | Uint16 rsvd[5]; 66 | Uint16 XNMICTR; 67 | }; 68 | 69 | //--------------------------------------------------------------------------- 70 | // External Interrupt References & Function Declarations: 71 | // 72 | extern volatile struct XINTRUPT_REGS XIntruptRegs; 73 | 74 | #ifdef __cplusplus 75 | } 76 | #endif /* extern "C" */ 77 | 78 | #endif // end of DSP2833x_XINTF_H definition 79 | 80 | //=========================================================================== 81 | // End of file. 82 | //=========================================================================== 83 | 84 | -------------------------------------------------------------------------------- /contrib/DSP2833x/DSP2833x_headers/include/DSP2833x_Xintf.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: July 27, 2009 13:57:25 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Xintf.h 6 | // 7 | // TITLE: DSP2833x Device External Interface Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 11 | // $Release Date: August 4, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_XINTF_H 15 | #define DSP2833x_XINTF_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | // XINTF timing register bit definitions: 24 | struct XTIMING_BITS { // bits description 25 | Uint16 XWRTRAIL:2; // 1:0 Write access trail timing 26 | Uint16 XWRACTIVE:3; // 4:2 Write access active timing 27 | Uint16 XWRLEAD:2; // 6:5 Write access lead timing 28 | Uint16 XRDTRAIL:2; // 8:7 Read access trail timing 29 | Uint16 XRDACTIVE:3; // 11:9 Read access active timing 30 | Uint16 XRDLEAD:2; // 13:12 Read access lead timing 31 | Uint16 USEREADY:1; // 14 Extend access using HW waitstates 32 | Uint16 READYMODE:1; // 15 Ready mode 33 | Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b 34 | Uint16 rsvd1:4; // 21:18 reserved 35 | Uint16 X2TIMING:1; // 22 Double lead/active/trail timing 36 | Uint16 rsvd3:9; // 31:23 reserved 37 | }; 38 | 39 | union XTIMING_REG { 40 | Uint32 all; 41 | struct XTIMING_BITS bit; 42 | }; 43 | 44 | // XINTF control register bit definitions: 45 | struct XINTCNF2_BITS { // bits description 46 | Uint16 WRBUFF:2; // 1:0 Write buffer depth 47 | Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK 48 | Uint16 CLKOFF:1; // 3 Disable XCLKOUT 49 | Uint16 rsvd1:2; // 5:4 reserved 50 | Uint16 WLEVEL:2; // 7:6 Current level of the write buffer 51 | Uint16 rsvd2:1; // 8 reserved 52 | Uint16 HOLD:1; // 9 Hold enable/disable 53 | Uint16 HOLDS:1; // 10 Current state of HOLDn input 54 | Uint16 HOLDAS:1; // 11 Current state of HOLDAn output 55 | Uint16 rsvd3:4; // 15:12 reserved 56 | Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK 57 | Uint16 rsvd4:13; // 31:19 reserved 58 | }; 59 | 60 | union XINTCNF2_REG { 61 | Uint32 all; 62 | struct XINTCNF2_BITS bit; 63 | }; 64 | 65 | // XINTF bank switching register bit definitions: 66 | struct XBANK_BITS { // bits description 67 | Uint16 BANK:3; // 2:0 Zone for which banking is enabled 68 | Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add 69 | Uint16 rsvd:10; // 15:6 reserved 70 | }; 71 | 72 | union XBANK_REG { 73 | Uint16 all; 74 | struct XBANK_BITS bit; 75 | }; 76 | 77 | struct XRESET_BITS { 78 | Uint16 XHARDRESET:1; 79 | Uint16 rsvd1:15; 80 | }; 81 | 82 | union XRESET_REG { 83 | Uint16 all; 84 | struct XRESET_BITS bit; 85 | }; 86 | 87 | 88 | //--------------------------------------------------------------------------- 89 | // XINTF Register File: 90 | // 91 | struct XINTF_REGS { 92 | union XTIMING_REG XTIMING0; 93 | Uint32 rsvd1[5]; 94 | union XTIMING_REG XTIMING6; 95 | union XTIMING_REG XTIMING7; 96 | Uint32 rsvd2[2]; 97 | union XINTCNF2_REG XINTCNF2; 98 | Uint32 rsvd3; 99 | union XBANK_REG XBANK; 100 | Uint16 rsvd4; 101 | Uint16 XREVISION; 102 | Uint16 rsvd5[2]; 103 | union XRESET_REG XRESET; 104 | }; 105 | 106 | //--------------------------------------------------------------------------- 107 | // XINTF External References & Function Declarations: 108 | // 109 | extern volatile struct XINTF_REGS XintfRegs; 110 | 111 | 112 | #ifdef __cplusplus 113 | } 114 | #endif /* extern "C" */ 115 | 116 | #endif // end of DSP2833x_XINTF_H definition 117 | 118 | //=========================================================================== 119 | // No more. 120 | //=========================================================================== 121 | -------------------------------------------------------------------------------- /contrib/dspProfiling/Profiling.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Profiling.c 3 | * 4 | * Created on: 24/09/2014 5 | * Author: bds 6 | */ 7 | #include "Profiling.h" 8 | #include "DSP2833x_Device.h" 9 | #include "DSP2833x_CpuTimers.h" 10 | 11 | unsigned long long profiling_getElapsedCycles(ProfilingTool * self) { 12 | unsigned long endTimeLow, endTimeHigh; 13 | long long result; 14 | 15 | endTimeHigh = CpuTimer2Regs.TIM.half.LSW; 16 | endTimeLow = CpuTimer2Regs.TIM.half.MSW; 17 | 18 | result = ( (self->startTimeHigh - endTimeHigh) + self->startTimeHigh*(self->startTimeLow - endTimeLow) ); 19 | 20 | return result; 21 | } 22 | 23 | void profiling_start(ProfilingTool * self) { 24 | // Save the start values from TIM register 25 | // It will be used to calculate the elapsed cycles at getElapsedCycles() 26 | self->startTimeHigh = CpuTimer2Regs.TIM.half.LSW; 27 | self->startTimeLow = CpuTimer2Regs.TIM.half.MSW; 28 | 29 | // Start Debug Timer 30 | CpuTimer2Regs.TCR.bit.TSS = 0; 31 | } 32 | 33 | void profiling_registerStep(ProfilingTool * self, unsigned short stepIdx) { 34 | // Stop timer 35 | CpuTimer2Regs.TCR.bit.TSS = 1; 36 | 37 | // Regiser cycle count 38 | self->cycleMeasuresSteps[self->timeMeasuresIndex][stepIdx] = self->getElapsedCycles(self); 39 | 40 | // Reset timer 41 | CpuTimer2Regs.TCR.bit.TRB = 1; 42 | 43 | // Restart timer 44 | CpuTimer2Regs.TCR.bit.TSS = 0; 45 | } 46 | 47 | void profiling_stop(ProfilingTool * self) { 48 | unsigned short idx, stepIdx; 49 | 50 | // Stop Debug Timer 51 | CpuTimer2Regs.TCR.bit.TSS = 1; 52 | 53 | // Reset timer 54 | CpuTimer2Regs.TCR.bit.TRB = 1; 55 | 56 | // Convert STEP cycles to uSeconds and register total utilized time & cycles 57 | #if PROFILING_EXTRA_CALCS 58 | for(idx = 0; idx < PROFILING_SIZE_TIME_MEASURES; idx++){ 59 | for(stepIdx = 0; stepIdx < PROFILING_SIZE_MAX_STEPS; stepIdx++){ 60 | self->timeMeasuresSteps[idx][stepIdx] = (self->cycleMeasuresSteps[idx][stepIdx] / PROFILING_DSPCLOCK); 61 | } 62 | } 63 | #endif 64 | 65 | // Reset timeMeasuresIndex 66 | if (self->timeMeasuresIndex >= PROFILING_SIZE_TIME_MEASURES){ 67 | self->timeMeasuresIndex = 0; 68 | 69 | // Break the code to show the results (if PROFILING_BREAK_MAX_MEASURES is set) 70 | if(PROFILING_BREAK_MAX_MEASURES) ESTOP0; 71 | } else { 72 | self->timeMeasuresIndex++; 73 | } 74 | } 75 | 76 | ProfilingTool construct_ProfilingTool(){ 77 | ProfilingTool profiling; 78 | unsigned short idx, stepIdx; 79 | 80 | profiling.startTimeHigh = 0; 81 | profiling.startTimeLow = 0; 82 | 83 | profiling.timeMeasuresIndex = 0; 84 | 85 | profiling.start = profiling_start; 86 | profiling.registerStep = profiling_registerStep; 87 | profiling.stop = profiling_stop; 88 | profiling.getElapsedCycles = profiling_getElapsedCycles; 89 | 90 | // Reset timeMeasures arrays 91 | for(idx = 0; idx < PROFILING_SIZE_TIME_MEASURES; idx++){ 92 | for(stepIdx = 0; stepIdx < PROFILING_SIZE_MAX_STEPS; stepIdx++) { 93 | profiling.timeMeasuresSteps[idx][stepIdx] = 0; 94 | profiling.cycleMeasuresSteps[idx][stepIdx] = 0; 95 | } 96 | } 97 | 98 | // Init CPU Timer 2 99 | // Initialize address pointers to respective timer registers: 100 | CpuTimer2.RegsAddr = &CpuTimer2Regs; 101 | // Initialize timer period to maximum: 102 | CpuTimer2Regs.PRD.all = 0xFFFFFFFF; 103 | // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): 104 | CpuTimer2Regs.TPR.all = 0; 105 | CpuTimer2Regs.TPRH.all = 0; 106 | // Make sure timer is stopped: 107 | CpuTimer2Regs.TCR.bit.TSS = 1; 108 | // Reload all counter register with period value: 109 | CpuTimer2Regs.TCR.bit.TRB = 1; 110 | // Reset interrupt counters: 111 | CpuTimer2.InterruptCount = 0; 112 | 113 | ConfigCpuTimer(&CpuTimer2, PROFILING_DSPCLOCK, 1000000); 114 | CpuTimer2Regs.TCR.bit.TRB = 1; 115 | 116 | return profiling; 117 | } 118 | -------------------------------------------------------------------------------- /contrib/dspProfiling/Profiling.h: -------------------------------------------------------------------------------- 1 | #ifndef PROFILING_H_ 2 | #define PROFILING_H_ 3 | 4 | #define PROFILING_SIZE_TIME_MEASURES 5 5 | #define PROFILING_SIZE_MAX_STEPS 5 6 | #define PROFILING_DSPCLOCK 150U // 150 Mhz 7 | #define PROFILING_EXTRA_CALCS 1 // true 8 | #define PROFILING_BREAK_MAX_MEASURES 1 // true 9 | 10 | typedef struct ProfilingTool ProfilingTool; 11 | 12 | struct ProfilingTool { 13 | unsigned long long cycleMeasuresSteps[PROFILING_SIZE_TIME_MEASURES][PROFILING_SIZE_MAX_STEPS]; 14 | long double timeMeasuresSteps[PROFILING_SIZE_TIME_MEASURES][PROFILING_SIZE_MAX_STEPS]; 15 | 16 | unsigned long startTimeHigh; 17 | unsigned long startTimeLow; 18 | 19 | unsigned int timeMeasuresIndex; 20 | 21 | void (*start)(ProfilingTool * self); 22 | void (*registerStep)(ProfilingTool * self, unsigned short idx); 23 | void (*stop)(ProfilingTool * self); 24 | unsigned long long (*getElapsedCycles)(ProfilingTool * self); 25 | }; 26 | 27 | inline unsigned long long profiling_getElapsedCycles(ProfilingTool * self); 28 | inline void profiling_start(ProfilingTool * self); 29 | inline void profiling_stop(ProfilingTool * self); 30 | inline void profiling_registerStep(ProfilingTool * self, unsigned short idx); 31 | ProfilingTool construct_ProfilingTool(); 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /contrib/modbus/Crc.c: -------------------------------------------------------------------------------- 1 | #include "Crc.h" 2 | 3 | unsigned int generateCrc(unsigned int * buf, int len, bool swap) 4 | { 5 | unsigned int crc = 0xFFFF; 6 | unsigned int temp = 0; 7 | int pos = 0; 8 | int i = 0; 9 | 10 | for (pos = 0; pos < len; pos++) { 11 | // XOR byte into least sig. byte of crc 12 | crc ^= (unsigned int) buf[pos]; 13 | 14 | // Loop over each bit 15 | for (i = 8; i != 0; i--) { 16 | 17 | // If the LSB is set 18 | if ((crc & 0x0001) != 0) { 19 | crc >>= 1; // Shift right and XOR 0xA001 20 | crc ^= 0xA001; 21 | } 22 | else 23 | crc >>= 1; // Just shift right 24 | } 25 | } 26 | 27 | // Swype bytes 28 | if(swap == true) { 29 | temp = crc; 30 | crc = (crc & 0xFF00) >> 8; 31 | crc = ( (temp & 0x00FF) << 8 ) | crc; 32 | } 33 | 34 | return crc; 35 | } 36 | -------------------------------------------------------------------------------- /contrib/modbus/ModbusData.c: -------------------------------------------------------------------------------- 1 | #include "ModbusDefinitions.h" 2 | #include "ModbusData.h" 3 | #include "Log.h" 4 | 5 | // Clears all data of Modbus Data 6 | void data_clear(ModbusData *self){ 7 | MB_DATA_RESPONSE_DEBUG(); 8 | self->slaveAddress = 0; 9 | self->functionCode = 0; 10 | self->size = 0; 11 | self->contentIdx = 0; 12 | self->crc = 0; 13 | } 14 | 15 | // Return a string with the data that will be transmited 16 | // Mostly used for the last step of process: MB_TRANSMIT (serial TX) 17 | Uint16 * data_getTransmitString(ModbusData *self){ 18 | static Uint16 string[MB_BUFFER_SIZE] = {0}; 19 | Uint16 stringIndex = 0; 20 | Uint16 contentIterator; 21 | 22 | string[stringIndex++] = self->slaveAddress; 23 | string[stringIndex++] = self->functionCode; 24 | 25 | // Loop throught the "general content" part of data frame 26 | for(contentIterator = 0; contentIterator < (self->size - MB_SIZE_COMMON_DATA); contentIterator++){ 27 | string[stringIndex++] = (self->content[contentIterator]) & 0x00FF; 28 | } 29 | 30 | string[stringIndex++] = (self->crc & 0xFF00) >> 8; 31 | string[stringIndex++] = self->crc & 0x00FF; 32 | 33 | MB_DATA_RESPONSE_DEBUG(); 34 | return string; 35 | } 36 | 37 | // Return a string with the data that will be transmited (but without CRC) 38 | // Mostly used to create the CRC (get this string and the size of it and then generate the CRC) 39 | Uint16 * data_getTransmitStringWithoutCRC(ModbusData *self){ 40 | static Uint16 string[MB_BUFFER_SIZE] = {0}; 41 | Uint16 stringIndex = 0; 42 | Uint16 contentIterator; 43 | 44 | string[stringIndex++] = self->slaveAddress; 45 | string[stringIndex++] = self->functionCode; 46 | 47 | // Loop throught the "general content" part of data frame 48 | for(contentIterator = 0; contentIterator < (self->size - MB_SIZE_COMMON_DATA); contentIterator++){ 49 | string[stringIndex++] = (self->content[contentIterator]); 50 | } 51 | 52 | MB_DATA_RESPONSE_DEBUG(); 53 | return string; 54 | } 55 | 56 | ModbusData construct_ModbusData(){ 57 | ModbusData modbusData; 58 | 59 | modbusData.slaveAddress = 0; 60 | modbusData.functionCode = 0; 61 | modbusData.contentIdx = 0; 62 | modbusData.crc = 0; 63 | modbusData.size = 0; 64 | 65 | modbusData.clear = data_clear; 66 | modbusData.getTransmitString = data_getTransmitString; 67 | modbusData.getTransmitStringWithoutCRC = data_getTransmitStringWithoutCRC; 68 | 69 | MB_DATA_RESPONSE_DEBUG(); 70 | 71 | return modbusData; 72 | } 73 | -------------------------------------------------------------------------------- /contrib/modbus/ModbusDataMap.c: -------------------------------------------------------------------------------- 1 | /* 2 | * ModbusVarMap.c 3 | * 4 | * Created on: 08/10/2014 5 | * Author: bds 6 | */ 7 | 8 | #include "ModbusSettings.h" 9 | #include MB_DATA_MAP 10 | #include "Log.h" 11 | 12 | #if MB_COILS_ENABLED 13 | ModbusCoilsMap construct_ModbusCoilsMap(){ 14 | ModbusCoilsMap coilsMap = {0}; 15 | return coilsMap; 16 | } 17 | #endif 18 | 19 | #if MB_INPUTS_ENABLED 20 | ModbusInputsMap construct_ModbusInputsMap(){ 21 | ModbusInputsMap inputsMap = {0}; 22 | return inputsMap; 23 | } 24 | #endif 25 | 26 | #if MB_INPUT_REGISTERS_ENABLED 27 | ModbusInputRegistersMap construct_ModbusInputRegistersMap(){ 28 | ModbusInputRegistersMap registersMap = {0}; 29 | return registersMap; 30 | } 31 | #endif 32 | 33 | #if MB_HOLDING_REGISTERS_ENABLED 34 | ModbusHoldingRegistersMap construct_ModbusHoldingRegistersMap(){ 35 | ModbusHoldingRegistersMap registersMap = {0}; 36 | return registersMap; 37 | } 38 | #endif 39 | -------------------------------------------------------------------------------- /contrib/modbus/include/Crc.h: -------------------------------------------------------------------------------- 1 | #ifndef CRC_UTIL_H_ 2 | #define CRC_UTIL_H_ 3 | 4 | #ifndef bool 5 | #define false 0 6 | #define true 1 7 | #define bool char 8 | #endif 9 | 10 | unsigned int generateCrc(unsigned int * buf, int len, bool swap); 11 | 12 | #endif /* CRC_UTIL_H_ */ 13 | 14 | -------------------------------------------------------------------------------- /contrib/modbus/include/DataTypes.h: -------------------------------------------------------------------------------- 1 | /* 2 | * DataTypes.h 3 | * 4 | * Created on: 29/10/2014 5 | * Author: bds 6 | */ 7 | 8 | #ifndef DATATYPES_H_ 9 | #define DATATYPES_H_ 10 | 11 | #ifndef bool 12 | #define false 0 13 | #define true 1 14 | #define bool unsigned int 15 | #endif 16 | 17 | #ifndef DSP28_DATA_TYPES 18 | #define DSP28_DATA_TYPES 19 | typedef int int16; 20 | typedef long int32; 21 | typedef long long int64; 22 | typedef unsigned int Uint16; 23 | typedef unsigned long Uint32; 24 | typedef unsigned long long Uint64; 25 | typedef float float32; 26 | typedef long double float64; 27 | #endif 28 | 29 | typedef short int8; 30 | typedef unsigned short Uint8; 31 | 32 | #endif /* DATATYPES_H_ */ 33 | -------------------------------------------------------------------------------- /contrib/modbus/include/Log.h: -------------------------------------------------------------------------------- 1 | #ifndef CRC_H_ 2 | #define CRC_H_ 3 | 4 | #include "ModbusSettings.h" 5 | 6 | // Log tool ============================= 7 | // When called it displays a message at console using Variadic feature 8 | // To disable it set DEBUG_LOG_ENABLED = 0 at Modbus.h 9 | #if DEBUG_LOG_ENABLED 10 | #include "stdio.h" 11 | #define SMART_DEBUG(fmt, ...) \ 12 | do { fprintf(stderr, "%s():%d called! " fmt "\n", __FUNCTION__, \ 13 | __LINE__); } \ 14 | while (0) 15 | // Original expression (found at web but don't work in some cases) 16 | //do { fprintf(stderr, "%s:%d:%s() ## " fmt "\n", __FILE__, \ 17 | // __LINE__, __FUNCTION__, __VA_ARGS__); } while (0) 18 | #else 19 | #define SMART_DEBUG(nonVariadicVar) 20 | #endif 21 | 22 | 23 | // Different logs ======================= 24 | // Each file has it's specific Log debug. If you want to enable only some 25 | // logs, go to Modbus.h and modify the macros XXXXX_DEBUG_ENABLED 26 | 27 | #if MB_DATA_REQUEST_DEBUG_ENABLED && DEBUG_LOG_ENABLED 28 | #define MB_DATA_REQUEST_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 29 | #else 30 | #define MB_DATA_REQUEST_DEBUG(nonVariadicVar) 31 | #endif 32 | 33 | #if MB_DATA_RESPONSE_DEBUG_ENABLED && DEBUG_LOG_ENABLED 34 | #define MB_DATA_RESPONSE_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 35 | #else 36 | #define MB_DATA_RESPONSE_DEBUG(nonVariadicVar) 37 | #endif 38 | 39 | #if MB_DATA_HANDLER_DEBUG_ENABLED && DEBUG_LOG_ENABLED 40 | #define MB_DATA_HANDLER_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 41 | #else 42 | #define MB_DATA_HANDLER_DEBUG(nonVariadicVar) 43 | #endif 44 | 45 | #if SERIAL_DEBUG_ENABLED && DEBUG_LOG_ENABLED 46 | #define SERIAL_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 47 | #else 48 | #define SERIAL_DEBUG(nonVariadicVar) 49 | #endif 50 | 51 | #if MB_MASTER_DEBUG_ENABLED && DEBUG_LOG_ENABLED 52 | #define MB_MASTER_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 53 | #else 54 | #define MB_MASTER_DEBUG(nonVariadicVar) 55 | #endif 56 | 57 | #if MB_SLAVE_DEBUG_ENABLED && DEBUG_LOG_ENABLED 58 | #define MB_SLAVE_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 59 | #else 60 | #define MB_SLAVE_DEBUG(nonVariadicVar) 61 | #endif 62 | 63 | #if MB_VAR_MAP_DEBUG && DEBUG_LOG_ENABLED 64 | #define MB_VAR_MAP_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 65 | #else 66 | #define MB_VAR_MAP_DEBUG(nonVariadicVar) 67 | #endif 68 | 69 | #if TIMER_DEBUG_ENABLED && DEBUG_LOG_ENABLED 70 | #define TIMER_DEBUG(fmt, ...) SMART_DEBUG(fmt, __VA_ARGS__) 71 | #else 72 | #define TIMER_DEBUG(nonVariadicVar) 73 | #endif 74 | 75 | #endif /* CRC_H_ */ 76 | -------------------------------------------------------------------------------- /contrib/modbus/include/ModbusData.h: -------------------------------------------------------------------------------- 1 | #ifndef MODBUS_DATA_RESPONSE_H_ 2 | #define MODBUS_DATA_RESPONSE_H_ 3 | 4 | #include "ModbusSettings.h" 5 | 6 | typedef struct ModbusData ModbusData; 7 | 8 | struct ModbusData { 9 | Uint16 slaveAddress; 10 | Uint16 functionCode; 11 | Uint16 contentIdx; 12 | Uint16 content[MB_BUFFER_SIZE]; 13 | Uint16 size; 14 | Uint16 crc; 15 | 16 | void (*clear)(ModbusData *self); 17 | Uint16 * (*getTransmitString)(ModbusData *self); 18 | Uint16 * (*getTransmitStringWithoutCRC)(ModbusData *self); 19 | }; 20 | 21 | inline void data_clear(ModbusData *self); 22 | inline Uint16 * data_getTransmitString(ModbusData *self); 23 | inline Uint16 * data_getTransmitStringWithoutCRC(ModbusData *self); 24 | ModbusData construct_ModbusData(); 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /contrib/modbus/include/ModbusDataHandler.h: -------------------------------------------------------------------------------- 1 | #ifndef MODBUS_IO_H_ 2 | #define MODBUS_IO_H_ 3 | 4 | #include "ModbusDefinitions.h" 5 | #include "ModbusSettings.h" 6 | #include MB_DATA_MAP 7 | 8 | typedef struct ModbusDataHandler ModbusDataHandler; 9 | typedef struct ModbusSlave ModbusSlave; 10 | 11 | struct ModbusDataHandler { 12 | void (*readDigitalData)(ModbusSlave *slave, ModbusFunctionCode funcCode); 13 | void (*readAnalogData)(ModbusSlave *slave, ModbusFunctionCode funcCode); 14 | 15 | void (*presetSingleRegister)(ModbusSlave *slave); 16 | void (*forceSingleCoil)(ModbusSlave *slave); 17 | void (*presetMultipleRegisters)(ModbusSlave *slave); 18 | void (*forceMultipleCoils)(ModbusSlave *slave); 19 | 20 | bool (*checkException)(ModbusSlave *slave, Uint16 firstAddr, Uint16 totalData, Uint16 sizeOfMap); 21 | void (*exception)(ModbusSlave *slave, ModbusError exceptionCode); 22 | }; 23 | 24 | inline void datahandler_readDigitalData(ModbusSlave *slave, ModbusFunctionCode funcCode); 25 | inline void datahandler_readAnalogData(ModbusSlave *slave, ModbusFunctionCode funcCode); 26 | inline void datahandler_presetSingleRegister(ModbusSlave *slave); 27 | inline void datahandler_forceSingleCoil(ModbusSlave *slave); 28 | inline void datahandler_presetMultipleRegisters(ModbusSlave *slave); 29 | inline void datahandler_forceMultipleCoils(ModbusSlave *slave); 30 | inline bool datahandler_checkException(ModbusSlave *slave, Uint16 firstAddr, Uint16 totalData, Uint16 sizeOfMap); 31 | inline void datahandler_exception(ModbusSlave *slave, ModbusError exceptionCode); 32 | ModbusDataHandler construct_ModbusDataHandler(); 33 | 34 | #endif 35 | -------------------------------------------------------------------------------- /contrib/modbus/include/ModbusDataMap.h: -------------------------------------------------------------------------------- 1 | /* 2 | * ModbusVarMap.h 3 | * 4 | * Created on: 08/10/2014 5 | * Author: bds 6 | */ 7 | 8 | #ifndef MODBUSVARMAP_H_ 9 | #define MODBUSVARMAP_H_ 10 | 11 | #include "ModbusSettings.h" 12 | 13 | #if MB_COILS_ENABLED 14 | typedef struct ModbusCoilsMap ModbusCoilsMap; 15 | struct ModbusCoilsMap{ 16 | Uint8 dummy0; 17 | Uint8 dummy1; 18 | Uint8 dummy2; 19 | Uint8 dummy3; 20 | Uint8 dummy4; 21 | Uint8 dummy5; 22 | Uint8 dummy6; 23 | Uint8 dummy7; 24 | Uint8 dummy8; 25 | Uint8 dummy9; 26 | Uint8 dummy10; 27 | Uint8 dummy11; 28 | Uint8 dummy12; 29 | Uint8 dummy13; 30 | Uint8 dummy14; 31 | Uint8 dummy15; 32 | Uint8 dummy16; 33 | Uint8 dummy17; 34 | Uint8 dummy18; 35 | }; 36 | 37 | ModbusCoilsMap construct_ModbusCoilsMap(); 38 | #endif 39 | 40 | #if MB_INPUTS_ENABLED 41 | typedef struct ModbusInputsMap ModbusInputsMap; 42 | struct ModbusInputsMap{ 43 | Uint8 dummy0; 44 | Uint8 dummy1; 45 | Uint8 dummy2; 46 | Uint8 dummy3; 47 | Uint8 dummy4; 48 | Uint8 dummy5; 49 | Uint8 dummy6; 50 | Uint8 dummy7; 51 | Uint8 dummy8; 52 | Uint8 dummy9; 53 | Uint8 dummy10; 54 | Uint8 dummy11; 55 | Uint8 dummy12; 56 | Uint8 dummy13; 57 | Uint8 dummy14; 58 | Uint8 dummy15; 59 | Uint8 dummy16; 60 | Uint8 dummy17; 61 | Uint8 dummy18; 62 | }; 63 | 64 | ModbusInputsMap construct_ModbusInputsMap(); 65 | #endif 66 | 67 | #if MB_HOLDING_REGISTERS_ENABLED 68 | typedef struct ModbusHoldingRegistersMap ModbusHoldingRegistersMap; 69 | struct ModbusHoldingRegistersMap { 70 | float32 dummy0; 71 | float32 dummy1; 72 | float32 dummy2; 73 | float32 dummy3; 74 | float32 dummy4; 75 | }; 76 | 77 | ModbusHoldingRegistersMap construct_ModbusHoldingRegistersMap(); 78 | #endif 79 | 80 | #if MB_INPUT_REGISTERS_ENABLED 81 | typedef struct ModbusInputRegistersMap ModbusInputRegistersMap; 82 | struct ModbusInputRegistersMap { 83 | float32 dummy0; 84 | float32 dummy1; 85 | float32 dummy2; 86 | float32 dummy3; 87 | float32 dummy4; 88 | }; 89 | 90 | ModbusInputRegistersMap construct_ModbusInputRegistersMap(); 91 | #endif 92 | 93 | #endif /* MODBUSVARMAP_H_ */ 94 | -------------------------------------------------------------------------------- /contrib/modbus/include/ModbusDataMapTests.h: -------------------------------------------------------------------------------- 1 | /* 2 | * ModbusVarMap.h 3 | * 4 | * Created on: 08/10/2014 5 | * Author: bds 6 | */ 7 | 8 | #ifndef MODBUSVARMAP_H_ 9 | #define MODBUSVARMAP_H_ 10 | 11 | #include "ModbusSettings.h" 12 | 13 | #if MB_COILS_ENABLED 14 | typedef struct ModbusCoilsMap ModbusCoilsMap; 15 | struct ModbusCoilsMap{ 16 | Uint8 dummy1; 17 | Uint8 dummy2; 18 | Uint8 dummy3; 19 | Uint8 dummy4; 20 | Uint8 dummy5; 21 | Uint8 dummy6; 22 | Uint8 dummy7; 23 | Uint8 dummy8; 24 | Uint8 dummy9; 25 | Uint8 dummy10; 26 | Uint8 dummy11; 27 | Uint8 dummy12; 28 | Uint8 dummy13; 29 | Uint8 dummy14; 30 | Uint8 dummy15; 31 | Uint8 dummy16; 32 | Uint8 dummy17; 33 | Uint8 dummy18; 34 | Uint8 dummy19; 35 | Uint8 dummy20; 36 | Uint8 dummy21; 37 | Uint8 dummy22; 38 | Uint8 dummy23; 39 | Uint8 dummy24; 40 | Uint8 dummy25; 41 | Uint8 dummy26; 42 | Uint8 dummy27; 43 | Uint8 dummy28; 44 | Uint8 dummy29; 45 | Uint8 dummy30; 46 | Uint8 dummy31; 47 | Uint8 dummy32; 48 | Uint8 dummy33; 49 | Uint8 dummy34; 50 | Uint8 dummy35; 51 | Uint8 dummy36; 52 | Uint8 dummy37; 53 | Uint8 dummy38; 54 | Uint8 dummy39; 55 | Uint8 dummy40; 56 | Uint8 dummy41; 57 | }; 58 | 59 | ModbusCoilsMap construct_ModbusCoilsMap(); 60 | #endif 61 | 62 | #if MB_INPUTS_ENABLED 63 | typedef struct ModbusInputsMap ModbusInputsMap; 64 | struct ModbusInputsMap{ 65 | Uint8 dummy1; 66 | Uint8 dummy2; 67 | Uint8 dummy3; 68 | Uint8 dummy4; 69 | Uint8 dummy5; 70 | Uint8 dummy6; 71 | Uint8 dummy7; 72 | Uint8 dummy8; 73 | Uint8 dummy9; 74 | Uint8 dummy10; 75 | Uint8 dummy11; 76 | Uint8 dummy12; 77 | Uint8 dummy13; 78 | Uint8 dummy14; 79 | Uint8 dummy15; 80 | Uint8 dummy16; 81 | Uint8 dummy17; 82 | Uint8 dummy18; 83 | Uint8 dummy19; 84 | Uint8 dummy20; 85 | Uint8 dummy21; 86 | Uint8 dummy22; 87 | Uint8 dummy23; 88 | Uint8 dummy24; 89 | Uint8 dummy25; 90 | Uint8 dummy26; 91 | Uint8 dummy27; 92 | Uint8 dummy28; 93 | Uint8 dummy29; 94 | }; 95 | 96 | ModbusInputsMap construct_ModbusInputsMap(); 97 | #endif 98 | 99 | #if MB_HOLDING_REGISTERS_ENABLED 100 | typedef struct ModbusHoldingRegistersMap ModbusHoldingRegistersMap; 101 | struct ModbusHoldingRegistersMap { 102 | Uint16 dummy1; 103 | Uint16 dummy2; 104 | Uint16 dummy3; 105 | Uint16 dummy4; 106 | Uint16 dummy5; 107 | Uint16 dummy6; 108 | Uint16 dummy7; 109 | Uint16 dummy8; 110 | Uint16 dummy9; 111 | Uint16 dummy10; 112 | Uint16 dummy11; 113 | Uint16 dummy12; 114 | Uint16 dummy13; 115 | Uint16 dummy14; 116 | Uint16 dummy15; 117 | Uint16 dummy16; 118 | Uint16 dummy17; 119 | Uint16 dummy18; 120 | Uint16 dummy19; 121 | Uint16 dummy20; 122 | Uint16 dummy21; 123 | Uint16 dummy22; 124 | Uint16 dummy23; 125 | Uint16 dummy24; 126 | Uint16 dummy25; 127 | Uint16 dummy26; 128 | Uint16 dummy27; 129 | Uint16 dummy28; 130 | // Uint16 dummy29; 131 | }; 132 | 133 | ModbusHoldingRegistersMap construct_ModbusHoldingRegistersMap(); 134 | #endif 135 | 136 | #if MB_INPUT_REGISTERS_ENABLED 137 | typedef struct ModbusInputRegistersMap ModbusInputRegistersMap; 138 | struct ModbusInputRegistersMap { 139 | Uint16 dummy1; 140 | Uint16 dummy2; 141 | Uint16 dummy3; 142 | Uint16 dummy4; 143 | Uint16 dummy5; 144 | Uint16 dummy6; 145 | Uint16 dummy7; 146 | Uint16 dummy8; 147 | Uint16 dummy9; 148 | Uint16 dummy10; 149 | Uint16 dummy11; 150 | Uint16 dummy12; 151 | Uint16 dummy13; 152 | Uint16 dummy14; 153 | Uint16 dummy15; 154 | Uint16 dummy16; 155 | Uint16 dummy17; 156 | Uint16 dummy18; 157 | Uint16 dummy19; 158 | Uint16 dummy20; 159 | Uint16 dummy21; 160 | Uint16 dummy22; 161 | Uint16 dummy23; 162 | Uint16 dummy24; 163 | Uint16 dummy25; 164 | }; 165 | 166 | ModbusInputRegistersMap construct_ModbusInputRegistersMap(); 167 | #endif 168 | 169 | #endif /* MODBUSVARMAP_H_ */ 170 | -------------------------------------------------------------------------------- /contrib/modbus/include/ModbusDefinitions.h: -------------------------------------------------------------------------------- 1 | #ifndef MODBUS_H_ 2 | #define MODBUS_H_ 3 | 4 | // DON'T MODIFY THE CODE BELOW! 5 | 6 | typedef enum { 7 | profiling_MB_TIMER_T35_WAIT = 0, 8 | profiling_MB_RECEIVE, 9 | profiling_MB_PROCESS, 10 | profiling_MB_TRANSMIT 11 | } ModbusProfiling; 12 | 13 | // Read codes 14 | typedef enum { 15 | MB_FUNC_READ_COIL = 1, 16 | MB_FUNC_READ_INPUT, 17 | MB_FUNC_READ_HOLDINGREGISTERS, 18 | MB_FUNC_READ_INPUTREGISTERS, 19 | MB_FUNC_FORCE_COIL, 20 | MB_FUNC_WRITE_HOLDINGREGISTER, 21 | MB_FUNC_FORCE_NCOILS = 15, 22 | MB_FUNC_WRITE_NREGISTERS = 16 23 | } ModbusFunctionCode; 24 | 25 | // State machine constants 26 | typedef enum { 27 | MB_CREATE, 28 | MB_START, 29 | MB_TIMER_T35_WAIT, 30 | MB_IDLE, 31 | MB_RECEIVE, 32 | MB_PROCESS, 33 | MB_TRANSMIT, 34 | MB_DESTROY 35 | } ModbusState; 36 | 37 | // Error codes 38 | typedef enum { 39 | MB_ERROR_ILLEGALFUNC = 1, 40 | MB_ERROR_ILLEGALADDR, 41 | MB_ERROR_ILLEGALDATA, 42 | MB_ERROR_SLVFAILURE, 43 | MB_ERROR_ACKNOWLEDGE, 44 | MB_ERROR_SLVBUSY, 45 | MB_ERROR_NEGACKNOWLEDGE, 46 | MB_ERROR_MEMPARITY, 47 | MB_ERROR_GATEWAYPATHUN 48 | } ModbusError; 49 | 50 | typedef enum { 51 | MB_READ_ADDRESS_HIGH, 52 | MB_READ_ADDRESS_LOW, 53 | MB_READ_TOTALDATA_HIGH, 54 | MB_READ_TOTALDATA_LOW 55 | } ModbusContentRequestReadIndexes; 56 | 57 | 58 | typedef enum { 59 | MB_WRITE_ADDRESS_HIGH, 60 | MB_WRITE_ADDRESS_LOW, 61 | MB_WRITE_VALUE_HIGH, 62 | MB_WRITE_VALUE_LOW 63 | } ModbusContentRequestWriteIndexes; 64 | 65 | typedef enum { 66 | MB_WRITE_N_ADDRESS_HIGH, 67 | MB_WRITE_N_ADDRESS_LOW, 68 | MB_WRITE_N_QUANTITY_HIGH, 69 | MB_WRITE_N_QUANTITY_LOW, 70 | MB_WRITE_N_BYTES, 71 | MB_WRITE_N_VALUES_START_HIGH, 72 | MB_WRITE_N_VALUES_START_LOW 73 | } ModbusContentRequestWriteNIndexes; 74 | 75 | // Size constants (with CRC) ============================== 76 | 77 | #define MB_DATA_MAX_SIZE 0x270E 78 | #define MB_DATA_MAX_REQUEST_SIZE 0x7D 79 | 80 | #define MB_SIZE_COMMON_DATA 4 // Slave address (1 byte) + Function Code (1 byte) + CRC (2 bytes) 81 | #define MB_SIZE_CONTENT_NORMAL 4 82 | // Response sizes 83 | #define MB_SIZE_RESP_READ_MINIMUM MB_SIZE_COMMON_DATA + 1 // MB_SIZE_COMMON_DATA + Number of requested registers (1 byte) 84 | #define MB_SIZE_RESP_WRITE MB_SIZE_COMMON_DATA + MB_SIZE_CONTENT_NORMAL // MB_SIZE_COMMON_DATA + Data address (2 bytes) + Value writen (2 bytes) 85 | #define MB_SIZE_RESP_WRITE_N MB_SIZE_COMMON_DATA + MB_SIZE_CONTENT_NORMAL // MB_SIZE_COMMON_DATA + Data address (2 bytes) + Number of writen values (2 bytes) 86 | #define MB_SIZE_RESP_EXCEPTION MB_SIZE_COMMON_DATA + 1 87 | // Request sizes 88 | #define MB_SIZE_REQ_WRITE_N_MINIMUM MB_SIZE_COMMON_DATA + 5 // Data addr (2 bytes) + Number of registers (2 bytes) + Following data (1 byte) 89 | #define MB_SIZE_REQ_READ MB_SIZE_COMMON_DATA + MB_SIZE_CONTENT_NORMAL 90 | #define MB_SIZE_REQ_WRITE MB_SIZE_COMMON_DATA + MB_SIZE_CONTENT_NORMAL 91 | 92 | // Size constants (without CRC) =========================== 93 | 94 | #define MB_SIZE_COMMON_DATA_WITHOUTCRC MB_SIZE_COMMON_DATA - 2 95 | // Response sizes 96 | #define MB_SIZE_RESP_READ_MINIMUM_WITHOUTCRC MB_SIZE_RESP_READ_MINIMUM - 2 97 | #define MB_SIZE_RESP_WRITE_WITHOUTCRC MB_SIZE_RESP_WRITE - 2 98 | #define MB_SIZE_RESP_WRITE_N_WITHOUTCRC MB_SIZE_RESP_WRITE_N - 2 99 | #define MB_SIZE_RESP_EXCEPTION_WITHOUTCRC MB_SIZE_RESP_EXCEPTION - 2 100 | // Request sizes 101 | #define MB_SIZE_REQ_WRITE_N_MINIMUM_WITHOUTCRC MB_SIZE_REQ_WRITE_N_MINIMUM - 2 102 | #define MB_SIZE_REQ_READ_WITHOUTCRC MB_SIZE_REQ_READ - 2 103 | #define MB_SIZE_REQ_WRITE_WITHOUTCRC MB_SIZE_REQ_WRITE - 2 104 | 105 | #endif /* MODBUS_H_ */ 106 | -------------------------------------------------------------------------------- /contrib/modbus/include/ModbusSettings.h: -------------------------------------------------------------------------------- 1 | #ifndef MODBUSSETTINGS_H_ 2 | #define MODBUSSETTINGS_H_ 3 | 4 | #include "DataTypes.h" 5 | #include "ModbusDefinitions.h" 6 | #include "Serial.h" 7 | 8 | // Modbus settings ======================================== 9 | #define MB_SLAVE_ID 0x01 10 | #define MB_CHECKS true // ID check and CRC check (enabled by default) 11 | #define MB_BUFFER_SIZE 256 // Size of content buffer on ModbusData - Depends on the size of your memory map 12 | #define MB_BROADCAST_EXTRA_ID 255 // Broadcast exclusive ID (it will work with Broadcast ID 0 too) 13 | #define MB_LIBMODBUS_TESTS false 14 | 15 | // Memory map settings ==================================== 16 | #if MB_LIBMODBUS_TESTS == false 17 | #define MB_DATA_MAP "ModbusDataMap.h" 18 | #define MB_32_BITS_REGISTERS true 19 | #define MB_COILS_ENABLED 1 20 | #define MB_INPUTS_ENABLED 0 21 | #define MB_HOLDING_REGISTERS_ENABLED 1 22 | #define MB_INPUT_REGISTERS_ENABLED 0 23 | #else 24 | #define MB_DATA_MAP "ModbusDataMapTests.h" // Use it when you run libmodbus tests 25 | #define MB_32_BITS_REGISTERS false // Use it when you run libmodbus tests 26 | #define MB_COILS_ENABLED 1 27 | #define MB_INPUTS_ENABLED 1 28 | #define MB_HOLDING_REGISTERS_ENABLED 1 29 | #define MB_INPUT_REGISTERS_ENABLED 1 30 | #endif 31 | 32 | // Device settings (DSP f28335) 33 | #define CPU_FREQ 150 34 | #define LOW_SPEED_CLOCK 37500000 35 | //#define LOW_SPEED_CLOCK 15000000 36 | 37 | // Serial settings ======================================== 38 | #define SERIAL_BAUDRATE 38400 39 | #define SERIAL_PARITY SERIAL_PARITY_NONE 40 | #define SERIAL_BITS_NUMBER 8 41 | 42 | #define SERIAL_START_STOP_NUMBER_BITS 2 43 | #if SERIAL_PARITY == SERIAL_PARITY_NONE 44 | #define SERIAL_PARITY_NUMBER_BITS 0 45 | #else 46 | #define SERIAL_PARITY_NUMBER_BITS 1 47 | #endif 48 | 49 | // Timer settings ========================================= 50 | // Time constant 51 | 52 | // Configure the 3.5c time for timer 53 | // For baudrates higher than 19200 is recommended a fixed value 54 | #if SERIAL_BAUDRATE > 19200 55 | #define mbT35 (unsigned long) 1750 56 | #define mbT15 (unsigned long) 750 57 | #else 58 | // Sum up the bits number of a common serial frame 59 | #define SERIAL_FRAME_SIZE \ 60 | SERIAL_START_STOP_NUMBER_BITS \ 61 | + SERIAL_BITS_NUMBER \ 62 | + SERIAL_PARITY_NUMBER_BITS 63 | #define mbT35 (unsigned long) ( (unsigned long)(SERIAL_FRAME_SIZE) * (unsigned long)(3500000 / SERIAL_BAUDRATE) ) 64 | #define mbT15 (unsigned long) ( (unsigned long)(SERIAL_FRAME_SIZE) * (unsigned long)(1500000 / SERIAL_BAUDRATE) ) 65 | #endif 66 | 67 | // Debug settings ========================================= 68 | #define DEBUG_UTILS_PROFILING 0 // Include the necessary files to the linker!! 69 | #define DEBUG_LOG_ENABLED 0 70 | 71 | // Will be used at Log.h 72 | #define MB_DATA_REQUEST_DEBUG_ENABLED 0 73 | #define MB_DATA_RESPONSE_DEBUG_ENABLED 0 74 | #define MB_DATA_HANDLER_DEBUG_ENABLED 0 75 | #define MB_SLAVE_DEBUG_ENABLED 0 76 | #define SERIAL_DEBUG_ENABLED 0 77 | #define TIMER_DEBUG_ENABLED 0 78 | 79 | #endif /* MODBUSSETTINGS_H_ */ 80 | -------------------------------------------------------------------------------- /contrib/modbus/include/ModbusSlave.h: -------------------------------------------------------------------------------- 1 | #ifndef MODBUS_SLAVE_H_ 2 | #define MODBUS_SLAVE_H_ 3 | 4 | #include "ModbusDefinitions.h" 5 | #include "ModbusData.h" 6 | #include "ModbusDataHandler.h" 7 | #include MB_DATA_MAP 8 | #include "Serial.h" 9 | #include "Timer.h" 10 | #include "Crc.h" 11 | 12 | // typedef struct ModbusSlave ModbusSlave; 13 | 14 | struct ModbusSlave { 15 | ModbusState state; 16 | 17 | ModbusData dataRequest; 18 | ModbusData dataResponse; 19 | 20 | #if MB_COILS_ENABLED 21 | ModbusCoilsMap coils; 22 | #endif 23 | #if MB_INPUTS_ENABLED 24 | ModbusInputsMap inputs; 25 | #endif 26 | #if MB_HOLDING_REGISTERS_ENABLED 27 | ModbusHoldingRegistersMap holdingRegisters; 28 | #endif 29 | #if MB_INPUT_REGISTERS_ENABLED 30 | ModbusInputRegistersMap inputRegisters; 31 | #endif 32 | 33 | Serial serial; 34 | Timer timer; 35 | 36 | ModbusDataHandler dataHandler; 37 | 38 | void (*loopStates)(ModbusSlave *self); 39 | void (*create)(ModbusSlave *self); 40 | void (*start)(ModbusSlave *self); 41 | void (*timerT35Wait)(ModbusSlave *self); 42 | void (*idle)(ModbusSlave *self); 43 | void (*receive)(ModbusSlave *self); 44 | void (*process)(ModbusSlave *self); 45 | void (*transmit)(ModbusSlave *self); 46 | void (*destroy)(ModbusSlave *self); 47 | 48 | bool jumpProcessState; 49 | }; 50 | 51 | void slave_loopStates(ModbusSlave *self); 52 | inline void slave_create(ModbusSlave *self); 53 | inline void slave_start(ModbusSlave *self); 54 | inline void slave_timerT35Wait(ModbusSlave *self); 55 | inline void slave_receive(ModbusSlave *self); 56 | inline void slave_process(ModbusSlave *self); 57 | inline void slave_transmit(ModbusSlave *self); 58 | inline void slave_destroy(ModbusSlave *self); 59 | ModbusSlave construct_ModbusSlave(); 60 | 61 | extern ModbusSlave mb; 62 | 63 | #endif 64 | -------------------------------------------------------------------------------- /contrib/modbus/include/Serial.h: -------------------------------------------------------------------------------- 1 | #ifndef MODBUS_SERIAL_H_ 2 | #define MODBUS_SERIAL_H_ 3 | 4 | #include "DataTypes.h" 5 | 6 | typedef struct Serial Serial; 7 | 8 | // Parity constants 9 | typedef enum { 10 | SERIAL_PARITY_NONE, 11 | SERIAL_PARITY_EVEN, 12 | SERIAL_PARITY_ODD 13 | } SerialParity; 14 | 15 | struct Serial { 16 | Uint16 bitsNumber; 17 | Uint16 parityType; 18 | Uint32 baudrate; 19 | 20 | Uint16 fifoWaitBuffer; 21 | 22 | void (*clear)(); 23 | Uint16 (*rxBufferStatus)(); 24 | void (*setSerialRxEnabled)(bool status); 25 | void (*setSerialTxEnabled)(bool status); 26 | void (*init)(Serial *self); 27 | void (*transmitData)(Uint16 * data, Uint16 size); 28 | Uint16 (*getRxBufferedWord)(); 29 | bool (*getRxError)(); 30 | }; 31 | 32 | void serial_clear(); 33 | inline Uint16 serial_rxBufferStatus(); 34 | inline void serial_setSerialRxEnabled(bool status); 35 | inline void serial_setSerialTxEnabled(bool status); 36 | inline void serial_init(Serial *self); 37 | inline void serial_transmitData(Uint16 * data, Uint16 size); 38 | inline Uint16 serial_getRxBufferedWord(); 39 | inline bool serial_getRxError(); 40 | Serial construct_Serial(); 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /contrib/modbus/include/Timer.h: -------------------------------------------------------------------------------- 1 | #ifndef MODBUS_TIMER_H_ 2 | #define MODBUS_TIMER_H_ 3 | 4 | #include "DataTypes.h" 5 | 6 | typedef struct Timer Timer; 7 | 8 | struct Timer { 9 | Uint32 reloadTime; 10 | bool timerEnabled; 11 | 12 | void (*resetTimer)(); 13 | bool (*expiredTimer)(Timer *self); 14 | void (*setTimerReloadPeriod)(Timer *self, Uint32 time); 15 | void (*init)(Timer *self, Uint32 time); 16 | void (*stop)(); 17 | void (*start)(); 18 | }; 19 | 20 | inline void timer_resetTimer(); 21 | inline bool timer_expiredTimer(Timer *self); 22 | inline void timer_setTimerReloadPeriod(Timer *self, Uint32 time); 23 | inline void timer_init(Timer *self, Uint32 time); 24 | inline void timer_stop(); 25 | inline void timer_start(); 26 | 27 | Timer construct_Timer(); 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /contrib/modbus/plataform/DSP2833x/Serial.c: -------------------------------------------------------------------------------- 1 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 2 | #include "Serial.h" 3 | #include "Log.h" 4 | #include "ModbusSettings.h" 5 | 6 | // Clear flags of overflow 7 | void serial_clear(){ 8 | static unsigned short i, destroyFifo; 9 | 10 | SERIAL_DEBUG(); 11 | 12 | // Reset Serial in case of error 13 | if(SciaRegs.SCIRXST.bit.RXERROR == true){ 14 | SciaRegs.SCICTL1.bit.SWRESET=0; 15 | } 16 | 17 | // Clears FIFO buffer (if there is any data) 18 | for (i = SciaRegs.SCIFFRX.bit.RXFFST; i > 0; i--) 19 | destroyFifo = SciaRegs.SCIRXBUF.all; 20 | 21 | // Reset FIFO 22 | SciaRegs.SCIFFRX.bit.RXFIFORESET=1; 23 | SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1; 24 | 25 | SciaRegs.SCICTL1.bit.SWRESET=1; 26 | 27 | } 28 | 29 | // Get how much data is at the RX FIFO Buffer 30 | Uint16 serial_rxBufferStatus(){ 31 | return SciaRegs.SCIFFRX.bit.RXFFST; 32 | } 33 | 34 | // Enable or disable RX (receiver) 35 | void serial_setSerialRxEnabled(bool status){ 36 | SERIAL_DEBUG(); 37 | SciaRegs.SCICTL1.bit.RXENA = status; 38 | } 39 | 40 | // Enable or disable TX (trasmiter) 41 | void serial_setSerialTxEnabled(bool status){ 42 | SERIAL_DEBUG(); 43 | SciaRegs.SCICTL1.bit.TXENA = status; 44 | 45 | } 46 | 47 | // Initialize Serial (actually SCIA) 48 | void serial_init(Serial *self){ 49 | Uint32 baudrate; 50 | 51 | // START: GOT FROM InitScia() FUNCTION (TEXAS FILES) //////////////////////////////////////// 52 | EALLOW; 53 | 54 | /* Enable internal pull-up for the selected pins */ 55 | // Pull-ups can be enabled or disabled disabled by the user. 56 | // This will enable the pullups for the specified pins. 57 | GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) 58 | GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) 59 | 60 | /* Set qualification for selected pins to asynch only */ 61 | // Inputs are synchronized to SYSCLKOUT by default. 62 | // This will select asynch (no qualification) for the selected pins. 63 | GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) 64 | 65 | /* Configure SCI-A pins using GPIO regs*/ 66 | // This specifies which of the possible GPIO pins will be SCI functional pins. 67 | GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation 68 | GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation 69 | 70 | EDIS; 71 | // END: GOT FROM InitScia() FUNCTION (TEXAS FILES) //////////////////////////////////////// 72 | // Number of bytes 73 | 74 | switch(self->bitsNumber) { 75 | case 8: 76 | SciaRegs.SCICCR.bit.SCICHAR = 0x7; 77 | break; 78 | case 7: 79 | SciaRegs.SCICCR.bit.SCICHAR = 0x6; 80 | break; 81 | default: 82 | SciaRegs.SCICCR.bit.SCICHAR = 0x7; 83 | } 84 | 85 | // Parity settings 86 | switch(self->parityType){ 87 | case SERIAL_PARITY_EVEN: 88 | SciaRegs.SCICCR.bit.PARITYENA = 1; 89 | SciaRegs.SCICCR.bit.PARITY = 1; 90 | break; 91 | case SERIAL_PARITY_ODD: 92 | SciaRegs.SCICCR.bit.PARITYENA = 1; 93 | SciaRegs.SCICCR.bit.PARITY = 0; 94 | break; 95 | case SERIAL_PARITY_NONE: 96 | SciaRegs.SCICCR.bit.PARITYENA = 0; 97 | break; 98 | default: 99 | SciaRegs.SCICCR.bit.PARITYENA = 0; 100 | } 101 | 102 | // Baud rate settings - Automatic depending on self->baudrate 103 | // baudrate = (Uint32) (SysCtrlRegs.LOSPCP.bit.LSPCLK / (self->baudrate*8) - 1); 104 | baudrate = (Uint32) (LOW_SPEED_CLOCK / (self->baudrate*8) - 1); 105 | 106 | // Configure the High and Low baud rate registers 107 | SciaRegs.SCIHBAUD = (baudrate & 0xFF00) >> 8; 108 | SciaRegs.SCILBAUD = (baudrate & 0x00FF); 109 | 110 | // Enables TX and RX Interrupts 111 | SciaRegs.SCICTL2.bit.TXINTENA = 0; 112 | SciaRegs.SCIFFTX.bit.TXFFIENA = 0; 113 | SciaRegs.SCICTL2.bit.RXBKINTENA = 0; 114 | SciaRegs.SCIFFRX.bit.RXFFIENA = 0; 115 | 116 | // FIFO TX configurations 117 | SciaRegs.SCIFFTX.bit.TXFFIL = 1; // Interrupt level 118 | SciaRegs.SCIFFTX.bit.SCIFFENA = 1; // Enables FIFO 119 | SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1; // Clear interrupt flag 120 | 121 | // FIFO: RX configurations 122 | SciaRegs.SCIFFRX.bit.RXFFIL = 1; // Interrupt level 123 | SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear interrupt flag 124 | SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 1; // Clear overflow flag 125 | 126 | // FIFO: Control configurations 127 | SciaRegs.SCIFFCT.all=0x00; 128 | 129 | // Enable RX and TX and reset the serial 130 | SciaRegs.SCICTL1.bit.RXENA = 1; 131 | SciaRegs.SCICTL1.bit.TXENA = 1; 132 | SciaRegs.SCICTL1.bit.SWRESET = 1; 133 | 134 | // FIFO: Reset 135 | SciaRegs.SCIFFRX.bit.RXFIFORESET = 1; 136 | SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1; 137 | SciaRegs.SCIFFTX.bit.SCIRST = 0; 138 | SciaRegs.SCIFFTX.bit.SCIRST = 1; 139 | 140 | SERIAL_DEBUG(); 141 | } 142 | 143 | // Transmit variable data based on passed size 144 | void serial_transmitData(Uint16 * data, Uint16 size){ 145 | static unsigned short i = 0; 146 | SERIAL_DEBUG(); 147 | 148 | for (i = 0; i < size; i++){ 149 | SciaRegs.SCITXBUF= data[i]; 150 | 151 | if(i%4 == 0){ 152 | while (SciaRegs.SCICTL2.bit.TXEMPTY != true) ; 153 | } 154 | } 155 | 156 | // If you want to wait until the TX buffer is empty, uncomment line below 157 | // while (SciaRegs.SCICTL2.bit.TXEMPTY != true) ; 158 | } 159 | 160 | // Read data from buffer (byte per byte) 161 | Uint16 serial_getRxBufferedWord(){ 162 | SERIAL_DEBUG(); 163 | 164 | // TODO: check if it is needed 165 | while (SciaRegs.SCIRXST.bit.RXRDY) ; 166 | 167 | return SciaRegs.SCIRXBUF.all; 168 | } 169 | 170 | bool serial_getRxError(){ 171 | SERIAL_DEBUG(); 172 | 173 | return SciaRegs.SCIRXST.bit.RXERROR; 174 | } 175 | 176 | // Construct the Serial Module 177 | Serial construct_Serial(){ 178 | Serial serial; 179 | 180 | serial.clear = serial_clear; 181 | serial.rxBufferStatus = serial_rxBufferStatus; 182 | serial.setSerialRxEnabled = serial_setSerialRxEnabled; 183 | serial.setSerialTxEnabled = serial_setSerialTxEnabled; 184 | serial.init = serial_init; 185 | serial.transmitData = serial_transmitData; 186 | serial.getRxBufferedWord = serial_getRxBufferedWord; 187 | serial.getRxError = serial_getRxError; 188 | 189 | serial.fifoWaitBuffer = 0; 190 | 191 | SERIAL_DEBUG(); 192 | 193 | return serial; 194 | } 195 | -------------------------------------------------------------------------------- /contrib/modbus/plataform/DSP2833x/Timer.c: -------------------------------------------------------------------------------- 1 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 2 | #include "DSP2833x_CpuTimers.h" 3 | #include "Timer.h" 4 | #include "Log.h" 5 | #include "ModbusSettings.h" 6 | 7 | struct CPUTIMER_VARS CpuTimer0; 8 | 9 | void timer_resetTimer(){ 10 | CpuTimer0Regs.TCR.bit.TRB = 1; 11 | TIMER_DEBUG(); 12 | } 13 | 14 | bool timer_expiredTimer(Timer *self){ 15 | Uint32 timerZeroed = CpuTimer0Regs.TCR.bit.TIF; 16 | TIMER_DEBUG(); 17 | 18 | if (timerZeroed == true) { 19 | return true; 20 | } 21 | else { 22 | return false; 23 | } 24 | } 25 | 26 | void timer_setTimerReloadPeriod(Timer *self, Uint32 time){ 27 | TIMER_DEBUG(); 28 | 29 | self->stop(); 30 | self->reloadTime = time; 31 | 32 | CpuTimer0.CPUFreqInMHz = CPU_FREQ; 33 | CpuTimer0.PeriodInUSec = time; 34 | CpuTimer0.RegsAddr->PRD.all = (long) time * CPU_FREQ; 35 | } 36 | 37 | 38 | void timer_init(Timer *self, Uint32 time){ 39 | // START: GOT FROM TEXAS FILES ////////////////////////////////////// 40 | // CPU Timer 0 41 | // Initialize address pointers to respective timer registers: 42 | CpuTimer0.RegsAddr = &CpuTimer0Regs; 43 | // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): 44 | CpuTimer0Regs.TPR.all = 0; 45 | CpuTimer0Regs.TPRH.all = 0; 46 | // Make sure timer is stopped: 47 | CpuTimer0Regs.TCR.bit.TSS = 1; 48 | // Reload all counter register with period value: 49 | CpuTimer0Regs.TCR.bit.TRB = 1; 50 | // Reset interrupt counters: 51 | CpuTimer0.InterruptCount = 0; 52 | // END: GOT FROM TEXAS FILES //////////////////////////////////////// 53 | 54 | // Config the timer reload period 55 | self->reloadTime = time; 56 | CpuTimer0.CPUFreqInMHz = CPU_FREQ; 57 | CpuTimer0.PeriodInUSec = time; 58 | CpuTimer0Regs.PRD.all = (long) time * CPU_FREQ; 59 | 60 | // Run mode settings 61 | CpuTimer0Regs.TCR.bit.SOFT = 1; 62 | CpuTimer0Regs.TCR.bit.FREE = 1; // Timer Free Run 63 | 64 | // If needed, you can set interruptions and other things here 65 | // CpuTimer0.RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt 66 | 67 | TIMER_DEBUG(); 68 | } 69 | 70 | void timer_stop(){ 71 | CpuTimer0Regs.TCR.bit.TSS = 1; 72 | TIMER_DEBUG(); 73 | } 74 | 75 | void timer_start(){ 76 | CpuTimer0Regs.TCR.bit.TSS = 0; 77 | TIMER_DEBUG(); 78 | } 79 | 80 | Timer construct_Timer(){ 81 | Timer timer; 82 | 83 | timer.timerEnabled = false; 84 | timer.reloadTime = 0; 85 | 86 | timer.resetTimer = timer_resetTimer; 87 | timer.expiredTimer = timer_expiredTimer; 88 | timer.setTimerReloadPeriod = timer_setTimerReloadPeriod; 89 | timer.init = timer_init; 90 | timer.stop = timer_stop; 91 | timer.start = timer_start; 92 | 93 | TIMER_DEBUG(); 94 | 95 | return timer; 96 | } 97 | -------------------------------------------------------------------------------- /contrib/modbus/plataform/DSP2833x/include/DSP2833x_CpuTimers.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: March 20, 2007 15:33:42 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_CpuTimers.h 6 | // 7 | // TITLE: DSP2833x CPU 32-bit Timers Register Definitions. 8 | // 9 | // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and 10 | // other realtime operating systems. 11 | // 12 | // Do not use these two timers in your application if you ever plan 13 | // on integrating DSP-BIOS or another realtime OS. 14 | // 15 | // For this reason, comment out the code to manipulate these two timers 16 | // if using DSP-BIOS or another realtime OS. 17 | // 18 | //########################################################################### 19 | // $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 20 | // $Release Date: August 4, 2009 $ 21 | //########################################################################### 22 | 23 | #ifndef DSP2833x_CPU_TIMERS_H 24 | #define DSP2833x_CPU_TIMERS_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | //--------------------------------------------------------------------------- 31 | // CPU Timer Register Bit Definitions: 32 | // 33 | // 34 | // TCR: Control register bit definitions: 35 | struct TCR_BITS { // bits description 36 | Uint16 rsvd1:4; // 3:0 reserved 37 | Uint16 TSS:1; // 4 Timer Start/Stop 38 | Uint16 TRB:1; // 5 Timer reload 39 | Uint16 rsvd2:4; // 9:6 reserved 40 | Uint16 SOFT:1; // 10 Emulation modes 41 | Uint16 FREE:1; // 11 42 | Uint16 rsvd3:2; // 12:13 reserved 43 | Uint16 TIE:1; // 14 Output enable 44 | Uint16 TIF:1; // 15 Interrupt flag 45 | }; 46 | 47 | union TCR_REG { 48 | Uint16 all; 49 | struct TCR_BITS bit; 50 | }; 51 | 52 | // TPR: Pre-scale low bit definitions: 53 | struct TPR_BITS { // bits description 54 | Uint16 TDDR:8; // 7:0 Divide-down low 55 | Uint16 PSC:8; // 15:8 Prescale counter low 56 | }; 57 | 58 | union TPR_REG { 59 | Uint16 all; 60 | struct TPR_BITS bit; 61 | }; 62 | 63 | // TPRH: Pre-scale high bit definitions: 64 | struct TPRH_BITS { // bits description 65 | Uint16 TDDRH:8; // 7:0 Divide-down high 66 | Uint16 PSCH:8; // 15:8 Prescale counter high 67 | }; 68 | 69 | union TPRH_REG { 70 | Uint16 all; 71 | struct TPRH_BITS bit; 72 | }; 73 | 74 | // TIM, TIMH: Timer register definitions: 75 | struct TIM_REG { 76 | Uint16 LSW; 77 | Uint16 MSW; 78 | }; 79 | 80 | union TIM_GROUP { 81 | Uint32 all; 82 | struct TIM_REG half; 83 | }; 84 | 85 | // PRD, PRDH: Period register definitions: 86 | struct PRD_REG { 87 | Uint16 LSW; 88 | Uint16 MSW; 89 | }; 90 | 91 | union PRD_GROUP { 92 | Uint32 all; 93 | struct PRD_REG half; 94 | }; 95 | 96 | //--------------------------------------------------------------------------- 97 | // CPU Timer Register File: 98 | // 99 | struct CPUTIMER_REGS { 100 | union TIM_GROUP TIM; // Timer counter register 101 | union PRD_GROUP PRD; // Period register 102 | union TCR_REG TCR; // Timer control register 103 | Uint16 rsvd1; // reserved 104 | union TPR_REG TPR; // Timer pre-scale low 105 | union TPRH_REG TPRH; // Timer pre-scale high 106 | }; 107 | 108 | //--------------------------------------------------------------------------- 109 | // CPU Timer Support Variables: 110 | // 111 | struct CPUTIMER_VARS { 112 | volatile struct CPUTIMER_REGS *RegsAddr; 113 | Uint32 InterruptCount; 114 | float CPUFreqInMHz; 115 | float PeriodInUSec; 116 | }; 117 | 118 | //--------------------------------------------------------------------------- 119 | // Function prototypes and external definitions: 120 | // 121 | void InitCpuTimers(void); 122 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 123 | 124 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 125 | extern struct CPUTIMER_VARS CpuTimer0; 126 | 127 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS 128 | extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 129 | extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 130 | 131 | extern struct CPUTIMER_VARS CpuTimer1; 132 | extern struct CPUTIMER_VARS CpuTimer2; 133 | 134 | //--------------------------------------------------------------------------- 135 | // Usefull Timer Operations: 136 | // 137 | // Start Timer: 138 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 139 | 140 | // Stop Timer: 141 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 142 | 143 | // Reload Timer With period Value: 144 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 145 | 146 | // Read 32-Bit Timer Value: 147 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 148 | 149 | // Read 32-Bit Period Value: 150 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 151 | 152 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 153 | // Do not use these two timers if you ever plan on integrating 154 | // DSP-BIOS or another realtime OS. 155 | // 156 | // For this reason, comment out the code to manipulate these two timers 157 | // if using DSP-BIOS or another realtime OS. 158 | 159 | // Start Timer: 160 | #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 161 | #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 162 | 163 | 164 | // Stop Timer: 165 | #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 166 | #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 167 | 168 | // Reload Timer With period Value: 169 | #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 170 | #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 171 | 172 | // Read 32-Bit Timer Value: 173 | #define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 174 | #define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 175 | 176 | // Read 32-Bit Period Value: 177 | #define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 178 | #define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 179 | 180 | 181 | #ifdef __cplusplus 182 | } 183 | #endif /* extern "C" */ 184 | 185 | #endif // end of DSP2833x_CPU_TIMERS_H definition 186 | 187 | 188 | //=========================================================================== 189 | // End of file. 190 | //=========================================================================== 191 | -------------------------------------------------------------------------------- /makeCCSv3.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | SET CCSv3OutputDir=CCSv3 3 | SET CopySerialTimerHeader=0 4 | 5 | echo ## Entering at 28335ModbusSlave directory... 6 | cd %~dp0 7 | echo. 8 | 9 | if not exist %CCSv3OutputDir% ( 10 | echo ## Creating %CCSv3OutputDir% directory... 11 | mkdir %CCSv3OutputDir% 12 | mkdir %CCSv3OutputDir%\Include 13 | mkdir %CCSv3OutputDir%\Source 14 | echo. 15 | ) 16 | 17 | 18 | echo ## Copying .c files to %CCSv3OutputDir%\Source... 19 | copy contrib\modbus\*.c %CCSv3OutputDir%\Source 20 | copy contrib\modbus\plataform\DSP2833x\*.c %CCSv3OutputDir%\Source 21 | echo. 22 | 23 | echo ## Copying .h files to %CCSv3OutputDir%\Include... 24 | copy contrib\modbus\include\*.h %CCSv3OutputDir%\Include 25 | if %CopySerialTimerHeader%==1 ( 26 | copy contrib\modbus\plataform\DSP2833x\include\*.h %CCSv3OutputDir%\Include 27 | ) 28 | echo. 29 | 30 | echo ## Done! 31 | pause -------------------------------------------------------------------------------- /makeCCSv3.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | script=$(readlink -f "$0") 3 | scriptPath=$(dirname "$script") 4 | CCSv3OutputDir="CCSv3" 5 | CopySerialTimerHeader=1 6 | 7 | echo "## Entering at 28335ModbusSlave directory..." 8 | cd $scriptPath 9 | echo 10 | 11 | if [ -d $CCSv3OutputDir ]; then 12 | echo "## Destroying old $CCSv3OutputDir directory..." 13 | echo 14 | rm -rf $CCSv3OutputDir; 15 | fi 16 | 17 | if [ ! -d $CCSv3OutputDir ]; then 18 | echo "## Creating $CCSv3OutputDir directory..." 19 | mkdir $CCSv3OutputDir 20 | mkdir $CCSv3OutputDir/Include 21 | mkdir $CCSv3OutputDir/Source 22 | echo 23 | fi 24 | 25 | echo "## Copying .c files to $CCSv3OutputDir/Source..." 26 | cp contrib/modbus/*.c $CCSv3OutputDir/Source 27 | cp contrib/modbus/plataform/DSP2833x/*.c $CCSv3OutputDir/Source 28 | echo 29 | 30 | echo "## Copying .h files to $CCSv3OutputDir/Include..." 31 | cp contrib/modbus/include/*.h $CCSv3OutputDir/Include 32 | if [ $CopySerialTimerHeader == 1 ]; then 33 | cp contrib/modbus/plataform/DSP2833x/include/*.h $CCSv3OutputDir/Include 34 | fi 35 | echo 36 | 37 | echo "## Ziping CCSv3 fileds" 38 | rm CCSv3.zip 39 | zip -r CCSv3 CCSv3 40 | 41 | echo "## Done!" 42 | -------------------------------------------------------------------------------- /src/DSP2833x_ADC_cal.asm: -------------------------------------------------------------------------------- 1 | ;; TI File $Revision: /main/1 $ 2 | ;; Checkin $Date: July 30, 2007 10:29:23 $ 3 | ;;########################################################################### 4 | ;; 5 | ;; FILE: ADC_cal.asm 6 | ;; 7 | ;; TITLE: 2833x Boot Rom ADC Cal routine. 8 | ;; 9 | ;; Functions: 10 | ;; 11 | ;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers 12 | ;; Notes: 13 | ;; 14 | ;;########################################################################### 15 | ;; $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 16 | ;; $Release Date: August 4, 2009 $ 17 | ;;########################################################################### 18 | 19 | .def _ADC_cal 20 | .asg "0x711C", ADCREFSEL_LOC 21 | 22 | ;----------------------------------------------- 23 | ; _ADC_cal 24 | ;----------------------------------------------- 25 | ;----------------------------------------------- 26 | ; This is the ADC cal routine.This routine is programmed into 27 | ; reserved memory by the factory. 0xAAAA and 0xBBBB are place- 28 | ; holders for calibration data. 29 | ;The actual values programmed by TI are device specific. 30 | ; 31 | ; This function assumes that the clocks have been 32 | ; enabled to the ADC module. 33 | ;----------------------------------------------- 34 | 35 | .sect ".adc_cal" 36 | 37 | _ADC_cal 38 | MOVW DP, #ADCREFSEL_LOC >> 6 39 | MOV @28, #0xAAAA ; actual value may not be 0xAAAA 40 | MOV @29, #0xBBBB ; actual value may not be 0xBBBB 41 | LRETR 42 | ;eof ---------- 43 | -------------------------------------------------------------------------------- /src/DSP2833x_CodeStartBranch.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:45:55 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_CodeStartBranch.asm 6 | ;// 7 | ;// TITLE: Branch for redirecting code execution after boot. 8 | ;// 9 | ;// For these examples, code_start is the first code that is executed after 10 | ;// exiting the boot ROM code. 11 | ;// 12 | ;// The codestart section in the linker cmd file is used to physically place 13 | ;// this code at the correct memory location. This section should be placed 14 | ;// at the location the BOOT ROM will re-direct the code to. For example, 15 | ;// for boot to FLASH this code will be located at 0x3f7ff6. 16 | ;// 17 | ;// In addition, the example DSP2833x projects are setup such that the codegen 18 | ;// entry point is also set to the code_start label. This is done by linker 19 | ;// option -e in the project build options. When the debugger loads the code, 20 | ;// it will automatically set the PC to the "entry point" address indicated by 21 | ;// the -e linker option. In this case the debugger is simply assigning the PC, 22 | ;// it is not the same as a full reset of the device. 23 | ;// 24 | ;// The compiler may warn that the entry point for the project is other then 25 | ;// _c_init00. _c_init00 is the C environment setup and is run before 26 | ;// main() is entered. The code_start code will re-direct the execution 27 | ;// to _c_init00 and thus there is no worry and this warning can be ignored. 28 | ;// 29 | ;//########################################################################### 30 | ;// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 31 | ;// $Release Date: August 4, 2009 $ 32 | ;//########################################################################### 33 | 34 | 35 | *********************************************************************** 36 | 37 | WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 38 | 39 | .ref _c_int00 40 | .global code_start 41 | 42 | *********************************************************************** 43 | * Function: codestart section 44 | * 45 | * Description: Branch to code starting point 46 | *********************************************************************** 47 | 48 | .sect "codestart" 49 | 50 | code_start: 51 | .if WD_DISABLE == 1 52 | LB wd_disable ;Branch to watchdog disable code 53 | .else 54 | LB _c_int00 ;Branch to start of boot.asm in RTS library 55 | .endif 56 | 57 | ;end codestart section 58 | 59 | 60 | *********************************************************************** 61 | * Function: wd_disable 62 | * 63 | * Description: Disables the watchdog timer 64 | *********************************************************************** 65 | .if WD_DISABLE == 1 66 | 67 | .text 68 | wd_disable: 69 | SETC OBJMODE ;Set OBJMODE for 28x object code 70 | EALLOW ;Enable EALLOW protected register access 71 | MOVZ DP, #7029h>>6 ;Set data page for WDCR register 72 | MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD 73 | EDIS ;Disable EALLOW protected register access 74 | LB _c_int00 ;Branch to start of boot.asm in RTS library 75 | 76 | .endif 77 | 78 | ;end wd_disable 79 | 80 | 81 | 82 | .end 83 | 84 | ;//=========================================================================== 85 | ;// End of file. 86 | ;//=========================================================================== 87 | -------------------------------------------------------------------------------- /src/DSP2833x_usDelay.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/4 $ 2 | ;// Checkin $Date: July 30, 2007 10:28:57 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_usDelay.asm 6 | ;// 7 | ;// TITLE: Simple delay function 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// This is a simple delay function that can be used to insert a specified 12 | ;// delay into code. 13 | ;// 14 | ;// This function is only accurate if executed from internal zero-waitstate 15 | ;// SARAM. If it is executed from waitstate memory then the delay will be 16 | ;// longer then specified. 17 | ;// 18 | ;// To use this function: 19 | ;// 20 | ;// 1 - update the CPU clock speed in the DSP2833x_Examples.h 21 | ;// file. For example: 22 | ;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed 23 | ;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed 24 | ;// 25 | ;// 2 - Call this function by using the DELAY_US(A) macro 26 | ;// that is defined in the DSP2833x_Examples.h file. This macro 27 | ;// will convert the number of microseconds specified 28 | ;// into a loop count for use with this function. 29 | ;// This count will be based on the CPU frequency you specify. 30 | ;// 31 | ;// 3 - For the most accurate delay 32 | ;// - Execute this function in 0 waitstate RAM. 33 | ;// - Disable interrupts before calling the function 34 | ;// If you do not disable interrupts, then think of 35 | ;// this as an "at least" delay function as the actual 36 | ;// delay may be longer. 37 | ;// 38 | ;// The C assembly call from the DELAY_US(time) macro will 39 | ;// look as follows: 40 | ;// 41 | ;// extern void Delay(long LoopCount); 42 | ;// 43 | ;// MOV AL,#LowLoopCount 44 | ;// MOV AH,#HighLoopCount 45 | ;// LCR _Delay 46 | ;// 47 | ;// Or as follows (if count is less then 16-bits): 48 | ;// 49 | ;// MOV ACC,#LoopCount 50 | ;// LCR _Delay 51 | ;// 52 | ;// 53 | ;//########################################################################### 54 | ;// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $ 55 | ;// $Release Date: August 4, 2009 $ 56 | ;//########################################################################### 57 | 58 | .def _DSP28x_usDelay 59 | .sect "ramfuncs" 60 | 61 | .global __DSP28x_usDelay 62 | _DSP28x_usDelay: 63 | SUB ACC,#1 64 | BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 65 | LRETR 66 | 67 | ;There is a 9/10 cycle overhead and each loop 68 | ;takes five cycles. The LoopCount is given by 69 | ;the following formula: 70 | ; DELAY_CPU_CYCLES = 9 + 5*LoopCount 71 | ; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 72 | ; The macro DELAY_US(A) performs this calculation for you 73 | ; 74 | ;//=========================================================================== 75 | ;// End of file. 76 | ;//=========================================================================== 77 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | #include "ModbusSlave.h" 2 | #include "DSP2833x_Device.h" 3 | #include "DSP2833x_GlobalPrototypes.h" 4 | 5 | ModbusSlave mb; 6 | 7 | int main(){ 8 | InitSysCtrl(); 9 | 10 | mb = construct_ModbusSlave(); 11 | 12 | #if MB_LIBMODBUS_TESTS 13 | // 0xAC, 0xDB, 0x35 14 | mb.inputs.dummy10 = 1; 15 | mb.inputs.dummy11 = 1; 16 | mb.inputs.dummy13 = 1; 17 | mb.inputs.dummy15 = 1; 18 | mb.inputs.dummy16 = 1; 19 | mb.inputs.dummy17 = 1; 20 | mb.inputs.dummy19 = 1; 21 | mb.inputs.dummy20 = 1; 22 | mb.inputs.dummy22 = 1; 23 | mb.inputs.dummy23 = 1; 24 | mb.inputs.dummy24 = 1; 25 | mb.inputs.dummy26 = 1; 26 | mb.inputs.dummy28 = 1; 27 | mb.inputs.dummy29 = 1; 28 | 29 | mb.inputRegisters.dummy25 = 0x000A; 30 | 31 | mb.holdingRegisters.dummy2 = 0x01; 32 | mb.holdingRegisters.dummy3 = 0x01; 33 | mb.holdingRegisters.dummy4 = 0x01; 34 | mb.holdingRegisters.dummy5 = 0x01; 35 | mb.holdingRegisters.dummy6 = 0x01; 36 | #endif 37 | 38 | while(1) { 39 | mb.loopStates(&mb); 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /tests/README.md: -------------------------------------------------------------------------------- 1 | You need libmodbus installed to use the unit-test-client program. It is adapted from the libmodbus unit tests. As is hard to test code on DSPs, I am using this client to certify that the requests are working properly. 2 | 3 | Sometimes, depending on the serial adapter that you're using, the program will throw a timeout. 4 | 5 | You can add tests to unit-test-client.c code and recompile the program. If you find anything that is not covered by the test, submit a pull request with it. 6 | -------------------------------------------------------------------------------- /tests/unit-test.h: -------------------------------------------------------------------------------- 1 | /* tests/unit-test.h. Generated from unit-test.h.in by configure. */ 2 | /* 3 | * Copyright © 2008-2014 Stéphane Raimbault 4 | * 5 | * This program is free software: you can redistribute it and/or modify 6 | * it under the terms of the BSD License. 7 | */ 8 | 9 | #ifndef _UNIT_TEST_H_ 10 | #define _UNIT_TEST_H_ 11 | 12 | /* Constants defined by configure.ac */ 13 | #define HAVE_INTTYPES_H 1 14 | #define HAVE_STDINT_H 1 15 | 16 | #ifdef HAVE_INTTYPES_H 17 | #include 18 | #endif 19 | #ifdef HAVE_STDINT_H 20 | # ifndef _MSC_VER 21 | # include 22 | # else 23 | # include "stdint.h" 24 | # endif 25 | #endif 26 | 27 | #define SERVER_ID 1 28 | #define INVALID_SERVER_ID 18 29 | 30 | /* Server allocates address + nb */ 31 | const uint16_t UT_BITS_ADDRESS = 0x07; 32 | const uint16_t UT_BITS_NB = 0x22; 33 | const uint8_t UT_BITS_TAB[] = { 0xCD, 0x6B, 0xB2, 0x0E, 0x03 }; 34 | 35 | const uint16_t UT_INPUT_BITS_ADDRESS = 0x07; 36 | const uint16_t UT_INPUT_BITS_NB = 0x16; 37 | const uint8_t UT_INPUT_BITS_TAB[] = { 0xAC, 0xDB, 0x35 }; 38 | 39 | const uint16_t UT_REGISTERS_ADDRESS = 0x0019; 40 | /* Raise a manual exception when this address is used for the first byte */ 41 | const uint16_t UT_REGISTERS_ADDRESS_SPECIAL = 0x6C; 42 | /* The response of the server will contains an invalid TID or slave */ 43 | const uint16_t UT_REGISTERS_ADDRESS_INVALID_TID_OR_SLAVE = 0x6D; 44 | /* The server will wait for 1 second before replying to test timeout */ 45 | const uint16_t UT_REGISTERS_ADDRESS_SLEEP_500_MS = 0x6E; 46 | /* The server will wait for 5 ms before sending each byte */ 47 | const uint16_t UT_REGISTERS_ADDRESS_BYTE_SLEEP_5_MS = 0x6F; 48 | 49 | const uint16_t UT_REGISTERS_NB = 0x3; 50 | const uint16_t UT_REGISTERS_TAB[] = { 0x022B, 0x0001, 0x0064 }; 51 | /* If the following value is used, a bad response is sent. 52 | It's better to test with a lower value than 53 | UT_REGISTERS_NB_POINTS to try to raise a segfault. */ 54 | const uint16_t UT_REGISTERS_NB_SPECIAL = 0x2; 55 | 56 | const uint16_t UT_INPUT_REGISTERS_ADDRESS = 0x0018; 57 | const uint16_t UT_INPUT_REGISTERS_NB = 0x1; 58 | const uint16_t UT_INPUT_REGISTERS_TAB[] = { 0x000A }; 59 | 60 | const float UT_REAL = 916.540649; 61 | const uint32_t UT_IREAL = 0x4465229a; 62 | const uint32_t UT_IREAL_DCBA = 0x9a226544; 63 | 64 | #endif /* _UNIT_TEST_H_ */ 65 | --------------------------------------------------------------------------------