├── .gitignore ├── FPGA-Wave-Generator.qpf ├── FPGA-Wave-Generator.qsf ├── README.md ├── ip ├── altpll │ ├── pll.ppf │ ├── pll.qip │ └── pll.v ├── lpm_add_sub │ ├── phase_adder.qip │ └── phase_adder.v └── rom_sin │ ├── rom_sin.qip │ └── rom_sin.v ├── src ├── toplevel.v └── waveform_controller.v └── waveform └── sin512.mif /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | ### AlteraQuartusII ### 3 | ##list taken from http://www.alterawiki.com/wiki/Version_Control (01.10.2015) 4 | 5 | ######### Quartus II source files 6 | 7 | # project files: 8 | ### project_name.qpf Quartus II project file 9 | ### project_name.qsf Quartus constraint file (lists the hardware constraints defined for a project, from the used chip and pinout to timing constraints) 10 | ### project_name.qws Quartus Window Settings ? (the configuration of the Quartus gui for the project, may be omitted) 11 | 12 | # top level source files: 13 | ### project_name.bdf Block diagram / Schematic file (top level schematic file, there may be many nested files) 14 | ### project_name.vhd VHDL file (top level VHDL file) 15 | ### project_name.v Verilog file (top level Verilog file) 16 | 17 | # component source files: 18 | ### component_name.bsf Block Symbol file (component symbol file) 19 | ### component_name.vhd VHDL file (top level VHDL file) 20 | ### component_name.v Verilog file (top level Verilog file) 21 | 22 | # SOPC builder project source files (SOPC builder creates many VHDL or Verilog files, that you do not need to store) 23 | ### sopc_project_name.ptf the list and configuration of components selected in the SOPC gui 24 | ### sopc_project_name.bsf Block Symbol file (SOPC component symbol file, especially if you modified it) 25 | 26 | # Board Description (if you created your own board, the list is incomplete!) 27 | ### board_name/class.ptf 28 | 29 | # software source files: 30 | ### tbd 31 | 32 | ######## Quartus II binary files 33 | 34 | # hardware binary files 35 | ### project_name.sof SRAM Object File 36 | 37 | # software binary files 38 | ### tbd 39 | 40 | .qsys_edit/ 41 | output_files/ 42 | db/ 43 | incremental_db/ 44 | greybox_tmp/ 45 | simulation/ 46 | stp2_auto_stripped.stp 47 | *.qws 48 | *.qdf 49 | *.done 50 | *.rpt 51 | *.summary 52 | *.smsg 53 | *.jdi 54 | *.pin 55 | *.pof 56 | *.sof 57 | *.cdf 58 | *.dpf 59 | *.stp 60 | 61 | # Created by https://www.gitignore.io/api/eclipse 62 | 63 | ### Eclipse ### 64 | 65 | .metadata 66 | bin/ 67 | tmp/ 68 | *.tmp 69 | *.bak 70 | *.swp 71 | *~.nib 72 | local.properties 73 | .settings/ 74 | .loadpath 75 | .recommenders 76 | 77 | # Eclipse Core 78 | .project 79 | 80 | # External tool builders 81 | .externalToolBuilders/ 82 | 83 | # Locally stored "Eclipse launch configurations" 84 | *.launch 85 | 86 | # PyDev specific (Python IDE for Eclipse) 87 | *.pydevproject 88 | 89 | # CDT-specific (C/C++ Development Tooling) 90 | .cproject 91 | 92 | # JDT-specific (Eclipse Java Development Tools) 93 | .classpath 94 | 95 | # Java annotation processor (APT) 96 | .factorypath 97 | 98 | # PDT-specific (PHP Development Tools) 99 | .buildpath 100 | 101 | # sbteclipse plugin 102 | .target 103 | 104 | # Tern plugin 105 | .tern-project 106 | 107 | # TeXlipse plugin 108 | .texlipse 109 | 110 | # STS (Spring Tool Suite) 111 | .springBeans 112 | 113 | # Code Recommenders 114 | .recommenders/ 115 | 116 | ### Sigasi ### 117 | .library_mapping.xml 118 | -------------------------------------------------------------------------------- /FPGA-Wave-Generator.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2016 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Intel and sold by Intel or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 22 | # Date created = 12:00:31 December 10, 2016 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.1" 27 | DATE = "12:00:31 December 10, 2016" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "FPGA-Wave-Generator" 32 | -------------------------------------------------------------------------------- /FPGA-Wave-Generator.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2016 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Intel and sold by Intel or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 22 | # Date created = 21:03:34 December 10, 2016 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # FPGA-Wave-Generator_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus Prime software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | # -------------------------------------------------------------------------- # 41 | # 42 | # Copyright (C) 2016 Intel Corporation. All rights reserved. 43 | # Your use of Intel Corporation's design tools, logic functions 44 | # and other software and tools, and its AMPP partner logic 45 | # functions, and any output files from any of the foregoing 46 | # (including device programming or simulation files), and any 47 | # associated documentation or information are expressly subject 48 | # to the terms and conditions of the Intel Program License 49 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 50 | # the Intel MegaCore Function License Agreement, or other 51 | # applicable license agreement, including, without limitation, 52 | # that your use is for the sole purpose of programming logic 53 | # devices manufactured by Intel and sold by Intel or its 54 | # authorized distributors. Please refer to the applicable 55 | # agreement for further details. 56 | # 57 | # -------------------------------------------------------------------------- # 58 | # 59 | # Quartus Prime 60 | # Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 61 | # Date created = 12:00:31 December 10, 2016 62 | # 63 | # -------------------------------------------------------------------------- # 64 | # 65 | # Notes: 66 | # 67 | # 1) The default values for assignments are stored in the file: 68 | # FPGA-Wave-Generator_assignment_defaults.qdf 69 | # If this file doesn't exist, see file: 70 | # assignment_defaults.qdf 71 | # 72 | # 2) Altera recommends that you do not modify this file. This 73 | # file is updated automatically by the Quartus Prime software 74 | # and any changes you make may be lost or overwritten. 75 | # 76 | # -------------------------------------------------------------------------- # 77 | 78 | 79 | set_global_assignment -name FAMILY "Cyclone IV E" 80 | set_global_assignment -name DEVICE EP4CE6F17C8 81 | set_global_assignment -name TOP_LEVEL_ENTITY toplevel 82 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 83 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:00:31 DECEMBER 10, 2016" 84 | set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" 85 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 86 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 87 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 88 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 89 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 90 | set_global_assignment -name EDA_TIME_SCALE "1 ns" -section_id eda_simulation 91 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 92 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 93 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 94 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 95 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 96 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 97 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 98 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH toplevel -section_id eda_simulation 99 | set_global_assignment -name EDA_TEST_BENCH_NAME toplevel -section_id eda_simulation 100 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id toplevel 101 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME toplevel_vlg_tst -section_id toplevel 102 | set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/toplevel.vt -section_id toplevel 103 | set_global_assignment -name ENABLE_SIGNALTAP ON 104 | set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp 105 | set_location_assignment PIN_E1 -to clk_50m 106 | set_location_assignment PIN_D8 -to da_db[7] 107 | set_location_assignment PIN_E8 -to da_db[6] 108 | set_location_assignment PIN_F7 -to da_db[5] 109 | set_location_assignment PIN_F9 -to da_db[4] 110 | set_location_assignment PIN_E9 -to da_db[3] 111 | set_location_assignment PIN_C9 -to da_db[2] 112 | set_location_assignment PIN_D9 -to da_db[1] 113 | set_location_assignment PIN_E10 -to da_db[0] 114 | set_location_assignment PIN_E7 -to da_clk 115 | set_location_assignment PIN_D11 -to freq_word[19] 116 | set_location_assignment PIN_E11 -to freq_word[17] 117 | set_location_assignment PIN_D12 -to freq_word[18] 118 | set_location_assignment PIN_C14 -to freq_word[16] 119 | set_location_assignment PIN_F10 -to freq_word[15] 120 | set_location_assignment PIN_F11 -to freq_word[13] 121 | set_location_assignment PIN_F14 -to freq_word[11] 122 | set_location_assignment PIN_K9 -to freq_word[9] 123 | set_location_assignment PIN_K10 -to freq_word[8] 124 | set_location_assignment PIN_G16 -to freq_word[7] 125 | set_location_assignment PIN_J12 -to freq_word[5] 126 | set_location_assignment PIN_J14 -to freq_word[3] 127 | set_location_assignment PIN_K12 -to freq_word[1] 128 | set_location_assignment PIN_D14 -to freq_word[14] 129 | set_location_assignment PIN_F13 -to freq_word[12] 130 | set_location_assignment PIN_G11 -to freq_word[10] 131 | set_location_assignment PIN_J11 -to freq_word[6] 132 | set_location_assignment PIN_J13 -to freq_word[4] 133 | set_location_assignment PIN_K11 -to freq_word[2] 134 | set_location_assignment PIN_L14 -to freq_word[0] 135 | set_location_assignment PIN_N14 -to wave_word[1] 136 | set_location_assignment PIN_M12 -to wave_word[0] 137 | set_location_assignment PIN_G5 -to pwm_word[0] 138 | set_location_assignment PIN_F2 -to pwm_word[1] 139 | set_location_assignment PIN_F3 -to pwm_word[2] 140 | set_location_assignment PIN_F5 -to pwm_word[3] 141 | set_location_assignment PIN_D1 -to pwm_word[4] 142 | set_location_assignment PIN_E5 -to pwm_word[6] 143 | set_location_assignment PIN_D3 -to pwm_word[5] 144 | set_location_assignment PIN_E15 -to enable 145 | set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 146 | set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 147 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 148 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 149 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 150 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 151 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 152 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 153 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 154 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 155 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 156 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0 157 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 158 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 159 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 160 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 161 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 162 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 163 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 164 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 165 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 166 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 167 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 168 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 169 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 170 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 171 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 172 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0 173 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0 174 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0 175 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 176 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 177 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 178 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0 179 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 180 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 181 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 182 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 183 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 184 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0 185 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to da_clk -section_id auto_signaltap_0 186 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to da_db[0] -section_id auto_signaltap_0 187 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to da_db[1] -section_id auto_signaltap_0 188 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to da_db[2] -section_id auto_signaltap_0 189 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to da_db[3] -section_id auto_signaltap_0 190 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to da_db[4] -section_id auto_signaltap_0 191 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to da_db[5] -section_id auto_signaltap_0 192 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to da_db[6] -section_id auto_signaltap_0 193 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to da_db[7] -section_id auto_signaltap_0 194 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to da_clk -section_id auto_signaltap_0 195 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to da_db[0] -section_id auto_signaltap_0 196 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to da_db[1] -section_id auto_signaltap_0 197 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to da_db[2] -section_id auto_signaltap_0 198 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to da_db[3] -section_id auto_signaltap_0 199 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to da_db[4] -section_id auto_signaltap_0 200 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to da_db[5] -section_id auto_signaltap_0 201 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to da_db[6] -section_id auto_signaltap_0 202 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to da_db[7] -section_id auto_signaltap_0 203 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=9" -section_id auto_signaltap_0 204 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=9" -section_id auto_signaltap_0 205 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=9" -section_id auto_signaltap_0 206 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 207 | set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=52" -section_id auto_signaltap_0 208 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 209 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 210 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 211 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 212 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 213 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 214 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 215 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 216 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 217 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 218 | set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk_50m -section_id auto_signaltap_0 219 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 220 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 221 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 222 | set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 223 | set_global_assignment -name VERILOG_FILE src/waveform_controller.v 224 | set_global_assignment -name VERILOG_FILE src/toplevel.v 225 | set_global_assignment -name QIP_FILE ip/lpm_add_sub/phase_adder.qip 226 | set_global_assignment -name QIP_FILE ip/altpll/pll.qip 227 | set_global_assignment -name QIP_FILE ip/rom_sin/rom_sin.qip 228 | set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp 229 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA-Wave-Generator 2 | 在Cyclone IV（EP4CE6F17C8）上实现的DDS信号发生器。 3 | 4 | 2017年全国大学生电子设计大赛北航第二轮选拔题目。 5 | -------------------------------------------------------------------------------- /ip/altpll/pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /ip/altpll/pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "16.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] 6 | -------------------------------------------------------------------------------- /ip/altpll/pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 16.1.0 Build 196 10/24/2016 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2016 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Intel and sold by Intel or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module pll ( 41 | inclk0, 42 | c0); 43 | 44 | input inclk0; 45 | output c0; 46 | 47 | wire [4:0] sub_wire0; 48 | wire [0:0] sub_wire4 = 1'h0; 49 | wire [0:0] sub_wire1 = sub_wire0[0:0]; 50 | wire c0 = sub_wire1; 51 | wire sub_wire2 = inclk0; 52 | wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; 53 | 54 | altpll altpll_component ( 55 | .inclk (sub_wire3), 56 | .clk (sub_wire0), 57 | .activeclock (), 58 | .areset (1'b0), 59 | .clkbad (), 60 | .clkena ({6{1'b1}}), 61 | .clkloss (), 62 | .clkswitch (1'b0), 63 | .configupdate (1'b0), 64 | .enable0 (), 65 | .enable1 (), 66 | .extclk (), 67 | .extclkena ({4{1'b1}}), 68 | .fbin (1'b1), 69 | .fbmimicbidir (), 70 | .fbout (), 71 | .fref (), 72 | .icdrclk (), 73 | .locked (), 74 | .pfdena (1'b1), 75 | .phasecounterselect ({4{1'b1}}), 76 | .phasedone (), 77 | .phasestep (1'b1), 78 | .phaseupdown (1'b1), 79 | .pllena (1'b1), 80 | .scanaclr (1'b0), 81 | .scanclk (1'b0), 82 | .scanclkena (1'b1), 83 | .scandata (1'b0), 84 | .scandataout (), 85 | .scandone (), 86 | .scanread (1'b0), 87 | .scanwrite (1'b0), 88 | .sclkout0 (), 89 | .sclkout1 (), 90 | .vcooverrange (), 91 | .vcounderrange ()); 92 | defparam 93 | altpll_component.bandwidth_type = "AUTO", 94 | altpll_component.clk0_divide_by = 1, 95 | altpll_component.clk0_duty_cycle = 50, 96 | altpll_component.clk0_multiply_by = 2, 97 | altpll_component.clk0_phase_shift = "0", 98 | altpll_component.compensate_clock = "CLK0", 99 | altpll_component.inclk0_input_frequency = 20000, 100 | altpll_component.intended_device_family = "Cyclone IV E", 101 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 102 | altpll_component.lpm_type = "altpll", 103 | altpll_component.operation_mode = "NORMAL", 104 | altpll_component.pll_type = "AUTO", 105 | altpll_component.port_activeclock = "PORT_UNUSED", 106 | altpll_component.port_areset = "PORT_UNUSED", 107 | altpll_component.port_clkbad0 = "PORT_UNUSED", 108 | altpll_component.port_clkbad1 = "PORT_UNUSED", 109 | altpll_component.port_clkloss = "PORT_UNUSED", 110 | altpll_component.port_clkswitch = "PORT_UNUSED", 111 | altpll_component.port_configupdate = "PORT_UNUSED", 112 | altpll_component.port_fbin = "PORT_UNUSED", 113 | altpll_component.port_inclk0 = "PORT_USED", 114 | altpll_component.port_inclk1 = "PORT_UNUSED", 115 | altpll_component.port_locked = "PORT_UNUSED", 116 | altpll_component.port_pfdena = "PORT_UNUSED", 117 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 118 | altpll_component.port_phasedone = "PORT_UNUSED", 119 | altpll_component.port_phasestep = "PORT_UNUSED", 120 | altpll_component.port_phaseupdown = "PORT_UNUSED", 121 | altpll_component.port_pllena = "PORT_UNUSED", 122 | altpll_component.port_scanaclr = "PORT_UNUSED", 123 | altpll_component.port_scanclk = "PORT_UNUSED", 124 | altpll_component.port_scanclkena = "PORT_UNUSED", 125 | altpll_component.port_scandata = "PORT_UNUSED", 126 | altpll_component.port_scandataout = "PORT_UNUSED", 127 | altpll_component.port_scandone = "PORT_UNUSED", 128 | altpll_component.port_scanread = "PORT_UNUSED", 129 | altpll_component.port_scanwrite = "PORT_UNUSED", 130 | altpll_component.port_clk0 = "PORT_USED", 131 | altpll_component.port_clk1 = "PORT_UNUSED", 132 | altpll_component.port_clk2 = "PORT_UNUSED", 133 | altpll_component.port_clk3 = "PORT_UNUSED", 134 | altpll_component.port_clk4 = "PORT_UNUSED", 135 | altpll_component.port_clk5 = "PORT_UNUSED", 136 | altpll_component.port_clkena0 = "PORT_UNUSED", 137 | altpll_component.port_clkena1 = "PORT_UNUSED", 138 | altpll_component.port_clkena2 = "PORT_UNUSED", 139 | altpll_component.port_clkena3 = "PORT_UNUSED", 140 | altpll_component.port_clkena4 = "PORT_UNUSED", 141 | altpll_component.port_clkena5 = "PORT_UNUSED", 142 | altpll_component.port_extclk0 = "PORT_UNUSED", 143 | altpll_component.port_extclk1 = "PORT_UNUSED", 144 | altpll_component.port_extclk2 = "PORT_UNUSED", 145 | altpll_component.port_extclk3 = "PORT_UNUSED", 146 | altpll_component.width_clock = 5; 147 | 148 | 149 | endmodule 150 | 151 | // ============================================================ 152 | // CNX file retrieval info 153 | // ============================================================ 154 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 155 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 156 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 157 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 158 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 159 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 160 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 161 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 162 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 163 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 164 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 165 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 166 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 168 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 169 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 170 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 171 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 172 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" 173 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 174 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 175 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 176 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 177 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 179 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 180 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 181 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 182 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 183 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 184 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 185 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 186 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 187 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 188 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 189 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 190 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 191 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 192 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 193 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 194 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 195 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 196 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 197 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" 198 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 199 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 200 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 201 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 202 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 203 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 204 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 205 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 206 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 207 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 208 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 209 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 210 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 212 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 213 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 214 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 215 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 216 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 217 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 218 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 219 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 220 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 221 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 222 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 223 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 224 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 225 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 226 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 227 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 228 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 229 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 230 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 231 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 232 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 233 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 234 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 235 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 236 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 237 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 238 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" 239 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 240 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 241 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 242 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 243 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 244 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 245 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 246 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 247 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 248 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 249 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 250 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 251 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 252 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 253 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 254 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 255 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 256 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 257 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 258 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 259 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 260 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 261 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 262 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 263 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 264 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 265 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 266 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 267 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 268 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 269 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 270 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 271 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 272 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 273 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 274 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 275 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 276 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 277 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 278 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 279 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 280 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 281 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 282 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 283 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 284 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 285 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 286 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 287 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 288 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 289 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 290 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 291 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 292 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 293 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 294 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 295 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 296 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 297 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 298 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 299 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE 300 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE 301 | // Retrieval info: LIB_FILE: altera_mf 302 | // Retrieval info: CBX_MODULE_PREFIX: ON 303 | -------------------------------------------------------------------------------- /ip/lpm_add_sub/phase_adder.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB" 2 | set_global_assignment -name IP_TOOL_VERSION "16.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "phase_adder.v"] 5 | -------------------------------------------------------------------------------- /ip/lpm_add_sub/phase_adder.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %LPM_ADD_SUB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: LPM_ADD_SUB 5 | 6 | // ============================================================ 7 | // File Name: phase_adder.v 8 | // Megafunction Name(s): 9 | // LPM_ADD_SUB 10 | // 11 | // Simulation Library Files(s): 12 | // lpm 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 16.1.0 Build 196 10/24/2016 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2016 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Intel and sold by Intel or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module phase_adder ( 41 | clock, 42 | dataa, 43 | datab, 44 | result); 45 | 46 | input clock; 47 | input [27:0] dataa; 48 | input [27:0] datab; 49 | output [27:0] result; 50 | 51 | wire [27:0] sub_wire0; 52 | wire [27:0] result = sub_wire0[27:0]; 53 | 54 | lpm_add_sub LPM_ADD_SUB_component ( 55 | .clock (clock), 56 | .dataa (dataa), 57 | .datab (datab), 58 | .result (sub_wire0) 59 | // synopsys translate_off 60 | , 61 | .aclr (), 62 | .add_sub (), 63 | .cin (), 64 | .clken (), 65 | .cout (), 66 | .overflow () 67 | // synopsys translate_on 68 | ); 69 | defparam 70 | LPM_ADD_SUB_component.lpm_direction = "ADD", 71 | LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", 72 | LPM_ADD_SUB_component.lpm_pipeline = 1, 73 | LPM_ADD_SUB_component.lpm_representation = "UNSIGNED", 74 | LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB", 75 | LPM_ADD_SUB_component.lpm_width = 28; 76 | 77 | 78 | endmodule 79 | 80 | // ============================================================ 81 | // CNX file retrieval info 82 | // ============================================================ 83 | // Retrieval info: PRIVATE: CarryIn NUMERIC "0" 84 | // Retrieval info: PRIVATE: CarryOut NUMERIC "0" 85 | // Retrieval info: PRIVATE: ConstantA NUMERIC "0" 86 | // Retrieval info: PRIVATE: ConstantB NUMERIC "0" 87 | // Retrieval info: PRIVATE: Function NUMERIC "0" 88 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" 90 | // Retrieval info: PRIVATE: Latency NUMERIC "1" 91 | // Retrieval info: PRIVATE: Overflow NUMERIC "0" 92 | // Retrieval info: PRIVATE: RadixA NUMERIC "10" 93 | // Retrieval info: PRIVATE: RadixB NUMERIC "10" 94 | // Retrieval info: PRIVATE: Representation NUMERIC "1" 95 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 96 | // Retrieval info: PRIVATE: ValidCtA NUMERIC "0" 97 | // Retrieval info: PRIVATE: ValidCtB NUMERIC "0" 98 | // Retrieval info: PRIVATE: WhichConstant NUMERIC "0" 99 | // Retrieval info: PRIVATE: aclr NUMERIC "0" 100 | // Retrieval info: PRIVATE: clken NUMERIC "0" 101 | // Retrieval info: PRIVATE: nBit NUMERIC "28" 102 | // Retrieval info: PRIVATE: new_diagram STRING "1" 103 | // Retrieval info: LIBRARY: lpm lpm.lpm_components.all 104 | // Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD" 105 | // Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" 106 | // Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" 107 | // Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" 108 | // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" 109 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "28" 110 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" 111 | // Retrieval info: USED_PORT: dataa 0 0 28 0 INPUT NODEFVAL "dataa[27..0]" 112 | // Retrieval info: USED_PORT: datab 0 0 28 0 INPUT NODEFVAL "datab[27..0]" 113 | // Retrieval info: USED_PORT: result 0 0 28 0 OUTPUT NODEFVAL "result[27..0]" 114 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @dataa 0 0 28 0 dataa 0 0 28 0 116 | // Retrieval info: CONNECT: @datab 0 0 28 0 datab 0 0 28 0 117 | // Retrieval info: CONNECT: result 0 0 28 0 @result 0 0 28 0 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL phase_adder.v TRUE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL phase_adder.inc FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL phase_adder.cmp FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL phase_adder.bsf FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL phase_adder_inst.v FALSE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL phase_adder_bb.v FALSE 124 | // Retrieval info: LIB_FILE: lpm 125 | -------------------------------------------------------------------------------- /ip/rom_sin/rom_sin.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "16.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_sin.v"] 5 | -------------------------------------------------------------------------------- /ip/rom_sin/rom_sin.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: rom_sin.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 16.1.0 Build 196 10/24/2016 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2016 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Intel and sold by Intel or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module rom_sin ( 41 | address, 42 | clock, 43 | q); 44 | 45 | input [8:0] address; 46 | input clock; 47 | output [7:0] q; 48 | `ifndef ALTERA_RESERVED_QIS 49 | // synopsys translate_off 50 | `endif 51 | tri1 clock; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_on 54 | `endif 55 | 56 | wire [7:0] sub_wire0; 57 | wire [7:0] q = sub_wire0[7:0]; 58 | 59 | altsyncram altsyncram_component ( 60 | .address_a (address), 61 | .clock0 (clock), 62 | .q_a (sub_wire0), 63 | .aclr0 (1'b0), 64 | .aclr1 (1'b0), 65 | .address_b (1'b1), 66 | .addressstall_a (1'b0), 67 | .addressstall_b (1'b0), 68 | .byteena_a (1'b1), 69 | .byteena_b (1'b1), 70 | .clock1 (1'b1), 71 | .clocken0 (1'b1), 72 | .clocken1 (1'b1), 73 | .clocken2 (1'b1), 74 | .clocken3 (1'b1), 75 | .data_a ({8{1'b1}}), 76 | .data_b (1'b1), 77 | .eccstatus (), 78 | .q_b (), 79 | .rden_a (1'b1), 80 | .rden_b (1'b1), 81 | .wren_a (1'b0), 82 | .wren_b (1'b0)); 83 | defparam 84 | altsyncram_component.address_aclr_a = "NONE", 85 | altsyncram_component.clock_enable_input_a = "BYPASS", 86 | altsyncram_component.clock_enable_output_a = "BYPASS", 87 | altsyncram_component.init_file = "./waveform/sin512.mif", 88 | altsyncram_component.intended_device_family = "Cyclone IV E", 89 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 90 | altsyncram_component.lpm_type = "altsyncram", 91 | altsyncram_component.numwords_a = 512, 92 | altsyncram_component.operation_mode = "ROM", 93 | altsyncram_component.outdata_aclr_a = "NONE", 94 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 95 | altsyncram_component.widthad_a = 9, 96 | altsyncram_component.width_a = 8, 97 | altsyncram_component.width_byteena_a = 1; 98 | 99 | 100 | endmodule 101 | 102 | // ============================================================ 103 | // CNX file retrieval info 104 | // ============================================================ 105 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 108 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 110 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 111 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 114 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 115 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 116 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 117 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 118 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 119 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 120 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 121 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 122 | // Retrieval info: PRIVATE: MIFfilename STRING "./waveform/sin512.mif" 123 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512" 124 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 125 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 126 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 127 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 128 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 129 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 130 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "9" 131 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 132 | // Retrieval info: PRIVATE: rden NUMERIC "0" 133 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 134 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 137 | // Retrieval info: CONSTANT: INIT_FILE STRING "./waveform/sin512.mif" 138 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 139 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 140 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 141 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" 142 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 143 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 144 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 145 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" 146 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 147 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 148 | // Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]" 149 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 150 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 151 | // Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0 152 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 153 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom_sin.v TRUE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom_sin.inc FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom_sin.cmp FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom_sin.bsf FALSE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom_sin_inst.v FALSE 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom_sin_bb.v FALSE 160 | // Retrieval info: LIB_FILE: altera_mf 161 | -------------------------------------------------------------------------------- /src/toplevel.v: -------------------------------------------------------------------------------- 1 | module toplevel( 2 | input clk_50m, // 50MHz 时钟 3 | input enable, // 使能 4 | input [1:0] wave_word, // 波形控制字，00->正弦 01->三角 10->方波 11->PWM 5 | input [19:0] freq_word, // 频率控制字，fout = 100e6 / (2^28) * (2^freq_word) 6 | input [6:0] pwm_word, // PWM 占空比控制字 7 | output da_clk, 8 | output [7:0] da_db 9 | ); 10 | 11 | /*******************************/ 12 | 13 | wire clk_100m; 14 | 15 | pll pll_instance ( 16 | .inclk0(clk_50m), 17 | .c0(clk_100m) 18 | ); 19 | 20 | /*******************************/ 21 | 22 | wire [27:0] phase; 23 | 24 | phase_adder phase_adder_instance ( 25 | .clock(clk_100m), 26 | .dataa({8'b0,freq_word}), 27 | .datab(phase), 28 | .result(phase) 29 | ); 30 | 31 | /*******************************/ 32 | 33 | wire [7:0] sinewave; 34 | 35 | rom_sin rom_sin_instance ( 36 | .address(phase[27:19]), 37 | .clock(clk_100m), 38 | .q(sinewave) 39 | ); 40 | 41 | /*******************************/ 42 | 43 | waveform_controller waveform_controller_instance ( 44 | .enable(enable), 45 | .clk(clk_100m), 46 | .wave_word(wave_word), 47 | .pwm_word(pwm_word), 48 | .sinewave(sinewave), 49 | .address(phase[27:19]), 50 | .waveform(da_db) 51 | ); 52 | 53 | assign da_clk = clk_100m; 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /src/waveform_controller.v: -------------------------------------------------------------------------------- 1 | module waveform_controller( 2 | input enable, 3 | input clk, 4 | input [1:0] wave_word, 5 | input [6:0] pwm_word, 6 | input [7:0] sinewave, 7 | input [8:0] address, 8 | output reg [7:0] waveform 9 | ); 10 | 11 | always @(posedge clk) begin 12 | case({enable,wave_word}) 13 | 3'b100 : waveform = sinewave; // 正弦 14 | 3'b101 : waveform = {8{address[8]}} ^ address[7:0]; // 三角 15 | 3'b110 : waveform = {address[8], {7{1'b1}}}; // 方波 16 | 3'b111 : waveform = {address<{pwm_word,2'b00}, {7{1'b1}}}; // PWM 17 | default : waveform = {1'b0,{7{1'b1}}}; // enable = 0 时输出为 0 18 | endcase 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /waveform/sin512.mif: -------------------------------------------------------------------------------- 1 | DEPTH = 512; 2 | WIDTH = 8; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | CONTENT 6 | BEGIN 7 | 0000 : 0080; 8 | 0001 : 0081; 9 | 0002 : 0083; 10 | 0003 : 0084; 11 | 0004 : 0086; 12 | 0005 : 0087; 13 | 0006 : 0089; 14 | 0007 : 008A; 15 | 0008 : 008C; 16 | 0009 : 008E; 17 | 000A : 008F; 18 | 000B : 0091; 19 | 000C : 0092; 20 | 000D : 0094; 21 | 000E : 0095; 22 | 000F : 0097; 23 | 0010 : 0098; 24 | 0011 : 009A; 25 | 0012 : 009B; 26 | 0013 : 009D; 27 | 0014 : 009E; 28 | 0015 : 00A0; 29 | 0016 : 00A2; 30 | 0017 : 00A3; 31 | 0018 : 00A5; 32 | 0019 : 00A6; 33 | 001A : 00A7; 34 | 001B : 00A9; 35 | 001C : 00AA; 36 | 001D : 00AC; 37 | 001E : 00AD; 38 | 001F : 00AF; 39 | 0020 : 00B0; 40 | 0021 : 00B2; 41 | 0022 : 00B3; 42 | 0023 : 00B5; 43 | 0024 : 00B6; 44 | 0025 : 00B7; 45 | 0026 : 00B9; 46 | 0027 : 00BA; 47 | 0028 : 00BC; 48 | 0029 : 00BD; 49 | 002A : 00BE; 50 | 002B : 00C0; 51 | 002C : 00C1; 52 | 002D : 00C2; 53 | 002E : 00C4; 54 | 002F : 00C5; 55 | 0030 : 00C6; 56 | 0031 : 00C8; 57 | 0032 : 00C9; 58 | 0033 : 00CA; 59 | 0034 : 00CB; 60 | 0035 : 00CD; 61 | 0036 : 00CE; 62 | 0037 : 00CF; 63 | 0038 : 00D0; 64 | 0039 : 00D2; 65 | 003A : 00D3; 66 | 003B : 00D4; 67 | 003C : 00D5; 68 | 003D : 00D6; 69 | 003E : 00D7; 70 | 003F : 00D9; 71 | 0040 : 00DA; 72 | 0041 : 00DB; 73 | 0042 : 00DC; 74 | 0043 : 00DD; 75 | 0044 : 00DE; 76 | 0045 : 00DF; 77 | 0046 : 00E0; 78 | 0047 : 00E1; 79 | 0048 : 00E2; 80 | 0049 : 00E3; 81 | 004A : 00E4; 82 | 004B : 00E5; 83 | 004C : 00E6; 84 | 004D : 00E7; 85 | 004E : 00E8; 86 | 004F : 00E9; 87 | 0050 : 00EA; 88 | 0051 : 00EA; 89 | 0052 : 00EB; 90 | 0053 : 00EC; 91 | 0054 : 00ED; 92 | 0055 : 00EE; 93 | 0056 : 00EE; 94 | 0057 : 00EF; 95 | 0058 : 00F0; 96 | 0059 : 00F1; 97 | 005A : 00F1; 98 | 005B : 00F2; 99 | 005C : 00F3; 100 | 005D : 00F3; 101 | 005E : 00F4; 102 | 005F : 00F5; 103 | 0060 : 00F5; 104 | 0061 : 00F6; 105 | 0062 : 00F6; 106 | 0063 : 00F7; 107 | 0064 : 00F8; 108 | 0065 : 00F8; 109 | 0066 : 00F9; 110 | 0067 : 00F9; 111 | 0068 : 00FA; 112 | 0069 : 00FA; 113 | 006A : 00FA; 114 | 006B : 00FB; 115 | 006C : 00FB; 116 | 006D : 00FC; 117 | 006E : 00FC; 118 | 006F : 00FC; 119 | 0070 : 00FD; 120 | 0071 : 00FD; 121 | 0072 : 00FD; 122 | 0073 : 00FD; 123 | 0074 : 00FE; 124 | 0075 : 00FE; 125 | 0076 : 00FE; 126 | 0077 : 00FE; 127 | 0078 : 00FE; 128 | 0079 : 00FF; 129 | 007A : 00FF; 130 | 007B : 00FF; 131 | 007C : 00FF; 132 | 007D : 00FF; 133 | 007E : 00FF; 134 | 007F : 00FF; 135 | 0080 : 00FF; 136 | 0081 : 00FF; 137 | 0082 : 00FF; 138 | 0083 : 00FF; 139 | 0084 : 00FF; 140 | 0085 : 00FF; 141 | 0086 : 00FF; 142 | 0087 : 00FF; 143 | 0088 : 00FE; 144 | 0089 : 00FE; 145 | 008A : 00FE; 146 | 008B : 00FE; 147 | 008C : 00FE; 148 | 008D : 00FD; 149 | 008E : 00FD; 150 | 008F : 00FD; 151 | 0090 : 00FD; 152 | 0091 : 00FC; 153 | 0092 : 00FC; 154 | 0093 : 00FC; 155 | 0094 : 00FB; 156 | 0095 : 00FB; 157 | 0096 : 00FA; 158 | 0097 : 00FA; 159 | 0098 : 00FA; 160 | 0099 : 00F9; 161 | 009A : 00F9; 162 | 009B : 00F8; 163 | 009C : 00F8; 164 | 009D : 00F7; 165 | 009E : 00F6; 166 | 009F : 00F6; 167 | 00A0 : 00F5; 168 | 00A1 : 00F5; 169 | 00A2 : 00F4; 170 | 00A3 : 00F3; 171 | 00A4 : 00F3; 172 | 00A5 : 00F2; 173 | 00A6 : 00F1; 174 | 00A7 : 00F1; 175 | 00A8 : 00F0; 176 | 00A9 : 00EF; 177 | 00AA : 00EE; 178 | 00AB : 00EE; 179 | 00AC : 00ED; 180 | 00AD : 00EC; 181 | 00AE : 00EB; 182 | 00AF : 00EA; 183 | 00B0 : 00EA; 184 | 00B1 : 00E9; 185 | 00B2 : 00E8; 186 | 00B3 : 00E7; 187 | 00B4 : 00E6; 188 | 00B5 : 00E5; 189 | 00B6 : 00E4; 190 | 00B7 : 00E3; 191 | 00B8 : 00E2; 192 | 00B9 : 00E1; 193 | 00BA : 00E0; 194 | 00BB : 00DF; 195 | 00BC : 00DE; 196 | 00BD : 00DD; 197 | 00BE : 00DC; 198 | 00BF : 00DB; 199 | 00C0 : 00DA; 200 | 00C1 : 00D9; 201 | 00C2 : 00D7; 202 | 00C3 : 00D6; 203 | 00C4 : 00D5; 204 | 00C5 : 00D4; 205 | 00C6 : 00D3; 206 | 00C7 : 00D2; 207 | 00C8 : 00D0; 208 | 00C9 : 00CF; 209 | 00CA : 00CE; 210 | 00CB : 00CD; 211 | 00CC : 00CB; 212 | 00CD : 00CA; 213 | 00CE : 00C9; 214 | 00CF : 00C8; 215 | 00D0 : 00C6; 216 | 00D1 : 00C5; 217 | 00D2 : 00C4; 218 | 00D3 : 00C2; 219 | 00D4 : 00C1; 220 | 00D5 : 00C0; 221 | 00D6 : 00BE; 222 | 00D7 : 00BD; 223 | 00D8 : 00BC; 224 | 00D9 : 00BA; 225 | 00DA : 00B9; 226 | 00DB : 00B7; 227 | 00DC : 00B6; 228 | 00DD : 00B5; 229 | 00DE : 00B3; 230 | 00DF : 00B2; 231 | 00E0 : 00B0; 232 | 00E1 : 00AF; 233 | 00E2 : 00AD; 234 | 00E3 : 00AC; 235 | 00E4 : 00AA; 236 | 00E5 : 00A9; 237 | 00E6 : 00A7; 238 | 00E7 : 00A6; 239 | 00E8 : 00A5; 240 | 00E9 : 00A3; 241 | 00EA : 00A2; 242 | 00EB : 00A0; 243 | 00EC : 009E; 244 | 00ED : 009D; 245 | 00EE : 009B; 246 | 00EF : 009A; 247 | 00F0 : 0098; 248 | 00F1 : 0097; 249 | 00F2 : 0095; 250 | 00F3 : 0094; 251 | 00F4 : 0092; 252 | 00F5 : 0091; 253 | 00F6 : 008F; 254 | 00F7 : 008E; 255 | 00F8 : 008C; 256 | 00F9 : 008A; 257 | 00FA : 0089; 258 | 00FB : 0087; 259 | 00FC : 0086; 260 | 00FD : 0084; 261 | 00FE : 0083; 262 | 00FF : 0081; 263 | 0100 : 007F; 264 | 0101 : 007E; 265 | 0102 : 007C; 266 | 0103 : 007B; 267 | 0104 : 0079; 268 | 0105 : 0078; 269 | 0106 : 0076; 270 | 0107 : 0075; 271 | 0108 : 0073; 272 | 0109 : 0071; 273 | 010A : 0070; 274 | 010B : 006E; 275 | 010C : 006D; 276 | 010D : 006B; 277 | 010E : 006A; 278 | 010F : 0068; 279 | 0110 : 0067; 280 | 0111 : 0065; 281 | 0112 : 0064; 282 | 0113 : 0062; 283 | 0114 : 0061; 284 | 0115 : 005F; 285 | 0116 : 005D; 286 | 0117 : 005C; 287 | 0118 : 005A; 288 | 0119 : 0059; 289 | 011A : 0058; 290 | 011B : 0056; 291 | 011C : 0055; 292 | 011D : 0053; 293 | 011E : 0052; 294 | 011F : 0050; 295 | 0120 : 004F; 296 | 0121 : 004D; 297 | 0122 : 004C; 298 | 0123 : 004A; 299 | 0124 : 0049; 300 | 0125 : 0048; 301 | 0126 : 0046; 302 | 0127 : 0045; 303 | 0128 : 0043; 304 | 0129 : 0042; 305 | 012A : 0041; 306 | 012B : 003F; 307 | 012C : 003E; 308 | 012D : 003D; 309 | 012E : 003B; 310 | 012F : 003A; 311 | 0130 : 0039; 312 | 0131 : 0037; 313 | 0132 : 0036; 314 | 0133 : 0035; 315 | 0134 : 0034; 316 | 0135 : 0032; 317 | 0136 : 0031; 318 | 0137 : 0030; 319 | 0138 : 002F; 320 | 0139 : 002D; 321 | 013A : 002C; 322 | 013B : 002B; 323 | 013C : 002A; 324 | 013D : 0029; 325 | 013E : 0028; 326 | 013F : 0026; 327 | 0140 : 0025; 328 | 0141 : 0024; 329 | 0142 : 0023; 330 | 0143 : 0022; 331 | 0144 : 0021; 332 | 0145 : 0020; 333 | 0146 : 001F; 334 | 0147 : 001E; 335 | 0148 : 001D; 336 | 0149 : 001C; 337 | 014A : 001B; 338 | 014B : 001A; 339 | 014C : 0019; 340 | 014D : 0018; 341 | 014E : 0017; 342 | 014F : 0016; 343 | 0150 : 0015; 344 | 0151 : 0015; 345 | 0152 : 0014; 346 | 0153 : 0013; 347 | 0154 : 0012; 348 | 0155 : 0011; 349 | 0156 : 0011; 350 | 0157 : 0010; 351 | 0158 : 000F; 352 | 0159 : 000E; 353 | 015A : 000E; 354 | 015B : 000D; 355 | 015C : 000C; 356 | 015D : 000C; 357 | 015E : 000B; 358 | 015F : 000A; 359 | 0160 : 000A; 360 | 0161 : 0009; 361 | 0162 : 0009; 362 | 0163 : 0008; 363 | 0164 : 0007; 364 | 0165 : 0007; 365 | 0166 : 0006; 366 | 0167 : 0006; 367 | 0168 : 0005; 368 | 0169 : 0005; 369 | 016A : 0005; 370 | 016B : 0004; 371 | 016C : 0004; 372 | 016D : 0003; 373 | 016E : 0003; 374 | 016F : 0003; 375 | 0170 : 0002; 376 | 0171 : 0002; 377 | 0172 : 0002; 378 | 0173 : 0002; 379 | 0174 : 0001; 380 | 0175 : 0001; 381 | 0176 : 0001; 382 | 0177 : 0001; 383 | 0178 : 0001; 384 | 0179 : 0000; 385 | 017A : 0000; 386 | 017B : 0000; 387 | 017C : 0000; 388 | 017D : 0000; 389 | 017E : 0000; 390 | 017F : 0000; 391 | 0180 : 0000; 392 | 0181 : 0000; 393 | 0182 : 0000; 394 | 0183 : 0000; 395 | 0184 : 0000; 396 | 0185 : 0000; 397 | 0186 : 0000; 398 | 0187 : 0000; 399 | 0188 : 0001; 400 | 0189 : 0001; 401 | 018A : 0001; 402 | 018B : 0001; 403 | 018C : 0001; 404 | 018D : 0002; 405 | 018E : 0002; 406 | 018F : 0002; 407 | 0190 : 0002; 408 | 0191 : 0003; 409 | 0192 : 0003; 410 | 0193 : 0003; 411 | 0194 : 0004; 412 | 0195 : 0004; 413 | 0196 : 0005; 414 | 0197 : 0005; 415 | 0198 : 0005; 416 | 0199 : 0006; 417 | 019A : 0006; 418 | 019B : 0007; 419 | 019C : 0007; 420 | 019D : 0008; 421 | 019E : 0009; 422 | 019F : 0009; 423 | 01A0 : 000A; 424 | 01A1 : 000A; 425 | 01A2 : 000B; 426 | 01A3 : 000C; 427 | 01A4 : 000C; 428 | 01A5 : 000D; 429 | 01A6 : 000E; 430 | 01A7 : 000E; 431 | 01A8 : 000F; 432 | 01A9 : 0010; 433 | 01AA : 0011; 434 | 01AB : 0011; 435 | 01AC : 0012; 436 | 01AD : 0013; 437 | 01AE : 0014; 438 | 01AF : 0015; 439 | 01B0 : 0015; 440 | 01B1 : 0016; 441 | 01B2 : 0017; 442 | 01B3 : 0018; 443 | 01B4 : 0019; 444 | 01B5 : 001A; 445 | 01B6 : 001B; 446 | 01B7 : 001C; 447 | 01B8 : 001D; 448 | 01B9 : 001E; 449 | 01BA : 001F; 450 | 01BB : 0020; 451 | 01BC : 0021; 452 | 01BD : 0022; 453 | 01BE : 0023; 454 | 01BF : 0024; 455 | 01C0 : 0025; 456 | 01C1 : 0026; 457 | 01C2 : 0028; 458 | 01C3 : 0029; 459 | 01C4 : 002A; 460 | 01C5 : 002B; 461 | 01C6 : 002C; 462 | 01C7 : 002D; 463 | 01C8 : 002F; 464 | 01C9 : 0030; 465 | 01CA : 0031; 466 | 01CB : 0032; 467 | 01CC : 0034; 468 | 01CD : 0035; 469 | 01CE : 0036; 470 | 01CF : 0037; 471 | 01D0 : 0039; 472 | 01D1 : 003A; 473 | 01D2 : 003B; 474 | 01D3 : 003D; 475 | 01D4 : 003E; 476 | 01D5 : 003F; 477 | 01D6 : 0041; 478 | 01D7 : 0042; 479 | 01D8 : 0043; 480 | 01D9 : 0045; 481 | 01DA : 0046; 482 | 01DB : 0048; 483 | 01DC : 0049; 484 | 01DD : 004A; 485 | 01DE : 004C; 486 | 01DF : 004D; 487 | 01E0 : 004F; 488 | 01E1 : 0050; 489 | 01E2 : 0052; 490 | 01E3 : 0053; 491 | 01E4 : 0055; 492 | 01E5 : 0056; 493 | 01E6 : 0058; 494 | 01E7 : 0059; 495 | 01E8 : 005A; 496 | 01E9 : 005C; 497 | 01EA : 005D; 498 | 01EB : 005F; 499 | 01EC : 0061; 500 | 01ED : 0062; 501 | 01EE : 0064; 502 | 01EF : 0065; 503 | 01F0 : 0067; 504 | 01F1 : 0068; 505 | 01F2 : 006A; 506 | 01F3 : 006B; 507 | 01F4 : 006D; 508 | 01F5 : 006E; 509 | 01F6 : 0070; 510 | 01F7 : 0071; 511 | 01F8 : 0073; 512 | 01F9 : 0075; 513 | 01FA : 0076; 514 | 01FB : 0078; 515 | 01FC : 0079; 516 | 01FD : 007B; 517 | 01FE : 007C; 518 | 01FF : 007E; 519 | END ; 520 | --------------------------------------------------------------------------------