├── 04 ├── Clk_tb.v ├── led.hack ├── tangnano4k-com.cst ├── led.asm ├── Not.v ├── Btn.v ├── Nand.v ├── DFFusr.v ├── Or.v ├── And.v ├── Computer_tb.v ├── Led.v ├── Xor.v ├── HalfAdder.v ├── DMux.v ├── Mux.v ├── Bit.v ├── RAM.v ├── ROM.v ├── Clk.v ├── FullAdder.v ├── Makefile ├── Or8Way.v ├── Memory.cmp ├── PC.v ├── Not16.v ├── Computer.v ├── And16.v ├── Memory_tb.v ├── Register.v ├── Mux16.v ├── Memory.v ├── CPU.cmp ├── Add16.v ├── ALUusr.v ├── CPU_tb.v ├── CPU.v └── README.md ├── .vscode ├── settings.json ├── configurationCache.log ├── dryrun.log └── targets.log ├── 00 ├── Xor.cmp ├── tangnano4k.cst ├── Not.v ├── Nand.v ├── Or.v ├── And.v ├── Makefile ├── Xor.v ├── Xor_tb.v └── README.md ├── 01 ├── Or8Way.cmp ├── Mux.cmp ├── tangnano4k-dmux.cst ├── DMux4Way.cmp ├── Not16.cmp ├── Not.v ├── Nand.v ├── And16.cmp ├── Or.v ├── And.v ├── DMux8Way.cmp ├── Mux16.cmp ├── Xor.v ├── DMux.v ├── Mux.v ├── Or8Way_tb.v ├── DMux_tb.v ├── DMux4Way.v ├── Not16_tb.v ├── Mux_tb.v ├── DMux4Way_tb.v ├── DMux8Way.v ├── And16_tb.v ├── Or8Way.v ├── Mux16_tb.v ├── Not16.v ├── Makefile ├── DMux8Way_tb.v ├── And16.v ├── Mux16.v └── README.md ├── 03 ├── tangnano4k-d.cst ├── Bit.cmp ├── Not.v ├── Nand.v ├── Register.cmp ├── DFF.v ├── PC.cmp ├── Or.v ├── And.v ├── RAM.cmp ├── HalfAdder.v ├── Xor.v ├── Mux.v ├── RAM.v ├── Bit.v ├── FullAdder.v ├── Makefile ├── Bit_tb.v ├── Register_tb.v ├── PC_tb.v ├── RAM_tb.v ├── PC.v ├── Mux16.v ├── Register.v ├── README.md └── Add16.v ├── 02 ├── FullAdder.cmp ├── tangnano4k-2i2o.cst ├── Not.v ├── Nand.v ├── Add16.cmp ├── Or.v ├── And.v ├── HalfAdder.v ├── Xor.v ├── Mux.v ├── Makefile ├── FullAdder.v ├── FullAdder_tb.v ├── Or8Way.v ├── Add16_tb.v ├── Not16.v ├── And16.v ├── Mux16.v ├── ALU.cmp ├── Add16.v ├── ALU_tb.v ├── ALU.v └── README.md ├── README.md ├── .gitignore └── LICENSE /04/Clk_tb.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "makefile.extensionOutputFolder": "./.vscode" 3 | } -------------------------------------------------------------------------------- /00/Xor.cmp: -------------------------------------------------------------------------------- 1 | | a | b |out| 2 | | 0 | 0 | 0 | 3 | | 0 | 1 | 1 | 4 | | 1 | 0 | 1 | 5 | | 1 | 1 | 0 | 6 | -------------------------------------------------------------------------------- /00/tangnano4k.cst: -------------------------------------------------------------------------------- 1 | // these are the HDMI pins! 2 | IO_LOC "out" 10; 3 | IO_LOC "a" 15; 4 | IO_LOC "b" 14; 5 | -------------------------------------------------------------------------------- /01/Or8Way.cmp: -------------------------------------------------------------------------------- 1 | |in|out| 2 | |00000000|0| 3 | |11111111|1| 4 | |00010000|1| 5 | |00000001|1| 6 | |00100110|1| 7 | -------------------------------------------------------------------------------- /03/tangnano4k-d.cst: -------------------------------------------------------------------------------- 1 | // these are the HDMI pins! 2 | IO_LOC "out" 10; // red 3 | IO_LOC "in" 15; 4 | IO_LOC "clk" 45; 5 | -------------------------------------------------------------------------------- /04/led.hack: -------------------------------------------------------------------------------- 1 | 0010000000000000 2 | 1111110000010000 3 | 0010000000000001 4 | 1110001100001000 5 | 0000000000000000 6 | 1110101010000111 -------------------------------------------------------------------------------- /01/Mux.cmp: -------------------------------------------------------------------------------- 1 | |a|b|sel|out| 2 | |0|0|0|0| 3 | |0|0|1|0| 4 | |0|1|0|0| 5 | |0|1|1|1| 6 | |1|0|0|1| 7 | |1|0|1|0| 8 | |1|1|0|1| 9 | |1|1|1|1| 10 | -------------------------------------------------------------------------------- /04/tangnano4k-com.cst: -------------------------------------------------------------------------------- 1 | // these are the HDMI pins! 2 | IO_LOC "led" 10; // red 3 | IO_LOC "btn" 15; 4 | IO_LOC "reset" 14; 5 | IO_LOC "clk_in" 45; 6 | -------------------------------------------------------------------------------- /.vscode/configurationCache.log: -------------------------------------------------------------------------------- 1 | {"buildTargets":[],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} -------------------------------------------------------------------------------- /01/tangnano4k-dmux.cst: -------------------------------------------------------------------------------- 1 | // these are the HDMI pins! 2 | IO_LOC "a" 10; // red 3 | IO_LOC "in" 15; 4 | IO_LOC "sel" 14; // right hand default 1 5 | IO_LOC "b" 2; // blue 6 | -------------------------------------------------------------------------------- /02/FullAdder.cmp: -------------------------------------------------------------------------------- 1 | |a|b|c|sum|carry| 2 | |0|0|0|0|0| 3 | |0|0|1|1|0| 4 | |0|1|0|1|0| 5 | |0|1|1|0|1| 6 | |1|0|0|1|0| 7 | |1|0|1|0|1| 8 | |1|1|0|0|1| 9 | |1|1|1|1|1| 10 | -------------------------------------------------------------------------------- /02/tangnano4k-2i2o.cst: -------------------------------------------------------------------------------- 1 | // these are the HDMI pins! 2 | IO_LOC "sum" 10; // red 3 | IO_LOC "a" 15; 4 | IO_LOC "b" 14; // right hand default 1 5 | IO_LOC "carry" 2; // blue 6 | -------------------------------------------------------------------------------- /01/DMux4Way.cmp: -------------------------------------------------------------------------------- 1 | |in|sel|a|b|c|d| 2 | |0|00|0|0|0|0| 3 | |0|01|0|0|0|0| 4 | |0|10|0|0|0|0| 5 | |0|11|0|0|0|0| 6 | |1|00|1|0|0|0| 7 | |1|01|0|1|0|0| 8 | |1|10|0|0|1|0| 9 | |1|11|0|0|0|1| 10 | -------------------------------------------------------------------------------- /01/Not16.cmp: -------------------------------------------------------------------------------- 1 | |in|out| 2 | |0000000000000000|1111111111111111| 3 | |1111111111111111|0000000000000000| 4 | |1010101010101010|0101010101010101| 5 | |0011110011000011|1100001100111100| 6 | |0001001000110100|1110110111001011| 7 | -------------------------------------------------------------------------------- /.vscode/dryrun.log: -------------------------------------------------------------------------------- 1 | make: Entering directory `/Users/buhe/code/gitHub/bugu-computer' 2 | make: Leaving directory `/Users/buhe/code/gitHub/bugu-computer' 3 | 4 | make: *** No targets specified and no makefile found. Stop. 5 | 6 | -------------------------------------------------------------------------------- /03/Bit.cmp: -------------------------------------------------------------------------------- 1 | |time|in|load|out| 2 | | 0|0|0|x| 3 | | 1|0|0|x| 4 | | 1|0|1|x| 5 | | 2|0|1|x| 6 | | 2|1|0|x| 7 | | 3|1|0|x| 8 | | 3|1|1|x| 9 | | 4|1|1|x| 10 | | 4|0|0|x| 11 | | 5|0|0|x| 12 | | 5|1|0|x| 13 | -------------------------------------------------------------------------------- /04/led.asm: -------------------------------------------------------------------------------- 1 | // led.asm 2 | // execute an infinite loop to 3 | // read the button state and write the result 4 | 5 | (LOOP) 6 | @8192 //read BUT 7 | D=M 8 | 9 | @8193 //write LED 10 | M=D 11 | 12 | @LOOP 13 | 0;JMP 14 | -------------------------------------------------------------------------------- /00/Not.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Not gate: 3 | * out = not in 4 | */ 5 | `include "Nand.v" 6 | `default_nettype none 7 | 8 | module Not( 9 | input in, 10 | output out 11 | ); 12 | Nand NAND(.a(in), .b(1'b1), .out(out)); 13 | endmodule 14 | -------------------------------------------------------------------------------- /01/Not.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Not gate: 3 | * out = not in 4 | */ 5 | `include "Nand.v" 6 | `default_nettype none 7 | 8 | module Not( 9 | input in, 10 | output out 11 | ); 12 | Nand NAND(.a(in), .b(1'b1), .out(out)); 13 | endmodule 14 | -------------------------------------------------------------------------------- /02/Not.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Not gate: 3 | * out = not in 4 | */ 5 | `include "Nand.v" 6 | `default_nettype none 7 | 8 | module Not( 9 | input in, 10 | output out 11 | ); 12 | Nand NAND(.a(in), .b(1'b1), .out(out)); 13 | endmodule 14 | -------------------------------------------------------------------------------- /03/Not.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Not gate: 3 | * out = not in 4 | */ 5 | `include "Nand.v" 6 | `default_nettype none 7 | 8 | module Not( 9 | input in, 10 | output out 11 | ); 12 | Nand NAND(.a(in), .b(1'b1), .out(out)); 13 | endmodule 14 | -------------------------------------------------------------------------------- /04/Not.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Not gate: 3 | * out = not in 4 | */ 5 | `include "Nand.v" 6 | `default_nettype none 7 | 8 | module Not( 9 | input in, 10 | output out 11 | ); 12 | Nand NAND(.a(in), .b(1'b1), .out(out)); 13 | endmodule 14 | -------------------------------------------------------------------------------- /04/Btn.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module Btn( 3 | input btn, 4 | output wire[15:0] out 5 | ); 6 | Mux16 MUX161( 7 | .a(16'b0000000000000000), 8 | .b(16'b0000000000000001), 9 | .sel(btn), 10 | .out(out) 11 | ); 12 | endmodule -------------------------------------------------------------------------------- /00/Nand.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Nand gate: 3 | * out = 0 if (a == 1 and b == 1) 4 | * 1 otherwise 5 | * 6 | * This module is implemented using verilog primitives 7 | */ 8 | 9 | `default_nettype none 10 | 11 | module Nand( 12 | input a, 13 | input b, 14 | output out 15 | ); 16 | nand(out,a,b); 17 | endmodule 18 | -------------------------------------------------------------------------------- /01/Nand.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Nand gate: 3 | * out = 0 if (a == 1 and b == 1) 4 | * 1 otherwise 5 | * 6 | * This module is implemented using verilog primitives 7 | */ 8 | 9 | `default_nettype none 10 | 11 | module Nand( 12 | input a, 13 | input b, 14 | output out 15 | ); 16 | nand(out,a,b); 17 | endmodule 18 | -------------------------------------------------------------------------------- /02/Nand.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Nand gate: 3 | * out = 0 if (a == 1 and b == 1) 4 | * 1 otherwise 5 | * 6 | * This module is implemented using verilog primitives 7 | */ 8 | 9 | `default_nettype none 10 | 11 | module Nand( 12 | input a, 13 | input b, 14 | output out 15 | ); 16 | nand(out,a,b); 17 | endmodule 18 | -------------------------------------------------------------------------------- /03/Nand.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Nand gate: 3 | * out = 0 if (a == 1 and b == 1) 4 | * 1 otherwise 5 | * 6 | * This module is implemented using verilog primitives 7 | */ 8 | 9 | `default_nettype none 10 | 11 | module Nand( 12 | input a, 13 | input b, 14 | output out 15 | ); 16 | nand(out,a,b); 17 | endmodule 18 | -------------------------------------------------------------------------------- /04/Nand.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Nand gate: 3 | * out = 0 if (a == 1 and b == 1) 4 | * 1 otherwise 5 | * 6 | * This module is implemented using verilog primitives 7 | */ 8 | 9 | `default_nettype none 10 | 11 | module Nand( 12 | input a, 13 | input b, 14 | output out 15 | ); 16 | nand(out,a,b); 17 | endmodule 18 | -------------------------------------------------------------------------------- /03/Register.cmp: -------------------------------------------------------------------------------- 1 | |time|in|load|out| 2 | | 0| 0|0| x| 3 | | 1| 0|0| 0| 4 | | 1| 0|1| 0| 5 | | 2| 0|1| 0| 6 | | 2|-32123|0| 0| 7 | | 3|-32123|0| 0| 8 | | 3| 11111|0| 0| 9 | | 4| 11111|0| 0| 10 | | 4|-32123|1| 0| 11 | | 5|-32123|1|-32123| 12 | | 5|-32123|1|-32123| 13 | -------------------------------------------------------------------------------- /01/And16.cmp: -------------------------------------------------------------------------------- 1 | |a|b|out| 2 | |0000000000000000|0000000000000000|0000000000000000| 3 | |0000000000000000|1111111111111111|0000000000000000| 4 | |1111111111111111|1111111111111111|1111111111111111| 5 | |1010101010101010|0101010101010101|0000000000000000| 6 | |0011110011000011|0000111111110000|0000110011000000| 7 | |0001001000110100|1001100001110110|0001000000110100| 8 | -------------------------------------------------------------------------------- /02/Add16.cmp: -------------------------------------------------------------------------------- 1 | |a|b|out| 2 | |0000000000000000|0000000000000000|0000000000000000| 3 | |0000000000000000|1111111111111111|1111111111111111| 4 | |1111111111111111|1111111111111111|1111111111111110| 5 | |1010101010101010|0101010101010101|1111111111111111| 6 | |0011110011000011|0000111111110000|0100110010110011| 7 | |0001001000110100|1001100001110110|1010101010101010| 8 | -------------------------------------------------------------------------------- /03/DFF.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Data-Flip-Flop 3 | * out[t+1] = in[t] 4 | * 5 | * This module is implemented using reg-variables in verilog 6 | */ 7 | 8 | `default_nettype none 9 | module DFFusr( 10 | input wire clk, 11 | input wire in, 12 | output reg out 13 | ); 14 | always @(negedge clk) 15 | if (in) out <= 1'b1; 16 | else out <= 1'b0; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /04/DFFusr.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Data-Flip-Flop 3 | * out[t+1] = in[t] 4 | * 5 | * This module is implemented using reg-variables in verilog 6 | */ 7 | 8 | `default_nettype none 9 | module DFFusr( 10 | input wire clk, 11 | input wire in, 12 | output reg out 13 | ); 14 | always @(negedge clk) 15 | if (in) out <= 1'b1; 16 | else out <= 1'b0; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /03/PC.cmp: -------------------------------------------------------------------------------- 1 | |time|in|reset|load|inc|out| 2 | | 0| 0|0|0|0| x| 3 | | 1| 0|0|0|0| 0| 4 | | 1| 0|0|0|1| 0| 5 | | 2| 0|0|0|1| 1| 6 | | 2|-32123|0|0|1| 1| 7 | | 3|-32123|0|0|1| 2| 8 | | 3|-32123|0|1|1| 2| 9 | | 4|-32123|0|1|1|-32123| 10 | | 4|-32123|0|0|1|-32123| 11 | | 5|-32123|0|0|1|-32122| 12 | | 5|-32123|0|0|1|-32122| 13 | -------------------------------------------------------------------------------- /00/Or.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Or gate: 3 | * out = 1 if (a == 1 or b == 1) 4 | * 0 otherwise 5 | */ 6 | `default_nettype none 7 | module Or( 8 | input a, 9 | input b, 10 | output out 11 | ); 12 | wire nota; 13 | wire notb; 14 | Not NOT1(.in(a), .out(nota)); 15 | Not NOT2(.in(b), .out(notb)); 16 | Nand NAND(.a(nota), .b(notb), .out(out)); 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /01/Or.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Or gate: 3 | * out = 1 if (a == 1 or b == 1) 4 | * 0 otherwise 5 | */ 6 | `default_nettype none 7 | module Or( 8 | input a, 9 | input b, 10 | output out 11 | ); 12 | wire nota; 13 | wire notb; 14 | Not NOT1(.in(a), .out(nota)); 15 | Not NOT2(.in(b), .out(notb)); 16 | Nand NAND(.a(nota), .b(notb), .out(out)); 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /02/Or.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Or gate: 3 | * out = 1 if (a == 1 or b == 1) 4 | * 0 otherwise 5 | */ 6 | `default_nettype none 7 | module Or( 8 | input a, 9 | input b, 10 | output out 11 | ); 12 | wire nota; 13 | wire notb; 14 | Not NOT1(.in(a), .out(nota)); 15 | Not NOT2(.in(b), .out(notb)); 16 | Nand NAND(.a(nota), .b(notb), .out(out)); 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /03/Or.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Or gate: 3 | * out = 1 if (a == 1 or b == 1) 4 | * 0 otherwise 5 | */ 6 | `default_nettype none 7 | module Or( 8 | input a, 9 | input b, 10 | output out 11 | ); 12 | wire nota; 13 | wire notb; 14 | Not NOT1(.in(a), .out(nota)); 15 | Not NOT2(.in(b), .out(notb)); 16 | Nand NAND(.a(nota), .b(notb), .out(out)); 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /04/Or.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Or gate: 3 | * out = 1 if (a == 1 or b == 1) 4 | * 0 otherwise 5 | */ 6 | `default_nettype none 7 | module Or( 8 | input a, 9 | input b, 10 | output out 11 | ); 12 | wire nota; 13 | wire notb; 14 | Not NOT1(.in(a), .out(nota)); 15 | Not NOT2(.in(b), .out(notb)); 16 | Nand NAND(.a(nota), .b(notb), .out(out)); 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /00/And.v: -------------------------------------------------------------------------------- 1 | /** 2 | * And gate: 3 | * out = 1 if (a == 1 and b == 1) 4 | * 0 otherwise 5 | */ 6 | 7 | `default_nettype none 8 | 9 | module And( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | wire notaandb; 15 | 16 | // your implementation comes here: 17 | Nand NAND(.a(a), .b(b), .out(notaandb)); 18 | Not NOT(.in(notaandb), .out(out)); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /01/And.v: -------------------------------------------------------------------------------- 1 | /** 2 | * And gate: 3 | * out = 1 if (a == 1 and b == 1) 4 | * 0 otherwise 5 | */ 6 | 7 | `default_nettype none 8 | 9 | module And( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | wire notaandb; 15 | 16 | // your implementation comes here: 17 | Nand NAND(.a(a), .b(b), .out(notaandb)); 18 | Not NOT(.in(notaandb), .out(out)); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /02/And.v: -------------------------------------------------------------------------------- 1 | /** 2 | * And gate: 3 | * out = 1 if (a == 1 and b == 1) 4 | * 0 otherwise 5 | */ 6 | 7 | `default_nettype none 8 | 9 | module And( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | wire notaandb; 15 | 16 | // your implementation comes here: 17 | Nand NAND(.a(a), .b(b), .out(notaandb)); 18 | Not NOT(.in(notaandb), .out(out)); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /03/And.v: -------------------------------------------------------------------------------- 1 | /** 2 | * And gate: 3 | * out = 1 if (a == 1 and b == 1) 4 | * 0 otherwise 5 | */ 6 | 7 | `default_nettype none 8 | 9 | module And( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | wire notaandb; 15 | 16 | // your implementation comes here: 17 | Nand NAND(.a(a), .b(b), .out(notaandb)); 18 | Not NOT(.in(notaandb), .out(out)); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /04/And.v: -------------------------------------------------------------------------------- 1 | /** 2 | * And gate: 3 | * out = 1 if (a == 1 and b == 1) 4 | * 0 otherwise 5 | */ 6 | 7 | `default_nettype none 8 | 9 | module And( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | wire notaandb; 15 | 16 | // your implementation comes here: 17 | Nand NAND(.a(a), .b(b), .out(notaandb)); 18 | Not NOT(.in(notaandb), .out(out)); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /03/RAM.cmp: -------------------------------------------------------------------------------- 1 | |time|in|load|address|out| 2 | | 0| 0|0| 0| x| 3 | | 1| 0|0| 0| x| 4 | | 1| 0|1| 0| x| 5 | | 2| 0|1| 0| 0| 6 | | 2| 4321|0| 0| 0| 7 | | 3| 4321|0| 0| 0| 8 | | 3| 4321|1| 4321| x| 9 | | 4| 4321|1| 4321| 4321| 10 | | 4| 4321|0| 0| 0| 11 | | 5| 4321|0| 0| 0| 12 | | 5| 12345|0| 12345| x| 13 | -------------------------------------------------------------------------------- /00/Makefile: -------------------------------------------------------------------------------- 1 | compile: 2 | iverilog -o Xor_tb.vvp Xor_tb.v 3 | 4 | sim: 5 | vvp Xor_tb.vvp 6 | 7 | diff: 8 | diff Xor.out Xor.cmp 9 | 10 | sym: 11 | yosys -p "read_verilog Xor.v; synth_gowin -json Xor.json" 12 | nextpnr-gowin --json Xor.json --write pnrXor.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k.cst 13 | gowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrXor.json 14 | 15 | flash: 16 | openFPGALoader -b tangnano4k pack.fs -------------------------------------------------------------------------------- /04/Computer_tb.v: -------------------------------------------------------------------------------- 1 | `include "Computer.v" 2 | module Computer_tb(); 3 | 4 | reg clk_in = 0; 5 | reg btn = 1; 6 | wire led; 7 | reg reset = 1; 8 | 9 | Computer 10 | HACK1( 11 | .clk_in(clk_in), 12 | .btn(btn), 13 | .led(led), 14 | .reset(reset) 15 | ); 16 | 17 | always #1 clk_in = ~clk_in; 18 | 19 | initial begin 20 | $dumpfile("Computer_tb.vcd"); 21 | $dumpvars(0, Computer_tb); 22 | #150 23 | $finish; 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /01/DMux8Way.cmp: -------------------------------------------------------------------------------- 1 | |in|sel|a|b|c|d|e|f|g|h| 2 | |0|000|0|0|0|0|0|0|0|0| 3 | |0|001|0|0|0|0|0|0|0|0| 4 | |0|010|0|0|0|0|0|0|0|0| 5 | |0|011|0|0|0|0|0|0|0|0| 6 | |0|100|0|0|0|0|0|0|0|0| 7 | |0|101|0|0|0|0|0|0|0|0| 8 | |0|110|0|0|0|0|0|0|0|0| 9 | |0|111|0|0|0|0|0|0|0|0| 10 | |1|000|1|0|0|0|0|0|0|0| 11 | |1|001|0|1|0|0|0|0|0|0| 12 | |1|010|0|0|1|0|0|0|0|0| 13 | |1|011|0|0|0|1|0|0|0|0| 14 | |1|100|0|0|0|0|1|0|0|0| 15 | |1|101|0|0|0|0|0|1|0|0| 16 | |1|110|0|0|0|0|0|0|1|0| 17 | |1|111|0|0|0|0|0|0|0|1| 18 | -------------------------------------------------------------------------------- /01/Mux16.cmp: -------------------------------------------------------------------------------- 1 | |a|b|sel|out| 2 | |0000000000000000|0000000000000000|0|0000000000000000| 3 | |0000000000000000|0000000000000000|1|0000000000000000| 4 | |0000000000000000|0001001000110100|0|0000000000000000| 5 | |0000000000000000|0001001000110100|1|0001001000110100| 6 | |1001100001110110|0000000000000000|0|1001100001110110| 7 | |1001100001110110|0000000000000000|1|0000000000000000| 8 | |1010101010101010|0101010101010101|0|1010101010101010| 9 | |1010101010101010|0101010101010101|1|0101010101010101| 10 | -------------------------------------------------------------------------------- /04/Led.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module Led( 4 | input clk, 5 | input wire load, 6 | output wire led, 7 | output wire[15:0] out, 8 | input wire[15:0] in 9 | ); 10 | wire prev; 11 | Mux MUX(.a(outLow),.b(in[0]),.sel(load),.out(prev)); 12 | assign led = prev; 13 | wire outLow; 14 | DFFusr DFF1(.clk(clk),.in(prev),.out(outLow)); 15 | Mux16 MUX161( 16 | .a(16'b0000000000000000), 17 | .b(16'b0000000000000001), 18 | .sel(outLow), 19 | .out(out) 20 | ); 21 | 22 | endmodule -------------------------------------------------------------------------------- /04/Xor.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Xor (exclusive or) gate: 3 | * If a<>b out=1 else out=0. 4 | */ 5 | 6 | `default_nettype none 7 | 8 | module Xor( 9 | input wire a, 10 | input wire b, 11 | output wire out 12 | ); 13 | wire nota; //new wire must be declared 14 | wire notb; 15 | Not NOT1(.in(a), .out(nota)); //NOT1 is instance name 16 | Not NOT2(.in(b), .out(notb)); 17 | 18 | wire w1; 19 | wire w2; 20 | And AND1(.a(a),.b(notb),.out(w1)); 21 | And AND2(.a(nota),.b(b),.out(w2)); 22 | 23 | Or OR(.a(w1),.b(w2),.out(out)); 24 | endmodule 25 | -------------------------------------------------------------------------------- /02/HalfAdder.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Computes the sum of two bits. 3 | */ 4 | `include "Xor.v" 5 | `default_nettype none 6 | module HalfAdder( 7 | input wire a, //1-bit input 8 | input wire b, //1-bit inpur 9 | output wire sum, //Right bit of a + b 10 | output wire carry //Lef bit of a + b 11 | ); 12 | 13 | // your implementation comes here: 14 | // Xor(a=a, b=b, out=sum); 15 | // And(a=a, b=b, out=carry); 16 | 17 | Xor XOR(.a(a),.b(b),.out(sum)); 18 | And AND(.a(a),.b(b),.out(carry)); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /03/HalfAdder.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Computes the sum of two bits. 3 | */ 4 | `include "Xor.v" 5 | `default_nettype none 6 | module HalfAdder( 7 | input wire a, //1-bit input 8 | input wire b, //1-bit inpur 9 | output wire sum, //Right bit of a + b 10 | output wire carry //Lef bit of a + b 11 | ); 12 | 13 | // your implementation comes here: 14 | // Xor(a=a, b=b, out=sum); 15 | // And(a=a, b=b, out=carry); 16 | 17 | Xor XOR(.a(a),.b(b),.out(sum)); 18 | And AND(.a(a),.b(b),.out(carry)); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /04/HalfAdder.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Computes the sum of two bits. 3 | */ 4 | `include "Xor.v" 5 | `default_nettype none 6 | module HalfAdder( 7 | input wire a, //1-bit input 8 | input wire b, //1-bit inpur 9 | output wire sum, //Right bit of a + b 10 | output wire carry //Lef bit of a + b 11 | ); 12 | 13 | // your implementation comes here: 14 | // Xor(a=a, b=b, out=sum); 15 | // And(a=a, b=b, out=carry); 16 | 17 | Xor XOR(.a(a),.b(b),.out(sum)); 18 | And AND(.a(a),.b(b),.out(carry)); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /04/DMux.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Demultiplexor: 3 | * {a, b} = {in, 0} if sel == 0 4 | * {0, in} if sel == 1 5 | */ 6 | `default_nettype none 7 | 8 | module DMux( 9 | input wire in, 10 | input wire sel, 11 | output wire a, 12 | output wire b 13 | ); 14 | 15 | // your implementation comes here: 16 | // Not(in=sel, out=notsel); 17 | // And(a=in, b=notsel, out=a); 18 | // And(a=in, b=sel, out=b); 19 | wire notsel; 20 | Not NOT2(.in(sel), .out(notsel)); 21 | And AND1(.a(in),.b(notsel),.out(a)); 22 | And AND2(.a(in),.b(sel),.out(b)); 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /00/Xor.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Xor (exclusive or) gate: 3 | * If a<>b out=1 else out=0. 4 | */ 5 | `include "Not.v" 6 | `include "And.v" 7 | `include "Or.v" 8 | `default_nettype none 9 | 10 | module Xor( 11 | input wire a, 12 | input wire b, 13 | output wire out 14 | ); 15 | wire nota; //new wire must be declared 16 | wire notb; 17 | Not NOT1(.in(a), .out(nota)); //NOT1 is instance name 18 | Not NOT2(.in(b), .out(notb)); 19 | 20 | wire w1; 21 | wire w2; 22 | And AND1(.a(a),.b(notb),.out(w1)); 23 | And AND2(.a(nota),.b(b),.out(w2)); 24 | 25 | Or OR(.a(w1),.b(w2),.out(out)); 26 | endmodule 27 | -------------------------------------------------------------------------------- /01/Xor.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Xor (exclusive or) gate: 3 | * If a<>b out=1 else out=0. 4 | */ 5 | `include "Not.v" 6 | `include "And.v" 7 | `include "Or.v" 8 | `default_nettype none 9 | 10 | module Xor( 11 | input wire a, 12 | input wire b, 13 | output wire out 14 | ); 15 | wire nota; //new wire must be declared 16 | wire notb; 17 | Not NOT1(.in(a), .out(nota)); //NOT1 is instance name 18 | Not NOT2(.in(b), .out(notb)); 19 | 20 | wire w1; 21 | wire w2; 22 | And AND1(.a(a),.b(notb),.out(w1)); 23 | And AND2(.a(nota),.b(b),.out(w2)); 24 | 25 | Or OR(.a(w1),.b(w2),.out(out)); 26 | endmodule 27 | -------------------------------------------------------------------------------- /02/Xor.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Xor (exclusive or) gate: 3 | * If a<>b out=1 else out=0. 4 | */ 5 | `include "Not.v" 6 | `include "And.v" 7 | `include "Or.v" 8 | `default_nettype none 9 | 10 | module Xor( 11 | input wire a, 12 | input wire b, 13 | output wire out 14 | ); 15 | wire nota; //new wire must be declared 16 | wire notb; 17 | Not NOT1(.in(a), .out(nota)); //NOT1 is instance name 18 | Not NOT2(.in(b), .out(notb)); 19 | 20 | wire w1; 21 | wire w2; 22 | And AND1(.a(a),.b(notb),.out(w1)); 23 | And AND2(.a(nota),.b(b),.out(w2)); 24 | 25 | Or OR(.a(w1),.b(w2),.out(out)); 26 | endmodule 27 | -------------------------------------------------------------------------------- /03/Xor.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Xor (exclusive or) gate: 3 | * If a<>b out=1 else out=0. 4 | */ 5 | `include "Not.v" 6 | `include "And.v" 7 | `include "Or.v" 8 | `default_nettype none 9 | 10 | module Xor( 11 | input wire a, 12 | input wire b, 13 | output wire out 14 | ); 15 | wire nota; //new wire must be declared 16 | wire notb; 17 | Not NOT1(.in(a), .out(nota)); //NOT1 is instance name 18 | Not NOT2(.in(b), .out(notb)); 19 | 20 | wire w1; 21 | wire w2; 22 | And AND1(.a(a),.b(notb),.out(w1)); 23 | And AND2(.a(nota),.b(b),.out(w2)); 24 | 25 | Or OR(.a(w1),.b(w2),.out(out)); 26 | endmodule 27 | -------------------------------------------------------------------------------- /03/Mux.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Multiplexor: 3 | * out = a if sel == 0 4 | * b otherwise 5 | */ 6 | `default_nettype none 7 | module Mux( 8 | input a, 9 | input b, 10 | input sel, 11 | output out 12 | ); 13 | // Not(in=sel, out=notsel); 14 | // And(a=a, b=notsel, out=outa); 15 | // And(a=b, b=sel, out=outb); 16 | // Or(a=outa, b=outb, out=out); 17 | 18 | wire notsel; 19 | Not NOT(.in(sel), .out(notsel)); 20 | 21 | wire w1; 22 | wire w2; 23 | And AND1(.a(a),.b(notsel),.out(w1)); 24 | And AND2(.a(b),.b(sel),.out(w2)); 25 | 26 | Or OR(.a(w1),.b(w2),.out(out)); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /04/Mux.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Multiplexor: 3 | * out = a if sel == 0 4 | * b otherwise 5 | */ 6 | `default_nettype none 7 | module Mux( 8 | input a, 9 | input b, 10 | input sel, 11 | output out 12 | ); 13 | // Not(in=sel, out=notsel); 14 | // And(a=a, b=notsel, out=outa); 15 | // And(a=b, b=sel, out=outb); 16 | // Or(a=outa, b=outb, out=out); 17 | 18 | wire notsel; 19 | Not NOT(.in(sel), .out(notsel)); 20 | 21 | wire w1; 22 | wire w2; 23 | And AND1(.a(a),.b(notsel),.out(w1)); 24 | And AND2(.a(b),.b(sel),.out(w2)); 25 | 26 | Or OR(.a(w1),.b(w2),.out(out)); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /04/Bit.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 1-bit register: 3 | * If load[t] == 1 then out[t+1] = in[t] 4 | * else out does not change (out[t+1] = out[t]) 5 | */ 6 | `include "DFFusr.v" 7 | `default_nettype none 8 | module Bit( 9 | input wire clk, 10 | input wire in, 11 | input wire load, 12 | output wire out 13 | ); 14 | 15 | // your implementation comes here: 16 | 17 | // Mux(a=muxb, b=in, sel=load, out=muxo); 18 | // DFF(in=muxo, out=out, out=muxb); 19 | // reg muxb; 20 | wire muxo; 21 | Mux MUX(.a(out),.b(in),.sel(load),.out(muxo)); 22 | DFFusr DFF1(.clk(clk),.in(muxo),.out(out)); 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /02/Mux.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Multiplexor: 3 | * out = a if sel == 0 4 | * b otherwise 5 | */ 6 | `default_nettype none 7 | 8 | module Mux( 9 | input a, 10 | input b, 11 | input sel, 12 | output out 13 | ); 14 | // Not(in=sel, out=notsel); 15 | // And(a=a, b=notsel, out=outa); 16 | // And(a=b, b=sel, out=outb); 17 | // Or(a=outa, b=outb, out=out); 18 | 19 | wire notsel; 20 | Not NOT(.in(sel), .out(notsel)); 21 | 22 | wire w1; 23 | wire w2; 24 | And AND1(.a(a),.b(notsel),.out(w1)); 25 | And AND2(.a(b),.b(sel),.out(w2)); 26 | 27 | Or OR(.a(w1),.b(w2),.out(out)); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /03/RAM.v: -------------------------------------------------------------------------------- 1 | /** 2 | * BlockRAM of iCE40 3 | * implements 2048 words of RAM addressed from 0000 - 2047 4 | * out = M[address] (continuosly assigned using combinatorial logic) 5 | * if (load =i= 1) M[address][t+1] = in[t] (clocked using sequential logic) 6 | */ 7 | 8 | `default_nettype none 9 | module RAM( 10 | input wire clk, 11 | input wire [15:0] address, 12 | input wire [15:0] in, 13 | input wire load, 14 | output wire [15:0] out 15 | ); 16 | 17 | reg [15:0] regRAM [0:2047]; 18 | always @(negedge clk) 19 | if (load) regRAM[address[10:0]] <= in; 20 | 21 | assign out = regRAM[address[10:0]]; 22 | endmodule 23 | -------------------------------------------------------------------------------- /01/DMux.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Demultiplexor: 3 | * {a, b} = {in, 0} if sel == 0 4 | * {0, in} if sel == 1 5 | */ 6 | `include "Not.v" 7 | `include "And.v" 8 | `default_nettype none 9 | 10 | module DMux( 11 | input wire in, 12 | input wire sel, 13 | output wire a, 14 | output wire b 15 | ); 16 | 17 | // your implementation comes here: 18 | // Not(in=sel, out=notsel); 19 | // And(a=in, b=notsel, out=a); 20 | // And(a=in, b=sel, out=b); 21 | wire notsel; 22 | Not NOT2(.in(sel), .out(notsel)); 23 | And AND1(.a(in),.b(notsel),.out(a)); 24 | And AND2(.a(in),.b(sel),.out(b)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /04/RAM.v: -------------------------------------------------------------------------------- 1 | /** 2 | * tangnano4k not support block ram https://github.com/YosysHQ/yosys/wiki/FPGA-family-feature-matrix 3 | * out = M[address] (continuosly assigned using combinatorial logic) 4 | * if (load =i= 1) M[address][t+1] = in[t] (clocked using sequential logic) 5 | */ 6 | 7 | `default_nettype none 8 | module RAM( 9 | input wire clk, 10 | input wire [15:0] address, 11 | input wire [15:0] in, 12 | input wire load, 13 | output wire [15:0] out 14 | ); 15 | 16 | reg [15:0] regRAM [0:10]; 17 | always @(negedge clk) 18 | if (load) regRAM[address[3:0]] <= in; 19 | 20 | assign out = regRAM[address[3:0]]; 21 | endmodule 22 | -------------------------------------------------------------------------------- /03/Bit.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 1-bit register: 3 | * If load[t] == 1 then out[t+1] = in[t] 4 | * else out does not change (out[t+1] = out[t]) 5 | */ 6 | `include "Mux.v" 7 | `include "DFF.v" 8 | `default_nettype none 9 | module Bit( 10 | input wire clk, 11 | input wire in, 12 | input wire load, 13 | output wire out 14 | ); 15 | 16 | // your implementation comes here: 17 | 18 | // Mux(a=muxb, b=in, sel=load, out=muxo); 19 | // DFF(in=muxo, out=out, out=muxb); 20 | // reg muxb; 21 | wire muxo; 22 | Mux MUX(.a(out),.b(in),.sel(load),.out(muxo)); 23 | DFFusr DFF1(.clk(clk),.in(muxo),.out(out)); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /04/ROM.v: -------------------------------------------------------------------------------- 1 | /** 2 | * instruction memory at boot time 3 | * The instruction memory is read only (ROM) and 4 | * preloaded with 2048 x 16bit of Hackcode holding the bootloader. 5 | * 6 | * instruction = ROM[pc] 7 | * tangnano4k not support block ram https://github.com/YosysHQ/yosys/wiki/FPGA-family-feature-matrix 8 | */ 9 | `default_nettype none 10 | 11 | module ROM( 12 | input wire [15:0] pc, 13 | output wire [15:0] instruction 14 | ); 15 | 16 | // ROM file of hack 17 | parameter ROMFILE = "./led.hack"; 18 | 19 | reg [15:0] mem [0:10]; 20 | assign instruction = mem[pc[3:0]]; 21 | 22 | initial begin 23 | $readmemb(ROMFILE,mem); 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /01/Mux.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Multiplexor: 3 | * out = a if sel == 0 4 | * b otherwise 5 | */ 6 | `include "Not.v" 7 | `include "And.v" 8 | `include "Or.v" 9 | `default_nettype none 10 | 11 | module Mux( 12 | input a, 13 | input b, 14 | input sel, 15 | output out 16 | ); 17 | // Not(in=sel, out=notsel); 18 | // And(a=a, b=notsel, out=outa); 19 | // And(a=b, b=sel, out=outb); 20 | // Or(a=outa, b=outb, out=out); 21 | 22 | wire notsel; 23 | Not NOT(.in(sel), .out(notsel)); 24 | 25 | wire w1; 26 | wire w2; 27 | And AND1(.a(a),.b(notsel),.out(w1)); 28 | And AND2(.a(b),.b(sel),.out(w2)); 29 | 30 | Or OR(.a(w1),.b(w2),.out(out)); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /00/Xor_tb.v: -------------------------------------------------------------------------------- 1 | `include "Xor.v" 2 | `default_nettype none 3 | module Xor_tb(); 4 | 5 | integer file; 6 | 7 | reg a = 0; 8 | reg b = 0; 9 | wire out; 10 | 11 | Xor XOR( 12 | .a(a), 13 | .b(b), 14 | .out(out) 15 | ); 16 | 17 | task display; 18 | #1 $fwrite(file, "| %1b | %1b | %1b |\n", a,b,out); 19 | endtask 20 | 21 | initial begin 22 | $dumpfile("Xor_tb.vcd"); 23 | $dumpvars(0, Xor_tb); 24 | file = $fopen("Xor.out","w"); 25 | $fwrite(file, "| a | b |out|\n"); 26 | 27 | a=0;b=0; 28 | display(); 29 | 30 | a=0;b=1; 31 | display(); 32 | 33 | a=1;b=0; 34 | display(); 35 | 36 | a=1;b=1; 37 | display(); 38 | $finish(); 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /01/Or8Way_tb.v: -------------------------------------------------------------------------------- 1 | `include "Or8Way.v" 2 | `default_nettype none 3 | module Or8Way_tb(); 4 | 5 | integer file; 6 | 7 | reg[7:0] in = 8'b00000000; 8 | wire out; 9 | 10 | Or8Way OR8WAY( 11 | .in(in), 12 | .out(out) 13 | ); 14 | 15 | task display; 16 | #1 $fwrite(file, "|%8b|%1b|\n", in,out); 17 | endtask 18 | 19 | initial begin 20 | $dumpfile("Or8Way_tb.vcd"); 21 | $dumpvars(0, Or8Way_tb); 22 | file = $fopen("Or8Way.out","w"); 23 | $fwrite(file, "|in|out|\n"); 24 | 25 | in=8'b00000000; 26 | display(); 27 | 28 | in=8'b11111111; 29 | display(); 30 | 31 | in=8'b00010000; 32 | display(); 33 | 34 | in=8'b00000001; 35 | display(); 36 | 37 | in=8'b00100110; 38 | display(); 39 | $finish(); 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /04/Clk.v: -------------------------------------------------------------------------------- 1 | /** 2 | * input clk_in: clock input 100 MHz 3 | * output clk: clock output 33.333333 MHz 4 | * 5 | * Implementation with 2 bit DFF-counter: 6 | * counter | 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 .... 7 | * clk | 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 .... 8 | */ 9 | 10 | `default_nettype none 11 | 12 | module Clk( 13 | input wire in, //external clock 100Mz 14 | output reg out = 1'b0 //Hack clock 33.333333 MHz 15 | ); 16 | 17 | // your implementation comes here: 18 | parameter NUM_DIV = 5; 19 | reg [15:0] cnt = 16'd0; 20 | // assign out <= 1'b0; 21 | 22 | always @(posedge in) 23 | if(cnt < NUM_DIV) begin 24 | cnt <= cnt + 1'b1; 25 | out <= out; 26 | end 27 | else begin 28 | cnt <= 16'd0; 29 | out <= ~out; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /01/DMux_tb.v: -------------------------------------------------------------------------------- 1 | `include "DMux.v" 2 | `default_nettype none 3 | module DMux_tb(); 4 | 5 | integer file; 6 | 7 | reg in = 1'b0; 8 | reg sel = 1'b0; 9 | wire a; 10 | wire b; 11 | 12 | DMux DMUX( 13 | .in(in), 14 | .sel(sel), 15 | .a(a), 16 | .b(b) 17 | ); 18 | 19 | task display; 20 | #1 $fwrite(file, "|%1b|%1b|%1b|%1b|\n", in,sel,a,b); 21 | endtask 22 | 23 | initial begin 24 | $dumpfile("DMux_tb.vcd"); 25 | $dumpvars(0, DMux_tb); 26 | file = $fopen("DMux.out","w"); 27 | $fwrite(file, "|in|sel|a|b|\n"); 28 | 29 | sel = 1'b0; 30 | display(); 31 | sel = 1'b1; 32 | display(); 33 | 34 | in = 1'b1; 35 | sel = 1'b0; 36 | display(); 37 | sel = 1'b1; 38 | display(); 39 | 40 | $finish(); 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /02/Makefile: -------------------------------------------------------------------------------- 1 | sym-half: 2 | yosys -p "read_verilog HalfAdder.v; synth_gowin -json HalfAdder.json" 3 | nextpnr-gowin --json HalfAdder.json --write pnrHalfAdder.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k-2i2o.cst 4 | gowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrHalfAdder.json 5 | 6 | flash: 7 | openFPGALoader -b tangnano4k pack.fs 8 | 9 | compile-full: 10 | iverilog -o FullAdder_tb.vvp FullAdder_tb.v 11 | 12 | sim-full: 13 | vvp FullAdder_tb.vvp 14 | 15 | diff-full: 16 | diff FullAdder.out FullAdder.cmp 17 | 18 | compile-add16: 19 | iverilog -o Add16_tb.vvp Add16_tb.v 20 | 21 | sim-add16: 22 | vvp Add16_tb.vvp 23 | 24 | diff-add16: 25 | diff Add16.out Add16.cmp 26 | 27 | compile-alu: 28 | iverilog -o ALU_tb.vvp ALU_tb.v 29 | 30 | sim-alu: 31 | vvp ALU_tb.vvp 32 | 33 | diff-alu: 34 | diff ALU.out ALU.cmp -------------------------------------------------------------------------------- /01/DMux4Way.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 4-way demultiplexor: 3 | * {a, b, c, d} = {in, 0, 0, 0} if sel == 00 4 | * {0, in, 0, 0} if sel == 01 5 | * {0, 0, in, 0} if sel == 10 6 | * {0, 0, 0, in} if sel == 11 7 | */ 8 | `include "DMux.v" 9 | module DMux4Way( 10 | input wire in, 11 | input wire [1:0] sel, 12 | output wire a, 13 | output wire b, 14 | output wire c, 15 | output wire d 16 | ); 17 | // your implementation comes here: 18 | // DMux(in=in, sel=sel[1], a=ab, b=cd); 19 | // DMux(in=ab, sel=sel[0], a=a, b=b); 20 | // DMux(in=cd, sel=sel[0], a=c, b=d); 21 | wire ab; 22 | wire cd; 23 | DMux DMUX1(.in(in), .sel(sel[1]), .a(ab), .b(cd)); 24 | DMux DMUX2(.in(ab), .sel(sel[0]), .a(a), .b(b)); 25 | DMux DMUX3(.in(cd), .sel(sel[0]), .a(c), .b(d)); 26 | 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /01/Not16_tb.v: -------------------------------------------------------------------------------- 1 | `include "Not16.v" 2 | `default_nettype none 3 | module Not16_tb(); 4 | 5 | integer file; 6 | 7 | reg[15:0] in = 16'b0000000000000000; 8 | wire[15:0] out; 9 | 10 | Not16 NOT16( 11 | .in(in), 12 | .out(out) 13 | ); 14 | 15 | task display; 16 | #1 $fwrite(file, "|%16b|%16b|\n", in,out); 17 | endtask 18 | 19 | initial begin 20 | $dumpfile("Not16_tb.vcd"); 21 | $dumpvars(0, Not16_tb); 22 | file = $fopen("Not16.out","w"); 23 | $fwrite(file, "|in|out|\n"); 24 | 25 | in=16'b0000000000000000; 26 | display(); 27 | 28 | in=16'b1111111111111111; 29 | display(); 30 | 31 | in=16'b1010101010101010; 32 | display(); 33 | 34 | in=16'b0011110011000011; 35 | display(); 36 | 37 | in=16'b0001001000110100; 38 | display(); 39 | $finish(); 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## bugu computer 2 | 3 | ![Untitled (3)](https://tva1.sinaimg.cn/large/008i3skNgy1gyomf2sm6zj30pm0be74x.jpg) 4 | 5 | 从与或非门开始构建一个计算机的教程（写给软件工程师） 6 | 7 | 作为一个软件工程师一定想过自己构建计算机，自己构建计算机是不是要连电路呀？得益于科技的发展，现在使用 verilog + Fpga 就可以了。本教程采用 verilog + Fpga 来从头构建一个最简单的计算机。 8 | 9 | 指令集采用 nand2tetris 的 Hack 。目标是运行如下汇编，不过也可以运行其他汇编因为是通用计算机。 10 | 11 | ```asm 12 | // led.asm 13 | // execute an infinite loop to 14 | // read the button state and write the result 15 | 16 | (LOOP) 17 | @8193 //read BUT 18 | D=M 19 | 20 | @8192 //write LED 21 | M=D 22 | 23 | @LOOP 24 | 0;JMP 25 | ``` 26 | 27 | 28 | 29 | - [00 准备](00/README.md) 30 | - [01 布尔逻辑](01/README.md) 31 | - [02 算术（ALU）](02/README.md) 32 | - [03 时序电路（存储）](03/README.md) 33 | - [04 组装](04/README.md) 34 | 35 | 参考 36 | 37 | - https://gitlab.com/x653/nand2tetris-fpga 38 | - https://www.nand2tetris.org/ 39 | -------------------------------------------------------------------------------- /02/FullAdder.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Computes the sum of three bits. 3 | */ 4 | `include "HalfAdder.v" 5 | `default_nettype none 6 | 7 | module FullAdder( 8 | input wire a, //1-bit input 9 | input wire b, //1-bit input 10 | input wire c, //1-bit input 11 | output wire sum, //Right bit of a + b + c 12 | output wire carry //Left bit of a + b + c 13 | ); 14 | // your implementation comes here: 15 | 16 | // HalfAdder(a=a, b=b, sum=hsum, carry=hcarry); 17 | // HalfAdder(a=c, b=hsum, sum=sum, carry=hcarry2); 18 | // Or(a=hcarry, b=hcarry2, out=carry); 19 | wire hsum; 20 | wire hcarry; 21 | HalfAdder HalfAdder1(.a(a),.b(b),.sum(hsum),.carry(hcarry)); 22 | wire hcarry2; 23 | HalfAdder HalfAdder2(.a(c),.b(hsum),.sum(sum),.carry(hcarry2)); 24 | Or OR(.a(hcarry),.b(hcarry2),.out(carry)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /03/FullAdder.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Computes the sum of three bits. 3 | */ 4 | `include "HalfAdder.v" 5 | `default_nettype none 6 | 7 | module FullAdder( 8 | input wire a, //1-bit input 9 | input wire b, //1-bit input 10 | input wire c, //1-bit input 11 | output wire sum, //Right bit of a + b + c 12 | output wire carry //Left bit of a + b + c 13 | ); 14 | // your implementation comes here: 15 | 16 | // HalfAdder(a=a, b=b, sum=hsum, carry=hcarry); 17 | // HalfAdder(a=c, b=hsum, sum=sum, carry=hcarry2); 18 | // Or(a=hcarry, b=hcarry2, out=carry); 19 | wire hsum; 20 | wire hcarry; 21 | HalfAdder HalfAdder1(.a(a),.b(b),.sum(hsum),.carry(hcarry)); 22 | wire hcarry2; 23 | HalfAdder HalfAdder2(.a(c),.b(hsum),.sum(sum),.carry(hcarry2)); 24 | Or OR(.a(hcarry),.b(hcarry2),.out(carry)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /04/FullAdder.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Computes the sum of three bits. 3 | */ 4 | `include "HalfAdder.v" 5 | `default_nettype none 6 | 7 | module FullAdder( 8 | input wire a, //1-bit input 9 | input wire b, //1-bit input 10 | input wire c, //1-bit input 11 | output wire sum, //Right bit of a + b + c 12 | output wire carry //Left bit of a + b + c 13 | ); 14 | // your implementation comes here: 15 | 16 | // HalfAdder(a=a, b=b, sum=hsum, carry=hcarry); 17 | // HalfAdder(a=c, b=hsum, sum=sum, carry=hcarry2); 18 | // Or(a=hcarry, b=hcarry2, out=carry); 19 | wire hsum; 20 | wire hcarry; 21 | HalfAdder HalfAdder1(.a(a),.b(b),.sum(hsum),.carry(hcarry)); 22 | wire hcarry2; 23 | HalfAdder HalfAdder2(.a(c),.b(hsum),.sum(sum),.carry(hcarry2)); 24 | Or OR(.a(hcarry),.b(hcarry2),.out(carry)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /04/Makefile: -------------------------------------------------------------------------------- 1 | compile-cpu: 2 | iverilog -o CPU_tb.vvp CPU_tb.v 3 | 4 | sim-cpu: 5 | vvp CPU_tb.vvp 6 | 7 | diff-cpu: 8 | diff CPU.out CPU.cmp 9 | 10 | compile-mem: 11 | iverilog -o Memory_tb.vvp Memory_tb.v 12 | 13 | sim-mem: 14 | vvp Memory_tb.vvp 15 | 16 | diff-mem: 17 | diff Memory.out Memory.cmp 18 | 19 | compile-rom: 20 | iverilog -o ROM.vvp ROM.v 21 | 22 | compile-com: 23 | iverilog -o Computer_tb.vvp Computer_tb.v 24 | 25 | sim-com: 26 | vvp Computer_tb.vvp 27 | 28 | diff-com: 29 | diff Computer.out Computer.cmp 30 | 31 | sym-com: 32 | yosys -p "read_verilog Computer.v; synth_gowin -json Computer.json" 33 | nextpnr-gowin --json Computer.json --write pnrComputer.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k-com.cst 34 | gowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrComputer.json 35 | 36 | flash: 37 | openFPGALoader -b tangnano4k pack.fs -------------------------------------------------------------------------------- /03/Makefile: -------------------------------------------------------------------------------- 1 | sym-d: 2 | yosys -p "read_verilog DFF.v; synth_gowin -json DFF.json" 3 | nextpnr-gowin --json DFF.json --write pnrDFF.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k-d.cst 4 | gowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrDFF.json 5 | 6 | flash: 7 | openFPGALoader -b tangnano4k pack.fs 8 | 9 | compile-d: 10 | iverilog -o DFF.vvp DFF.v 11 | 12 | compile-bit: 13 | iverilog -o Bit_tb.vvp Bit_tb.v 14 | 15 | sim-bit: 16 | vvp Bit_tb.vvp 17 | 18 | diff-bit: 19 | diff Bit.out Bit.cmp 20 | 21 | compile-reg: 22 | iverilog -o Register_tb.vvp Register_tb.v 23 | 24 | sim-reg: 25 | vvp Register_tb.vvp 26 | 27 | diff-reg: 28 | diff Register.out Register.cmp 29 | 30 | compile-pc: 31 | iverilog -o PC_tb.vvp PC_tb.v 32 | 33 | sim-pc: 34 | vvp PC_tb.vvp 35 | 36 | diff-pc: 37 | diff PC.out PC.cmp 38 | 39 | compile-ram: 40 | iverilog -o RAM_tb.vvp RAM_tb.v 41 | 42 | sim-ram: 43 | vvp RAM_tb.vvp 44 | 45 | diff-ram: 46 | diff RAM.out RAM.cmp -------------------------------------------------------------------------------- /01/Mux_tb.v: -------------------------------------------------------------------------------- 1 | `include "Mux.v" 2 | `default_nettype none 3 | module Mux_tb(); 4 | 5 | integer file; 6 | 7 | reg a = 0; 8 | reg b = 0; 9 | reg sel = 0; 10 | wire out; 11 | 12 | Mux MUX( 13 | .a(a), 14 | .b(b), 15 | .sel(sel), 16 | .out(out) 17 | ); 18 | 19 | task display; 20 | #1 $fwrite(file, "|%1b|%1b|%1b|%1b|\n", a,b,sel,out); 21 | endtask 22 | 23 | initial begin 24 | $dumpfile("Mux_tb.vcd"); 25 | $dumpvars(0, Mux_tb); 26 | file = $fopen("Mux.out","w"); 27 | $fwrite(file, "|a|b|sel|out|\n"); 28 | 29 | a=0;b=0;sel=0; 30 | display(); 31 | 32 | a=0;b=0;sel=1; 33 | display(); 34 | 35 | a=0;b=1;sel=0; 36 | display(); 37 | 38 | a=0;b=1;sel=1; 39 | display(); 40 | 41 | a=1;b=0;sel=0; 42 | display(); 43 | 44 | a=1;b=0;sel=1; 45 | display(); 46 | 47 | a=1;b=1;sel=0; 48 | display(); 49 | 50 | a=1;b=1;sel=1; 51 | display(); 52 | $finish(); 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /03/Bit_tb.v: -------------------------------------------------------------------------------- 1 | `include "Bit.v" 2 | module Bit_tb(); 3 | 4 | integer file; 5 | 6 | reg clk = 1; 7 | wire out; 8 | reg load = 0; 9 | reg in=0; 10 | reg[9:0] t = 10'b0; 11 | 12 | Bit BIT( 13 | .clk(clk), 14 | .load(load), 15 | .in(in), 16 | .out(out) 17 | ); 18 | 19 | always #1 clk = ~clk; 20 | 21 | task display; 22 | #1 $fwrite(file, "|%4d|%1b|%1b|%1b|\n", t,in,load,out); 23 | endtask 24 | 25 | initial begin 26 | $dumpfile("Bit_tb.vcd"); 27 | $dumpvars(0, Bit_tb); 28 | file = $fopen("Bit.out","w"); 29 | $fwrite(file, "|time|in|load|out|\n"); 30 | display(); 31 | 32 | t=1;display(); 33 | 34 | in=0;load=1;display(); 35 | 36 | t=2;display(); 37 | 38 | in=1;load=0;display(); 39 | 40 | t=3;display(); 41 | 42 | in=1;load=1;display(); 43 | 44 | t=4;display(); 45 | 46 | in=0;load=0;display(); 47 | 48 | t=5;display(); 49 | 50 | in=1;load=0;display(); 51 | $finish; 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /01/DMux4Way_tb.v: -------------------------------------------------------------------------------- 1 | `include "DMux4Way.v" 2 | `default_nettype none 3 | module DMux4Way_tb(); 4 | 5 | integer file; 6 | 7 | reg in = 1'b0; 8 | reg[1:0] sel = 2'b00; 9 | wire a; 10 | wire b; 11 | wire c; 12 | wire d; 13 | 14 | DMux4Way DMUX4WAY( 15 | .in(in), 16 | .sel(sel), 17 | .a(a), 18 | .b(b), 19 | .c(c), 20 | .d(d) 21 | ); 22 | 23 | task display; 24 | #1 $fwrite(file, "|%1b|%2b|%1b|%1b|%1b|%1b|\n", in,sel,a,b,c,d); 25 | endtask 26 | 27 | initial begin 28 | $dumpfile("DMux4Way_tb.vcd"); 29 | $dumpvars(0, DMux4Way_tb); 30 | file = $fopen("DMux4Way.out","w"); 31 | $fwrite(file, "|in|sel|a|b|c|d|\n"); 32 | 33 | sel = 2'b00; 34 | display(); 35 | sel = 2'b01; 36 | display(); 37 | sel = 2'b10; 38 | display(); 39 | sel = 2'b11; 40 | display(); 41 | in = 1'b1; 42 | sel = 2'b00; 43 | display(); 44 | sel = 2'b01; 45 | display(); 46 | sel = 2'b10; 47 | display(); 48 | sel = 2'b11; 49 | display(); 50 | $finish(); 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /02/FullAdder_tb.v: -------------------------------------------------------------------------------- 1 | `include "FullAdder.v" 2 | `default_nettype none 3 | module FullAdder_tb(); 4 | 5 | integer file; 6 | 7 | reg a = 0; 8 | reg b = 0; 9 | reg c = 0; 10 | wire sum; 11 | wire carry; 12 | 13 | FullAdder FullAdder1( 14 | .a(a), 15 | .b(b), 16 | .c(c), 17 | .sum(sum), 18 | .carry(carry) 19 | ); 20 | 21 | task display; 22 | #1 $fwrite(file, "|%1b|%1b|%1b|%1b|%1b|\n", a,b,c,sum,carry); 23 | endtask 24 | 25 | initial begin 26 | $dumpfile("FullAdder_tb.vcd"); 27 | $dumpvars(0, FullAdder_tb); 28 | file = $fopen("FullAdder.out","w"); 29 | $fwrite(file, "|a|b|c|sum|carry|\n"); 30 | 31 | a=0;b=0;c=0; 32 | display(); 33 | 34 | c=1; 35 | display(); 36 | 37 | b=1;c=0; 38 | display(); 39 | 40 | c=1; 41 | display(); 42 | 43 | a=1;b=0;c=0; 44 | display(); 45 | 46 | c=1; 47 | display(); 48 | 49 | b=1;c=0; 50 | display(); 51 | 52 | c=1; 53 | display(); 54 | $finish(); 55 | end 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /02/Or8Way.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 8-way Or: 3 | * out = (in[0] or in[1] or ... or in[7]) 4 | */ 5 | `default_nettype none 6 | 7 | module Or8Way( 8 | input [7:0] in, 9 | output out 10 | ); 11 | 12 | // Or(a=in[0], b=in[1], out=temp01); 13 | // Or(a=temp01, b=in[2], out=temp012); 14 | // Or(a=temp012, b=in[3], out=temp0123); 15 | // Or(a=temp0123, b=in[4], out=temp01234); 16 | // Or(a=temp01234, b=in[5], out=temp012345); 17 | // Or(a=temp012345, b=in[6], out=temp0123456); 18 | // Or(a=temp0123456, b=in[7], out=out); 19 | wire temp01; 20 | wire temp012; 21 | wire temp0123; 22 | wire temp01234; 23 | wire temp012345; 24 | wire temp0123456; 25 | 26 | Or OR1(.a(in[0]),.b(in[1]),.out(temp01)); 27 | Or OR2(.a(temp01),.b(in[2]),.out(temp012)); 28 | Or OR3(.a(temp012),.b(in[3]),.out(temp0123)); 29 | Or OR4(.a(temp0123),.b(in[4]),.out(temp01234)); 30 | Or OR5(.a(temp01234),.b(in[5]),.out(temp012345)); 31 | Or OR6(.a(temp012345),.b(in[6]),.out(temp0123456)); 32 | Or OR7(.a(temp0123456),.b(in[7]),.out(out)); 33 | endmodule 34 | -------------------------------------------------------------------------------- /04/Or8Way.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 8-way Or: 3 | * out = (in[0] or in[1] or ... or in[7]) 4 | */ 5 | `default_nettype none 6 | 7 | module Or8Way( 8 | input [7:0] in, 9 | output out 10 | ); 11 | 12 | // Or(a=in[0], b=in[1], out=temp01); 13 | // Or(a=temp01, b=in[2], out=temp012); 14 | // Or(a=temp012, b=in[3], out=temp0123); 15 | // Or(a=temp0123, b=in[4], out=temp01234); 16 | // Or(a=temp01234, b=in[5], out=temp012345); 17 | // Or(a=temp012345, b=in[6], out=temp0123456); 18 | // Or(a=temp0123456, b=in[7], out=out); 19 | wire temp01; 20 | wire temp012; 21 | wire temp0123; 22 | wire temp01234; 23 | wire temp012345; 24 | wire temp0123456; 25 | 26 | Or OR1(.a(in[0]),.b(in[1]),.out(temp01)); 27 | Or OR2(.a(temp01),.b(in[2]),.out(temp012)); 28 | Or OR3(.a(temp012),.b(in[3]),.out(temp0123)); 29 | Or OR4(.a(temp0123),.b(in[4]),.out(temp01234)); 30 | Or OR5(.a(temp01234),.b(in[5]),.out(temp012345)); 31 | Or OR6(.a(temp012345),.b(in[6]),.out(temp0123456)); 32 | Or OR7(.a(temp0123456),.b(in[7]),.out(out)); 33 | endmodule 34 | -------------------------------------------------------------------------------- /01/DMux8Way.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 8-way demultiplexor: 3 | * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000 4 | * {0, in, 0, 0, 0, 0, 0, 0} if sel == 001 5 | * etc. 6 | * {0, 0, 0, 0, 0, 0, 0, in} if sel == 111 7 | */ 8 | `include "DMux4Way.v" 9 | module DMux8Way( 10 | input wire in, 11 | input wire [2:0] sel, 12 | output wire a, 13 | output wire b, 14 | output wire c, 15 | output wire d, 16 | output wire e, 17 | output wire f, 18 | output wire g, 19 | output wire h 20 | ); 21 | 22 | // your implementation comes here: 23 | // DMux(in=in, sel=sel[2], a=abcd, b=efgh); 24 | // DMux4Way(in=abcd, sel=sel[0..1], a=a, b=b, c=c, d=d); 25 | // DMux4Way(in=efgh, sel=sel[0..1], a=e, b=f, c=g, d=h); 26 | wire abcd; 27 | wire efgh; 28 | DMux DMUX1(.in(in), .sel(sel[2]), .a(abcd), .b(efgh)); 29 | DMux4Way DMUX2(.in(abcd), .sel(sel[1:0]), .a(a), .b(b),.c(c), .d(d)); 30 | DMux4Way DMUX3(.in(efgh), .sel(sel[1:0]), .a(e), .b(f),.c(g), .d(h)); 31 | 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /01/And16_tb.v: -------------------------------------------------------------------------------- 1 | `include "And16.v" 2 | `default_nettype none 3 | module And16_tb(); 4 | 5 | integer file; 6 | 7 | reg[15:0] a = 16'b0000000000000000; 8 | reg[15:0] b = 16'b0000000000000000; 9 | wire[15:0] out; 10 | 11 | And16 AND16( 12 | .a(a), 13 | .b(b), 14 | .out(out) 15 | ); 16 | 17 | task display; 18 | #1 $fwrite(file, "|%16b|%16b|%16b|\n", a,b,out); 19 | endtask 20 | 21 | initial begin 22 | $dumpfile("And16_tb.vcd"); 23 | $dumpvars(0, And16_tb); 24 | file = $fopen("And16.out","w"); 25 | $fwrite(file, "|a|b|out|\n"); 26 | 27 | a=16'b0000000000000000;b=16'b0000000000000000; 28 | display(); 29 | 30 | a=16'b0000000000000000;b=16'b1111111111111111; 31 | display(); 32 | 33 | a=16'b1111111111111111;b=16'b1111111111111111; 34 | display(); 35 | 36 | a=16'b1010101010101010;b=16'b0101010101010101; 37 | display(); 38 | 39 | a=16'b0011110011000011;b=16'b0000111111110000; 40 | display(); 41 | 42 | a=16'b0001001000110100;b=16'b1001100001110110; 43 | display(); 44 | $finish(); 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /02/Add16_tb.v: -------------------------------------------------------------------------------- 1 | `include "Add16.v" 2 | `default_nettype none 3 | module Add16_tb(); 4 | 5 | integer file; 6 | 7 | reg[15:0] a = 16'b0000000000000000; 8 | reg[15:0] b = 16'b0000000000000000; 9 | wire[15:0] out; 10 | 11 | Add16 ADD16( 12 | .a(a), 13 | .b(b), 14 | .out(out) 15 | ); 16 | 17 | task display; 18 | #1 $fwrite(file, "|%16b|%16b|%16b|\n", a,b,out); 19 | endtask 20 | 21 | initial begin 22 | $dumpfile("Add16_tb.vcd"); 23 | $dumpvars(0, Add16_tb); 24 | file = $fopen("Add16.out","w"); 25 | $fwrite(file, "|a|b|out|\n"); 26 | 27 | a=16'b0000000000000000;b=16'b0000000000000000; 28 | display(); 29 | 30 | a=16'b0000000000000000;b=16'b1111111111111111; 31 | display(); 32 | 33 | a=16'b1111111111111111;b=16'b1111111111111111; 34 | display(); 35 | 36 | a=16'b1010101010101010;b=16'b0101010101010101; 37 | display(); 38 | 39 | a=16'b0011110011000011;b=16'b0000111111110000; 40 | display(); 41 | 42 | a=16'b0001001000110100;b=16'b1001100001110110; 43 | display(); 44 | $finish(); 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /03/Register_tb.v: -------------------------------------------------------------------------------- 1 | `include "Register.v" 2 | module Register_tb(); 3 | 4 | integer file; 5 | 6 | reg clk = 1; 7 | wire signed [15:0] out; 8 | reg load = 0; 9 | reg signed [15:0] in=0; 10 | reg[9:0] t = 10'b0; 11 | 12 | Register REGISTER( 13 | .clk(clk), 14 | .load(load), 15 | .in(in), 16 | .out(out) 17 | ); 18 | 19 | always #1 clk = ~clk; 20 | 21 | task display; 22 | #1 $fwrite(file, "|%4d|%6d|%1b|%6d|\n", t,in,load,out); 23 | endtask 24 | 25 | initial begin 26 | $dumpfile("Register_tb.vcd"); 27 | $dumpvars(0, Register_tb); 28 | file = $fopen("Register.out","w"); 29 | $fwrite(file, "|time|in|load|out|\n"); 30 | display(); 31 | 32 | t=1;display(); 33 | 34 | in=0;load=1;display(); 35 | 36 | t=2;display(); 37 | 38 | in=-32123;load=0;display(); 39 | 40 | t=3;display(); 41 | 42 | in=11111;load=0;display(); 43 | 44 | t=4;display(); 45 | 46 | in=-32123;load=1;display(); 47 | 48 | t=5;display(); 49 | 50 | in=-32123;load=1;display(); 51 | $finish; 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /01/Or8Way.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 8-way Or: 3 | * out = (in[0] or in[1] or ... or in[7]) 4 | */ 5 | `include "Or.v" 6 | `include "Not.v" 7 | `default_nettype none 8 | 9 | module Or8Way( 10 | input [7:0] in, 11 | output out 12 | ); 13 | 14 | // Or(a=in[0], b=in[1], out=temp01); 15 | // Or(a=temp01, b=in[2], out=temp012); 16 | // Or(a=temp012, b=in[3], out=temp0123); 17 | // Or(a=temp0123, b=in[4], out=temp01234); 18 | // Or(a=temp01234, b=in[5], out=temp012345); 19 | // Or(a=temp012345, b=in[6], out=temp0123456); 20 | // Or(a=temp0123456, b=in[7], out=out); 21 | wire temp01; 22 | wire temp012; 23 | wire temp0123; 24 | wire temp01234; 25 | wire temp012345; 26 | wire temp0123456; 27 | 28 | Or OR1(.a(in[0]),.b(in[1]),.out(temp01)); 29 | Or OR2(.a(temp01),.b(in[2]),.out(temp012)); 30 | Or OR3(.a(temp012),.b(in[3]),.out(temp0123)); 31 | Or OR4(.a(temp0123),.b(in[4]),.out(temp01234)); 32 | Or OR5(.a(temp01234),.b(in[5]),.out(temp012345)); 33 | Or OR6(.a(temp012345),.b(in[6]),.out(temp0123456)); 34 | Or OR7(.a(temp0123456),.b(in[7]),.out(out)); 35 | endmodule 36 | -------------------------------------------------------------------------------- /03/PC_tb.v: -------------------------------------------------------------------------------- 1 | `include "PC.v" 2 | module PC_tb(); 3 | 4 | integer file; 5 | 6 | reg clk = 1; 7 | wire signed [15:0] out; 8 | reg reset = 0; 9 | reg load = 0; 10 | reg inc = 0; 11 | reg signed [15:0] in=0; 12 | reg[9:0] t = 10'b0; 13 | 14 | PC PC1( 15 | .clk(clk), 16 | .reset(reset), 17 | .load(load), 18 | .inc(inc), 19 | .in(in), 20 | .out(out) 21 | ); 22 | 23 | always #1 clk = ~clk; 24 | 25 | task display; 26 | #1 $fwrite(file, "|%4d|%6d|%1b|%1b|%1b|%6d|\n", t,in,reset,load,inc,out); 27 | endtask 28 | 29 | initial begin 30 | $dumpfile("PC_tb.vcd"); 31 | $dumpvars(0, PC_tb); 32 | file = $fopen("PC.out","w"); 33 | $fwrite(file, "|time|in|reset|load|inc|out|\n"); 34 | display(); 35 | 36 | t=1;display(); 37 | 38 | inc=1;display(); 39 | 40 | t=2;display(); 41 | 42 | in=-32123;display(); 43 | 44 | t=3;display(); 45 | 46 | load=1;display(); 47 | 48 | t=4;display(); 49 | 50 | load=0;display(); 51 | 52 | t=5;display(); 53 | 54 | display(); 55 | $finish; 56 | end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /03/RAM_tb.v: -------------------------------------------------------------------------------- 1 | `include "RAM.v" 2 | module RAM_tb(); 3 | 4 | integer file; 5 | 6 | reg clk = 1; 7 | wire signed [15:0] out; 8 | reg signed [15:0] address=0; 9 | reg load = 0; 10 | reg signed [15:0] in=0; 11 | reg[9:0] t = 10'b0; 12 | 13 | RAM RAM1( 14 | .clk(clk), 15 | .address(address), 16 | .load(load), 17 | .in(in), 18 | .out(out) 19 | ); 20 | 21 | always #1 clk = ~clk; 22 | 23 | task display; 24 | #1 $fwrite(file, "|%4d|%6d|%1b|%6d|%6d|\n", t,in,load,address,out); 25 | endtask 26 | 27 | initial begin 28 | $dumpfile("RAM_tb.vcd"); 29 | $dumpvars(0, RAM_tb); 30 | file = $fopen("RAM.out","w"); 31 | $fwrite(file, "|time|in|load|address|out|\n"); 32 | display(); 33 | 34 | t=1;display(); 35 | 36 | load=1;display(); 37 | 38 | t=2;display(); 39 | 40 | in=4321;load=0;display(); 41 | 42 | t=3;display(); 43 | 44 | address=4321;load=1;display(); 45 | 46 | t=4;display(); 47 | 48 | address=0;load=0;display(); 49 | 50 | t=5;display(); 51 | 52 | in=12345;address=12345;display(); 53 | $finish; 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /01/Mux16_tb.v: -------------------------------------------------------------------------------- 1 | `include "Mux16.v" 2 | `default_nettype none 3 | module Mux16_tb(); 4 | 5 | integer file; 6 | 7 | reg[15:0] a = 16'b0000000000000000; 8 | reg[15:0] b = 16'b0000000000000000; 9 | reg sel = 0; 10 | wire[15:0] out; 11 | 12 | Mux16 MUX16( 13 | .a(a), 14 | .b(b), 15 | .sel(sel), 16 | .out(out) 17 | ); 18 | 19 | task display; 20 | #1 $fwrite(file, "|%16b|%16b|%1b|%16b|\n", a,b,sel,out); 21 | endtask 22 | 23 | initial begin 24 | $dumpfile("Mux16_tb.vcd"); 25 | $dumpvars(0, Mux16_tb); 26 | file = $fopen("Mux16.out","w"); 27 | $fwrite(file, "|a|b|sel|out|\n"); 28 | 29 | display(); 30 | 31 | sel = 1; 32 | display(); 33 | 34 | a=16'b0000000000000000; 35 | b=16'b0001001000110100; 36 | sel=0; 37 | display(); 38 | 39 | sel = 1; 40 | display(); 41 | 42 | a=16'b1001100001110110; 43 | b=16'b0000000000000000; 44 | sel=0; 45 | display(); 46 | 47 | sel=1; 48 | display(); 49 | 50 | a=16'b1010101010101010; 51 | b=16'b0101010101010101; 52 | sel=0; 53 | display(); 54 | 55 | sel=1; 56 | display(); 57 | $finish(); 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /04/Memory.cmp: -------------------------------------------------------------------------------- 1 | | in |load | address | out | led | btn | 2 | | 12345| 0 |0010000000000000| 1| x | 1 | 3 | | 12345| 0 |0010000000000000| 1| 0 | 1 | 4 | | 1| 1 |0010000000000001| 0| 1 | 1 | 5 | | 1| 1 |0010000000000001| 1| 1 | 1 | 6 | | -1| 1 |0000000000000000| x| 1 | 1 | 7 | | -1| 1 |0000000000000000| -1| 1 | 1 | 8 | | 9999| 0 |0000000000000000| -1| 1 | 1 | 9 | | 9999| 0 |0000000000000000| -1| 1 | 1 | 10 | | 9999| 0 |0000001111101000| x| 1 | 1 | 11 | | 9999| 0 |0000010010110000| x| 1 | 1 | 12 | | 12345| 1 |0000000000000000| -1| 1 | 1 | 13 | | 12345| 1 |0000000000000000| 12345| 1 | 1 | 14 | | 12345| 1 |0010000000000001| 1| 1 | 1 | 15 | | 12345| 1 |0010000000000001| 1| 1 | 1 | 16 | | 2222| 1 |0000001111101000| x| 1 | 1 | 17 | | 2222| 1 |0000001111101000| 2222| 1 | 1 | 18 | | 9999| 0 |0000001111101000| 2222| 1 | 1 | 19 | | 9999| 0 |0000001111101000| 2222| 1 | 1 | 20 | | 9999| 0 |0000000000000000| 12345| 1 | 1 | 21 | | 9999| 0 |0000010010110000| x| 1 | 1 | 22 | | 9999| 0 |0000000000000001| x| 1 | 1 | 23 | | 9999| 0 |0000000000000010| x| 1 | 1 | 24 | -------------------------------------------------------------------------------- /04/PC.v: -------------------------------------------------------------------------------- 1 | /** 2 | * A 16-bit counter with load control bit. 3 | * if (load[t] == 1) out[t+1] = in[t] 4 | * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition) 5 | * else out[t+1] = out[t] 6 | */ 7 | 8 | `default_nettype none 9 | module PC( 10 | input wire clk, 11 | input wire reset, 12 | input wire [15:0] in, 13 | input wire load, 14 | input wire inc, 15 | output wire [15:0] out 16 | ); 17 | // Mux16(a=oldstate, b=op1, sel=inc, out=nextout1); 18 | // Mux16(a=nextout1, b=in, sel=load, out=nextout2); 19 | // Mux16(a=nextout2, b=false, sel=reset, out=nextout3); 20 | // Register(in=nextout3, load=true, out=oldstate, out=out); 21 | // Inc16(in=oldstate, out=op1); 22 | 23 | wire[15:0] nextout1; 24 | wire[15:0] nextout2; 25 | wire[15:0] nextout3; 26 | 27 | wire[15:0] op1; 28 | Mux16 MUX161(.a(oldstate),.b(op1),.sel(inc), .out(nextout1)); 29 | Mux16 MUX162(.a(nextout1),.b(in),.sel(load), .out(nextout2)); 30 | Mux16 MUX163(.a(nextout2),.b(16'b0000000000000000),.sel(reset), .out(nextout3)); 31 | 32 | Register REGISTER1(.in(nextout3),.load(1'b1),.out(out), .clk(clk)); 33 | wire[15:0] oldstate = out; 34 | Add16 ADD161(.a(oldstate),.b(16'b0000000000000001),.out(op1)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /03/PC.v: -------------------------------------------------------------------------------- 1 | /** 2 | * A 16-bit counter with load control bit. 3 | * if (load[t] == 1) out[t+1] = in[t] 4 | * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition) 5 | * else out[t+1] = out[t] 6 | */ 7 | 8 | `default_nettype none 9 | `include "Mux16.v" 10 | `include "Register.v" 11 | `include "Add16.v" 12 | 13 | module PC( 14 | input wire clk, 15 | input wire reset, 16 | input wire [15:0] in, 17 | input wire load, 18 | input wire inc, 19 | output wire [15:0] out 20 | ); 21 | // Mux16(a=oldstate, b=op1, sel=inc, out=nextout1); 22 | // Mux16(a=nextout1, b=in, sel=load, out=nextout2); 23 | // Mux16(a=nextout2, b=false, sel=reset, out=nextout3); 24 | // Register(in=nextout3, load=true, out=oldstate, out=out); 25 | // Inc16(in=oldstate, out=op1); 26 | 27 | wire[15:0] nextout1; 28 | wire[15:0] nextout2; 29 | wire[15:0] nextout3; 30 | 31 | wire[15:0] op1; 32 | Mux16 MUX161(.a(oldstate),.b(op1),.sel(inc), .out(nextout1)); 33 | Mux16 MUX162(.a(nextout1),.b(in),.sel(load), .out(nextout2)); 34 | Mux16 MUX163(.a(nextout2),.b(16'b0000000000000000),.sel(reset), .out(nextout3)); 35 | 36 | Register REGISTER1(.in(nextout3),.load(1'b1),.out(out), .clk(clk)); 37 | wire[15:0] oldstate = out; 38 | Add16 ADD161(.a(oldstate),.b(16'b0000000000000001),.out(op1)); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /02/Not16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit Not: 3 | * for i=0..15: out[i] = not in[i] 4 | */ 5 | `default_nettype none 6 | 7 | module Not16( 8 | input [15:0] in, 9 | output [15:0] out 10 | ); 11 | 12 | // Not(in=in[0], out=out[0]); 13 | // Not(in=in[1], out=out[1]); 14 | // Not(in=in[2], out=out[2]); 15 | // Not(in=in[3], out=out[3]); 16 | // Not(in=in[4], out=out[4]); 17 | // Not(in=in[5], out=out[5]); 18 | // Not(in=in[6], out=out[6]); 19 | // Not(in=in[7], out=out[7]); 20 | // Not(in=in[8], out=out[8]); 21 | // Not(in=in[9], out=out[9]); 22 | // Not(in=in[10], out=out[10]); 23 | // Not(in=in[11], out=out[11]); 24 | // Not(in=in[12], out=out[12]); 25 | // Not(in=in[13], out=out[13]); 26 | // Not(in=in[14], out=out[14]); 27 | // Not(in=in[15], out=out[15]); 28 | 29 | Not NOT1(.in(in[0]), .out(out[0])); 30 | Not NOT2(.in(in[1]), .out(out[1])); 31 | Not NOT3(.in(in[2]), .out(out[2])); 32 | Not NOT4(.in(in[3]), .out(out[3])); 33 | Not NOT5(.in(in[4]), .out(out[4])); 34 | Not NOT6(.in(in[5]), .out(out[5])); 35 | Not NOT7(.in(in[6]), .out(out[6])); 36 | Not NOT8(.in(in[7]), .out(out[7])); 37 | Not NOT9(.in(in[8]), .out(out[8])); 38 | Not NOT10(.in(in[9]), .out(out[9])); 39 | Not NOT11(.in(in[10]), .out(out[10])); 40 | Not NOT12(.in(in[11]), .out(out[11])); 41 | Not NOT13(.in(in[12]), .out(out[12])); 42 | Not NOT14(.in(in[13]), .out(out[13])); 43 | Not NOT15(.in(in[14]), .out(out[14])); 44 | Not NOT16(.in(in[15]), .out(out[15])); 45 | endmodule 46 | -------------------------------------------------------------------------------- /04/Not16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit Not: 3 | * for i=0..15: out[i] = not in[i] 4 | */ 5 | `default_nettype none 6 | 7 | module Not16( 8 | input [15:0] in, 9 | output [15:0] out 10 | ); 11 | 12 | // Not(in=in[0], out=out[0]); 13 | // Not(in=in[1], out=out[1]); 14 | // Not(in=in[2], out=out[2]); 15 | // Not(in=in[3], out=out[3]); 16 | // Not(in=in[4], out=out[4]); 17 | // Not(in=in[5], out=out[5]); 18 | // Not(in=in[6], out=out[6]); 19 | // Not(in=in[7], out=out[7]); 20 | // Not(in=in[8], out=out[8]); 21 | // Not(in=in[9], out=out[9]); 22 | // Not(in=in[10], out=out[10]); 23 | // Not(in=in[11], out=out[11]); 24 | // Not(in=in[12], out=out[12]); 25 | // Not(in=in[13], out=out[13]); 26 | // Not(in=in[14], out=out[14]); 27 | // Not(in=in[15], out=out[15]); 28 | 29 | Not NOT1(.in(in[0]), .out(out[0])); 30 | Not NOT2(.in(in[1]), .out(out[1])); 31 | Not NOT3(.in(in[2]), .out(out[2])); 32 | Not NOT4(.in(in[3]), .out(out[3])); 33 | Not NOT5(.in(in[4]), .out(out[4])); 34 | Not NOT6(.in(in[5]), .out(out[5])); 35 | Not NOT7(.in(in[6]), .out(out[6])); 36 | Not NOT8(.in(in[7]), .out(out[7])); 37 | Not NOT9(.in(in[8]), .out(out[8])); 38 | Not NOT10(.in(in[9]), .out(out[9])); 39 | Not NOT11(.in(in[10]), .out(out[10])); 40 | Not NOT12(.in(in[11]), .out(out[11])); 41 | Not NOT13(.in(in[12]), .out(out[12])); 42 | Not NOT14(.in(in[13]), .out(out[13])); 43 | Not NOT15(.in(in[14]), .out(out[14])); 44 | Not NOT16(.in(in[15]), .out(out[15])); 45 | endmodule 46 | -------------------------------------------------------------------------------- /01/Not16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit Not: 3 | * for i=0..15: out[i] = not in[i] 4 | */ 5 | `include "Not.v" 6 | `default_nettype none 7 | 8 | module Not16( 9 | input [15:0] in, 10 | output [15:0] out 11 | ); 12 | 13 | // Not(in=in[0], out=out[0]); 14 | // Not(in=in[1], out=out[1]); 15 | // Not(in=in[2], out=out[2]); 16 | // Not(in=in[3], out=out[3]); 17 | // Not(in=in[4], out=out[4]); 18 | // Not(in=in[5], out=out[5]); 19 | // Not(in=in[6], out=out[6]); 20 | // Not(in=in[7], out=out[7]); 21 | // Not(in=in[8], out=out[8]); 22 | // Not(in=in[9], out=out[9]); 23 | // Not(in=in[10], out=out[10]); 24 | // Not(in=in[11], out=out[11]); 25 | // Not(in=in[12], out=out[12]); 26 | // Not(in=in[13], out=out[13]); 27 | // Not(in=in[14], out=out[14]); 28 | // Not(in=in[15], out=out[15]); 29 | 30 | Not NOT1(.in(in[0]), .out(out[0])); 31 | Not NOT2(.in(in[1]), .out(out[1])); 32 | Not NOT3(.in(in[2]), .out(out[2])); 33 | Not NOT4(.in(in[3]), .out(out[3])); 34 | Not NOT5(.in(in[4]), .out(out[4])); 35 | Not NOT6(.in(in[5]), .out(out[5])); 36 | Not NOT7(.in(in[6]), .out(out[6])); 37 | Not NOT8(.in(in[7]), .out(out[7])); 38 | Not NOT9(.in(in[8]), .out(out[8])); 39 | Not NOT10(.in(in[9]), .out(out[9])); 40 | Not NOT11(.in(in[10]), .out(out[10])); 41 | Not NOT12(.in(in[11]), .out(out[11])); 42 | Not NOT13(.in(in[12]), .out(out[12])); 43 | Not NOT14(.in(in[13]), .out(out[13])); 44 | Not NOT15(.in(in[14]), .out(out[14])); 45 | Not NOT16(.in(in[15]), .out(out[15])); 46 | endmodule 47 | -------------------------------------------------------------------------------- /01/Makefile: -------------------------------------------------------------------------------- 1 | sym-dmux: 2 | yosys -p "read_verilog DMux.v; synth_gowin -json DMux.json" 3 | nextpnr-gowin --json DMux.json --write pnrDMux.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k-dmux.cst 4 | gowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrDMux.json 5 | 6 | flash: 7 | openFPGALoader -b tangnano4k pack.fs 8 | 9 | compile-mux: 10 | iverilog -o Mux_tb.vvp Mux_tb.v 11 | 12 | sim-mux: 13 | vvp Mux_tb.vvp 14 | 15 | diff-mux: 16 | diff Mux.out Mux.cmp 17 | 18 | compile-and16: 19 | iverilog -o And16_tb.vvp And16_tb.v 20 | 21 | sim-and16: 22 | vvp And16_tb.vvp 23 | 24 | diff-and16: 25 | diff And16.out And16.cmp 26 | 27 | compile-dmux4way: 28 | iverilog -o DMux4Way_tb.vvp DMux4Way_tb.v 29 | 30 | sim-dmux4way: 31 | vvp DMux4Way_tb.vvp 32 | 33 | diff-dmux4way: 34 | diff DMux4Way.out DMux4Way.cmp 35 | 36 | 37 | compile-dmux8way: 38 | iverilog -o DMux8Way_tb.vvp DMux8Way_tb.v 39 | 40 | sim-dmux8way: 41 | vvp DMux8Way_tb.vvp 42 | 43 | diff-dmux8way: 44 | diff DMux8Way.out DMux8Way.cmp 45 | 46 | compile-not16: 47 | iverilog -o Not16_tb.vvp Not16_tb.v 48 | 49 | sim-not16: 50 | vvp Not16_tb.vvp 51 | 52 | diff-not16: 53 | diff Not16.out Not16.cmp 54 | 55 | compile-mux16: 56 | iverilog -o Mux16_tb.vvp Mux16_tb.v 57 | 58 | sim-mux16: 59 | vvp Mux16_tb.vvp 60 | 61 | diff-mux16: 62 | diff Mux16.out Mux16.cmp 63 | 64 | compile-or8way: 65 | iverilog -o Or8Way_tb.vvp Or8Way_tb.v 66 | 67 | sim-or8way: 68 | vvp Or8Way_tb.vvp 69 | 70 | diff-or8way: 71 | diff Or8Way.out Or8Way.cmp -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | 00/Xor_tb.vvp 2 | 00/pack.fs 3 | 00/pnrXor.json 4 | 00/Xor.json 5 | 00/Xor.out 6 | 01/DMux.json 7 | 01/pack.fs 8 | 01/pnrDMux.json 9 | 01/Mux.vvp 10 | 01/Mux_tb.vvp 11 | 01/Mux_tb.vcd 12 | 01/Mux.out 13 | 01/And16.out 14 | 01/And16_tb.vvp 15 | 01/And16_tb.vcd 16 | 01/DMux4Way_tb.vcd 17 | 01/DMux4Way_tb.vvp 18 | 01/DMux4Way.out 19 | 01/DMux_tb.vcd 20 | 01/DMux_tb.vvp 21 | 01/DMux.out 22 | 01/DMux8Way_tb.vcd 23 | 01/DMux8Way_tb.vvp 24 | 01/DMux8Way.out 25 | 01/Not16_tb.vcd 26 | 01/Not16_tb.vvp 27 | 01/Not16.out 28 | 01/Mux16_tb.vcd 29 | 01/Mux16_tb.vvp 30 | 01/Mux16.out 31 | 01/Or8Way.out 32 | 01/Or8Way_tb.vcd 33 | 01/Or8Way_tb.vvp 34 | 02/Add16.out 35 | 02/ALU.out 36 | 02/FullAdder.out 37 | 02/HalfAdder.out 38 | 02/Inc16.out 39 | 03/Bit.out 40 | 03/PC.out 41 | 03/Register.out 42 | 04/CPU.out 43 | 04/Memory.out 44 | 02/HalfAdder.json 45 | 02/pack.fs 46 | 02/pnrHalfAdder.json 47 | 02/FullAdder_tb.vcd 48 | 02/FullAdder_tb.vvp 49 | 02/Add16_tb.vcd 50 | 02/Add16_tb.vvp 51 | 02/ALU.vvp 52 | 02/ALU_tb.vvp 53 | 02/ALU_tb.vcd 54 | 03/DFF.json 55 | 03/DFF.vvp 56 | 03/pack.fs 57 | 03/pnrDFF.json 58 | 03/Bit.vvp 59 | 03/Bit_tb.vcd 60 | 03/Bit_tb.vvp 61 | 03/Register_tb.vcd 62 | 03/Register_tb.vvp 63 | 03/PC.vvp 64 | 03/PC_tb.vcd 65 | 03/PC_tb.vvp 66 | 03/RAM.out 67 | 03/RAM_tb.vvp 68 | 03/RAM_tb.vcd 69 | 04/CPU.vvp 70 | 04/CPU_tb.vvp 71 | 04/CPU_tb.vcd 72 | 04/Memory.vvp 73 | 04/Memory_tb.vcd 74 | 04/Memory_tb.vvp 75 | 04/ROM.vvp 76 | 04/Computer_tb.vvp 77 | 04/Computer_tb.vcd 78 | 04/Computer.json 79 | 04/pnrComputer.json 80 | 04/pack.fs 81 | -------------------------------------------------------------------------------- /01/DMux8Way_tb.v: -------------------------------------------------------------------------------- 1 | `include "DMux8Way.v" 2 | `default_nettype none 3 | module DMux8Way_tb(); 4 | 5 | integer file; 6 | 7 | reg in = 1'b0; 8 | reg[2:0] sel = 3'b000; 9 | wire a; 10 | wire b; 11 | wire c; 12 | wire d; 13 | wire e; 14 | wire f; 15 | wire g; 16 | wire h; 17 | 18 | DMux8Way DMUX8WAY( 19 | .in(in), 20 | .sel(sel), 21 | .a(a), 22 | .b(b), 23 | .c(c), 24 | .d(d), 25 | .e(e), 26 | .f(f), 27 | .g(g), 28 | .h(h) 29 | ); 30 | 31 | task display; 32 | #1 $fwrite(file, "|%1b|%3b|%1b|%1b|%1b|%1b|%1b|%1b|%1b|%1b|\n", in,sel,a,b,c,d,e,f,g,h); 33 | endtask 34 | 35 | initial begin 36 | $dumpfile("DMux8Way_tb.vcd"); 37 | $dumpvars(0, DMux8Way_tb); 38 | file = $fopen("DMux8Way.out","w"); 39 | $fwrite(file, "|in|sel|a|b|c|d|e|f|g|h|\n"); 40 | 41 | sel = 3'b000; 42 | display(); 43 | sel = 3'b001; 44 | display(); 45 | sel = 3'b010; 46 | display(); 47 | sel = 3'b011; 48 | display(); 49 | sel = 3'b100; 50 | display(); 51 | sel = 3'b101; 52 | display(); 53 | sel = 3'b110; 54 | display(); 55 | sel = 3'b111; 56 | display(); 57 | 58 | in = 1'b1; 59 | sel = 3'b000; 60 | display(); 61 | sel = 3'b001; 62 | display(); 63 | sel = 3'b010; 64 | display(); 65 | sel = 3'b011; 66 | display(); 67 | sel = 3'b100; 68 | display(); 69 | sel = 3'b101; 70 | display(); 71 | sel = 3'b110; 72 | display(); 73 | sel = 3'b111; 74 | display(); 75 | $finish(); 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /04/Computer.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `include "Mux16.v" 3 | `include "DMux.v" 4 | `include "Btn.v" 5 | `include "Led.v" 6 | 7 | `include "Not.v" 8 | `include "And.v" 9 | `include "Or.v" 10 | `include "RAM.v" 11 | `include "Register.v" 12 | `include "ALUusr.v" 13 | `include "PC.v" 14 | `include "Not16.v" 15 | `include "And16.v" 16 | `include "Add16.v" 17 | `include "Or8Way.v" 18 | 19 | `include "Memory.v" 20 | `include "CPU.v" 21 | `include "ROM.v" 22 | `include "Clk.v" 23 | module Computer( 24 | input clk_in, // external clock 100 MHz 25 | input btn, // buttons (0 if pressed, 1 if released) 26 | output led, // leds (0 off, 1 on) 27 | input reset 28 | ); 29 | 30 | // ROM32K(address=pc ,out=instruction ); 31 | // CPU(inM=Mout ,instruction=instruction ,reset=reset ,outM=outM ,writeM=writeM ,addressM=addressM ,pc=pc ); 32 | // Memory(in=outM ,load=writeM ,address=addressM ,out=Mout ); 33 | wire clk_out; 34 | Clk CLK( 35 | .in(clk_in), 36 | .out(clk_out) 37 | ); 38 | 39 | wire [15:0] addressM; 40 | wire [15:0] outM; 41 | wire [15:0] instruction; 42 | wire [15:0] pc; 43 | wire [15:0] Mout; 44 | 45 | wire writeM; 46 | 47 | ROM ROM( 48 | .instruction(instruction), 49 | .pc(pc) 50 | ); 51 | CPU CPU( 52 | .clk(clk_out), 53 | .inM(Mout), 54 | .instruction(instruction), 55 | .reset(~reset), 56 | .outM(outM), 57 | .writeM(writeM), 58 | .addressM(addressM), 59 | .pc(pc) 60 | ); 61 | 62 | Memory MEMORY( 63 | .clk(clk_out), 64 | .address(addressM), 65 | .in(outM), 66 | .out(Mout), 67 | .load(writeM), 68 | .btn(btn), 69 | .led(led) 70 | ); 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /02/And16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Adds two 16-bit values. 3 | * The most significant carry bit is ignored. 4 | * out = a + b (16 bit) 5 | */ 6 | 7 | `default_nettype none 8 | module And16( 9 | input wire [15:0] a, 10 | input wire [15:0] b, 11 | output wire [15:0] out 12 | ); 13 | // your implementation comes here: 14 | // And(a=a[0], b=b[0], out=out[0]); 15 | // And(a=a[1], b=b[1], out=out[1]); 16 | // And(a=a[2], b=b[2], out=out[2]); 17 | // And(a=a[3], b=b[3], out=out[3]); 18 | // And(a=a[4], b=b[4], out=out[4]); 19 | // And(a=a[5], b=b[5], out=out[5]); 20 | // And(a=a[6], b=b[6], out=out[6]); 21 | // And(a=a[7], b=b[7], out=out[7]); 22 | // And(a=a[8], b=b[8], out=out[8]); 23 | // And(a=a[9], b=b[9], out=out[9]); 24 | // And(a=a[10], b=b[10], out=out[10]); 25 | // And(a=a[11], b=b[11], out=out[11]); 26 | // And(a=a[12], b=b[12], out=out[12]); 27 | // And(a=a[13], b=b[13], out=out[13]); 28 | // And(a=a[14], b=b[14], out=out[14]); 29 | // And(a=a[15], b=b[15], out=out[15]); 30 | 31 | And AND1(.a(a[0]),.b(b[0]),.out(out[0])); 32 | And AND2(.a(a[1]),.b(b[1]),.out(out[1])); 33 | And AND3(.a(a[2]),.b(b[2]),.out(out[2])); 34 | And AND4(.a(a[3]),.b(b[3]),.out(out[3])); 35 | And AND5(.a(a[4]),.b(b[4]),.out(out[4])); 36 | And AND6(.a(a[5]),.b(b[5]),.out(out[5])); 37 | And AND7(.a(a[6]),.b(b[6]),.out(out[6])); 38 | And AND8(.a(a[7]),.b(b[7]),.out(out[7])); 39 | And AND9(.a(a[8]),.b(b[8]),.out(out[8])); 40 | And AND10(.a(a[9]),.b(b[9]),.out(out[9])); 41 | And AND11(.a(a[10]),.b(b[10]),.out(out[10])); 42 | And AND12(.a(a[11]),.b(b[11]),.out(out[11])); 43 | And AND13(.a(a[12]),.b(b[12]),.out(out[12])); 44 | And AND14(.a(a[13]),.b(b[13]),.out(out[13])); 45 | And AND15(.a(a[14]),.b(b[14]),.out(out[14])); 46 | And AND16(.a(a[15]),.b(b[15]),.out(out[15])); 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /04/And16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Adds two 16-bit values. 3 | * The most significant carry bit is ignored. 4 | * out = a + b (16 bit) 5 | */ 6 | 7 | `default_nettype none 8 | module And16( 9 | input wire [15:0] a, 10 | input wire [15:0] b, 11 | output wire [15:0] out 12 | ); 13 | // your implementation comes here: 14 | // And(a=a[0], b=b[0], out=out[0]); 15 | // And(a=a[1], b=b[1], out=out[1]); 16 | // And(a=a[2], b=b[2], out=out[2]); 17 | // And(a=a[3], b=b[3], out=out[3]); 18 | // And(a=a[4], b=b[4], out=out[4]); 19 | // And(a=a[5], b=b[5], out=out[5]); 20 | // And(a=a[6], b=b[6], out=out[6]); 21 | // And(a=a[7], b=b[7], out=out[7]); 22 | // And(a=a[8], b=b[8], out=out[8]); 23 | // And(a=a[9], b=b[9], out=out[9]); 24 | // And(a=a[10], b=b[10], out=out[10]); 25 | // And(a=a[11], b=b[11], out=out[11]); 26 | // And(a=a[12], b=b[12], out=out[12]); 27 | // And(a=a[13], b=b[13], out=out[13]); 28 | // And(a=a[14], b=b[14], out=out[14]); 29 | // And(a=a[15], b=b[15], out=out[15]); 30 | 31 | And AND1(.a(a[0]),.b(b[0]),.out(out[0])); 32 | And AND2(.a(a[1]),.b(b[1]),.out(out[1])); 33 | And AND3(.a(a[2]),.b(b[2]),.out(out[2])); 34 | And AND4(.a(a[3]),.b(b[3]),.out(out[3])); 35 | And AND5(.a(a[4]),.b(b[4]),.out(out[4])); 36 | And AND6(.a(a[5]),.b(b[5]),.out(out[5])); 37 | And AND7(.a(a[6]),.b(b[6]),.out(out[6])); 38 | And AND8(.a(a[7]),.b(b[7]),.out(out[7])); 39 | And AND9(.a(a[8]),.b(b[8]),.out(out[8])); 40 | And AND10(.a(a[9]),.b(b[9]),.out(out[9])); 41 | And AND11(.a(a[10]),.b(b[10]),.out(out[10])); 42 | And AND12(.a(a[11]),.b(b[11]),.out(out[11])); 43 | And AND13(.a(a[12]),.b(b[12]),.out(out[12])); 44 | And AND14(.a(a[13]),.b(b[13]),.out(out[13])); 45 | And AND15(.a(a[14]),.b(b[14]),.out(out[14])); 46 | And AND16(.a(a[15]),.b(b[15]),.out(out[15])); 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /01/And16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Adds two 16-bit values. 3 | * The most significant carry bit is ignored. 4 | * out = a + b (16 bit) 5 | */ 6 | 7 | `include "Not.v" 8 | `include "And.v" 9 | `default_nettype none 10 | module And16( 11 | input wire [15:0] a, 12 | input wire [15:0] b, 13 | output wire [15:0] out 14 | ); 15 | // your implementation comes here: 16 | // And(a=a[0], b=b[0], out=out[0]); 17 | // And(a=a[1], b=b[1], out=out[1]); 18 | // And(a=a[2], b=b[2], out=out[2]); 19 | // And(a=a[3], b=b[3], out=out[3]); 20 | // And(a=a[4], b=b[4], out=out[4]); 21 | // And(a=a[5], b=b[5], out=out[5]); 22 | // And(a=a[6], b=b[6], out=out[6]); 23 | // And(a=a[7], b=b[7], out=out[7]); 24 | // And(a=a[8], b=b[8], out=out[8]); 25 | // And(a=a[9], b=b[9], out=out[9]); 26 | // And(a=a[10], b=b[10], out=out[10]); 27 | // And(a=a[11], b=b[11], out=out[11]); 28 | // And(a=a[12], b=b[12], out=out[12]); 29 | // And(a=a[13], b=b[13], out=out[13]); 30 | // And(a=a[14], b=b[14], out=out[14]); 31 | // And(a=a[15], b=b[15], out=out[15]); 32 | 33 | And AND1(.a(a[0]),.b(b[0]),.out(out[0])); 34 | And AND2(.a(a[1]),.b(b[1]),.out(out[1])); 35 | And AND3(.a(a[2]),.b(b[2]),.out(out[2])); 36 | And AND4(.a(a[3]),.b(b[3]),.out(out[3])); 37 | And AND5(.a(a[4]),.b(b[4]),.out(out[4])); 38 | And AND6(.a(a[5]),.b(b[5]),.out(out[5])); 39 | And AND7(.a(a[6]),.b(b[6]),.out(out[6])); 40 | And AND8(.a(a[7]),.b(b[7]),.out(out[7])); 41 | And AND9(.a(a[8]),.b(b[8]),.out(out[8])); 42 | And AND10(.a(a[9]),.b(b[9]),.out(out[9])); 43 | And AND11(.a(a[10]),.b(b[10]),.out(out[10])); 44 | And AND12(.a(a[11]),.b(b[11]),.out(out[11])); 45 | And AND13(.a(a[12]),.b(b[12]),.out(out[12])); 46 | And AND14(.a(a[13]),.b(b[13]),.out(out[13])); 47 | And AND15(.a(a[14]),.b(b[14]),.out(out[14])); 48 | And AND16(.a(a[15]),.b(b[15]),.out(out[15])); 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /04/Memory_tb.v: -------------------------------------------------------------------------------- 1 | `include "Mux16.v" 2 | `include "DMux.v" 3 | `include "Btn.v" 4 | `include "Led.v" 5 | 6 | `include "Not.v" 7 | `include "And.v" 8 | `include "Or.v" 9 | `include "DFFusr.v" 10 | `include "RAM.v" 11 | `include "Memory.v" 12 | module Memory_tb(); 13 | 14 | integer file; 15 | reg clk = 1; 16 | reg [15:0] address = 16'h1FFC; 17 | reg load = 1; 18 | wire signed [15:0] out; 19 | reg btn = 1; 20 | wire led; 21 | reg signed [15:0] in= 16'h0000; 22 | 23 | Memory 24 | Memory1( 25 | .address(address), 26 | .load(load), 27 | .in(in), 28 | .led(led), 29 | .btn(btn), 30 | .out(out), 31 | .clk(clk) 32 | ); 33 | 34 | // always #1 address = address+1; 35 | always #1 clk = ~clk; 36 | 37 | task display; 38 | #1 $fwrite(file, "|%6d| %1b |%16b|%6d| %1b | %1b |\n",in,load,address,out,led,btn); 39 | endtask 40 | 41 | initial begin 42 | $dumpfile("Memory_tb.vcd"); 43 | $dumpvars(0, Memory_tb); 44 | file = $fopen("Memory.out","w"); 45 | $fwrite(file, "| in |load | address | out | led | btn |\n"); 46 | in = 12345;load=0;address=16'd8192; 47 | display(); 48 | display(); 49 | 50 | in=1;load=1;address=16'd8193; 51 | display(); 52 | display(); 53 | 54 | in=-1;load=1;address=16'h0000; 55 | display(); 56 | display(); 57 | 58 | in=9999;load=0; 59 | display(); 60 | display(); 61 | 62 | address=16'd1000; 63 | display(); 64 | address=16'd1200; 65 | display(); 66 | 67 | in=12345;load=1;address=16'h0000; 68 | display(); 69 | display(); 70 | 71 | address=16'd8193; 72 | display(); 73 | display(); 74 | 75 | in=2222;load=1;address=16'd1000; 76 | display(); 77 | display(); 78 | 79 | in=9999;load=0; 80 | display(); 81 | display(); 82 | 83 | address=16'h0000; 84 | display(); 85 | address=16'd1200; 86 | display(); 87 | 88 | load=0;address=16'h0001; 89 | display(); 90 | address=16'h0002; 91 | display(); 92 | 93 | 94 | 95 | $finish; 96 | end 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /03/Mux16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit multiplexor: 3 | * for i = 0..15 out[i] = a[i] if sel == 0 4 | * b[i] if sel == 1 5 | */ 6 | `default_nettype none 7 | 8 | module Mux16( 9 | input [15:0] a, 10 | input [15:0] b, 11 | input sel, 12 | output [15:0] out 13 | ); 14 | // your implementation comes here: 15 | 16 | // Mux(a=a[0], b=b[0], sel=sel, out=out[0]); 17 | // Mux(a=a[1], b=b[1], sel=sel, out=out[1]); 18 | // Mux(a=a[2], b=b[2], sel=sel, out=out[2]); 19 | // Mux(a=a[3], b=b[3], sel=sel, out=out[3]); 20 | // Mux(a=a[4], b=b[4], sel=sel, out=out[4]); 21 | // Mux(a=a[5], b=b[5], sel=sel, out=out[5]); 22 | // Mux(a=a[6], b=b[6], sel=sel, out=out[6]); 23 | // Mux(a=a[7], b=b[7], sel=sel, out=out[7]); 24 | // Mux(a=a[8], b=b[8], sel=sel, out=out[8]); 25 | // Mux(a=a[9], b=b[9], sel=sel, out=out[9]); 26 | // Mux(a=a[10], b=b[10], sel=sel, out=out[10]); 27 | // Mux(a=a[11], b=b[11], sel=sel, out=out[11]); 28 | // Mux(a=a[12], b=b[12], sel=sel, out=out[12]); 29 | // Mux(a=a[13], b=b[13], sel=sel, out=out[13]); 30 | // Mux(a=a[14], b=b[14], sel=sel, out=out[14]); 31 | // Mux(a=a[15], b=b[15], sel=sel, out=out[15]); 32 | Mux MUX1(.a(a[0]),.b(b[0]),.sel(sel),.out(out[0])); 33 | Mux MUX2(.a(a[1]),.b(b[1]),.sel(sel),.out(out[1])); 34 | Mux MUX3(.a(a[2]),.b(b[2]),.sel(sel),.out(out[2])); 35 | Mux MUX4(.a(a[3]),.b(b[3]),.sel(sel),.out(out[3])); 36 | Mux MUX5(.a(a[4]),.b(b[4]),.sel(sel),.out(out[4])); 37 | Mux MUX6(.a(a[5]),.b(b[5]),.sel(sel),.out(out[5])); 38 | Mux MUX7(.a(a[6]),.b(b[6]),.sel(sel),.out(out[6])); 39 | Mux MUX8(.a(a[7]),.b(b[7]),.sel(sel),.out(out[7])); 40 | Mux MUX9(.a(a[8]),.b(b[8]),.sel(sel),.out(out[8])); 41 | Mux MUX10(.a(a[9]),.b(b[9]),.sel(sel),.out(out[9])); 42 | Mux MUX11(.a(a[10]),.b(b[10]),.sel(sel),.out(out[10])); 43 | Mux MUX12(.a(a[11]),.b(b[11]),.sel(sel),.out(out[11])); 44 | Mux MUX13(.a(a[12]),.b(b[12]),.sel(sel),.out(out[12])); 45 | Mux MUX14(.a(a[13]),.b(b[13]),.sel(sel),.out(out[13])); 46 | Mux MUX15(.a(a[14]),.b(b[14]),.sel(sel),.out(out[14])); 47 | Mux MUX16(.a(a[15]),.b(b[15]),.sel(sel),.out(out[15])); 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /03/Register.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit register: 3 | * If load[t] == 1 then out[t+1] = in[t] 4 | * else out does not change 5 | */ 6 | `include "Bit.v" 7 | `default_nettype none 8 | 9 | module Register( 10 | input clk, 11 | input [15:0] in, 12 | input load, 13 | output [15:0] out 14 | ); 15 | // Bit(in=in[0], load=load, out=out[0]); 16 | // Bit(in=in[1], load=load, out=out[1]); 17 | // Bit(in=in[2], load=load, out=out[2]); 18 | // Bit(in=in[3], load=load, out=out[3]); 19 | // Bit(in=in[4], load=load, out=out[4]); 20 | // Bit(in=in[5], load=load, out=out[5]); 21 | // Bit(in=in[6], load=load, out=out[6]); 22 | // Bit(in=in[7], load=load, out=out[7]); 23 | // Bit(in=in[8], load=load, out=out[8]); 24 | // Bit(in=in[9], load=load, out=out[9]); 25 | // Bit(in=in[10], load=load, out=out[10]); 26 | // Bit(in=in[11], load=load, out=out[11]); 27 | // Bit(in=in[12], load=load, out=out[12]); 28 | // Bit(in=in[13], load=load, out=out[13]); 29 | // Bit(in=in[14], load=load, out=out[14]); 30 | // Bit(in=in[15], load=load, out=out[15]); 31 | Bit BIT1(.in(in[0]),.load(load),.out(out[0]), .clk(clk)); 32 | Bit BIT2(.in(in[1]),.load(load),.out(out[1]), .clk(clk)); 33 | Bit BIT3(.in(in[2]),.load(load),.out(out[2]), .clk(clk)); 34 | Bit BIT4(.in(in[3]),.load(load),.out(out[3]), .clk(clk)); 35 | Bit BIT5(.in(in[4]),.load(load),.out(out[4]), .clk(clk)); 36 | Bit BIT6(.in(in[5]),.load(load),.out(out[5]), .clk(clk)); 37 | Bit BIT7(.in(in[6]),.load(load),.out(out[6]), .clk(clk)); 38 | Bit BIT8(.in(in[7]),.load(load),.out(out[7]), .clk(clk)); 39 | Bit BIT9(.in(in[8]),.load(load),.out(out[8]), .clk(clk)); 40 | Bit BIT10(.in(in[9]),.load(load),.out(out[9]), .clk(clk)); 41 | Bit BIT11(.in(in[10]),.load(load),.out(out[10]), .clk(clk)); 42 | Bit BIT12(.in(in[11]),.load(load),.out(out[11]), .clk(clk)); 43 | Bit BIT13(.in(in[12]),.load(load),.out(out[12]), .clk(clk)); 44 | Bit BIT14(.in(in[13]),.load(load),.out(out[13]), .clk(clk)); 45 | Bit BIT15(.in(in[14]),.load(load),.out(out[14]), .clk(clk)); 46 | Bit BIT16(.in(in[15]),.load(load),.out(out[15]), .clk(clk)); 47 | 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /04/Register.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit register: 3 | * If load[t] == 1 then out[t+1] = in[t] 4 | * else out does not change 5 | */ 6 | `include "Bit.v" 7 | `default_nettype none 8 | 9 | module Register( 10 | input clk, 11 | input [15:0] in, 12 | input load, 13 | output [15:0] out 14 | ); 15 | // Bit(in=in[0], load=load, out=out[0]); 16 | // Bit(in=in[1], load=load, out=out[1]); 17 | // Bit(in=in[2], load=load, out=out[2]); 18 | // Bit(in=in[3], load=load, out=out[3]); 19 | // Bit(in=in[4], load=load, out=out[4]); 20 | // Bit(in=in[5], load=load, out=out[5]); 21 | // Bit(in=in[6], load=load, out=out[6]); 22 | // Bit(in=in[7], load=load, out=out[7]); 23 | // Bit(in=in[8], load=load, out=out[8]); 24 | // Bit(in=in[9], load=load, out=out[9]); 25 | // Bit(in=in[10], load=load, out=out[10]); 26 | // Bit(in=in[11], load=load, out=out[11]); 27 | // Bit(in=in[12], load=load, out=out[12]); 28 | // Bit(in=in[13], load=load, out=out[13]); 29 | // Bit(in=in[14], load=load, out=out[14]); 30 | // Bit(in=in[15], load=load, out=out[15]); 31 | Bit BIT1(.in(in[0]),.load(load),.out(out[0]), .clk(clk)); 32 | Bit BIT2(.in(in[1]),.load(load),.out(out[1]), .clk(clk)); 33 | Bit BIT3(.in(in[2]),.load(load),.out(out[2]), .clk(clk)); 34 | Bit BIT4(.in(in[3]),.load(load),.out(out[3]), .clk(clk)); 35 | Bit BIT5(.in(in[4]),.load(load),.out(out[4]), .clk(clk)); 36 | Bit BIT6(.in(in[5]),.load(load),.out(out[5]), .clk(clk)); 37 | Bit BIT7(.in(in[6]),.load(load),.out(out[6]), .clk(clk)); 38 | Bit BIT8(.in(in[7]),.load(load),.out(out[7]), .clk(clk)); 39 | Bit BIT9(.in(in[8]),.load(load),.out(out[8]), .clk(clk)); 40 | Bit BIT10(.in(in[9]),.load(load),.out(out[9]), .clk(clk)); 41 | Bit BIT11(.in(in[10]),.load(load),.out(out[10]), .clk(clk)); 42 | Bit BIT12(.in(in[11]),.load(load),.out(out[11]), .clk(clk)); 43 | Bit BIT13(.in(in[12]),.load(load),.out(out[12]), .clk(clk)); 44 | Bit BIT14(.in(in[13]),.load(load),.out(out[13]), .clk(clk)); 45 | Bit BIT15(.in(in[14]),.load(load),.out(out[14]), .clk(clk)); 46 | Bit BIT16(.in(in[15]),.load(load),.out(out[15]), .clk(clk)); 47 | 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /02/Mux16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit multiplexor: 3 | * for i = 0..15 out[i] = a[i] if sel == 0 4 | * b[i] if sel == 1 5 | */ 6 | `default_nettype none 7 | `include "Mux.v" 8 | module Mux16( 9 | input [15:0] a, 10 | input [15:0] b, 11 | input sel, 12 | output [15:0] out 13 | ); 14 | // your implementation comes here: 15 | 16 | // Mux(a=a[0], b=b[0], sel=sel, out=out[0]); 17 | // Mux(a=a[1], b=b[1], sel=sel, out=out[1]); 18 | // Mux(a=a[2], b=b[2], sel=sel, out=out[2]); 19 | // Mux(a=a[3], b=b[3], sel=sel, out=out[3]); 20 | // Mux(a=a[4], b=b[4], sel=sel, out=out[4]); 21 | // Mux(a=a[5], b=b[5], sel=sel, out=out[5]); 22 | // Mux(a=a[6], b=b[6], sel=sel, out=out[6]); 23 | // Mux(a=a[7], b=b[7], sel=sel, out=out[7]); 24 | // Mux(a=a[8], b=b[8], sel=sel, out=out[8]); 25 | // Mux(a=a[9], b=b[9], sel=sel, out=out[9]); 26 | // Mux(a=a[10], b=b[10], sel=sel, out=out[10]); 27 | // Mux(a=a[11], b=b[11], sel=sel, out=out[11]); 28 | // Mux(a=a[12], b=b[12], sel=sel, out=out[12]); 29 | // Mux(a=a[13], b=b[13], sel=sel, out=out[13]); 30 | // Mux(a=a[14], b=b[14], sel=sel, out=out[14]); 31 | // Mux(a=a[15], b=b[15], sel=sel, out=out[15]); 32 | Mux MUX1(.a(a[0]),.b(b[0]),.sel(sel),.out(out[0])); 33 | Mux MUX2(.a(a[1]),.b(b[1]),.sel(sel),.out(out[1])); 34 | Mux MUX3(.a(a[2]),.b(b[2]),.sel(sel),.out(out[2])); 35 | Mux MUX4(.a(a[3]),.b(b[3]),.sel(sel),.out(out[3])); 36 | Mux MUX5(.a(a[4]),.b(b[4]),.sel(sel),.out(out[4])); 37 | Mux MUX6(.a(a[5]),.b(b[5]),.sel(sel),.out(out[5])); 38 | Mux MUX7(.a(a[6]),.b(b[6]),.sel(sel),.out(out[6])); 39 | Mux MUX8(.a(a[7]),.b(b[7]),.sel(sel),.out(out[7])); 40 | Mux MUX9(.a(a[8]),.b(b[8]),.sel(sel),.out(out[8])); 41 | Mux MUX10(.a(a[9]),.b(b[9]),.sel(sel),.out(out[9])); 42 | Mux MUX11(.a(a[10]),.b(b[10]),.sel(sel),.out(out[10])); 43 | Mux MUX12(.a(a[11]),.b(b[11]),.sel(sel),.out(out[11])); 44 | Mux MUX13(.a(a[12]),.b(b[12]),.sel(sel),.out(out[12])); 45 | Mux MUX14(.a(a[13]),.b(b[13]),.sel(sel),.out(out[13])); 46 | Mux MUX15(.a(a[14]),.b(b[14]),.sel(sel),.out(out[14])); 47 | Mux MUX16(.a(a[15]),.b(b[15]),.sel(sel),.out(out[15])); 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /04/Mux16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit multiplexor: 3 | * for i = 0..15 out[i] = a[i] if sel == 0 4 | * b[i] if sel == 1 5 | */ 6 | `default_nettype none 7 | `include "Mux.v" 8 | module Mux16( 9 | input [15:0] a, 10 | input [15:0] b, 11 | input sel, 12 | output [15:0] out 13 | ); 14 | // your implementation comes here: 15 | 16 | // Mux(a=a[0], b=b[0], sel=sel, out=out[0]); 17 | // Mux(a=a[1], b=b[1], sel=sel, out=out[1]); 18 | // Mux(a=a[2], b=b[2], sel=sel, out=out[2]); 19 | // Mux(a=a[3], b=b[3], sel=sel, out=out[3]); 20 | // Mux(a=a[4], b=b[4], sel=sel, out=out[4]); 21 | // Mux(a=a[5], b=b[5], sel=sel, out=out[5]); 22 | // Mux(a=a[6], b=b[6], sel=sel, out=out[6]); 23 | // Mux(a=a[7], b=b[7], sel=sel, out=out[7]); 24 | // Mux(a=a[8], b=b[8], sel=sel, out=out[8]); 25 | // Mux(a=a[9], b=b[9], sel=sel, out=out[9]); 26 | // Mux(a=a[10], b=b[10], sel=sel, out=out[10]); 27 | // Mux(a=a[11], b=b[11], sel=sel, out=out[11]); 28 | // Mux(a=a[12], b=b[12], sel=sel, out=out[12]); 29 | // Mux(a=a[13], b=b[13], sel=sel, out=out[13]); 30 | // Mux(a=a[14], b=b[14], sel=sel, out=out[14]); 31 | // Mux(a=a[15], b=b[15], sel=sel, out=out[15]); 32 | Mux MUX1(.a(a[0]),.b(b[0]),.sel(sel),.out(out[0])); 33 | Mux MUX2(.a(a[1]),.b(b[1]),.sel(sel),.out(out[1])); 34 | Mux MUX3(.a(a[2]),.b(b[2]),.sel(sel),.out(out[2])); 35 | Mux MUX4(.a(a[3]),.b(b[3]),.sel(sel),.out(out[3])); 36 | Mux MUX5(.a(a[4]),.b(b[4]),.sel(sel),.out(out[4])); 37 | Mux MUX6(.a(a[5]),.b(b[5]),.sel(sel),.out(out[5])); 38 | Mux MUX7(.a(a[6]),.b(b[6]),.sel(sel),.out(out[6])); 39 | Mux MUX8(.a(a[7]),.b(b[7]),.sel(sel),.out(out[7])); 40 | Mux MUX9(.a(a[8]),.b(b[8]),.sel(sel),.out(out[8])); 41 | Mux MUX10(.a(a[9]),.b(b[9]),.sel(sel),.out(out[9])); 42 | Mux MUX11(.a(a[10]),.b(b[10]),.sel(sel),.out(out[10])); 43 | Mux MUX12(.a(a[11]),.b(b[11]),.sel(sel),.out(out[11])); 44 | Mux MUX13(.a(a[12]),.b(b[12]),.sel(sel),.out(out[12])); 45 | Mux MUX14(.a(a[13]),.b(b[13]),.sel(sel),.out(out[13])); 46 | Mux MUX15(.a(a[14]),.b(b[14]),.sel(sel),.out(out[14])); 47 | Mux MUX16(.a(a[15]),.b(b[15]),.sel(sel),.out(out[15])); 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /01/Mux16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * 16-bit multiplexor: 3 | * for i = 0..15 out[i] = a[i] if sel == 0 4 | * b[i] if sel == 1 5 | */ 6 | `default_nettype none 7 | `include "Mux.v" 8 | module Mux16( 9 | input [15:0] a, 10 | input [15:0] b, 11 | input sel, 12 | output [15:0] out 13 | ); 14 | 15 | // your implementation comes here: 16 | 17 | // Mux(a=a[0], b=b[0], sel=sel, out=out[0]); 18 | // Mux(a=a[1], b=b[1], sel=sel, out=out[1]); 19 | // Mux(a=a[2], b=b[2], sel=sel, out=out[2]); 20 | // Mux(a=a[3], b=b[3], sel=sel, out=out[3]); 21 | // Mux(a=a[4], b=b[4], sel=sel, out=out[4]); 22 | // Mux(a=a[5], b=b[5], sel=sel, out=out[5]); 23 | // Mux(a=a[6], b=b[6], sel=sel, out=out[6]); 24 | // Mux(a=a[7], b=b[7], sel=sel, out=out[7]); 25 | // Mux(a=a[8], b=b[8], sel=sel, out=out[8]); 26 | // Mux(a=a[9], b=b[9], sel=sel, out=out[9]); 27 | // Mux(a=a[10], b=b[10], sel=sel, out=out[10]); 28 | // Mux(a=a[11], b=b[11], sel=sel, out=out[11]); 29 | // Mux(a=a[12], b=b[12], sel=sel, out=out[12]); 30 | // Mux(a=a[13], b=b[13], sel=sel, out=out[13]); 31 | // Mux(a=a[14], b=b[14], sel=sel, out=out[14]); 32 | // Mux(a=a[15], b=b[15], sel=sel, out=out[15]); 33 | Mux MUX1(.a(a[0]),.b(b[0]),.sel(sel),.out(out[0])); 34 | Mux MUX2(.a(a[1]),.b(b[1]),.sel(sel),.out(out[1])); 35 | Mux MUX3(.a(a[2]),.b(b[2]),.sel(sel),.out(out[2])); 36 | Mux MUX4(.a(a[3]),.b(b[3]),.sel(sel),.out(out[3])); 37 | Mux MUX5(.a(a[4]),.b(b[4]),.sel(sel),.out(out[4])); 38 | Mux MUX6(.a(a[5]),.b(b[5]),.sel(sel),.out(out[5])); 39 | Mux MUX7(.a(a[6]),.b(b[6]),.sel(sel),.out(out[6])); 40 | Mux MUX8(.a(a[7]),.b(b[7]),.sel(sel),.out(out[7])); 41 | Mux MUX9(.a(a[8]),.b(b[8]),.sel(sel),.out(out[8])); 42 | Mux MUX10(.a(a[9]),.b(b[9]),.sel(sel),.out(out[9])); 43 | Mux MUX11(.a(a[10]),.b(b[10]),.sel(sel),.out(out[10])); 44 | Mux MUX12(.a(a[11]),.b(b[11]),.sel(sel),.out(out[11])); 45 | Mux MUX13(.a(a[12]),.b(b[12]),.sel(sel),.out(out[12])); 46 | Mux MUX14(.a(a[13]),.b(b[13]),.sel(sel),.out(out[13])); 47 | Mux MUX15(.a(a[14]),.b(b[14]),.sel(sel),.out(out[14])); 48 | Mux MUX16(.a(a[15]),.b(b[15]),.sel(sel),.out(out[15])); 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /04/Memory.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Memory mapped IO 3 | * 4 | * Big Multiplexer/Demultiplexer to address Memory. 5 | * 6 | * if (load==1) and (address[13]==0) loadRAM=1 7 | * if (load==1) and (address[13]==1 and address[3:0]==0000) load0000=1 8 | * if (load==1) and (address[13]==1 and address[3:0]==0001) load0001=1 9 | * if (load==1) and (address[13]==1 and address[3:0]==0010) load0010=1 10 | * ... 11 | * if (address[13]==0) data = dataRAM 12 | * if (address[13]==1 and address[3:0]=0000) data = data0000 13 | * if (address[13]==1 and address[3:0]=0001) data = data0001 14 | * if (address[13]==1 and address[3:0]=0010) data = data0010 15 | */ 16 | 17 | `default_nettype none 18 | module Memory( 19 | input clk, 20 | input wire [15:0] address, 21 | input wire load, 22 | input wire btn, 23 | output wire led, 24 | output wire [15:0] out, 25 | input wire [15:0] in 26 | ); 27 | 28 | //your implementation comes here: 29 | // DMux(in=load ,sel=address[14] ,a=load1 ,b=load2 ); 30 | // DMux(in=load2,sel=address[13] ,a=load21,b=load22); 31 | // RAM16K(in=in ,load=load1 ,address=address[0..13] ,out=out1 ); 32 | // Screen(in=in ,load=load21 ,address=address[0..12] ,out=out2 ); 33 | // Keyboard(out= out3); 34 | // Mux16(a=out2 ,b=out3 ,sel=address[13] ,out=tmp); 35 | // Mux16(a=out1 ,b=tmp ,sel=address[14] ,out=out ); 36 | 37 | wire loadRAM; 38 | wire loadIO; 39 | wire loadBtn; 40 | wire loadLed; 41 | DMux DMUX1( 42 | .in(load), 43 | .sel(address[13]), 44 | .a(loadRAM), 45 | .b(loadIO) 46 | ); 47 | DMux DMUX2( 48 | .in(loadIO), 49 | .sel(address[0]), 50 | .a(loadBtn), 51 | .b(loadLed) 52 | ); 53 | 54 | wire[15:0] outRAM; 55 | RAM RAM1( 56 | .clk(clk), 57 | .address(address), 58 | .load(loadRAM), 59 | .in(in), 60 | .out(outRAM) 61 | ); 62 | 63 | // button - only read 64 | wire[15:0] outBtn; 65 | Btn BTN(.out(outBtn), .btn(btn)); 66 | // led - only write 67 | wire[15:0] outLed; 68 | Led LED(.clk(clk), .in(in), .out(outLed), .load(loadLed), .led(led)); 69 | 70 | wire[15:0] tmp; 71 | Mux16 MUX161( 72 | .a(outBtn), 73 | .b(outLed), 74 | .sel(address[0]), 75 | .out(tmp) 76 | ); 77 | 78 | Mux16 MUX162( 79 | .a(outRAM), 80 | .b(tmp), 81 | .sel(address[13]), 82 | .out(out) 83 | ); 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /02/ALU.cmp: -------------------------------------------------------------------------------- 1 | |x|y|zx|nx|zy|ny|f|no|out|zr|ng| 2 | |0000000000000000|1111111111111111|1|0|1|0|1|0|0000000000000000|1|0| 3 | |0000000000000000|1111111111111111|1|1|1|1|1|1|0000000000000001|0|0| 4 | |0000000000000000|1111111111111111|1|1|1|0|1|0|1111111111111111|0|1| 5 | |0000000000000000|1111111111111111|0|0|1|1|0|0|0000000000000000|1|0| 6 | |0000000000000000|1111111111111111|1|1|0|0|0|0|1111111111111111|0|1| 7 | |0000000000000000|1111111111111111|0|0|1|1|0|1|1111111111111111|0|1| 8 | |0000000000000000|1111111111111111|1|1|0|0|0|1|0000000000000000|1|0| 9 | |0000000000000000|1111111111111111|0|0|1|1|1|1|0000000000000000|1|0| 10 | |0000000000000000|1111111111111111|1|1|0|0|1|1|0000000000000001|0|0| 11 | |0000000000000000|1111111111111111|0|1|1|1|1|1|0000000000000001|0|0| 12 | |0000000000000000|1111111111111111|1|1|0|1|1|1|0000000000000000|1|0| 13 | |0000000000000000|1111111111111111|0|0|1|1|1|0|1111111111111111|0|1| 14 | |0000000000000000|1111111111111111|1|1|0|0|1|0|1111111111111110|0|1| 15 | |0000000000000000|1111111111111111|0|0|0|0|1|0|1111111111111111|0|1| 16 | |0000000000000000|1111111111111111|0|1|0|0|1|1|0000000000000001|0|0| 17 | |0000000000000000|1111111111111111|0|0|0|1|1|1|1111111111111111|0|1| 18 | |0000000000000000|1111111111111111|0|0|0|0|0|0|0000000000000000|1|0| 19 | |0000000000000000|1111111111111111|0|1|0|1|0|1|1111111111111111|0|1| 20 | |0000000000010001|0000000000000011|1|0|1|0|1|0|0000000000000000|1|0| 21 | |0000000000010001|0000000000000011|1|1|1|1|1|1|0000000000000001|0|0| 22 | |0000000000010001|0000000000000011|1|1|1|0|1|0|1111111111111111|0|1| 23 | |0000000000010001|0000000000000011|0|0|1|1|0|0|0000000000010001|0|0| 24 | |0000000000010001|0000000000000011|1|1|0|0|0|0|0000000000000011|0|0| 25 | |0000000000010001|0000000000000011|0|0|1|1|0|1|1111111111101110|0|1| 26 | |0000000000010001|0000000000000011|1|1|0|0|0|1|1111111111111100|0|1| 27 | |0000000000010001|0000000000000011|0|0|1|1|1|1|1111111111101111|0|1| 28 | |0000000000010001|0000000000000011|1|1|0|0|1|1|1111111111111101|0|1| 29 | |0000000000010001|0000000000000011|0|1|1|1|1|1|0000000000010010|0|0| 30 | |0000000000010001|0000000000000011|1|1|0|1|1|1|0000000000000100|0|0| 31 | |0000000000010001|0000000000000011|0|0|1|1|1|0|0000000000010000|0|0| 32 | |0000000000010001|0000000000000011|1|1|0|0|1|0|0000000000000010|0|0| 33 | |0000000000010001|0000000000000011|0|0|0|0|1|0|0000000000010100|0|0| 34 | |0000000000010001|0000000000000011|0|1|0|0|1|1|0000000000001110|0|0| 35 | |0000000000010001|0000000000000011|0|0|0|1|1|1|1111111111110010|0|1| 36 | |0000000000010001|0000000000000011|0|0|0|0|0|0|0000000000000001|0|0| 37 | |0000000000010001|0000000000000011|0|1|0|1|0|1|0000000000010011|0|0| 38 | -------------------------------------------------------------------------------- /04/CPU.cmp: -------------------------------------------------------------------------------- 1 | | time | inM | instruction |reset| outM |writeM|addres| pc | 2 | | 0| 0|0011000000111001| 0 | 0| 0 | x| x| 3 | | 1| 0|0011000000111001| 0 | 0| 0 | 12345| 0| 4 | | 1| 0|1110110000010000| 0 | 12345| 0 | 12345| 0| 5 | | 2| 0|1110110000010000| 0 | 12345| 0 | 12345| 1| 6 | | 2| 0|0101101110100000| 0 | -1| 0 | 12345| 1| 7 | | 3| 0|0101101110100000| 0 | -1| 0 | 23456| 2| 8 | | 3| 11111|1110000111110000| 0 | 11111| 0 | 23456| 2| 9 | | 4| 11111|1110000111110000| 0 | 0| 0 | 11111| 3| 10 | | 4| 11111|0000001111101011| 0 |-11111| 0 | 11111| 3| 11 | | 5| 11111|0000001111101011| 0 |-11111| 0 | 1003| 4| 12 | | 5| 11111|1110001100001000| 0 | 11111| 1 | 1003| 4| 13 | | 6| 11111|1110001100001000| 0 | 11111| 1 | 1003| 5| 14 | | 6| 11111|0000001111101100| 0 |-11111| 0 | 1003| 5| 15 | | 7| 11111|0000001111101100| 0 |-11111| 0 | 1004| 6| 16 | | 7| 11111|1110001110011000| 0 | 11110| 1 | 1004| 6| 17 | | 8| 11111|1110001110011000| 0 | 11109| 1 | 1004| 7| 18 | | 8| 11111|0000001111101000| 0 |-11110| 0 | 1004| 7| 19 | | 9| 11111|0000001111101000| 0 |-11110| 0 | 1000| 8| 20 | | 9| 11111|1111010011110000| 0 | -1| 0 | 1000| 8| 21 | | 10| 11111|1111010011110000| 0 |-11112| 0 | 32767| 9| 22 | | 10| 11111|0000000000001110| 0 | -1| 0 | 32767| 9| 23 | | 11| 11111|0000000000001110| 0 | 14| 0 | 14| 10| 24 | | 11| 11111|1110001100000100| 0 | -1| 0 | 14| 10| 25 | | 12| 11111|1110001100000100| 0 | -1| 0 | 14| 14| 26 | | 12| 11111|0000001111100111| 0 | 1| 0 | 14| 14| 27 | | 13| 11111|0000001111100111| 0 | 1| 0 | 999| 15| 28 | | 13| 11111|1111110111100000| 0 | 11112| 0 | 999| 15| 29 | | 14| 11111|1111110111100000| 0 | 11112| 0 | 11112| 16| 30 | | 14| 11111|1110001100101000| 0 | -1| 1 | 11112| 16| 31 | | 15| 11111|1110001100101000| 0 | -1| 1 | 32767| 17| 32 | | 15| 11111|0000000000010101| 0 | -1| 0 | 32767| 17| 33 | | 16| 11111|0000000000010101| 0 | 21| 0 | 21| 18| 34 | | 16| 11111|1110011111000010| 0 | 0| 0 | 21| 18| 35 | | 17| 11111|1110011111000010| 0 | 0| 0 | 21| 21| 36 | | 17| 11111|0000000000000010| 0 | 21| 0 | 21| 21| 37 | | 18| 11111|0000000000000010| 0 | 2| 0 | 2| 22| 38 | | 18| 11111|1110000010111000| 0 | 1| 1 | 2| 22| 39 | | 19| 11111|1110000010111000| 0 | 2| 1 | 1| 23| 40 | -------------------------------------------------------------------------------- /03/README.md: -------------------------------------------------------------------------------- 1 | ## 时序电路（存储） 2 | 3 | ### 时序电路 4 | 5 | 所谓时序电路就是含有时钟信号的电路，时钟信号上下翻转 6 | 7 | ### D 触发器 8 | 9 | 因为 D 触发器只有一个输入和一个输出，可以用硬件测试。因为 D 触发器是时钟触发的，所以约束文件一定要带上时钟。 10 | 11 | ``` 12 | IO_LOC "out" 10; // red 13 | IO_LOC "in" 15; 14 | IO_LOC "clk" 45; 15 | ``` 16 | 17 | D 触发器具有存储功能，其实是通过反馈实现的，所以我们用它来实现存储电路。 18 | 19 | ### Bit 20 | 21 | bit 是一位存储，由 D 触发器实现。和单纯的 D 触发器不同，额外使用了数据选择器实现数据的改变。 22 | 23 | ```verilog 24 | wire muxo; 25 | Mux MUX(.a(out),.b(in),.sel(load),.out(muxo)); 26 | DFFusr DFF1(.clk(clk),.in(muxo),.out(out)); 27 | ``` 28 | 29 | 当 load = 1 时，D 触发器的输入被改变，所以 D 触发器的下一个状态改变。 30 | 31 | 因为时序电路用到了 clk ，所以仿真时 clk 不会自动变化，需要添加 always #1 clk = ~clk; 来使 clk 每隔一个时钟周期翻转一次。 32 | 33 | ### 寄存器 34 | 35 | 因为我们要构建的计算机是 16 位的，所以寄存器是 16 位的，寄存器由 16 个 Bit 组成。 36 | 37 | ```verilog 38 | Bit BIT1(.in(in[0]),.load(load),.out(out[0]), .clk(clk)); 39 | Bit BIT2(.in(in[1]),.load(load),.out(out[1]), .clk(clk)); 40 | Bit BIT3(.in(in[2]),.load(load),.out(out[2]), .clk(clk)); 41 | Bit BIT4(.in(in[3]),.load(load),.out(out[3]), .clk(clk)); 42 | Bit BIT5(.in(in[4]),.load(load),.out(out[4]), .clk(clk)); 43 | Bit BIT6(.in(in[5]),.load(load),.out(out[5]), .clk(clk)); 44 | Bit BIT7(.in(in[6]),.load(load),.out(out[6]), .clk(clk)); 45 | Bit BIT8(.in(in[7]),.load(load),.out(out[7]), .clk(clk)); 46 | Bit BIT9(.in(in[8]),.load(load),.out(out[8]), .clk(clk)); 47 | Bit BIT10(.in(in[9]),.load(load),.out(out[9]), .clk(clk)); 48 | Bit BIT11(.in(in[10]),.load(load),.out(out[10]), .clk(clk)); 49 | Bit BIT12(.in(in[11]),.load(load),.out(out[11]), .clk(clk)); 50 | Bit BIT13(.in(in[12]),.load(load),.out(out[12]), .clk(clk)); 51 | Bit BIT14(.in(in[13]),.load(load),.out(out[13]), .clk(clk)); 52 | Bit BIT15(.in(in[14]),.load(load),.out(out[14]), .clk(clk)); 53 | Bit BIT16(.in(in[15]),.load(load),.out(out[15]), .clk(clk)); 54 | ``` 55 | 56 | ### PC 57 | 58 | PC 又称程序计数器，主要由寄存器实现。PC 有三个条件，分别为 reset load inc 。由三个二选一数据选择器实现，先后次序决定优先级，加 1 由加法器实现。 59 | 60 | 有三个功能： 61 | 62 | - 当 inc = 1 时，加 1 63 | - 当 load = 1 时，把 in 的值赋给 PC 64 | - 当 reset = 1 时，复位 65 | 66 | ### RAM 67 | 68 | 现代体系结构中 RAM + io 映射等于所谓的主存，本节我们先实现 RAM 。根据 nand2tetris ，RAM 用寄存器实现，让 verilog 自己生成。当然更正确的做法是使用 Fpga 的 block RAM ，但是开源工具不支持： https://github.com/YosysHQ/yosys/wiki/FPGA-family-feature-matrix 。 69 | 70 | ```verilog 71 | module RAM( 72 | input wire clk, 73 | input wire [15:0] address, 74 | input wire [15:0] in, 75 | input wire load, 76 | output wire [15:0] out 77 | ); 78 | 79 | reg [15:0] regRAM [0:10]; 80 | always @(negedge clk) 81 | if (load) regRAM[address[3:0]] <= in; 82 | 83 | assign out = regRAM[address[3:0]]; 84 | endmodule 85 | ``` 86 | 87 | 低 4 位都用来访问 RAM ，regRAM 代表 10 个 16 位空间。 88 | 89 | > 关于 BlockRAM：http://xilinx.eetrend.com/blog/2020/100049862.html 90 | 91 | > 关于 LUT：https://cloud.tencent.com/developer/article/1794053 92 | 93 | > 代码：https://github.com/buhe/bugu-computer/tree/master/03 -------------------------------------------------------------------------------- /01/README.md: -------------------------------------------------------------------------------- 1 | ## 布尔逻辑 2 | 大部分电路输入都大于两个，如 Mux 有三个输入，And16 甚至有 16 个输入。只有 DMux 有两个输入两个输出。 3 | 4 | 虽然 tangnaono 只有一个 led 能被程序控制，但 tangnano 有很多 gpio ，gpio 是通用接口，程序可以控制它产生高低电平（也就是 0 1 ）。可以把一个 led 接在 gpio 上（这里一端接到 2 一端接地）这样控制 gpio 的电平可以间接控制 led 的灯亮灭。 5 | 6 | IMG_1879 7 | 8 | ### DMux 9 | 10 | DMux 又称数据分配器。根据 sel 的信号分配 in 的信号，如果 sel 等于 0 则 a 等于 in 的信号，如果 sel 等于 1 则 b 等于 in 的信号。 11 | 12 | ```verilog 13 | `include "Not.v" 14 | `include "And.v" 15 | `default_nettype none 16 | 17 | module DMux( 18 | input wire in, 19 | input wire sel, 20 | output wire a, 21 | output wire b 22 | ); 23 | wire notsel; 24 | Not NOT2(.in(sel), .out(notsel)); 25 | And AND1(.a(in),.b(notsel),.out(a)); 26 | And AND2(.a(in),.b(sel),.out(b)); 27 | 28 | endmodule 29 | ``` 30 | 31 | 约束文件如下： 32 | 33 | ``` 34 | IO_LOC "a" 10; // red 35 | IO_LOC "in" 15; 36 | IO_LOC "sel" 14; // right hand default 1 37 | IO_LOC "b" 2; // blue 38 | ``` 39 | 40 | 执行以下命令写入 Fpga 41 | 42 | ```bash 43 | make sym-dmux 44 | 45 | make flash 46 | ``` 47 | 48 | 因为开关（14 也就是右边那个按钮）松开默认是 1 ，所以当写入 Fpga 后什么都不做，sel 等于 1 ，b 的信号等于 in 的信号，此时因为 in 绑定到按钮上（15 左边的按钮）也默认为 1 ，所以 b 为 1 ，连接到 gpio 2 的 led 发光（因为是 1 也就是高电平）。按下右边的按钮（sel），sel 等于 0 ，in 分配给了 a，红灯（10）亮，外接的 led（2）灭。 49 | 50 | ### 其他 51 | 52 | 这次的其他电路输入都大于 2 个，我们的 Fpga 只有两个按钮，在其上很难测试，虽然也可以连接额外的按钮，可 And16 有 16 个输入，同时按不现实，所以选择用仿真测试，以 And16 为例，其他同理。 53 | 54 | And16 其实就是 16 个与门按位与： 55 | 56 | ```verilog 57 | `include "Not.v" 58 | `include "And.v" 59 | `default_nettype none 60 | module And16( 61 | input wire [15:0] a, 62 | input wire [15:0] b, 63 | output wire [15:0] out 64 | ); 65 | And AND1(.a(a[0]),.b(b[0]),.out(out[0])); 66 | And AND2(.a(a[1]),.b(b[1]),.out(out[1])); 67 | And AND3(.a(a[2]),.b(b[2]),.out(out[2])); 68 | And AND4(.a(a[3]),.b(b[3]),.out(out[3])); 69 | And AND5(.a(a[4]),.b(b[4]),.out(out[4])); 70 | And AND6(.a(a[5]),.b(b[5]),.out(out[5])); 71 | And AND7(.a(a[6]),.b(b[6]),.out(out[6])); 72 | And AND8(.a(a[7]),.b(b[7]),.out(out[7])); 73 | And AND9(.a(a[8]),.b(b[8]),.out(out[8])); 74 | And AND10(.a(a[9]),.b(b[9]),.out(out[9])); 75 | And AND11(.a(a[10]),.b(b[10]),.out(out[10])); 76 | And AND12(.a(a[11]),.b(b[11]),.out(out[11])); 77 | And AND13(.a(a[12]),.b(b[12]),.out(out[12])); 78 | And AND14(.a(a[13]),.b(b[13]),.out(out[13])); 79 | And AND15(.a(a[14]),.b(b[14]),.out(out[14])); 80 | And AND16(.a(a[15]),.b(b[15]),.out(out[15])); 81 | endmodule 82 | ``` 83 | 84 | 很简单，可以看到创建了 16 个与门，a b 每一位相与的结果放在 out 的对应位。 85 | 86 | 编译，执行测试（仿真，激励）。 87 | 88 | ```bash 89 | iverilog -o And16_tb.vvp And16_tb.v 90 | 91 | vvp And16_tb.vvp 92 | ``` 93 | 94 | 测试会把结果写入 *.out 文件里，然后和提供的 *.cmp 比较就可以了，如果一样就代表通过了。 95 | 96 | ```bash 97 | diff And16.out And16.cmp 98 | ``` 99 | 100 | 其他逻辑电路相同。 101 | 102 | > 代码：https://github.com/buhe/bugu-computer/tree/master/01 -------------------------------------------------------------------------------- /02/Add16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Adds two 16-bit values. 3 | * The most significant carry bit is ignored. 4 | * out = a + b (16 bit) 5 | */ 6 | `include "FullAdder.v" 7 | `default_nettype none 8 | module Add16( 9 | input wire [15:0] a, 10 | input wire [15:0] b, 11 | output wire [15:0] out 12 | ); 13 | // your implementation comes here: 14 | // HalfAdder(a=a[0], b=b[0], sum=out[0], carry=carry); 15 | // FullAdder(a=a[1], b=b[1], c=carry, sum=out[1], carry=carry1); 16 | // FullAdder(a=a[2], b=b[2], c=carry1, sum=out[2], carry=carry2); 17 | // FullAdder(a=a[3], b=b[3], c=carry2, sum=out[3], carry=carry3); 18 | // FullAdder(a=a[4], b=b[4], c=carry3, sum=out[4], carry=carry4); 19 | // FullAdder(a=a[5], b=b[5], c=carry4, sum=out[5], carry=carry5); 20 | // FullAdder(a=a[6], b=b[6], c=carry5, sum=out[6], carry=carry6); 21 | // FullAdder(a=a[7], b=b[7], c=carry6, sum=out[7], carry=carry7); 22 | // FullAdder(a=a[8], b=b[8], c=carry7, sum=out[8], carry=carry8); 23 | // FullAdder(a=a[9], b=b[9], c=carry8, sum=out[9], carry=carry9); 24 | // FullAdder(a=a[10], b=b[10], c=carry9, sum=out[10], carry=carry10); 25 | // FullAdder(a=a[11], b=b[11], c=carry10, sum=out[11], carry=carry11); 26 | // FullAdder(a=a[12], b=b[12], c=carry11, sum=out[12], carry=carry12); 27 | // FullAdder(a=a[13], b=b[13], c=carry12, sum=out[13], carry=carry13); 28 | // FullAdder(a=a[14], b=b[14], c=carry13, sum=out[14], carry=carry14); 29 | // FullAdder(a=a[15], b=b[15], c=carry14, sum=out[15], carry=carry15); 30 | 31 | wire carry; 32 | wire carry1; 33 | wire carry2; 34 | wire carry3; 35 | wire carry4; 36 | wire carry5; 37 | wire carry6; 38 | wire carry7; 39 | wire carry8; 40 | wire carry9; 41 | wire carry10; 42 | wire carry11; 43 | wire carry12; 44 | wire carry13; 45 | wire carry14; 46 | wire carry15; 47 | HalfAdder HalfAdder1(.a(a[0]),.b(b[0]),.sum(out[0]),.carry(carry)); 48 | FullAdder FullAdder1(.a(a[1]),.b(b[1]),.c(carry),.sum(out[1]),.carry(carry1)); 49 | FullAdder FullAdder2(.a(a[2]),.b(b[2]),.c(carry1),.sum(out[2]),.carry(carry2)); 50 | FullAdder FullAdder3(.a(a[3]),.b(b[3]),.c(carry2),.sum(out[3]),.carry(carry3)); 51 | FullAdder FullAdder4(.a(a[4]),.b(b[4]),.c(carry3),.sum(out[4]),.carry(carry4)); 52 | FullAdder FullAdder5(.a(a[5]),.b(b[5]),.c(carry4),.sum(out[5]),.carry(carry5)); 53 | FullAdder FullAdder6(.a(a[6]),.b(b[6]),.c(carry5),.sum(out[6]),.carry(carry6)); 54 | FullAdder FullAdder7(.a(a[7]),.b(b[7]),.c(carry6),.sum(out[7]),.carry(carry7)); 55 | FullAdder FullAdder8(.a(a[8]),.b(b[8]),.c(carry7),.sum(out[8]),.carry(carry8)); 56 | FullAdder FullAdder9(.a(a[9]),.b(b[9]),.c(carry8),.sum(out[9]),.carry(carry9)); 57 | FullAdder FullAdder10(.a(a[10]),.b(b[10]),.c(carry9),.sum(out[10]),.carry(carry10)); 58 | FullAdder FullAdder11(.a(a[11]),.b(b[11]),.c(carry10),.sum(out[11]),.carry(carry11)); 59 | FullAdder FullAdder12(.a(a[12]),.b(b[12]),.c(carry11),.sum(out[12]),.carry(carry12)); 60 | FullAdder FullAdder13(.a(a[13]),.b(b[13]),.c(carry12),.sum(out[13]),.carry(carry13)); 61 | FullAdder FullAdder14(.a(a[14]),.b(b[14]),.c(carry13),.sum(out[14]),.carry(carry14)); 62 | FullAdder FullAdder15(.a(a[15]),.b(b[15]),.c(carry14),.sum(out[15]),.carry(carry15)); 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /03/Add16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Adds two 16-bit values. 3 | * The most significant carry bit is ignored. 4 | * out = a + b (16 bit) 5 | */ 6 | `include "FullAdder.v" 7 | 8 | `default_nettype none 9 | module Add16( 10 | input wire [15:0] a, 11 | input wire [15:0] b, 12 | output wire [15:0] out 13 | ); 14 | // your implementation comes here: 15 | // HalfAdder(a=a[0], b=b[0], sum=out[0], carry=carry); 16 | // FullAdder(a=a[1], b=b[1], c=carry, sum=out[1], carry=carry1); 17 | // FullAdder(a=a[2], b=b[2], c=carry1, sum=out[2], carry=carry2); 18 | // FullAdder(a=a[3], b=b[3], c=carry2, sum=out[3], carry=carry3); 19 | // FullAdder(a=a[4], b=b[4], c=carry3, sum=out[4], carry=carry4); 20 | // FullAdder(a=a[5], b=b[5], c=carry4, sum=out[5], carry=carry5); 21 | // FullAdder(a=a[6], b=b[6], c=carry5, sum=out[6], carry=carry6); 22 | // FullAdder(a=a[7], b=b[7], c=carry6, sum=out[7], carry=carry7); 23 | // FullAdder(a=a[8], b=b[8], c=carry7, sum=out[8], carry=carry8); 24 | // FullAdder(a=a[9], b=b[9], c=carry8, sum=out[9], carry=carry9); 25 | // FullAdder(a=a[10], b=b[10], c=carry9, sum=out[10], carry=carry10); 26 | // FullAdder(a=a[11], b=b[11], c=carry10, sum=out[11], carry=carry11); 27 | // FullAdder(a=a[12], b=b[12], c=carry11, sum=out[12], carry=carry12); 28 | // FullAdder(a=a[13], b=b[13], c=carry12, sum=out[13], carry=carry13); 29 | // FullAdder(a=a[14], b=b[14], c=carry13, sum=out[14], carry=carry14); 30 | // FullAdder(a=a[15], b=b[15], c=carry14, sum=out[15], carry=carry15); 31 | 32 | wire carry; 33 | wire carry1; 34 | wire carry2; 35 | wire carry3; 36 | wire carry4; 37 | wire carry5; 38 | wire carry6; 39 | wire carry7; 40 | wire carry8; 41 | wire carry9; 42 | wire carry10; 43 | wire carry11; 44 | wire carry12; 45 | wire carry13; 46 | wire carry14; 47 | wire carry15; 48 | HalfAdder HalfAdder1(.a(a[0]),.b(b[0]),.sum(out[0]),.carry(carry)); 49 | FullAdder FullAdder1(.a(a[1]),.b(b[1]),.c(carry),.sum(out[1]),.carry(carry1)); 50 | FullAdder FullAdder2(.a(a[2]),.b(b[2]),.c(carry1),.sum(out[2]),.carry(carry2)); 51 | FullAdder FullAdder3(.a(a[3]),.b(b[3]),.c(carry2),.sum(out[3]),.carry(carry3)); 52 | FullAdder FullAdder4(.a(a[4]),.b(b[4]),.c(carry3),.sum(out[4]),.carry(carry4)); 53 | FullAdder FullAdder5(.a(a[5]),.b(b[5]),.c(carry4),.sum(out[5]),.carry(carry5)); 54 | FullAdder FullAdder6(.a(a[6]),.b(b[6]),.c(carry5),.sum(out[6]),.carry(carry6)); 55 | FullAdder FullAdder7(.a(a[7]),.b(b[7]),.c(carry6),.sum(out[7]),.carry(carry7)); 56 | FullAdder FullAdder8(.a(a[8]),.b(b[8]),.c(carry7),.sum(out[8]),.carry(carry8)); 57 | FullAdder FullAdder9(.a(a[9]),.b(b[9]),.c(carry8),.sum(out[9]),.carry(carry9)); 58 | FullAdder FullAdder10(.a(a[10]),.b(b[10]),.c(carry9),.sum(out[10]),.carry(carry10)); 59 | FullAdder FullAdder11(.a(a[11]),.b(b[11]),.c(carry10),.sum(out[11]),.carry(carry11)); 60 | FullAdder FullAdder12(.a(a[12]),.b(b[12]),.c(carry11),.sum(out[12]),.carry(carry12)); 61 | FullAdder FullAdder13(.a(a[13]),.b(b[13]),.c(carry12),.sum(out[13]),.carry(carry13)); 62 | FullAdder FullAdder14(.a(a[14]),.b(b[14]),.c(carry13),.sum(out[14]),.carry(carry14)); 63 | FullAdder FullAdder15(.a(a[15]),.b(b[15]),.c(carry14),.sum(out[15]),.carry(carry15)); 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /04/Add16.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Adds two 16-bit values. 3 | * The most significant carry bit is ignored. 4 | * out = a + b (16 bit) 5 | */ 6 | `include "FullAdder.v" 7 | 8 | `default_nettype none 9 | module Add16( 10 | input wire [15:0] a, 11 | input wire [15:0] b, 12 | output wire [15:0] out 13 | ); 14 | // your implementation comes here: 15 | // HalfAdder(a=a[0], b=b[0], sum=out[0], carry=carry); 16 | // FullAdder(a=a[1], b=b[1], c=carry, sum=out[1], carry=carry1); 17 | // FullAdder(a=a[2], b=b[2], c=carry1, sum=out[2], carry=carry2); 18 | // FullAdder(a=a[3], b=b[3], c=carry2, sum=out[3], carry=carry3); 19 | // FullAdder(a=a[4], b=b[4], c=carry3, sum=out[4], carry=carry4); 20 | // FullAdder(a=a[5], b=b[5], c=carry4, sum=out[5], carry=carry5); 21 | // FullAdder(a=a[6], b=b[6], c=carry5, sum=out[6], carry=carry6); 22 | // FullAdder(a=a[7], b=b[7], c=carry6, sum=out[7], carry=carry7); 23 | // FullAdder(a=a[8], b=b[8], c=carry7, sum=out[8], carry=carry8); 24 | // FullAdder(a=a[9], b=b[9], c=carry8, sum=out[9], carry=carry9); 25 | // FullAdder(a=a[10], b=b[10], c=carry9, sum=out[10], carry=carry10); 26 | // FullAdder(a=a[11], b=b[11], c=carry10, sum=out[11], carry=carry11); 27 | // FullAdder(a=a[12], b=b[12], c=carry11, sum=out[12], carry=carry12); 28 | // FullAdder(a=a[13], b=b[13], c=carry12, sum=out[13], carry=carry13); 29 | // FullAdder(a=a[14], b=b[14], c=carry13, sum=out[14], carry=carry14); 30 | // FullAdder(a=a[15], b=b[15], c=carry14, sum=out[15], carry=carry15); 31 | 32 | wire carry; 33 | wire carry1; 34 | wire carry2; 35 | wire carry3; 36 | wire carry4; 37 | wire carry5; 38 | wire carry6; 39 | wire carry7; 40 | wire carry8; 41 | wire carry9; 42 | wire carry10; 43 | wire carry11; 44 | wire carry12; 45 | wire carry13; 46 | wire carry14; 47 | wire carry15; 48 | HalfAdder HalfAdder1(.a(a[0]),.b(b[0]),.sum(out[0]),.carry(carry)); 49 | FullAdder FullAdder1(.a(a[1]),.b(b[1]),.c(carry),.sum(out[1]),.carry(carry1)); 50 | FullAdder FullAdder2(.a(a[2]),.b(b[2]),.c(carry1),.sum(out[2]),.carry(carry2)); 51 | FullAdder FullAdder3(.a(a[3]),.b(b[3]),.c(carry2),.sum(out[3]),.carry(carry3)); 52 | FullAdder FullAdder4(.a(a[4]),.b(b[4]),.c(carry3),.sum(out[4]),.carry(carry4)); 53 | FullAdder FullAdder5(.a(a[5]),.b(b[5]),.c(carry4),.sum(out[5]),.carry(carry5)); 54 | FullAdder FullAdder6(.a(a[6]),.b(b[6]),.c(carry5),.sum(out[6]),.carry(carry6)); 55 | FullAdder FullAdder7(.a(a[7]),.b(b[7]),.c(carry6),.sum(out[7]),.carry(carry7)); 56 | FullAdder FullAdder8(.a(a[8]),.b(b[8]),.c(carry7),.sum(out[8]),.carry(carry8)); 57 | FullAdder FullAdder9(.a(a[9]),.b(b[9]),.c(carry8),.sum(out[9]),.carry(carry9)); 58 | FullAdder FullAdder10(.a(a[10]),.b(b[10]),.c(carry9),.sum(out[10]),.carry(carry10)); 59 | FullAdder FullAdder11(.a(a[11]),.b(b[11]),.c(carry10),.sum(out[11]),.carry(carry11)); 60 | FullAdder FullAdder12(.a(a[12]),.b(b[12]),.c(carry11),.sum(out[12]),.carry(carry12)); 61 | FullAdder FullAdder13(.a(a[13]),.b(b[13]),.c(carry12),.sum(out[13]),.carry(carry13)); 62 | FullAdder FullAdder14(.a(a[14]),.b(b[14]),.c(carry13),.sum(out[14]),.carry(carry14)); 63 | FullAdder FullAdder15(.a(a[15]),.b(b[15]),.c(carry14),.sum(out[15]),.carry(carry15)); 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /02/ALU_tb.v: -------------------------------------------------------------------------------- 1 | `include "ALU.v" 2 | `default_nettype none 3 | module ALU_tb(); 4 | 5 | integer file; 6 | 7 | reg[15:0] x = 16'b0000000000000000; 8 | reg[15:0] y = 16'b1111111111111111; 9 | reg zx = 0; 10 | reg nx = 0; 11 | reg zy = 0; 12 | reg ny = 0; 13 | reg f = 0; 14 | reg no = 0; 15 | 16 | wire[15:0] out; 17 | wire zr; 18 | wire ng; 19 | 20 | ALU ALU( 21 | .x(x), 22 | .y(y), 23 | .zx(zx), 24 | .nx(nx), 25 | .zy(zy), 26 | .ny(ny), 27 | .f(f), 28 | .no(no), 29 | .out(out), 30 | .zr(zr), 31 | .ng(ng) 32 | ); 33 | 34 | task display; 35 | #1 $fwrite(file, "|%16b|%16b|%1b|%1b|%1b|%1b|%1b|%1b|%16b|%1b|%1b|\n", x,y,zx,nx,zy,ny,f,no,out,zr,ng); 36 | endtask 37 | 38 | initial begin 39 | $dumpfile("ALU_tb.vcd"); 40 | $dumpvars(0, ALU_tb); 41 | file = $fopen("ALU.out","w"); 42 | $fwrite(file, "|x|y|zx|nx|zy|ny|f|no|out|zr|ng|\n"); 43 | 44 | zx=1;nx=0;zy=1;ny=0;f=1;no=0; 45 | display(); 46 | 47 | zx=1;nx=1;zy=1;ny=1;f=1;no=1; 48 | display(); 49 | 50 | zx=1;nx=1;zy=1;ny=0;f=1;no=0; 51 | display(); 52 | 53 | zx=0;nx=0;zy=1;ny=1;f=0;no=0; 54 | display(); 55 | 56 | zx=1;nx=1;zy=0;ny=0;f=0;no=0; 57 | display(); 58 | 59 | zx=0;nx=0;zy=1;ny=1;f=0;no=1; 60 | display(); 61 | 62 | zx=1;nx=1;zy=0;ny=0;f=0;no=1; 63 | display(); 64 | 65 | zx=0;nx=0;zy=1;ny=1;f=1;no=1; 66 | display(); 67 | 68 | zx=1;nx=1;zy=0;ny=0;f=1;no=1; 69 | display(); 70 | 71 | zx=0;nx=1;zy=1;ny=1;f=1;no=1; 72 | display(); 73 | 74 | zx=1;nx=1;zy=0;ny=1;f=1;no=1; 75 | display(); 76 | 77 | zx=0;nx=0;zy=1;ny=1;f=1;no=0; 78 | display(); 79 | 80 | zx=1;nx=1;zy=0;ny=0;f=1;no=0; 81 | display(); 82 | 83 | zx=0;nx=0;zy=0;ny=0;f=1;no=0; 84 | display(); 85 | 86 | zx=0;nx=1;zy=0;ny=0;f=1;no=1; 87 | display(); 88 | 89 | zx=0;nx=0;zy=0;ny=1;f=1;no=1; 90 | display(); 91 | 92 | zx=0;nx=0;zy=0;ny=0;f=0;no=0; 93 | display(); 94 | 95 | zx=0;nx=1;zy=0;ny=1;f=0;no=1; 96 | display(); 97 | 98 | x = 16'b000000000010001; 99 | y = 16'b000000000000011; 100 | zx=1;nx=0;zy=1;ny=0;f=1;no=0; 101 | display(); 102 | 103 | zx=1;nx=1;zy=1;ny=1;f=1;no=1; 104 | display(); 105 | 106 | zx=1;nx=1;zy=1;ny=0;f=1;no=0; 107 | display(); 108 | 109 | zx=0;nx=0;zy=1;ny=1;f=0;no=0; 110 | display(); 111 | 112 | zx=1;nx=1;zy=0;ny=0;f=0;no=0; 113 | display(); 114 | 115 | zx=0;nx=0;zy=1;ny=1;f=0;no=1; 116 | display(); 117 | 118 | zx=1;nx=1;zy=0;ny=0;f=0;no=1; 119 | display(); 120 | 121 | zx=0;nx=0;zy=1;ny=1;f=1;no=1; 122 | display(); 123 | 124 | zx=1;nx=1;zy=0;ny=0;f=1;no=1; 125 | display(); 126 | 127 | zx=0;nx=1;zy=1;ny=1;f=1;no=1; 128 | display(); 129 | 130 | zx=1;nx=1;zy=0;ny=1;f=1;no=1; 131 | display(); 132 | 133 | zx=0;nx=0;zy=1;ny=1;f=1;no=0; 134 | display(); 135 | 136 | zx=1;nx=1;zy=0;ny=0;f=1;no=0; 137 | display(); 138 | 139 | zx=0;nx=0;zy=0;ny=0;f=1;no=0; 140 | display(); 141 | 142 | zx=0;nx=1;zy=0;ny=0;f=1;no=1; 143 | display(); 144 | 145 | zx=0;nx=0;zy=0;ny=1;f=1;no=1; 146 | display(); 147 | 148 | zx=0;nx=0;zy=0;ny=0;f=0;no=0; 149 | display(); 150 | 151 | zx=0;nx=1;zy=0;ny=1;f=0;no=1; 152 | display(); 153 | $finish(); 154 | end 155 | 156 | endmodule 157 | -------------------------------------------------------------------------------- /04/ALUusr.v: -------------------------------------------------------------------------------- 1 | /** 2 | * The ALU (Arithmetic Logic Unit). 3 | * Computes one of the following functions: 4 | * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y, 5 | * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs, 6 | * according to 6 input bits denoted zx,nx,zy,ny,f,no. 7 | * In addition, the ALU computes two 1-bit outputs: 8 | * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0; 9 | * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0. 10 | */ 11 | 12 | // Implementation: the ALU logic manipulates the x and y inputs 13 | // and operates on the resulting values, as follows: 14 | // if (zx == 1) set x = 0 // 16-bit constant 15 | // if (nx == 1) set x = !x // bitwise not 16 | // if (zy == 1) set y = 0 // 16-bit constant 17 | // if (ny == 1) set y = !y // bitwise not 18 | // if (f == 1) set out = x + y // integer 2's complement addition 19 | // if (f == 0) set out = x & y // bitwise and 20 | // if (no == 1) set out = !out // bitwise not 21 | // if (out == 0) set zr = 1 22 | // if (out < 0) set ng = 1 23 | 24 | `default_nettype none 25 | 26 | module ALUusr( 27 | input wire [15:0] x, // input x (16 bit) 28 | input wire [15:0] y, // input y (16 bit) 29 | input wire zx, // zero the x input? 30 | input wire nx, // negate the x input? 31 | input wire zy, // zero the y input? 32 | input wire ny, // negate the y input? 33 | input wire f, // compute out = x + y (if 1) or x & y (if 0) 34 | input wire no, // negate the out output? 35 | output wire [15:0] out, // 16-bit output 36 | output wire zr, // 1 if (out == 0), 0 otherwise 37 | output wire ng // 1 if (out < 0), 0 otherwise 38 | ); 39 | 40 | // your implementation comes here: 41 | 42 | // Mux16(a=x ,b=false ,sel=zx ,out=x1 ); 43 | // Not16(in=x1, out=notx1); 44 | // Mux16(a=x1,b=notx1,sel=nx ,out=x2 ); 45 | 46 | // Mux16(a=y ,b=false ,sel=zy ,out=y1 ); 47 | // Not16(in=y1,out=noty1); 48 | // Mux16(a=y1,b=noty1,sel=ny ,out=y2 ); 49 | 50 | // And16(a=x2 ,b=y2 ,out=andxy ); 51 | // Add16(a=x2 ,b=y2 ,out=addxy ); 52 | // Mux16(a=andxy,b=addxy,sel=f,out=xy); 53 | 54 | // Not16(in=xy,out=notxy); 55 | // Mux16(a=xy,b=notxy,sel=no,out[15]=tmp,out[0..7]=out07,out[8..15]=out815,out=out); 56 | 57 | // And(a=tmp,b=true,out=ng); 58 | // Or8Way(in=out07,out=tmp1); 59 | // Or8Way(in=out815,out=tmp2); 60 | // Or(a=tmp1,b=tmp2,out=tmp3); 61 | // Not(in=tmp3,out=zr); 62 | 63 | wire[15:0] x1; 64 | wire[15:0] x2; 65 | wire[15:0] notx1; 66 | Mux16 MUX16x(.a(x),.b(16'b0000000000000000),.sel(zx),.out(x1)); 67 | Not16 NOT16x(.in(x1),.out(notx1)); 68 | Mux16 MUX16x1(.a(x1),.b(notx1),.sel(nx),.out(x2)); 69 | 70 | wire[15:0] y1; 71 | wire[15:0] y2; 72 | wire[15:0] noty1; 73 | Mux16 MUX16y(.a(y),.b(16'b0000000000000000),.sel(zy),.out(y1)); 74 | Not16 NOT16y(.in(y1),.out(noty1)); 75 | Mux16 MUX16y1(.a(y1),.b(noty1),.sel(ny),.out(y2)); 76 | 77 | wire[15:0] andxy; 78 | wire[15:0] addxy; 79 | wire[15:0] xy; 80 | And16 AND16xy(.a(x2),.b(y2),.out(andxy)); 81 | Add16 ADD16xy(.a(x2),.b(y2),.out(addxy)); 82 | Mux16 MUX16andadd(.a(andxy),.b(addxy),.sel(f),.out(xy)); 83 | 84 | wire[15:0] notxy; 85 | Not16 NOT16xy(.in(xy),.out(notxy)); 86 | Mux16 MUX16xy(.a(xy),.b(notxy),.sel(no),.out(out)); 87 | wire tmp = out[15]; 88 | wire[7:0] out07= out[7:0]; 89 | wire[7:0] out815 = out[15:8]; 90 | 91 | wire tmp1; 92 | wire tmp2; 93 | wire tmp3; 94 | And AND(.a(tmp),.b(1'b1),.out(ng)); 95 | Or8Way OR8WAY07(.in(out07),.out(tmp1)); 96 | Or8Way OR8WAY815(.in(out815),.out(tmp2)); 97 | Or OR(.a(tmp1),.b(tmp2),.out(tmp3)); 98 | Not NOT(.in(tmp3),.out(zr)); 99 | 100 | endmodule 101 | -------------------------------------------------------------------------------- /02/ALU.v: -------------------------------------------------------------------------------- 1 | /** 2 | * The ALU (Arithmetic Logic Unit). 3 | * Computes one of the following functions: 4 | * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y, 5 | * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs, 6 | * according to 6 input bits denoted zx,nx,zy,ny,f,no. 7 | * In addition, the ALU computes two 1-bit outputs: 8 | * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0; 9 | * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0. 10 | */ 11 | 12 | // Implementation: the ALU logic manipulates the x and y inputs 13 | // and operates on the resulting values, as follows: 14 | // if (zx == 1) set x = 0 // 16-bit constant 15 | // if (nx == 1) set x = !x // bitwise not 16 | // if (zy == 1) set y = 0 // 16-bit constant 17 | // if (ny == 1) set y = !y // bitwise not 18 | // if (f == 1) set out = x + y // integer 2's complement addition 19 | // if (f == 0) set out = x & y // bitwise and 20 | // if (no == 1) set out = !out // bitwise not 21 | // if (out == 0) set zr = 1 22 | // if (out < 0) set ng = 1 23 | 24 | `default_nettype none 25 | `include "Mux16.v" 26 | `include "Not16.v" 27 | `include "And16.v" 28 | `include "Add16.v" 29 | `include "Or8Way.v" 30 | module ALU( 31 | input wire [15:0] x, // input x (16 bit) 32 | input wire [15:0] y, // input y (16 bit) 33 | input wire zx, // zero the x input? 34 | input wire nx, // negate the x input? 35 | input wire zy, // zero the y input? 36 | input wire ny, // negate the y input? 37 | input wire f, // compute out = x + y (if 1) or x & y (if 0) 38 | input wire no, // negate the out output? 39 | output wire [15:0] out, // 16-bit output 40 | output wire zr, // 1 if (out == 0), 0 otherwise 41 | output wire ng // 1 if (out < 0), 0 otherwise 42 | ); 43 | 44 | // your implementation comes here: 45 | 46 | // Mux16(a=x ,b=false ,sel=zx ,out=x1 ); 47 | // Not16(in=x1, out=notx1); 48 | // Mux16(a=x1,b=notx1,sel=nx ,out=x2 ); 49 | 50 | // Mux16(a=y ,b=false ,sel=zy ,out=y1 ); 51 | // Not16(in=y1,out=noty1); 52 | // Mux16(a=y1,b=noty1,sel=ny ,out=y2 ); 53 | 54 | // And16(a=x2 ,b=y2 ,out=andxy ); 55 | // Add16(a=x2 ,b=y2 ,out=addxy ); 56 | // Mux16(a=andxy,b=addxy,sel=f,out=xy); 57 | 58 | // Not16(in=xy,out=notxy); 59 | // Mux16(a=xy,b=notxy,sel=no,out[15]=tmp,out[0..7]=out07,out[8..15]=out815,out=out); 60 | 61 | // And(a=tmp,b=true,out=ng); 62 | // Or8Way(in=out07,out=tmp1); 63 | // Or8Way(in=out815,out=tmp2); 64 | // Or(a=tmp1,b=tmp2,out=tmp3); 65 | // Not(in=tmp3,out=zr); 66 | 67 | wire[15:0] x1; 68 | wire[15:0] x2; 69 | wire[15:0] notx1; 70 | Mux16 MUX16x(.a(x),.b(16'b0000000000000000),.sel(zx),.out(x1)); 71 | Not16 NOT16x(.in(x1),.out(notx1)); 72 | Mux16 MUX16x1(.a(x1),.b(notx1),.sel(nx),.out(x2)); 73 | 74 | wire[15:0] y1; 75 | wire[15:0] y2; 76 | wire[15:0] noty1; 77 | Mux16 MUX16y(.a(y),.b(16'b0000000000000000),.sel(zy),.out(y1)); 78 | Not16 NOT16y(.in(y1),.out(noty1)); 79 | Mux16 MUX16y1(.a(y1),.b(noty1),.sel(ny),.out(y2)); 80 | 81 | wire[15:0] andxy; 82 | wire[15:0] addxy; 83 | wire[15:0] xy; 84 | And16 AND16xy(.a(x2),.b(y2),.out(andxy)); 85 | Add16 ADD16xy(.a(x2),.b(y2),.out(addxy)); 86 | Mux16 MUX16andadd(.a(andxy),.b(addxy),.sel(f),.out(xy)); 87 | 88 | wire[15:0] notxy; 89 | Not16 NOT16xy(.in(xy),.out(notxy)); 90 | Mux16 MUX16xy(.a(xy),.b(notxy),.sel(no),.out(out)); 91 | wire tmp = out[15]; 92 | wire[7:0] out07= out[7:0]; 93 | wire[7:0] out815 = out[15:8]; 94 | 95 | wire tmp1; 96 | wire tmp2; 97 | wire tmp3; 98 | And AND(.a(tmp),.b(1'b1),.out(ng)); 99 | Or8Way OR8WAY07(.in(out07),.out(tmp1)); 100 | Or8Way OR8WAY815(.in(out815),.out(tmp2)); 101 | Or OR(.a(tmp1),.b(tmp2),.out(tmp3)); 102 | Not NOT(.in(tmp3),.out(zr)); 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /02/README.md: -------------------------------------------------------------------------------- 1 | ## 算术（ALU） 2 | 3 | ### 半加器 4 | 5 | 半加器是不考虑来自进位的一位加法器。用二进制表示： 6 | 7 | - 0 + 0 =00 8 | - 1 + 0 = 01 9 | - 0 + 1 = 01 10 | - 1 + 1 = 10 11 | 12 | 因为有两个输入和两个输出，可以写入 Fpga 进行测试。两个输入对应两个按钮，两个输出对应两个 led ，执行： 13 | 14 | ```bash 15 | yosys -p "read_verilog HalfAdder.v; synth_gowin -json HalfAdder.json" 16 | nextpnr-gowin --json HalfAdder.json --write pnrHalfAdder.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k-2i2o.cst 17 | gowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrHalfAdder.json 18 | 19 | openFPGALoader -b tangnano4k pack.fs 20 | ``` 21 | 22 | 然后按下按钮测试，注意按钮松开的时候为 1 。 23 | 24 | ### 全加器 25 | 26 | 全加器是考虑来自进位的一位加法器。简单的说就是三个一位相加。真值表如： 27 | 28 | | 输入 | 输出 | | | | 29 | | ---- | ---- | ---- | ---- | ----- | 30 | | C | A | B | sum | carry | 31 | | 0 | 0 | 0 | 0 | 0 | 32 | | 0 | 0 | 1 | 1 | 0 | 33 | | 0 | 1 | 0 | 1 | 0 | 34 | | 0 | 1 | 1 | 0 | 1 | 35 | | 1 | 0 | 0 | 1 | 0 | 36 | | 1 | 0 | 1 | 0 | 1 | 37 | | 1 | 1 | 0 | 0 | 1 | 38 | | 1 | 1 | 1 | 1 | 1 | 39 | 40 | 全加器可以用两个半加器和一个或门实现。 41 | 42 | ```verilog 43 | wire hsum; 44 | wire hcarry; 45 | HalfAdder HalfAdder1(.a(a),.b(b),.sum(hsum),.carry(hcarry)); 46 | wire hcarry2; 47 | HalfAdder HalfAdder2(.a(c),.b(hsum),.sum(sum),.carry(hcarry2)); 48 | Or OR(.a(hcarry),.b(hcarry2),.out(carry)); 49 | ``` 50 | 51 | - sum 很简单和 a + b + c 的 sum 相同。 52 | - carry 则有点麻烦，a + b 和 a + b 的 sum + c，有一个进位则 carry 为 1。 53 | 54 | ### 16 进制加法器 55 | 56 | 其实就是 15 个全加器和 1 个半加器，因为最低位没有进位故采用半加器，其余各位都有低一位来自的进位，最高位的进位舍弃，我们称为溢出。 57 | 58 | ### 算术器 59 | 60 | 先看看注释： 61 | 62 | ``` 63 | // if (zx == 1) set x = 0 // 16-bit constant 64 | // if (nx == 1) set x = !x // bitwise not 65 | // if (zy == 1) set y = 0 // 16-bit constant 66 | // if (ny == 1) set y = !y // bitwise not 67 | // if (f == 1) set out = x + y // integer 2's complement addition 68 | // if (f == 0) set out = x & y // bitwise and 69 | // if (no == 1) set out = !out // bitwise not 70 | // if (out == 0) set zr = 1 71 | // if (out < 0) set ng = 1 72 | ``` 73 | 74 | - 当 zx 等于 1 ，x 常为 16 进制的 0 75 | - 当 nx 等于 1，x 取反。 76 | - 当 zy 等于 1 ，y 常为 16 进制的 0 77 | - 当 ny 等于 1，y 取反。 78 | - 当 f 等于 1，输出 x + y 79 | - 当 f 等于 0，输出 x & y 80 | - 当 no 等于 1，输出取反。 81 | - 当输出等于 0，zr 设为 1 82 | - 当输出小于 0，ng 设为 1 83 | 84 | 减法、乘除法都可以转化成加法。逻辑运算也都可以转化为与非门（!(x & y) 就是与非门，可以通过设 f=0,no=1 来构建）。所以实现上述电路就可以计算所以算术。 85 | 86 | ```verilog 87 | wire[15:0] x1; 88 | wire[15:0] x2; 89 | wire[15:0] notx1; 90 | Mux16 MUX16x(.a(x),.b(16'b0000000000000000),.sel(zx),.out(x1)); 91 | Not16 NOT16x(.in(x1),.out(notx1)); 92 | Mux16 MUX16x1(.a(x1),.b(notx1),.sel(nx),.out(x2)); 93 | 94 | wire[15:0] y1; 95 | wire[15:0] y2; 96 | wire[15:0] noty1; 97 | Mux16 MUX16y(.a(y),.b(16'b0000000000000000),.sel(zy),.out(y1)); 98 | Not16 NOT16y(.in(y1),.out(noty1)); 99 | Mux16 MUX16y1(.a(y1),.b(noty1),.sel(ny),.out(y2)); 100 | 101 | wire[15:0] andxy; 102 | wire[15:0] addxy; 103 | wire[15:0] xy; 104 | And16 AND16xy(.a(x2),.b(y2),.out(andxy)); 105 | Add16 ADD16xy(.a(x2),.b(y2),.out(addxy)); 106 | Mux16 MUX16andadd(.a(andxy),.b(addxy),.sel(f),.out(xy)); 107 | 108 | wire[15:0] notxy; 109 | Not16 NOT16xy(.in(xy),.out(notxy)); 110 | Mux16 MUX16xy(.a(xy),.b(notxy),.sel(no),.out(out)); 111 | wire tmp = out[15]; 112 | wire[7:0] out07= out[7:0]; 113 | wire[7:0] out815 = out[15:8]; 114 | 115 | wire tmp1; 116 | wire tmp2; 117 | wire tmp3; 118 | And AND(.a(tmp),.b(1'b1),.out(ng)); 119 | Or8Way OR8WAY07(.in(out07),.out(tmp1)); 120 | Or8Way OR8WAY815(.in(out815),.out(tmp2)); 121 | Or OR(.a(tmp1),.b(tmp2),.out(tmp3)); 122 | Not NOT(.in(tmp3),.out(zr)); 123 | ``` 124 | 125 | 25 行之前很好理解，按部就班实现，不过要注意优先级。 126 | 127 | ```verilog 128 | wire tmp = out[15]; 129 | wire[7:0] out07= out[7:0]; 130 | wire[7:0] out815 = out[15:8]; 131 | 132 | wire tmp1; 133 | wire tmp2; 134 | wire tmp3; 135 | /*line 8*/ And AND(.a(tmp),.b(1'b1),.out(ng)); 136 | Or8Way OR8WAY07(.in(out07),.out(tmp1)); 137 | Or8Way OR8WAY815(.in(out815),.out(tmp2)); 138 | Or OR(.a(tmp1),.b(tmp2),.out(tmp3)); 139 | Not NOT(.in(tmp3),.out(zr)); 140 | ``` 141 | 142 | 1. 按补码规定，最高位为 1 则整个数小于 0，所以第 8 行通过判断最高位是否为 1 来判断整个数是否小于 0。 143 | 2. 9、10、11 其实判断每位是否不为 0，如果每一位都为 0 则 tmp3 为 0。zr 是 tmp3 取反。 144 | 145 | > 代码：https://github.com/buhe/bugu-computer/tree/master/02 -------------------------------------------------------------------------------- /04/CPU_tb.v: -------------------------------------------------------------------------------- 1 | `include "Mux16.v" 2 | `include "Register.v" 3 | `include "ALU.v" 4 | `include "PC.v" 5 | `include "Not16.v" 6 | `include "And16.v" 7 | `include "Add16.v" 8 | `include "Or8Way.v" 9 | `include "And.v" 10 | `include "Not.v" 11 | `include "Or.v" 12 | 13 | `include "CPU.v" 14 | `default_nettype none 15 | module CPU_tb(); 16 | 17 | integer file; 18 | reg clk = 1; 19 | reg [15:0] inM=0; 20 | reg [15:0] instruction=0; 21 | reg reset=0; 22 | wire signed [15:0] outM; 23 | wire writeM; 24 | wire [15:0] addressM; 25 | wire [15:0] pc; 26 | reg[9:0] t = 10'b0; 27 | 28 | CPU CPU( 29 | .clk(clk), 30 | .inM(inM), 31 | .instruction(instruction), 32 | .reset(reset), 33 | .outM(outM), 34 | .writeM(writeM), 35 | .addressM(addressM), 36 | .pc(pc) 37 | ); 38 | 39 | 40 | always #1 clk = ~clk; 41 | 42 | task display; 43 | #1 $fwrite(file, "|%6d|%6d|%16b| %1b |%6d| %1b |%6d|%6d|\n",t,inM,instruction,reset,outM,writeM,addressM[14:0],pc); 44 | endtask 45 | 46 | initial begin 47 | $dumpfile("CPU_tb.vcd"); 48 | $dumpvars(0, CPU_tb); 49 | file = $fopen("CPU.out","w"); 50 | $fwrite(file, "| time | inM | instruction |reset| outM |writeM|addres| pc |\n"); 51 | 52 | 53 | instruction = 16'b0011000000111001; // @12345 54 | display(); 55 | t=1;display(); 56 | 57 | instruction = 16'b1110110000010000; // D=A 58 | display(); 59 | t=2;display(); 60 | 61 | instruction = 16'b0101101110100000; // @23456 62 | display(); 63 | t=3;display(); 64 | 65 | instruction = 16'b1110000111110000; // AD=A-D 66 | inM = 11111; 67 | display(); 68 | t=4;display(); 69 | 70 | instruction = 16'b0000001111101011; // @1003 71 | display(); 72 | t=5;display(); 73 | 74 | instruction = 16'b1110001100001000; // M=D 75 | display(); 76 | t=6;display(); 77 | 78 | instruction = 16'b0000001111101100; // @1004 79 | display(); 80 | t=7;display(); 81 | 82 | instruction = 16'b1110001110011000; // MD=D-1 83 | display(); 84 | t=8;display(); 85 | 86 | instruction = 16'b0000001111101000; // @1000 87 | display(); 88 | t=9;display(); 89 | 90 | instruction = 16'b1111010011110000; // AD=D-M 91 | display(); 92 | t=10;display(); 93 | 94 | instruction = 16'b0000000000001110; // @14 95 | display(); 96 | t=11;display(); 97 | 98 | instruction = 16'b1110001100000100; // D;jlt 99 | display(); 100 | t=12;display(); 101 | 102 | instruction = 16'b0000001111100111; // @999 103 | display(); 104 | t=13;display(); 105 | 106 | instruction = 16'b1111110111100000; // A=M+1 107 | display(); 108 | t=14;display(); 109 | 110 | instruction = 16'b1110001100101000; // AM=D 111 | display(); 112 | t=15;display(); 113 | 114 | instruction = 16'b0000000000010101; // @21 115 | display(); 116 | t=16;display(); 117 | 118 | instruction = 16'b1110011111000010; // D+1;jeq 119 | display(); 120 | t=17;display(); 121 | 122 | instruction = 16'b0000000000000010; // @2 123 | display(); 124 | t=18;display(); 125 | 126 | instruction = 16'b1110000010111000; // AMD=D+A 127 | display(); 128 | t=19;display(); 129 | 130 | // #2 instruction = 16'b0000001111101000; // @1000 131 | // display(); 132 | 133 | // #2 instruction = 16'b1110111010010000; // D=-1 134 | // display(); 135 | 136 | // #2 instruction = 16'b1110001100000001; // D;JGT 137 | // display(); 138 | 139 | // #2 instruction = 16'b1110001100000010; // D;JEQ 140 | // display(); 141 | 142 | // #2 instruction = 16'b1110001100000011; // D;JGE 143 | // display(); 144 | 145 | // #2 instruction = 16'b1110001100000100; // D;JLT 146 | // display(); 147 | 148 | // #2 instruction = 16'b1110001100000101; // D;JNE 149 | // display(); 150 | 151 | // #2 instruction = 16'b1110001100000110; // D;JLE 152 | // display(); 153 | 154 | // #2 instruction = 16'b1110001100000111; // D;JMP 155 | // display(); 156 | 157 | // #2 instruction = 16'b1110101010010000; // D=0 158 | // display(); 159 | 160 | // #2 instruction = 16'b1110001100000001; // D;JGT 161 | // display(); 162 | 163 | // #2 instruction = 16'b1110001100000010; // D;JEQ 164 | // display(); 165 | 166 | // #2 instruction = 16'b1110001100000011; // D;JGE 167 | // display(); 168 | 169 | // #2 instruction = 16'b1110001100000100; // D;JLT 170 | // display(); 171 | 172 | // #2 instruction = 16'b1110001100000101; // D;JNE 173 | // display(); 174 | 175 | // #2 instruction = 16'b1110001100000110; // D;JLE 176 | // display(); 177 | 178 | // #2 instruction = 16'b1110001100000111; // D;JMP 179 | // display(); 180 | 181 | // #2 instruction = 16'b1110111111010000; // D=1 182 | // display(); 183 | 184 | // #2 instruction = 16'b1110001100000001; // D;JGT 185 | // display(); 186 | 187 | // #2 instruction = 16'b1110001100000010; // D;JEQ 188 | // display(); 189 | 190 | // #2 instruction = 16'b1110001100000011; // D;JGE 191 | // display(); 192 | 193 | // #2 instruction = 16'b1110001100000100; // D;JLT 194 | // display(); 195 | 196 | // #2 instruction = 16'b1110001100000101; // D;JNE 197 | // display(); 198 | 199 | // #2 instruction = 16'b1110001100000110; // D;JLE 200 | // display(); 201 | 202 | // #2 instruction = 16'b1110001100000111; // D;JMP 203 | // display(); 204 | 205 | // #2 reset=1; 206 | // display(); 207 | 208 | // #2 instruction = 16'b0111111111111111; // @32767 209 | // #2 reset=0; 210 | // display(); 211 | 212 | 213 | $finish; 214 | end 215 | endmodule 216 | -------------------------------------------------------------------------------- /04/CPU.v: -------------------------------------------------------------------------------- 1 | /** 2 | * The Hack CPU (Central Processing unit), consisting of an ALU, 3 | * two registers named A and D, and a program counter named PC. 4 | * The CPU is designed to fetch and execute instructions written in 5 | * the Hack machine language. In particular, functions as follows: 6 | * Executes the inputted instruction according to the Hack machine 7 | * language specification. The D and A in the language specification 8 | * refer to CPU-resident registers, while M refers to the external 9 | * memory location addressed by A, i.e. to Memory[A]. The inM input 10 | * holds the value of this location. If the current instruction needs 11 | * to write a value to M, the value is placed in outM, the address 12 | * of the target location is placed in the addressM output, and the 13 | * writeM control bit is asserted. (When writeM==0, any value may 14 | * appear in outM). The outM and writeM outputs are combinational: 15 | * they are affected instantaneously by the execution of the current 16 | * instruction. The addressM and pc outputs are clocked: although they 17 | * are affected by the execution of the current instruction, they commit 18 | * to their new values only in the next time step. If reset==1 then the 19 | * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 20 | * than to the address resulting from executing the current instruction. 21 | */ 22 | 23 | `default_nettype none 24 | module CPU( 25 | input clk, 26 | input [15:0] inM, // M value input (M = contents of RAM[A]) 27 | input [15:0] instruction, // Instruction for execution 28 | input reset, // Signals whether to re-start the current 29 | // program (reset==1) or continue executing 30 | // the current program (reset==0). 31 | 32 | output [15:0] outM, // M value output 33 | output writeM, // Write to M? 34 | output [15:0] addressM, // Address in data memory (of M) to read 35 | output [15:0] pc // address of next instruction 36 | ); 37 | 38 | // your implementation comes here: 39 | 40 | // And(a=instruction[15] ,b=instruction[5] ,out=d1 ); A 41 | // And(a=instruction[15] ,b=instruction[4] ,out=d2 ); D 42 | // And(a=instruction[15] ,b=instruction[3] ,out=d3,out=writeM ); M 43 | // And(a=instruction[15] ,b=instruction[2] ,out=j1 ); 44 | // And(a=instruction[15] ,b=instruction[1] ,out=j2 ); 45 | // And(a=instruction[15] ,b=instruction[0] ,out=j3 ); 46 | 47 | // //A Register 48 | // Mux16(a=instruction ,b=outputM ,sel=instruction[15] ,out=Ainput ); 49 | // Not(in=instruction[15],out=Aload1); 50 | // Or(a=d1,b=Aload1,out=Aload); 51 | // ARegister(in=Ainput ,load=Aload ,out=Areg, out[0..14]= addressM ); 52 | 53 | // //D Register 54 | // DRegister(in=outputM ,load=d2 ,out=Dreg ); 55 | 56 | // //ALU 57 | // Mux16(a=Areg,b=inM,sel=instruction[12],out=y); when a == 1 opr M else opr A 58 | // ALU(x=Dreg ,y=y ,zx=instruction[11] ,nx=instruction[10] ,zy=instruction[9] ,ny=instruction[8] ,f=instruction[7] ,no=instruction[6] ,out=outputM ,out=outM,zr=zr ,ng=ng ); 59 | 60 | // //PC 61 | // And(a=ng,b=j1,out=tmp1); < 0 62 | // And(a=zr,b=j2,out=tmp2); == 0 63 | // Not(in=zr,out=notzr); 64 | // Not(in=ng,out=notng); 65 | // And(a=notzr,b=notng,out=ps); > 0 66 | // And(a=ps,b=j3,out=tmp3); 67 | // Or(a=tmp1,b=tmp2,out=tmp); 68 | // Or(a=tmp,b=tmp3,out=jump); when != 000 jump 69 | // Not(in=jump,out=inc); 70 | // PC(in=Areg ,load=jump ,inc=inc ,reset=reset ,out[0..14]=pc ); 71 | 72 | wire d1; 73 | wire d2; 74 | wire d3; 75 | wire j1; 76 | wire j2; 77 | wire j3; 78 | And AND1(.a(instruction[15]),.b(instruction[5]),.out(d1)); 79 | And AND2(.a(instruction[15]),.b(instruction[4]),.out(d2)); 80 | And AND3(.a(instruction[15]),.b(instruction[3]),.out(d3)); 81 | assign writeM = d3; 82 | And AND4(.a(instruction[15]),.b(instruction[2]),.out(j1)); 83 | And AND5(.a(instruction[15]),.b(instruction[1]),.out(j2)); 84 | And AND6(.a(instruction[15]),.b(instruction[0]),.out(j3)); 85 | 86 | // A reg 87 | wire[15:0] outputM; 88 | wire[15:0] Ainput; 89 | wire Aload1; 90 | wire Aload; 91 | wire[15:0] Areg; 92 | Mux16 MUX16a(.a(instruction),.b(outputM),.sel(instruction[15]),.out(Ainput)); 93 | Not NOT1(.in(instruction[15]), .out(Aload1)); 94 | Or OR1(.a(Aload1),.b(d1),.out(Aload)); 95 | Register REGISTERa(.in(Ainput),.load(Aload),.out(Areg), .clk(clk)); 96 | assign addressM = Areg; 97 | 98 | // D reg 99 | wire[15:0] Dreg; 100 | Register REGISTER1d(.in(outputM),.load(d2),.out(Dreg), .clk(clk)); 101 | 102 | // ALU 103 | wire[15:0] y; 104 | wire zr; 105 | wire ng; 106 | Mux16 MUX16alu(.a(Areg),.b(inM),.sel(instruction[12]),.out(y)); 107 | 108 | ALUusr ALU( 109 | .x(Dreg), 110 | .y(y), 111 | .zx(instruction[11]), 112 | .nx(instruction[10]), 113 | .zy(instruction[9]), 114 | .ny(instruction[8]), 115 | .f(instruction[7]), 116 | .no(instruction[6]), 117 | .out(outputM), 118 | .zr(zr), 119 | .ng(ng) 120 | ); 121 | assign outM = outputM; 122 | 123 | // PC 124 | wire tmp1; 125 | wire tmp2; 126 | wire tmp3; 127 | wire notzr; 128 | wire notng; 129 | wire ps; 130 | wire tmp; 131 | wire jump; 132 | wire inc; 133 | And ANDpc1(.a(ng),.b(j1),.out(tmp1)); 134 | And ANDpc2(.a(zr),.b(j2),.out(tmp2)); 135 | Not NOTpc1(.in(zr), .out(notzr)); 136 | Not NOTpc2(.in(ng), .out(notng)); 137 | And ANDpc3(.a(notzr),.b(notng),.out(ps)); 138 | And ANDpc4(.a(ps),.b(j3),.out(tmp3)); 139 | Or ORpc1(.a(tmp1),.b(tmp2),.out(tmp)); 140 | Or ORpc2(.a(tmp),.b(tmp3),.out(jump)); 141 | Not NOTpc3(.in(jump), .out(inc)); 142 | PC PC1( 143 | .clk(clk), 144 | .reset(reset), 145 | .load(jump), 146 | .inc(inc), 147 | .in(Areg), 148 | .out(pc) 149 | ); 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /00/README.md: -------------------------------------------------------------------------------- 1 | ## 准备 2 | 3 | 作为一个软件工程师，计算机是我们赖以生存的工具，所有我们开发的软件都在计算机上执行，那么通过与或非等最基础的门电路构建一个计算机一方面可以更深入的了解计算机，一方面也可以更好的开发软件。 4 | 5 | 基于门电路从头开始当然可以，但连接电路比较费劲，所以这里采用了 verilog + Fpga 的形式。verilog + Fpga 本质就是自己设计连接电路，和自己从头基于门电路连接一样。 6 | 7 | 第一个项目来搭建开发环境和构建最基础的几个电路。 8 | 9 | ### 硬件 10 | 11 | - tangnano 4k 12 | 13 | 硬件采用国产的 tangnano 而没有采用国外大厂的。一方面为了支持国产 IC 一方面中国是以制造业为主的国家、国产的 Fpga 性价比较高。 14 | 15 | ### 搭建环境 16 | 17 | 常见的 EDA 工具一般仅支持 windows 和 linux 不支持 macos，这里不对专有和开源软件的优劣做对比，以免引战。在本教程中我尽量使用开源软件而不使用厂家的专有软件。 18 | 19 | ```bash 20 | # 安装综合的工具 21 | brew install yosys 22 | pip install apycula 23 | brew install eigen 24 | 25 | # 安装 gowin 的布线工具 26 | git clone git@github.com:YosysHQ/nextpnr.git 27 | cmake . -DARCH=gowin 28 | make -j$(nproc) 29 | sudo make install 30 | # 参考 https://github.com/YosysHQ/nextpnr#nextpnr-gowin 31 | 32 | # 安装刷入 Fpga 的工具 33 | brew install openfpgaloader --HEAD 34 | 35 | # 安装编译成可仿真的文件 36 | brew install icarus-verilog 37 | 38 | # 安装查看波形的软件 39 | brew install --cask gtkwave 40 | ``` 41 | 42 | > 综合和布线其实就是生成电路，和物理的连接电路一样，具体的 Fpga 的原理请参考 https://zh.wikipedia.org/zh-tw/%E7%8E%B0%E5%9C%BA%E5%8F%AF%E7%BC%96%E7%A8%8B%E9%80%BB%E8%BE%91%E9%97%A8%E9%98%B5%E5%88%97 。 43 | 44 | ### Nand 45 | 46 | Nand 又称为与非门，其他门一般通过它来构建，是基本门电路，原因如下： 47 | 48 | 1. 考虑电子元件的成本，也许从逻辑上来看与非门和或非门比与门和非门更复杂，但是实际上由于Mos管的物理结构，实现与非门和或非门需要的元件其实更少，成本更低，而简单的与门和或门其实在结构上比前者更复杂。 49 | 2. 或非门和与非门具有逻辑完备性，任何一个门通过组合可以实现任意电路，而与门和或门不具有这样的能力 50 | 3. 仍然和电子元件的物理结构有关，与非门和或非门实际运行效率比与门和或门更高。 51 | 52 | 与非门的真值表： 53 | 54 | | A | B | A NAND B | 55 | | ---- | ---- | -------- | 56 | | 0 | 0 | 1 | 57 | | 0 | 1 | 1 | 58 | | 1 | 0 | 1 | 59 | | 1 | 1 | 0 | 60 | 61 | ### 非 62 | 63 | 非门是用 Nand（与非门）实现的，代码如下： 64 | 65 | ```verilog 66 | /** 67 | * Not gate: 68 | * out = not in 69 | */ 70 | `include "Nand.v" 71 | `default_nettype none 72 | 73 | module Not( 74 | input in, 75 | output out 76 | ); 77 | Nand NAND(.a(in), .b(1'b1), .out(out)); 78 | endmodule 79 | ``` 80 | 81 | 非门顾名思义就是取反操作，0 转成 1 ， 1 转成 0 。所以只要输入和 1 与然后取反就可以了，利用与非门很容易做到。 82 | 83 | ### 或 84 | 85 | 或门利用非门和与非门实现，a or b == not (not a and not b)，如果想了解这个公式怎么来的，请查阅“德摩根定律”。 86 | 87 | ```verilog 88 | /** 89 | * Or gate: 90 | * out = 1 if (a == 1 or b == 1) 91 | * 0 otherwise 92 | */ 93 | `default_nettype none 94 | module Or( 95 | input a, 96 | input b, 97 | output out 98 | ); 99 | wire nota; 100 | wire notb; 101 | Not NOT1(.in(a), .out(nota)); 102 | Not NOT2(.in(b), .out(notb)); 103 | Nand NAND(.a(nota), .b(notb), .out(out)); 104 | 105 | 106 | endmodule 107 | ``` 108 | 109 | ### 与 110 | 111 | 与门很简单，与非门的结果取反就行了。 112 | 113 | ```verilog 114 | /** 115 | * And gate: 116 | * out = 1 if (a == 1 and b == 1) 117 | * 0 otherwise 118 | */ 119 | 120 | `default_nettype none 121 | 122 | module And( 123 | input a, 124 | input b, 125 | output out 126 | ); 127 | wire notaandb; 128 | 129 | // your implementation comes here: 130 | Nand NAND(.a(a), .b(b), .out(notaandb)); 131 | Not NOT(.in(notaandb), .out(out)); 132 | 133 | 134 | endmodule 135 | ``` 136 | 137 | ### 异或 138 | 139 | 异或门是第一个有挑战的门电路，异或门的意义是两个输入不同结果为 1 ，w1 和 w2 分别断言 a = 1, b = 0 和 a = 0 , b = 1 ，w1 or w2 是上述有一个成立结果就为 1。因为 a b 只有两种取指，上述描述就覆盖了所有情况。 140 | 141 | ```verilog 142 | /** 143 | * Xor (exclusive or) gate: 144 | * If a<>b out=1 else out=0. 145 | */ 146 | `include "Not.v" 147 | `include "And.v" 148 | `include "Or.v" 149 | `default_nettype none 150 | 151 | module Xor( 152 | input wire a, 153 | input wire b, 154 | output wire out 155 | ); 156 | wire nota; //new wire must be declared 157 | wire notb; 158 | Not NOT1(.in(a), .out(nota)); //NOT1 is instance name 159 | Not NOT2(.in(b), .out(notb)); 160 | 161 | wire w1; 162 | wire w2; 163 | And AND1(.a(a),.b(notb),.out(w1)); 164 | And AND2(.a(nota),.b(b),.out(w2)); 165 | 166 | Or OR(.a(w1),.b(w2),.out(out)); 167 | endmodule 168 | ``` 169 | 170 | 真值表如下： 171 | 172 | | A | B | A XOR B | 173 | | ---- | ---- | ------- | 174 | | 0 | 0 | 0 | 175 | | 0 | 1 | 1 | 176 | | 1 | 0 | 1 | 177 | | 1 | 1 | 0 | 178 | 179 | ### 激励 180 | 181 | 所谓激励和软件工程师的单元测试差不多，以下激励就是用来测试异或门的，很好理解。 182 | 183 | a = ... b= ... 就是给 a b 赋值来测试在不同取值下的结果。结果通过 display 写入Xor.out 文件中，波形写入 Xor_tb.vcd 中，待会介绍波形。 184 | 185 | ```verilog 186 | `include "Xor.v" 187 | `default_nettype none 188 | module Xor_tb(); 189 | 190 | integer file; 191 | 192 | reg a = 0; 193 | reg b = 0; 194 | wire out; 195 | 196 | Xor XOR( 197 | .a(a), 198 | .b(b), 199 | .out(out) 200 | ); 201 | 202 | task display; 203 | #1 $fwrite(file, "| %1b | %1b | %1b |\n", a,b,out); 204 | endtask 205 | 206 | initial begin 207 | $dumpfile("Xor_tb.vcd"); 208 | $dumpvars(0, Xor_tb); 209 | file = $fopen("Xor.out","w"); 210 | $fwrite(file, "| a | b |out|\n"); 211 | 212 | a=0;b=0; 213 | display(); 214 | 215 | a=0;b=1; 216 | display(); 217 | 218 | a=1;b=0; 219 | display(); 220 | 221 | a=1;b=1; 222 | display(); 223 | $finish(); 224 | end 225 | 226 | endmodule 227 | ``` 228 | 229 | 230 | 231 | ### 编译 232 | 233 | 编译 Xor_tb.v，有编译错误在这步就会打印出来。 234 | 235 | ```bash 236 | iverilog -o Xor_tb.vvp Xor_tb.v 237 | ``` 238 | 239 | ### 仿真（模拟） 240 | 241 | 所谓仿真其实就是模拟，仿真其实就是模拟硬件，在不同的输入（信号）下展现不同的波形。 242 | 243 | ```bash 244 | vvp sample_tb.vvp 245 | open -a gtkwave 246 | ``` 247 | 248 | 使用 gtkwave 查看波形，右键点击Xor_tb ，选择 a b out ，然后 append ，删除内部变量。可以看到当 a b 不同结果为 1 （高电平）。 249 | 250 | #### ![Xor](https://tva1.sinaimg.cn/large/e6c9d24egy1h2sll4iicfj20x40abgmv.jpg) 251 | 252 | #### 比较 253 | 254 | *.cmp 是提供的比较文件， *.out 是我们执行仿真产生的结果文件。二者应该是相同的，采用这种方式来断言我们的程序写的对不对。 255 | 256 | ```bash 257 | diff Xor.out Xor.cmp 258 | ``` 259 | 260 | 如果程序写的对什么也不输出，否则输出不同的地方。 261 | 262 | ### 上传到 tangnano 263 | 264 | #### 综合和布线 265 | 266 | 综合和布线就是通过 verilog 产生电路的过程。 267 | 268 | ```bash 269 | yosys -p "read_verilog Xor.v; synth_gowin -json Xor.json" 270 | ``` 271 | 272 | 综合比较简单，布线需要引入所谓的约束文件： 273 | 274 | ``` 275 | IO_LOC "out" 10; 276 | IO_LOC "a" 15; 277 | IO_LOC "b" 14; 278 | ``` 279 | 280 | 14 和 15 是 tangnano 的两个按钮，分别被绑定到了 a b ，10 是 led 灯。需要注意的是按钮松开的时候是 1 ，按下是 0 。约束文件把程序中的变量绑定到了实际的物理硬件，改变物理量就改变了变量。 281 | 282 | ```bash 283 | nextpnr-gowin --json Xor.json --write pnrXor.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k.cst 284 | ``` 285 | 286 | 最后生成二进制文件。 287 | 288 | ```bash 289 | gowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrXor.json 290 | ``` 291 | 292 | #### 写入硬件 293 | 294 | 刷入 Fpga 。 295 | 296 | ```bash 297 | openFPGALoader -b tangnano4k pack.fs 298 | ``` 299 | 300 | #### 测试 301 | 302 | 实际按下按钮试试。当按钮的状态不同时，结果为 1 ，反之结果为 0。完成了异或门。下面是视频，点击即可。 303 | 304 | ### 结果 305 | [](https://youtube.com/shorts/S9ERI2q2dWQ?feature=share) 306 | 307 | 308 | 309 | > 代码：https://github.com/buhe/bugu-computer/tree/master/00 310 | -------------------------------------------------------------------------------- /04/README.md: -------------------------------------------------------------------------------- 1 | ## 组装 2 | 3 | ### CPU 4 | 5 | 硬件和机器语言某种程度上是一一对应的，先确定机器语言再根据机器语言设计对应的硬件。 6 | 7 | nand2tetris 的机器语言很简单，分为 A 指令和 C 指令，A 指令主要用来指定数字放进 A 寄存器中，C 指令用来访存，计算等。规范如下： 8 | 9 | ![n2t_4_4](https://tva1.sinaimg.cn/large/e6c9d24egy1h2yslot438j20gl03pglu.jpg) 10 | 11 | 12 | 13 | ![n2t_4_5](https://tva1.sinaimg.cn/large/e6c9d24egy1h2ysm1labhj20hb04jaae.jpg) 14 | 15 | 规范没有什么特别的，人为设计的，指令等长、精简。 16 | 17 | #### 操作目标和跳转规范 18 | 19 | 20 | ![n2t_4_7](https://tva1.sinaimg.cn/large/e6c9d24egy1h2ysnb6oboj20gy0620te.jpg) 21 | 22 | ![n2t_4_8](https://tva1.sinaimg.cn/large/e6c9d24egy1h2ysnji2tij20eq06kwev.jpg) 23 | 24 | 操作目标和跳转规则如上 25 | 26 | 27 | ```verilog 28 | wire d1; 29 | wire d2; 30 | wire d3; 31 | wire j1; 32 | wire j2; 33 | wire j3; 34 | And AND1(.a(instruction[15]),.b(instruction[5]),.out(d1)); 35 | And AND2(.a(instruction[15]),.b(instruction[4]),.out(d2)); 36 | And AND3(.a(instruction[15]),.b(instruction[3]),.out(d3)); 37 | assign writeM = d3; 38 | And AND4(.a(instruction[15]),.b(instruction[2]),.out(j1)); 39 | And AND5(.a(instruction[15]),.b(instruction[1]),.out(j2)); 40 | And AND6(.a(instruction[15]),.b(instruction[0]),.out(j3)); 41 | ``` 42 | 43 | 通过这些简单的 verilog 来确定操作目标和跳转规则，d1 ~ d3 指定操作目标，j1 ~ j3 指定跳转规则，额外的 d3 付给 writeM 指定是否写内存。 44 | 45 | #### A 寄存器 46 | 47 | ```verilog 48 | wire[15:0] outputM; 49 | wire[15:0] Ainput; 50 | wire Aload1; 51 | wire Aload; 52 | wire[15:0] Areg; 53 | Mux16 MUX16a(.a(instruction),.b(outputM),.sel(instruction[15]),.out(Ainput)); 54 | Not NOT1(.in(instruction[15]), .out(Aload1)); 55 | Or OR1(.a(Aload1),.b(d1),.out(Aload)); 56 | Register REGISTERa(.in(Ainput),.load(Aload),.out(Areg), .clk(clk)); 57 | assign addressM = Areg; 58 | ``` 59 | 60 | 首先判断是 A 还是 C 指令，A 指令就按原本写入 A 寄存器，C 指令则操作目标是否含有 A 寄存器，如果含有把 ALU 的计算结果写入 A 寄存器。 61 | 62 | #### D 寄存器 63 | 64 | ```verilog 65 | wire[15:0] Dreg; 66 | Register REGISTER1d(.in(outputM),.load(d2),.out(Dreg), .clk(clk)); 67 | ``` 68 | 69 | 如果操作目标含有 D 寄存器，则 ALU 的计算结果赋给 D 寄存器。 70 | 71 | #### ALU 72 | 73 | ```verilog 74 | wire[15:0] y; 75 | wire zr; 76 | wire ng; 77 | Mux16 MUX16alu(.a(Areg),.b(inM),.sel(instruction[12]),.out(y)); 78 | ALU ALU( 79 | .x(Dreg), 80 | .y(y), 81 | .zx(instruction[11]), 82 | .nx(instruction[10]), 83 | .zy(instruction[9]), 84 | .ny(instruction[8]), 85 | .f(instruction[7]), 86 | .no(instruction[6]), 87 | .out(outputM), 88 | .zr(zr), 89 | .ng(ng) 90 | ); 91 | assign outM = outputM; 92 | ``` 93 | 94 | ![n2t_4_6](https://tva1.sinaimg.cn/large/e6c9d24egy1h2yt9ep6r9j20fa0d7aas.jpg) 95 | 96 | 根据指令的 12 ~ 6 位，决定 ALU 的计算规则。 97 | 98 | #### PC 99 | 100 | ```verilog 101 | wire tmp1; 102 | wire tmp2; 103 | wire tmp3; 104 | wire notzr; 105 | wire notng; 106 | wire ps; 107 | wire tmp; 108 | wire jump; 109 | wire inc; 110 | And ANDpc1(.a(ng),.b(j1),.out(tmp1)); 111 | And ANDpc2(.a(zr),.b(j2),.out(tmp2)); 112 | Not NOTpc1(.in(zr), .out(notzr)); 113 | Not NOTpc2(.in(ng), .out(notng)); 114 | And ANDpc3(.a(notzr),.b(notng),.out(ps)); 115 | And ANDpc4(.a(ps),.b(j3),.out(tmp3)); 116 | Or ORpc1(.a(tmp1),.b(tmp2),.out(tmp)); 117 | Or ORpc2(.a(tmp),.b(tmp3),.out(jump)); 118 | Not NOTpc3(.in(jump), .out(inc)); 119 | PC PC1( 120 | .clk(clk), 121 | .reset(reset), 122 | .load(jump), 123 | .inc(inc), 124 | .in(Areg), 125 | .out(pc) 126 | ); 127 | ``` 128 | 129 | 使用 PC 的逻辑看似复杂，其实理解了想要干什么就简单了。当判断大于 0 的时候结果刚好大于 0，判断等于 0 时刚好等于 0，判断小于 0 时刚好小于 0 ，有一种情况满足则赋值 jump 为 1 ，否则 inc 为 1，然后通通给 PC ，结果就是：跳转的时候给 PC 赋值，其他情况 PC 加 1 。 130 | 131 | ### 内存 132 | 133 | #### 布局 134 | 135 | 136 | |address | memory|R/W|function| 137 | |-|-|-|-| 138 | |0-2047| RAM|R/W|R0--R15, static, stack, heap| 139 | | 8192 - 第 14 位 | but - 16 位 |R/W|0 = button pressed, 1 = button released| 140 | | 8193 - 第 14，1 位 | led - 16 位 |R/W|0 = led off, 1 = led on| 141 | 142 | 通过判断第 14 位，确定是访问 RAM 还是映射 IO 。 143 | 144 | ```verilog 145 | DMux DMUX1( 146 | .in(load), 147 | .sel(address[13]), 148 | .a(loadRAM), 149 | .b(loadIO) 150 | ); 151 | ``` 152 | 153 | 进而判断第 1 位，确定是访问按钮还是 LED 。 154 | 155 | ```verilog 156 | DMux DMUX2( 157 | .in(loadIO), 158 | .sel(address[0]), 159 | .a(loadBtn), 160 | .b(loadLed) 161 | ); 162 | ``` 163 | 164 | 通过抽象按钮和 LED 简化逻辑 165 | 166 | ```verilog 167 | // button - only read 168 | wire[15:0] outBtn; 169 | Btn BTN(.out(outBtn), .btn(btn)); 170 | // led - only write 171 | wire[15:0] outLed; 172 | Led LED(.clk(clk), .in(in), .out(outLed), .load(loadLed), .led(led)); 173 | ``` 174 | 175 | 按钮的 verilog，当 btn 设为 0 则 out 为 16'b0000000000000000，反之为 16'b0000000000000001 。可见返回值依赖 btn 的值。 176 | 177 | ```verilog 178 | `default_nettype none 179 | module Btn( 180 | input btn, 181 | output wire[15:0] out 182 | ); 183 | Mux16 MUX161( 184 | .a(16'b0000000000000000), 185 | .b(16'b0000000000000001), 186 | .sel(btn), 187 | .out(out) 188 | ); 189 | endmodule 190 | ``` 191 | 192 | LED 的 verilog ，如果 load 为 1 则 in 的第一位替换 out 的第一位，反之则保留上一个状态，这里有个副作用是 assign led = prev; ，把当前的状态赋给 led 变量，进而改变 led 。然后把当前状态保存在 DFF 中。最后根据 out 的第一位返回 out 。 193 | 194 | ```verilog 195 | `default_nettype none 196 | module Led( 197 | input clk, 198 | input wire load, 199 | output wire led, 200 | output wire[15:0] out, 201 | input wire[15:0] in 202 | ); 203 | wire prev; 204 | Mux MUX(.a(outLow),.b(in[0]),.sel(load),.out(prev)); 205 | assign led = prev; 206 | wire outLow; 207 | DFFusr DFF1(.clk(clk),.in(prev),.out(outLow)); 208 | 209 | Mux16 MUX161( 210 | .a(16'b0000000000000000), 211 | .b(16'b0000000000000001), 212 | .sel(outLow), 213 | .out(out) 214 | ); 215 | endmodule 216 | ``` 217 | 218 | 最后根据地址的第 14 位和第一位确定 memory 的最终返回值 219 | 220 | ```verilog 221 | Mux16 MUX161( 222 | .a(outBtn), 223 | .b(outLed), 224 | .sel(address[0]), 225 | .out(tmp) 226 | ); 227 | 228 | Mux16 MUX162( 229 | .a(outRAM), 230 | .b(tmp), 231 | .sel(address[13]), 232 | .out(out) 233 | ); 234 | ``` 235 | 236 | ### ROM 237 | 238 | ROM 和 RAM 差不多，不同的是加载了 led.hack 的二进制到 mem 中。然后根据 pc 返回 instruction ，由于开源的综合工具不能生成 block RAM ，所以这里只声明了 3 位 mem 以免使用过多 LUT 综合不了。 239 | 240 | ```verilog 241 | `default_nettype none 242 | 243 | module ROM( 244 | input wire [15:0] pc, 245 | output wire [15:0] instruction 246 | ); 247 | 248 | // ROM file of hack 249 | parameter ROMFILE = "./led.hack"; 250 | 251 | reg [15:0] mem [0:10]; 252 | assign instruction = mem[pc[3:0]]; 253 | 254 | initial begin 255 | $readmemb(ROMFILE,mem); 256 | end 257 | 258 | endmodule 259 | ``` 260 | 261 | ### 组装 262 | 263 | 最后把 CPU、Memory、ROM 组装起来。 264 | 265 | ```verilog 266 | wire [15:0] addressM; 267 | wire [15:0] outM; 268 | wire [15:0] instruction; 269 | wire [15:0] pc; 270 | wire [15:0] Mout; 271 | 272 | wire writeM; 273 | 274 | ROM ROM( 275 | .instruction(instruction), 276 | .pc(pc) 277 | ); 278 | CPU CPU( 279 | .clk(clk_out), 280 | .inM(Mout), 281 | .instruction(instruction), 282 | .reset(~reset), 283 | .outM(outM), 284 | .writeM(writeM), 285 | .addressM(addressM), 286 | .pc(pc) 287 | ); 288 | 289 | Memory MEMORY( 290 | .clk(clk_out), 291 | .address(addressM), 292 | .in(outM), 293 | .out(Mout), 294 | .load(writeM), 295 | .btn(btn), 296 | .led(led) 297 | ); 298 | ``` 299 | 300 | 1. ROM 根据 CPU 返回的 pc 产生指令 301 | 2. CPU 负责计算指令，通过 pc 指定下一条指令 302 | 3. CPU 如果要操作内存则把 address 提供给 Memory 303 | 304 | ### 降低频率 305 | 306 | 仿真正确，烧录到硬件上指令执行的太快了，需要降低频率。 307 | 308 | ```verilog 309 | `default_nettype none 310 | 311 | module Clk( 312 | input wire in, //external clock 100Mz 313 | output reg out = 1'b0 //Hack clock 33.333333 MHz 314 | ); 315 | 316 | // your implementation comes here: 317 | parameter NUM_DIV = 5; 318 | reg [15:0] cnt = 16'd0; 319 | // assign out <= 1'b0; 320 | 321 | always @(posedge in) 322 | if(cnt < NUM_DIV) begin 323 | cnt <= cnt + 1'b1; 324 | out <= out; 325 | end 326 | else begin 327 | cnt <= 16'd0; 328 | out <= ~out; 329 | end 330 | 331 | endmodule 332 | ``` 333 | 334 | 时钟频率降低 5 倍后，再烧录到硬件就可以了，最后看看我们完整的结果--可以执行任意汇编的计算机。 335 | 336 | [](https://youtube.com/shorts/UHfUUAZkFgE?feature=share) 337 | 338 | 339 | > 代码：https://github.com/buhe/bugu-computer/tree/master/04 340 | -------------------------------------------------------------------------------- /.vscode/targets.log: -------------------------------------------------------------------------------- 1 | make all --print-data-base --no-builtin-variables --no-builtin-rules --question 2 | # GNU Make 3.81 3 | # Copyright (C) 2006 Free Software Foundation, Inc. 4 | # This is free software; see the source for copying conditions. 5 | # There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A 6 | # PARTICULAR PURPOSE. 7 | 8 | # This program built for i386-apple-darwin11.3.0 9 | 10 | make: *** No rule to make target `all'. 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No Surrender of Others' Freedom. 541 | 542 | If conditions are imposed on you (whether by court order, agreement or 543 | otherwise) that contradict the conditions of this License, they do not 544 | excuse you from the conditions of this License. If you cannot convey a 545 | covered work so as to satisfy simultaneously your obligations under this 546 | License and any other pertinent obligations, then as a consequence you may 547 | not convey it at all. For example, if you agree to terms that obligate you 548 | to collect a royalty for further conveying from those to whom you convey 549 | the Program, the only way you could satisfy both those terms and this 550 | License would be to refrain entirely from conveying the Program. 551 | 552 | 13. Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . --------------------------------------------------------------------------------